stm32-fmt-code/access_control_stm32/Debug/access_control_stm32.list

access_control_stm32.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000198  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         00001e58  08000198  08000198  00010198  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00000020  08001ff0  08001ff0  00011ff0  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  08002010  08002010  0002000c  2**0
                  CONTENTS
  4 .ARM          00000008  08002010  08002010  00012010  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  08002018  08002018  0002000c  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08002018  08002018  00012018  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  0800201c  0800201c  0001201c  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         0000000c  20000000  08002020  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00000070  2000000c  0800202c  0002000c  2**2
                  ALLOC
 10 ._user_heap_stack 00000604  2000007c  0800202c  0002007c  2**0
                  ALLOC
 11 .ARM.attributes 00000030  00000000  00000000  0002000c  2**0
                  CONTENTS, READONLY
 12 .comment      00000043  00000000  00000000  0002003c  2**0
                  CONTENTS, READONLY
 13 .debug_info   000070ba  00000000  00000000  0002007f  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_abbrev 000012d1  00000000  00000000  00027139  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_aranges 00000608  00000000  00000000  00028410  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_rnglists 0000049c  00000000  00000000  00028a18  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_macro  0001483d  00000000  00000000  00028eb4  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_line   00007952  00000000  00000000  0003d6f1  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .debug_str    000818ec  00000000  00000000  00045043  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 20 .debug_frame  000017a4  00000000  00000000  000c6930  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 21 .debug_line_str 00000072  00000000  00000000  000c80d4  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

08000198 <__do_global_dtors_aux>:
 8000198:	b510      	push	{r4, lr}
 800019a:	4c05      	ldr	r4, [pc, #20]	; (80001b0 <__do_global_dtors_aux+0x18>)
 800019c:	7823      	ldrb	r3, [r4, #0]
 800019e:	b933      	cbnz	r3, 80001ae <__do_global_dtors_aux+0x16>
 80001a0:	4b04      	ldr	r3, [pc, #16]	; (80001b4 <__do_global_dtors_aux+0x1c>)
 80001a2:	b113      	cbz	r3, 80001aa <__do_global_dtors_aux+0x12>
 80001a4:	4804      	ldr	r0, [pc, #16]	; (80001b8 <__do_global_dtors_aux+0x20>)
 80001a6:	f3af 8000 	nop.w
 80001aa:	2301      	movs	r3, #1
 80001ac:	7023      	strb	r3, [r4, #0]
 80001ae:	bd10      	pop	{r4, pc}
 80001b0:	2000000c 	.word	0x2000000c
 80001b4:	00000000 	.word	0x00000000
 80001b8:	08001fd8 	.word	0x08001fd8

080001bc <frame_dummy>:
 80001bc:	b508      	push	{r3, lr}
 80001be:	4b03      	ldr	r3, [pc, #12]	; (80001cc <frame_dummy+0x10>)
 80001c0:	b11b      	cbz	r3, 80001ca <frame_dummy+0xe>
 80001c2:	4903      	ldr	r1, [pc, #12]	; (80001d0 <frame_dummy+0x14>)
 80001c4:	4803      	ldr	r0, [pc, #12]	; (80001d4 <frame_dummy+0x18>)
 80001c6:	f3af 8000 	nop.w
 80001ca:	bd08      	pop	{r3, pc}
 80001cc:	00000000 	.word	0x00000000
 80001d0:	20000010 	.word	0x20000010
 80001d4:	08001fd8 	.word	0x08001fd8

080001d8 <__aeabi_uldivmod>:
 80001d8:	b953      	cbnz	r3, 80001f0 <__aeabi_uldivmod+0x18>
 80001da:	b94a      	cbnz	r2, 80001f0 <__aeabi_uldivmod+0x18>
 80001dc:	2900      	cmp	r1, #0
 80001de:	bf08      	it	eq
 80001e0:	2800      	cmpeq	r0, #0
 80001e2:	bf1c      	itt	ne
 80001e4:	f04f 31ff 	movne.w	r1, #4294967295
 80001e8:	f04f 30ff 	movne.w	r0, #4294967295
 80001ec:	f000 b970 	b.w	80004d0 <__aeabi_idiv0>
 80001f0:	f1ad 0c08 	sub.w	ip, sp, #8
 80001f4:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 80001f8:	f000 f806 	bl	8000208 <__udivmoddi4>
 80001fc:	f8dd e004 	ldr.w	lr, [sp, #4]
 8000200:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 8000204:	b004      	add	sp, #16
 8000206:	4770      	bx	lr

08000208 <__udivmoddi4>:
 8000208:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 800020c:	9e08      	ldr	r6, [sp, #32]
 800020e:	460d      	mov	r5, r1
 8000210:	4604      	mov	r4, r0
 8000212:	460f      	mov	r7, r1
 8000214:	2b00      	cmp	r3, #0
 8000216:	d14a      	bne.n	80002ae <__udivmoddi4+0xa6>
 8000218:	428a      	cmp	r2, r1
 800021a:	4694      	mov	ip, r2
 800021c:	d965      	bls.n	80002ea <__udivmoddi4+0xe2>
 800021e:	fab2 f382 	clz	r3, r2
 8000222:	b143      	cbz	r3, 8000236 <__udivmoddi4+0x2e>
 8000224:	fa02 fc03 	lsl.w	ip, r2, r3
 8000228:	f1c3 0220 	rsb	r2, r3, #32
 800022c:	409f      	lsls	r7, r3
 800022e:	fa20 f202 	lsr.w	r2, r0, r2
 8000232:	4317      	orrs	r7, r2
 8000234:	409c      	lsls	r4, r3
 8000236:	ea4f 4e1c 	mov.w	lr, ip, lsr #16
 800023a:	fa1f f58c 	uxth.w	r5, ip
 800023e:	fbb7 f1fe 	udiv	r1, r7, lr
 8000242:	0c22      	lsrs	r2, r4, #16
 8000244:	fb0e 7711 	mls	r7, lr, r1, r7
 8000248:	ea42 4207 	orr.w	r2, r2, r7, lsl #16
 800024c:	fb01 f005 	mul.w	r0, r1, r5
 8000250:	4290      	cmp	r0, r2
 8000252:	d90a      	bls.n	800026a <__udivmoddi4+0x62>
 8000254:	eb1c 0202 	adds.w	r2, ip, r2
 8000258:	f101 37ff 	add.w	r7, r1, #4294967295
 800025c:	f080 811c 	bcs.w	8000498 <__udivmoddi4+0x290>
 8000260:	4290      	cmp	r0, r2
 8000262:	f240 8119 	bls.w	8000498 <__udivmoddi4+0x290>
 8000266:	3902      	subs	r1, #2
 8000268:	4462      	add	r2, ip
 800026a:	1a12      	subs	r2, r2, r0
 800026c:	b2a4      	uxth	r4, r4
 800026e:	fbb2 f0fe 	udiv	r0, r2, lr
 8000272:	fb0e 2210 	mls	r2, lr, r0, r2
 8000276:	ea44 4402 	orr.w	r4, r4, r2, lsl #16
 800027a:	fb00 f505 	mul.w	r5, r0, r5
 800027e:	42a5      	cmp	r5, r4
 8000280:	d90a      	bls.n	8000298 <__udivmoddi4+0x90>
 8000282:	eb1c 0404 	adds.w	r4, ip, r4
 8000286:	f100 32ff 	add.w	r2, r0, #4294967295
 800028a:	f080 8107 	bcs.w	800049c <__udivmoddi4+0x294>
 800028e:	42a5      	cmp	r5, r4
 8000290:	f240 8104 	bls.w	800049c <__udivmoddi4+0x294>
 8000294:	4464      	add	r4, ip
 8000296:	3802      	subs	r0, #2
 8000298:	ea40 4001 	orr.w	r0, r0, r1, lsl #16
 800029c:	1b64      	subs	r4, r4, r5
 800029e:	2100      	movs	r1, #0
 80002a0:	b11e      	cbz	r6, 80002aa <__udivmoddi4+0xa2>
 80002a2:	40dc      	lsrs	r4, r3
 80002a4:	2300      	movs	r3, #0
 80002a6:	e9c6 4300 	strd	r4, r3, [r6]
 80002aa:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002ae:	428b      	cmp	r3, r1
 80002b0:	d908      	bls.n	80002c4 <__udivmoddi4+0xbc>
 80002b2:	2e00      	cmp	r6, #0
 80002b4:	f000 80ed 	beq.w	8000492 <__udivmoddi4+0x28a>
 80002b8:	2100      	movs	r1, #0
 80002ba:	e9c6 0500 	strd	r0, r5, [r6]
 80002be:	4608      	mov	r0, r1
 80002c0:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002c4:	fab3 f183 	clz	r1, r3
 80002c8:	2900      	cmp	r1, #0
 80002ca:	d149      	bne.n	8000360 <__udivmoddi4+0x158>
 80002cc:	42ab      	cmp	r3, r5
 80002ce:	d302      	bcc.n	80002d6 <__udivmoddi4+0xce>
 80002d0:	4282      	cmp	r2, r0
 80002d2:	f200 80f8 	bhi.w	80004c6 <__udivmoddi4+0x2be>
 80002d6:	1a84      	subs	r4, r0, r2
 80002d8:	eb65 0203 	sbc.w	r2, r5, r3
 80002dc:	2001      	movs	r0, #1
 80002de:	4617      	mov	r7, r2
 80002e0:	2e00      	cmp	r6, #0
 80002e2:	d0e2      	beq.n	80002aa <__udivmoddi4+0xa2>
 80002e4:	e9c6 4700 	strd	r4, r7, [r6]
 80002e8:	e7df      	b.n	80002aa <__udivmoddi4+0xa2>
 80002ea:	b902      	cbnz	r2, 80002ee <__udivmoddi4+0xe6>
 80002ec:	deff      	udf	#255	; 0xff
 80002ee:	fab2 f382 	clz	r3, r2
 80002f2:	2b00      	cmp	r3, #0
 80002f4:	f040 8090 	bne.w	8000418 <__udivmoddi4+0x210>
 80002f8:	1a8a      	subs	r2, r1, r2
 80002fa:	ea4f 471c 	mov.w	r7, ip, lsr #16
 80002fe:	fa1f fe8c 	uxth.w	lr, ip
 8000302:	2101      	movs	r1, #1
 8000304:	fbb2 f5f7 	udiv	r5, r2, r7
 8000308:	fb07 2015 	mls	r0, r7, r5, r2
 800030c:	0c22      	lsrs	r2, r4, #16
 800030e:	ea42 4200 	orr.w	r2, r2, r0, lsl #16
 8000312:	fb0e f005 	mul.w	r0, lr, r5
 8000316:	4290      	cmp	r0, r2
 8000318:	d908      	bls.n	800032c <__udivmoddi4+0x124>
 800031a:	eb1c 0202 	adds.w	r2, ip, r2
 800031e:	f105 38ff 	add.w	r8, r5, #4294967295
 8000322:	d202      	bcs.n	800032a <__udivmoddi4+0x122>
 8000324:	4290      	cmp	r0, r2
 8000326:	f200 80cb 	bhi.w	80004c0 <__udivmoddi4+0x2b8>
 800032a:	4645      	mov	r5, r8
 800032c:	1a12      	subs	r2, r2, r0
 800032e:	b2a4      	uxth	r4, r4
 8000330:	fbb2 f0f7 	udiv	r0, r2, r7
 8000334:	fb07 2210 	mls	r2, r7, r0, r2
 8000338:	ea44 4402 	orr.w	r4, r4, r2, lsl #16
 800033c:	fb0e fe00 	mul.w	lr, lr, r0
 8000340:	45a6      	cmp	lr, r4
 8000342:	d908      	bls.n	8000356 <__udivmoddi4+0x14e>
 8000344:	eb1c 0404 	adds.w	r4, ip, r4
 8000348:	f100 32ff 	add.w	r2, r0, #4294967295
 800034c:	d202      	bcs.n	8000354 <__udivmoddi4+0x14c>
 800034e:	45a6      	cmp	lr, r4
 8000350:	f200 80bb 	bhi.w	80004ca <__udivmoddi4+0x2c2>
 8000354:	4610      	mov	r0, r2
 8000356:	eba4 040e 	sub.w	r4, r4, lr
 800035a:	ea40 4005 	orr.w	r0, r0, r5, lsl #16
 800035e:	e79f      	b.n	80002a0 <__udivmoddi4+0x98>
 8000360:	f1c1 0720 	rsb	r7, r1, #32
 8000364:	408b      	lsls	r3, r1
 8000366:	fa22 fc07 	lsr.w	ip, r2, r7
 800036a:	ea4c 0c03 	orr.w	ip, ip, r3
 800036e:	fa05 f401 	lsl.w	r4, r5, r1
 8000372:	fa20 f307 	lsr.w	r3, r0, r7
 8000376:	40fd      	lsrs	r5, r7
 8000378:	ea4f 491c 	mov.w	r9, ip, lsr #16
 800037c:	4323      	orrs	r3, r4
 800037e:	fbb5 f8f9 	udiv	r8, r5, r9
 8000382:	fa1f fe8c 	uxth.w	lr, ip
 8000386:	fb09 5518 	mls	r5, r9, r8, r5
 800038a:	0c1c      	lsrs	r4, r3, #16
 800038c:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
 8000390:	fb08 f50e 	mul.w	r5, r8, lr
 8000394:	42a5      	cmp	r5, r4
 8000396:	fa02 f201 	lsl.w	r2, r2, r1
 800039a:	fa00 f001 	lsl.w	r0, r0, r1
 800039e:	d90b      	bls.n	80003b8 <__udivmoddi4+0x1b0>
 80003a0:	eb1c 0404 	adds.w	r4, ip, r4
 80003a4:	f108 3aff 	add.w	sl, r8, #4294967295
 80003a8:	f080 8088 	bcs.w	80004bc <__udivmoddi4+0x2b4>
 80003ac:	42a5      	cmp	r5, r4
 80003ae:	f240 8085 	bls.w	80004bc <__udivmoddi4+0x2b4>
 80003b2:	f1a8 0802 	sub.w	r8, r8, #2
 80003b6:	4464      	add	r4, ip
 80003b8:	1b64      	subs	r4, r4, r5
 80003ba:	b29d      	uxth	r5, r3
 80003bc:	fbb4 f3f9 	udiv	r3, r4, r9
 80003c0:	fb09 4413 	mls	r4, r9, r3, r4
 80003c4:	ea45 4404 	orr.w	r4, r5, r4, lsl #16
 80003c8:	fb03 fe0e 	mul.w	lr, r3, lr
 80003cc:	45a6      	cmp	lr, r4
 80003ce:	d908      	bls.n	80003e2 <__udivmoddi4+0x1da>
 80003d0:	eb1c 0404 	adds.w	r4, ip, r4
 80003d4:	f103 35ff 	add.w	r5, r3, #4294967295
 80003d8:	d26c      	bcs.n	80004b4 <__udivmoddi4+0x2ac>
 80003da:	45a6      	cmp	lr, r4
 80003dc:	d96a      	bls.n	80004b4 <__udivmoddi4+0x2ac>
 80003de:	3b02      	subs	r3, #2
 80003e0:	4464      	add	r4, ip
 80003e2:	ea43 4308 	orr.w	r3, r3, r8, lsl #16
 80003e6:	fba3 9502 	umull	r9, r5, r3, r2
 80003ea:	eba4 040e 	sub.w	r4, r4, lr
 80003ee:	42ac      	cmp	r4, r5
 80003f0:	46c8      	mov	r8, r9
 80003f2:	46ae      	mov	lr, r5
 80003f4:	d356      	bcc.n	80004a4 <__udivmoddi4+0x29c>
 80003f6:	d053      	beq.n	80004a0 <__udivmoddi4+0x298>
 80003f8:	b156      	cbz	r6, 8000410 <__udivmoddi4+0x208>
 80003fa:	ebb0 0208 	subs.w	r2, r0, r8
 80003fe:	eb64 040e 	sbc.w	r4, r4, lr
 8000402:	fa04 f707 	lsl.w	r7, r4, r7
 8000406:	40ca      	lsrs	r2, r1
 8000408:	40cc      	lsrs	r4, r1
 800040a:	4317      	orrs	r7, r2
 800040c:	e9c6 7400 	strd	r7, r4, [r6]
 8000410:	4618      	mov	r0, r3
 8000412:	2100      	movs	r1, #0
 8000414:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000418:	f1c3 0120 	rsb	r1, r3, #32
 800041c:	fa02 fc03 	lsl.w	ip, r2, r3
 8000420:	fa20 f201 	lsr.w	r2, r0, r1
 8000424:	fa25 f101 	lsr.w	r1, r5, r1
 8000428:	409d      	lsls	r5, r3
 800042a:	432a      	orrs	r2, r5
 800042c:	ea4f 471c 	mov.w	r7, ip, lsr #16
 8000430:	fa1f fe8c 	uxth.w	lr, ip
 8000434:	fbb1 f0f7 	udiv	r0, r1, r7
 8000438:	fb07 1510 	mls	r5, r7, r0, r1
 800043c:	0c11      	lsrs	r1, r2, #16
 800043e:	ea41 4105 	orr.w	r1, r1, r5, lsl #16
 8000442:	fb00 f50e 	mul.w	r5, r0, lr
 8000446:	428d      	cmp	r5, r1
 8000448:	fa04 f403 	lsl.w	r4, r4, r3
 800044c:	d908      	bls.n	8000460 <__udivmoddi4+0x258>
 800044e:	eb1c 0101 	adds.w	r1, ip, r1
 8000452:	f100 38ff 	add.w	r8, r0, #4294967295
 8000456:	d22f      	bcs.n	80004b8 <__udivmoddi4+0x2b0>
 8000458:	428d      	cmp	r5, r1
 800045a:	d92d      	bls.n	80004b8 <__udivmoddi4+0x2b0>
 800045c:	3802      	subs	r0, #2
 800045e:	4461      	add	r1, ip
 8000460:	1b49      	subs	r1, r1, r5
 8000462:	b292      	uxth	r2, r2
 8000464:	fbb1 f5f7 	udiv	r5, r1, r7
 8000468:	fb07 1115 	mls	r1, r7, r5, r1
 800046c:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
 8000470:	fb05 f10e 	mul.w	r1, r5, lr
 8000474:	4291      	cmp	r1, r2
 8000476:	d908      	bls.n	800048a <__udivmoddi4+0x282>
 8000478:	eb1c 0202 	adds.w	r2, ip, r2
 800047c:	f105 38ff 	add.w	r8, r5, #4294967295
 8000480:	d216      	bcs.n	80004b0 <__udivmoddi4+0x2a8>
 8000482:	4291      	cmp	r1, r2
 8000484:	d914      	bls.n	80004b0 <__udivmoddi4+0x2a8>
 8000486:	3d02      	subs	r5, #2
 8000488:	4462      	add	r2, ip
 800048a:	1a52      	subs	r2, r2, r1
 800048c:	ea45 4100 	orr.w	r1, r5, r0, lsl #16
 8000490:	e738      	b.n	8000304 <__udivmoddi4+0xfc>
 8000492:	4631      	mov	r1, r6
 8000494:	4630      	mov	r0, r6
 8000496:	e708      	b.n	80002aa <__udivmoddi4+0xa2>
 8000498:	4639      	mov	r1, r7
 800049a:	e6e6      	b.n	800026a <__udivmoddi4+0x62>
 800049c:	4610      	mov	r0, r2
 800049e:	e6fb      	b.n	8000298 <__udivmoddi4+0x90>
 80004a0:	4548      	cmp	r0, r9
 80004a2:	d2a9      	bcs.n	80003f8 <__udivmoddi4+0x1f0>
 80004a4:	ebb9 0802 	subs.w	r8, r9, r2
 80004a8:	eb65 0e0c 	sbc.w	lr, r5, ip
 80004ac:	3b01      	subs	r3, #1
 80004ae:	e7a3      	b.n	80003f8 <__udivmoddi4+0x1f0>
 80004b0:	4645      	mov	r5, r8
 80004b2:	e7ea      	b.n	800048a <__udivmoddi4+0x282>
 80004b4:	462b      	mov	r3, r5
 80004b6:	e794      	b.n	80003e2 <__udivmoddi4+0x1da>
 80004b8:	4640      	mov	r0, r8
 80004ba:	e7d1      	b.n	8000460 <__udivmoddi4+0x258>
 80004bc:	46d0      	mov	r8, sl
 80004be:	e77b      	b.n	80003b8 <__udivmoddi4+0x1b0>
 80004c0:	3d02      	subs	r5, #2
 80004c2:	4462      	add	r2, ip
 80004c4:	e732      	b.n	800032c <__udivmoddi4+0x124>
 80004c6:	4608      	mov	r0, r1
 80004c8:	e70a      	b.n	80002e0 <__udivmoddi4+0xd8>
 80004ca:	4464      	add	r4, ip
 80004cc:	3802      	subs	r0, #2
 80004ce:	e742      	b.n	8000356 <__udivmoddi4+0x14e>

080004d0 <__aeabi_idiv0>:
 80004d0:	4770      	bx	lr
 80004d2:	bf00      	nop

080004d4 <main>:

/**
 * @brief  The application entry point.
 * @retval int
 */
int main(void) {
 80004d4:	b580      	push	{r7, lr}
 80004d6:	af00      	add	r7, sp, #0
	/* USER CODE END 1 */

	/* MCU Configuration--------------------------------------------------------*/

	/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
	HAL_Init();
 80004d8:	f000 fa02 	bl	80008e0 <HAL_Init>
	/* USER CODE BEGIN Init */

	/* USER CODE END Init */

	/* Configure the system clock */
	SystemClock_Config();
 80004dc:	f000 f816 	bl	800050c <SystemClock_Config>
	/* USER CODE BEGIN SysInit */

	/* USER CODE END SysInit */

	/* Initialize all configured peripherals */
	MX_GPIO_Init();
 80004e0:	f000 f8a8 	bl	8000634 <MX_GPIO_Init>
	MX_USART2_UART_Init();
 80004e4:	f000 f87c 	bl	80005e0 <MX_USART2_UART_Init>
	/* USER CODE BEGIN 2 */
	memset(uart_buffer, 0, 10);
 80004e8:	220a      	movs	r2, #10
 80004ea:	2100      	movs	r1, #0
 80004ec:	4804      	ldr	r0, [pc, #16]	; (8000500 <main+0x2c>)
 80004ee:	f001 fd47 	bl	8001f80 <memset>
//				}
//				uart_index = 0;
//				memset(uart_buffer, 0, 10);
//			}
//		}
		HAL_UART_Transmit(&huart2, (uint8_t*)"Hello", 5, 100);
 80004f2:	2364      	movs	r3, #100	; 0x64
 80004f4:	2205      	movs	r2, #5
 80004f6:	4903      	ldr	r1, [pc, #12]	; (8000504 <main+0x30>)
 80004f8:	4803      	ldr	r0, [pc, #12]	; (8000508 <main+0x34>)
 80004fa:	f001 f9cc 	bl	8001896 <HAL_UART_Transmit>
 80004fe:	e7f8      	b.n	80004f2 <main+0x1e>
 8000500:	2000006c 	.word	0x2000006c
 8000504:	08001ff0 	.word	0x08001ff0
 8000508:	20000028 	.word	0x20000028

0800050c <SystemClock_Config>:

/**
 * @brief System Clock Configuration
 * @retval None
 */
void SystemClock_Config(void) {
 800050c:	b580      	push	{r7, lr}
 800050e:	b094      	sub	sp, #80	; 0x50
 8000510:	af00      	add	r7, sp, #0
	RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
 8000512:	f107 0320 	add.w	r3, r7, #32
 8000516:	2230      	movs	r2, #48	; 0x30
 8000518:	2100      	movs	r1, #0
 800051a:	4618      	mov	r0, r3
 800051c:	f001 fd30 	bl	8001f80 <memset>
	RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
 8000520:	f107 030c 	add.w	r3, r7, #12
 8000524:	2200      	movs	r2, #0
 8000526:	601a      	str	r2, [r3, #0]
 8000528:	605a      	str	r2, [r3, #4]
 800052a:	609a      	str	r2, [r3, #8]
 800052c:	60da      	str	r2, [r3, #12]
 800052e:	611a      	str	r2, [r3, #16]

	/** Configure the main internal regulator output voltage
	 */
	__HAL_RCC_PWR_CLK_ENABLE();
 8000530:	2300      	movs	r3, #0
 8000532:	60bb      	str	r3, [r7, #8]
 8000534:	4b28      	ldr	r3, [pc, #160]	; (80005d8 <SystemClock_Config+0xcc>)
 8000536:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000538:	4a27      	ldr	r2, [pc, #156]	; (80005d8 <SystemClock_Config+0xcc>)
 800053a:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 800053e:	6413      	str	r3, [r2, #64]	; 0x40
 8000540:	4b25      	ldr	r3, [pc, #148]	; (80005d8 <SystemClock_Config+0xcc>)
 8000542:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000544:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000548:	60bb      	str	r3, [r7, #8]
 800054a:	68bb      	ldr	r3, [r7, #8]
	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 800054c:	2300      	movs	r3, #0
 800054e:	607b      	str	r3, [r7, #4]
 8000550:	4b22      	ldr	r3, [pc, #136]	; (80005dc <SystemClock_Config+0xd0>)
 8000552:	681b      	ldr	r3, [r3, #0]
 8000554:	4a21      	ldr	r2, [pc, #132]	; (80005dc <SystemClock_Config+0xd0>)
 8000556:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
 800055a:	6013      	str	r3, [r2, #0]
 800055c:	4b1f      	ldr	r3, [pc, #124]	; (80005dc <SystemClock_Config+0xd0>)
 800055e:	681b      	ldr	r3, [r3, #0]
 8000560:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
 8000564:	607b      	str	r3, [r7, #4]
 8000566:	687b      	ldr	r3, [r7, #4]

	/** Initializes the RCC Oscillators according to the specified parameters
	 * in the RCC_OscInitTypeDef structure.
	 */
	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8000568:	2302      	movs	r3, #2
 800056a:	623b      	str	r3, [r7, #32]
	RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 800056c:	2301      	movs	r3, #1
 800056e:	62fb      	str	r3, [r7, #44]	; 0x2c
	RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8000570:	2310      	movs	r3, #16
 8000572:	633b      	str	r3, [r7, #48]	; 0x30
	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8000574:	2302      	movs	r3, #2
 8000576:	63bb      	str	r3, [r7, #56]	; 0x38
	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 8000578:	2300      	movs	r3, #0
 800057a:	63fb      	str	r3, [r7, #60]	; 0x3c
	RCC_OscInitStruct.PLL.PLLM = 16;
 800057c:	2310      	movs	r3, #16
 800057e:	643b      	str	r3, [r7, #64]	; 0x40
	RCC_OscInitStruct.PLL.PLLN = 336;
 8000580:	f44f 73a8 	mov.w	r3, #336	; 0x150
 8000584:	647b      	str	r3, [r7, #68]	; 0x44
	RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
 8000586:	2304      	movs	r3, #4
 8000588:	64bb      	str	r3, [r7, #72]	; 0x48
	RCC_OscInitStruct.PLL.PLLQ = 4;
 800058a:	2304      	movs	r3, #4
 800058c:	64fb      	str	r3, [r7, #76]	; 0x4c
	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
 800058e:	f107 0320 	add.w	r3, r7, #32
 8000592:	4618      	mov	r0, r3
 8000594:	f000 fc9a 	bl	8000ecc <HAL_RCC_OscConfig>
 8000598:	4603      	mov	r3, r0
 800059a:	2b00      	cmp	r3, #0
 800059c:	d001      	beq.n	80005a2 <SystemClock_Config+0x96>
		Error_Handler();
 800059e:	f000 f8c3 	bl	8000728 <Error_Handler>
	}

	/** Initializes the CPU, AHB and APB buses clocks
	 */
	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
 80005a2:	230f      	movs	r3, #15
 80005a4:	60fb      	str	r3, [r7, #12]
			| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 80005a6:	2302      	movs	r3, #2
 80005a8:	613b      	str	r3, [r7, #16]
	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 80005aa:	2300      	movs	r3, #0
 80005ac:	617b      	str	r3, [r7, #20]
	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 80005ae:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 80005b2:	61bb      	str	r3, [r7, #24]
	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 80005b4:	2300      	movs	r3, #0
 80005b6:	61fb      	str	r3, [r7, #28]

	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
 80005b8:	f107 030c 	add.w	r3, r7, #12
 80005bc:	2102      	movs	r1, #2
 80005be:	4618      	mov	r0, r3
 80005c0:	f000 fefc 	bl	80013bc <HAL_RCC_ClockConfig>
 80005c4:	4603      	mov	r3, r0
 80005c6:	2b00      	cmp	r3, #0
 80005c8:	d001      	beq.n	80005ce <SystemClock_Config+0xc2>
		Error_Handler();
 80005ca:	f000 f8ad 	bl	8000728 <Error_Handler>
	}
}
 80005ce:	bf00      	nop
 80005d0:	3750      	adds	r7, #80	; 0x50
 80005d2:	46bd      	mov	sp, r7
 80005d4:	bd80      	pop	{r7, pc}
 80005d6:	bf00      	nop
 80005d8:	40023800 	.word	0x40023800
 80005dc:	40007000 	.word	0x40007000

080005e0 <MX_USART2_UART_Init>:
/**
 * @brief USART2 Initialization Function
 * @param None
 * @retval None
 */
static void MX_USART2_UART_Init(void) {
 80005e0:	b580      	push	{r7, lr}
 80005e2:	af00      	add	r7, sp, #0
	/* USER CODE END USART2_Init 0 */

	/* USER CODE BEGIN USART2_Init 1 */

	/* USER CODE END USART2_Init 1 */
	huart2.Instance = USART2;
 80005e4:	4b11      	ldr	r3, [pc, #68]	; (800062c <MX_USART2_UART_Init+0x4c>)
 80005e6:	4a12      	ldr	r2, [pc, #72]	; (8000630 <MX_USART2_UART_Init+0x50>)
 80005e8:	601a      	str	r2, [r3, #0]
	huart2.Init.BaudRate = 115200;
 80005ea:	4b10      	ldr	r3, [pc, #64]	; (800062c <MX_USART2_UART_Init+0x4c>)
 80005ec:	f44f 32e1 	mov.w	r2, #115200	; 0x1c200
 80005f0:	605a      	str	r2, [r3, #4]
	huart2.Init.WordLength = UART_WORDLENGTH_8B;
 80005f2:	4b0e      	ldr	r3, [pc, #56]	; (800062c <MX_USART2_UART_Init+0x4c>)
 80005f4:	2200      	movs	r2, #0
 80005f6:	609a      	str	r2, [r3, #8]
	huart2.Init.StopBits = UART_STOPBITS_1;
 80005f8:	4b0c      	ldr	r3, [pc, #48]	; (800062c <MX_USART2_UART_Init+0x4c>)
 80005fa:	2200      	movs	r2, #0
 80005fc:	60da      	str	r2, [r3, #12]
	huart2.Init.Parity = UART_PARITY_NONE;
 80005fe:	4b0b      	ldr	r3, [pc, #44]	; (800062c <MX_USART2_UART_Init+0x4c>)
 8000600:	2200      	movs	r2, #0
 8000602:	611a      	str	r2, [r3, #16]
	huart2.Init.Mode = UART_MODE_TX_RX;
 8000604:	4b09      	ldr	r3, [pc, #36]	; (800062c <MX_USART2_UART_Init+0x4c>)
 8000606:	220c      	movs	r2, #12
 8000608:	615a      	str	r2, [r3, #20]
	huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 800060a:	4b08      	ldr	r3, [pc, #32]	; (800062c <MX_USART2_UART_Init+0x4c>)
 800060c:	2200      	movs	r2, #0
 800060e:	619a      	str	r2, [r3, #24]
	huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 8000610:	4b06      	ldr	r3, [pc, #24]	; (800062c <MX_USART2_UART_Init+0x4c>)
 8000612:	2200      	movs	r2, #0
 8000614:	61da      	str	r2, [r3, #28]
	if (HAL_UART_Init(&huart2) != HAL_OK) {
 8000616:	4805      	ldr	r0, [pc, #20]	; (800062c <MX_USART2_UART_Init+0x4c>)
 8000618:	f001 f8f0 	bl	80017fc <HAL_UART_Init>
 800061c:	4603      	mov	r3, r0
 800061e:	2b00      	cmp	r3, #0
 8000620:	d001      	beq.n	8000626 <MX_USART2_UART_Init+0x46>
		Error_Handler();
 8000622:	f000 f881 	bl	8000728 <Error_Handler>
	}
	/* USER CODE BEGIN USART2_Init 2 */

	/* USER CODE END USART2_Init 2 */

}
 8000626:	bf00      	nop
 8000628:	bd80      	pop	{r7, pc}
 800062a:	bf00      	nop
 800062c:	20000028 	.word	0x20000028
 8000630:	40004400 	.word	0x40004400

08000634 <MX_GPIO_Init>:
/**
 * @brief GPIO Initialization Function
 * @param None
 * @retval None
 */
static void MX_GPIO_Init(void) {
 8000634:	b580      	push	{r7, lr}
 8000636:	b08a      	sub	sp, #40	; 0x28
 8000638:	af00      	add	r7, sp, #0
	GPIO_InitTypeDef GPIO_InitStruct = { 0 };
 800063a:	f107 0314 	add.w	r3, r7, #20
 800063e:	2200      	movs	r2, #0
 8000640:	601a      	str	r2, [r3, #0]
 8000642:	605a      	str	r2, [r3, #4]
 8000644:	609a      	str	r2, [r3, #8]
 8000646:	60da      	str	r2, [r3, #12]
 8000648:	611a      	str	r2, [r3, #16]
	/* USER CODE BEGIN MX_GPIO_Init_1 */
	/* USER CODE END MX_GPIO_Init_1 */

	/* GPIO Ports Clock Enable */
	__HAL_RCC_GPIOC_CLK_ENABLE();
 800064a:	2300      	movs	r3, #0
 800064c:	613b      	str	r3, [r7, #16]
 800064e:	4b33      	ldr	r3, [pc, #204]	; (800071c <MX_GPIO_Init+0xe8>)
 8000650:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000652:	4a32      	ldr	r2, [pc, #200]	; (800071c <MX_GPIO_Init+0xe8>)
 8000654:	f043 0304 	orr.w	r3, r3, #4
 8000658:	6313      	str	r3, [r2, #48]	; 0x30
 800065a:	4b30      	ldr	r3, [pc, #192]	; (800071c <MX_GPIO_Init+0xe8>)
 800065c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 800065e:	f003 0304 	and.w	r3, r3, #4
 8000662:	613b      	str	r3, [r7, #16]
 8000664:	693b      	ldr	r3, [r7, #16]
	__HAL_RCC_GPIOH_CLK_ENABLE();
 8000666:	2300      	movs	r3, #0
 8000668:	60fb      	str	r3, [r7, #12]
 800066a:	4b2c      	ldr	r3, [pc, #176]	; (800071c <MX_GPIO_Init+0xe8>)
 800066c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 800066e:	4a2b      	ldr	r2, [pc, #172]	; (800071c <MX_GPIO_Init+0xe8>)
 8000670:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 8000674:	6313      	str	r3, [r2, #48]	; 0x30
 8000676:	4b29      	ldr	r3, [pc, #164]	; (800071c <MX_GPIO_Init+0xe8>)
 8000678:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 800067a:	f003 0380 	and.w	r3, r3, #128	; 0x80
 800067e:	60fb      	str	r3, [r7, #12]
 8000680:	68fb      	ldr	r3, [r7, #12]
	__HAL_RCC_GPIOA_CLK_ENABLE();
 8000682:	2300      	movs	r3, #0
 8000684:	60bb      	str	r3, [r7, #8]
 8000686:	4b25      	ldr	r3, [pc, #148]	; (800071c <MX_GPIO_Init+0xe8>)
 8000688:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 800068a:	4a24      	ldr	r2, [pc, #144]	; (800071c <MX_GPIO_Init+0xe8>)
 800068c:	f043 0301 	orr.w	r3, r3, #1
 8000690:	6313      	str	r3, [r2, #48]	; 0x30
 8000692:	4b22      	ldr	r3, [pc, #136]	; (800071c <MX_GPIO_Init+0xe8>)
 8000694:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000696:	f003 0301 	and.w	r3, r3, #1
 800069a:	60bb      	str	r3, [r7, #8]
 800069c:	68bb      	ldr	r3, [r7, #8]
	__HAL_RCC_GPIOB_CLK_ENABLE();
 800069e:	2300      	movs	r3, #0
 80006a0:	607b      	str	r3, [r7, #4]
 80006a2:	4b1e      	ldr	r3, [pc, #120]	; (800071c <MX_GPIO_Init+0xe8>)
 80006a4:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80006a6:	4a1d      	ldr	r2, [pc, #116]	; (800071c <MX_GPIO_Init+0xe8>)
 80006a8:	f043 0302 	orr.w	r3, r3, #2
 80006ac:	6313      	str	r3, [r2, #48]	; 0x30
 80006ae:	4b1b      	ldr	r3, [pc, #108]	; (800071c <MX_GPIO_Init+0xe8>)
 80006b0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80006b2:	f003 0302 	and.w	r3, r3, #2
 80006b6:	607b      	str	r3, [r7, #4]
 80006b8:	687b      	ldr	r3, [r7, #4]

	/*Configure GPIO pin Output Level */
	HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
 80006ba:	2200      	movs	r2, #0
 80006bc:	2120      	movs	r1, #32
 80006be:	4818      	ldr	r0, [pc, #96]	; (8000720 <MX_GPIO_Init+0xec>)
 80006c0:	f000 fbea 	bl	8000e98 <HAL_GPIO_WritePin>

	/*Configure GPIO pin : B1_Pin */
	GPIO_InitStruct.Pin = B1_Pin;
 80006c4:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 80006c8:	617b      	str	r3, [r7, #20]
	GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
 80006ca:	f44f 1304 	mov.w	r3, #2162688	; 0x210000
 80006ce:	61bb      	str	r3, [r7, #24]
	GPIO_InitStruct.Pull = GPIO_NOPULL;
 80006d0:	2300      	movs	r3, #0
 80006d2:	61fb      	str	r3, [r7, #28]
	HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
 80006d4:	f107 0314 	add.w	r3, r7, #20
 80006d8:	4619      	mov	r1, r3
 80006da:	4812      	ldr	r0, [pc, #72]	; (8000724 <MX_GPIO_Init+0xf0>)
 80006dc:	f000 fa58 	bl	8000b90 <HAL_GPIO_Init>

	/*Configure GPIO pin : LD2_Pin */
	GPIO_InitStruct.Pin = LD2_Pin;
 80006e0:	2320      	movs	r3, #32
 80006e2:	617b      	str	r3, [r7, #20]
	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 80006e4:	2301      	movs	r3, #1
 80006e6:	61bb      	str	r3, [r7, #24]
	GPIO_InitStruct.Pull = GPIO_NOPULL;
 80006e8:	2300      	movs	r3, #0
 80006ea:	61fb      	str	r3, [r7, #28]
	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 80006ec:	2300      	movs	r3, #0
 80006ee:	623b      	str	r3, [r7, #32]
	HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
 80006f0:	f107 0314 	add.w	r3, r7, #20
 80006f4:	4619      	mov	r1, r3
 80006f6:	480a      	ldr	r0, [pc, #40]	; (8000720 <MX_GPIO_Init+0xec>)
 80006f8:	f000 fa4a 	bl	8000b90 <HAL_GPIO_Init>

	/*Configure GPIO pin : Door_Sensor_Pin */
	GPIO_InitStruct.Pin = Door_Sensor_Pin;
 80006fc:	2380      	movs	r3, #128	; 0x80
 80006fe:	617b      	str	r3, [r7, #20]
	GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 8000700:	2300      	movs	r3, #0
 8000702:	61bb      	str	r3, [r7, #24]
	GPIO_InitStruct.Pull = GPIO_PULLUP;
 8000704:	2301      	movs	r3, #1
 8000706:	61fb      	str	r3, [r7, #28]
	HAL_GPIO_Init(Door_Sensor_GPIO_Port, &GPIO_InitStruct);
 8000708:	f107 0314 	add.w	r3, r7, #20
 800070c:	4619      	mov	r1, r3
 800070e:	4804      	ldr	r0, [pc, #16]	; (8000720 <MX_GPIO_Init+0xec>)
 8000710:	f000 fa3e 	bl	8000b90 <HAL_GPIO_Init>

	/* USER CODE BEGIN MX_GPIO_Init_2 */
	/* USER CODE END MX_GPIO_Init_2 */
}
 8000714:	bf00      	nop
 8000716:	3728      	adds	r7, #40	; 0x28
 8000718:	46bd      	mov	sp, r7
 800071a:	bd80      	pop	{r7, pc}
 800071c:	40023800 	.word	0x40023800
 8000720:	40020000 	.word	0x40020000
 8000724:	40020800 	.word	0x40020800

08000728 <Error_Handler>:

/**
 * @brief  This function is executed in case of error occurrence.
 * @retval None
 */
void Error_Handler(void) {
 8000728:	b480      	push	{r7}
 800072a:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 800072c:	b672      	cpsid	i
}
 800072e:	bf00      	nop
	/* USER CODE BEGIN Error_Handler_Debug */
	/* User can add his own implementation to report the HAL error return state */
	__disable_irq();
	while (1) {
 8000730:	e7fe      	b.n	8000730 <Error_Handler+0x8>
	...

08000734 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8000734:	b580      	push	{r7, lr}
 8000736:	b082      	sub	sp, #8
 8000738:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 800073a:	2300      	movs	r3, #0
 800073c:	607b      	str	r3, [r7, #4]
 800073e:	4b10      	ldr	r3, [pc, #64]	; (8000780 <HAL_MspInit+0x4c>)
 8000740:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000742:	4a0f      	ldr	r2, [pc, #60]	; (8000780 <HAL_MspInit+0x4c>)
 8000744:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 8000748:	6453      	str	r3, [r2, #68]	; 0x44
 800074a:	4b0d      	ldr	r3, [pc, #52]	; (8000780 <HAL_MspInit+0x4c>)
 800074c:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 800074e:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 8000752:	607b      	str	r3, [r7, #4]
 8000754:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 8000756:	2300      	movs	r3, #0
 8000758:	603b      	str	r3, [r7, #0]
 800075a:	4b09      	ldr	r3, [pc, #36]	; (8000780 <HAL_MspInit+0x4c>)
 800075c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800075e:	4a08      	ldr	r2, [pc, #32]	; (8000780 <HAL_MspInit+0x4c>)
 8000760:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8000764:	6413      	str	r3, [r2, #64]	; 0x40
 8000766:	4b06      	ldr	r3, [pc, #24]	; (8000780 <HAL_MspInit+0x4c>)
 8000768:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800076a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800076e:	603b      	str	r3, [r7, #0]
 8000770:	683b      	ldr	r3, [r7, #0]

  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
 8000772:	2007      	movs	r0, #7
 8000774:	f000 f9d8 	bl	8000b28 <HAL_NVIC_SetPriorityGrouping>
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8000778:	bf00      	nop
 800077a:	3708      	adds	r7, #8
 800077c:	46bd      	mov	sp, r7
 800077e:	bd80      	pop	{r7, pc}
 8000780:	40023800 	.word	0x40023800

08000784 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8000784:	b580      	push	{r7, lr}
 8000786:	b08a      	sub	sp, #40	; 0x28
 8000788:	af00      	add	r7, sp, #0
 800078a:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800078c:	f107 0314 	add.w	r3, r7, #20
 8000790:	2200      	movs	r2, #0
 8000792:	601a      	str	r2, [r3, #0]
 8000794:	605a      	str	r2, [r3, #4]
 8000796:	609a      	str	r2, [r3, #8]
 8000798:	60da      	str	r2, [r3, #12]
 800079a:	611a      	str	r2, [r3, #16]
  if(huart->Instance==USART2)
 800079c:	687b      	ldr	r3, [r7, #4]
 800079e:	681b      	ldr	r3, [r3, #0]
 80007a0:	4a19      	ldr	r2, [pc, #100]	; (8000808 <HAL_UART_MspInit+0x84>)
 80007a2:	4293      	cmp	r3, r2
 80007a4:	d12b      	bne.n	80007fe <HAL_UART_MspInit+0x7a>
  {
  /* USER CODE BEGIN USART2_MspInit 0 */

  /* USER CODE END USART2_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART2_CLK_ENABLE();
 80007a6:	2300      	movs	r3, #0
 80007a8:	613b      	str	r3, [r7, #16]
 80007aa:	4b18      	ldr	r3, [pc, #96]	; (800080c <HAL_UART_MspInit+0x88>)
 80007ac:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80007ae:	4a17      	ldr	r2, [pc, #92]	; (800080c <HAL_UART_MspInit+0x88>)
 80007b0:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 80007b4:	6413      	str	r3, [r2, #64]	; 0x40
 80007b6:	4b15      	ldr	r3, [pc, #84]	; (800080c <HAL_UART_MspInit+0x88>)
 80007b8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80007ba:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80007be:	613b      	str	r3, [r7, #16]
 80007c0:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 80007c2:	2300      	movs	r3, #0
 80007c4:	60fb      	str	r3, [r7, #12]
 80007c6:	4b11      	ldr	r3, [pc, #68]	; (800080c <HAL_UART_MspInit+0x88>)
 80007c8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80007ca:	4a10      	ldr	r2, [pc, #64]	; (800080c <HAL_UART_MspInit+0x88>)
 80007cc:	f043 0301 	orr.w	r3, r3, #1
 80007d0:	6313      	str	r3, [r2, #48]	; 0x30
 80007d2:	4b0e      	ldr	r3, [pc, #56]	; (800080c <HAL_UART_MspInit+0x88>)
 80007d4:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80007d6:	f003 0301 	and.w	r3, r3, #1
 80007da:	60fb      	str	r3, [r7, #12]
 80007dc:	68fb      	ldr	r3, [r7, #12]
    /**USART2 GPIO Configuration
    PA2     ------> USART2_TX
    PA3     ------> USART2_RX
    */
    GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
 80007de:	230c      	movs	r3, #12
 80007e0:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 80007e2:	2302      	movs	r3, #2
 80007e4:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 80007e6:	2300      	movs	r3, #0
 80007e8:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 80007ea:	2303      	movs	r3, #3
 80007ec:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
 80007ee:	2307      	movs	r3, #7
 80007f0:	627b      	str	r3, [r7, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 80007f2:	f107 0314 	add.w	r3, r7, #20
 80007f6:	4619      	mov	r1, r3
 80007f8:	4805      	ldr	r0, [pc, #20]	; (8000810 <HAL_UART_MspInit+0x8c>)
 80007fa:	f000 f9c9 	bl	8000b90 <HAL_GPIO_Init>
  /* USER CODE BEGIN USART2_MspInit 1 */

  /* USER CODE END USART2_MspInit 1 */
  }

}
 80007fe:	bf00      	nop
 8000800:	3728      	adds	r7, #40	; 0x28
 8000802:	46bd      	mov	sp, r7
 8000804:	bd80      	pop	{r7, pc}
 8000806:	bf00      	nop
 8000808:	40004400 	.word	0x40004400
 800080c:	40023800 	.word	0x40023800
 8000810:	40020000 	.word	0x40020000

08000814 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 8000814:	b480      	push	{r7}
 8000816:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 8000818:	e7fe      	b.n	8000818 <NMI_Handler+0x4>

0800081a <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 800081a:	b480      	push	{r7}
 800081c:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 800081e:	e7fe      	b.n	800081e <HardFault_Handler+0x4>

08000820 <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8000820:	b480      	push	{r7}
 8000822:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8000824:	e7fe      	b.n	8000824 <MemManage_Handler+0x4>

08000826 <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8000826:	b480      	push	{r7}
 8000828:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 800082a:	e7fe      	b.n	800082a <BusFault_Handler+0x4>

0800082c <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 800082c:	b480      	push	{r7}
 800082e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8000830:	e7fe      	b.n	8000830 <UsageFault_Handler+0x4>

08000832 <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 8000832:	b480      	push	{r7}
 8000834:	af00      	add	r7, sp, #0

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 8000836:	bf00      	nop
 8000838:	46bd      	mov	sp, r7
 800083a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800083e:	4770      	bx	lr

08000840 <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8000840:	b480      	push	{r7}
 8000842:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8000844:	bf00      	nop
 8000846:	46bd      	mov	sp, r7
 8000848:	f85d 7b04 	ldr.w	r7, [sp], #4
 800084c:	4770      	bx	lr

0800084e <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 800084e:	b480      	push	{r7}
 8000850:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8000852:	bf00      	nop
 8000854:	46bd      	mov	sp, r7
 8000856:	f85d 7b04 	ldr.w	r7, [sp], #4
 800085a:	4770      	bx	lr

0800085c <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 800085c:	b580      	push	{r7, lr}
 800085e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8000860:	f000 f890 	bl	8000984 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 8000864:	bf00      	nop
 8000866:	bd80      	pop	{r7, pc}

08000868 <SystemInit>:
  *         configuration.
  * @param  None
  * @retval None
  */
void SystemInit(void)
{
 8000868:	b480      	push	{r7}
 800086a:	af00      	add	r7, sp, #0
  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 800086c:	4b06      	ldr	r3, [pc, #24]	; (8000888 <SystemInit+0x20>)
 800086e:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8000872:	4a05      	ldr	r2, [pc, #20]	; (8000888 <SystemInit+0x20>)
 8000874:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
 8000878:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88

  /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
 800087c:	bf00      	nop
 800087e:	46bd      	mov	sp, r7
 8000880:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000884:	4770      	bx	lr
 8000886:	bf00      	nop
 8000888:	e000ed00 	.word	0xe000ed00

0800088c <Reset_Handler>:

    .section  .text.Reset_Handler
  .weak  Reset_Handler
  .type  Reset_Handler, %function
Reset_Handler:  
  ldr   sp, =_estack    		 /* set stack pointer */
 800088c:	f8df d034 	ldr.w	sp, [pc, #52]	; 80008c4 <LoopFillZerobss+0x12>

/* Copy the data segment initializers from flash to SRAM */  
  ldr r0, =_sdata
 8000890:	480d      	ldr	r0, [pc, #52]	; (80008c8 <LoopFillZerobss+0x16>)
  ldr r1, =_edata
 8000892:	490e      	ldr	r1, [pc, #56]	; (80008cc <LoopFillZerobss+0x1a>)
  ldr r2, =_sidata
 8000894:	4a0e      	ldr	r2, [pc, #56]	; (80008d0 <LoopFillZerobss+0x1e>)
  movs r3, #0
 8000896:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8000898:	e002      	b.n	80008a0 <LoopCopyDataInit>

0800089a <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 800089a:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 800089c:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 800089e:	3304      	adds	r3, #4

080008a0 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 80008a0:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 80008a2:	428c      	cmp	r4, r1
  bcc CopyDataInit
 80008a4:	d3f9      	bcc.n	800089a <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 80008a6:	4a0b      	ldr	r2, [pc, #44]	; (80008d4 <LoopFillZerobss+0x22>)
  ldr r4, =_ebss
 80008a8:	4c0b      	ldr	r4, [pc, #44]	; (80008d8 <LoopFillZerobss+0x26>)
  movs r3, #0
 80008aa:	2300      	movs	r3, #0
  b LoopFillZerobss
 80008ac:	e001      	b.n	80008b2 <LoopFillZerobss>

080008ae <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 80008ae:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 80008b0:	3204      	adds	r2, #4

080008b2 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 80008b2:	42a2      	cmp	r2, r4
  bcc FillZerobss
 80008b4:	d3fb      	bcc.n	80008ae <FillZerobss>

/* Call the clock system initialization function.*/
  bl  SystemInit   
 80008b6:	f7ff ffd7 	bl	8000868 <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 80008ba:	f001 fb69 	bl	8001f90 <__libc_init_array>
/* Call the application's entry point.*/
  bl  main
 80008be:	f7ff fe09 	bl	80004d4 <main>
  bx  lr    
 80008c2:	4770      	bx	lr
  ldr   sp, =_estack    		 /* set stack pointer */
 80008c4:	20020000 	.word	0x20020000
  ldr r0, =_sdata
 80008c8:	20000000 	.word	0x20000000
  ldr r1, =_edata
 80008cc:	2000000c 	.word	0x2000000c
  ldr r2, =_sidata
 80008d0:	08002020 	.word	0x08002020
  ldr r2, =_sbss
 80008d4:	2000000c 	.word	0x2000000c
  ldr r4, =_ebss
 80008d8:	2000007c 	.word	0x2000007c

080008dc <ADC_IRQHandler>:
 * @retval None       
*/
    .section  .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b  Infinite_Loop
 80008dc:	e7fe      	b.n	80008dc <ADC_IRQHandler>
	...

080008e0 <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 80008e0:	b580      	push	{r7, lr}
 80008e2:	af00      	add	r7, sp, #0
  /* Configure Flash prefetch, Instruction cache, Data cache */ 
#if (INSTRUCTION_CACHE_ENABLE != 0U)
  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 80008e4:	4b0e      	ldr	r3, [pc, #56]	; (8000920 <HAL_Init+0x40>)
 80008e6:	681b      	ldr	r3, [r3, #0]
 80008e8:	4a0d      	ldr	r2, [pc, #52]	; (8000920 <HAL_Init+0x40>)
 80008ea:	f443 7300 	orr.w	r3, r3, #512	; 0x200
 80008ee:	6013      	str	r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */

#if (DATA_CACHE_ENABLE != 0U)
  __HAL_FLASH_DATA_CACHE_ENABLE();
 80008f0:	4b0b      	ldr	r3, [pc, #44]	; (8000920 <HAL_Init+0x40>)
 80008f2:	681b      	ldr	r3, [r3, #0]
 80008f4:	4a0a      	ldr	r2, [pc, #40]	; (8000920 <HAL_Init+0x40>)
 80008f6:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
 80008fa:	6013      	str	r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */

#if (PREFETCH_ENABLE != 0U)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 80008fc:	4b08      	ldr	r3, [pc, #32]	; (8000920 <HAL_Init+0x40>)
 80008fe:	681b      	ldr	r3, [r3, #0]
 8000900:	4a07      	ldr	r2, [pc, #28]	; (8000920 <HAL_Init+0x40>)
 8000902:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8000906:	6013      	str	r3, [r2, #0]
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8000908:	2003      	movs	r0, #3
 800090a:	f000 f90d 	bl	8000b28 <HAL_NVIC_SetPriorityGrouping>

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  HAL_InitTick(TICK_INT_PRIORITY);
 800090e:	2000      	movs	r0, #0
 8000910:	f000 f808 	bl	8000924 <HAL_InitTick>

  /* Init the low level hardware */
  HAL_MspInit();
 8000914:	f7ff ff0e 	bl	8000734 <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 8000918:	2300      	movs	r3, #0
}
 800091a:	4618      	mov	r0, r3
 800091c:	bd80      	pop	{r7, pc}
 800091e:	bf00      	nop
 8000920:	40023c00 	.word	0x40023c00

08000924 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8000924:	b580      	push	{r7, lr}
 8000926:	b082      	sub	sp, #8
 8000928:	af00      	add	r7, sp, #0
 800092a:	6078      	str	r0, [r7, #4]
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 800092c:	4b12      	ldr	r3, [pc, #72]	; (8000978 <HAL_InitTick+0x54>)
 800092e:	681a      	ldr	r2, [r3, #0]
 8000930:	4b12      	ldr	r3, [pc, #72]	; (800097c <HAL_InitTick+0x58>)
 8000932:	781b      	ldrb	r3, [r3, #0]
 8000934:	4619      	mov	r1, r3
 8000936:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 800093a:	fbb3 f3f1 	udiv	r3, r3, r1
 800093e:	fbb2 f3f3 	udiv	r3, r2, r3
 8000942:	4618      	mov	r0, r3
 8000944:	f000 f917 	bl	8000b76 <HAL_SYSTICK_Config>
 8000948:	4603      	mov	r3, r0
 800094a:	2b00      	cmp	r3, #0
 800094c:	d001      	beq.n	8000952 <HAL_InitTick+0x2e>
  {
    return HAL_ERROR;
 800094e:	2301      	movs	r3, #1
 8000950:	e00e      	b.n	8000970 <HAL_InitTick+0x4c>
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8000952:	687b      	ldr	r3, [r7, #4]
 8000954:	2b0f      	cmp	r3, #15
 8000956:	d80a      	bhi.n	800096e <HAL_InitTick+0x4a>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8000958:	2200      	movs	r2, #0
 800095a:	6879      	ldr	r1, [r7, #4]
 800095c:	f04f 30ff 	mov.w	r0, #4294967295
 8000960:	f000 f8ed 	bl	8000b3e <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8000964:	4a06      	ldr	r2, [pc, #24]	; (8000980 <HAL_InitTick+0x5c>)
 8000966:	687b      	ldr	r3, [r7, #4]
 8000968:	6013      	str	r3, [r2, #0]
  {
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
 800096a:	2300      	movs	r3, #0
 800096c:	e000      	b.n	8000970 <HAL_InitTick+0x4c>
    return HAL_ERROR;
 800096e:	2301      	movs	r3, #1
}
 8000970:	4618      	mov	r0, r3
 8000972:	3708      	adds	r7, #8
 8000974:	46bd      	mov	sp, r7
 8000976:	bd80      	pop	{r7, pc}
 8000978:	20000000 	.word	0x20000000
 800097c:	20000008 	.word	0x20000008
 8000980:	20000004 	.word	0x20000004

08000984 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other 
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8000984:	b480      	push	{r7}
 8000986:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 8000988:	4b06      	ldr	r3, [pc, #24]	; (80009a4 <HAL_IncTick+0x20>)
 800098a:	781b      	ldrb	r3, [r3, #0]
 800098c:	461a      	mov	r2, r3
 800098e:	4b06      	ldr	r3, [pc, #24]	; (80009a8 <HAL_IncTick+0x24>)
 8000990:	681b      	ldr	r3, [r3, #0]
 8000992:	4413      	add	r3, r2
 8000994:	4a04      	ldr	r2, [pc, #16]	; (80009a8 <HAL_IncTick+0x24>)
 8000996:	6013      	str	r3, [r2, #0]
}
 8000998:	bf00      	nop
 800099a:	46bd      	mov	sp, r7
 800099c:	f85d 7b04 	ldr.w	r7, [sp], #4
 80009a0:	4770      	bx	lr
 80009a2:	bf00      	nop
 80009a4:	20000008 	.word	0x20000008
 80009a8:	20000078 	.word	0x20000078

080009ac <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other 
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 80009ac:	b480      	push	{r7}
 80009ae:	af00      	add	r7, sp, #0
  return uwTick;
 80009b0:	4b03      	ldr	r3, [pc, #12]	; (80009c0 <HAL_GetTick+0x14>)
 80009b2:	681b      	ldr	r3, [r3, #0]
}
 80009b4:	4618      	mov	r0, r3
 80009b6:	46bd      	mov	sp, r7
 80009b8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80009bc:	4770      	bx	lr
 80009be:	bf00      	nop
 80009c0:	20000078 	.word	0x20000078

080009c4 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80009c4:	b480      	push	{r7}
 80009c6:	b085      	sub	sp, #20
 80009c8:	af00      	add	r7, sp, #0
 80009ca:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 80009cc:	687b      	ldr	r3, [r7, #4]
 80009ce:	f003 0307 	and.w	r3, r3, #7
 80009d2:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 80009d4:	4b0c      	ldr	r3, [pc, #48]	; (8000a08 <__NVIC_SetPriorityGrouping+0x44>)
 80009d6:	68db      	ldr	r3, [r3, #12]
 80009d8:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 80009da:	68ba      	ldr	r2, [r7, #8]
 80009dc:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
 80009e0:	4013      	ands	r3, r2
 80009e2:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 80009e4:	68fb      	ldr	r3, [r7, #12]
 80009e6:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 80009e8:	68bb      	ldr	r3, [r7, #8]
 80009ea:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 80009ec:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 80009f0:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 80009f4:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 80009f6:	4a04      	ldr	r2, [pc, #16]	; (8000a08 <__NVIC_SetPriorityGrouping+0x44>)
 80009f8:	68bb      	ldr	r3, [r7, #8]
 80009fa:	60d3      	str	r3, [r2, #12]
}
 80009fc:	bf00      	nop
 80009fe:	3714      	adds	r7, #20
 8000a00:	46bd      	mov	sp, r7
 8000a02:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a06:	4770      	bx	lr
 8000a08:	e000ed00 	.word	0xe000ed00

08000a0c <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 8000a0c:	b480      	push	{r7}
 8000a0e:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8000a10:	4b04      	ldr	r3, [pc, #16]	; (8000a24 <__NVIC_GetPriorityGrouping+0x18>)
 8000a12:	68db      	ldr	r3, [r3, #12]
 8000a14:	0a1b      	lsrs	r3, r3, #8
 8000a16:	f003 0307 	and.w	r3, r3, #7
}
 8000a1a:	4618      	mov	r0, r3
 8000a1c:	46bd      	mov	sp, r7
 8000a1e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a22:	4770      	bx	lr
 8000a24:	e000ed00 	.word	0xe000ed00

08000a28 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8000a28:	b480      	push	{r7}
 8000a2a:	b083      	sub	sp, #12
 8000a2c:	af00      	add	r7, sp, #0
 8000a2e:	4603      	mov	r3, r0
 8000a30:	6039      	str	r1, [r7, #0]
 8000a32:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8000a34:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000a38:	2b00      	cmp	r3, #0
 8000a3a:	db0a      	blt.n	8000a52 <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000a3c:	683b      	ldr	r3, [r7, #0]
 8000a3e:	b2da      	uxtb	r2, r3
 8000a40:	490c      	ldr	r1, [pc, #48]	; (8000a74 <__NVIC_SetPriority+0x4c>)
 8000a42:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000a46:	0112      	lsls	r2, r2, #4
 8000a48:	b2d2      	uxtb	r2, r2
 8000a4a:	440b      	add	r3, r1
 8000a4c:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 8000a50:	e00a      	b.n	8000a68 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000a52:	683b      	ldr	r3, [r7, #0]
 8000a54:	b2da      	uxtb	r2, r3
 8000a56:	4908      	ldr	r1, [pc, #32]	; (8000a78 <__NVIC_SetPriority+0x50>)
 8000a58:	79fb      	ldrb	r3, [r7, #7]
 8000a5a:	f003 030f 	and.w	r3, r3, #15
 8000a5e:	3b04      	subs	r3, #4
 8000a60:	0112      	lsls	r2, r2, #4
 8000a62:	b2d2      	uxtb	r2, r2
 8000a64:	440b      	add	r3, r1
 8000a66:	761a      	strb	r2, [r3, #24]
}
 8000a68:	bf00      	nop
 8000a6a:	370c      	adds	r7, #12
 8000a6c:	46bd      	mov	sp, r7
 8000a6e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000a72:	4770      	bx	lr
 8000a74:	e000e100 	.word	0xe000e100
 8000a78:	e000ed00 	.word	0xe000ed00

08000a7c <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8000a7c:	b480      	push	{r7}
 8000a7e:	b089      	sub	sp, #36	; 0x24
 8000a80:	af00      	add	r7, sp, #0
 8000a82:	60f8      	str	r0, [r7, #12]
 8000a84:	60b9      	str	r1, [r7, #8]
 8000a86:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8000a88:	68fb      	ldr	r3, [r7, #12]
 8000a8a:	f003 0307 	and.w	r3, r3, #7
 8000a8e:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8000a90:	69fb      	ldr	r3, [r7, #28]
 8000a92:	f1c3 0307 	rsb	r3, r3, #7
 8000a96:	2b04      	cmp	r3, #4
 8000a98:	bf28      	it	cs
 8000a9a:	2304      	movcs	r3, #4
 8000a9c:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000a9e:	69fb      	ldr	r3, [r7, #28]
 8000aa0:	3304      	adds	r3, #4
 8000aa2:	2b06      	cmp	r3, #6
 8000aa4:	d902      	bls.n	8000aac <NVIC_EncodePriority+0x30>
 8000aa6:	69fb      	ldr	r3, [r7, #28]
 8000aa8:	3b03      	subs	r3, #3
 8000aaa:	e000      	b.n	8000aae <NVIC_EncodePriority+0x32>
 8000aac:	2300      	movs	r3, #0
 8000aae:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000ab0:	f04f 32ff 	mov.w	r2, #4294967295
 8000ab4:	69bb      	ldr	r3, [r7, #24]
 8000ab6:	fa02 f303 	lsl.w	r3, r2, r3
 8000aba:	43da      	mvns	r2, r3
 8000abc:	68bb      	ldr	r3, [r7, #8]
 8000abe:	401a      	ands	r2, r3
 8000ac0:	697b      	ldr	r3, [r7, #20]
 8000ac2:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8000ac4:	f04f 31ff 	mov.w	r1, #4294967295
 8000ac8:	697b      	ldr	r3, [r7, #20]
 8000aca:	fa01 f303 	lsl.w	r3, r1, r3
 8000ace:	43d9      	mvns	r1, r3
 8000ad0:	687b      	ldr	r3, [r7, #4]
 8000ad2:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000ad4:	4313      	orrs	r3, r2
         );
}
 8000ad6:	4618      	mov	r0, r3
 8000ad8:	3724      	adds	r7, #36	; 0x24
 8000ada:	46bd      	mov	sp, r7
 8000adc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000ae0:	4770      	bx	lr
	...

08000ae4 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 8000ae4:	b580      	push	{r7, lr}
 8000ae6:	b082      	sub	sp, #8
 8000ae8:	af00      	add	r7, sp, #0
 8000aea:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8000aec:	687b      	ldr	r3, [r7, #4]
 8000aee:	3b01      	subs	r3, #1
 8000af0:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
 8000af4:	d301      	bcc.n	8000afa <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 8000af6:	2301      	movs	r3, #1
 8000af8:	e00f      	b.n	8000b1a <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8000afa:	4a0a      	ldr	r2, [pc, #40]	; (8000b24 <SysTick_Config+0x40>)
 8000afc:	687b      	ldr	r3, [r7, #4]
 8000afe:	3b01      	subs	r3, #1
 8000b00:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 8000b02:	210f      	movs	r1, #15
 8000b04:	f04f 30ff 	mov.w	r0, #4294967295
 8000b08:	f7ff ff8e 	bl	8000a28 <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8000b0c:	4b05      	ldr	r3, [pc, #20]	; (8000b24 <SysTick_Config+0x40>)
 8000b0e:	2200      	movs	r2, #0
 8000b10:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 8000b12:	4b04      	ldr	r3, [pc, #16]	; (8000b24 <SysTick_Config+0x40>)
 8000b14:	2207      	movs	r2, #7
 8000b16:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 8000b18:	2300      	movs	r3, #0
}
 8000b1a:	4618      	mov	r0, r3
 8000b1c:	3708      	adds	r7, #8
 8000b1e:	46bd      	mov	sp, r7
 8000b20:	bd80      	pop	{r7, pc}
 8000b22:	bf00      	nop
 8000b24:	e000e010 	.word	0xe000e010

08000b28 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8000b28:	b580      	push	{r7, lr}
 8000b2a:	b082      	sub	sp, #8
 8000b2c:	af00      	add	r7, sp, #0
 8000b2e:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 8000b30:	6878      	ldr	r0, [r7, #4]
 8000b32:	f7ff ff47 	bl	80009c4 <__NVIC_SetPriorityGrouping>
}
 8000b36:	bf00      	nop
 8000b38:	3708      	adds	r7, #8
 8000b3a:	46bd      	mov	sp, r7
 8000b3c:	bd80      	pop	{r7, pc}

08000b3e <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 8000b3e:	b580      	push	{r7, lr}
 8000b40:	b086      	sub	sp, #24
 8000b42:	af00      	add	r7, sp, #0
 8000b44:	4603      	mov	r3, r0
 8000b46:	60b9      	str	r1, [r7, #8]
 8000b48:	607a      	str	r2, [r7, #4]
 8000b4a:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00U;
 8000b4c:	2300      	movs	r3, #0
 8000b4e:	617b      	str	r3, [r7, #20]
  
  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  
  prioritygroup = NVIC_GetPriorityGrouping();
 8000b50:	f7ff ff5c 	bl	8000a0c <__NVIC_GetPriorityGrouping>
 8000b54:	6178      	str	r0, [r7, #20]
  
  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 8000b56:	687a      	ldr	r2, [r7, #4]
 8000b58:	68b9      	ldr	r1, [r7, #8]
 8000b5a:	6978      	ldr	r0, [r7, #20]
 8000b5c:	f7ff ff8e 	bl	8000a7c <NVIC_EncodePriority>
 8000b60:	4602      	mov	r2, r0
 8000b62:	f997 300f 	ldrsb.w	r3, [r7, #15]
 8000b66:	4611      	mov	r1, r2
 8000b68:	4618      	mov	r0, r3
 8000b6a:	f7ff ff5d 	bl	8000a28 <__NVIC_SetPriority>
}
 8000b6e:	bf00      	nop
 8000b70:	3718      	adds	r7, #24
 8000b72:	46bd      	mov	sp, r7
 8000b74:	bd80      	pop	{r7, pc}

08000b76 <HAL_SYSTICK_Config>:
  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 8000b76:	b580      	push	{r7, lr}
 8000b78:	b082      	sub	sp, #8
 8000b7a:	af00      	add	r7, sp, #0
 8000b7c:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 8000b7e:	6878      	ldr	r0, [r7, #4]
 8000b80:	f7ff ffb0 	bl	8000ae4 <SysTick_Config>
 8000b84:	4603      	mov	r3, r0
}
 8000b86:	4618      	mov	r0, r3
 8000b88:	3708      	adds	r7, #8
 8000b8a:	46bd      	mov	sp, r7
 8000b8c:	bd80      	pop	{r7, pc}
	...

08000b90 <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8000b90:	b480      	push	{r7}
 8000b92:	b089      	sub	sp, #36	; 0x24
 8000b94:	af00      	add	r7, sp, #0
 8000b96:	6078      	str	r0, [r7, #4]
 8000b98:	6039      	str	r1, [r7, #0]
  uint32_t position;
  uint32_t ioposition = 0x00U;
 8000b9a:	2300      	movs	r3, #0
 8000b9c:	617b      	str	r3, [r7, #20]
  uint32_t iocurrent = 0x00U;
 8000b9e:	2300      	movs	r3, #0
 8000ba0:	613b      	str	r3, [r7, #16]
  uint32_t temp = 0x00U;
 8000ba2:	2300      	movs	r3, #0
 8000ba4:	61bb      	str	r3, [r7, #24]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  for(position = 0U; position < GPIO_NUMBER; position++)
 8000ba6:	2300      	movs	r3, #0
 8000ba8:	61fb      	str	r3, [r7, #28]
 8000baa:	e159      	b.n	8000e60 <HAL_GPIO_Init+0x2d0>
  {
    /* Get the IO position */
    ioposition = 0x01U << position;
 8000bac:	2201      	movs	r2, #1
 8000bae:	69fb      	ldr	r3, [r7, #28]
 8000bb0:	fa02 f303 	lsl.w	r3, r2, r3
 8000bb4:	617b      	str	r3, [r7, #20]
    /* Get the current IO position */
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8000bb6:	683b      	ldr	r3, [r7, #0]
 8000bb8:	681b      	ldr	r3, [r3, #0]
 8000bba:	697a      	ldr	r2, [r7, #20]
 8000bbc:	4013      	ands	r3, r2
 8000bbe:	613b      	str	r3, [r7, #16]

    if(iocurrent == ioposition)
 8000bc0:	693a      	ldr	r2, [r7, #16]
 8000bc2:	697b      	ldr	r3, [r7, #20]
 8000bc4:	429a      	cmp	r2, r3
 8000bc6:	f040 8148 	bne.w	8000e5a <HAL_GPIO_Init+0x2ca>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
 8000bca:	683b      	ldr	r3, [r7, #0]
 8000bcc:	685b      	ldr	r3, [r3, #4]
 8000bce:	f003 0303 	and.w	r3, r3, #3
 8000bd2:	2b01      	cmp	r3, #1
 8000bd4:	d005      	beq.n	8000be2 <HAL_GPIO_Init+0x52>
          (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8000bd6:	683b      	ldr	r3, [r7, #0]
 8000bd8:	685b      	ldr	r3, [r3, #4]
 8000bda:	f003 0303 	and.w	r3, r3, #3
      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
 8000bde:	2b02      	cmp	r3, #2
 8000be0:	d130      	bne.n	8000c44 <HAL_GPIO_Init+0xb4>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR; 
 8000be2:	687b      	ldr	r3, [r7, #4]
 8000be4:	689b      	ldr	r3, [r3, #8]
 8000be6:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
 8000be8:	69fb      	ldr	r3, [r7, #28]
 8000bea:	005b      	lsls	r3, r3, #1
 8000bec:	2203      	movs	r2, #3
 8000bee:	fa02 f303 	lsl.w	r3, r2, r3
 8000bf2:	43db      	mvns	r3, r3
 8000bf4:	69ba      	ldr	r2, [r7, #24]
 8000bf6:	4013      	ands	r3, r2
 8000bf8:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_Init->Speed << (position * 2U));
 8000bfa:	683b      	ldr	r3, [r7, #0]
 8000bfc:	68da      	ldr	r2, [r3, #12]
 8000bfe:	69fb      	ldr	r3, [r7, #28]
 8000c00:	005b      	lsls	r3, r3, #1
 8000c02:	fa02 f303 	lsl.w	r3, r2, r3
 8000c06:	69ba      	ldr	r2, [r7, #24]
 8000c08:	4313      	orrs	r3, r2
 8000c0a:	61bb      	str	r3, [r7, #24]
        GPIOx->OSPEEDR = temp;
 8000c0c:	687b      	ldr	r3, [r7, #4]
 8000c0e:	69ba      	ldr	r2, [r7, #24]
 8000c10:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 8000c12:	687b      	ldr	r3, [r7, #4]
 8000c14:	685b      	ldr	r3, [r3, #4]
 8000c16:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
 8000c18:	2201      	movs	r2, #1
 8000c1a:	69fb      	ldr	r3, [r7, #28]
 8000c1c:	fa02 f303 	lsl.w	r3, r2, r3
 8000c20:	43db      	mvns	r3, r3
 8000c22:	69ba      	ldr	r2, [r7, #24]
 8000c24:	4013      	ands	r3, r2
 8000c26:	61bb      	str	r3, [r7, #24]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 8000c28:	683b      	ldr	r3, [r7, #0]
 8000c2a:	685b      	ldr	r3, [r3, #4]
 8000c2c:	091b      	lsrs	r3, r3, #4
 8000c2e:	f003 0201 	and.w	r2, r3, #1
 8000c32:	69fb      	ldr	r3, [r7, #28]
 8000c34:	fa02 f303 	lsl.w	r3, r2, r3
 8000c38:	69ba      	ldr	r2, [r7, #24]
 8000c3a:	4313      	orrs	r3, r2
 8000c3c:	61bb      	str	r3, [r7, #24]
        GPIOx->OTYPER = temp;
 8000c3e:	687b      	ldr	r3, [r7, #4]
 8000c40:	69ba      	ldr	r2, [r7, #24]
 8000c42:	605a      	str	r2, [r3, #4]
       }

      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 8000c44:	683b      	ldr	r3, [r7, #0]
 8000c46:	685b      	ldr	r3, [r3, #4]
 8000c48:	f003 0303 	and.w	r3, r3, #3
 8000c4c:	2b03      	cmp	r3, #3
 8000c4e:	d017      	beq.n	8000c80 <HAL_GPIO_Init+0xf0>
      {
        /* Check the parameters */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
        
        /* Activate the Pull-up or Pull down resistor for the current IO */
        temp = GPIOx->PUPDR;
 8000c50:	687b      	ldr	r3, [r7, #4]
 8000c52:	68db      	ldr	r3, [r3, #12]
 8000c54:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
 8000c56:	69fb      	ldr	r3, [r7, #28]
 8000c58:	005b      	lsls	r3, r3, #1
 8000c5a:	2203      	movs	r2, #3
 8000c5c:	fa02 f303 	lsl.w	r3, r2, r3
 8000c60:	43db      	mvns	r3, r3
 8000c62:	69ba      	ldr	r2, [r7, #24]
 8000c64:	4013      	ands	r3, r2
 8000c66:	61bb      	str	r3, [r7, #24]
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 8000c68:	683b      	ldr	r3, [r7, #0]
 8000c6a:	689a      	ldr	r2, [r3, #8]
 8000c6c:	69fb      	ldr	r3, [r7, #28]
 8000c6e:	005b      	lsls	r3, r3, #1
 8000c70:	fa02 f303 	lsl.w	r3, r2, r3
 8000c74:	69ba      	ldr	r2, [r7, #24]
 8000c76:	4313      	orrs	r3, r2
 8000c78:	61bb      	str	r3, [r7, #24]
        GPIOx->PUPDR = temp;
 8000c7a:	687b      	ldr	r3, [r7, #4]
 8000c7c:	69ba      	ldr	r2, [r7, #24]
 8000c7e:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8000c80:	683b      	ldr	r3, [r7, #0]
 8000c82:	685b      	ldr	r3, [r3, #4]
 8000c84:	f003 0303 	and.w	r3, r3, #3
 8000c88:	2b02      	cmp	r3, #2
 8000c8a:	d123      	bne.n	8000cd4 <HAL_GPIO_Init+0x144>
      {
        /* Check the Alternate function parameter */
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3U];
 8000c8c:	69fb      	ldr	r3, [r7, #28]
 8000c8e:	08da      	lsrs	r2, r3, #3
 8000c90:	687b      	ldr	r3, [r7, #4]
 8000c92:	3208      	adds	r2, #8
 8000c94:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 8000c98:	61bb      	str	r3, [r7, #24]
        temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
 8000c9a:	69fb      	ldr	r3, [r7, #28]
 8000c9c:	f003 0307 	and.w	r3, r3, #7
 8000ca0:	009b      	lsls	r3, r3, #2
 8000ca2:	220f      	movs	r2, #15
 8000ca4:	fa02 f303 	lsl.w	r3, r2, r3
 8000ca8:	43db      	mvns	r3, r3
 8000caa:	69ba      	ldr	r2, [r7, #24]
 8000cac:	4013      	ands	r3, r2
 8000cae:	61bb      	str	r3, [r7, #24]
        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
 8000cb0:	683b      	ldr	r3, [r7, #0]
 8000cb2:	691a      	ldr	r2, [r3, #16]
 8000cb4:	69fb      	ldr	r3, [r7, #28]
 8000cb6:	f003 0307 	and.w	r3, r3, #7
 8000cba:	009b      	lsls	r3, r3, #2
 8000cbc:	fa02 f303 	lsl.w	r3, r2, r3
 8000cc0:	69ba      	ldr	r2, [r7, #24]
 8000cc2:	4313      	orrs	r3, r2
 8000cc4:	61bb      	str	r3, [r7, #24]
        GPIOx->AFR[position >> 3U] = temp;
 8000cc6:	69fb      	ldr	r3, [r7, #28]
 8000cc8:	08da      	lsrs	r2, r3, #3
 8000cca:	687b      	ldr	r3, [r7, #4]
 8000ccc:	3208      	adds	r2, #8
 8000cce:	69b9      	ldr	r1, [r7, #24]
 8000cd0:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 8000cd4:	687b      	ldr	r3, [r7, #4]
 8000cd6:	681b      	ldr	r3, [r3, #0]
 8000cd8:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
 8000cda:	69fb      	ldr	r3, [r7, #28]
 8000cdc:	005b      	lsls	r3, r3, #1
 8000cde:	2203      	movs	r2, #3
 8000ce0:	fa02 f303 	lsl.w	r3, r2, r3
 8000ce4:	43db      	mvns	r3, r3
 8000ce6:	69ba      	ldr	r2, [r7, #24]
 8000ce8:	4013      	ands	r3, r2
 8000cea:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
 8000cec:	683b      	ldr	r3, [r7, #0]
 8000cee:	685b      	ldr	r3, [r3, #4]
 8000cf0:	f003 0203 	and.w	r2, r3, #3
 8000cf4:	69fb      	ldr	r3, [r7, #28]
 8000cf6:	005b      	lsls	r3, r3, #1
 8000cf8:	fa02 f303 	lsl.w	r3, r2, r3
 8000cfc:	69ba      	ldr	r2, [r7, #24]
 8000cfe:	4313      	orrs	r3, r2
 8000d00:	61bb      	str	r3, [r7, #24]
      GPIOx->MODER = temp;
 8000d02:	687b      	ldr	r3, [r7, #4]
 8000d04:	69ba      	ldr	r2, [r7, #24]
 8000d06:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
 8000d08:	683b      	ldr	r3, [r7, #0]
 8000d0a:	685b      	ldr	r3, [r3, #4]
 8000d0c:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8000d10:	2b00      	cmp	r3, #0
 8000d12:	f000 80a2 	beq.w	8000e5a <HAL_GPIO_Init+0x2ca>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 8000d16:	2300      	movs	r3, #0
 8000d18:	60fb      	str	r3, [r7, #12]
 8000d1a:	4b57      	ldr	r3, [pc, #348]	; (8000e78 <HAL_GPIO_Init+0x2e8>)
 8000d1c:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000d1e:	4a56      	ldr	r2, [pc, #344]	; (8000e78 <HAL_GPIO_Init+0x2e8>)
 8000d20:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 8000d24:	6453      	str	r3, [r2, #68]	; 0x44
 8000d26:	4b54      	ldr	r3, [pc, #336]	; (8000e78 <HAL_GPIO_Init+0x2e8>)
 8000d28:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000d2a:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 8000d2e:	60fb      	str	r3, [r7, #12]
 8000d30:	68fb      	ldr	r3, [r7, #12]

        temp = SYSCFG->EXTICR[position >> 2U];
 8000d32:	4a52      	ldr	r2, [pc, #328]	; (8000e7c <HAL_GPIO_Init+0x2ec>)
 8000d34:	69fb      	ldr	r3, [r7, #28]
 8000d36:	089b      	lsrs	r3, r3, #2
 8000d38:	3302      	adds	r3, #2
 8000d3a:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8000d3e:	61bb      	str	r3, [r7, #24]
        temp &= ~(0x0FU << (4U * (position & 0x03U)));
 8000d40:	69fb      	ldr	r3, [r7, #28]
 8000d42:	f003 0303 	and.w	r3, r3, #3
 8000d46:	009b      	lsls	r3, r3, #2
 8000d48:	220f      	movs	r2, #15
 8000d4a:	fa02 f303 	lsl.w	r3, r2, r3
 8000d4e:	43db      	mvns	r3, r3
 8000d50:	69ba      	ldr	r2, [r7, #24]
 8000d52:	4013      	ands	r3, r2
 8000d54:	61bb      	str	r3, [r7, #24]
        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8000d56:	687b      	ldr	r3, [r7, #4]
 8000d58:	4a49      	ldr	r2, [pc, #292]	; (8000e80 <HAL_GPIO_Init+0x2f0>)
 8000d5a:	4293      	cmp	r3, r2
 8000d5c:	d019      	beq.n	8000d92 <HAL_GPIO_Init+0x202>
 8000d5e:	687b      	ldr	r3, [r7, #4]
 8000d60:	4a48      	ldr	r2, [pc, #288]	; (8000e84 <HAL_GPIO_Init+0x2f4>)
 8000d62:	4293      	cmp	r3, r2
 8000d64:	d013      	beq.n	8000d8e <HAL_GPIO_Init+0x1fe>
 8000d66:	687b      	ldr	r3, [r7, #4]
 8000d68:	4a47      	ldr	r2, [pc, #284]	; (8000e88 <HAL_GPIO_Init+0x2f8>)
 8000d6a:	4293      	cmp	r3, r2
 8000d6c:	d00d      	beq.n	8000d8a <HAL_GPIO_Init+0x1fa>
 8000d6e:	687b      	ldr	r3, [r7, #4]
 8000d70:	4a46      	ldr	r2, [pc, #280]	; (8000e8c <HAL_GPIO_Init+0x2fc>)
 8000d72:	4293      	cmp	r3, r2
 8000d74:	d007      	beq.n	8000d86 <HAL_GPIO_Init+0x1f6>
 8000d76:	687b      	ldr	r3, [r7, #4]
 8000d78:	4a45      	ldr	r2, [pc, #276]	; (8000e90 <HAL_GPIO_Init+0x300>)
 8000d7a:	4293      	cmp	r3, r2
 8000d7c:	d101      	bne.n	8000d82 <HAL_GPIO_Init+0x1f2>
 8000d7e:	2304      	movs	r3, #4
 8000d80:	e008      	b.n	8000d94 <HAL_GPIO_Init+0x204>
 8000d82:	2307      	movs	r3, #7
 8000d84:	e006      	b.n	8000d94 <HAL_GPIO_Init+0x204>
 8000d86:	2303      	movs	r3, #3
 8000d88:	e004      	b.n	8000d94 <HAL_GPIO_Init+0x204>
 8000d8a:	2302      	movs	r3, #2
 8000d8c:	e002      	b.n	8000d94 <HAL_GPIO_Init+0x204>
 8000d8e:	2301      	movs	r3, #1
 8000d90:	e000      	b.n	8000d94 <HAL_GPIO_Init+0x204>
 8000d92:	2300      	movs	r3, #0
 8000d94:	69fa      	ldr	r2, [r7, #28]
 8000d96:	f002 0203 	and.w	r2, r2, #3
 8000d9a:	0092      	lsls	r2, r2, #2
 8000d9c:	4093      	lsls	r3, r2
 8000d9e:	69ba      	ldr	r2, [r7, #24]
 8000da0:	4313      	orrs	r3, r2
 8000da2:	61bb      	str	r3, [r7, #24]
        SYSCFG->EXTICR[position >> 2U] = temp;
 8000da4:	4935      	ldr	r1, [pc, #212]	; (8000e7c <HAL_GPIO_Init+0x2ec>)
 8000da6:	69fb      	ldr	r3, [r7, #28]
 8000da8:	089b      	lsrs	r3, r3, #2
 8000daa:	3302      	adds	r3, #2
 8000dac:	69ba      	ldr	r2, [r7, #24]
 8000dae:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR;
 8000db2:	4b38      	ldr	r3, [pc, #224]	; (8000e94 <HAL_GPIO_Init+0x304>)
 8000db4:	689b      	ldr	r3, [r3, #8]
 8000db6:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8000db8:	693b      	ldr	r3, [r7, #16]
 8000dba:	43db      	mvns	r3, r3
 8000dbc:	69ba      	ldr	r2, [r7, #24]
 8000dbe:	4013      	ands	r3, r2
 8000dc0:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
 8000dc2:	683b      	ldr	r3, [r7, #0]
 8000dc4:	685b      	ldr	r3, [r3, #4]
 8000dc6:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
 8000dca:	2b00      	cmp	r3, #0
 8000dcc:	d003      	beq.n	8000dd6 <HAL_GPIO_Init+0x246>
        {
          temp |= iocurrent;
 8000dce:	69ba      	ldr	r2, [r7, #24]
 8000dd0:	693b      	ldr	r3, [r7, #16]
 8000dd2:	4313      	orrs	r3, r2
 8000dd4:	61bb      	str	r3, [r7, #24]
        }
        EXTI->RTSR = temp;
 8000dd6:	4a2f      	ldr	r2, [pc, #188]	; (8000e94 <HAL_GPIO_Init+0x304>)
 8000dd8:	69bb      	ldr	r3, [r7, #24]
 8000dda:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR;
 8000ddc:	4b2d      	ldr	r3, [pc, #180]	; (8000e94 <HAL_GPIO_Init+0x304>)
 8000dde:	68db      	ldr	r3, [r3, #12]
 8000de0:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8000de2:	693b      	ldr	r3, [r7, #16]
 8000de4:	43db      	mvns	r3, r3
 8000de6:	69ba      	ldr	r2, [r7, #24]
 8000de8:	4013      	ands	r3, r2
 8000dea:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
 8000dec:	683b      	ldr	r3, [r7, #0]
 8000dee:	685b      	ldr	r3, [r3, #4]
 8000df0:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 8000df4:	2b00      	cmp	r3, #0
 8000df6:	d003      	beq.n	8000e00 <HAL_GPIO_Init+0x270>
        {
          temp |= iocurrent;
 8000df8:	69ba      	ldr	r2, [r7, #24]
 8000dfa:	693b      	ldr	r3, [r7, #16]
 8000dfc:	4313      	orrs	r3, r2
 8000dfe:	61bb      	str	r3, [r7, #24]
        }
        EXTI->FTSR = temp;
 8000e00:	4a24      	ldr	r2, [pc, #144]	; (8000e94 <HAL_GPIO_Init+0x304>)
 8000e02:	69bb      	ldr	r3, [r7, #24]
 8000e04:	60d3      	str	r3, [r2, #12]

        temp = EXTI->EMR;
 8000e06:	4b23      	ldr	r3, [pc, #140]	; (8000e94 <HAL_GPIO_Init+0x304>)
 8000e08:	685b      	ldr	r3, [r3, #4]
 8000e0a:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8000e0c:	693b      	ldr	r3, [r7, #16]
 8000e0e:	43db      	mvns	r3, r3
 8000e10:	69ba      	ldr	r2, [r7, #24]
 8000e12:	4013      	ands	r3, r2
 8000e14:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
 8000e16:	683b      	ldr	r3, [r7, #0]
 8000e18:	685b      	ldr	r3, [r3, #4]
 8000e1a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000e1e:	2b00      	cmp	r3, #0
 8000e20:	d003      	beq.n	8000e2a <HAL_GPIO_Init+0x29a>
        {
          temp |= iocurrent;
 8000e22:	69ba      	ldr	r2, [r7, #24]
 8000e24:	693b      	ldr	r3, [r7, #16]
 8000e26:	4313      	orrs	r3, r2
 8000e28:	61bb      	str	r3, [r7, #24]
        }
        EXTI->EMR = temp;
 8000e2a:	4a1a      	ldr	r2, [pc, #104]	; (8000e94 <HAL_GPIO_Init+0x304>)
 8000e2c:	69bb      	ldr	r3, [r7, #24]
 8000e2e:	6053      	str	r3, [r2, #4]

        /* Clear EXTI line configuration */
        temp = EXTI->IMR;
 8000e30:	4b18      	ldr	r3, [pc, #96]	; (8000e94 <HAL_GPIO_Init+0x304>)
 8000e32:	681b      	ldr	r3, [r3, #0]
 8000e34:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8000e36:	693b      	ldr	r3, [r7, #16]
 8000e38:	43db      	mvns	r3, r3
 8000e3a:	69ba      	ldr	r2, [r7, #24]
 8000e3c:	4013      	ands	r3, r2
 8000e3e:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
 8000e40:	683b      	ldr	r3, [r7, #0]
 8000e42:	685b      	ldr	r3, [r3, #4]
 8000e44:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8000e48:	2b00      	cmp	r3, #0
 8000e4a:	d003      	beq.n	8000e54 <HAL_GPIO_Init+0x2c4>
        {
          temp |= iocurrent;
 8000e4c:	69ba      	ldr	r2, [r7, #24]
 8000e4e:	693b      	ldr	r3, [r7, #16]
 8000e50:	4313      	orrs	r3, r2
 8000e52:	61bb      	str	r3, [r7, #24]
        }
        EXTI->IMR = temp;
 8000e54:	4a0f      	ldr	r2, [pc, #60]	; (8000e94 <HAL_GPIO_Init+0x304>)
 8000e56:	69bb      	ldr	r3, [r7, #24]
 8000e58:	6013      	str	r3, [r2, #0]
  for(position = 0U; position < GPIO_NUMBER; position++)
 8000e5a:	69fb      	ldr	r3, [r7, #28]
 8000e5c:	3301      	adds	r3, #1
 8000e5e:	61fb      	str	r3, [r7, #28]
 8000e60:	69fb      	ldr	r3, [r7, #28]
 8000e62:	2b0f      	cmp	r3, #15
 8000e64:	f67f aea2 	bls.w	8000bac <HAL_GPIO_Init+0x1c>
      }
    }
  }
}
 8000e68:	bf00      	nop
 8000e6a:	bf00      	nop
 8000e6c:	3724      	adds	r7, #36	; 0x24
 8000e6e:	46bd      	mov	sp, r7
 8000e70:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000e74:	4770      	bx	lr
 8000e76:	bf00      	nop
 8000e78:	40023800 	.word	0x40023800
 8000e7c:	40013800 	.word	0x40013800
 8000e80:	40020000 	.word	0x40020000
 8000e84:	40020400 	.word	0x40020400
 8000e88:	40020800 	.word	0x40020800
 8000e8c:	40020c00 	.word	0x40020c00
 8000e90:	40021000 	.word	0x40021000
 8000e94:	40013c00 	.word	0x40013c00

08000e98 <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 8000e98:	b480      	push	{r7}
 8000e9a:	b083      	sub	sp, #12
 8000e9c:	af00      	add	r7, sp, #0
 8000e9e:	6078      	str	r0, [r7, #4]
 8000ea0:	460b      	mov	r3, r1
 8000ea2:	807b      	strh	r3, [r7, #2]
 8000ea4:	4613      	mov	r3, r2
 8000ea6:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if(PinState != GPIO_PIN_RESET)
 8000ea8:	787b      	ldrb	r3, [r7, #1]
 8000eaa:	2b00      	cmp	r3, #0
 8000eac:	d003      	beq.n	8000eb6 <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = GPIO_Pin;
 8000eae:	887a      	ldrh	r2, [r7, #2]
 8000eb0:	687b      	ldr	r3, [r7, #4]
 8000eb2:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
  }
}
 8000eb4:	e003      	b.n	8000ebe <HAL_GPIO_WritePin+0x26>
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
 8000eb6:	887b      	ldrh	r3, [r7, #2]
 8000eb8:	041a      	lsls	r2, r3, #16
 8000eba:	687b      	ldr	r3, [r7, #4]
 8000ebc:	619a      	str	r2, [r3, #24]
}
 8000ebe:	bf00      	nop
 8000ec0:	370c      	adds	r7, #12
 8000ec2:	46bd      	mov	sp, r7
 8000ec4:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000ec8:	4770      	bx	lr
	...

08000ecc <HAL_RCC_OscConfig>:
  *         supported by this API. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8000ecc:	b580      	push	{r7, lr}
 8000ece:	b086      	sub	sp, #24
 8000ed0:	af00      	add	r7, sp, #0
 8000ed2:	6078      	str	r0, [r7, #4]
  uint32_t tickstart, pll_config;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 8000ed4:	687b      	ldr	r3, [r7, #4]
 8000ed6:	2b00      	cmp	r3, #0
 8000ed8:	d101      	bne.n	8000ede <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 8000eda:	2301      	movs	r3, #1
 8000edc:	e267      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8000ede:	687b      	ldr	r3, [r7, #4]
 8000ee0:	681b      	ldr	r3, [r3, #0]
 8000ee2:	f003 0301 	and.w	r3, r3, #1
 8000ee6:	2b00      	cmp	r3, #0
 8000ee8:	d075      	beq.n	8000fd6 <HAL_RCC_OscConfig+0x10a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
 8000eea:	4b88      	ldr	r3, [pc, #544]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000eec:	689b      	ldr	r3, [r3, #8]
 8000eee:	f003 030c 	and.w	r3, r3, #12
 8000ef2:	2b04      	cmp	r3, #4
 8000ef4:	d00c      	beq.n	8000f10 <HAL_RCC_OscConfig+0x44>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 8000ef6:	4b85      	ldr	r3, [pc, #532]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000ef8:	689b      	ldr	r3, [r3, #8]
 8000efa:	f003 030c 	and.w	r3, r3, #12
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
 8000efe:	2b08      	cmp	r3, #8
 8000f00:	d112      	bne.n	8000f28 <HAL_RCC_OscConfig+0x5c>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 8000f02:	4b82      	ldr	r3, [pc, #520]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f04:	685b      	ldr	r3, [r3, #4]
 8000f06:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 8000f0a:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
 8000f0e:	d10b      	bne.n	8000f28 <HAL_RCC_OscConfig+0x5c>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8000f10:	4b7e      	ldr	r3, [pc, #504]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f12:	681b      	ldr	r3, [r3, #0]
 8000f14:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000f18:	2b00      	cmp	r3, #0
 8000f1a:	d05b      	beq.n	8000fd4 <HAL_RCC_OscConfig+0x108>
 8000f1c:	687b      	ldr	r3, [r7, #4]
 8000f1e:	685b      	ldr	r3, [r3, #4]
 8000f20:	2b00      	cmp	r3, #0
 8000f22:	d157      	bne.n	8000fd4 <HAL_RCC_OscConfig+0x108>
      {
        return HAL_ERROR;
 8000f24:	2301      	movs	r3, #1
 8000f26:	e242      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8000f28:	687b      	ldr	r3, [r7, #4]
 8000f2a:	685b      	ldr	r3, [r3, #4]
 8000f2c:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8000f30:	d106      	bne.n	8000f40 <HAL_RCC_OscConfig+0x74>
 8000f32:	4b76      	ldr	r3, [pc, #472]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f34:	681b      	ldr	r3, [r3, #0]
 8000f36:	4a75      	ldr	r2, [pc, #468]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f38:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8000f3c:	6013      	str	r3, [r2, #0]
 8000f3e:	e01d      	b.n	8000f7c <HAL_RCC_OscConfig+0xb0>
 8000f40:	687b      	ldr	r3, [r7, #4]
 8000f42:	685b      	ldr	r3, [r3, #4]
 8000f44:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8000f48:	d10c      	bne.n	8000f64 <HAL_RCC_OscConfig+0x98>
 8000f4a:	4b70      	ldr	r3, [pc, #448]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f4c:	681b      	ldr	r3, [r3, #0]
 8000f4e:	4a6f      	ldr	r2, [pc, #444]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f50:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8000f54:	6013      	str	r3, [r2, #0]
 8000f56:	4b6d      	ldr	r3, [pc, #436]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f58:	681b      	ldr	r3, [r3, #0]
 8000f5a:	4a6c      	ldr	r2, [pc, #432]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f5c:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8000f60:	6013      	str	r3, [r2, #0]
 8000f62:	e00b      	b.n	8000f7c <HAL_RCC_OscConfig+0xb0>
 8000f64:	4b69      	ldr	r3, [pc, #420]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f66:	681b      	ldr	r3, [r3, #0]
 8000f68:	4a68      	ldr	r2, [pc, #416]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f6a:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8000f6e:	6013      	str	r3, [r2, #0]
 8000f70:	4b66      	ldr	r3, [pc, #408]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f72:	681b      	ldr	r3, [r3, #0]
 8000f74:	4a65      	ldr	r2, [pc, #404]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000f76:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8000f7a:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
 8000f7c:	687b      	ldr	r3, [r7, #4]
 8000f7e:	685b      	ldr	r3, [r3, #4]
 8000f80:	2b00      	cmp	r3, #0
 8000f82:	d013      	beq.n	8000fac <HAL_RCC_OscConfig+0xe0>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000f84:	f7ff fd12 	bl	80009ac <HAL_GetTick>
 8000f88:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000f8a:	e008      	b.n	8000f9e <HAL_RCC_OscConfig+0xd2>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000f8c:	f7ff fd0e 	bl	80009ac <HAL_GetTick>
 8000f90:	4602      	mov	r2, r0
 8000f92:	693b      	ldr	r3, [r7, #16]
 8000f94:	1ad3      	subs	r3, r2, r3
 8000f96:	2b64      	cmp	r3, #100	; 0x64
 8000f98:	d901      	bls.n	8000f9e <HAL_RCC_OscConfig+0xd2>
          {
            return HAL_TIMEOUT;
 8000f9a:	2303      	movs	r3, #3
 8000f9c:	e207      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8000f9e:	4b5b      	ldr	r3, [pc, #364]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000fa0:	681b      	ldr	r3, [r3, #0]
 8000fa2:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000fa6:	2b00      	cmp	r3, #0
 8000fa8:	d0f0      	beq.n	8000f8c <HAL_RCC_OscConfig+0xc0>
 8000faa:	e014      	b.n	8000fd6 <HAL_RCC_OscConfig+0x10a>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8000fac:	f7ff fcfe 	bl	80009ac <HAL_GetTick>
 8000fb0:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is bypassed or disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8000fb2:	e008      	b.n	8000fc6 <HAL_RCC_OscConfig+0xfa>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8000fb4:	f7ff fcfa 	bl	80009ac <HAL_GetTick>
 8000fb8:	4602      	mov	r2, r0
 8000fba:	693b      	ldr	r3, [r7, #16]
 8000fbc:	1ad3      	subs	r3, r2, r3
 8000fbe:	2b64      	cmp	r3, #100	; 0x64
 8000fc0:	d901      	bls.n	8000fc6 <HAL_RCC_OscConfig+0xfa>
          {
            return HAL_TIMEOUT;
 8000fc2:	2303      	movs	r3, #3
 8000fc4:	e1f3      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8000fc6:	4b51      	ldr	r3, [pc, #324]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000fc8:	681b      	ldr	r3, [r3, #0]
 8000fca:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000fce:	2b00      	cmp	r3, #0
 8000fd0:	d1f0      	bne.n	8000fb4 <HAL_RCC_OscConfig+0xe8>
 8000fd2:	e000      	b.n	8000fd6 <HAL_RCC_OscConfig+0x10a>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8000fd4:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8000fd6:	687b      	ldr	r3, [r7, #4]
 8000fd8:	681b      	ldr	r3, [r3, #0]
 8000fda:	f003 0302 	and.w	r3, r3, #2
 8000fde:	2b00      	cmp	r3, #0
 8000fe0:	d063      	beq.n	80010aa <HAL_RCC_OscConfig+0x1de>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
 8000fe2:	4b4a      	ldr	r3, [pc, #296]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000fe4:	689b      	ldr	r3, [r3, #8]
 8000fe6:	f003 030c 	and.w	r3, r3, #12
 8000fea:	2b00      	cmp	r3, #0
 8000fec:	d00b      	beq.n	8001006 <HAL_RCC_OscConfig+0x13a>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 8000fee:	4b47      	ldr	r3, [pc, #284]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000ff0:	689b      	ldr	r3, [r3, #8]
 8000ff2:	f003 030c 	and.w	r3, r3, #12
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
 8000ff6:	2b08      	cmp	r3, #8
 8000ff8:	d11c      	bne.n	8001034 <HAL_RCC_OscConfig+0x168>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 8000ffa:	4b44      	ldr	r3, [pc, #272]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8000ffc:	685b      	ldr	r3, [r3, #4]
 8000ffe:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 8001002:	2b00      	cmp	r3, #0
 8001004:	d116      	bne.n	8001034 <HAL_RCC_OscConfig+0x168>
    {
      /* When HSI is used as system clock it will not disabled */
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8001006:	4b41      	ldr	r3, [pc, #260]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8001008:	681b      	ldr	r3, [r3, #0]
 800100a:	f003 0302 	and.w	r3, r3, #2
 800100e:	2b00      	cmp	r3, #0
 8001010:	d005      	beq.n	800101e <HAL_RCC_OscConfig+0x152>
 8001012:	687b      	ldr	r3, [r7, #4]
 8001014:	68db      	ldr	r3, [r3, #12]
 8001016:	2b01      	cmp	r3, #1
 8001018:	d001      	beq.n	800101e <HAL_RCC_OscConfig+0x152>
      {
        return HAL_ERROR;
 800101a:	2301      	movs	r3, #1
 800101c:	e1c7      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 800101e:	4b3b      	ldr	r3, [pc, #236]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8001020:	681b      	ldr	r3, [r3, #0]
 8001022:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 8001026:	687b      	ldr	r3, [r7, #4]
 8001028:	691b      	ldr	r3, [r3, #16]
 800102a:	00db      	lsls	r3, r3, #3
 800102c:	4937      	ldr	r1, [pc, #220]	; (800110c <HAL_RCC_OscConfig+0x240>)
 800102e:	4313      	orrs	r3, r2
 8001030:	600b      	str	r3, [r1, #0]
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8001032:	e03a      	b.n	80010aa <HAL_RCC_OscConfig+0x1de>
      }
    }
    else
    {
      /* Check the HSI State */
      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
 8001034:	687b      	ldr	r3, [r7, #4]
 8001036:	68db      	ldr	r3, [r3, #12]
 8001038:	2b00      	cmp	r3, #0
 800103a:	d020      	beq.n	800107e <HAL_RCC_OscConfig+0x1b2>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 800103c:	4b34      	ldr	r3, [pc, #208]	; (8001110 <HAL_RCC_OscConfig+0x244>)
 800103e:	2201      	movs	r2, #1
 8001040:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001042:	f7ff fcb3 	bl	80009ac <HAL_GetTick>
 8001046:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8001048:	e008      	b.n	800105c <HAL_RCC_OscConfig+0x190>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 800104a:	f7ff fcaf 	bl	80009ac <HAL_GetTick>
 800104e:	4602      	mov	r2, r0
 8001050:	693b      	ldr	r3, [r7, #16]
 8001052:	1ad3      	subs	r3, r2, r3
 8001054:	2b02      	cmp	r3, #2
 8001056:	d901      	bls.n	800105c <HAL_RCC_OscConfig+0x190>
          {
            return HAL_TIMEOUT;
 8001058:	2303      	movs	r3, #3
 800105a:	e1a8      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 800105c:	4b2b      	ldr	r3, [pc, #172]	; (800110c <HAL_RCC_OscConfig+0x240>)
 800105e:	681b      	ldr	r3, [r3, #0]
 8001060:	f003 0302 	and.w	r3, r3, #2
 8001064:	2b00      	cmp	r3, #0
 8001066:	d0f0      	beq.n	800104a <HAL_RCC_OscConfig+0x17e>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8001068:	4b28      	ldr	r3, [pc, #160]	; (800110c <HAL_RCC_OscConfig+0x240>)
 800106a:	681b      	ldr	r3, [r3, #0]
 800106c:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 8001070:	687b      	ldr	r3, [r7, #4]
 8001072:	691b      	ldr	r3, [r3, #16]
 8001074:	00db      	lsls	r3, r3, #3
 8001076:	4925      	ldr	r1, [pc, #148]	; (800110c <HAL_RCC_OscConfig+0x240>)
 8001078:	4313      	orrs	r3, r2
 800107a:	600b      	str	r3, [r1, #0]
 800107c:	e015      	b.n	80010aa <HAL_RCC_OscConfig+0x1de>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 800107e:	4b24      	ldr	r3, [pc, #144]	; (8001110 <HAL_RCC_OscConfig+0x244>)
 8001080:	2200      	movs	r2, #0
 8001082:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001084:	f7ff fc92 	bl	80009ac <HAL_GetTick>
 8001088:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 800108a:	e008      	b.n	800109e <HAL_RCC_OscConfig+0x1d2>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 800108c:	f7ff fc8e 	bl	80009ac <HAL_GetTick>
 8001090:	4602      	mov	r2, r0
 8001092:	693b      	ldr	r3, [r7, #16]
 8001094:	1ad3      	subs	r3, r2, r3
 8001096:	2b02      	cmp	r3, #2
 8001098:	d901      	bls.n	800109e <HAL_RCC_OscConfig+0x1d2>
          {
            return HAL_TIMEOUT;
 800109a:	2303      	movs	r3, #3
 800109c:	e187      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 800109e:	4b1b      	ldr	r3, [pc, #108]	; (800110c <HAL_RCC_OscConfig+0x240>)
 80010a0:	681b      	ldr	r3, [r3, #0]
 80010a2:	f003 0302 	and.w	r3, r3, #2
 80010a6:	2b00      	cmp	r3, #0
 80010a8:	d1f0      	bne.n	800108c <HAL_RCC_OscConfig+0x1c0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 80010aa:	687b      	ldr	r3, [r7, #4]
 80010ac:	681b      	ldr	r3, [r3, #0]
 80010ae:	f003 0308 	and.w	r3, r3, #8
 80010b2:	2b00      	cmp	r3, #0
 80010b4:	d036      	beq.n	8001124 <HAL_RCC_OscConfig+0x258>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
 80010b6:	687b      	ldr	r3, [r7, #4]
 80010b8:	695b      	ldr	r3, [r3, #20]
 80010ba:	2b00      	cmp	r3, #0
 80010bc:	d016      	beq.n	80010ec <HAL_RCC_OscConfig+0x220>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 80010be:	4b15      	ldr	r3, [pc, #84]	; (8001114 <HAL_RCC_OscConfig+0x248>)
 80010c0:	2201      	movs	r2, #1
 80010c2:	601a      	str	r2, [r3, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 80010c4:	f7ff fc72 	bl	80009ac <HAL_GetTick>
 80010c8:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 80010ca:	e008      	b.n	80010de <HAL_RCC_OscConfig+0x212>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 80010cc:	f7ff fc6e 	bl	80009ac <HAL_GetTick>
 80010d0:	4602      	mov	r2, r0
 80010d2:	693b      	ldr	r3, [r7, #16]
 80010d4:	1ad3      	subs	r3, r2, r3
 80010d6:	2b02      	cmp	r3, #2
 80010d8:	d901      	bls.n	80010de <HAL_RCC_OscConfig+0x212>
        {
          return HAL_TIMEOUT;
 80010da:	2303      	movs	r3, #3
 80010dc:	e167      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 80010de:	4b0b      	ldr	r3, [pc, #44]	; (800110c <HAL_RCC_OscConfig+0x240>)
 80010e0:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 80010e2:	f003 0302 	and.w	r3, r3, #2
 80010e6:	2b00      	cmp	r3, #0
 80010e8:	d0f0      	beq.n	80010cc <HAL_RCC_OscConfig+0x200>
 80010ea:	e01b      	b.n	8001124 <HAL_RCC_OscConfig+0x258>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 80010ec:	4b09      	ldr	r3, [pc, #36]	; (8001114 <HAL_RCC_OscConfig+0x248>)
 80010ee:	2200      	movs	r2, #0
 80010f0:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 80010f2:	f7ff fc5b 	bl	80009ac <HAL_GetTick>
 80010f6:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 80010f8:	e00e      	b.n	8001118 <HAL_RCC_OscConfig+0x24c>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 80010fa:	f7ff fc57 	bl	80009ac <HAL_GetTick>
 80010fe:	4602      	mov	r2, r0
 8001100:	693b      	ldr	r3, [r7, #16]
 8001102:	1ad3      	subs	r3, r2, r3
 8001104:	2b02      	cmp	r3, #2
 8001106:	d907      	bls.n	8001118 <HAL_RCC_OscConfig+0x24c>
        {
          return HAL_TIMEOUT;
 8001108:	2303      	movs	r3, #3
 800110a:	e150      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
 800110c:	40023800 	.word	0x40023800
 8001110:	42470000 	.word	0x42470000
 8001114:	42470e80 	.word	0x42470e80
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8001118:	4b88      	ldr	r3, [pc, #544]	; (800133c <HAL_RCC_OscConfig+0x470>)
 800111a:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 800111c:	f003 0302 	and.w	r3, r3, #2
 8001120:	2b00      	cmp	r3, #0
 8001122:	d1ea      	bne.n	80010fa <HAL_RCC_OscConfig+0x22e>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8001124:	687b      	ldr	r3, [r7, #4]
 8001126:	681b      	ldr	r3, [r3, #0]
 8001128:	f003 0304 	and.w	r3, r3, #4
 800112c:	2b00      	cmp	r3, #0
 800112e:	f000 8097 	beq.w	8001260 <HAL_RCC_OscConfig+0x394>
  {
    FlagStatus       pwrclkchanged = RESET;
 8001132:	2300      	movs	r3, #0
 8001134:	75fb      	strb	r3, [r7, #23]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8001136:	4b81      	ldr	r3, [pc, #516]	; (800133c <HAL_RCC_OscConfig+0x470>)
 8001138:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800113a:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800113e:	2b00      	cmp	r3, #0
 8001140:	d10f      	bne.n	8001162 <HAL_RCC_OscConfig+0x296>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 8001142:	2300      	movs	r3, #0
 8001144:	60bb      	str	r3, [r7, #8]
 8001146:	4b7d      	ldr	r3, [pc, #500]	; (800133c <HAL_RCC_OscConfig+0x470>)
 8001148:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800114a:	4a7c      	ldr	r2, [pc, #496]	; (800133c <HAL_RCC_OscConfig+0x470>)
 800114c:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8001150:	6413      	str	r3, [r2, #64]	; 0x40
 8001152:	4b7a      	ldr	r3, [pc, #488]	; (800133c <HAL_RCC_OscConfig+0x470>)
 8001154:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001156:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800115a:	60bb      	str	r3, [r7, #8]
 800115c:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 800115e:	2301      	movs	r3, #1
 8001160:	75fb      	strb	r3, [r7, #23]
    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001162:	4b77      	ldr	r3, [pc, #476]	; (8001340 <HAL_RCC_OscConfig+0x474>)
 8001164:	681b      	ldr	r3, [r3, #0]
 8001166:	f403 7380 	and.w	r3, r3, #256	; 0x100
 800116a:	2b00      	cmp	r3, #0
 800116c:	d118      	bne.n	80011a0 <HAL_RCC_OscConfig+0x2d4>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 800116e:	4b74      	ldr	r3, [pc, #464]	; (8001340 <HAL_RCC_OscConfig+0x474>)
 8001170:	681b      	ldr	r3, [r3, #0]
 8001172:	4a73      	ldr	r2, [pc, #460]	; (8001340 <HAL_RCC_OscConfig+0x474>)
 8001174:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8001178:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 800117a:	f7ff fc17 	bl	80009ac <HAL_GetTick>
 800117e:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001180:	e008      	b.n	8001194 <HAL_RCC_OscConfig+0x2c8>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8001182:	f7ff fc13 	bl	80009ac <HAL_GetTick>
 8001186:	4602      	mov	r2, r0
 8001188:	693b      	ldr	r3, [r7, #16]
 800118a:	1ad3      	subs	r3, r2, r3
 800118c:	2b02      	cmp	r3, #2
 800118e:	d901      	bls.n	8001194 <HAL_RCC_OscConfig+0x2c8>
        {
          return HAL_TIMEOUT;
 8001190:	2303      	movs	r3, #3
 8001192:	e10c      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8001194:	4b6a      	ldr	r3, [pc, #424]	; (8001340 <HAL_RCC_OscConfig+0x474>)
 8001196:	681b      	ldr	r3, [r3, #0]
 8001198:	f403 7380 	and.w	r3, r3, #256	; 0x100
 800119c:	2b00      	cmp	r3, #0
 800119e:	d0f0      	beq.n	8001182 <HAL_RCC_OscConfig+0x2b6>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 80011a0:	687b      	ldr	r3, [r7, #4]
 80011a2:	689b      	ldr	r3, [r3, #8]
 80011a4:	2b01      	cmp	r3, #1
 80011a6:	d106      	bne.n	80011b6 <HAL_RCC_OscConfig+0x2ea>
 80011a8:	4b64      	ldr	r3, [pc, #400]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011aa:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80011ac:	4a63      	ldr	r2, [pc, #396]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011ae:	f043 0301 	orr.w	r3, r3, #1
 80011b2:	6713      	str	r3, [r2, #112]	; 0x70
 80011b4:	e01c      	b.n	80011f0 <HAL_RCC_OscConfig+0x324>
 80011b6:	687b      	ldr	r3, [r7, #4]
 80011b8:	689b      	ldr	r3, [r3, #8]
 80011ba:	2b05      	cmp	r3, #5
 80011bc:	d10c      	bne.n	80011d8 <HAL_RCC_OscConfig+0x30c>
 80011be:	4b5f      	ldr	r3, [pc, #380]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011c0:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80011c2:	4a5e      	ldr	r2, [pc, #376]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011c4:	f043 0304 	orr.w	r3, r3, #4
 80011c8:	6713      	str	r3, [r2, #112]	; 0x70
 80011ca:	4b5c      	ldr	r3, [pc, #368]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011cc:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80011ce:	4a5b      	ldr	r2, [pc, #364]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011d0:	f043 0301 	orr.w	r3, r3, #1
 80011d4:	6713      	str	r3, [r2, #112]	; 0x70
 80011d6:	e00b      	b.n	80011f0 <HAL_RCC_OscConfig+0x324>
 80011d8:	4b58      	ldr	r3, [pc, #352]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011da:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80011dc:	4a57      	ldr	r2, [pc, #348]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011de:	f023 0301 	bic.w	r3, r3, #1
 80011e2:	6713      	str	r3, [r2, #112]	; 0x70
 80011e4:	4b55      	ldr	r3, [pc, #340]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011e6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80011e8:	4a54      	ldr	r2, [pc, #336]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80011ea:	f023 0304 	bic.w	r3, r3, #4
 80011ee:	6713      	str	r3, [r2, #112]	; 0x70
    /* Check the LSE State */
    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
 80011f0:	687b      	ldr	r3, [r7, #4]
 80011f2:	689b      	ldr	r3, [r3, #8]
 80011f4:	2b00      	cmp	r3, #0
 80011f6:	d015      	beq.n	8001224 <HAL_RCC_OscConfig+0x358>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 80011f8:	f7ff fbd8 	bl	80009ac <HAL_GetTick>
 80011fc:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 80011fe:	e00a      	b.n	8001216 <HAL_RCC_OscConfig+0x34a>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8001200:	f7ff fbd4 	bl	80009ac <HAL_GetTick>
 8001204:	4602      	mov	r2, r0
 8001206:	693b      	ldr	r3, [r7, #16]
 8001208:	1ad3      	subs	r3, r2, r3
 800120a:	f241 3288 	movw	r2, #5000	; 0x1388
 800120e:	4293      	cmp	r3, r2
 8001210:	d901      	bls.n	8001216 <HAL_RCC_OscConfig+0x34a>
        {
          return HAL_TIMEOUT;
 8001212:	2303      	movs	r3, #3
 8001214:	e0cb      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8001216:	4b49      	ldr	r3, [pc, #292]	; (800133c <HAL_RCC_OscConfig+0x470>)
 8001218:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 800121a:	f003 0302 	and.w	r3, r3, #2
 800121e:	2b00      	cmp	r3, #0
 8001220:	d0ee      	beq.n	8001200 <HAL_RCC_OscConfig+0x334>
 8001222:	e014      	b.n	800124e <HAL_RCC_OscConfig+0x382>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8001224:	f7ff fbc2 	bl	80009ac <HAL_GetTick>
 8001228:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 800122a:	e00a      	b.n	8001242 <HAL_RCC_OscConfig+0x376>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 800122c:	f7ff fbbe 	bl	80009ac <HAL_GetTick>
 8001230:	4602      	mov	r2, r0
 8001232:	693b      	ldr	r3, [r7, #16]
 8001234:	1ad3      	subs	r3, r2, r3
 8001236:	f241 3288 	movw	r2, #5000	; 0x1388
 800123a:	4293      	cmp	r3, r2
 800123c:	d901      	bls.n	8001242 <HAL_RCC_OscConfig+0x376>
        {
          return HAL_TIMEOUT;
 800123e:	2303      	movs	r3, #3
 8001240:	e0b5      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8001242:	4b3e      	ldr	r3, [pc, #248]	; (800133c <HAL_RCC_OscConfig+0x470>)
 8001244:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8001246:	f003 0302 	and.w	r3, r3, #2
 800124a:	2b00      	cmp	r3, #0
 800124c:	d1ee      	bne.n	800122c <HAL_RCC_OscConfig+0x360>
        }
      }
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 800124e:	7dfb      	ldrb	r3, [r7, #23]
 8001250:	2b01      	cmp	r3, #1
 8001252:	d105      	bne.n	8001260 <HAL_RCC_OscConfig+0x394>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8001254:	4b39      	ldr	r3, [pc, #228]	; (800133c <HAL_RCC_OscConfig+0x470>)
 8001256:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001258:	4a38      	ldr	r2, [pc, #224]	; (800133c <HAL_RCC_OscConfig+0x470>)
 800125a:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 800125e:	6413      	str	r3, [r2, #64]	; 0x40
    }
  }
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8001260:	687b      	ldr	r3, [r7, #4]
 8001262:	699b      	ldr	r3, [r3, #24]
 8001264:	2b00      	cmp	r3, #0
 8001266:	f000 80a1 	beq.w	80013ac <HAL_RCC_OscConfig+0x4e0>
  {
    /* Check if the PLL is used as system clock or not */
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
 800126a:	4b34      	ldr	r3, [pc, #208]	; (800133c <HAL_RCC_OscConfig+0x470>)
 800126c:	689b      	ldr	r3, [r3, #8]
 800126e:	f003 030c 	and.w	r3, r3, #12
 8001272:	2b08      	cmp	r3, #8
 8001274:	d05c      	beq.n	8001330 <HAL_RCC_OscConfig+0x464>
    {
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8001276:	687b      	ldr	r3, [r7, #4]
 8001278:	699b      	ldr	r3, [r3, #24]
 800127a:	2b02      	cmp	r3, #2
 800127c:	d141      	bne.n	8001302 <HAL_RCC_OscConfig+0x436>
        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 800127e:	4b31      	ldr	r3, [pc, #196]	; (8001344 <HAL_RCC_OscConfig+0x478>)
 8001280:	2200      	movs	r2, #0
 8001282:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001284:	f7ff fb92 	bl	80009ac <HAL_GetTick>
 8001288:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 800128a:	e008      	b.n	800129e <HAL_RCC_OscConfig+0x3d2>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 800128c:	f7ff fb8e 	bl	80009ac <HAL_GetTick>
 8001290:	4602      	mov	r2, r0
 8001292:	693b      	ldr	r3, [r7, #16]
 8001294:	1ad3      	subs	r3, r2, r3
 8001296:	2b02      	cmp	r3, #2
 8001298:	d901      	bls.n	800129e <HAL_RCC_OscConfig+0x3d2>
          {
            return HAL_TIMEOUT;
 800129a:	2303      	movs	r3, #3
 800129c:	e087      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 800129e:	4b27      	ldr	r3, [pc, #156]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80012a0:	681b      	ldr	r3, [r3, #0]
 80012a2:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 80012a6:	2b00      	cmp	r3, #0
 80012a8:	d1f0      	bne.n	800128c <HAL_RCC_OscConfig+0x3c0>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
 80012aa:	687b      	ldr	r3, [r7, #4]
 80012ac:	69da      	ldr	r2, [r3, #28]
 80012ae:	687b      	ldr	r3, [r7, #4]
 80012b0:	6a1b      	ldr	r3, [r3, #32]
 80012b2:	431a      	orrs	r2, r3
 80012b4:	687b      	ldr	r3, [r7, #4]
 80012b6:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80012b8:	019b      	lsls	r3, r3, #6
 80012ba:	431a      	orrs	r2, r3
 80012bc:	687b      	ldr	r3, [r7, #4]
 80012be:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80012c0:	085b      	lsrs	r3, r3, #1
 80012c2:	3b01      	subs	r3, #1
 80012c4:	041b      	lsls	r3, r3, #16
 80012c6:	431a      	orrs	r2, r3
 80012c8:	687b      	ldr	r3, [r7, #4]
 80012ca:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80012cc:	061b      	lsls	r3, r3, #24
 80012ce:	491b      	ldr	r1, [pc, #108]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80012d0:	4313      	orrs	r3, r2
 80012d2:	604b      	str	r3, [r1, #4]
                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 80012d4:	4b1b      	ldr	r3, [pc, #108]	; (8001344 <HAL_RCC_OscConfig+0x478>)
 80012d6:	2201      	movs	r2, #1
 80012d8:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80012da:	f7ff fb67 	bl	80009ac <HAL_GetTick>
 80012de:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 80012e0:	e008      	b.n	80012f4 <HAL_RCC_OscConfig+0x428>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 80012e2:	f7ff fb63 	bl	80009ac <HAL_GetTick>
 80012e6:	4602      	mov	r2, r0
 80012e8:	693b      	ldr	r3, [r7, #16]
 80012ea:	1ad3      	subs	r3, r2, r3
 80012ec:	2b02      	cmp	r3, #2
 80012ee:	d901      	bls.n	80012f4 <HAL_RCC_OscConfig+0x428>
          {
            return HAL_TIMEOUT;
 80012f0:	2303      	movs	r3, #3
 80012f2:	e05c      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 80012f4:	4b11      	ldr	r3, [pc, #68]	; (800133c <HAL_RCC_OscConfig+0x470>)
 80012f6:	681b      	ldr	r3, [r3, #0]
 80012f8:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 80012fc:	2b00      	cmp	r3, #0
 80012fe:	d0f0      	beq.n	80012e2 <HAL_RCC_OscConfig+0x416>
 8001300:	e054      	b.n	80013ac <HAL_RCC_OscConfig+0x4e0>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8001302:	4b10      	ldr	r3, [pc, #64]	; (8001344 <HAL_RCC_OscConfig+0x478>)
 8001304:	2200      	movs	r2, #0
 8001306:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001308:	f7ff fb50 	bl	80009ac <HAL_GetTick>
 800130c:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 800130e:	e008      	b.n	8001322 <HAL_RCC_OscConfig+0x456>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8001310:	f7ff fb4c 	bl	80009ac <HAL_GetTick>
 8001314:	4602      	mov	r2, r0
 8001316:	693b      	ldr	r3, [r7, #16]
 8001318:	1ad3      	subs	r3, r2, r3
 800131a:	2b02      	cmp	r3, #2
 800131c:	d901      	bls.n	8001322 <HAL_RCC_OscConfig+0x456>
          {
            return HAL_TIMEOUT;
 800131e:	2303      	movs	r3, #3
 8001320:	e045      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8001322:	4b06      	ldr	r3, [pc, #24]	; (800133c <HAL_RCC_OscConfig+0x470>)
 8001324:	681b      	ldr	r3, [r3, #0]
 8001326:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 800132a:	2b00      	cmp	r3, #0
 800132c:	d1f0      	bne.n	8001310 <HAL_RCC_OscConfig+0x444>
 800132e:	e03d      	b.n	80013ac <HAL_RCC_OscConfig+0x4e0>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 8001330:	687b      	ldr	r3, [r7, #4]
 8001332:	699b      	ldr	r3, [r3, #24]
 8001334:	2b01      	cmp	r3, #1
 8001336:	d107      	bne.n	8001348 <HAL_RCC_OscConfig+0x47c>
      {
        return HAL_ERROR;
 8001338:	2301      	movs	r3, #1
 800133a:	e038      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
 800133c:	40023800 	.word	0x40023800
 8001340:	40007000 	.word	0x40007000
 8001344:	42470060 	.word	0x42470060
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->PLLCFGR;
 8001348:	4b1b      	ldr	r3, [pc, #108]	; (80013b8 <HAL_RCC_OscConfig+0x4ec>)
 800134a:	685b      	ldr	r3, [r3, #4]
 800134c:	60fb      	str	r3, [r7, #12]
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 800134e:	687b      	ldr	r3, [r7, #4]
 8001350:	699b      	ldr	r3, [r3, #24]
 8001352:	2b01      	cmp	r3, #1
 8001354:	d028      	beq.n	80013a8 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8001356:	68fb      	ldr	r3, [r7, #12]
 8001358:	f403 0280 	and.w	r2, r3, #4194304	; 0x400000
 800135c:	687b      	ldr	r3, [r7, #4]
 800135e:	69db      	ldr	r3, [r3, #28]
        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 8001360:	429a      	cmp	r2, r3
 8001362:	d121      	bne.n	80013a8 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
 8001364:	68fb      	ldr	r3, [r7, #12]
 8001366:	f003 023f 	and.w	r2, r3, #63	; 0x3f
 800136a:	687b      	ldr	r3, [r7, #4]
 800136c:	6a1b      	ldr	r3, [r3, #32]
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 800136e:	429a      	cmp	r2, r3
 8001370:	d11a      	bne.n	80013a8 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
 8001372:	68fa      	ldr	r2, [r7, #12]
 8001374:	f647 73c0 	movw	r3, #32704	; 0x7fc0
 8001378:	4013      	ands	r3, r2
 800137a:	687a      	ldr	r2, [r7, #4]
 800137c:	6a52      	ldr	r2, [r2, #36]	; 0x24
 800137e:	0192      	lsls	r2, r2, #6
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
 8001380:	4293      	cmp	r3, r2
 8001382:	d111      	bne.n	80013a8 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
 8001384:	68fb      	ldr	r3, [r7, #12]
 8001386:	f403 3240 	and.w	r2, r3, #196608	; 0x30000
 800138a:	687b      	ldr	r3, [r7, #4]
 800138c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800138e:	085b      	lsrs	r3, r3, #1
 8001390:	3b01      	subs	r3, #1
 8001392:	041b      	lsls	r3, r3, #16
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
 8001394:	429a      	cmp	r2, r3
 8001396:	d107      	bne.n	80013a8 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
 8001398:	68fb      	ldr	r3, [r7, #12]
 800139a:	f003 6270 	and.w	r2, r3, #251658240	; 0xf000000
 800139e:	687b      	ldr	r3, [r7, #4]
 80013a0:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80013a2:	061b      	lsls	r3, r3, #24
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
 80013a4:	429a      	cmp	r2, r3
 80013a6:	d001      	beq.n	80013ac <HAL_RCC_OscConfig+0x4e0>
#endif
        {
          return HAL_ERROR;
 80013a8:	2301      	movs	r3, #1
 80013aa:	e000      	b.n	80013ae <HAL_RCC_OscConfig+0x4e2>
        }
      }
    }
  }
  return HAL_OK;
 80013ac:	2300      	movs	r3, #0
}
 80013ae:	4618      	mov	r0, r3
 80013b0:	3718      	adds	r7, #24
 80013b2:	46bd      	mov	sp, r7
 80013b4:	bd80      	pop	{r7, pc}
 80013b6:	bf00      	nop
 80013b8:	40023800 	.word	0x40023800

080013bc <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 80013bc:	b580      	push	{r7, lr}
 80013be:	b084      	sub	sp, #16
 80013c0:	af00      	add	r7, sp, #0
 80013c2:	6078      	str	r0, [r7, #4]
 80013c4:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;

  /* Check Null pointer */
  if(RCC_ClkInitStruct == NULL)
 80013c6:	687b      	ldr	r3, [r7, #4]
 80013c8:	2b00      	cmp	r3, #0
 80013ca:	d101      	bne.n	80013d0 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 80013cc:	2301      	movs	r3, #1
 80013ce:	e0cc      	b.n	800156a <HAL_RCC_ClockConfig+0x1ae>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 80013d0:	4b68      	ldr	r3, [pc, #416]	; (8001574 <HAL_RCC_ClockConfig+0x1b8>)
 80013d2:	681b      	ldr	r3, [r3, #0]
 80013d4:	f003 0307 	and.w	r3, r3, #7
 80013d8:	683a      	ldr	r2, [r7, #0]
 80013da:	429a      	cmp	r2, r3
 80013dc:	d90c      	bls.n	80013f8 <HAL_RCC_ClockConfig+0x3c>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 80013de:	4b65      	ldr	r3, [pc, #404]	; (8001574 <HAL_RCC_ClockConfig+0x1b8>)
 80013e0:	683a      	ldr	r2, [r7, #0]
 80013e2:	b2d2      	uxtb	r2, r2
 80013e4:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 80013e6:	4b63      	ldr	r3, [pc, #396]	; (8001574 <HAL_RCC_ClockConfig+0x1b8>)
 80013e8:	681b      	ldr	r3, [r3, #0]
 80013ea:	f003 0307 	and.w	r3, r3, #7
 80013ee:	683a      	ldr	r2, [r7, #0]
 80013f0:	429a      	cmp	r2, r3
 80013f2:	d001      	beq.n	80013f8 <HAL_RCC_ClockConfig+0x3c>
    {
      return HAL_ERROR;
 80013f4:	2301      	movs	r3, #1
 80013f6:	e0b8      	b.n	800156a <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 80013f8:	687b      	ldr	r3, [r7, #4]
 80013fa:	681b      	ldr	r3, [r3, #0]
 80013fc:	f003 0302 	and.w	r3, r3, #2
 8001400:	2b00      	cmp	r3, #0
 8001402:	d020      	beq.n	8001446 <HAL_RCC_ClockConfig+0x8a>
  {
    /* Set the highest APBx dividers in order to ensure that we do not go through
       a non-spec phase whatever we decrease or increase HCLK. */
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001404:	687b      	ldr	r3, [r7, #4]
 8001406:	681b      	ldr	r3, [r3, #0]
 8001408:	f003 0304 	and.w	r3, r3, #4
 800140c:	2b00      	cmp	r3, #0
 800140e:	d005      	beq.n	800141c <HAL_RCC_ClockConfig+0x60>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8001410:	4b59      	ldr	r3, [pc, #356]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 8001412:	689b      	ldr	r3, [r3, #8]
 8001414:	4a58      	ldr	r2, [pc, #352]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 8001416:	f443 53e0 	orr.w	r3, r3, #7168	; 0x1c00
 800141a:	6093      	str	r3, [r2, #8]
    }

    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 800141c:	687b      	ldr	r3, [r7, #4]
 800141e:	681b      	ldr	r3, [r3, #0]
 8001420:	f003 0308 	and.w	r3, r3, #8
 8001424:	2b00      	cmp	r3, #0
 8001426:	d005      	beq.n	8001434 <HAL_RCC_ClockConfig+0x78>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8001428:	4b53      	ldr	r3, [pc, #332]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 800142a:	689b      	ldr	r3, [r3, #8]
 800142c:	4a52      	ldr	r2, [pc, #328]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 800142e:	f443 4360 	orr.w	r3, r3, #57344	; 0xe000
 8001432:	6093      	str	r3, [r2, #8]
    }

    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8001434:	4b50      	ldr	r3, [pc, #320]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 8001436:	689b      	ldr	r3, [r3, #8]
 8001438:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 800143c:	687b      	ldr	r3, [r7, #4]
 800143e:	689b      	ldr	r3, [r3, #8]
 8001440:	494d      	ldr	r1, [pc, #308]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 8001442:	4313      	orrs	r3, r2
 8001444:	608b      	str	r3, [r1, #8]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8001446:	687b      	ldr	r3, [r7, #4]
 8001448:	681b      	ldr	r3, [r3, #0]
 800144a:	f003 0301 	and.w	r3, r3, #1
 800144e:	2b00      	cmp	r3, #0
 8001450:	d044      	beq.n	80014dc <HAL_RCC_ClockConfig+0x120>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 8001452:	687b      	ldr	r3, [r7, #4]
 8001454:	685b      	ldr	r3, [r3, #4]
 8001456:	2b01      	cmp	r3, #1
 8001458:	d107      	bne.n	800146a <HAL_RCC_ClockConfig+0xae>
    {
      /* Check the HSE ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 800145a:	4b47      	ldr	r3, [pc, #284]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 800145c:	681b      	ldr	r3, [r3, #0]
 800145e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001462:	2b00      	cmp	r3, #0
 8001464:	d119      	bne.n	800149a <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8001466:	2301      	movs	r3, #1
 8001468:	e07f      	b.n	800156a <HAL_RCC_ClockConfig+0x1ae>
      }
    }
    /* PLL is selected as System Clock Source */
    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 800146a:	687b      	ldr	r3, [r7, #4]
 800146c:	685b      	ldr	r3, [r3, #4]
 800146e:	2b02      	cmp	r3, #2
 8001470:	d003      	beq.n	800147a <HAL_RCC_ClockConfig+0xbe>
            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
 8001472:	687b      	ldr	r3, [r7, #4]
 8001474:	685b      	ldr	r3, [r3, #4]
    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 8001476:	2b03      	cmp	r3, #3
 8001478:	d107      	bne.n	800148a <HAL_RCC_ClockConfig+0xce>
    {
      /* Check the PLL ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 800147a:	4b3f      	ldr	r3, [pc, #252]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 800147c:	681b      	ldr	r3, [r3, #0]
 800147e:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8001482:	2b00      	cmp	r3, #0
 8001484:	d109      	bne.n	800149a <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8001486:	2301      	movs	r3, #1
 8001488:	e06f      	b.n	800156a <HAL_RCC_ClockConfig+0x1ae>
    }
    /* HSI is selected as System Clock Source */
    else
    {
      /* Check the HSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 800148a:	4b3b      	ldr	r3, [pc, #236]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 800148c:	681b      	ldr	r3, [r3, #0]
 800148e:	f003 0302 	and.w	r3, r3, #2
 8001492:	2b00      	cmp	r3, #0
 8001494:	d101      	bne.n	800149a <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8001496:	2301      	movs	r3, #1
 8001498:	e067      	b.n	800156a <HAL_RCC_ClockConfig+0x1ae>
      }
    }

    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 800149a:	4b37      	ldr	r3, [pc, #220]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 800149c:	689b      	ldr	r3, [r3, #8]
 800149e:	f023 0203 	bic.w	r2, r3, #3
 80014a2:	687b      	ldr	r3, [r7, #4]
 80014a4:	685b      	ldr	r3, [r3, #4]
 80014a6:	4934      	ldr	r1, [pc, #208]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 80014a8:	4313      	orrs	r3, r2
 80014aa:	608b      	str	r3, [r1, #8]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 80014ac:	f7ff fa7e 	bl	80009ac <HAL_GetTick>
 80014b0:	60f8      	str	r0, [r7, #12]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 80014b2:	e00a      	b.n	80014ca <HAL_RCC_ClockConfig+0x10e>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 80014b4:	f7ff fa7a 	bl	80009ac <HAL_GetTick>
 80014b8:	4602      	mov	r2, r0
 80014ba:	68fb      	ldr	r3, [r7, #12]
 80014bc:	1ad3      	subs	r3, r2, r3
 80014be:	f241 3288 	movw	r2, #5000	; 0x1388
 80014c2:	4293      	cmp	r3, r2
 80014c4:	d901      	bls.n	80014ca <HAL_RCC_ClockConfig+0x10e>
      {
        return HAL_TIMEOUT;
 80014c6:	2303      	movs	r3, #3
 80014c8:	e04f      	b.n	800156a <HAL_RCC_ClockConfig+0x1ae>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 80014ca:	4b2b      	ldr	r3, [pc, #172]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 80014cc:	689b      	ldr	r3, [r3, #8]
 80014ce:	f003 020c 	and.w	r2, r3, #12
 80014d2:	687b      	ldr	r3, [r7, #4]
 80014d4:	685b      	ldr	r3, [r3, #4]
 80014d6:	009b      	lsls	r3, r3, #2
 80014d8:	429a      	cmp	r2, r3
 80014da:	d1eb      	bne.n	80014b4 <HAL_RCC_ClockConfig+0xf8>
      }
    }
  }

  /* Decreasing the number of wait states because of lower CPU frequency */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 80014dc:	4b25      	ldr	r3, [pc, #148]	; (8001574 <HAL_RCC_ClockConfig+0x1b8>)
 80014de:	681b      	ldr	r3, [r3, #0]
 80014e0:	f003 0307 	and.w	r3, r3, #7
 80014e4:	683a      	ldr	r2, [r7, #0]
 80014e6:	429a      	cmp	r2, r3
 80014e8:	d20c      	bcs.n	8001504 <HAL_RCC_ClockConfig+0x148>
  {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 80014ea:	4b22      	ldr	r3, [pc, #136]	; (8001574 <HAL_RCC_ClockConfig+0x1b8>)
 80014ec:	683a      	ldr	r2, [r7, #0]
 80014ee:	b2d2      	uxtb	r2, r2
 80014f0:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 80014f2:	4b20      	ldr	r3, [pc, #128]	; (8001574 <HAL_RCC_ClockConfig+0x1b8>)
 80014f4:	681b      	ldr	r3, [r3, #0]
 80014f6:	f003 0307 	and.w	r3, r3, #7
 80014fa:	683a      	ldr	r2, [r7, #0]
 80014fc:	429a      	cmp	r2, r3
 80014fe:	d001      	beq.n	8001504 <HAL_RCC_ClockConfig+0x148>
    {
      return HAL_ERROR;
 8001500:	2301      	movs	r3, #1
 8001502:	e032      	b.n	800156a <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 8001504:	687b      	ldr	r3, [r7, #4]
 8001506:	681b      	ldr	r3, [r3, #0]
 8001508:	f003 0304 	and.w	r3, r3, #4
 800150c:	2b00      	cmp	r3, #0
 800150e:	d008      	beq.n	8001522 <HAL_RCC_ClockConfig+0x166>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8001510:	4b19      	ldr	r3, [pc, #100]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 8001512:	689b      	ldr	r3, [r3, #8]
 8001514:	f423 52e0 	bic.w	r2, r3, #7168	; 0x1c00
 8001518:	687b      	ldr	r3, [r7, #4]
 800151a:	68db      	ldr	r3, [r3, #12]
 800151c:	4916      	ldr	r1, [pc, #88]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 800151e:	4313      	orrs	r3, r2
 8001520:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8001522:	687b      	ldr	r3, [r7, #4]
 8001524:	681b      	ldr	r3, [r3, #0]
 8001526:	f003 0308 	and.w	r3, r3, #8
 800152a:	2b00      	cmp	r3, #0
 800152c:	d009      	beq.n	8001542 <HAL_RCC_ClockConfig+0x186>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 800152e:	4b12      	ldr	r3, [pc, #72]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 8001530:	689b      	ldr	r3, [r3, #8]
 8001532:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 8001536:	687b      	ldr	r3, [r7, #4]
 8001538:	691b      	ldr	r3, [r3, #16]
 800153a:	00db      	lsls	r3, r3, #3
 800153c:	490e      	ldr	r1, [pc, #56]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 800153e:	4313      	orrs	r3, r2
 8001540:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 8001542:	f000 f821 	bl	8001588 <HAL_RCC_GetSysClockFreq>
 8001546:	4602      	mov	r2, r0
 8001548:	4b0b      	ldr	r3, [pc, #44]	; (8001578 <HAL_RCC_ClockConfig+0x1bc>)
 800154a:	689b      	ldr	r3, [r3, #8]
 800154c:	091b      	lsrs	r3, r3, #4
 800154e:	f003 030f 	and.w	r3, r3, #15
 8001552:	490a      	ldr	r1, [pc, #40]	; (800157c <HAL_RCC_ClockConfig+0x1c0>)
 8001554:	5ccb      	ldrb	r3, [r1, r3]
 8001556:	fa22 f303 	lsr.w	r3, r2, r3
 800155a:	4a09      	ldr	r2, [pc, #36]	; (8001580 <HAL_RCC_ClockConfig+0x1c4>)
 800155c:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings */
  HAL_InitTick (uwTickPrio);
 800155e:	4b09      	ldr	r3, [pc, #36]	; (8001584 <HAL_RCC_ClockConfig+0x1c8>)
 8001560:	681b      	ldr	r3, [r3, #0]
 8001562:	4618      	mov	r0, r3
 8001564:	f7ff f9de 	bl	8000924 <HAL_InitTick>

  return HAL_OK;
 8001568:	2300      	movs	r3, #0
}
 800156a:	4618      	mov	r0, r3
 800156c:	3710      	adds	r7, #16
 800156e:	46bd      	mov	sp, r7
 8001570:	bd80      	pop	{r7, pc}
 8001572:	bf00      	nop
 8001574:	40023c00 	.word	0x40023c00
 8001578:	40023800 	.word	0x40023800
 800157c:	08001ff8 	.word	0x08001ff8
 8001580:	20000000 	.word	0x20000000
 8001584:	20000004 	.word	0x20000004

08001588 <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8001588:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 800158c:	b094      	sub	sp, #80	; 0x50
 800158e:	af00      	add	r7, sp, #0
  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
 8001590:	2300      	movs	r3, #0
 8001592:	647b      	str	r3, [r7, #68]	; 0x44
 8001594:	2300      	movs	r3, #0
 8001596:	64fb      	str	r3, [r7, #76]	; 0x4c
 8001598:	2300      	movs	r3, #0
 800159a:	643b      	str	r3, [r7, #64]	; 0x40
  uint32_t sysclockfreq = 0U;
 800159c:	2300      	movs	r3, #0
 800159e:	64bb      	str	r3, [r7, #72]	; 0x48

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (RCC->CFGR & RCC_CFGR_SWS)
 80015a0:	4b79      	ldr	r3, [pc, #484]	; (8001788 <HAL_RCC_GetSysClockFreq+0x200>)
 80015a2:	689b      	ldr	r3, [r3, #8]
 80015a4:	f003 030c 	and.w	r3, r3, #12
 80015a8:	2b08      	cmp	r3, #8
 80015aa:	d00d      	beq.n	80015c8 <HAL_RCC_GetSysClockFreq+0x40>
 80015ac:	2b08      	cmp	r3, #8
 80015ae:	f200 80e1 	bhi.w	8001774 <HAL_RCC_GetSysClockFreq+0x1ec>
 80015b2:	2b00      	cmp	r3, #0
 80015b4:	d002      	beq.n	80015bc <HAL_RCC_GetSysClockFreq+0x34>
 80015b6:	2b04      	cmp	r3, #4
 80015b8:	d003      	beq.n	80015c2 <HAL_RCC_GetSysClockFreq+0x3a>
 80015ba:	e0db      	b.n	8001774 <HAL_RCC_GetSysClockFreq+0x1ec>
  {
    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
    {
      sysclockfreq = HSI_VALUE;
 80015bc:	4b73      	ldr	r3, [pc, #460]	; (800178c <HAL_RCC_GetSysClockFreq+0x204>)
 80015be:	64bb      	str	r3, [r7, #72]	; 0x48
       break;
 80015c0:	e0db      	b.n	800177a <HAL_RCC_GetSysClockFreq+0x1f2>
    }
    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
    {
      sysclockfreq = HSE_VALUE;
 80015c2:	4b73      	ldr	r3, [pc, #460]	; (8001790 <HAL_RCC_GetSysClockFreq+0x208>)
 80015c4:	64bb      	str	r3, [r7, #72]	; 0x48
      break;
 80015c6:	e0d8      	b.n	800177a <HAL_RCC_GetSysClockFreq+0x1f2>
    }
    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
    {
      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
      SYSCLK = PLL_VCO / PLLP */
      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 80015c8:	4b6f      	ldr	r3, [pc, #444]	; (8001788 <HAL_RCC_GetSysClockFreq+0x200>)
 80015ca:	685b      	ldr	r3, [r3, #4]
 80015cc:	f003 033f 	and.w	r3, r3, #63	; 0x3f
 80015d0:	647b      	str	r3, [r7, #68]	; 0x44
      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
 80015d2:	4b6d      	ldr	r3, [pc, #436]	; (8001788 <HAL_RCC_GetSysClockFreq+0x200>)
 80015d4:	685b      	ldr	r3, [r3, #4]
 80015d6:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 80015da:	2b00      	cmp	r3, #0
 80015dc:	d063      	beq.n	80016a6 <HAL_RCC_GetSysClockFreq+0x11e>
      {
        /* HSE used as PLL clock source */
        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 80015de:	4b6a      	ldr	r3, [pc, #424]	; (8001788 <HAL_RCC_GetSysClockFreq+0x200>)
 80015e0:	685b      	ldr	r3, [r3, #4]
 80015e2:	099b      	lsrs	r3, r3, #6
 80015e4:	2200      	movs	r2, #0
 80015e6:	63bb      	str	r3, [r7, #56]	; 0x38
 80015e8:	63fa      	str	r2, [r7, #60]	; 0x3c
 80015ea:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 80015ec:	f3c3 0308 	ubfx	r3, r3, #0, #9
 80015f0:	633b      	str	r3, [r7, #48]	; 0x30
 80015f2:	2300      	movs	r3, #0
 80015f4:	637b      	str	r3, [r7, #52]	; 0x34
 80015f6:	e9d7 450c 	ldrd	r4, r5, [r7, #48]	; 0x30
 80015fa:	4622      	mov	r2, r4
 80015fc:	462b      	mov	r3, r5
 80015fe:	f04f 0000 	mov.w	r0, #0
 8001602:	f04f 0100 	mov.w	r1, #0
 8001606:	0159      	lsls	r1, r3, #5
 8001608:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
 800160c:	0150      	lsls	r0, r2, #5
 800160e:	4602      	mov	r2, r0
 8001610:	460b      	mov	r3, r1
 8001612:	4621      	mov	r1, r4
 8001614:	1a51      	subs	r1, r2, r1
 8001616:	6139      	str	r1, [r7, #16]
 8001618:	4629      	mov	r1, r5
 800161a:	eb63 0301 	sbc.w	r3, r3, r1
 800161e:	617b      	str	r3, [r7, #20]
 8001620:	f04f 0200 	mov.w	r2, #0
 8001624:	f04f 0300 	mov.w	r3, #0
 8001628:	e9d7 ab04 	ldrd	sl, fp, [r7, #16]
 800162c:	4659      	mov	r1, fp
 800162e:	018b      	lsls	r3, r1, #6
 8001630:	4651      	mov	r1, sl
 8001632:	ea43 6391 	orr.w	r3, r3, r1, lsr #26
 8001636:	4651      	mov	r1, sl
 8001638:	018a      	lsls	r2, r1, #6
 800163a:	4651      	mov	r1, sl
 800163c:	ebb2 0801 	subs.w	r8, r2, r1
 8001640:	4659      	mov	r1, fp
 8001642:	eb63 0901 	sbc.w	r9, r3, r1
 8001646:	f04f 0200 	mov.w	r2, #0
 800164a:	f04f 0300 	mov.w	r3, #0
 800164e:	ea4f 03c9 	mov.w	r3, r9, lsl #3
 8001652:	ea43 7358 	orr.w	r3, r3, r8, lsr #29
 8001656:	ea4f 02c8 	mov.w	r2, r8, lsl #3
 800165a:	4690      	mov	r8, r2
 800165c:	4699      	mov	r9, r3
 800165e:	4623      	mov	r3, r4
 8001660:	eb18 0303 	adds.w	r3, r8, r3
 8001664:	60bb      	str	r3, [r7, #8]
 8001666:	462b      	mov	r3, r5
 8001668:	eb49 0303 	adc.w	r3, r9, r3
 800166c:	60fb      	str	r3, [r7, #12]
 800166e:	f04f 0200 	mov.w	r2, #0
 8001672:	f04f 0300 	mov.w	r3, #0
 8001676:	e9d7 4502 	ldrd	r4, r5, [r7, #8]
 800167a:	4629      	mov	r1, r5
 800167c:	024b      	lsls	r3, r1, #9
 800167e:	4621      	mov	r1, r4
 8001680:	ea43 53d1 	orr.w	r3, r3, r1, lsr #23
 8001684:	4621      	mov	r1, r4
 8001686:	024a      	lsls	r2, r1, #9
 8001688:	4610      	mov	r0, r2
 800168a:	4619      	mov	r1, r3
 800168c:	6c7b      	ldr	r3, [r7, #68]	; 0x44
 800168e:	2200      	movs	r2, #0
 8001690:	62bb      	str	r3, [r7, #40]	; 0x28
 8001692:	62fa      	str	r2, [r7, #44]	; 0x2c
 8001694:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	; 0x28
 8001698:	f7fe fd9e 	bl	80001d8 <__aeabi_uldivmod>
 800169c:	4602      	mov	r2, r0
 800169e:	460b      	mov	r3, r1
 80016a0:	4613      	mov	r3, r2
 80016a2:	64fb      	str	r3, [r7, #76]	; 0x4c
 80016a4:	e058      	b.n	8001758 <HAL_RCC_GetSysClockFreq+0x1d0>
      }
      else
      {
        /* HSI used as PLL clock source */
        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 80016a6:	4b38      	ldr	r3, [pc, #224]	; (8001788 <HAL_RCC_GetSysClockFreq+0x200>)
 80016a8:	685b      	ldr	r3, [r3, #4]
 80016aa:	099b      	lsrs	r3, r3, #6
 80016ac:	2200      	movs	r2, #0
 80016ae:	4618      	mov	r0, r3
 80016b0:	4611      	mov	r1, r2
 80016b2:	f3c0 0308 	ubfx	r3, r0, #0, #9
 80016b6:	623b      	str	r3, [r7, #32]
 80016b8:	2300      	movs	r3, #0
 80016ba:	627b      	str	r3, [r7, #36]	; 0x24
 80016bc:	e9d7 8908 	ldrd	r8, r9, [r7, #32]
 80016c0:	4642      	mov	r2, r8
 80016c2:	464b      	mov	r3, r9
 80016c4:	f04f 0000 	mov.w	r0, #0
 80016c8:	f04f 0100 	mov.w	r1, #0
 80016cc:	0159      	lsls	r1, r3, #5
 80016ce:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
 80016d2:	0150      	lsls	r0, r2, #5
 80016d4:	4602      	mov	r2, r0
 80016d6:	460b      	mov	r3, r1
 80016d8:	4641      	mov	r1, r8
 80016da:	ebb2 0a01 	subs.w	sl, r2, r1
 80016de:	4649      	mov	r1, r9
 80016e0:	eb63 0b01 	sbc.w	fp, r3, r1
 80016e4:	f04f 0200 	mov.w	r2, #0
 80016e8:	f04f 0300 	mov.w	r3, #0
 80016ec:	ea4f 138b 	mov.w	r3, fp, lsl #6
 80016f0:	ea43 639a 	orr.w	r3, r3, sl, lsr #26
 80016f4:	ea4f 128a 	mov.w	r2, sl, lsl #6
 80016f8:	ebb2 040a 	subs.w	r4, r2, sl
 80016fc:	eb63 050b 	sbc.w	r5, r3, fp
 8001700:	f04f 0200 	mov.w	r2, #0
 8001704:	f04f 0300 	mov.w	r3, #0
 8001708:	00eb      	lsls	r3, r5, #3
 800170a:	ea43 7354 	orr.w	r3, r3, r4, lsr #29
 800170e:	00e2      	lsls	r2, r4, #3
 8001710:	4614      	mov	r4, r2
 8001712:	461d      	mov	r5, r3
 8001714:	4643      	mov	r3, r8
 8001716:	18e3      	adds	r3, r4, r3
 8001718:	603b      	str	r3, [r7, #0]
 800171a:	464b      	mov	r3, r9
 800171c:	eb45 0303 	adc.w	r3, r5, r3
 8001720:	607b      	str	r3, [r7, #4]
 8001722:	f04f 0200 	mov.w	r2, #0
 8001726:	f04f 0300 	mov.w	r3, #0
 800172a:	e9d7 4500 	ldrd	r4, r5, [r7]
 800172e:	4629      	mov	r1, r5
 8001730:	028b      	lsls	r3, r1, #10
 8001732:	4621      	mov	r1, r4
 8001734:	ea43 5391 	orr.w	r3, r3, r1, lsr #22
 8001738:	4621      	mov	r1, r4
 800173a:	028a      	lsls	r2, r1, #10
 800173c:	4610      	mov	r0, r2
 800173e:	4619      	mov	r1, r3
 8001740:	6c7b      	ldr	r3, [r7, #68]	; 0x44
 8001742:	2200      	movs	r2, #0
 8001744:	61bb      	str	r3, [r7, #24]
 8001746:	61fa      	str	r2, [r7, #28]
 8001748:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
 800174c:	f7fe fd44 	bl	80001d8 <__aeabi_uldivmod>
 8001750:	4602      	mov	r2, r0
 8001752:	460b      	mov	r3, r1
 8001754:	4613      	mov	r3, r2
 8001756:	64fb      	str	r3, [r7, #76]	; 0x4c
      }
      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
 8001758:	4b0b      	ldr	r3, [pc, #44]	; (8001788 <HAL_RCC_GetSysClockFreq+0x200>)
 800175a:	685b      	ldr	r3, [r3, #4]
 800175c:	0c1b      	lsrs	r3, r3, #16
 800175e:	f003 0303 	and.w	r3, r3, #3
 8001762:	3301      	adds	r3, #1
 8001764:	005b      	lsls	r3, r3, #1
 8001766:	643b      	str	r3, [r7, #64]	; 0x40

      sysclockfreq = pllvco/pllp;
 8001768:	6cfa      	ldr	r2, [r7, #76]	; 0x4c
 800176a:	6c3b      	ldr	r3, [r7, #64]	; 0x40
 800176c:	fbb2 f3f3 	udiv	r3, r2, r3
 8001770:	64bb      	str	r3, [r7, #72]	; 0x48
      break;
 8001772:	e002      	b.n	800177a <HAL_RCC_GetSysClockFreq+0x1f2>
    }
    default:
    {
      sysclockfreq = HSI_VALUE;
 8001774:	4b05      	ldr	r3, [pc, #20]	; (800178c <HAL_RCC_GetSysClockFreq+0x204>)
 8001776:	64bb      	str	r3, [r7, #72]	; 0x48
      break;
 8001778:	bf00      	nop
    }
  }
  return sysclockfreq;
 800177a:	6cbb      	ldr	r3, [r7, #72]	; 0x48
}
 800177c:	4618      	mov	r0, r3
 800177e:	3750      	adds	r7, #80	; 0x50
 8001780:	46bd      	mov	sp, r7
 8001782:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 8001786:	bf00      	nop
 8001788:	40023800 	.word	0x40023800
 800178c:	00f42400 	.word	0x00f42400
 8001790:	007a1200 	.word	0x007a1200

08001794 <HAL_RCC_GetHCLKFreq>:
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 8001794:	b480      	push	{r7}
 8001796:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 8001798:	4b03      	ldr	r3, [pc, #12]	; (80017a8 <HAL_RCC_GetHCLKFreq+0x14>)
 800179a:	681b      	ldr	r3, [r3, #0]
}
 800179c:	4618      	mov	r0, r3
 800179e:	46bd      	mov	sp, r7
 80017a0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80017a4:	4770      	bx	lr
 80017a6:	bf00      	nop
 80017a8:	20000000 	.word	0x20000000

080017ac <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 80017ac:	b580      	push	{r7, lr}
 80017ae:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
 80017b0:	f7ff fff0 	bl	8001794 <HAL_RCC_GetHCLKFreq>
 80017b4:	4602      	mov	r2, r0
 80017b6:	4b05      	ldr	r3, [pc, #20]	; (80017cc <HAL_RCC_GetPCLK1Freq+0x20>)
 80017b8:	689b      	ldr	r3, [r3, #8]
 80017ba:	0a9b      	lsrs	r3, r3, #10
 80017bc:	f003 0307 	and.w	r3, r3, #7
 80017c0:	4903      	ldr	r1, [pc, #12]	; (80017d0 <HAL_RCC_GetPCLK1Freq+0x24>)
 80017c2:	5ccb      	ldrb	r3, [r1, r3]
 80017c4:	fa22 f303 	lsr.w	r3, r2, r3
}
 80017c8:	4618      	mov	r0, r3
 80017ca:	bd80      	pop	{r7, pc}
 80017cc:	40023800 	.word	0x40023800
 80017d0:	08002008 	.word	0x08002008

080017d4 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 80017d4:	b580      	push	{r7, lr}
 80017d6:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
 80017d8:	f7ff ffdc 	bl	8001794 <HAL_RCC_GetHCLKFreq>
 80017dc:	4602      	mov	r2, r0
 80017de:	4b05      	ldr	r3, [pc, #20]	; (80017f4 <HAL_RCC_GetPCLK2Freq+0x20>)
 80017e0:	689b      	ldr	r3, [r3, #8]
 80017e2:	0b5b      	lsrs	r3, r3, #13
 80017e4:	f003 0307 	and.w	r3, r3, #7
 80017e8:	4903      	ldr	r1, [pc, #12]	; (80017f8 <HAL_RCC_GetPCLK2Freq+0x24>)
 80017ea:	5ccb      	ldrb	r3, [r1, r3]
 80017ec:	fa22 f303 	lsr.w	r3, r2, r3
}
 80017f0:	4618      	mov	r0, r3
 80017f2:	bd80      	pop	{r7, pc}
 80017f4:	40023800 	.word	0x40023800
 80017f8:	08002008 	.word	0x08002008

080017fc <HAL_UART_Init>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 80017fc:	b580      	push	{r7, lr}
 80017fe:	b082      	sub	sp, #8
 8001800:	af00      	add	r7, sp, #0
 8001802:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 8001804:	687b      	ldr	r3, [r7, #4]
 8001806:	2b00      	cmp	r3, #0
 8001808:	d101      	bne.n	800180e <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 800180a:	2301      	movs	r3, #1
 800180c:	e03f      	b.n	800188e <HAL_UART_Init+0x92>
    assert_param(IS_UART_INSTANCE(huart->Instance));
  }
  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));

  if (huart->gState == HAL_UART_STATE_RESET)
 800180e:	687b      	ldr	r3, [r7, #4]
 8001810:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8001814:	b2db      	uxtb	r3, r3
 8001816:	2b00      	cmp	r3, #0
 8001818:	d106      	bne.n	8001828 <HAL_UART_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 800181a:	687b      	ldr	r3, [r7, #4]
 800181c:	2200      	movs	r2, #0
 800181e:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 8001822:	6878      	ldr	r0, [r7, #4]
 8001824:	f7fe ffae 	bl	8000784 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 8001828:	687b      	ldr	r3, [r7, #4]
 800182a:	2224      	movs	r2, #36	; 0x24
 800182c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Disable the peripheral */
  __HAL_UART_DISABLE(huart);
 8001830:	687b      	ldr	r3, [r7, #4]
 8001832:	681b      	ldr	r3, [r3, #0]
 8001834:	68da      	ldr	r2, [r3, #12]
 8001836:	687b      	ldr	r3, [r7, #4]
 8001838:	681b      	ldr	r3, [r3, #0]
 800183a:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
 800183e:	60da      	str	r2, [r3, #12]

  /* Set the UART Communication parameters */
  UART_SetConfig(huart);
 8001840:	6878      	ldr	r0, [r7, #4]
 8001842:	f000 f929 	bl	8001a98 <UART_SetConfig>

  /* In asynchronous mode, the following bits must be kept cleared:
     - LINEN and CLKEN bits in the USART_CR2 register,
     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8001846:	687b      	ldr	r3, [r7, #4]
 8001848:	681b      	ldr	r3, [r3, #0]
 800184a:	691a      	ldr	r2, [r3, #16]
 800184c:	687b      	ldr	r3, [r7, #4]
 800184e:	681b      	ldr	r3, [r3, #0]
 8001850:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8001854:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8001856:	687b      	ldr	r3, [r7, #4]
 8001858:	681b      	ldr	r3, [r3, #0]
 800185a:	695a      	ldr	r2, [r3, #20]
 800185c:	687b      	ldr	r3, [r7, #4]
 800185e:	681b      	ldr	r3, [r3, #0]
 8001860:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8001864:	615a      	str	r2, [r3, #20]

  /* Enable the peripheral */
  __HAL_UART_ENABLE(huart);
 8001866:	687b      	ldr	r3, [r7, #4]
 8001868:	681b      	ldr	r3, [r3, #0]
 800186a:	68da      	ldr	r2, [r3, #12]
 800186c:	687b      	ldr	r3, [r7, #4]
 800186e:	681b      	ldr	r3, [r3, #0]
 8001870:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8001874:	60da      	str	r2, [r3, #12]

  /* Initialize the UART state */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8001876:	687b      	ldr	r3, [r7, #4]
 8001878:	2200      	movs	r2, #0
 800187a:	641a      	str	r2, [r3, #64]	; 0x40
  huart->gState = HAL_UART_STATE_READY;
 800187c:	687b      	ldr	r3, [r7, #4]
 800187e:	2220      	movs	r2, #32
 8001880:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
  huart->RxState = HAL_UART_STATE_READY;
 8001884:	687b      	ldr	r3, [r7, #4]
 8001886:	2220      	movs	r2, #32
 8001888:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

  return HAL_OK;
 800188c:	2300      	movs	r3, #0
}
 800188e:	4618      	mov	r0, r3
 8001890:	3708      	adds	r7, #8
 8001892:	46bd      	mov	sp, r7
 8001894:	bd80      	pop	{r7, pc}

08001896 <HAL_UART_Transmit>:
  * @param  Size  Amount of data elements (u8 or u16) to be sent
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 8001896:	b580      	push	{r7, lr}
 8001898:	b08a      	sub	sp, #40	; 0x28
 800189a:	af02      	add	r7, sp, #8
 800189c:	60f8      	str	r0, [r7, #12]
 800189e:	60b9      	str	r1, [r7, #8]
 80018a0:	603b      	str	r3, [r7, #0]
 80018a2:	4613      	mov	r3, r2
 80018a4:	80fb      	strh	r3, [r7, #6]
  const uint8_t  *pdata8bits;
  const uint16_t *pdata16bits;
  uint32_t tickstart = 0U;
 80018a6:	2300      	movs	r3, #0
 80018a8:	617b      	str	r3, [r7, #20]

  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 80018aa:	68fb      	ldr	r3, [r7, #12]
 80018ac:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 80018b0:	b2db      	uxtb	r3, r3
 80018b2:	2b20      	cmp	r3, #32
 80018b4:	d17c      	bne.n	80019b0 <HAL_UART_Transmit+0x11a>
  {
    if ((pData == NULL) || (Size == 0U))
 80018b6:	68bb      	ldr	r3, [r7, #8]
 80018b8:	2b00      	cmp	r3, #0
 80018ba:	d002      	beq.n	80018c2 <HAL_UART_Transmit+0x2c>
 80018bc:	88fb      	ldrh	r3, [r7, #6]
 80018be:	2b00      	cmp	r3, #0
 80018c0:	d101      	bne.n	80018c6 <HAL_UART_Transmit+0x30>
    {
      return  HAL_ERROR;
 80018c2:	2301      	movs	r3, #1
 80018c4:	e075      	b.n	80019b2 <HAL_UART_Transmit+0x11c>
    }

    /* Process Locked */
    __HAL_LOCK(huart);
 80018c6:	68fb      	ldr	r3, [r7, #12]
 80018c8:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 80018cc:	2b01      	cmp	r3, #1
 80018ce:	d101      	bne.n	80018d4 <HAL_UART_Transmit+0x3e>
 80018d0:	2302      	movs	r3, #2
 80018d2:	e06e      	b.n	80019b2 <HAL_UART_Transmit+0x11c>
 80018d4:	68fb      	ldr	r3, [r7, #12]
 80018d6:	2201      	movs	r2, #1
 80018d8:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 80018dc:	68fb      	ldr	r3, [r7, #12]
 80018de:	2200      	movs	r2, #0
 80018e0:	641a      	str	r2, [r3, #64]	; 0x40
    huart->gState = HAL_UART_STATE_BUSY_TX;
 80018e2:	68fb      	ldr	r3, [r7, #12]
 80018e4:	2221      	movs	r2, #33	; 0x21
 80018e6:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

    /* Init tickstart for timeout management */
    tickstart = HAL_GetTick();
 80018ea:	f7ff f85f 	bl	80009ac <HAL_GetTick>
 80018ee:	6178      	str	r0, [r7, #20]

    huart->TxXferSize = Size;
 80018f0:	68fb      	ldr	r3, [r7, #12]
 80018f2:	88fa      	ldrh	r2, [r7, #6]
 80018f4:	849a      	strh	r2, [r3, #36]	; 0x24
    huart->TxXferCount = Size;
 80018f6:	68fb      	ldr	r3, [r7, #12]
 80018f8:	88fa      	ldrh	r2, [r7, #6]
 80018fa:	84da      	strh	r2, [r3, #38]	; 0x26

    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 80018fc:	68fb      	ldr	r3, [r7, #12]
 80018fe:	689b      	ldr	r3, [r3, #8]
 8001900:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8001904:	d108      	bne.n	8001918 <HAL_UART_Transmit+0x82>
 8001906:	68fb      	ldr	r3, [r7, #12]
 8001908:	691b      	ldr	r3, [r3, #16]
 800190a:	2b00      	cmp	r3, #0
 800190c:	d104      	bne.n	8001918 <HAL_UART_Transmit+0x82>
    {
      pdata8bits  = NULL;
 800190e:	2300      	movs	r3, #0
 8001910:	61fb      	str	r3, [r7, #28]
      pdata16bits = (const uint16_t *) pData;
 8001912:	68bb      	ldr	r3, [r7, #8]
 8001914:	61bb      	str	r3, [r7, #24]
 8001916:	e003      	b.n	8001920 <HAL_UART_Transmit+0x8a>
    }
    else
    {
      pdata8bits  = pData;
 8001918:	68bb      	ldr	r3, [r7, #8]
 800191a:	61fb      	str	r3, [r7, #28]
      pdata16bits = NULL;
 800191c:	2300      	movs	r3, #0
 800191e:	61bb      	str	r3, [r7, #24]
    }

    /* Process Unlocked */
    __HAL_UNLOCK(huart);
 8001920:	68fb      	ldr	r3, [r7, #12]
 8001922:	2200      	movs	r2, #0
 8001924:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    while (huart->TxXferCount > 0U)
 8001928:	e02a      	b.n	8001980 <HAL_UART_Transmit+0xea>
    {
      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 800192a:	683b      	ldr	r3, [r7, #0]
 800192c:	9300      	str	r3, [sp, #0]
 800192e:	697b      	ldr	r3, [r7, #20]
 8001930:	2200      	movs	r2, #0
 8001932:	2180      	movs	r1, #128	; 0x80
 8001934:	68f8      	ldr	r0, [r7, #12]
 8001936:	f000 f840 	bl	80019ba <UART_WaitOnFlagUntilTimeout>
 800193a:	4603      	mov	r3, r0
 800193c:	2b00      	cmp	r3, #0
 800193e:	d001      	beq.n	8001944 <HAL_UART_Transmit+0xae>
      {
        return HAL_TIMEOUT;
 8001940:	2303      	movs	r3, #3
 8001942:	e036      	b.n	80019b2 <HAL_UART_Transmit+0x11c>
      }
      if (pdata8bits == NULL)
 8001944:	69fb      	ldr	r3, [r7, #28]
 8001946:	2b00      	cmp	r3, #0
 8001948:	d10b      	bne.n	8001962 <HAL_UART_Transmit+0xcc>
      {
        huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
 800194a:	69bb      	ldr	r3, [r7, #24]
 800194c:	881b      	ldrh	r3, [r3, #0]
 800194e:	461a      	mov	r2, r3
 8001950:	68fb      	ldr	r3, [r7, #12]
 8001952:	681b      	ldr	r3, [r3, #0]
 8001954:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8001958:	605a      	str	r2, [r3, #4]
        pdata16bits++;
 800195a:	69bb      	ldr	r3, [r7, #24]
 800195c:	3302      	adds	r3, #2
 800195e:	61bb      	str	r3, [r7, #24]
 8001960:	e007      	b.n	8001972 <HAL_UART_Transmit+0xdc>
      }
      else
      {
        huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
 8001962:	69fb      	ldr	r3, [r7, #28]
 8001964:	781a      	ldrb	r2, [r3, #0]
 8001966:	68fb      	ldr	r3, [r7, #12]
 8001968:	681b      	ldr	r3, [r3, #0]
 800196a:	605a      	str	r2, [r3, #4]
        pdata8bits++;
 800196c:	69fb      	ldr	r3, [r7, #28]
 800196e:	3301      	adds	r3, #1
 8001970:	61fb      	str	r3, [r7, #28]
      }
      huart->TxXferCount--;
 8001972:	68fb      	ldr	r3, [r7, #12]
 8001974:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
 8001976:	b29b      	uxth	r3, r3
 8001978:	3b01      	subs	r3, #1
 800197a:	b29a      	uxth	r2, r3
 800197c:	68fb      	ldr	r3, [r7, #12]
 800197e:	84da      	strh	r2, [r3, #38]	; 0x26
    while (huart->TxXferCount > 0U)
 8001980:	68fb      	ldr	r3, [r7, #12]
 8001982:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
 8001984:	b29b      	uxth	r3, r3
 8001986:	2b00      	cmp	r3, #0
 8001988:	d1cf      	bne.n	800192a <HAL_UART_Transmit+0x94>
    }

    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 800198a:	683b      	ldr	r3, [r7, #0]
 800198c:	9300      	str	r3, [sp, #0]
 800198e:	697b      	ldr	r3, [r7, #20]
 8001990:	2200      	movs	r2, #0
 8001992:	2140      	movs	r1, #64	; 0x40
 8001994:	68f8      	ldr	r0, [r7, #12]
 8001996:	f000 f810 	bl	80019ba <UART_WaitOnFlagUntilTimeout>
 800199a:	4603      	mov	r3, r0
 800199c:	2b00      	cmp	r3, #0
 800199e:	d001      	beq.n	80019a4 <HAL_UART_Transmit+0x10e>
    {
      return HAL_TIMEOUT;
 80019a0:	2303      	movs	r3, #3
 80019a2:	e006      	b.n	80019b2 <HAL_UART_Transmit+0x11c>
    }

    /* At end of Tx process, restore huart->gState to Ready */
    huart->gState = HAL_UART_STATE_READY;
 80019a4:	68fb      	ldr	r3, [r7, #12]
 80019a6:	2220      	movs	r2, #32
 80019a8:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

    return HAL_OK;
 80019ac:	2300      	movs	r3, #0
 80019ae:	e000      	b.n	80019b2 <HAL_UART_Transmit+0x11c>
  }
  else
  {
    return HAL_BUSY;
 80019b0:	2302      	movs	r3, #2
  }
}
 80019b2:	4618      	mov	r0, r3
 80019b4:	3720      	adds	r7, #32
 80019b6:	46bd      	mov	sp, r7
 80019b8:	bd80      	pop	{r7, pc}

080019ba <UART_WaitOnFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                                     uint32_t Tickstart, uint32_t Timeout)
{
 80019ba:	b580      	push	{r7, lr}
 80019bc:	b090      	sub	sp, #64	; 0x40
 80019be:	af00      	add	r7, sp, #0
 80019c0:	60f8      	str	r0, [r7, #12]
 80019c2:	60b9      	str	r1, [r7, #8]
 80019c4:	603b      	str	r3, [r7, #0]
 80019c6:	4613      	mov	r3, r2
 80019c8:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 80019ca:	e050      	b.n	8001a6e <UART_WaitOnFlagUntilTimeout+0xb4>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 80019cc:	6cbb      	ldr	r3, [r7, #72]	; 0x48
 80019ce:	f1b3 3fff 	cmp.w	r3, #4294967295
 80019d2:	d04c      	beq.n	8001a6e <UART_WaitOnFlagUntilTimeout+0xb4>
    {
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
 80019d4:	6cbb      	ldr	r3, [r7, #72]	; 0x48
 80019d6:	2b00      	cmp	r3, #0
 80019d8:	d007      	beq.n	80019ea <UART_WaitOnFlagUntilTimeout+0x30>
 80019da:	f7fe ffe7 	bl	80009ac <HAL_GetTick>
 80019de:	4602      	mov	r2, r0
 80019e0:	683b      	ldr	r3, [r7, #0]
 80019e2:	1ad3      	subs	r3, r2, r3
 80019e4:	6cba      	ldr	r2, [r7, #72]	; 0x48
 80019e6:	429a      	cmp	r2, r3
 80019e8:	d241      	bcs.n	8001a6e <UART_WaitOnFlagUntilTimeout+0xb4>
      {
        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 80019ea:	68fb      	ldr	r3, [r7, #12]
 80019ec:	681b      	ldr	r3, [r3, #0]
 80019ee:	330c      	adds	r3, #12
 80019f0:	62bb      	str	r3, [r7, #40]	; 0x28
 */
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
    uint32_t result;

   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 80019f2:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80019f4:	e853 3f00 	ldrex	r3, [r3]
 80019f8:	627b      	str	r3, [r7, #36]	; 0x24
   return(result);
 80019fa:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80019fc:	f423 73d0 	bic.w	r3, r3, #416	; 0x1a0
 8001a00:	63fb      	str	r3, [r7, #60]	; 0x3c
 8001a02:	68fb      	ldr	r3, [r7, #12]
 8001a04:	681b      	ldr	r3, [r3, #0]
 8001a06:	330c      	adds	r3, #12
 8001a08:	6bfa      	ldr	r2, [r7, #60]	; 0x3c
 8001a0a:	637a      	str	r2, [r7, #52]	; 0x34
 8001a0c:	633b      	str	r3, [r7, #48]	; 0x30
 */
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
   uint32_t result;

   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8001a0e:	6b39      	ldr	r1, [r7, #48]	; 0x30
 8001a10:	6b7a      	ldr	r2, [r7, #52]	; 0x34
 8001a12:	e841 2300 	strex	r3, r2, [r1]
 8001a16:	62fb      	str	r3, [r7, #44]	; 0x2c
   return(result);
 8001a18:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8001a1a:	2b00      	cmp	r3, #0
 8001a1c:	d1e5      	bne.n	80019ea <UART_WaitOnFlagUntilTimeout+0x30>
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8001a1e:	68fb      	ldr	r3, [r7, #12]
 8001a20:	681b      	ldr	r3, [r3, #0]
 8001a22:	3314      	adds	r3, #20
 8001a24:	617b      	str	r3, [r7, #20]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8001a26:	697b      	ldr	r3, [r7, #20]
 8001a28:	e853 3f00 	ldrex	r3, [r3]
 8001a2c:	613b      	str	r3, [r7, #16]
   return(result);
 8001a2e:	693b      	ldr	r3, [r7, #16]
 8001a30:	f023 0301 	bic.w	r3, r3, #1
 8001a34:	63bb      	str	r3, [r7, #56]	; 0x38
 8001a36:	68fb      	ldr	r3, [r7, #12]
 8001a38:	681b      	ldr	r3, [r3, #0]
 8001a3a:	3314      	adds	r3, #20
 8001a3c:	6bba      	ldr	r2, [r7, #56]	; 0x38
 8001a3e:	623a      	str	r2, [r7, #32]
 8001a40:	61fb      	str	r3, [r7, #28]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8001a42:	69f9      	ldr	r1, [r7, #28]
 8001a44:	6a3a      	ldr	r2, [r7, #32]
 8001a46:	e841 2300 	strex	r3, r2, [r1]
 8001a4a:	61bb      	str	r3, [r7, #24]
   return(result);
 8001a4c:	69bb      	ldr	r3, [r7, #24]
 8001a4e:	2b00      	cmp	r3, #0
 8001a50:	d1e5      	bne.n	8001a1e <UART_WaitOnFlagUntilTimeout+0x64>

        huart->gState  = HAL_UART_STATE_READY;
 8001a52:	68fb      	ldr	r3, [r7, #12]
 8001a54:	2220      	movs	r2, #32
 8001a56:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
        huart->RxState = HAL_UART_STATE_READY;
 8001a5a:	68fb      	ldr	r3, [r7, #12]
 8001a5c:	2220      	movs	r2, #32
 8001a5e:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

        /* Process Unlocked */
        __HAL_UNLOCK(huart);
 8001a62:	68fb      	ldr	r3, [r7, #12]
 8001a64:	2200      	movs	r2, #0
 8001a66:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

        return HAL_TIMEOUT;
 8001a6a:	2303      	movs	r3, #3
 8001a6c:	e00f      	b.n	8001a8e <UART_WaitOnFlagUntilTimeout+0xd4>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8001a6e:	68fb      	ldr	r3, [r7, #12]
 8001a70:	681b      	ldr	r3, [r3, #0]
 8001a72:	681a      	ldr	r2, [r3, #0]
 8001a74:	68bb      	ldr	r3, [r7, #8]
 8001a76:	4013      	ands	r3, r2
 8001a78:	68ba      	ldr	r2, [r7, #8]
 8001a7a:	429a      	cmp	r2, r3
 8001a7c:	bf0c      	ite	eq
 8001a7e:	2301      	moveq	r3, #1
 8001a80:	2300      	movne	r3, #0
 8001a82:	b2db      	uxtb	r3, r3
 8001a84:	461a      	mov	r2, r3
 8001a86:	79fb      	ldrb	r3, [r7, #7]
 8001a88:	429a      	cmp	r2, r3
 8001a8a:	d09f      	beq.n	80019cc <UART_WaitOnFlagUntilTimeout+0x12>
      }
    }
  }
  return HAL_OK;
 8001a8c:	2300      	movs	r3, #0
}
 8001a8e:	4618      	mov	r0, r3
 8001a90:	3740      	adds	r7, #64	; 0x40
 8001a92:	46bd      	mov	sp, r7
 8001a94:	bd80      	pop	{r7, pc}
	...

08001a98 <UART_SetConfig>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 8001a98:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 8001a9c:	b0c0      	sub	sp, #256	; 0x100
 8001a9e:	af00      	add	r7, sp, #0
 8001aa0:	f8c7 00f4 	str.w	r0, [r7, #244]	; 0xf4
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits
     according to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8001aa4:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001aa8:	681b      	ldr	r3, [r3, #0]
 8001aaa:	691b      	ldr	r3, [r3, #16]
 8001aac:	f423 5040 	bic.w	r0, r3, #12288	; 0x3000
 8001ab0:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001ab4:	68d9      	ldr	r1, [r3, #12]
 8001ab6:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001aba:	681a      	ldr	r2, [r3, #0]
 8001abc:	ea40 0301 	orr.w	r3, r0, r1
 8001ac0:	6113      	str	r3, [r2, #16]
     Set the M bits according to huart->Init.WordLength value
     Set PCE and PS bits according to huart->Init.Parity value
     Set TE and RE bits according to huart->Init.Mode value
     Set OVER8 bit according to huart->Init.OverSampling value */

  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
 8001ac2:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001ac6:	689a      	ldr	r2, [r3, #8]
 8001ac8:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001acc:	691b      	ldr	r3, [r3, #16]
 8001ace:	431a      	orrs	r2, r3
 8001ad0:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001ad4:	695b      	ldr	r3, [r3, #20]
 8001ad6:	431a      	orrs	r2, r3
 8001ad8:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001adc:	69db      	ldr	r3, [r3, #28]
 8001ade:	4313      	orrs	r3, r2
 8001ae0:	f8c7 30f8 	str.w	r3, [r7, #248]	; 0xf8
  MODIFY_REG(huart->Instance->CR1,
 8001ae4:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001ae8:	681b      	ldr	r3, [r3, #0]
 8001aea:	68db      	ldr	r3, [r3, #12]
 8001aec:	f423 4116 	bic.w	r1, r3, #38400	; 0x9600
 8001af0:	f021 010c 	bic.w	r1, r1, #12
 8001af4:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001af8:	681a      	ldr	r2, [r3, #0]
 8001afa:	f8d7 30f8 	ldr.w	r3, [r7, #248]	; 0xf8
 8001afe:	430b      	orrs	r3, r1
 8001b00:	60d3      	str	r3, [r2, #12]
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
             tmpreg);

  /*-------------------------- USART CR3 Configuration -----------------------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 8001b02:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001b06:	681b      	ldr	r3, [r3, #0]
 8001b08:	695b      	ldr	r3, [r3, #20]
 8001b0a:	f423 7040 	bic.w	r0, r3, #768	; 0x300
 8001b0e:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001b12:	6999      	ldr	r1, [r3, #24]
 8001b14:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001b18:	681a      	ldr	r2, [r3, #0]
 8001b1a:	ea40 0301 	orr.w	r3, r0, r1
 8001b1e:	6153      	str	r3, [r2, #20]
    if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
    {
      pclk = HAL_RCC_GetPCLK2Freq();
    }
#elif defined(USART6)
    if ((huart->Instance == USART1) || (huart->Instance == USART6))
 8001b20:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001b24:	681a      	ldr	r2, [r3, #0]
 8001b26:	4b8f      	ldr	r3, [pc, #572]	; (8001d64 <UART_SetConfig+0x2cc>)
 8001b28:	429a      	cmp	r2, r3
 8001b2a:	d005      	beq.n	8001b38 <UART_SetConfig+0xa0>
 8001b2c:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001b30:	681a      	ldr	r2, [r3, #0]
 8001b32:	4b8d      	ldr	r3, [pc, #564]	; (8001d68 <UART_SetConfig+0x2d0>)
 8001b34:	429a      	cmp	r2, r3
 8001b36:	d104      	bne.n	8001b42 <UART_SetConfig+0xaa>
    {
      pclk = HAL_RCC_GetPCLK2Freq();
 8001b38:	f7ff fe4c 	bl	80017d4 <HAL_RCC_GetPCLK2Freq>
 8001b3c:	f8c7 00fc 	str.w	r0, [r7, #252]	; 0xfc
 8001b40:	e003      	b.n	8001b4a <UART_SetConfig+0xb2>
      pclk = HAL_RCC_GetPCLK2Freq();
    }
#endif /* USART6 */
    else
    {
      pclk = HAL_RCC_GetPCLK1Freq();
 8001b42:	f7ff fe33 	bl	80017ac <HAL_RCC_GetPCLK1Freq>
 8001b46:	f8c7 00fc 	str.w	r0, [r7, #252]	; 0xfc
    }
  /*-------------------------- USART BRR Configuration ---------------------*/
  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 8001b4a:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001b4e:	69db      	ldr	r3, [r3, #28]
 8001b50:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
 8001b54:	f040 810c 	bne.w	8001d70 <UART_SetConfig+0x2d8>
  {
    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
 8001b58:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 8001b5c:	2200      	movs	r2, #0
 8001b5e:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
 8001b62:	f8c7 20ec 	str.w	r2, [r7, #236]	; 0xec
 8001b66:	e9d7 453a 	ldrd	r4, r5, [r7, #232]	; 0xe8
 8001b6a:	4622      	mov	r2, r4
 8001b6c:	462b      	mov	r3, r5
 8001b6e:	1891      	adds	r1, r2, r2
 8001b70:	65b9      	str	r1, [r7, #88]	; 0x58
 8001b72:	415b      	adcs	r3, r3
 8001b74:	65fb      	str	r3, [r7, #92]	; 0x5c
 8001b76:	e9d7 2316 	ldrd	r2, r3, [r7, #88]	; 0x58
 8001b7a:	4621      	mov	r1, r4
 8001b7c:	eb12 0801 	adds.w	r8, r2, r1
 8001b80:	4629      	mov	r1, r5
 8001b82:	eb43 0901 	adc.w	r9, r3, r1
 8001b86:	f04f 0200 	mov.w	r2, #0
 8001b8a:	f04f 0300 	mov.w	r3, #0
 8001b8e:	ea4f 03c9 	mov.w	r3, r9, lsl #3
 8001b92:	ea43 7358 	orr.w	r3, r3, r8, lsr #29
 8001b96:	ea4f 02c8 	mov.w	r2, r8, lsl #3
 8001b9a:	4690      	mov	r8, r2
 8001b9c:	4699      	mov	r9, r3
 8001b9e:	4623      	mov	r3, r4
 8001ba0:	eb18 0303 	adds.w	r3, r8, r3
 8001ba4:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
 8001ba8:	462b      	mov	r3, r5
 8001baa:	eb49 0303 	adc.w	r3, r9, r3
 8001bae:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
 8001bb2:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001bb6:	685b      	ldr	r3, [r3, #4]
 8001bb8:	2200      	movs	r2, #0
 8001bba:	f8c7 30d8 	str.w	r3, [r7, #216]	; 0xd8
 8001bbe:	f8c7 20dc 	str.w	r2, [r7, #220]	; 0xdc
 8001bc2:	e9d7 1236 	ldrd	r1, r2, [r7, #216]	; 0xd8
 8001bc6:	460b      	mov	r3, r1
 8001bc8:	18db      	adds	r3, r3, r3
 8001bca:	653b      	str	r3, [r7, #80]	; 0x50
 8001bcc:	4613      	mov	r3, r2
 8001bce:	eb42 0303 	adc.w	r3, r2, r3
 8001bd2:	657b      	str	r3, [r7, #84]	; 0x54
 8001bd4:	e9d7 2314 	ldrd	r2, r3, [r7, #80]	; 0x50
 8001bd8:	e9d7 0138 	ldrd	r0, r1, [r7, #224]	; 0xe0
 8001bdc:	f7fe fafc 	bl	80001d8 <__aeabi_uldivmod>
 8001be0:	4602      	mov	r2, r0
 8001be2:	460b      	mov	r3, r1
 8001be4:	4b61      	ldr	r3, [pc, #388]	; (8001d6c <UART_SetConfig+0x2d4>)
 8001be6:	fba3 2302 	umull	r2, r3, r3, r2
 8001bea:	095b      	lsrs	r3, r3, #5
 8001bec:	011c      	lsls	r4, r3, #4
 8001bee:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 8001bf2:	2200      	movs	r2, #0
 8001bf4:	f8c7 30d0 	str.w	r3, [r7, #208]	; 0xd0
 8001bf8:	f8c7 20d4 	str.w	r2, [r7, #212]	; 0xd4
 8001bfc:	e9d7 8934 	ldrd	r8, r9, [r7, #208]	; 0xd0
 8001c00:	4642      	mov	r2, r8
 8001c02:	464b      	mov	r3, r9
 8001c04:	1891      	adds	r1, r2, r2
 8001c06:	64b9      	str	r1, [r7, #72]	; 0x48
 8001c08:	415b      	adcs	r3, r3
 8001c0a:	64fb      	str	r3, [r7, #76]	; 0x4c
 8001c0c:	e9d7 2312 	ldrd	r2, r3, [r7, #72]	; 0x48
 8001c10:	4641      	mov	r1, r8
 8001c12:	eb12 0a01 	adds.w	sl, r2, r1
 8001c16:	4649      	mov	r1, r9
 8001c18:	eb43 0b01 	adc.w	fp, r3, r1
 8001c1c:	f04f 0200 	mov.w	r2, #0
 8001c20:	f04f 0300 	mov.w	r3, #0
 8001c24:	ea4f 03cb 	mov.w	r3, fp, lsl #3
 8001c28:	ea43 735a 	orr.w	r3, r3, sl, lsr #29
 8001c2c:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 8001c30:	4692      	mov	sl, r2
 8001c32:	469b      	mov	fp, r3
 8001c34:	4643      	mov	r3, r8
 8001c36:	eb1a 0303 	adds.w	r3, sl, r3
 8001c3a:	f8c7 30c8 	str.w	r3, [r7, #200]	; 0xc8
 8001c3e:	464b      	mov	r3, r9
 8001c40:	eb4b 0303 	adc.w	r3, fp, r3
 8001c44:	f8c7 30cc 	str.w	r3, [r7, #204]	; 0xcc
 8001c48:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001c4c:	685b      	ldr	r3, [r3, #4]
 8001c4e:	2200      	movs	r2, #0
 8001c50:	f8c7 30c0 	str.w	r3, [r7, #192]	; 0xc0
 8001c54:	f8c7 20c4 	str.w	r2, [r7, #196]	; 0xc4
 8001c58:	e9d7 1230 	ldrd	r1, r2, [r7, #192]	; 0xc0
 8001c5c:	460b      	mov	r3, r1
 8001c5e:	18db      	adds	r3, r3, r3
 8001c60:	643b      	str	r3, [r7, #64]	; 0x40
 8001c62:	4613      	mov	r3, r2
 8001c64:	eb42 0303 	adc.w	r3, r2, r3
 8001c68:	647b      	str	r3, [r7, #68]	; 0x44
 8001c6a:	e9d7 2310 	ldrd	r2, r3, [r7, #64]	; 0x40
 8001c6e:	e9d7 0132 	ldrd	r0, r1, [r7, #200]	; 0xc8
 8001c72:	f7fe fab1 	bl	80001d8 <__aeabi_uldivmod>
 8001c76:	4602      	mov	r2, r0
 8001c78:	460b      	mov	r3, r1
 8001c7a:	4611      	mov	r1, r2
 8001c7c:	4b3b      	ldr	r3, [pc, #236]	; (8001d6c <UART_SetConfig+0x2d4>)
 8001c7e:	fba3 2301 	umull	r2, r3, r3, r1
 8001c82:	095b      	lsrs	r3, r3, #5
 8001c84:	2264      	movs	r2, #100	; 0x64
 8001c86:	fb02 f303 	mul.w	r3, r2, r3
 8001c8a:	1acb      	subs	r3, r1, r3
 8001c8c:	00db      	lsls	r3, r3, #3
 8001c8e:	f103 0232 	add.w	r2, r3, #50	; 0x32
 8001c92:	4b36      	ldr	r3, [pc, #216]	; (8001d6c <UART_SetConfig+0x2d4>)
 8001c94:	fba3 2302 	umull	r2, r3, r3, r2
 8001c98:	095b      	lsrs	r3, r3, #5
 8001c9a:	005b      	lsls	r3, r3, #1
 8001c9c:	f403 73f8 	and.w	r3, r3, #496	; 0x1f0
 8001ca0:	441c      	add	r4, r3
 8001ca2:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 8001ca6:	2200      	movs	r2, #0
 8001ca8:	f8c7 30b8 	str.w	r3, [r7, #184]	; 0xb8
 8001cac:	f8c7 20bc 	str.w	r2, [r7, #188]	; 0xbc
 8001cb0:	e9d7 892e 	ldrd	r8, r9, [r7, #184]	; 0xb8
 8001cb4:	4642      	mov	r2, r8
 8001cb6:	464b      	mov	r3, r9
 8001cb8:	1891      	adds	r1, r2, r2
 8001cba:	63b9      	str	r1, [r7, #56]	; 0x38
 8001cbc:	415b      	adcs	r3, r3
 8001cbe:	63fb      	str	r3, [r7, #60]	; 0x3c
 8001cc0:	e9d7 230e 	ldrd	r2, r3, [r7, #56]	; 0x38
 8001cc4:	4641      	mov	r1, r8
 8001cc6:	1851      	adds	r1, r2, r1
 8001cc8:	6339      	str	r1, [r7, #48]	; 0x30
 8001cca:	4649      	mov	r1, r9
 8001ccc:	414b      	adcs	r3, r1
 8001cce:	637b      	str	r3, [r7, #52]	; 0x34
 8001cd0:	f04f 0200 	mov.w	r2, #0
 8001cd4:	f04f 0300 	mov.w	r3, #0
 8001cd8:	e9d7 ab0c 	ldrd	sl, fp, [r7, #48]	; 0x30
 8001cdc:	4659      	mov	r1, fp
 8001cde:	00cb      	lsls	r3, r1, #3
 8001ce0:	4651      	mov	r1, sl
 8001ce2:	ea43 7351 	orr.w	r3, r3, r1, lsr #29
 8001ce6:	4651      	mov	r1, sl
 8001ce8:	00ca      	lsls	r2, r1, #3
 8001cea:	4610      	mov	r0, r2
 8001cec:	4619      	mov	r1, r3
 8001cee:	4603      	mov	r3, r0
 8001cf0:	4642      	mov	r2, r8
 8001cf2:	189b      	adds	r3, r3, r2
 8001cf4:	f8c7 30b0 	str.w	r3, [r7, #176]	; 0xb0
 8001cf8:	464b      	mov	r3, r9
 8001cfa:	460a      	mov	r2, r1
 8001cfc:	eb42 0303 	adc.w	r3, r2, r3
 8001d00:	f8c7 30b4 	str.w	r3, [r7, #180]	; 0xb4
 8001d04:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001d08:	685b      	ldr	r3, [r3, #4]
 8001d0a:	2200      	movs	r2, #0
 8001d0c:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
 8001d10:	f8c7 20ac 	str.w	r2, [r7, #172]	; 0xac
 8001d14:	e9d7 122a 	ldrd	r1, r2, [r7, #168]	; 0xa8
 8001d18:	460b      	mov	r3, r1
 8001d1a:	18db      	adds	r3, r3, r3
 8001d1c:	62bb      	str	r3, [r7, #40]	; 0x28
 8001d1e:	4613      	mov	r3, r2
 8001d20:	eb42 0303 	adc.w	r3, r2, r3
 8001d24:	62fb      	str	r3, [r7, #44]	; 0x2c
 8001d26:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	; 0x28
 8001d2a:	e9d7 012c 	ldrd	r0, r1, [r7, #176]	; 0xb0
 8001d2e:	f7fe fa53 	bl	80001d8 <__aeabi_uldivmod>
 8001d32:	4602      	mov	r2, r0
 8001d34:	460b      	mov	r3, r1
 8001d36:	4b0d      	ldr	r3, [pc, #52]	; (8001d6c <UART_SetConfig+0x2d4>)
 8001d38:	fba3 1302 	umull	r1, r3, r3, r2
 8001d3c:	095b      	lsrs	r3, r3, #5
 8001d3e:	2164      	movs	r1, #100	; 0x64
 8001d40:	fb01 f303 	mul.w	r3, r1, r3
 8001d44:	1ad3      	subs	r3, r2, r3
 8001d46:	00db      	lsls	r3, r3, #3
 8001d48:	3332      	adds	r3, #50	; 0x32
 8001d4a:	4a08      	ldr	r2, [pc, #32]	; (8001d6c <UART_SetConfig+0x2d4>)
 8001d4c:	fba2 2303 	umull	r2, r3, r2, r3
 8001d50:	095b      	lsrs	r3, r3, #5
 8001d52:	f003 0207 	and.w	r2, r3, #7
 8001d56:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001d5a:	681b      	ldr	r3, [r3, #0]
 8001d5c:	4422      	add	r2, r4
 8001d5e:	609a      	str	r2, [r3, #8]
  }
  else
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
  }
}
 8001d60:	e106      	b.n	8001f70 <UART_SetConfig+0x4d8>
 8001d62:	bf00      	nop
 8001d64:	40011000 	.word	0x40011000
 8001d68:	40011400 	.word	0x40011400
 8001d6c:	51eb851f 	.word	0x51eb851f
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 8001d70:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 8001d74:	2200      	movs	r2, #0
 8001d76:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0
 8001d7a:	f8c7 20a4 	str.w	r2, [r7, #164]	; 0xa4
 8001d7e:	e9d7 8928 	ldrd	r8, r9, [r7, #160]	; 0xa0
 8001d82:	4642      	mov	r2, r8
 8001d84:	464b      	mov	r3, r9
 8001d86:	1891      	adds	r1, r2, r2
 8001d88:	6239      	str	r1, [r7, #32]
 8001d8a:	415b      	adcs	r3, r3
 8001d8c:	627b      	str	r3, [r7, #36]	; 0x24
 8001d8e:	e9d7 2308 	ldrd	r2, r3, [r7, #32]
 8001d92:	4641      	mov	r1, r8
 8001d94:	1854      	adds	r4, r2, r1
 8001d96:	4649      	mov	r1, r9
 8001d98:	eb43 0501 	adc.w	r5, r3, r1
 8001d9c:	f04f 0200 	mov.w	r2, #0
 8001da0:	f04f 0300 	mov.w	r3, #0
 8001da4:	00eb      	lsls	r3, r5, #3
 8001da6:	ea43 7354 	orr.w	r3, r3, r4, lsr #29
 8001daa:	00e2      	lsls	r2, r4, #3
 8001dac:	4614      	mov	r4, r2
 8001dae:	461d      	mov	r5, r3
 8001db0:	4643      	mov	r3, r8
 8001db2:	18e3      	adds	r3, r4, r3
 8001db4:	f8c7 3098 	str.w	r3, [r7, #152]	; 0x98
 8001db8:	464b      	mov	r3, r9
 8001dba:	eb45 0303 	adc.w	r3, r5, r3
 8001dbe:	f8c7 309c 	str.w	r3, [r7, #156]	; 0x9c
 8001dc2:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001dc6:	685b      	ldr	r3, [r3, #4]
 8001dc8:	2200      	movs	r2, #0
 8001dca:	f8c7 3090 	str.w	r3, [r7, #144]	; 0x90
 8001dce:	f8c7 2094 	str.w	r2, [r7, #148]	; 0x94
 8001dd2:	f04f 0200 	mov.w	r2, #0
 8001dd6:	f04f 0300 	mov.w	r3, #0
 8001dda:	e9d7 4524 	ldrd	r4, r5, [r7, #144]	; 0x90
 8001dde:	4629      	mov	r1, r5
 8001de0:	008b      	lsls	r3, r1, #2
 8001de2:	4621      	mov	r1, r4
 8001de4:	ea43 7391 	orr.w	r3, r3, r1, lsr #30
 8001de8:	4621      	mov	r1, r4
 8001dea:	008a      	lsls	r2, r1, #2
 8001dec:	e9d7 0126 	ldrd	r0, r1, [r7, #152]	; 0x98
 8001df0:	f7fe f9f2 	bl	80001d8 <__aeabi_uldivmod>
 8001df4:	4602      	mov	r2, r0
 8001df6:	460b      	mov	r3, r1
 8001df8:	4b60      	ldr	r3, [pc, #384]	; (8001f7c <UART_SetConfig+0x4e4>)
 8001dfa:	fba3 2302 	umull	r2, r3, r3, r2
 8001dfe:	095b      	lsrs	r3, r3, #5
 8001e00:	011c      	lsls	r4, r3, #4
 8001e02:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 8001e06:	2200      	movs	r2, #0
 8001e08:	f8c7 3088 	str.w	r3, [r7, #136]	; 0x88
 8001e0c:	f8c7 208c 	str.w	r2, [r7, #140]	; 0x8c
 8001e10:	e9d7 8922 	ldrd	r8, r9, [r7, #136]	; 0x88
 8001e14:	4642      	mov	r2, r8
 8001e16:	464b      	mov	r3, r9
 8001e18:	1891      	adds	r1, r2, r2
 8001e1a:	61b9      	str	r1, [r7, #24]
 8001e1c:	415b      	adcs	r3, r3
 8001e1e:	61fb      	str	r3, [r7, #28]
 8001e20:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
 8001e24:	4641      	mov	r1, r8
 8001e26:	1851      	adds	r1, r2, r1
 8001e28:	6139      	str	r1, [r7, #16]
 8001e2a:	4649      	mov	r1, r9
 8001e2c:	414b      	adcs	r3, r1
 8001e2e:	617b      	str	r3, [r7, #20]
 8001e30:	f04f 0200 	mov.w	r2, #0
 8001e34:	f04f 0300 	mov.w	r3, #0
 8001e38:	e9d7 ab04 	ldrd	sl, fp, [r7, #16]
 8001e3c:	4659      	mov	r1, fp
 8001e3e:	00cb      	lsls	r3, r1, #3
 8001e40:	4651      	mov	r1, sl
 8001e42:	ea43 7351 	orr.w	r3, r3, r1, lsr #29
 8001e46:	4651      	mov	r1, sl
 8001e48:	00ca      	lsls	r2, r1, #3
 8001e4a:	4610      	mov	r0, r2
 8001e4c:	4619      	mov	r1, r3
 8001e4e:	4603      	mov	r3, r0
 8001e50:	4642      	mov	r2, r8
 8001e52:	189b      	adds	r3, r3, r2
 8001e54:	f8c7 3080 	str.w	r3, [r7, #128]	; 0x80
 8001e58:	464b      	mov	r3, r9
 8001e5a:	460a      	mov	r2, r1
 8001e5c:	eb42 0303 	adc.w	r3, r2, r3
 8001e60:	f8c7 3084 	str.w	r3, [r7, #132]	; 0x84
 8001e64:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001e68:	685b      	ldr	r3, [r3, #4]
 8001e6a:	2200      	movs	r2, #0
 8001e6c:	67bb      	str	r3, [r7, #120]	; 0x78
 8001e6e:	67fa      	str	r2, [r7, #124]	; 0x7c
 8001e70:	f04f 0200 	mov.w	r2, #0
 8001e74:	f04f 0300 	mov.w	r3, #0
 8001e78:	e9d7 891e 	ldrd	r8, r9, [r7, #120]	; 0x78
 8001e7c:	4649      	mov	r1, r9
 8001e7e:	008b      	lsls	r3, r1, #2
 8001e80:	4641      	mov	r1, r8
 8001e82:	ea43 7391 	orr.w	r3, r3, r1, lsr #30
 8001e86:	4641      	mov	r1, r8
 8001e88:	008a      	lsls	r2, r1, #2
 8001e8a:	e9d7 0120 	ldrd	r0, r1, [r7, #128]	; 0x80
 8001e8e:	f7fe f9a3 	bl	80001d8 <__aeabi_uldivmod>
 8001e92:	4602      	mov	r2, r0
 8001e94:	460b      	mov	r3, r1
 8001e96:	4611      	mov	r1, r2
 8001e98:	4b38      	ldr	r3, [pc, #224]	; (8001f7c <UART_SetConfig+0x4e4>)
 8001e9a:	fba3 2301 	umull	r2, r3, r3, r1
 8001e9e:	095b      	lsrs	r3, r3, #5
 8001ea0:	2264      	movs	r2, #100	; 0x64
 8001ea2:	fb02 f303 	mul.w	r3, r2, r3
 8001ea6:	1acb      	subs	r3, r1, r3
 8001ea8:	011b      	lsls	r3, r3, #4
 8001eaa:	3332      	adds	r3, #50	; 0x32
 8001eac:	4a33      	ldr	r2, [pc, #204]	; (8001f7c <UART_SetConfig+0x4e4>)
 8001eae:	fba2 2303 	umull	r2, r3, r2, r3
 8001eb2:	095b      	lsrs	r3, r3, #5
 8001eb4:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 8001eb8:	441c      	add	r4, r3
 8001eba:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 8001ebe:	2200      	movs	r2, #0
 8001ec0:	673b      	str	r3, [r7, #112]	; 0x70
 8001ec2:	677a      	str	r2, [r7, #116]	; 0x74
 8001ec4:	e9d7 891c 	ldrd	r8, r9, [r7, #112]	; 0x70
 8001ec8:	4642      	mov	r2, r8
 8001eca:	464b      	mov	r3, r9
 8001ecc:	1891      	adds	r1, r2, r2
 8001ece:	60b9      	str	r1, [r7, #8]
 8001ed0:	415b      	adcs	r3, r3
 8001ed2:	60fb      	str	r3, [r7, #12]
 8001ed4:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
 8001ed8:	4641      	mov	r1, r8
 8001eda:	1851      	adds	r1, r2, r1
 8001edc:	6039      	str	r1, [r7, #0]
 8001ede:	4649      	mov	r1, r9
 8001ee0:	414b      	adcs	r3, r1
 8001ee2:	607b      	str	r3, [r7, #4]
 8001ee4:	f04f 0200 	mov.w	r2, #0
 8001ee8:	f04f 0300 	mov.w	r3, #0
 8001eec:	e9d7 ab00 	ldrd	sl, fp, [r7]
 8001ef0:	4659      	mov	r1, fp
 8001ef2:	00cb      	lsls	r3, r1, #3
 8001ef4:	4651      	mov	r1, sl
 8001ef6:	ea43 7351 	orr.w	r3, r3, r1, lsr #29
 8001efa:	4651      	mov	r1, sl
 8001efc:	00ca      	lsls	r2, r1, #3
 8001efe:	4610      	mov	r0, r2
 8001f00:	4619      	mov	r1, r3
 8001f02:	4603      	mov	r3, r0
 8001f04:	4642      	mov	r2, r8
 8001f06:	189b      	adds	r3, r3, r2
 8001f08:	66bb      	str	r3, [r7, #104]	; 0x68
 8001f0a:	464b      	mov	r3, r9
 8001f0c:	460a      	mov	r2, r1
 8001f0e:	eb42 0303 	adc.w	r3, r2, r3
 8001f12:	66fb      	str	r3, [r7, #108]	; 0x6c
 8001f14:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001f18:	685b      	ldr	r3, [r3, #4]
 8001f1a:	2200      	movs	r2, #0
 8001f1c:	663b      	str	r3, [r7, #96]	; 0x60
 8001f1e:	667a      	str	r2, [r7, #100]	; 0x64
 8001f20:	f04f 0200 	mov.w	r2, #0
 8001f24:	f04f 0300 	mov.w	r3, #0
 8001f28:	e9d7 8918 	ldrd	r8, r9, [r7, #96]	; 0x60
 8001f2c:	4649      	mov	r1, r9
 8001f2e:	008b      	lsls	r3, r1, #2
 8001f30:	4641      	mov	r1, r8
 8001f32:	ea43 7391 	orr.w	r3, r3, r1, lsr #30
 8001f36:	4641      	mov	r1, r8
 8001f38:	008a      	lsls	r2, r1, #2
 8001f3a:	e9d7 011a 	ldrd	r0, r1, [r7, #104]	; 0x68
 8001f3e:	f7fe f94b 	bl	80001d8 <__aeabi_uldivmod>
 8001f42:	4602      	mov	r2, r0
 8001f44:	460b      	mov	r3, r1
 8001f46:	4b0d      	ldr	r3, [pc, #52]	; (8001f7c <UART_SetConfig+0x4e4>)
 8001f48:	fba3 1302 	umull	r1, r3, r3, r2
 8001f4c:	095b      	lsrs	r3, r3, #5
 8001f4e:	2164      	movs	r1, #100	; 0x64
 8001f50:	fb01 f303 	mul.w	r3, r1, r3
 8001f54:	1ad3      	subs	r3, r2, r3
 8001f56:	011b      	lsls	r3, r3, #4
 8001f58:	3332      	adds	r3, #50	; 0x32
 8001f5a:	4a08      	ldr	r2, [pc, #32]	; (8001f7c <UART_SetConfig+0x4e4>)
 8001f5c:	fba2 2303 	umull	r2, r3, r2, r3
 8001f60:	095b      	lsrs	r3, r3, #5
 8001f62:	f003 020f 	and.w	r2, r3, #15
 8001f66:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8001f6a:	681b      	ldr	r3, [r3, #0]
 8001f6c:	4422      	add	r2, r4
 8001f6e:	609a      	str	r2, [r3, #8]
}
 8001f70:	bf00      	nop
 8001f72:	f507 7780 	add.w	r7, r7, #256	; 0x100
 8001f76:	46bd      	mov	sp, r7
 8001f78:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 8001f7c:	51eb851f 	.word	0x51eb851f

08001f80 <memset>:
 8001f80:	4402      	add	r2, r0
 8001f82:	4603      	mov	r3, r0
 8001f84:	4293      	cmp	r3, r2
 8001f86:	d100      	bne.n	8001f8a <memset+0xa>
 8001f88:	4770      	bx	lr
 8001f8a:	f803 1b01 	strb.w	r1, [r3], #1
 8001f8e:	e7f9      	b.n	8001f84 <memset+0x4>

08001f90 <__libc_init_array>:
 8001f90:	b570      	push	{r4, r5, r6, lr}
 8001f92:	4d0d      	ldr	r5, [pc, #52]	; (8001fc8 <__libc_init_array+0x38>)
 8001f94:	4c0d      	ldr	r4, [pc, #52]	; (8001fcc <__libc_init_array+0x3c>)
 8001f96:	1b64      	subs	r4, r4, r5
 8001f98:	10a4      	asrs	r4, r4, #2
 8001f9a:	2600      	movs	r6, #0
 8001f9c:	42a6      	cmp	r6, r4
 8001f9e:	d109      	bne.n	8001fb4 <__libc_init_array+0x24>
 8001fa0:	4d0b      	ldr	r5, [pc, #44]	; (8001fd0 <__libc_init_array+0x40>)
 8001fa2:	4c0c      	ldr	r4, [pc, #48]	; (8001fd4 <__libc_init_array+0x44>)
 8001fa4:	f000 f818 	bl	8001fd8 <_init>
 8001fa8:	1b64      	subs	r4, r4, r5
 8001faa:	10a4      	asrs	r4, r4, #2
 8001fac:	2600      	movs	r6, #0
 8001fae:	42a6      	cmp	r6, r4
 8001fb0:	d105      	bne.n	8001fbe <__libc_init_array+0x2e>
 8001fb2:	bd70      	pop	{r4, r5, r6, pc}
 8001fb4:	f855 3b04 	ldr.w	r3, [r5], #4
 8001fb8:	4798      	blx	r3
 8001fba:	3601      	adds	r6, #1
 8001fbc:	e7ee      	b.n	8001f9c <__libc_init_array+0xc>
 8001fbe:	f855 3b04 	ldr.w	r3, [r5], #4
 8001fc2:	4798      	blx	r3
 8001fc4:	3601      	adds	r6, #1
 8001fc6:	e7f2      	b.n	8001fae <__libc_init_array+0x1e>
 8001fc8:	08002018 	.word	0x08002018
 8001fcc:	08002018 	.word	0x08002018
 8001fd0:	08002018 	.word	0x08002018
 8001fd4:	0800201c 	.word	0x0800201c

08001fd8 <_init>:
 8001fd8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001fda:	bf00      	nop
 8001fdc:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8001fde:	bc08      	pop	{r3}
 8001fe0:	469e      	mov	lr, r3
 8001fe2:	4770      	bx	lr

08001fe4 <_fini>:
 8001fe4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8001fe6:	bf00      	nop
 8001fe8:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8001fea:	bc08      	pop	{r3}
 8001fec:	469e      	mov	lr, r3
 8001fee:	4770      	bx	lr