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stm32-fmt-code/access_control_stm32/Debug/access_control_stm32.list

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initial_commit
2023-09-17 08:27:41 +00:00
access_control_stm32.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000198 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00001ebc 08000198 08000198 00010198 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000018 08002054 08002054 00012054 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 0800206c 0800206c 0002000c 2**0
CONTENTS
4 .ARM 00000008 0800206c 0800206c 0001206c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08002074 08002074 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08002074 08002074 00012074 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08002078 08002078 00012078 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 0800207c 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000070 2000000c 08002088 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 2000007c 08002088 0002007c 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .comment 00000043 00000000 00000000 0002003c 2**0
CONTENTS, READONLY
13 .debug_info 000070cd 00000000 00000000 0002007f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_abbrev 000012d3 00000000 00000000 0002714c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00000608 00000000 00000000 00028420 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_rnglists 0000049d 00000000 00000000 00028a28 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_macro 000152be 00000000 00000000 00028ec5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_line 00007ae1 00000000 00000000 0003e183 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_str 00085048 00000000 00000000 00045c64 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_frame 000017a4 00000000 00000000 000cacac 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000072 00000000 00000000 000cc450 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000198 <__do_global_dtors_aux>:
8000198: b510 push {r4, lr}
800019a: 4c05 ldr r4, [pc, #20] ; (80001b0 <__do_global_dtors_aux+0x18>)
800019c: 7823 ldrb r3, [r4, #0]
800019e: b933 cbnz r3, 80001ae <__do_global_dtors_aux+0x16>
80001a0: 4b04 ldr r3, [pc, #16] ; (80001b4 <__do_global_dtors_aux+0x1c>)
80001a2: b113 cbz r3, 80001aa <__do_global_dtors_aux+0x12>
80001a4: 4804 ldr r0, [pc, #16] ; (80001b8 <__do_global_dtors_aux+0x20>)
80001a6: f3af 8000 nop.w
80001aa: 2301 movs r3, #1
80001ac: 7023 strb r3, [r4, #0]
80001ae: bd10 pop {r4, pc}
80001b0: 2000000c .word 0x2000000c
80001b4: 00000000 .word 0x00000000
80001b8: 0800203c .word 0x0800203c
080001bc <frame_dummy>:
80001bc: b508 push {r3, lr}
80001be: 4b03 ldr r3, [pc, #12] ; (80001cc <frame_dummy+0x10>)
80001c0: b11b cbz r3, 80001ca <frame_dummy+0xe>
80001c2: 4903 ldr r1, [pc, #12] ; (80001d0 <frame_dummy+0x14>)
80001c4: 4803 ldr r0, [pc, #12] ; (80001d4 <frame_dummy+0x18>)
80001c6: f3af 8000 nop.w
80001ca: bd08 pop {r3, pc}
80001cc: 00000000 .word 0x00000000
80001d0: 20000010 .word 0x20000010
80001d4: 0800203c .word 0x0800203c
080001d8 <__aeabi_uldivmod>:
80001d8: b953 cbnz r3, 80001f0 <__aeabi_uldivmod+0x18>
80001da: b94a cbnz r2, 80001f0 <__aeabi_uldivmod+0x18>
80001dc: 2900 cmp r1, #0
80001de: bf08 it eq
80001e0: 2800 cmpeq r0, #0
80001e2: bf1c itt ne
80001e4: f04f 31ff movne.w r1, #4294967295
80001e8: f04f 30ff movne.w r0, #4294967295
80001ec: f000 b970 b.w 80004d0 <__aeabi_idiv0>
80001f0: f1ad 0c08 sub.w ip, sp, #8
80001f4: e96d ce04 strd ip, lr, [sp, #-16]!
80001f8: f000 f806 bl 8000208 <__udivmoddi4>
80001fc: f8dd e004 ldr.w lr, [sp, #4]
8000200: e9dd 2302 ldrd r2, r3, [sp, #8]
8000204: b004 add sp, #16
8000206: 4770 bx lr
08000208 <__udivmoddi4>:
8000208: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800020c: 9e08 ldr r6, [sp, #32]
800020e: 460d mov r5, r1
8000210: 4604 mov r4, r0
8000212: 460f mov r7, r1
8000214: 2b00 cmp r3, #0
8000216: d14a bne.n 80002ae <__udivmoddi4+0xa6>
8000218: 428a cmp r2, r1
800021a: 4694 mov ip, r2
800021c: d965 bls.n 80002ea <__udivmoddi4+0xe2>
800021e: fab2 f382 clz r3, r2
8000222: b143 cbz r3, 8000236 <__udivmoddi4+0x2e>
8000224: fa02 fc03 lsl.w ip, r2, r3
8000228: f1c3 0220 rsb r2, r3, #32
800022c: 409f lsls r7, r3
800022e: fa20 f202 lsr.w r2, r0, r2
8000232: 4317 orrs r7, r2
8000234: 409c lsls r4, r3
8000236: ea4f 4e1c mov.w lr, ip, lsr #16
800023a: fa1f f58c uxth.w r5, ip
800023e: fbb7 f1fe udiv r1, r7, lr
8000242: 0c22 lsrs r2, r4, #16
8000244: fb0e 7711 mls r7, lr, r1, r7
8000248: ea42 4207 orr.w r2, r2, r7, lsl #16
800024c: fb01 f005 mul.w r0, r1, r5
8000250: 4290 cmp r0, r2
8000252: d90a bls.n 800026a <__udivmoddi4+0x62>
8000254: eb1c 0202 adds.w r2, ip, r2
8000258: f101 37ff add.w r7, r1, #4294967295
800025c: f080 811c bcs.w 8000498 <__udivmoddi4+0x290>
8000260: 4290 cmp r0, r2
8000262: f240 8119 bls.w 8000498 <__udivmoddi4+0x290>
8000266: 3902 subs r1, #2
8000268: 4462 add r2, ip
800026a: 1a12 subs r2, r2, r0
800026c: b2a4 uxth r4, r4
800026e: fbb2 f0fe udiv r0, r2, lr
8000272: fb0e 2210 mls r2, lr, r0, r2
8000276: ea44 4402 orr.w r4, r4, r2, lsl #16
800027a: fb00 f505 mul.w r5, r0, r5
800027e: 42a5 cmp r5, r4
8000280: d90a bls.n 8000298 <__udivmoddi4+0x90>
8000282: eb1c 0404 adds.w r4, ip, r4
8000286: f100 32ff add.w r2, r0, #4294967295
800028a: f080 8107 bcs.w 800049c <__udivmoddi4+0x294>
800028e: 42a5 cmp r5, r4
8000290: f240 8104 bls.w 800049c <__udivmoddi4+0x294>
8000294: 4464 add r4, ip
8000296: 3802 subs r0, #2
8000298: ea40 4001 orr.w r0, r0, r1, lsl #16
800029c: 1b64 subs r4, r4, r5
800029e: 2100 movs r1, #0
80002a0: b11e cbz r6, 80002aa <__udivmoddi4+0xa2>
80002a2: 40dc lsrs r4, r3
80002a4: 2300 movs r3, #0
80002a6: e9c6 4300 strd r4, r3, [r6]
80002aa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002ae: 428b cmp r3, r1
80002b0: d908 bls.n 80002c4 <__udivmoddi4+0xbc>
80002b2: 2e00 cmp r6, #0
80002b4: f000 80ed beq.w 8000492 <__udivmoddi4+0x28a>
80002b8: 2100 movs r1, #0
80002ba: e9c6 0500 strd r0, r5, [r6]
80002be: 4608 mov r0, r1
80002c0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002c4: fab3 f183 clz r1, r3
80002c8: 2900 cmp r1, #0
80002ca: d149 bne.n 8000360 <__udivmoddi4+0x158>
80002cc: 42ab cmp r3, r5
80002ce: d302 bcc.n 80002d6 <__udivmoddi4+0xce>
80002d0: 4282 cmp r2, r0
80002d2: f200 80f8 bhi.w 80004c6 <__udivmoddi4+0x2be>
80002d6: 1a84 subs r4, r0, r2
80002d8: eb65 0203 sbc.w r2, r5, r3
80002dc: 2001 movs r0, #1
80002de: 4617 mov r7, r2
80002e0: 2e00 cmp r6, #0
80002e2: d0e2 beq.n 80002aa <__udivmoddi4+0xa2>
80002e4: e9c6 4700 strd r4, r7, [r6]
80002e8: e7df b.n 80002aa <__udivmoddi4+0xa2>
80002ea: b902 cbnz r2, 80002ee <__udivmoddi4+0xe6>
80002ec: deff udf #255 ; 0xff
80002ee: fab2 f382 clz r3, r2
80002f2: 2b00 cmp r3, #0
80002f4: f040 8090 bne.w 8000418 <__udivmoddi4+0x210>
80002f8: 1a8a subs r2, r1, r2
80002fa: ea4f 471c mov.w r7, ip, lsr #16
80002fe: fa1f fe8c uxth.w lr, ip
8000302: 2101 movs r1, #1
8000304: fbb2 f5f7 udiv r5, r2, r7
8000308: fb07 2015 mls r0, r7, r5, r2
800030c: 0c22 lsrs r2, r4, #16
800030e: ea42 4200 orr.w r2, r2, r0, lsl #16
8000312: fb0e f005 mul.w r0, lr, r5
8000316: 4290 cmp r0, r2
8000318: d908 bls.n 800032c <__udivmoddi4+0x124>
800031a: eb1c 0202 adds.w r2, ip, r2
800031e: f105 38ff add.w r8, r5, #4294967295
8000322: d202 bcs.n 800032a <__udivmoddi4+0x122>
8000324: 4290 cmp r0, r2
8000326: f200 80cb bhi.w 80004c0 <__udivmoddi4+0x2b8>
800032a: 4645 mov r5, r8
800032c: 1a12 subs r2, r2, r0
800032e: b2a4 uxth r4, r4
8000330: fbb2 f0f7 udiv r0, r2, r7
8000334: fb07 2210 mls r2, r7, r0, r2
8000338: ea44 4402 orr.w r4, r4, r2, lsl #16
800033c: fb0e fe00 mul.w lr, lr, r0
8000340: 45a6 cmp lr, r4
8000342: d908 bls.n 8000356 <__udivmoddi4+0x14e>
8000344: eb1c 0404 adds.w r4, ip, r4
8000348: f100 32ff add.w r2, r0, #4294967295
800034c: d202 bcs.n 8000354 <__udivmoddi4+0x14c>
800034e: 45a6 cmp lr, r4
8000350: f200 80bb bhi.w 80004ca <__udivmoddi4+0x2c2>
8000354: 4610 mov r0, r2
8000356: eba4 040e sub.w r4, r4, lr
800035a: ea40 4005 orr.w r0, r0, r5, lsl #16
800035e: e79f b.n 80002a0 <__udivmoddi4+0x98>
8000360: f1c1 0720 rsb r7, r1, #32
8000364: 408b lsls r3, r1
8000366: fa22 fc07 lsr.w ip, r2, r7
800036a: ea4c 0c03 orr.w ip, ip, r3
800036e: fa05 f401 lsl.w r4, r5, r1
8000372: fa20 f307 lsr.w r3, r0, r7
8000376: 40fd lsrs r5, r7
8000378: ea4f 491c mov.w r9, ip, lsr #16
800037c: 4323 orrs r3, r4
800037e: fbb5 f8f9 udiv r8, r5, r9
8000382: fa1f fe8c uxth.w lr, ip
8000386: fb09 5518 mls r5, r9, r8, r5
800038a: 0c1c lsrs r4, r3, #16
800038c: ea44 4405 orr.w r4, r4, r5, lsl #16
8000390: fb08 f50e mul.w r5, r8, lr
8000394: 42a5 cmp r5, r4
8000396: fa02 f201 lsl.w r2, r2, r1
800039a: fa00 f001 lsl.w r0, r0, r1
800039e: d90b bls.n 80003b8 <__udivmoddi4+0x1b0>
80003a0: eb1c 0404 adds.w r4, ip, r4
80003a4: f108 3aff add.w sl, r8, #4294967295
80003a8: f080 8088 bcs.w 80004bc <__udivmoddi4+0x2b4>
80003ac: 42a5 cmp r5, r4
80003ae: f240 8085 bls.w 80004bc <__udivmoddi4+0x2b4>
80003b2: f1a8 0802 sub.w r8, r8, #2
80003b6: 4464 add r4, ip
80003b8: 1b64 subs r4, r4, r5
80003ba: b29d uxth r5, r3
80003bc: fbb4 f3f9 udiv r3, r4, r9
80003c0: fb09 4413 mls r4, r9, r3, r4
80003c4: ea45 4404 orr.w r4, r5, r4, lsl #16
80003c8: fb03 fe0e mul.w lr, r3, lr
80003cc: 45a6 cmp lr, r4
80003ce: d908 bls.n 80003e2 <__udivmoddi4+0x1da>
80003d0: eb1c 0404 adds.w r4, ip, r4
80003d4: f103 35ff add.w r5, r3, #4294967295
80003d8: d26c bcs.n 80004b4 <__udivmoddi4+0x2ac>
80003da: 45a6 cmp lr, r4
80003dc: d96a bls.n 80004b4 <__udivmoddi4+0x2ac>
80003de: 3b02 subs r3, #2
80003e0: 4464 add r4, ip
80003e2: ea43 4308 orr.w r3, r3, r8, lsl #16
80003e6: fba3 9502 umull r9, r5, r3, r2
80003ea: eba4 040e sub.w r4, r4, lr
80003ee: 42ac cmp r4, r5
80003f0: 46c8 mov r8, r9
80003f2: 46ae mov lr, r5
80003f4: d356 bcc.n 80004a4 <__udivmoddi4+0x29c>
80003f6: d053 beq.n 80004a0 <__udivmoddi4+0x298>
80003f8: b156 cbz r6, 8000410 <__udivmoddi4+0x208>
80003fa: ebb0 0208 subs.w r2, r0, r8
80003fe: eb64 040e sbc.w r4, r4, lr
8000402: fa04 f707 lsl.w r7, r4, r7
8000406: 40ca lsrs r2, r1
8000408: 40cc lsrs r4, r1
800040a: 4317 orrs r7, r2
800040c: e9c6 7400 strd r7, r4, [r6]
8000410: 4618 mov r0, r3
8000412: 2100 movs r1, #0
8000414: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000418: f1c3 0120 rsb r1, r3, #32
800041c: fa02 fc03 lsl.w ip, r2, r3
8000420: fa20 f201 lsr.w r2, r0, r1
8000424: fa25 f101 lsr.w r1, r5, r1
8000428: 409d lsls r5, r3
800042a: 432a orrs r2, r5
800042c: ea4f 471c mov.w r7, ip, lsr #16
8000430: fa1f fe8c uxth.w lr, ip
8000434: fbb1 f0f7 udiv r0, r1, r7
8000438: fb07 1510 mls r5, r7, r0, r1
800043c: 0c11 lsrs r1, r2, #16
800043e: ea41 4105 orr.w r1, r1, r5, lsl #16
8000442: fb00 f50e mul.w r5, r0, lr
8000446: 428d cmp r5, r1
8000448: fa04 f403 lsl.w r4, r4, r3
800044c: d908 bls.n 8000460 <__udivmoddi4+0x258>
800044e: eb1c 0101 adds.w r1, ip, r1
8000452: f100 38ff add.w r8, r0, #4294967295
8000456: d22f bcs.n 80004b8 <__udivmoddi4+0x2b0>
8000458: 428d cmp r5, r1
800045a: d92d bls.n 80004b8 <__udivmoddi4+0x2b0>
800045c: 3802 subs r0, #2
800045e: 4461 add r1, ip
8000460: 1b49 subs r1, r1, r5
8000462: b292 uxth r2, r2
8000464: fbb1 f5f7 udiv r5, r1, r7
8000468: fb07 1115 mls r1, r7, r5, r1
800046c: ea42 4201 orr.w r2, r2, r1, lsl #16
8000470: fb05 f10e mul.w r1, r5, lr
8000474: 4291 cmp r1, r2
8000476: d908 bls.n 800048a <__udivmoddi4+0x282>
8000478: eb1c 0202 adds.w r2, ip, r2
800047c: f105 38ff add.w r8, r5, #4294967295
8000480: d216 bcs.n 80004b0 <__udivmoddi4+0x2a8>
8000482: 4291 cmp r1, r2
8000484: d914 bls.n 80004b0 <__udivmoddi4+0x2a8>
8000486: 3d02 subs r5, #2
8000488: 4462 add r2, ip
800048a: 1a52 subs r2, r2, r1
800048c: ea45 4100 orr.w r1, r5, r0, lsl #16
8000490: e738 b.n 8000304 <__udivmoddi4+0xfc>
8000492: 4631 mov r1, r6
8000494: 4630 mov r0, r6
8000496: e708 b.n 80002aa <__udivmoddi4+0xa2>
8000498: 4639 mov r1, r7
800049a: e6e6 b.n 800026a <__udivmoddi4+0x62>
800049c: 4610 mov r0, r2
800049e: e6fb b.n 8000298 <__udivmoddi4+0x90>
80004a0: 4548 cmp r0, r9
80004a2: d2a9 bcs.n 80003f8 <__udivmoddi4+0x1f0>
80004a4: ebb9 0802 subs.w r8, r9, r2
80004a8: eb65 0e0c sbc.w lr, r5, ip
80004ac: 3b01 subs r3, #1
80004ae: e7a3 b.n 80003f8 <__udivmoddi4+0x1f0>
80004b0: 4645 mov r5, r8
80004b2: e7ea b.n 800048a <__udivmoddi4+0x282>
80004b4: 462b mov r3, r5
80004b6: e794 b.n 80003e2 <__udivmoddi4+0x1da>
80004b8: 4640 mov r0, r8
80004ba: e7d1 b.n 8000460 <__udivmoddi4+0x258>
80004bc: 46d0 mov r8, sl
80004be: e77b b.n 80003b8 <__udivmoddi4+0x1b0>
80004c0: 3d02 subs r5, #2
80004c2: 4462 add r2, ip
80004c4: e732 b.n 800032c <__udivmoddi4+0x124>
80004c6: 4608 mov r0, r1
80004c8: e70a b.n 80002e0 <__udivmoddi4+0xd8>
80004ca: 4464 add r4, ip
80004cc: 3802 subs r0, #2
80004ce: e742 b.n 8000356 <__udivmoddi4+0x14e>
080004d0 <__aeabi_idiv0>:
80004d0: 4770 bx lr
80004d2: bf00 nop
080004d4 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80004d4: b580 push {r7, lr}
80004d6: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();;
80004d8: f000 fa24 bl 8000924 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80004dc: f000 f844 bl 8000568 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80004e0: f000 f8d6 bl 8000690 <MX_GPIO_Init>
MX_USART2_UART_Init();
80004e4: f000 f8aa bl 800063c <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
memset(uart_buffer,0,10);
80004e8: 220a movs r2, #10
80004ea: 2100 movs r1, #0
80004ec: 481a ldr r0, [pc, #104] ; (8000558 <main+0x84>)
80004ee: f001 fd79 bl 8001fe4 <memset>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1)
{
/* USER CODE END WHILE */
if(HAL_UART_Receive(&huart2, uart_buffer+uart_index, 1, 250) == HAL_OK) {
80004f2: 4b1a ldr r3, [pc, #104] ; (800055c <main+0x88>)
80004f4: 781b ldrb r3, [r3, #0]
80004f6: 461a mov r2, r3
80004f8: 4b17 ldr r3, [pc, #92] ; (8000558 <main+0x84>)
80004fa: 18d1 adds r1, r2, r3
80004fc: 23fa movs r3, #250 ; 0xfa
80004fe: 2201 movs r2, #1
8000500: 4817 ldr r0, [pc, #92] ; (8000560 <main+0x8c>)
8000502: f001 f9ea bl 80018da <HAL_UART_Receive>
8000506: 4603 mov r3, r0
8000508: 2b00 cmp r3, #0
800050a: d1f2 bne.n 80004f2 <main+0x1e>
uart_index++;
800050c: 4b13 ldr r3, [pc, #76] ; (800055c <main+0x88>)
800050e: 781b ldrb r3, [r3, #0]
8000510: 3301 adds r3, #1
8000512: b2da uxtb r2, r3
8000514: 4b11 ldr r3, [pc, #68] ; (800055c <main+0x88>)
8000516: 701a strb r2, [r3, #0]
if(uart_buffer[uart_index-1] == 0xFF) {
8000518: 4b10 ldr r3, [pc, #64] ; (800055c <main+0x88>)
800051a: 781b ldrb r3, [r3, #0]
800051c: 3b01 subs r3, #1
800051e: 4a0e ldr r2, [pc, #56] ; (8000558 <main+0x84>)
8000520: 5cd3 ldrb r3, [r2, r3]
8000522: 2bff cmp r3, #255 ; 0xff
8000524: d1e5 bne.n 80004f2 <main+0x1e>
if(uart_index>1) {
8000526: 4b0d ldr r3, [pc, #52] ; (800055c <main+0x88>)
8000528: 781b ldrb r3, [r3, #0]
800052a: 2b01 cmp r3, #1
800052c: d90a bls.n 8000544 <main+0x70>
if(uart_buffer[0]==0x00) {
800052e: 4b0a ldr r3, [pc, #40] ; (8000558 <main+0x84>)
8000530: 781b ldrb r3, [r3, #0]
8000532: 2b00 cmp r3, #0
8000534: d106 bne.n 8000544 <main+0x70>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, uart_buffer[1]);
8000536: 4b08 ldr r3, [pc, #32] ; (8000558 <main+0x84>)
8000538: 785b ldrb r3, [r3, #1]
800053a: 461a mov r2, r3
800053c: 2120 movs r1, #32
800053e: 4809 ldr r0, [pc, #36] ; (8000564 <main+0x90>)
8000540: f000 fccc bl 8000edc <HAL_GPIO_WritePin>
}
}
uart_index = 0;
8000544: 4b05 ldr r3, [pc, #20] ; (800055c <main+0x88>)
8000546: 2200 movs r2, #0
8000548: 701a strb r2, [r3, #0]
memset(uart_buffer,0,10);
800054a: 220a movs r2, #10
800054c: 2100 movs r1, #0
800054e: 4802 ldr r0, [pc, #8] ; (8000558 <main+0x84>)
8000550: f001 fd48 bl 8001fe4 <memset>
if(HAL_UART_Receive(&huart2, uart_buffer+uart_index, 1, 250) == HAL_OK) {
8000554: e7cd b.n 80004f2 <main+0x1e>
8000556: bf00 nop
8000558: 2000006c .word 0x2000006c
800055c: 20000076 .word 0x20000076
8000560: 20000028 .word 0x20000028
8000564: 40020000 .word 0x40020000
08000568 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000568: b580 push {r7, lr}
800056a: b094 sub sp, #80 ; 0x50
800056c: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800056e: f107 0320 add.w r3, r7, #32
8000572: 2230 movs r2, #48 ; 0x30
8000574: 2100 movs r1, #0
8000576: 4618 mov r0, r3
8000578: f001 fd34 bl 8001fe4 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800057c: f107 030c add.w r3, r7, #12
8000580: 2200 movs r2, #0
8000582: 601a str r2, [r3, #0]
8000584: 605a str r2, [r3, #4]
8000586: 609a str r2, [r3, #8]
8000588: 60da str r2, [r3, #12]
800058a: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
800058c: 2300 movs r3, #0
800058e: 60bb str r3, [r7, #8]
8000590: 4b28 ldr r3, [pc, #160] ; (8000634 <SystemClock_Config+0xcc>)
8000592: 6c1b ldr r3, [r3, #64] ; 0x40
8000594: 4a27 ldr r2, [pc, #156] ; (8000634 <SystemClock_Config+0xcc>)
8000596: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
800059a: 6413 str r3, [r2, #64] ; 0x40
800059c: 4b25 ldr r3, [pc, #148] ; (8000634 <SystemClock_Config+0xcc>)
800059e: 6c1b ldr r3, [r3, #64] ; 0x40
80005a0: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80005a4: 60bb str r3, [r7, #8]
80005a6: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
80005a8: 2300 movs r3, #0
80005aa: 607b str r3, [r7, #4]
80005ac: 4b22 ldr r3, [pc, #136] ; (8000638 <SystemClock_Config+0xd0>)
80005ae: 681b ldr r3, [r3, #0]
80005b0: 4a21 ldr r2, [pc, #132] ; (8000638 <SystemClock_Config+0xd0>)
80005b2: f443 4340 orr.w r3, r3, #49152 ; 0xc000
80005b6: 6013 str r3, [r2, #0]
80005b8: 4b1f ldr r3, [pc, #124] ; (8000638 <SystemClock_Config+0xd0>)
80005ba: 681b ldr r3, [r3, #0]
80005bc: f403 4340 and.w r3, r3, #49152 ; 0xc000
80005c0: 607b str r3, [r7, #4]
80005c2: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
80005c4: 2302 movs r3, #2
80005c6: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80005c8: 2301 movs r3, #1
80005ca: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80005cc: 2310 movs r3, #16
80005ce: 633b str r3, [r7, #48] ; 0x30
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80005d0: 2302 movs r3, #2
80005d2: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
80005d4: 2300 movs r3, #0
80005d6: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLM = 16;
80005d8: 2310 movs r3, #16
80005da: 643b str r3, [r7, #64] ; 0x40
RCC_OscInitStruct.PLL.PLLN = 336;
80005dc: f44f 73a8 mov.w r3, #336 ; 0x150
80005e0: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
80005e2: 2304 movs r3, #4
80005e4: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLQ = 4;
80005e6: 2304 movs r3, #4
80005e8: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80005ea: f107 0320 add.w r3, r7, #32
80005ee: 4618 mov r0, r3
80005f0: f000 fc8e bl 8000f10 <HAL_RCC_OscConfig>
80005f4: 4603 mov r3, r0
80005f6: 2b00 cmp r3, #0
80005f8: d001 beq.n 80005fe <SystemClock_Config+0x96>
{
Error_Handler();
80005fa: f000 f8b7 bl 800076c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80005fe: 230f movs r3, #15
8000600: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
8000602: 2302 movs r3, #2
8000604: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000606: 2300 movs r3, #0
8000608: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
800060a: f44f 5380 mov.w r3, #4096 ; 0x1000
800060e: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
8000610: 2300 movs r3, #0
8000612: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
8000614: f107 030c add.w r3, r7, #12
8000618: 2102 movs r1, #2
800061a: 4618 mov r0, r3
800061c: f000 fef0 bl 8001400 <HAL_RCC_ClockConfig>
8000620: 4603 mov r3, r0
8000622: 2b00 cmp r3, #0
8000624: d001 beq.n 800062a <SystemClock_Config+0xc2>
{
Error_Handler();
8000626: f000 f8a1 bl 800076c <Error_Handler>
}
}
800062a: bf00 nop
800062c: 3750 adds r7, #80 ; 0x50
800062e: 46bd mov sp, r7
8000630: bd80 pop {r7, pc}
8000632: bf00 nop
8000634: 40023800 .word 0x40023800
8000638: 40007000 .word 0x40007000
0800063c <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
800063c: b580 push {r7, lr}
800063e: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
8000640: 4b11 ldr r3, [pc, #68] ; (8000688 <MX_USART2_UART_Init+0x4c>)
8000642: 4a12 ldr r2, [pc, #72] ; (800068c <MX_USART2_UART_Init+0x50>)
8000644: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
8000646: 4b10 ldr r3, [pc, #64] ; (8000688 <MX_USART2_UART_Init+0x4c>)
8000648: f44f 32e1 mov.w r2, #115200 ; 0x1c200
800064c: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
800064e: 4b0e ldr r3, [pc, #56] ; (8000688 <MX_USART2_UART_Init+0x4c>)
8000650: 2200 movs r2, #0
8000652: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8000654: 4b0c ldr r3, [pc, #48] ; (8000688 <MX_USART2_UART_Init+0x4c>)
8000656: 2200 movs r2, #0
8000658: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
800065a: 4b0b ldr r3, [pc, #44] ; (8000688 <MX_USART2_UART_Init+0x4c>)
800065c: 2200 movs r2, #0
800065e: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
8000660: 4b09 ldr r3, [pc, #36] ; (8000688 <MX_USART2_UART_Init+0x4c>)
8000662: 220c movs r2, #12
8000664: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000666: 4b08 ldr r3, [pc, #32] ; (8000688 <MX_USART2_UART_Init+0x4c>)
8000668: 2200 movs r2, #0
800066a: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
800066c: 4b06 ldr r3, [pc, #24] ; (8000688 <MX_USART2_UART_Init+0x4c>)
800066e: 2200 movs r2, #0
8000670: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK)
8000672: 4805 ldr r0, [pc, #20] ; (8000688 <MX_USART2_UART_Init+0x4c>)
8000674: f001 f8e4 bl 8001840 <HAL_UART_Init>
8000678: 4603 mov r3, r0
800067a: 2b00 cmp r3, #0
800067c: d001 beq.n 8000682 <MX_USART2_UART_Init+0x46>
{
Error_Handler();
800067e: f000 f875 bl 800076c <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
8000682: bf00 nop
8000684: bd80 pop {r7, pc}
8000686: bf00 nop
8000688: 20000028 .word 0x20000028
800068c: 40004400 .word 0x40004400
08000690 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000690: b580 push {r7, lr}
8000692: b08a sub sp, #40 ; 0x28
8000694: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000696: f107 0314 add.w r3, r7, #20
800069a: 2200 movs r2, #0
800069c: 601a str r2, [r3, #0]
800069e: 605a str r2, [r3, #4]
80006a0: 609a str r2, [r3, #8]
80006a2: 60da str r2, [r3, #12]
80006a4: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80006a6: 2300 movs r3, #0
80006a8: 613b str r3, [r7, #16]
80006aa: 4b2d ldr r3, [pc, #180] ; (8000760 <MX_GPIO_Init+0xd0>)
80006ac: 6b1b ldr r3, [r3, #48] ; 0x30
80006ae: 4a2c ldr r2, [pc, #176] ; (8000760 <MX_GPIO_Init+0xd0>)
80006b0: f043 0304 orr.w r3, r3, #4
80006b4: 6313 str r3, [r2, #48] ; 0x30
80006b6: 4b2a ldr r3, [pc, #168] ; (8000760 <MX_GPIO_Init+0xd0>)
80006b8: 6b1b ldr r3, [r3, #48] ; 0x30
80006ba: f003 0304 and.w r3, r3, #4
80006be: 613b str r3, [r7, #16]
80006c0: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
80006c2: 2300 movs r3, #0
80006c4: 60fb str r3, [r7, #12]
80006c6: 4b26 ldr r3, [pc, #152] ; (8000760 <MX_GPIO_Init+0xd0>)
80006c8: 6b1b ldr r3, [r3, #48] ; 0x30
80006ca: 4a25 ldr r2, [pc, #148] ; (8000760 <MX_GPIO_Init+0xd0>)
80006cc: f043 0380 orr.w r3, r3, #128 ; 0x80
80006d0: 6313 str r3, [r2, #48] ; 0x30
80006d2: 4b23 ldr r3, [pc, #140] ; (8000760 <MX_GPIO_Init+0xd0>)
80006d4: 6b1b ldr r3, [r3, #48] ; 0x30
80006d6: f003 0380 and.w r3, r3, #128 ; 0x80
80006da: 60fb str r3, [r7, #12]
80006dc: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80006de: 2300 movs r3, #0
80006e0: 60bb str r3, [r7, #8]
80006e2: 4b1f ldr r3, [pc, #124] ; (8000760 <MX_GPIO_Init+0xd0>)
80006e4: 6b1b ldr r3, [r3, #48] ; 0x30
80006e6: 4a1e ldr r2, [pc, #120] ; (8000760 <MX_GPIO_Init+0xd0>)
80006e8: f043 0301 orr.w r3, r3, #1
80006ec: 6313 str r3, [r2, #48] ; 0x30
80006ee: 4b1c ldr r3, [pc, #112] ; (8000760 <MX_GPIO_Init+0xd0>)
80006f0: 6b1b ldr r3, [r3, #48] ; 0x30
80006f2: f003 0301 and.w r3, r3, #1
80006f6: 60bb str r3, [r7, #8]
80006f8: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
80006fa: 2300 movs r3, #0
80006fc: 607b str r3, [r7, #4]
80006fe: 4b18 ldr r3, [pc, #96] ; (8000760 <MX_GPIO_Init+0xd0>)
8000700: 6b1b ldr r3, [r3, #48] ; 0x30
8000702: 4a17 ldr r2, [pc, #92] ; (8000760 <MX_GPIO_Init+0xd0>)
8000704: f043 0302 orr.w r3, r3, #2
8000708: 6313 str r3, [r2, #48] ; 0x30
800070a: 4b15 ldr r3, [pc, #84] ; (8000760 <MX_GPIO_Init+0xd0>)
800070c: 6b1b ldr r3, [r3, #48] ; 0x30
800070e: f003 0302 and.w r3, r3, #2
8000712: 607b str r3, [r7, #4]
8000714: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8000716: 2200 movs r2, #0
8000718: 2120 movs r1, #32
800071a: 4812 ldr r0, [pc, #72] ; (8000764 <MX_GPIO_Init+0xd4>)
800071c: f000 fbde bl 8000edc <HAL_GPIO_WritePin>
/*Configure GPIO pin : B1_Pin */
GPIO_InitStruct.Pin = B1_Pin;
8000720: f44f 5300 mov.w r3, #8192 ; 0x2000
8000724: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
8000726: f44f 1304 mov.w r3, #2162688 ; 0x210000
800072a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800072c: 2300 movs r3, #0
800072e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
8000730: f107 0314 add.w r3, r7, #20
8000734: 4619 mov r1, r3
8000736: 480c ldr r0, [pc, #48] ; (8000768 <MX_GPIO_Init+0xd8>)
8000738: f000 fa4c bl 8000bd4 <HAL_GPIO_Init>
/*Configure GPIO pin : LD2_Pin */
GPIO_InitStruct.Pin = LD2_Pin;
800073c: 2320 movs r3, #32
800073e: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000740: 2301 movs r3, #1
8000742: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000744: 2300 movs r3, #0
8000746: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000748: 2300 movs r3, #0
800074a: 623b str r3, [r7, #32]
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
800074c: f107 0314 add.w r3, r7, #20
8000750: 4619 mov r1, r3
8000752: 4804 ldr r0, [pc, #16] ; (8000764 <MX_GPIO_Init+0xd4>)
8000754: f000 fa3e bl 8000bd4 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8000758: bf00 nop
800075a: 3728 adds r7, #40 ; 0x28
800075c: 46bd mov sp, r7
800075e: bd80 pop {r7, pc}
8000760: 40023800 .word 0x40023800
8000764: 40020000 .word 0x40020000
8000768: 40020800 .word 0x40020800
0800076c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800076c: b480 push {r7}
800076e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000770: b672 cpsid i
}
8000772: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8000774: e7fe b.n 8000774 <Error_Handler+0x8>
...
08000778 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000778: b580 push {r7, lr}
800077a: b082 sub sp, #8
800077c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800077e: 2300 movs r3, #0
8000780: 607b str r3, [r7, #4]
8000782: 4b10 ldr r3, [pc, #64] ; (80007c4 <HAL_MspInit+0x4c>)
8000784: 6c5b ldr r3, [r3, #68] ; 0x44
8000786: 4a0f ldr r2, [pc, #60] ; (80007c4 <HAL_MspInit+0x4c>)
8000788: f443 4380 orr.w r3, r3, #16384 ; 0x4000
800078c: 6453 str r3, [r2, #68] ; 0x44
800078e: 4b0d ldr r3, [pc, #52] ; (80007c4 <HAL_MspInit+0x4c>)
8000790: 6c5b ldr r3, [r3, #68] ; 0x44
8000792: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000796: 607b str r3, [r7, #4]
8000798: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800079a: 2300 movs r3, #0
800079c: 603b str r3, [r7, #0]
800079e: 4b09 ldr r3, [pc, #36] ; (80007c4 <HAL_MspInit+0x4c>)
80007a0: 6c1b ldr r3, [r3, #64] ; 0x40
80007a2: 4a08 ldr r2, [pc, #32] ; (80007c4 <HAL_MspInit+0x4c>)
80007a4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80007a8: 6413 str r3, [r2, #64] ; 0x40
80007aa: 4b06 ldr r3, [pc, #24] ; (80007c4 <HAL_MspInit+0x4c>)
80007ac: 6c1b ldr r3, [r3, #64] ; 0x40
80007ae: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80007b2: 603b str r3, [r7, #0]
80007b4: 683b ldr r3, [r7, #0]
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
80007b6: 2007 movs r0, #7
80007b8: f000 f9d8 bl 8000b6c <HAL_NVIC_SetPriorityGrouping>
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80007bc: bf00 nop
80007be: 3708 adds r7, #8
80007c0: 46bd mov sp, r7
80007c2: bd80 pop {r7, pc}
80007c4: 40023800 .word 0x40023800
080007c8 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
80007c8: b580 push {r7, lr}
80007ca: b08a sub sp, #40 ; 0x28
80007cc: af00 add r7, sp, #0
80007ce: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80007d0: f107 0314 add.w r3, r7, #20
80007d4: 2200 movs r2, #0
80007d6: 601a str r2, [r3, #0]
80007d8: 605a str r2, [r3, #4]
80007da: 609a str r2, [r3, #8]
80007dc: 60da str r2, [r3, #12]
80007de: 611a str r2, [r3, #16]
if(huart->Instance==USART2)
80007e0: 687b ldr r3, [r7, #4]
80007e2: 681b ldr r3, [r3, #0]
80007e4: 4a19 ldr r2, [pc, #100] ; (800084c <HAL_UART_MspInit+0x84>)
80007e6: 4293 cmp r3, r2
80007e8: d12b bne.n 8000842 <HAL_UART_MspInit+0x7a>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
80007ea: 2300 movs r3, #0
80007ec: 613b str r3, [r7, #16]
80007ee: 4b18 ldr r3, [pc, #96] ; (8000850 <HAL_UART_MspInit+0x88>)
80007f0: 6c1b ldr r3, [r3, #64] ; 0x40
80007f2: 4a17 ldr r2, [pc, #92] ; (8000850 <HAL_UART_MspInit+0x88>)
80007f4: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80007f8: 6413 str r3, [r2, #64] ; 0x40
80007fa: 4b15 ldr r3, [pc, #84] ; (8000850 <HAL_UART_MspInit+0x88>)
80007fc: 6c1b ldr r3, [r3, #64] ; 0x40
80007fe: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000802: 613b str r3, [r7, #16]
8000804: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000806: 2300 movs r3, #0
8000808: 60fb str r3, [r7, #12]
800080a: 4b11 ldr r3, [pc, #68] ; (8000850 <HAL_UART_MspInit+0x88>)
800080c: 6b1b ldr r3, [r3, #48] ; 0x30
800080e: 4a10 ldr r2, [pc, #64] ; (8000850 <HAL_UART_MspInit+0x88>)
8000810: f043 0301 orr.w r3, r3, #1
8000814: 6313 str r3, [r2, #48] ; 0x30
8000816: 4b0e ldr r3, [pc, #56] ; (8000850 <HAL_UART_MspInit+0x88>)
8000818: 6b1b ldr r3, [r3, #48] ; 0x30
800081a: f003 0301 and.w r3, r3, #1
800081e: 60fb str r3, [r7, #12]
8000820: 68fb ldr r3, [r7, #12]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
8000822: 230c movs r3, #12
8000824: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000826: 2302 movs r3, #2
8000828: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800082a: 2300 movs r3, #0
800082c: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800082e: 2303 movs r3, #3
8000830: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8000832: 2307 movs r3, #7
8000834: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000836: f107 0314 add.w r3, r7, #20
800083a: 4619 mov r1, r3
800083c: 4805 ldr r0, [pc, #20] ; (8000854 <HAL_UART_MspInit+0x8c>)
800083e: f000 f9c9 bl 8000bd4 <HAL_GPIO_Init>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
8000842: bf00 nop
8000844: 3728 adds r7, #40 ; 0x28
8000846: 46bd mov sp, r7
8000848: bd80 pop {r7, pc}
800084a: bf00 nop
800084c: 40004400 .word 0x40004400
8000850: 40023800 .word 0x40023800
8000854: 40020000 .word 0x40020000
08000858 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000858: b480 push {r7}
800085a: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
800085c: e7fe b.n 800085c <NMI_Handler+0x4>
0800085e <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800085e: b480 push {r7}
8000860: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000862: e7fe b.n 8000862 <HardFault_Handler+0x4>
08000864 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000864: b480 push {r7}
8000866: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000868: e7fe b.n 8000868 <MemManage_Handler+0x4>
0800086a <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800086a: b480 push {r7}
800086c: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
800086e: e7fe b.n 800086e <BusFault_Handler+0x4>
08000870 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000870: b480 push {r7}
8000872: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000874: e7fe b.n 8000874 <UsageFault_Handler+0x4>
08000876 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
8000876: b480 push {r7}
8000878: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800087a: bf00 nop
800087c: 46bd mov sp, r7
800087e: f85d 7b04 ldr.w r7, [sp], #4
8000882: 4770 bx lr
08000884 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000884: b480 push {r7}
8000886: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000888: bf00 nop
800088a: 46bd mov sp, r7
800088c: f85d 7b04 ldr.w r7, [sp], #4
8000890: 4770 bx lr
08000892 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8000892: b480 push {r7}
8000894: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8000896: bf00 nop
8000898: 46bd mov sp, r7
800089a: f85d 7b04 ldr.w r7, [sp], #4
800089e: 4770 bx lr
080008a0 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80008a0: b580 push {r7, lr}
80008a2: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80008a4: f000 f890 bl 80009c8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80008a8: bf00 nop
80008aa: bd80 pop {r7, pc}
080008ac <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
80008ac: b480 push {r7}
80008ae: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
80008b0: 4b06 ldr r3, [pc, #24] ; (80008cc <SystemInit+0x20>)
80008b2: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80008b6: 4a05 ldr r2, [pc, #20] ; (80008cc <SystemInit+0x20>)
80008b8: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
80008bc: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80008c0: bf00 nop
80008c2: 46bd mov sp, r7
80008c4: f85d 7b04 ldr.w r7, [sp], #4
80008c8: 4770 bx lr
80008ca: bf00 nop
80008cc: e000ed00 .word 0xe000ed00
080008d0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
80008d0: f8df d034 ldr.w sp, [pc, #52] ; 8000908 <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80008d4: 480d ldr r0, [pc, #52] ; (800090c <LoopFillZerobss+0x16>)
ldr r1, =_edata
80008d6: 490e ldr r1, [pc, #56] ; (8000910 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
80008d8: 4a0e ldr r2, [pc, #56] ; (8000914 <LoopFillZerobss+0x1e>)
movs r3, #0
80008da: 2300 movs r3, #0
b LoopCopyDataInit
80008dc: e002 b.n 80008e4 <LoopCopyDataInit>
080008de <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80008de: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80008e0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80008e2: 3304 adds r3, #4
080008e4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80008e4: 18c4 adds r4, r0, r3
cmp r4, r1
80008e6: 428c cmp r4, r1
bcc CopyDataInit
80008e8: d3f9 bcc.n 80008de <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80008ea: 4a0b ldr r2, [pc, #44] ; (8000918 <LoopFillZerobss+0x22>)
ldr r4, =_ebss
80008ec: 4c0b ldr r4, [pc, #44] ; (800091c <LoopFillZerobss+0x26>)
movs r3, #0
80008ee: 2300 movs r3, #0
b LoopFillZerobss
80008f0: e001 b.n 80008f6 <LoopFillZerobss>
080008f2 <FillZerobss>:
FillZerobss:
str r3, [r2]
80008f2: 6013 str r3, [r2, #0]
adds r2, r2, #4
80008f4: 3204 adds r2, #4
080008f6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80008f6: 42a2 cmp r2, r4
bcc FillZerobss
80008f8: d3fb bcc.n 80008f2 <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
80008fa: f7ff ffd7 bl 80008ac <SystemInit>
/* Call static constructors */
bl __libc_init_array
80008fe: f001 fb79 bl 8001ff4 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000902: f7ff fde7 bl 80004d4 <main>
bx lr
8000906: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8000908: 20020000 .word 0x20020000
ldr r0, =_sdata
800090c: 20000000 .word 0x20000000
ldr r1, =_edata
8000910: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000914: 0800207c .word 0x0800207c
ldr r2, =_sbss
8000918: 2000000c .word 0x2000000c
ldr r4, =_ebss
800091c: 2000007c .word 0x2000007c
08000920 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000920: e7fe b.n 8000920 <ADC_IRQHandler>
...
08000924 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000924: b580 push {r7, lr}
8000926: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8000928: 4b0e ldr r3, [pc, #56] ; (8000964 <HAL_Init+0x40>)
800092a: 681b ldr r3, [r3, #0]
800092c: 4a0d ldr r2, [pc, #52] ; (8000964 <HAL_Init+0x40>)
800092e: f443 7300 orr.w r3, r3, #512 ; 0x200
8000932: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8000934: 4b0b ldr r3, [pc, #44] ; (8000964 <HAL_Init+0x40>)
8000936: 681b ldr r3, [r3, #0]
8000938: 4a0a ldr r2, [pc, #40] ; (8000964 <HAL_Init+0x40>)
800093a: f443 6380 orr.w r3, r3, #1024 ; 0x400
800093e: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000940: 4b08 ldr r3, [pc, #32] ; (8000964 <HAL_Init+0x40>)
8000942: 681b ldr r3, [r3, #0]
8000944: 4a07 ldr r2, [pc, #28] ; (8000964 <HAL_Init+0x40>)
8000946: f443 7380 orr.w r3, r3, #256 ; 0x100
800094a: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
800094c: 2003 movs r0, #3
800094e: f000 f90d bl 8000b6c <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000952: 2000 movs r0, #0
8000954: f000 f808 bl 8000968 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000958: f7ff ff0e bl 8000778 <HAL_MspInit>
/* Return function status */
return HAL_OK;
800095c: 2300 movs r3, #0
}
800095e: 4618 mov r0, r3
8000960: bd80 pop {r7, pc}
8000962: bf00 nop
8000964: 40023c00 .word 0x40023c00
08000968 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000968: b580 push {r7, lr}
800096a: b082 sub sp, #8
800096c: af00 add r7, sp, #0
800096e: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
8000970: 4b12 ldr r3, [pc, #72] ; (80009bc <HAL_InitTick+0x54>)
8000972: 681a ldr r2, [r3, #0]
8000974: 4b12 ldr r3, [pc, #72] ; (80009c0 <HAL_InitTick+0x58>)
8000976: 781b ldrb r3, [r3, #0]
8000978: 4619 mov r1, r3
800097a: f44f 737a mov.w r3, #1000 ; 0x3e8
800097e: fbb3 f3f1 udiv r3, r3, r1
8000982: fbb2 f3f3 udiv r3, r2, r3
8000986: 4618 mov r0, r3
8000988: f000 f917 bl 8000bba <HAL_SYSTICK_Config>
800098c: 4603 mov r3, r0
800098e: 2b00 cmp r3, #0
8000990: d001 beq.n 8000996 <HAL_InitTick+0x2e>
{
return HAL_ERROR;
8000992: 2301 movs r3, #1
8000994: e00e b.n 80009b4 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000996: 687b ldr r3, [r7, #4]
8000998: 2b0f cmp r3, #15
800099a: d80a bhi.n 80009b2 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800099c: 2200 movs r2, #0
800099e: 6879 ldr r1, [r7, #4]
80009a0: f04f 30ff mov.w r0, #4294967295
80009a4: f000 f8ed bl 8000b82 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80009a8: 4a06 ldr r2, [pc, #24] ; (80009c4 <HAL_InitTick+0x5c>)
80009aa: 687b ldr r3, [r7, #4]
80009ac: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80009ae: 2300 movs r3, #0
80009b0: e000 b.n 80009b4 <HAL_InitTick+0x4c>
return HAL_ERROR;
80009b2: 2301 movs r3, #1
}
80009b4: 4618 mov r0, r3
80009b6: 3708 adds r7, #8
80009b8: 46bd mov sp, r7
80009ba: bd80 pop {r7, pc}
80009bc: 20000000 .word 0x20000000
80009c0: 20000008 .word 0x20000008
80009c4: 20000004 .word 0x20000004
080009c8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
80009c8: b480 push {r7}
80009ca: af00 add r7, sp, #0
uwTick += uwTickFreq;
80009cc: 4b06 ldr r3, [pc, #24] ; (80009e8 <HAL_IncTick+0x20>)
80009ce: 781b ldrb r3, [r3, #0]
80009d0: 461a mov r2, r3
80009d2: 4b06 ldr r3, [pc, #24] ; (80009ec <HAL_IncTick+0x24>)
80009d4: 681b ldr r3, [r3, #0]
80009d6: 4413 add r3, r2
80009d8: 4a04 ldr r2, [pc, #16] ; (80009ec <HAL_IncTick+0x24>)
80009da: 6013 str r3, [r2, #0]
}
80009dc: bf00 nop
80009de: 46bd mov sp, r7
80009e0: f85d 7b04 ldr.w r7, [sp], #4
80009e4: 4770 bx lr
80009e6: bf00 nop
80009e8: 20000008 .word 0x20000008
80009ec: 20000078 .word 0x20000078
080009f0 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
80009f0: b480 push {r7}
80009f2: af00 add r7, sp, #0
return uwTick;
80009f4: 4b03 ldr r3, [pc, #12] ; (8000a04 <HAL_GetTick+0x14>)
80009f6: 681b ldr r3, [r3, #0]
}
80009f8: 4618 mov r0, r3
80009fa: 46bd mov sp, r7
80009fc: f85d 7b04 ldr.w r7, [sp], #4
8000a00: 4770 bx lr
8000a02: bf00 nop
8000a04: 20000078 .word 0x20000078
08000a08 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000a08: b480 push {r7}
8000a0a: b085 sub sp, #20
8000a0c: af00 add r7, sp, #0
8000a0e: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000a10: 687b ldr r3, [r7, #4]
8000a12: f003 0307 and.w r3, r3, #7
8000a16: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000a18: 4b0c ldr r3, [pc, #48] ; (8000a4c <__NVIC_SetPriorityGrouping+0x44>)
8000a1a: 68db ldr r3, [r3, #12]
8000a1c: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000a1e: 68ba ldr r2, [r7, #8]
8000a20: f64f 03ff movw r3, #63743 ; 0xf8ff
8000a24: 4013 ands r3, r2
8000a26: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000a28: 68fb ldr r3, [r7, #12]
8000a2a: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000a2c: 68bb ldr r3, [r7, #8]
8000a2e: 4313 orrs r3, r2
reg_value = (reg_value |
8000a30: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000a34: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000a38: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000a3a: 4a04 ldr r2, [pc, #16] ; (8000a4c <__NVIC_SetPriorityGrouping+0x44>)
8000a3c: 68bb ldr r3, [r7, #8]
8000a3e: 60d3 str r3, [r2, #12]
}
8000a40: bf00 nop
8000a42: 3714 adds r7, #20
8000a44: 46bd mov sp, r7
8000a46: f85d 7b04 ldr.w r7, [sp], #4
8000a4a: 4770 bx lr
8000a4c: e000ed00 .word 0xe000ed00
08000a50 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000a50: b480 push {r7}
8000a52: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000a54: 4b04 ldr r3, [pc, #16] ; (8000a68 <__NVIC_GetPriorityGrouping+0x18>)
8000a56: 68db ldr r3, [r3, #12]
8000a58: 0a1b lsrs r3, r3, #8
8000a5a: f003 0307 and.w r3, r3, #7
}
8000a5e: 4618 mov r0, r3
8000a60: 46bd mov sp, r7
8000a62: f85d 7b04 ldr.w r7, [sp], #4
8000a66: 4770 bx lr
8000a68: e000ed00 .word 0xe000ed00
08000a6c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000a6c: b480 push {r7}
8000a6e: b083 sub sp, #12
8000a70: af00 add r7, sp, #0
8000a72: 4603 mov r3, r0
8000a74: 6039 str r1, [r7, #0]
8000a76: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000a78: f997 3007 ldrsb.w r3, [r7, #7]
8000a7c: 2b00 cmp r3, #0
8000a7e: db0a blt.n 8000a96 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000a80: 683b ldr r3, [r7, #0]
8000a82: b2da uxtb r2, r3
8000a84: 490c ldr r1, [pc, #48] ; (8000ab8 <__NVIC_SetPriority+0x4c>)
8000a86: f997 3007 ldrsb.w r3, [r7, #7]
8000a8a: 0112 lsls r2, r2, #4
8000a8c: b2d2 uxtb r2, r2
8000a8e: 440b add r3, r1
8000a90: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000a94: e00a b.n 8000aac <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000a96: 683b ldr r3, [r7, #0]
8000a98: b2da uxtb r2, r3
8000a9a: 4908 ldr r1, [pc, #32] ; (8000abc <__NVIC_SetPriority+0x50>)
8000a9c: 79fb ldrb r3, [r7, #7]
8000a9e: f003 030f and.w r3, r3, #15
8000aa2: 3b04 subs r3, #4
8000aa4: 0112 lsls r2, r2, #4
8000aa6: b2d2 uxtb r2, r2
8000aa8: 440b add r3, r1
8000aaa: 761a strb r2, [r3, #24]
}
8000aac: bf00 nop
8000aae: 370c adds r7, #12
8000ab0: 46bd mov sp, r7
8000ab2: f85d 7b04 ldr.w r7, [sp], #4
8000ab6: 4770 bx lr
8000ab8: e000e100 .word 0xe000e100
8000abc: e000ed00 .word 0xe000ed00
08000ac0 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000ac0: b480 push {r7}
8000ac2: b089 sub sp, #36 ; 0x24
8000ac4: af00 add r7, sp, #0
8000ac6: 60f8 str r0, [r7, #12]
8000ac8: 60b9 str r1, [r7, #8]
8000aca: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000acc: 68fb ldr r3, [r7, #12]
8000ace: f003 0307 and.w r3, r3, #7
8000ad2: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000ad4: 69fb ldr r3, [r7, #28]
8000ad6: f1c3 0307 rsb r3, r3, #7
8000ada: 2b04 cmp r3, #4
8000adc: bf28 it cs
8000ade: 2304 movcs r3, #4
8000ae0: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000ae2: 69fb ldr r3, [r7, #28]
8000ae4: 3304 adds r3, #4
8000ae6: 2b06 cmp r3, #6
8000ae8: d902 bls.n 8000af0 <NVIC_EncodePriority+0x30>
8000aea: 69fb ldr r3, [r7, #28]
8000aec: 3b03 subs r3, #3
8000aee: e000 b.n 8000af2 <NVIC_EncodePriority+0x32>
8000af0: 2300 movs r3, #0
8000af2: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000af4: f04f 32ff mov.w r2, #4294967295
8000af8: 69bb ldr r3, [r7, #24]
8000afa: fa02 f303 lsl.w r3, r2, r3
8000afe: 43da mvns r2, r3
8000b00: 68bb ldr r3, [r7, #8]
8000b02: 401a ands r2, r3
8000b04: 697b ldr r3, [r7, #20]
8000b06: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000b08: f04f 31ff mov.w r1, #4294967295
8000b0c: 697b ldr r3, [r7, #20]
8000b0e: fa01 f303 lsl.w r3, r1, r3
8000b12: 43d9 mvns r1, r3
8000b14: 687b ldr r3, [r7, #4]
8000b16: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000b18: 4313 orrs r3, r2
);
}
8000b1a: 4618 mov r0, r3
8000b1c: 3724 adds r7, #36 ; 0x24
8000b1e: 46bd mov sp, r7
8000b20: f85d 7b04 ldr.w r7, [sp], #4
8000b24: 4770 bx lr
...
08000b28 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000b28: b580 push {r7, lr}
8000b2a: b082 sub sp, #8
8000b2c: af00 add r7, sp, #0
8000b2e: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000b30: 687b ldr r3, [r7, #4]
8000b32: 3b01 subs r3, #1
8000b34: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8000b38: d301 bcc.n 8000b3e <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000b3a: 2301 movs r3, #1
8000b3c: e00f b.n 8000b5e <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000b3e: 4a0a ldr r2, [pc, #40] ; (8000b68 <SysTick_Config+0x40>)
8000b40: 687b ldr r3, [r7, #4]
8000b42: 3b01 subs r3, #1
8000b44: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000b46: 210f movs r1, #15
8000b48: f04f 30ff mov.w r0, #4294967295
8000b4c: f7ff ff8e bl 8000a6c <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000b50: 4b05 ldr r3, [pc, #20] ; (8000b68 <SysTick_Config+0x40>)
8000b52: 2200 movs r2, #0
8000b54: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000b56: 4b04 ldr r3, [pc, #16] ; (8000b68 <SysTick_Config+0x40>)
8000b58: 2207 movs r2, #7
8000b5a: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000b5c: 2300 movs r3, #0
}
8000b5e: 4618 mov r0, r3
8000b60: 3708 adds r7, #8
8000b62: 46bd mov sp, r7
8000b64: bd80 pop {r7, pc}
8000b66: bf00 nop
8000b68: e000e010 .word 0xe000e010
08000b6c <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000b6c: b580 push {r7, lr}
8000b6e: b082 sub sp, #8
8000b70: af00 add r7, sp, #0
8000b72: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000b74: 6878 ldr r0, [r7, #4]
8000b76: f7ff ff47 bl 8000a08 <__NVIC_SetPriorityGrouping>
}
8000b7a: bf00 nop
8000b7c: 3708 adds r7, #8
8000b7e: 46bd mov sp, r7
8000b80: bd80 pop {r7, pc}
08000b82 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000b82: b580 push {r7, lr}
8000b84: b086 sub sp, #24
8000b86: af00 add r7, sp, #0
8000b88: 4603 mov r3, r0
8000b8a: 60b9 str r1, [r7, #8]
8000b8c: 607a str r2, [r7, #4]
8000b8e: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8000b90: 2300 movs r3, #0
8000b92: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000b94: f7ff ff5c bl 8000a50 <__NVIC_GetPriorityGrouping>
8000b98: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000b9a: 687a ldr r2, [r7, #4]
8000b9c: 68b9 ldr r1, [r7, #8]
8000b9e: 6978 ldr r0, [r7, #20]
8000ba0: f7ff ff8e bl 8000ac0 <NVIC_EncodePriority>
8000ba4: 4602 mov r2, r0
8000ba6: f997 300f ldrsb.w r3, [r7, #15]
8000baa: 4611 mov r1, r2
8000bac: 4618 mov r0, r3
8000bae: f7ff ff5d bl 8000a6c <__NVIC_SetPriority>
}
8000bb2: bf00 nop
8000bb4: 3718 adds r7, #24
8000bb6: 46bd mov sp, r7
8000bb8: bd80 pop {r7, pc}
08000bba <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000bba: b580 push {r7, lr}
8000bbc: b082 sub sp, #8
8000bbe: af00 add r7, sp, #0
8000bc0: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000bc2: 6878 ldr r0, [r7, #4]
8000bc4: f7ff ffb0 bl 8000b28 <SysTick_Config>
8000bc8: 4603 mov r3, r0
}
8000bca: 4618 mov r0, r3
8000bcc: 3708 adds r7, #8
8000bce: 46bd mov sp, r7
8000bd0: bd80 pop {r7, pc}
...
08000bd4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000bd4: b480 push {r7}
8000bd6: b089 sub sp, #36 ; 0x24
8000bd8: af00 add r7, sp, #0
8000bda: 6078 str r0, [r7, #4]
8000bdc: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
8000bde: 2300 movs r3, #0
8000be0: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8000be2: 2300 movs r3, #0
8000be4: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8000be6: 2300 movs r3, #0
8000be8: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
8000bea: 2300 movs r3, #0
8000bec: 61fb str r3, [r7, #28]
8000bee: e159 b.n 8000ea4 <HAL_GPIO_Init+0x2d0>
{
/* Get the IO position */
ioposition = 0x01U << position;
8000bf0: 2201 movs r2, #1
8000bf2: 69fb ldr r3, [r7, #28]
8000bf4: fa02 f303 lsl.w r3, r2, r3
8000bf8: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8000bfa: 683b ldr r3, [r7, #0]
8000bfc: 681b ldr r3, [r3, #0]
8000bfe: 697a ldr r2, [r7, #20]
8000c00: 4013 ands r3, r2
8000c02: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8000c04: 693a ldr r2, [r7, #16]
8000c06: 697b ldr r3, [r7, #20]
8000c08: 429a cmp r2, r3
8000c0a: f040 8148 bne.w 8000e9e <HAL_GPIO_Init+0x2ca>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8000c0e: 683b ldr r3, [r7, #0]
8000c10: 685b ldr r3, [r3, #4]
8000c12: f003 0303 and.w r3, r3, #3
8000c16: 2b01 cmp r3, #1
8000c18: d005 beq.n 8000c26 <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000c1a: 683b ldr r3, [r7, #0]
8000c1c: 685b ldr r3, [r3, #4]
8000c1e: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8000c22: 2b02 cmp r3, #2
8000c24: d130 bne.n 8000c88 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000c26: 687b ldr r3, [r7, #4]
8000c28: 689b ldr r3, [r3, #8]
8000c2a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8000c2c: 69fb ldr r3, [r7, #28]
8000c2e: 005b lsls r3, r3, #1
8000c30: 2203 movs r2, #3
8000c32: fa02 f303 lsl.w r3, r2, r3
8000c36: 43db mvns r3, r3
8000c38: 69ba ldr r2, [r7, #24]
8000c3a: 4013 ands r3, r2
8000c3c: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8000c3e: 683b ldr r3, [r7, #0]
8000c40: 68da ldr r2, [r3, #12]
8000c42: 69fb ldr r3, [r7, #28]
8000c44: 005b lsls r3, r3, #1
8000c46: fa02 f303 lsl.w r3, r2, r3
8000c4a: 69ba ldr r2, [r7, #24]
8000c4c: 4313 orrs r3, r2
8000c4e: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8000c50: 687b ldr r3, [r7, #4]
8000c52: 69ba ldr r2, [r7, #24]
8000c54: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000c56: 687b ldr r3, [r7, #4]
8000c58: 685b ldr r3, [r3, #4]
8000c5a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8000c5c: 2201 movs r2, #1
8000c5e: 69fb ldr r3, [r7, #28]
8000c60: fa02 f303 lsl.w r3, r2, r3
8000c64: 43db mvns r3, r3
8000c66: 69ba ldr r2, [r7, #24]
8000c68: 4013 ands r3, r2
8000c6a: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000c6c: 683b ldr r3, [r7, #0]
8000c6e: 685b ldr r3, [r3, #4]
8000c70: 091b lsrs r3, r3, #4
8000c72: f003 0201 and.w r2, r3, #1
8000c76: 69fb ldr r3, [r7, #28]
8000c78: fa02 f303 lsl.w r3, r2, r3
8000c7c: 69ba ldr r2, [r7, #24]
8000c7e: 4313 orrs r3, r2
8000c80: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8000c82: 687b ldr r3, [r7, #4]
8000c84: 69ba ldr r2, [r7, #24]
8000c86: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000c88: 683b ldr r3, [r7, #0]
8000c8a: 685b ldr r3, [r3, #4]
8000c8c: f003 0303 and.w r3, r3, #3
8000c90: 2b03 cmp r3, #3
8000c92: d017 beq.n 8000cc4 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000c94: 687b ldr r3, [r7, #4]
8000c96: 68db ldr r3, [r3, #12]
8000c98: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8000c9a: 69fb ldr r3, [r7, #28]
8000c9c: 005b lsls r3, r3, #1
8000c9e: 2203 movs r2, #3
8000ca0: fa02 f303 lsl.w r3, r2, r3
8000ca4: 43db mvns r3, r3
8000ca6: 69ba ldr r2, [r7, #24]
8000ca8: 4013 ands r3, r2
8000caa: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8000cac: 683b ldr r3, [r7, #0]
8000cae: 689a ldr r2, [r3, #8]
8000cb0: 69fb ldr r3, [r7, #28]
8000cb2: 005b lsls r3, r3, #1
8000cb4: fa02 f303 lsl.w r3, r2, r3
8000cb8: 69ba ldr r2, [r7, #24]
8000cba: 4313 orrs r3, r2
8000cbc: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8000cbe: 687b ldr r3, [r7, #4]
8000cc0: 69ba ldr r2, [r7, #24]
8000cc2: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000cc4: 683b ldr r3, [r7, #0]
8000cc6: 685b ldr r3, [r3, #4]
8000cc8: f003 0303 and.w r3, r3, #3
8000ccc: 2b02 cmp r3, #2
8000cce: d123 bne.n 8000d18 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8000cd0: 69fb ldr r3, [r7, #28]
8000cd2: 08da lsrs r2, r3, #3
8000cd4: 687b ldr r3, [r7, #4]
8000cd6: 3208 adds r2, #8
8000cd8: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8000cdc: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
8000cde: 69fb ldr r3, [r7, #28]
8000ce0: f003 0307 and.w r3, r3, #7
8000ce4: 009b lsls r3, r3, #2
8000ce6: 220f movs r2, #15
8000ce8: fa02 f303 lsl.w r3, r2, r3
8000cec: 43db mvns r3, r3
8000cee: 69ba ldr r2, [r7, #24]
8000cf0: 4013 ands r3, r2
8000cf2: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8000cf4: 683b ldr r3, [r7, #0]
8000cf6: 691a ldr r2, [r3, #16]
8000cf8: 69fb ldr r3, [r7, #28]
8000cfa: f003 0307 and.w r3, r3, #7
8000cfe: 009b lsls r3, r3, #2
8000d00: fa02 f303 lsl.w r3, r2, r3
8000d04: 69ba ldr r2, [r7, #24]
8000d06: 4313 orrs r3, r2
8000d08: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8000d0a: 69fb ldr r3, [r7, #28]
8000d0c: 08da lsrs r2, r3, #3
8000d0e: 687b ldr r3, [r7, #4]
8000d10: 3208 adds r2, #8
8000d12: 69b9 ldr r1, [r7, #24]
8000d14: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000d18: 687b ldr r3, [r7, #4]
8000d1a: 681b ldr r3, [r3, #0]
8000d1c: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
8000d1e: 69fb ldr r3, [r7, #28]
8000d20: 005b lsls r3, r3, #1
8000d22: 2203 movs r2, #3
8000d24: fa02 f303 lsl.w r3, r2, r3
8000d28: 43db mvns r3, r3
8000d2a: 69ba ldr r2, [r7, #24]
8000d2c: 4013 ands r3, r2
8000d2e: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8000d30: 683b ldr r3, [r7, #0]
8000d32: 685b ldr r3, [r3, #4]
8000d34: f003 0203 and.w r2, r3, #3
8000d38: 69fb ldr r3, [r7, #28]
8000d3a: 005b lsls r3, r3, #1
8000d3c: fa02 f303 lsl.w r3, r2, r3
8000d40: 69ba ldr r2, [r7, #24]
8000d42: 4313 orrs r3, r2
8000d44: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8000d46: 687b ldr r3, [r7, #4]
8000d48: 69ba ldr r2, [r7, #24]
8000d4a: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8000d4c: 683b ldr r3, [r7, #0]
8000d4e: 685b ldr r3, [r3, #4]
8000d50: f403 3340 and.w r3, r3, #196608 ; 0x30000
8000d54: 2b00 cmp r3, #0
8000d56: f000 80a2 beq.w 8000e9e <HAL_GPIO_Init+0x2ca>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000d5a: 2300 movs r3, #0
8000d5c: 60fb str r3, [r7, #12]
8000d5e: 4b57 ldr r3, [pc, #348] ; (8000ebc <HAL_GPIO_Init+0x2e8>)
8000d60: 6c5b ldr r3, [r3, #68] ; 0x44
8000d62: 4a56 ldr r2, [pc, #344] ; (8000ebc <HAL_GPIO_Init+0x2e8>)
8000d64: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000d68: 6453 str r3, [r2, #68] ; 0x44
8000d6a: 4b54 ldr r3, [pc, #336] ; (8000ebc <HAL_GPIO_Init+0x2e8>)
8000d6c: 6c5b ldr r3, [r3, #68] ; 0x44
8000d6e: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000d72: 60fb str r3, [r7, #12]
8000d74: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8000d76: 4a52 ldr r2, [pc, #328] ; (8000ec0 <HAL_GPIO_Init+0x2ec>)
8000d78: 69fb ldr r3, [r7, #28]
8000d7a: 089b lsrs r3, r3, #2
8000d7c: 3302 adds r3, #2
8000d7e: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000d82: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8000d84: 69fb ldr r3, [r7, #28]
8000d86: f003 0303 and.w r3, r3, #3
8000d8a: 009b lsls r3, r3, #2
8000d8c: 220f movs r2, #15
8000d8e: fa02 f303 lsl.w r3, r2, r3
8000d92: 43db mvns r3, r3
8000d94: 69ba ldr r2, [r7, #24]
8000d96: 4013 ands r3, r2
8000d98: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8000d9a: 687b ldr r3, [r7, #4]
8000d9c: 4a49 ldr r2, [pc, #292] ; (8000ec4 <HAL_GPIO_Init+0x2f0>)
8000d9e: 4293 cmp r3, r2
8000da0: d019 beq.n 8000dd6 <HAL_GPIO_Init+0x202>
8000da2: 687b ldr r3, [r7, #4]
8000da4: 4a48 ldr r2, [pc, #288] ; (8000ec8 <HAL_GPIO_Init+0x2f4>)
8000da6: 4293 cmp r3, r2
8000da8: d013 beq.n 8000dd2 <HAL_GPIO_Init+0x1fe>
8000daa: 687b ldr r3, [r7, #4]
8000dac: 4a47 ldr r2, [pc, #284] ; (8000ecc <HAL_GPIO_Init+0x2f8>)
8000dae: 4293 cmp r3, r2
8000db0: d00d beq.n 8000dce <HAL_GPIO_Init+0x1fa>
8000db2: 687b ldr r3, [r7, #4]
8000db4: 4a46 ldr r2, [pc, #280] ; (8000ed0 <HAL_GPIO_Init+0x2fc>)
8000db6: 4293 cmp r3, r2
8000db8: d007 beq.n 8000dca <HAL_GPIO_Init+0x1f6>
8000dba: 687b ldr r3, [r7, #4]
8000dbc: 4a45 ldr r2, [pc, #276] ; (8000ed4 <HAL_GPIO_Init+0x300>)
8000dbe: 4293 cmp r3, r2
8000dc0: d101 bne.n 8000dc6 <HAL_GPIO_Init+0x1f2>
8000dc2: 2304 movs r3, #4
8000dc4: e008 b.n 8000dd8 <HAL_GPIO_Init+0x204>
8000dc6: 2307 movs r3, #7
8000dc8: e006 b.n 8000dd8 <HAL_GPIO_Init+0x204>
8000dca: 2303 movs r3, #3
8000dcc: e004 b.n 8000dd8 <HAL_GPIO_Init+0x204>
8000dce: 2302 movs r3, #2
8000dd0: e002 b.n 8000dd8 <HAL_GPIO_Init+0x204>
8000dd2: 2301 movs r3, #1
8000dd4: e000 b.n 8000dd8 <HAL_GPIO_Init+0x204>
8000dd6: 2300 movs r3, #0
8000dd8: 69fa ldr r2, [r7, #28]
8000dda: f002 0203 and.w r2, r2, #3
8000dde: 0092 lsls r2, r2, #2
8000de0: 4093 lsls r3, r2
8000de2: 69ba ldr r2, [r7, #24]
8000de4: 4313 orrs r3, r2
8000de6: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8000de8: 4935 ldr r1, [pc, #212] ; (8000ec0 <HAL_GPIO_Init+0x2ec>)
8000dea: 69fb ldr r3, [r7, #28]
8000dec: 089b lsrs r3, r3, #2
8000dee: 3302 adds r3, #2
8000df0: 69ba ldr r2, [r7, #24]
8000df2: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8000df6: 4b38 ldr r3, [pc, #224] ; (8000ed8 <HAL_GPIO_Init+0x304>)
8000df8: 689b ldr r3, [r3, #8]
8000dfa: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8000dfc: 693b ldr r3, [r7, #16]
8000dfe: 43db mvns r3, r3
8000e00: 69ba ldr r2, [r7, #24]
8000e02: 4013 ands r3, r2
8000e04: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8000e06: 683b ldr r3, [r7, #0]
8000e08: 685b ldr r3, [r3, #4]
8000e0a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8000e0e: 2b00 cmp r3, #0
8000e10: d003 beq.n 8000e1a <HAL_GPIO_Init+0x246>
{
temp |= iocurrent;
8000e12: 69ba ldr r2, [r7, #24]
8000e14: 693b ldr r3, [r7, #16]
8000e16: 4313 orrs r3, r2
8000e18: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8000e1a: 4a2f ldr r2, [pc, #188] ; (8000ed8 <HAL_GPIO_Init+0x304>)
8000e1c: 69bb ldr r3, [r7, #24]
8000e1e: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8000e20: 4b2d ldr r3, [pc, #180] ; (8000ed8 <HAL_GPIO_Init+0x304>)
8000e22: 68db ldr r3, [r3, #12]
8000e24: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8000e26: 693b ldr r3, [r7, #16]
8000e28: 43db mvns r3, r3
8000e2a: 69ba ldr r2, [r7, #24]
8000e2c: 4013 ands r3, r2
8000e2e: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8000e30: 683b ldr r3, [r7, #0]
8000e32: 685b ldr r3, [r3, #4]
8000e34: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8000e38: 2b00 cmp r3, #0
8000e3a: d003 beq.n 8000e44 <HAL_GPIO_Init+0x270>
{
temp |= iocurrent;
8000e3c: 69ba ldr r2, [r7, #24]
8000e3e: 693b ldr r3, [r7, #16]
8000e40: 4313 orrs r3, r2
8000e42: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8000e44: 4a24 ldr r2, [pc, #144] ; (8000ed8 <HAL_GPIO_Init+0x304>)
8000e46: 69bb ldr r3, [r7, #24]
8000e48: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8000e4a: 4b23 ldr r3, [pc, #140] ; (8000ed8 <HAL_GPIO_Init+0x304>)
8000e4c: 685b ldr r3, [r3, #4]
8000e4e: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8000e50: 693b ldr r3, [r7, #16]
8000e52: 43db mvns r3, r3
8000e54: 69ba ldr r2, [r7, #24]
8000e56: 4013 ands r3, r2
8000e58: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8000e5a: 683b ldr r3, [r7, #0]
8000e5c: 685b ldr r3, [r3, #4]
8000e5e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000e62: 2b00 cmp r3, #0
8000e64: d003 beq.n 8000e6e <HAL_GPIO_Init+0x29a>
{
temp |= iocurrent;
8000e66: 69ba ldr r2, [r7, #24]
8000e68: 693b ldr r3, [r7, #16]
8000e6a: 4313 orrs r3, r2
8000e6c: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8000e6e: 4a1a ldr r2, [pc, #104] ; (8000ed8 <HAL_GPIO_Init+0x304>)
8000e70: 69bb ldr r3, [r7, #24]
8000e72: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8000e74: 4b18 ldr r3, [pc, #96] ; (8000ed8 <HAL_GPIO_Init+0x304>)
8000e76: 681b ldr r3, [r3, #0]
8000e78: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8000e7a: 693b ldr r3, [r7, #16]
8000e7c: 43db mvns r3, r3
8000e7e: 69ba ldr r2, [r7, #24]
8000e80: 4013 ands r3, r2
8000e82: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8000e84: 683b ldr r3, [r7, #0]
8000e86: 685b ldr r3, [r3, #4]
8000e88: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000e8c: 2b00 cmp r3, #0
8000e8e: d003 beq.n 8000e98 <HAL_GPIO_Init+0x2c4>
{
temp |= iocurrent;
8000e90: 69ba ldr r2, [r7, #24]
8000e92: 693b ldr r3, [r7, #16]
8000e94: 4313 orrs r3, r2
8000e96: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8000e98: 4a0f ldr r2, [pc, #60] ; (8000ed8 <HAL_GPIO_Init+0x304>)
8000e9a: 69bb ldr r3, [r7, #24]
8000e9c: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
8000e9e: 69fb ldr r3, [r7, #28]
8000ea0: 3301 adds r3, #1
8000ea2: 61fb str r3, [r7, #28]
8000ea4: 69fb ldr r3, [r7, #28]
8000ea6: 2b0f cmp r3, #15
8000ea8: f67f aea2 bls.w 8000bf0 <HAL_GPIO_Init+0x1c>
}
}
}
}
8000eac: bf00 nop
8000eae: bf00 nop
8000eb0: 3724 adds r7, #36 ; 0x24
8000eb2: 46bd mov sp, r7
8000eb4: f85d 7b04 ldr.w r7, [sp], #4
8000eb8: 4770 bx lr
8000eba: bf00 nop
8000ebc: 40023800 .word 0x40023800
8000ec0: 40013800 .word 0x40013800
8000ec4: 40020000 .word 0x40020000
8000ec8: 40020400 .word 0x40020400
8000ecc: 40020800 .word 0x40020800
8000ed0: 40020c00 .word 0x40020c00
8000ed4: 40021000 .word 0x40021000
8000ed8: 40013c00 .word 0x40013c00
08000edc <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8000edc: b480 push {r7}
8000ede: b083 sub sp, #12
8000ee0: af00 add r7, sp, #0
8000ee2: 6078 str r0, [r7, #4]
8000ee4: 460b mov r3, r1
8000ee6: 807b strh r3, [r7, #2]
8000ee8: 4613 mov r3, r2
8000eea: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8000eec: 787b ldrb r3, [r7, #1]
8000eee: 2b00 cmp r3, #0
8000ef0: d003 beq.n 8000efa <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8000ef2: 887a ldrh r2, [r7, #2]
8000ef4: 687b ldr r3, [r7, #4]
8000ef6: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8000ef8: e003 b.n 8000f02 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
8000efa: 887b ldrh r3, [r7, #2]
8000efc: 041a lsls r2, r3, #16
8000efe: 687b ldr r3, [r7, #4]
8000f00: 619a str r2, [r3, #24]
}
8000f02: bf00 nop
8000f04: 370c adds r7, #12
8000f06: 46bd mov sp, r7
8000f08: f85d 7b04 ldr.w r7, [sp], #4
8000f0c: 4770 bx lr
...
08000f10 <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000f10: b580 push {r7, lr}
8000f12: b086 sub sp, #24
8000f14: af00 add r7, sp, #0
8000f16: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8000f18: 687b ldr r3, [r7, #4]
8000f1a: 2b00 cmp r3, #0
8000f1c: d101 bne.n 8000f22 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000f1e: 2301 movs r3, #1
8000f20: e267 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000f22: 687b ldr r3, [r7, #4]
8000f24: 681b ldr r3, [r3, #0]
8000f26: f003 0301 and.w r3, r3, #1
8000f2a: 2b00 cmp r3, #0
8000f2c: d075 beq.n 800101a <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8000f2e: 4b88 ldr r3, [pc, #544] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000f30: 689b ldr r3, [r3, #8]
8000f32: f003 030c and.w r3, r3, #12
8000f36: 2b04 cmp r3, #4
8000f38: d00c beq.n 8000f54 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8000f3a: 4b85 ldr r3, [pc, #532] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000f3c: 689b ldr r3, [r3, #8]
8000f3e: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8000f42: 2b08 cmp r3, #8
8000f44: d112 bne.n 8000f6c <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8000f46: 4b82 ldr r3, [pc, #520] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000f48: 685b ldr r3, [r3, #4]
8000f4a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8000f4e: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8000f52: d10b bne.n 8000f6c <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000f54: 4b7e ldr r3, [pc, #504] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000f56: 681b ldr r3, [r3, #0]
8000f58: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000f5c: 2b00 cmp r3, #0
8000f5e: d05b beq.n 8001018 <HAL_RCC_OscConfig+0x108>
8000f60: 687b ldr r3, [r7, #4]
8000f62: 685b ldr r3, [r3, #4]
8000f64: 2b00 cmp r3, #0
8000f66: d157 bne.n 8001018 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8000f68: 2301 movs r3, #1
8000f6a: e242 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000f6c: 687b ldr r3, [r7, #4]
8000f6e: 685b ldr r3, [r3, #4]
8000f70: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000f74: d106 bne.n 8000f84 <HAL_RCC_OscConfig+0x74>
8000f76: 4b76 ldr r3, [pc, #472] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000f78: 681b ldr r3, [r3, #0]
8000f7a: 4a75 ldr r2, [pc, #468] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000f7c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000f80: 6013 str r3, [r2, #0]
8000f82: e01d b.n 8000fc0 <HAL_RCC_OscConfig+0xb0>
8000f84: 687b ldr r3, [r7, #4]
8000f86: 685b ldr r3, [r3, #4]
8000f88: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8000f8c: d10c bne.n 8000fa8 <HAL_RCC_OscConfig+0x98>
8000f8e: 4b70 ldr r3, [pc, #448] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000f90: 681b ldr r3, [r3, #0]
8000f92: 4a6f ldr r2, [pc, #444] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000f94: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8000f98: 6013 str r3, [r2, #0]
8000f9a: 4b6d ldr r3, [pc, #436] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000f9c: 681b ldr r3, [r3, #0]
8000f9e: 4a6c ldr r2, [pc, #432] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000fa0: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000fa4: 6013 str r3, [r2, #0]
8000fa6: e00b b.n 8000fc0 <HAL_RCC_OscConfig+0xb0>
8000fa8: 4b69 ldr r3, [pc, #420] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000faa: 681b ldr r3, [r3, #0]
8000fac: 4a68 ldr r2, [pc, #416] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000fae: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8000fb2: 6013 str r3, [r2, #0]
8000fb4: 4b66 ldr r3, [pc, #408] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000fb6: 681b ldr r3, [r3, #0]
8000fb8: 4a65 ldr r2, [pc, #404] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000fba: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8000fbe: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
8000fc0: 687b ldr r3, [r7, #4]
8000fc2: 685b ldr r3, [r3, #4]
8000fc4: 2b00 cmp r3, #0
8000fc6: d013 beq.n 8000ff0 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000fc8: f7ff fd12 bl 80009f0 <HAL_GetTick>
8000fcc: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000fce: e008 b.n 8000fe2 <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000fd0: f7ff fd0e bl 80009f0 <HAL_GetTick>
8000fd4: 4602 mov r2, r0
8000fd6: 693b ldr r3, [r7, #16]
8000fd8: 1ad3 subs r3, r2, r3
8000fda: 2b64 cmp r3, #100 ; 0x64
8000fdc: d901 bls.n 8000fe2 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
8000fde: 2303 movs r3, #3
8000fe0: e207 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8000fe2: 4b5b ldr r3, [pc, #364] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8000fe4: 681b ldr r3, [r3, #0]
8000fe6: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000fea: 2b00 cmp r3, #0
8000fec: d0f0 beq.n 8000fd0 <HAL_RCC_OscConfig+0xc0>
8000fee: e014 b.n 800101a <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8000ff0: f7ff fcfe bl 80009f0 <HAL_GetTick>
8000ff4: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8000ff6: e008 b.n 800100a <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8000ff8: f7ff fcfa bl 80009f0 <HAL_GetTick>
8000ffc: 4602 mov r2, r0
8000ffe: 693b ldr r3, [r7, #16]
8001000: 1ad3 subs r3, r2, r3
8001002: 2b64 cmp r3, #100 ; 0x64
8001004: d901 bls.n 800100a <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8001006: 2303 movs r3, #3
8001008: e1f3 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800100a: 4b51 ldr r3, [pc, #324] ; (8001150 <HAL_RCC_OscConfig+0x240>)
800100c: 681b ldr r3, [r3, #0]
800100e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001012: 2b00 cmp r3, #0
8001014: d1f0 bne.n 8000ff8 <HAL_RCC_OscConfig+0xe8>
8001016: e000 b.n 800101a <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001018: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800101a: 687b ldr r3, [r7, #4]
800101c: 681b ldr r3, [r3, #0]
800101e: f003 0302 and.w r3, r3, #2
8001022: 2b00 cmp r3, #0
8001024: d063 beq.n 80010ee <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8001026: 4b4a ldr r3, [pc, #296] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8001028: 689b ldr r3, [r3, #8]
800102a: f003 030c and.w r3, r3, #12
800102e: 2b00 cmp r3, #0
8001030: d00b beq.n 800104a <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8001032: 4b47 ldr r3, [pc, #284] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8001034: 689b ldr r3, [r3, #8]
8001036: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
800103a: 2b08 cmp r3, #8
800103c: d11c bne.n 8001078 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
800103e: 4b44 ldr r3, [pc, #272] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8001040: 685b ldr r3, [r3, #4]
8001042: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8001046: 2b00 cmp r3, #0
8001048: d116 bne.n 8001078 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
800104a: 4b41 ldr r3, [pc, #260] ; (8001150 <HAL_RCC_OscConfig+0x240>)
800104c: 681b ldr r3, [r3, #0]
800104e: f003 0302 and.w r3, r3, #2
8001052: 2b00 cmp r3, #0
8001054: d005 beq.n 8001062 <HAL_RCC_OscConfig+0x152>
8001056: 687b ldr r3, [r7, #4]
8001058: 68db ldr r3, [r3, #12]
800105a: 2b01 cmp r3, #1
800105c: d001 beq.n 8001062 <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
800105e: 2301 movs r3, #1
8001060: e1c7 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001062: 4b3b ldr r3, [pc, #236] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8001064: 681b ldr r3, [r3, #0]
8001066: f023 02f8 bic.w r2, r3, #248 ; 0xf8
800106a: 687b ldr r3, [r7, #4]
800106c: 691b ldr r3, [r3, #16]
800106e: 00db lsls r3, r3, #3
8001070: 4937 ldr r1, [pc, #220] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8001072: 4313 orrs r3, r2
8001074: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001076: e03a b.n 80010ee <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
8001078: 687b ldr r3, [r7, #4]
800107a: 68db ldr r3, [r3, #12]
800107c: 2b00 cmp r3, #0
800107e: d020 beq.n 80010c2 <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001080: 4b34 ldr r3, [pc, #208] ; (8001154 <HAL_RCC_OscConfig+0x244>)
8001082: 2201 movs r2, #1
8001084: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001086: f7ff fcb3 bl 80009f0 <HAL_GetTick>
800108a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800108c: e008 b.n 80010a0 <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800108e: f7ff fcaf bl 80009f0 <HAL_GetTick>
8001092: 4602 mov r2, r0
8001094: 693b ldr r3, [r7, #16]
8001096: 1ad3 subs r3, r2, r3
8001098: 2b02 cmp r3, #2
800109a: d901 bls.n 80010a0 <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
800109c: 2303 movs r3, #3
800109e: e1a8 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80010a0: 4b2b ldr r3, [pc, #172] ; (8001150 <HAL_RCC_OscConfig+0x240>)
80010a2: 681b ldr r3, [r3, #0]
80010a4: f003 0302 and.w r3, r3, #2
80010a8: 2b00 cmp r3, #0
80010aa: d0f0 beq.n 800108e <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80010ac: 4b28 ldr r3, [pc, #160] ; (8001150 <HAL_RCC_OscConfig+0x240>)
80010ae: 681b ldr r3, [r3, #0]
80010b0: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80010b4: 687b ldr r3, [r7, #4]
80010b6: 691b ldr r3, [r3, #16]
80010b8: 00db lsls r3, r3, #3
80010ba: 4925 ldr r1, [pc, #148] ; (8001150 <HAL_RCC_OscConfig+0x240>)
80010bc: 4313 orrs r3, r2
80010be: 600b str r3, [r1, #0]
80010c0: e015 b.n 80010ee <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80010c2: 4b24 ldr r3, [pc, #144] ; (8001154 <HAL_RCC_OscConfig+0x244>)
80010c4: 2200 movs r2, #0
80010c6: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80010c8: f7ff fc92 bl 80009f0 <HAL_GetTick>
80010cc: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80010ce: e008 b.n 80010e2 <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
80010d0: f7ff fc8e bl 80009f0 <HAL_GetTick>
80010d4: 4602 mov r2, r0
80010d6: 693b ldr r3, [r7, #16]
80010d8: 1ad3 subs r3, r2, r3
80010da: 2b02 cmp r3, #2
80010dc: d901 bls.n 80010e2 <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
80010de: 2303 movs r3, #3
80010e0: e187 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
80010e2: 4b1b ldr r3, [pc, #108] ; (8001150 <HAL_RCC_OscConfig+0x240>)
80010e4: 681b ldr r3, [r3, #0]
80010e6: f003 0302 and.w r3, r3, #2
80010ea: 2b00 cmp r3, #0
80010ec: d1f0 bne.n 80010d0 <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80010ee: 687b ldr r3, [r7, #4]
80010f0: 681b ldr r3, [r3, #0]
80010f2: f003 0308 and.w r3, r3, #8
80010f6: 2b00 cmp r3, #0
80010f8: d036 beq.n 8001168 <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
80010fa: 687b ldr r3, [r7, #4]
80010fc: 695b ldr r3, [r3, #20]
80010fe: 2b00 cmp r3, #0
8001100: d016 beq.n 8001130 <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001102: 4b15 ldr r3, [pc, #84] ; (8001158 <HAL_RCC_OscConfig+0x248>)
8001104: 2201 movs r2, #1
8001106: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001108: f7ff fc72 bl 80009f0 <HAL_GetTick>
800110c: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800110e: e008 b.n 8001122 <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001110: f7ff fc6e bl 80009f0 <HAL_GetTick>
8001114: 4602 mov r2, r0
8001116: 693b ldr r3, [r7, #16]
8001118: 1ad3 subs r3, r2, r3
800111a: 2b02 cmp r3, #2
800111c: d901 bls.n 8001122 <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
800111e: 2303 movs r3, #3
8001120: e167 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001122: 4b0b ldr r3, [pc, #44] ; (8001150 <HAL_RCC_OscConfig+0x240>)
8001124: 6f5b ldr r3, [r3, #116] ; 0x74
8001126: f003 0302 and.w r3, r3, #2
800112a: 2b00 cmp r3, #0
800112c: d0f0 beq.n 8001110 <HAL_RCC_OscConfig+0x200>
800112e: e01b b.n 8001168 <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8001130: 4b09 ldr r3, [pc, #36] ; (8001158 <HAL_RCC_OscConfig+0x248>)
8001132: 2200 movs r2, #0
8001134: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001136: f7ff fc5b bl 80009f0 <HAL_GetTick>
800113a: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800113c: e00e b.n 800115c <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
800113e: f7ff fc57 bl 80009f0 <HAL_GetTick>
8001142: 4602 mov r2, r0
8001144: 693b ldr r3, [r7, #16]
8001146: 1ad3 subs r3, r2, r3
8001148: 2b02 cmp r3, #2
800114a: d907 bls.n 800115c <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
800114c: 2303 movs r3, #3
800114e: e150 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
8001150: 40023800 .word 0x40023800
8001154: 42470000 .word 0x42470000
8001158: 42470e80 .word 0x42470e80
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
800115c: 4b88 ldr r3, [pc, #544] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800115e: 6f5b ldr r3, [r3, #116] ; 0x74
8001160: f003 0302 and.w r3, r3, #2
8001164: 2b00 cmp r3, #0
8001166: d1ea bne.n 800113e <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001168: 687b ldr r3, [r7, #4]
800116a: 681b ldr r3, [r3, #0]
800116c: f003 0304 and.w r3, r3, #4
8001170: 2b00 cmp r3, #0
8001172: f000 8097 beq.w 80012a4 <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
8001176: 2300 movs r3, #0
8001178: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800117a: 4b81 ldr r3, [pc, #516] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800117c: 6c1b ldr r3, [r3, #64] ; 0x40
800117e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001182: 2b00 cmp r3, #0
8001184: d10f bne.n 80011a6 <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001186: 2300 movs r3, #0
8001188: 60bb str r3, [r7, #8]
800118a: 4b7d ldr r3, [pc, #500] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800118c: 6c1b ldr r3, [r3, #64] ; 0x40
800118e: 4a7c ldr r2, [pc, #496] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001190: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001194: 6413 str r3, [r2, #64] ; 0x40
8001196: 4b7a ldr r3, [pc, #488] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001198: 6c1b ldr r3, [r3, #64] ; 0x40
800119a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800119e: 60bb str r3, [r7, #8]
80011a0: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
80011a2: 2301 movs r3, #1
80011a4: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80011a6: 4b77 ldr r3, [pc, #476] ; (8001384 <HAL_RCC_OscConfig+0x474>)
80011a8: 681b ldr r3, [r3, #0]
80011aa: f403 7380 and.w r3, r3, #256 ; 0x100
80011ae: 2b00 cmp r3, #0
80011b0: d118 bne.n 80011e4 <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
80011b2: 4b74 ldr r3, [pc, #464] ; (8001384 <HAL_RCC_OscConfig+0x474>)
80011b4: 681b ldr r3, [r3, #0]
80011b6: 4a73 ldr r2, [pc, #460] ; (8001384 <HAL_RCC_OscConfig+0x474>)
80011b8: f443 7380 orr.w r3, r3, #256 ; 0x100
80011bc: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80011be: f7ff fc17 bl 80009f0 <HAL_GetTick>
80011c2: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80011c4: e008 b.n 80011d8 <HAL_RCC_OscConfig+0x2c8>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80011c6: f7ff fc13 bl 80009f0 <HAL_GetTick>
80011ca: 4602 mov r2, r0
80011cc: 693b ldr r3, [r7, #16]
80011ce: 1ad3 subs r3, r2, r3
80011d0: 2b02 cmp r3, #2
80011d2: d901 bls.n 80011d8 <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
80011d4: 2303 movs r3, #3
80011d6: e10c b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
80011d8: 4b6a ldr r3, [pc, #424] ; (8001384 <HAL_RCC_OscConfig+0x474>)
80011da: 681b ldr r3, [r3, #0]
80011dc: f403 7380 and.w r3, r3, #256 ; 0x100
80011e0: 2b00 cmp r3, #0
80011e2: d0f0 beq.n 80011c6 <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80011e4: 687b ldr r3, [r7, #4]
80011e6: 689b ldr r3, [r3, #8]
80011e8: 2b01 cmp r3, #1
80011ea: d106 bne.n 80011fa <HAL_RCC_OscConfig+0x2ea>
80011ec: 4b64 ldr r3, [pc, #400] ; (8001380 <HAL_RCC_OscConfig+0x470>)
80011ee: 6f1b ldr r3, [r3, #112] ; 0x70
80011f0: 4a63 ldr r2, [pc, #396] ; (8001380 <HAL_RCC_OscConfig+0x470>)
80011f2: f043 0301 orr.w r3, r3, #1
80011f6: 6713 str r3, [r2, #112] ; 0x70
80011f8: e01c b.n 8001234 <HAL_RCC_OscConfig+0x324>
80011fa: 687b ldr r3, [r7, #4]
80011fc: 689b ldr r3, [r3, #8]
80011fe: 2b05 cmp r3, #5
8001200: d10c bne.n 800121c <HAL_RCC_OscConfig+0x30c>
8001202: 4b5f ldr r3, [pc, #380] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001204: 6f1b ldr r3, [r3, #112] ; 0x70
8001206: 4a5e ldr r2, [pc, #376] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001208: f043 0304 orr.w r3, r3, #4
800120c: 6713 str r3, [r2, #112] ; 0x70
800120e: 4b5c ldr r3, [pc, #368] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001210: 6f1b ldr r3, [r3, #112] ; 0x70
8001212: 4a5b ldr r2, [pc, #364] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001214: f043 0301 orr.w r3, r3, #1
8001218: 6713 str r3, [r2, #112] ; 0x70
800121a: e00b b.n 8001234 <HAL_RCC_OscConfig+0x324>
800121c: 4b58 ldr r3, [pc, #352] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800121e: 6f1b ldr r3, [r3, #112] ; 0x70
8001220: 4a57 ldr r2, [pc, #348] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001222: f023 0301 bic.w r3, r3, #1
8001226: 6713 str r3, [r2, #112] ; 0x70
8001228: 4b55 ldr r3, [pc, #340] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800122a: 6f1b ldr r3, [r3, #112] ; 0x70
800122c: 4a54 ldr r2, [pc, #336] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800122e: f023 0304 bic.w r3, r3, #4
8001232: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8001234: 687b ldr r3, [r7, #4]
8001236: 689b ldr r3, [r3, #8]
8001238: 2b00 cmp r3, #0
800123a: d015 beq.n 8001268 <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800123c: f7ff fbd8 bl 80009f0 <HAL_GetTick>
8001240: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001242: e00a b.n 800125a <HAL_RCC_OscConfig+0x34a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001244: f7ff fbd4 bl 80009f0 <HAL_GetTick>
8001248: 4602 mov r2, r0
800124a: 693b ldr r3, [r7, #16]
800124c: 1ad3 subs r3, r2, r3
800124e: f241 3288 movw r2, #5000 ; 0x1388
8001252: 4293 cmp r3, r2
8001254: d901 bls.n 800125a <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
8001256: 2303 movs r3, #3
8001258: e0cb b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
800125a: 4b49 ldr r3, [pc, #292] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800125c: 6f1b ldr r3, [r3, #112] ; 0x70
800125e: f003 0302 and.w r3, r3, #2
8001262: 2b00 cmp r3, #0
8001264: d0ee beq.n 8001244 <HAL_RCC_OscConfig+0x334>
8001266: e014 b.n 8001292 <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001268: f7ff fbc2 bl 80009f0 <HAL_GetTick>
800126c: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800126e: e00a b.n 8001286 <HAL_RCC_OscConfig+0x376>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001270: f7ff fbbe bl 80009f0 <HAL_GetTick>
8001274: 4602 mov r2, r0
8001276: 693b ldr r3, [r7, #16]
8001278: 1ad3 subs r3, r2, r3
800127a: f241 3288 movw r2, #5000 ; 0x1388
800127e: 4293 cmp r3, r2
8001280: d901 bls.n 8001286 <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
8001282: 2303 movs r3, #3
8001284: e0b5 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001286: 4b3e ldr r3, [pc, #248] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001288: 6f1b ldr r3, [r3, #112] ; 0x70
800128a: f003 0302 and.w r3, r3, #2
800128e: 2b00 cmp r3, #0
8001290: d1ee bne.n 8001270 <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8001292: 7dfb ldrb r3, [r7, #23]
8001294: 2b01 cmp r3, #1
8001296: d105 bne.n 80012a4 <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001298: 4b39 ldr r3, [pc, #228] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800129a: 6c1b ldr r3, [r3, #64] ; 0x40
800129c: 4a38 ldr r2, [pc, #224] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800129e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
80012a2: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
80012a4: 687b ldr r3, [r7, #4]
80012a6: 699b ldr r3, [r3, #24]
80012a8: 2b00 cmp r3, #0
80012aa: f000 80a1 beq.w 80013f0 <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
80012ae: 4b34 ldr r3, [pc, #208] ; (8001380 <HAL_RCC_OscConfig+0x470>)
80012b0: 689b ldr r3, [r3, #8]
80012b2: f003 030c and.w r3, r3, #12
80012b6: 2b08 cmp r3, #8
80012b8: d05c beq.n 8001374 <HAL_RCC_OscConfig+0x464>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
80012ba: 687b ldr r3, [r7, #4]
80012bc: 699b ldr r3, [r3, #24]
80012be: 2b02 cmp r3, #2
80012c0: d141 bne.n 8001346 <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80012c2: 4b31 ldr r3, [pc, #196] ; (8001388 <HAL_RCC_OscConfig+0x478>)
80012c4: 2200 movs r2, #0
80012c6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80012c8: f7ff fb92 bl 80009f0 <HAL_GetTick>
80012cc: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80012ce: e008 b.n 80012e2 <HAL_RCC_OscConfig+0x3d2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80012d0: f7ff fb8e bl 80009f0 <HAL_GetTick>
80012d4: 4602 mov r2, r0
80012d6: 693b ldr r3, [r7, #16]
80012d8: 1ad3 subs r3, r2, r3
80012da: 2b02 cmp r3, #2
80012dc: d901 bls.n 80012e2 <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
80012de: 2303 movs r3, #3
80012e0: e087 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80012e2: 4b27 ldr r3, [pc, #156] ; (8001380 <HAL_RCC_OscConfig+0x470>)
80012e4: 681b ldr r3, [r3, #0]
80012e6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80012ea: 2b00 cmp r3, #0
80012ec: d1f0 bne.n 80012d0 <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
80012ee: 687b ldr r3, [r7, #4]
80012f0: 69da ldr r2, [r3, #28]
80012f2: 687b ldr r3, [r7, #4]
80012f4: 6a1b ldr r3, [r3, #32]
80012f6: 431a orrs r2, r3
80012f8: 687b ldr r3, [r7, #4]
80012fa: 6a5b ldr r3, [r3, #36] ; 0x24
80012fc: 019b lsls r3, r3, #6
80012fe: 431a orrs r2, r3
8001300: 687b ldr r3, [r7, #4]
8001302: 6a9b ldr r3, [r3, #40] ; 0x28
8001304: 085b lsrs r3, r3, #1
8001306: 3b01 subs r3, #1
8001308: 041b lsls r3, r3, #16
800130a: 431a orrs r2, r3
800130c: 687b ldr r3, [r7, #4]
800130e: 6adb ldr r3, [r3, #44] ; 0x2c
8001310: 061b lsls r3, r3, #24
8001312: 491b ldr r1, [pc, #108] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001314: 4313 orrs r3, r2
8001316: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
8001318: 4b1b ldr r3, [pc, #108] ; (8001388 <HAL_RCC_OscConfig+0x478>)
800131a: 2201 movs r2, #1
800131c: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800131e: f7ff fb67 bl 80009f0 <HAL_GetTick>
8001322: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001324: e008 b.n 8001338 <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001326: f7ff fb63 bl 80009f0 <HAL_GetTick>
800132a: 4602 mov r2, r0
800132c: 693b ldr r3, [r7, #16]
800132e: 1ad3 subs r3, r2, r3
8001330: 2b02 cmp r3, #2
8001332: d901 bls.n 8001338 <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
8001334: 2303 movs r3, #3
8001336: e05c b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001338: 4b11 ldr r3, [pc, #68] ; (8001380 <HAL_RCC_OscConfig+0x470>)
800133a: 681b ldr r3, [r3, #0]
800133c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001340: 2b00 cmp r3, #0
8001342: d0f0 beq.n 8001326 <HAL_RCC_OscConfig+0x416>
8001344: e054 b.n 80013f0 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001346: 4b10 ldr r3, [pc, #64] ; (8001388 <HAL_RCC_OscConfig+0x478>)
8001348: 2200 movs r2, #0
800134a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800134c: f7ff fb50 bl 80009f0 <HAL_GetTick>
8001350: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001352: e008 b.n 8001366 <HAL_RCC_OscConfig+0x456>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001354: f7ff fb4c bl 80009f0 <HAL_GetTick>
8001358: 4602 mov r2, r0
800135a: 693b ldr r3, [r7, #16]
800135c: 1ad3 subs r3, r2, r3
800135e: 2b02 cmp r3, #2
8001360: d901 bls.n 8001366 <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
8001362: 2303 movs r3, #3
8001364: e045 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001366: 4b06 ldr r3, [pc, #24] ; (8001380 <HAL_RCC_OscConfig+0x470>)
8001368: 681b ldr r3, [r3, #0]
800136a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800136e: 2b00 cmp r3, #0
8001370: d1f0 bne.n 8001354 <HAL_RCC_OscConfig+0x444>
8001372: e03d b.n 80013f0 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001374: 687b ldr r3, [r7, #4]
8001376: 699b ldr r3, [r3, #24]
8001378: 2b01 cmp r3, #1
800137a: d107 bne.n 800138c <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
800137c: 2301 movs r3, #1
800137e: e038 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
8001380: 40023800 .word 0x40023800
8001384: 40007000 .word 0x40007000
8001388: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
800138c: 4b1b ldr r3, [pc, #108] ; (80013fc <HAL_RCC_OscConfig+0x4ec>)
800138e: 685b ldr r3, [r3, #4]
8001390: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001392: 687b ldr r3, [r7, #4]
8001394: 699b ldr r3, [r3, #24]
8001396: 2b01 cmp r3, #1
8001398: d028 beq.n 80013ec <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800139a: 68fb ldr r3, [r7, #12]
800139c: f403 0280 and.w r2, r3, #4194304 ; 0x400000
80013a0: 687b ldr r3, [r7, #4]
80013a2: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
80013a4: 429a cmp r2, r3
80013a6: d121 bne.n 80013ec <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
80013a8: 68fb ldr r3, [r7, #12]
80013aa: f003 023f and.w r2, r3, #63 ; 0x3f
80013ae: 687b ldr r3, [r7, #4]
80013b0: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
80013b2: 429a cmp r2, r3
80013b4: d11a bne.n 80013ec <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
80013b6: 68fa ldr r2, [r7, #12]
80013b8: f647 73c0 movw r3, #32704 ; 0x7fc0
80013bc: 4013 ands r3, r2
80013be: 687a ldr r2, [r7, #4]
80013c0: 6a52 ldr r2, [r2, #36] ; 0x24
80013c2: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
80013c4: 4293 cmp r3, r2
80013c6: d111 bne.n 80013ec <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
80013c8: 68fb ldr r3, [r7, #12]
80013ca: f403 3240 and.w r2, r3, #196608 ; 0x30000
80013ce: 687b ldr r3, [r7, #4]
80013d0: 6a9b ldr r3, [r3, #40] ; 0x28
80013d2: 085b lsrs r3, r3, #1
80013d4: 3b01 subs r3, #1
80013d6: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
80013d8: 429a cmp r2, r3
80013da: d107 bne.n 80013ec <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
80013dc: 68fb ldr r3, [r7, #12]
80013de: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
80013e2: 687b ldr r3, [r7, #4]
80013e4: 6adb ldr r3, [r3, #44] ; 0x2c
80013e6: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
80013e8: 429a cmp r2, r3
80013ea: d001 beq.n 80013f0 <HAL_RCC_OscConfig+0x4e0>
#endif
{
return HAL_ERROR;
80013ec: 2301 movs r3, #1
80013ee: e000 b.n 80013f2 <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
80013f0: 2300 movs r3, #0
}
80013f2: 4618 mov r0, r3
80013f4: 3718 adds r7, #24
80013f6: 46bd mov sp, r7
80013f8: bd80 pop {r7, pc}
80013fa: bf00 nop
80013fc: 40023800 .word 0x40023800
08001400 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001400: b580 push {r7, lr}
8001402: b084 sub sp, #16
8001404: af00 add r7, sp, #0
8001406: 6078 str r0, [r7, #4]
8001408: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
800140a: 687b ldr r3, [r7, #4]
800140c: 2b00 cmp r3, #0
800140e: d101 bne.n 8001414 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001410: 2301 movs r3, #1
8001412: e0cc b.n 80015ae <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001414: 4b68 ldr r3, [pc, #416] ; (80015b8 <HAL_RCC_ClockConfig+0x1b8>)
8001416: 681b ldr r3, [r3, #0]
8001418: f003 0307 and.w r3, r3, #7
800141c: 683a ldr r2, [r7, #0]
800141e: 429a cmp r2, r3
8001420: d90c bls.n 800143c <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001422: 4b65 ldr r3, [pc, #404] ; (80015b8 <HAL_RCC_ClockConfig+0x1b8>)
8001424: 683a ldr r2, [r7, #0]
8001426: b2d2 uxtb r2, r2
8001428: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800142a: 4b63 ldr r3, [pc, #396] ; (80015b8 <HAL_RCC_ClockConfig+0x1b8>)
800142c: 681b ldr r3, [r3, #0]
800142e: f003 0307 and.w r3, r3, #7
8001432: 683a ldr r2, [r7, #0]
8001434: 429a cmp r2, r3
8001436: d001 beq.n 800143c <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
8001438: 2301 movs r3, #1
800143a: e0b8 b.n 80015ae <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800143c: 687b ldr r3, [r7, #4]
800143e: 681b ldr r3, [r3, #0]
8001440: f003 0302 and.w r3, r3, #2
8001444: 2b00 cmp r3, #0
8001446: d020 beq.n 800148a <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001448: 687b ldr r3, [r7, #4]
800144a: 681b ldr r3, [r3, #0]
800144c: f003 0304 and.w r3, r3, #4
8001450: 2b00 cmp r3, #0
8001452: d005 beq.n 8001460 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001454: 4b59 ldr r3, [pc, #356] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
8001456: 689b ldr r3, [r3, #8]
8001458: 4a58 ldr r2, [pc, #352] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
800145a: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
800145e: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001460: 687b ldr r3, [r7, #4]
8001462: 681b ldr r3, [r3, #0]
8001464: f003 0308 and.w r3, r3, #8
8001468: 2b00 cmp r3, #0
800146a: d005 beq.n 8001478 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
800146c: 4b53 ldr r3, [pc, #332] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
800146e: 689b ldr r3, [r3, #8]
8001470: 4a52 ldr r2, [pc, #328] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
8001472: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8001476: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001478: 4b50 ldr r3, [pc, #320] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
800147a: 689b ldr r3, [r3, #8]
800147c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001480: 687b ldr r3, [r7, #4]
8001482: 689b ldr r3, [r3, #8]
8001484: 494d ldr r1, [pc, #308] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
8001486: 4313 orrs r3, r2
8001488: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800148a: 687b ldr r3, [r7, #4]
800148c: 681b ldr r3, [r3, #0]
800148e: f003 0301 and.w r3, r3, #1
8001492: 2b00 cmp r3, #0
8001494: d044 beq.n 8001520 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001496: 687b ldr r3, [r7, #4]
8001498: 685b ldr r3, [r3, #4]
800149a: 2b01 cmp r3, #1
800149c: d107 bne.n 80014ae <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800149e: 4b47 ldr r3, [pc, #284] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
80014a0: 681b ldr r3, [r3, #0]
80014a2: f403 3300 and.w r3, r3, #131072 ; 0x20000
80014a6: 2b00 cmp r3, #0
80014a8: d119 bne.n 80014de <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80014aa: 2301 movs r3, #1
80014ac: e07f b.n 80015ae <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
80014ae: 687b ldr r3, [r7, #4]
80014b0: 685b ldr r3, [r3, #4]
80014b2: 2b02 cmp r3, #2
80014b4: d003 beq.n 80014be <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
80014b6: 687b ldr r3, [r7, #4]
80014b8: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
80014ba: 2b03 cmp r3, #3
80014bc: d107 bne.n 80014ce <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80014be: 4b3f ldr r3, [pc, #252] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
80014c0: 681b ldr r3, [r3, #0]
80014c2: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80014c6: 2b00 cmp r3, #0
80014c8: d109 bne.n 80014de <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80014ca: 2301 movs r3, #1
80014cc: e06f b.n 80015ae <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
80014ce: 4b3b ldr r3, [pc, #236] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
80014d0: 681b ldr r3, [r3, #0]
80014d2: f003 0302 and.w r3, r3, #2
80014d6: 2b00 cmp r3, #0
80014d8: d101 bne.n 80014de <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
80014da: 2301 movs r3, #1
80014dc: e067 b.n 80015ae <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
80014de: 4b37 ldr r3, [pc, #220] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
80014e0: 689b ldr r3, [r3, #8]
80014e2: f023 0203 bic.w r2, r3, #3
80014e6: 687b ldr r3, [r7, #4]
80014e8: 685b ldr r3, [r3, #4]
80014ea: 4934 ldr r1, [pc, #208] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
80014ec: 4313 orrs r3, r2
80014ee: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
80014f0: f7ff fa7e bl 80009f0 <HAL_GetTick>
80014f4: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80014f6: e00a b.n 800150e <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80014f8: f7ff fa7a bl 80009f0 <HAL_GetTick>
80014fc: 4602 mov r2, r0
80014fe: 68fb ldr r3, [r7, #12]
8001500: 1ad3 subs r3, r2, r3
8001502: f241 3288 movw r2, #5000 ; 0x1388
8001506: 4293 cmp r3, r2
8001508: d901 bls.n 800150e <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
800150a: 2303 movs r3, #3
800150c: e04f b.n 80015ae <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800150e: 4b2b ldr r3, [pc, #172] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
8001510: 689b ldr r3, [r3, #8]
8001512: f003 020c and.w r2, r3, #12
8001516: 687b ldr r3, [r7, #4]
8001518: 685b ldr r3, [r3, #4]
800151a: 009b lsls r3, r3, #2
800151c: 429a cmp r2, r3
800151e: d1eb bne.n 80014f8 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001520: 4b25 ldr r3, [pc, #148] ; (80015b8 <HAL_RCC_ClockConfig+0x1b8>)
8001522: 681b ldr r3, [r3, #0]
8001524: f003 0307 and.w r3, r3, #7
8001528: 683a ldr r2, [r7, #0]
800152a: 429a cmp r2, r3
800152c: d20c bcs.n 8001548 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
800152e: 4b22 ldr r3, [pc, #136] ; (80015b8 <HAL_RCC_ClockConfig+0x1b8>)
8001530: 683a ldr r2, [r7, #0]
8001532: b2d2 uxtb r2, r2
8001534: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
8001536: 4b20 ldr r3, [pc, #128] ; (80015b8 <HAL_RCC_ClockConfig+0x1b8>)
8001538: 681b ldr r3, [r3, #0]
800153a: f003 0307 and.w r3, r3, #7
800153e: 683a ldr r2, [r7, #0]
8001540: 429a cmp r2, r3
8001542: d001 beq.n 8001548 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
8001544: 2301 movs r3, #1
8001546: e032 b.n 80015ae <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8001548: 687b ldr r3, [r7, #4]
800154a: 681b ldr r3, [r3, #0]
800154c: f003 0304 and.w r3, r3, #4
8001550: 2b00 cmp r3, #0
8001552: d008 beq.n 8001566 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001554: 4b19 ldr r3, [pc, #100] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
8001556: 689b ldr r3, [r3, #8]
8001558: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
800155c: 687b ldr r3, [r7, #4]
800155e: 68db ldr r3, [r3, #12]
8001560: 4916 ldr r1, [pc, #88] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
8001562: 4313 orrs r3, r2
8001564: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001566: 687b ldr r3, [r7, #4]
8001568: 681b ldr r3, [r3, #0]
800156a: f003 0308 and.w r3, r3, #8
800156e: 2b00 cmp r3, #0
8001570: d009 beq.n 8001586 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8001572: 4b12 ldr r3, [pc, #72] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
8001574: 689b ldr r3, [r3, #8]
8001576: f423 4260 bic.w r2, r3, #57344 ; 0xe000
800157a: 687b ldr r3, [r7, #4]
800157c: 691b ldr r3, [r3, #16]
800157e: 00db lsls r3, r3, #3
8001580: 490e ldr r1, [pc, #56] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
8001582: 4313 orrs r3, r2
8001584: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8001586: f000 f821 bl 80015cc <HAL_RCC_GetSysClockFreq>
800158a: 4602 mov r2, r0
800158c: 4b0b ldr r3, [pc, #44] ; (80015bc <HAL_RCC_ClockConfig+0x1bc>)
800158e: 689b ldr r3, [r3, #8]
8001590: 091b lsrs r3, r3, #4
8001592: f003 030f and.w r3, r3, #15
8001596: 490a ldr r1, [pc, #40] ; (80015c0 <HAL_RCC_ClockConfig+0x1c0>)
8001598: 5ccb ldrb r3, [r1, r3]
800159a: fa22 f303 lsr.w r3, r2, r3
800159e: 4a09 ldr r2, [pc, #36] ; (80015c4 <HAL_RCC_ClockConfig+0x1c4>)
80015a0: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
80015a2: 4b09 ldr r3, [pc, #36] ; (80015c8 <HAL_RCC_ClockConfig+0x1c8>)
80015a4: 681b ldr r3, [r3, #0]
80015a6: 4618 mov r0, r3
80015a8: f7ff f9de bl 8000968 <HAL_InitTick>
return HAL_OK;
80015ac: 2300 movs r3, #0
}
80015ae: 4618 mov r0, r3
80015b0: 3710 adds r7, #16
80015b2: 46bd mov sp, r7
80015b4: bd80 pop {r7, pc}
80015b6: bf00 nop
80015b8: 40023c00 .word 0x40023c00
80015bc: 40023800 .word 0x40023800
80015c0: 08002054 .word 0x08002054
80015c4: 20000000 .word 0x20000000
80015c8: 20000004 .word 0x20000004
080015cc <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
80015cc: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
80015d0: b094 sub sp, #80 ; 0x50
80015d2: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
80015d4: 2300 movs r3, #0
80015d6: 647b str r3, [r7, #68] ; 0x44
80015d8: 2300 movs r3, #0
80015da: 64fb str r3, [r7, #76] ; 0x4c
80015dc: 2300 movs r3, #0
80015de: 643b str r3, [r7, #64] ; 0x40
uint32_t sysclockfreq = 0U;
80015e0: 2300 movs r3, #0
80015e2: 64bb str r3, [r7, #72] ; 0x48
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
80015e4: 4b79 ldr r3, [pc, #484] ; (80017cc <HAL_RCC_GetSysClockFreq+0x200>)
80015e6: 689b ldr r3, [r3, #8]
80015e8: f003 030c and.w r3, r3, #12
80015ec: 2b08 cmp r3, #8
80015ee: d00d beq.n 800160c <HAL_RCC_GetSysClockFreq+0x40>
80015f0: 2b08 cmp r3, #8
80015f2: f200 80e1 bhi.w 80017b8 <HAL_RCC_GetSysClockFreq+0x1ec>
80015f6: 2b00 cmp r3, #0
80015f8: d002 beq.n 8001600 <HAL_RCC_GetSysClockFreq+0x34>
80015fa: 2b04 cmp r3, #4
80015fc: d003 beq.n 8001606 <HAL_RCC_GetSysClockFreq+0x3a>
80015fe: e0db b.n 80017b8 <HAL_RCC_GetSysClockFreq+0x1ec>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001600: 4b73 ldr r3, [pc, #460] ; (80017d0 <HAL_RCC_GetSysClockFreq+0x204>)
8001602: 64bb str r3, [r7, #72] ; 0x48
break;
8001604: e0db b.n 80017be <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8001606: 4b73 ldr r3, [pc, #460] ; (80017d4 <HAL_RCC_GetSysClockFreq+0x208>)
8001608: 64bb str r3, [r7, #72] ; 0x48
break;
800160a: e0d8 b.n 80017be <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
800160c: 4b6f ldr r3, [pc, #444] ; (80017cc <HAL_RCC_GetSysClockFreq+0x200>)
800160e: 685b ldr r3, [r3, #4]
8001610: f003 033f and.w r3, r3, #63 ; 0x3f
8001614: 647b str r3, [r7, #68] ; 0x44
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8001616: 4b6d ldr r3, [pc, #436] ; (80017cc <HAL_RCC_GetSysClockFreq+0x200>)
8001618: 685b ldr r3, [r3, #4]
800161a: f403 0380 and.w r3, r3, #4194304 ; 0x400000
800161e: 2b00 cmp r3, #0
8001620: d063 beq.n 80016ea <HAL_RCC_GetSysClockFreq+0x11e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001622: 4b6a ldr r3, [pc, #424] ; (80017cc <HAL_RCC_GetSysClockFreq+0x200>)
8001624: 685b ldr r3, [r3, #4]
8001626: 099b lsrs r3, r3, #6
8001628: 2200 movs r2, #0
800162a: 63bb str r3, [r7, #56] ; 0x38
800162c: 63fa str r2, [r7, #60] ; 0x3c
800162e: 6bbb ldr r3, [r7, #56] ; 0x38
8001630: f3c3 0308 ubfx r3, r3, #0, #9
8001634: 633b str r3, [r7, #48] ; 0x30
8001636: 2300 movs r3, #0
8001638: 637b str r3, [r7, #52] ; 0x34
800163a: e9d7 450c ldrd r4, r5, [r7, #48] ; 0x30
800163e: 4622 mov r2, r4
8001640: 462b mov r3, r5
8001642: f04f 0000 mov.w r0, #0
8001646: f04f 0100 mov.w r1, #0
800164a: 0159 lsls r1, r3, #5
800164c: ea41 61d2 orr.w r1, r1, r2, lsr #27
8001650: 0150 lsls r0, r2, #5
8001652: 4602 mov r2, r0
8001654: 460b mov r3, r1
8001656: 4621 mov r1, r4
8001658: 1a51 subs r1, r2, r1
800165a: 6139 str r1, [r7, #16]
800165c: 4629 mov r1, r5
800165e: eb63 0301 sbc.w r3, r3, r1
8001662: 617b str r3, [r7, #20]
8001664: f04f 0200 mov.w r2, #0
8001668: f04f 0300 mov.w r3, #0
800166c: e9d7 ab04 ldrd sl, fp, [r7, #16]
8001670: 4659 mov r1, fp
8001672: 018b lsls r3, r1, #6
8001674: 4651 mov r1, sl
8001676: ea43 6391 orr.w r3, r3, r1, lsr #26
800167a: 4651 mov r1, sl
800167c: 018a lsls r2, r1, #6
800167e: 4651 mov r1, sl
8001680: ebb2 0801 subs.w r8, r2, r1
8001684: 4659 mov r1, fp
8001686: eb63 0901 sbc.w r9, r3, r1
800168a: f04f 0200 mov.w r2, #0
800168e: f04f 0300 mov.w r3, #0
8001692: ea4f 03c9 mov.w r3, r9, lsl #3
8001696: ea43 7358 orr.w r3, r3, r8, lsr #29
800169a: ea4f 02c8 mov.w r2, r8, lsl #3
800169e: 4690 mov r8, r2
80016a0: 4699 mov r9, r3
80016a2: 4623 mov r3, r4
80016a4: eb18 0303 adds.w r3, r8, r3
80016a8: 60bb str r3, [r7, #8]
80016aa: 462b mov r3, r5
80016ac: eb49 0303 adc.w r3, r9, r3
80016b0: 60fb str r3, [r7, #12]
80016b2: f04f 0200 mov.w r2, #0
80016b6: f04f 0300 mov.w r3, #0
80016ba: e9d7 4502 ldrd r4, r5, [r7, #8]
80016be: 4629 mov r1, r5
80016c0: 024b lsls r3, r1, #9
80016c2: 4621 mov r1, r4
80016c4: ea43 53d1 orr.w r3, r3, r1, lsr #23
80016c8: 4621 mov r1, r4
80016ca: 024a lsls r2, r1, #9
80016cc: 4610 mov r0, r2
80016ce: 4619 mov r1, r3
80016d0: 6c7b ldr r3, [r7, #68] ; 0x44
80016d2: 2200 movs r2, #0
80016d4: 62bb str r3, [r7, #40] ; 0x28
80016d6: 62fa str r2, [r7, #44] ; 0x2c
80016d8: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
80016dc: f7fe fd7c bl 80001d8 <__aeabi_uldivmod>
80016e0: 4602 mov r2, r0
80016e2: 460b mov r3, r1
80016e4: 4613 mov r3, r2
80016e6: 64fb str r3, [r7, #76] ; 0x4c
80016e8: e058 b.n 800179c <HAL_RCC_GetSysClockFreq+0x1d0>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
80016ea: 4b38 ldr r3, [pc, #224] ; (80017cc <HAL_RCC_GetSysClockFreq+0x200>)
80016ec: 685b ldr r3, [r3, #4]
80016ee: 099b lsrs r3, r3, #6
80016f0: 2200 movs r2, #0
80016f2: 4618 mov r0, r3
80016f4: 4611 mov r1, r2
80016f6: f3c0 0308 ubfx r3, r0, #0, #9
80016fa: 623b str r3, [r7, #32]
80016fc: 2300 movs r3, #0
80016fe: 627b str r3, [r7, #36] ; 0x24
8001700: e9d7 8908 ldrd r8, r9, [r7, #32]
8001704: 4642 mov r2, r8
8001706: 464b mov r3, r9
8001708: f04f 0000 mov.w r0, #0
800170c: f04f 0100 mov.w r1, #0
8001710: 0159 lsls r1, r3, #5
8001712: ea41 61d2 orr.w r1, r1, r2, lsr #27
8001716: 0150 lsls r0, r2, #5
8001718: 4602 mov r2, r0
800171a: 460b mov r3, r1
800171c: 4641 mov r1, r8
800171e: ebb2 0a01 subs.w sl, r2, r1
8001722: 4649 mov r1, r9
8001724: eb63 0b01 sbc.w fp, r3, r1
8001728: f04f 0200 mov.w r2, #0
800172c: f04f 0300 mov.w r3, #0
8001730: ea4f 138b mov.w r3, fp, lsl #6
8001734: ea43 639a orr.w r3, r3, sl, lsr #26
8001738: ea4f 128a mov.w r2, sl, lsl #6
800173c: ebb2 040a subs.w r4, r2, sl
8001740: eb63 050b sbc.w r5, r3, fp
8001744: f04f 0200 mov.w r2, #0
8001748: f04f 0300 mov.w r3, #0
800174c: 00eb lsls r3, r5, #3
800174e: ea43 7354 orr.w r3, r3, r4, lsr #29
8001752: 00e2 lsls r2, r4, #3
8001754: 4614 mov r4, r2
8001756: 461d mov r5, r3
8001758: 4643 mov r3, r8
800175a: 18e3 adds r3, r4, r3
800175c: 603b str r3, [r7, #0]
800175e: 464b mov r3, r9
8001760: eb45 0303 adc.w r3, r5, r3
8001764: 607b str r3, [r7, #4]
8001766: f04f 0200 mov.w r2, #0
800176a: f04f 0300 mov.w r3, #0
800176e: e9d7 4500 ldrd r4, r5, [r7]
8001772: 4629 mov r1, r5
8001774: 028b lsls r3, r1, #10
8001776: 4621 mov r1, r4
8001778: ea43 5391 orr.w r3, r3, r1, lsr #22
800177c: 4621 mov r1, r4
800177e: 028a lsls r2, r1, #10
8001780: 4610 mov r0, r2
8001782: 4619 mov r1, r3
8001784: 6c7b ldr r3, [r7, #68] ; 0x44
8001786: 2200 movs r2, #0
8001788: 61bb str r3, [r7, #24]
800178a: 61fa str r2, [r7, #28]
800178c: e9d7 2306 ldrd r2, r3, [r7, #24]
8001790: f7fe fd22 bl 80001d8 <__aeabi_uldivmod>
8001794: 4602 mov r2, r0
8001796: 460b mov r3, r1
8001798: 4613 mov r3, r2
800179a: 64fb str r3, [r7, #76] ; 0x4c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
800179c: 4b0b ldr r3, [pc, #44] ; (80017cc <HAL_RCC_GetSysClockFreq+0x200>)
800179e: 685b ldr r3, [r3, #4]
80017a0: 0c1b lsrs r3, r3, #16
80017a2: f003 0303 and.w r3, r3, #3
80017a6: 3301 adds r3, #1
80017a8: 005b lsls r3, r3, #1
80017aa: 643b str r3, [r7, #64] ; 0x40
sysclockfreq = pllvco/pllp;
80017ac: 6cfa ldr r2, [r7, #76] ; 0x4c
80017ae: 6c3b ldr r3, [r7, #64] ; 0x40
80017b0: fbb2 f3f3 udiv r3, r2, r3
80017b4: 64bb str r3, [r7, #72] ; 0x48
break;
80017b6: e002 b.n 80017be <HAL_RCC_GetSysClockFreq+0x1f2>
}
default:
{
sysclockfreq = HSI_VALUE;
80017b8: 4b05 ldr r3, [pc, #20] ; (80017d0 <HAL_RCC_GetSysClockFreq+0x204>)
80017ba: 64bb str r3, [r7, #72] ; 0x48
break;
80017bc: bf00 nop
}
}
return sysclockfreq;
80017be: 6cbb ldr r3, [r7, #72] ; 0x48
}
80017c0: 4618 mov r0, r3
80017c2: 3750 adds r7, #80 ; 0x50
80017c4: 46bd mov sp, r7
80017c6: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80017ca: bf00 nop
80017cc: 40023800 .word 0x40023800
80017d0: 00f42400 .word 0x00f42400
80017d4: 007a1200 .word 0x007a1200
080017d8 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
80017d8: b480 push {r7}
80017da: af00 add r7, sp, #0
return SystemCoreClock;
80017dc: 4b03 ldr r3, [pc, #12] ; (80017ec <HAL_RCC_GetHCLKFreq+0x14>)
80017de: 681b ldr r3, [r3, #0]
}
80017e0: 4618 mov r0, r3
80017e2: 46bd mov sp, r7
80017e4: f85d 7b04 ldr.w r7, [sp], #4
80017e8: 4770 bx lr
80017ea: bf00 nop
80017ec: 20000000 .word 0x20000000
080017f0 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
80017f0: b580 push {r7, lr}
80017f2: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
80017f4: f7ff fff0 bl 80017d8 <HAL_RCC_GetHCLKFreq>
80017f8: 4602 mov r2, r0
80017fa: 4b05 ldr r3, [pc, #20] ; (8001810 <HAL_RCC_GetPCLK1Freq+0x20>)
80017fc: 689b ldr r3, [r3, #8]
80017fe: 0a9b lsrs r3, r3, #10
8001800: f003 0307 and.w r3, r3, #7
8001804: 4903 ldr r1, [pc, #12] ; (8001814 <HAL_RCC_GetPCLK1Freq+0x24>)
8001806: 5ccb ldrb r3, [r1, r3]
8001808: fa22 f303 lsr.w r3, r2, r3
}
800180c: 4618 mov r0, r3
800180e: bd80 pop {r7, pc}
8001810: 40023800 .word 0x40023800
8001814: 08002064 .word 0x08002064
08001818 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8001818: b580 push {r7, lr}
800181a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
800181c: f7ff ffdc bl 80017d8 <HAL_RCC_GetHCLKFreq>
8001820: 4602 mov r2, r0
8001822: 4b05 ldr r3, [pc, #20] ; (8001838 <HAL_RCC_GetPCLK2Freq+0x20>)
8001824: 689b ldr r3, [r3, #8]
8001826: 0b5b lsrs r3, r3, #13
8001828: f003 0307 and.w r3, r3, #7
800182c: 4903 ldr r1, [pc, #12] ; (800183c <HAL_RCC_GetPCLK2Freq+0x24>)
800182e: 5ccb ldrb r3, [r1, r3]
8001830: fa22 f303 lsr.w r3, r2, r3
}
8001834: 4618 mov r0, r3
8001836: bd80 pop {r7, pc}
8001838: 40023800 .word 0x40023800
800183c: 08002064 .word 0x08002064
08001840 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8001840: b580 push {r7, lr}
8001842: b082 sub sp, #8
8001844: af00 add r7, sp, #0
8001846: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8001848: 687b ldr r3, [r7, #4]
800184a: 2b00 cmp r3, #0
800184c: d101 bne.n 8001852 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800184e: 2301 movs r3, #1
8001850: e03f b.n 80018d2 <HAL_UART_Init+0x92>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
8001852: 687b ldr r3, [r7, #4]
8001854: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001858: b2db uxtb r3, r3
800185a: 2b00 cmp r3, #0
800185c: d106 bne.n 800186c <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
800185e: 687b ldr r3, [r7, #4]
8001860: 2200 movs r2, #0
8001862: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8001866: 6878 ldr r0, [r7, #4]
8001868: f7fe ffae bl 80007c8 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
800186c: 687b ldr r3, [r7, #4]
800186e: 2224 movs r2, #36 ; 0x24
8001870: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8001874: 687b ldr r3, [r7, #4]
8001876: 681b ldr r3, [r3, #0]
8001878: 68da ldr r2, [r3, #12]
800187a: 687b ldr r3, [r7, #4]
800187c: 681b ldr r3, [r3, #0]
800187e: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8001882: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8001884: 6878 ldr r0, [r7, #4]
8001886: f000 f939 bl 8001afc <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800188a: 687b ldr r3, [r7, #4]
800188c: 681b ldr r3, [r3, #0]
800188e: 691a ldr r2, [r3, #16]
8001890: 687b ldr r3, [r7, #4]
8001892: 681b ldr r3, [r3, #0]
8001894: f422 4290 bic.w r2, r2, #18432 ; 0x4800
8001898: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800189a: 687b ldr r3, [r7, #4]
800189c: 681b ldr r3, [r3, #0]
800189e: 695a ldr r2, [r3, #20]
80018a0: 687b ldr r3, [r7, #4]
80018a2: 681b ldr r3, [r3, #0]
80018a4: f022 022a bic.w r2, r2, #42 ; 0x2a
80018a8: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
80018aa: 687b ldr r3, [r7, #4]
80018ac: 681b ldr r3, [r3, #0]
80018ae: 68da ldr r2, [r3, #12]
80018b0: 687b ldr r3, [r7, #4]
80018b2: 681b ldr r3, [r3, #0]
80018b4: f442 5200 orr.w r2, r2, #8192 ; 0x2000
80018b8: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80018ba: 687b ldr r3, [r7, #4]
80018bc: 2200 movs r2, #0
80018be: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_READY;
80018c0: 687b ldr r3, [r7, #4]
80018c2: 2220 movs r2, #32
80018c4: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80018c8: 687b ldr r3, [r7, #4]
80018ca: 2220 movs r2, #32
80018cc: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
80018d0: 2300 movs r3, #0
}
80018d2: 4618 mov r0, r3
80018d4: 3708 adds r7, #8
80018d6: 46bd mov sp, r7
80018d8: bd80 pop {r7, pc}
080018da <HAL_UART_Receive>:
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
80018da: b580 push {r7, lr}
80018dc: b08a sub sp, #40 ; 0x28
80018de: af02 add r7, sp, #8
80018e0: 60f8 str r0, [r7, #12]
80018e2: 60b9 str r1, [r7, #8]
80018e4: 603b str r3, [r7, #0]
80018e6: 4613 mov r3, r2
80018e8: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
80018ea: 2300 movs r3, #0
80018ec: 617b str r3, [r7, #20]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
80018ee: 68fb ldr r3, [r7, #12]
80018f0: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
80018f4: b2db uxtb r3, r3
80018f6: 2b20 cmp r3, #32
80018f8: f040 808c bne.w 8001a14 <HAL_UART_Receive+0x13a>
{
if ((pData == NULL) || (Size == 0U))
80018fc: 68bb ldr r3, [r7, #8]
80018fe: 2b00 cmp r3, #0
8001900: d002 beq.n 8001908 <HAL_UART_Receive+0x2e>
8001902: 88fb ldrh r3, [r7, #6]
8001904: 2b00 cmp r3, #0
8001906: d101 bne.n 800190c <HAL_UART_Receive+0x32>
{
return HAL_ERROR;
8001908: 2301 movs r3, #1
800190a: e084 b.n 8001a16 <HAL_UART_Receive+0x13c>
}
/* Process Locked */
__HAL_LOCK(huart);
800190c: 68fb ldr r3, [r7, #12]
800190e: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8001912: 2b01 cmp r3, #1
8001914: d101 bne.n 800191a <HAL_UART_Receive+0x40>
8001916: 2302 movs r3, #2
8001918: e07d b.n 8001a16 <HAL_UART_Receive+0x13c>
800191a: 68fb ldr r3, [r7, #12]
800191c: 2201 movs r2, #1
800191e: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8001922: 68fb ldr r3, [r7, #12]
8001924: 2200 movs r2, #0
8001926: 641a str r2, [r3, #64] ; 0x40
huart->RxState = HAL_UART_STATE_BUSY_RX;
8001928: 68fb ldr r3, [r7, #12]
800192a: 2222 movs r2, #34 ; 0x22
800192c: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8001930: 68fb ldr r3, [r7, #12]
8001932: 2200 movs r2, #0
8001934: 631a str r2, [r3, #48] ; 0x30
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8001936: f7ff f85b bl 80009f0 <HAL_GetTick>
800193a: 6178 str r0, [r7, #20]
huart->RxXferSize = Size;
800193c: 68fb ldr r3, [r7, #12]
800193e: 88fa ldrh r2, [r7, #6]
8001940: 859a strh r2, [r3, #44] ; 0x2c
huart->RxXferCount = Size;
8001942: 68fb ldr r3, [r7, #12]
8001944: 88fa ldrh r2, [r7, #6]
8001946: 85da strh r2, [r3, #46] ; 0x2e
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8001948: 68fb ldr r3, [r7, #12]
800194a: 689b ldr r3, [r3, #8]
800194c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8001950: d108 bne.n 8001964 <HAL_UART_Receive+0x8a>
8001952: 68fb ldr r3, [r7, #12]
8001954: 691b ldr r3, [r3, #16]
8001956: 2b00 cmp r3, #0
8001958: d104 bne.n 8001964 <HAL_UART_Receive+0x8a>
{
pdata8bits = NULL;
800195a: 2300 movs r3, #0
800195c: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
800195e: 68bb ldr r3, [r7, #8]
8001960: 61bb str r3, [r7, #24]
8001962: e003 b.n 800196c <HAL_UART_Receive+0x92>
}
else
{
pdata8bits = pData;
8001964: 68bb ldr r3, [r7, #8]
8001966: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8001968: 2300 movs r3, #0
800196a: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
800196c: 68fb ldr r3, [r7, #12]
800196e: 2200 movs r2, #0
8001970: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Check the remain data to be received */
while (huart->RxXferCount > 0U)
8001974: e043 b.n 80019fe <HAL_UART_Receive+0x124>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
8001976: 683b ldr r3, [r7, #0]
8001978: 9300 str r3, [sp, #0]
800197a: 697b ldr r3, [r7, #20]
800197c: 2200 movs r2, #0
800197e: 2120 movs r1, #32
8001980: 68f8 ldr r0, [r7, #12]
8001982: f000 f84c bl 8001a1e <UART_WaitOnFlagUntilTimeout>
8001986: 4603 mov r3, r0
8001988: 2b00 cmp r3, #0
800198a: d001 beq.n 8001990 <HAL_UART_Receive+0xb6>
{
return HAL_TIMEOUT;
800198c: 2303 movs r3, #3
800198e: e042 b.n 8001a16 <HAL_UART_Receive+0x13c>
}
if (pdata8bits == NULL)
8001990: 69fb ldr r3, [r7, #28]
8001992: 2b00 cmp r3, #0
8001994: d10c bne.n 80019b0 <HAL_UART_Receive+0xd6>
{
*pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
8001996: 68fb ldr r3, [r7, #12]
8001998: 681b ldr r3, [r3, #0]
800199a: 685b ldr r3, [r3, #4]
800199c: b29b uxth r3, r3
800199e: f3c3 0308 ubfx r3, r3, #0, #9
80019a2: b29a uxth r2, r3
80019a4: 69bb ldr r3, [r7, #24]
80019a6: 801a strh r2, [r3, #0]
pdata16bits++;
80019a8: 69bb ldr r3, [r7, #24]
80019aa: 3302 adds r3, #2
80019ac: 61bb str r3, [r7, #24]
80019ae: e01f b.n 80019f0 <HAL_UART_Receive+0x116>
}
else
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
80019b0: 68fb ldr r3, [r7, #12]
80019b2: 689b ldr r3, [r3, #8]
80019b4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80019b8: d007 beq.n 80019ca <HAL_UART_Receive+0xf0>
80019ba: 68fb ldr r3, [r7, #12]
80019bc: 689b ldr r3, [r3, #8]
80019be: 2b00 cmp r3, #0
80019c0: d10a bne.n 80019d8 <HAL_UART_Receive+0xfe>
80019c2: 68fb ldr r3, [r7, #12]
80019c4: 691b ldr r3, [r3, #16]
80019c6: 2b00 cmp r3, #0
80019c8: d106 bne.n 80019d8 <HAL_UART_Receive+0xfe>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
80019ca: 68fb ldr r3, [r7, #12]
80019cc: 681b ldr r3, [r3, #0]
80019ce: 685b ldr r3, [r3, #4]
80019d0: b2da uxtb r2, r3
80019d2: 69fb ldr r3, [r7, #28]
80019d4: 701a strb r2, [r3, #0]
80019d6: e008 b.n 80019ea <HAL_UART_Receive+0x110>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
80019d8: 68fb ldr r3, [r7, #12]
80019da: 681b ldr r3, [r3, #0]
80019dc: 685b ldr r3, [r3, #4]
80019de: b2db uxtb r3, r3
80019e0: f003 037f and.w r3, r3, #127 ; 0x7f
80019e4: b2da uxtb r2, r3
80019e6: 69fb ldr r3, [r7, #28]
80019e8: 701a strb r2, [r3, #0]
}
pdata8bits++;
80019ea: 69fb ldr r3, [r7, #28]
80019ec: 3301 adds r3, #1
80019ee: 61fb str r3, [r7, #28]
}
huart->RxXferCount--;
80019f0: 68fb ldr r3, [r7, #12]
80019f2: 8ddb ldrh r3, [r3, #46] ; 0x2e
80019f4: b29b uxth r3, r3
80019f6: 3b01 subs r3, #1
80019f8: b29a uxth r2, r3
80019fa: 68fb ldr r3, [r7, #12]
80019fc: 85da strh r2, [r3, #46] ; 0x2e
while (huart->RxXferCount > 0U)
80019fe: 68fb ldr r3, [r7, #12]
8001a00: 8ddb ldrh r3, [r3, #46] ; 0x2e
8001a02: b29b uxth r3, r3
8001a04: 2b00 cmp r3, #0
8001a06: d1b6 bne.n 8001976 <HAL_UART_Receive+0x9c>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8001a08: 68fb ldr r3, [r7, #12]
8001a0a: 2220 movs r2, #32
8001a0c: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8001a10: 2300 movs r3, #0
8001a12: e000 b.n 8001a16 <HAL_UART_Receive+0x13c>
}
else
{
return HAL_BUSY;
8001a14: 2302 movs r3, #2
}
}
8001a16: 4618 mov r0, r3
8001a18: 3720 adds r7, #32
8001a1a: 46bd mov sp, r7
8001a1c: bd80 pop {r7, pc}
08001a1e <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8001a1e: b580 push {r7, lr}
8001a20: b090 sub sp, #64 ; 0x40
8001a22: af00 add r7, sp, #0
8001a24: 60f8 str r0, [r7, #12]
8001a26: 60b9 str r1, [r7, #8]
8001a28: 603b str r3, [r7, #0]
8001a2a: 4613 mov r3, r2
8001a2c: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8001a2e: e050 b.n 8001ad2 <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8001a30: 6cbb ldr r3, [r7, #72] ; 0x48
8001a32: f1b3 3fff cmp.w r3, #4294967295
8001a36: d04c beq.n 8001ad2 <UART_WaitOnFlagUntilTimeout+0xb4>
{
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
8001a38: 6cbb ldr r3, [r7, #72] ; 0x48
8001a3a: 2b00 cmp r3, #0
8001a3c: d007 beq.n 8001a4e <UART_WaitOnFlagUntilTimeout+0x30>
8001a3e: f7fe ffd7 bl 80009f0 <HAL_GetTick>
8001a42: 4602 mov r2, r0
8001a44: 683b ldr r3, [r7, #0]
8001a46: 1ad3 subs r3, r2, r3
8001a48: 6cba ldr r2, [r7, #72] ; 0x48
8001a4a: 429a cmp r2, r3
8001a4c: d241 bcs.n 8001ad2 <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
8001a4e: 68fb ldr r3, [r7, #12]
8001a50: 681b ldr r3, [r3, #0]
8001a52: 330c adds r3, #12
8001a54: 62bb str r3, [r7, #40] ; 0x28
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8001a56: 6abb ldr r3, [r7, #40] ; 0x28
8001a58: e853 3f00 ldrex r3, [r3]
8001a5c: 627b str r3, [r7, #36] ; 0x24
return(result);
8001a5e: 6a7b ldr r3, [r7, #36] ; 0x24
8001a60: f423 73d0 bic.w r3, r3, #416 ; 0x1a0
8001a64: 63fb str r3, [r7, #60] ; 0x3c
8001a66: 68fb ldr r3, [r7, #12]
8001a68: 681b ldr r3, [r3, #0]
8001a6a: 330c adds r3, #12
8001a6c: 6bfa ldr r2, [r7, #60] ; 0x3c
8001a6e: 637a str r2, [r7, #52] ; 0x34
8001a70: 633b str r3, [r7, #48] ; 0x30
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8001a72: 6b39 ldr r1, [r7, #48] ; 0x30
8001a74: 6b7a ldr r2, [r7, #52] ; 0x34
8001a76: e841 2300 strex r3, r2, [r1]
8001a7a: 62fb str r3, [r7, #44] ; 0x2c
return(result);
8001a7c: 6afb ldr r3, [r7, #44] ; 0x2c
8001a7e: 2b00 cmp r3, #0
8001a80: d1e5 bne.n 8001a4e <UART_WaitOnFlagUntilTimeout+0x30>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8001a82: 68fb ldr r3, [r7, #12]
8001a84: 681b ldr r3, [r3, #0]
8001a86: 3314 adds r3, #20
8001a88: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8001a8a: 697b ldr r3, [r7, #20]
8001a8c: e853 3f00 ldrex r3, [r3]
8001a90: 613b str r3, [r7, #16]
return(result);
8001a92: 693b ldr r3, [r7, #16]
8001a94: f023 0301 bic.w r3, r3, #1
8001a98: 63bb str r3, [r7, #56] ; 0x38
8001a9a: 68fb ldr r3, [r7, #12]
8001a9c: 681b ldr r3, [r3, #0]
8001a9e: 3314 adds r3, #20
8001aa0: 6bba ldr r2, [r7, #56] ; 0x38
8001aa2: 623a str r2, [r7, #32]
8001aa4: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8001aa6: 69f9 ldr r1, [r7, #28]
8001aa8: 6a3a ldr r2, [r7, #32]
8001aaa: e841 2300 strex r3, r2, [r1]
8001aae: 61bb str r3, [r7, #24]
return(result);
8001ab0: 69bb ldr r3, [r7, #24]
8001ab2: 2b00 cmp r3, #0
8001ab4: d1e5 bne.n 8001a82 <UART_WaitOnFlagUntilTimeout+0x64>
huart->gState = HAL_UART_STATE_READY;
8001ab6: 68fb ldr r3, [r7, #12]
8001ab8: 2220 movs r2, #32
8001aba: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
8001abe: 68fb ldr r3, [r7, #12]
8001ac0: 2220 movs r2, #32
8001ac2: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Process Unlocked */
__HAL_UNLOCK(huart);
8001ac6: 68fb ldr r3, [r7, #12]
8001ac8: 2200 movs r2, #0
8001aca: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
8001ace: 2303 movs r3, #3
8001ad0: e00f b.n 8001af2 <UART_WaitOnFlagUntilTimeout+0xd4>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8001ad2: 68fb ldr r3, [r7, #12]
8001ad4: 681b ldr r3, [r3, #0]
8001ad6: 681a ldr r2, [r3, #0]
8001ad8: 68bb ldr r3, [r7, #8]
8001ada: 4013 ands r3, r2
8001adc: 68ba ldr r2, [r7, #8]
8001ade: 429a cmp r2, r3
8001ae0: bf0c ite eq
8001ae2: 2301 moveq r3, #1
8001ae4: 2300 movne r3, #0
8001ae6: b2db uxtb r3, r3
8001ae8: 461a mov r2, r3
8001aea: 79fb ldrb r3, [r7, #7]
8001aec: 429a cmp r2, r3
8001aee: d09f beq.n 8001a30 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
8001af0: 2300 movs r3, #0
}
8001af2: 4618 mov r0, r3
8001af4: 3740 adds r7, #64 ; 0x40
8001af6: 46bd mov sp, r7
8001af8: bd80 pop {r7, pc}
...
08001afc <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8001afc: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001b00: b0c0 sub sp, #256 ; 0x100
8001b02: af00 add r7, sp, #0
8001b04: f8c7 00f4 str.w r0, [r7, #244] ; 0xf4
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8001b08: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b0c: 681b ldr r3, [r3, #0]
8001b0e: 691b ldr r3, [r3, #16]
8001b10: f423 5040 bic.w r0, r3, #12288 ; 0x3000
8001b14: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b18: 68d9 ldr r1, [r3, #12]
8001b1a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b1e: 681a ldr r2, [r3, #0]
8001b20: ea40 0301 orr.w r3, r0, r1
8001b24: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
8001b26: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b2a: 689a ldr r2, [r3, #8]
8001b2c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b30: 691b ldr r3, [r3, #16]
8001b32: 431a orrs r2, r3
8001b34: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b38: 695b ldr r3, [r3, #20]
8001b3a: 431a orrs r2, r3
8001b3c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b40: 69db ldr r3, [r3, #28]
8001b42: 4313 orrs r3, r2
8001b44: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8
MODIFY_REG(huart->Instance->CR1,
8001b48: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b4c: 681b ldr r3, [r3, #0]
8001b4e: 68db ldr r3, [r3, #12]
8001b50: f423 4116 bic.w r1, r3, #38400 ; 0x9600
8001b54: f021 010c bic.w r1, r1, #12
8001b58: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b5c: 681a ldr r2, [r3, #0]
8001b5e: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8
8001b62: 430b orrs r3, r1
8001b64: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8001b66: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b6a: 681b ldr r3, [r3, #0]
8001b6c: 695b ldr r3, [r3, #20]
8001b6e: f423 7040 bic.w r0, r3, #768 ; 0x300
8001b72: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b76: 6999 ldr r1, [r3, #24]
8001b78: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b7c: 681a ldr r2, [r3, #0]
8001b7e: ea40 0301 orr.w r3, r0, r1
8001b82: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
8001b84: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b88: 681a ldr r2, [r3, #0]
8001b8a: 4b8f ldr r3, [pc, #572] ; (8001dc8 <UART_SetConfig+0x2cc>)
8001b8c: 429a cmp r2, r3
8001b8e: d005 beq.n 8001b9c <UART_SetConfig+0xa0>
8001b90: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001b94: 681a ldr r2, [r3, #0]
8001b96: 4b8d ldr r3, [pc, #564] ; (8001dcc <UART_SetConfig+0x2d0>)
8001b98: 429a cmp r2, r3
8001b9a: d104 bne.n 8001ba6 <UART_SetConfig+0xaa>
{
pclk = HAL_RCC_GetPCLK2Freq();
8001b9c: f7ff fe3c bl 8001818 <HAL_RCC_GetPCLK2Freq>
8001ba0: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
8001ba4: e003 b.n 8001bae <UART_SetConfig+0xb2>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
8001ba6: f7ff fe23 bl 80017f0 <HAL_RCC_GetPCLK1Freq>
8001baa: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8001bae: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001bb2: 69db ldr r3, [r3, #28]
8001bb4: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8001bb8: f040 810c bne.w 8001dd4 <UART_SetConfig+0x2d8>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
8001bbc: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001bc0: 2200 movs r2, #0
8001bc2: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8
8001bc6: f8c7 20ec str.w r2, [r7, #236] ; 0xec
8001bca: e9d7 453a ldrd r4, r5, [r7, #232] ; 0xe8
8001bce: 4622 mov r2, r4
8001bd0: 462b mov r3, r5
8001bd2: 1891 adds r1, r2, r2
8001bd4: 65b9 str r1, [r7, #88] ; 0x58
8001bd6: 415b adcs r3, r3
8001bd8: 65fb str r3, [r7, #92] ; 0x5c
8001bda: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58
8001bde: 4621 mov r1, r4
8001be0: eb12 0801 adds.w r8, r2, r1
8001be4: 4629 mov r1, r5
8001be6: eb43 0901 adc.w r9, r3, r1
8001bea: f04f 0200 mov.w r2, #0
8001bee: f04f 0300 mov.w r3, #0
8001bf2: ea4f 03c9 mov.w r3, r9, lsl #3
8001bf6: ea43 7358 orr.w r3, r3, r8, lsr #29
8001bfa: ea4f 02c8 mov.w r2, r8, lsl #3
8001bfe: 4690 mov r8, r2
8001c00: 4699 mov r9, r3
8001c02: 4623 mov r3, r4
8001c04: eb18 0303 adds.w r3, r8, r3
8001c08: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
8001c0c: 462b mov r3, r5
8001c0e: eb49 0303 adc.w r3, r9, r3
8001c12: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
8001c16: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001c1a: 685b ldr r3, [r3, #4]
8001c1c: 2200 movs r2, #0
8001c1e: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
8001c22: f8c7 20dc str.w r2, [r7, #220] ; 0xdc
8001c26: e9d7 1236 ldrd r1, r2, [r7, #216] ; 0xd8
8001c2a: 460b mov r3, r1
8001c2c: 18db adds r3, r3, r3
8001c2e: 653b str r3, [r7, #80] ; 0x50
8001c30: 4613 mov r3, r2
8001c32: eb42 0303 adc.w r3, r2, r3
8001c36: 657b str r3, [r7, #84] ; 0x54
8001c38: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50
8001c3c: e9d7 0138 ldrd r0, r1, [r7, #224] ; 0xe0
8001c40: f7fe faca bl 80001d8 <__aeabi_uldivmod>
8001c44: 4602 mov r2, r0
8001c46: 460b mov r3, r1
8001c48: 4b61 ldr r3, [pc, #388] ; (8001dd0 <UART_SetConfig+0x2d4>)
8001c4a: fba3 2302 umull r2, r3, r3, r2
8001c4e: 095b lsrs r3, r3, #5
8001c50: 011c lsls r4, r3, #4
8001c52: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001c56: 2200 movs r2, #0
8001c58: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
8001c5c: f8c7 20d4 str.w r2, [r7, #212] ; 0xd4
8001c60: e9d7 8934 ldrd r8, r9, [r7, #208] ; 0xd0
8001c64: 4642 mov r2, r8
8001c66: 464b mov r3, r9
8001c68: 1891 adds r1, r2, r2
8001c6a: 64b9 str r1, [r7, #72] ; 0x48
8001c6c: 415b adcs r3, r3
8001c6e: 64fb str r3, [r7, #76] ; 0x4c
8001c70: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48
8001c74: 4641 mov r1, r8
8001c76: eb12 0a01 adds.w sl, r2, r1
8001c7a: 4649 mov r1, r9
8001c7c: eb43 0b01 adc.w fp, r3, r1
8001c80: f04f 0200 mov.w r2, #0
8001c84: f04f 0300 mov.w r3, #0
8001c88: ea4f 03cb mov.w r3, fp, lsl #3
8001c8c: ea43 735a orr.w r3, r3, sl, lsr #29
8001c90: ea4f 02ca mov.w r2, sl, lsl #3
8001c94: 4692 mov sl, r2
8001c96: 469b mov fp, r3
8001c98: 4643 mov r3, r8
8001c9a: eb1a 0303 adds.w r3, sl, r3
8001c9e: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
8001ca2: 464b mov r3, r9
8001ca4: eb4b 0303 adc.w r3, fp, r3
8001ca8: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
8001cac: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001cb0: 685b ldr r3, [r3, #4]
8001cb2: 2200 movs r2, #0
8001cb4: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
8001cb8: f8c7 20c4 str.w r2, [r7, #196] ; 0xc4
8001cbc: e9d7 1230 ldrd r1, r2, [r7, #192] ; 0xc0
8001cc0: 460b mov r3, r1
8001cc2: 18db adds r3, r3, r3
8001cc4: 643b str r3, [r7, #64] ; 0x40
8001cc6: 4613 mov r3, r2
8001cc8: eb42 0303 adc.w r3, r2, r3
8001ccc: 647b str r3, [r7, #68] ; 0x44
8001cce: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40
8001cd2: e9d7 0132 ldrd r0, r1, [r7, #200] ; 0xc8
8001cd6: f7fe fa7f bl 80001d8 <__aeabi_uldivmod>
8001cda: 4602 mov r2, r0
8001cdc: 460b mov r3, r1
8001cde: 4611 mov r1, r2
8001ce0: 4b3b ldr r3, [pc, #236] ; (8001dd0 <UART_SetConfig+0x2d4>)
8001ce2: fba3 2301 umull r2, r3, r3, r1
8001ce6: 095b lsrs r3, r3, #5
8001ce8: 2264 movs r2, #100 ; 0x64
8001cea: fb02 f303 mul.w r3, r2, r3
8001cee: 1acb subs r3, r1, r3
8001cf0: 00db lsls r3, r3, #3
8001cf2: f103 0232 add.w r2, r3, #50 ; 0x32
8001cf6: 4b36 ldr r3, [pc, #216] ; (8001dd0 <UART_SetConfig+0x2d4>)
8001cf8: fba3 2302 umull r2, r3, r3, r2
8001cfc: 095b lsrs r3, r3, #5
8001cfe: 005b lsls r3, r3, #1
8001d00: f403 73f8 and.w r3, r3, #496 ; 0x1f0
8001d04: 441c add r4, r3
8001d06: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001d0a: 2200 movs r2, #0
8001d0c: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
8001d10: f8c7 20bc str.w r2, [r7, #188] ; 0xbc
8001d14: e9d7 892e ldrd r8, r9, [r7, #184] ; 0xb8
8001d18: 4642 mov r2, r8
8001d1a: 464b mov r3, r9
8001d1c: 1891 adds r1, r2, r2
8001d1e: 63b9 str r1, [r7, #56] ; 0x38
8001d20: 415b adcs r3, r3
8001d22: 63fb str r3, [r7, #60] ; 0x3c
8001d24: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38
8001d28: 4641 mov r1, r8
8001d2a: 1851 adds r1, r2, r1
8001d2c: 6339 str r1, [r7, #48] ; 0x30
8001d2e: 4649 mov r1, r9
8001d30: 414b adcs r3, r1
8001d32: 637b str r3, [r7, #52] ; 0x34
8001d34: f04f 0200 mov.w r2, #0
8001d38: f04f 0300 mov.w r3, #0
8001d3c: e9d7 ab0c ldrd sl, fp, [r7, #48] ; 0x30
8001d40: 4659 mov r1, fp
8001d42: 00cb lsls r3, r1, #3
8001d44: 4651 mov r1, sl
8001d46: ea43 7351 orr.w r3, r3, r1, lsr #29
8001d4a: 4651 mov r1, sl
8001d4c: 00ca lsls r2, r1, #3
8001d4e: 4610 mov r0, r2
8001d50: 4619 mov r1, r3
8001d52: 4603 mov r3, r0
8001d54: 4642 mov r2, r8
8001d56: 189b adds r3, r3, r2
8001d58: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
8001d5c: 464b mov r3, r9
8001d5e: 460a mov r2, r1
8001d60: eb42 0303 adc.w r3, r2, r3
8001d64: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
8001d68: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001d6c: 685b ldr r3, [r3, #4]
8001d6e: 2200 movs r2, #0
8001d70: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
8001d74: f8c7 20ac str.w r2, [r7, #172] ; 0xac
8001d78: e9d7 122a ldrd r1, r2, [r7, #168] ; 0xa8
8001d7c: 460b mov r3, r1
8001d7e: 18db adds r3, r3, r3
8001d80: 62bb str r3, [r7, #40] ; 0x28
8001d82: 4613 mov r3, r2
8001d84: eb42 0303 adc.w r3, r2, r3
8001d88: 62fb str r3, [r7, #44] ; 0x2c
8001d8a: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
8001d8e: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0
8001d92: f7fe fa21 bl 80001d8 <__aeabi_uldivmod>
8001d96: 4602 mov r2, r0
8001d98: 460b mov r3, r1
8001d9a: 4b0d ldr r3, [pc, #52] ; (8001dd0 <UART_SetConfig+0x2d4>)
8001d9c: fba3 1302 umull r1, r3, r3, r2
8001da0: 095b lsrs r3, r3, #5
8001da2: 2164 movs r1, #100 ; 0x64
8001da4: fb01 f303 mul.w r3, r1, r3
8001da8: 1ad3 subs r3, r2, r3
8001daa: 00db lsls r3, r3, #3
8001dac: 3332 adds r3, #50 ; 0x32
8001dae: 4a08 ldr r2, [pc, #32] ; (8001dd0 <UART_SetConfig+0x2d4>)
8001db0: fba2 2303 umull r2, r3, r2, r3
8001db4: 095b lsrs r3, r3, #5
8001db6: f003 0207 and.w r2, r3, #7
8001dba: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001dbe: 681b ldr r3, [r3, #0]
8001dc0: 4422 add r2, r4
8001dc2: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
8001dc4: e106 b.n 8001fd4 <UART_SetConfig+0x4d8>
8001dc6: bf00 nop
8001dc8: 40011000 .word 0x40011000
8001dcc: 40011400 .word 0x40011400
8001dd0: 51eb851f .word 0x51eb851f
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8001dd4: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001dd8: 2200 movs r2, #0
8001dda: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
8001dde: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
8001de2: e9d7 8928 ldrd r8, r9, [r7, #160] ; 0xa0
8001de6: 4642 mov r2, r8
8001de8: 464b mov r3, r9
8001dea: 1891 adds r1, r2, r2
8001dec: 6239 str r1, [r7, #32]
8001dee: 415b adcs r3, r3
8001df0: 627b str r3, [r7, #36] ; 0x24
8001df2: e9d7 2308 ldrd r2, r3, [r7, #32]
8001df6: 4641 mov r1, r8
8001df8: 1854 adds r4, r2, r1
8001dfa: 4649 mov r1, r9
8001dfc: eb43 0501 adc.w r5, r3, r1
8001e00: f04f 0200 mov.w r2, #0
8001e04: f04f 0300 mov.w r3, #0
8001e08: 00eb lsls r3, r5, #3
8001e0a: ea43 7354 orr.w r3, r3, r4, lsr #29
8001e0e: 00e2 lsls r2, r4, #3
8001e10: 4614 mov r4, r2
8001e12: 461d mov r5, r3
8001e14: 4643 mov r3, r8
8001e16: 18e3 adds r3, r4, r3
8001e18: f8c7 3098 str.w r3, [r7, #152] ; 0x98
8001e1c: 464b mov r3, r9
8001e1e: eb45 0303 adc.w r3, r5, r3
8001e22: f8c7 309c str.w r3, [r7, #156] ; 0x9c
8001e26: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001e2a: 685b ldr r3, [r3, #4]
8001e2c: 2200 movs r2, #0
8001e2e: f8c7 3090 str.w r3, [r7, #144] ; 0x90
8001e32: f8c7 2094 str.w r2, [r7, #148] ; 0x94
8001e36: f04f 0200 mov.w r2, #0
8001e3a: f04f 0300 mov.w r3, #0
8001e3e: e9d7 4524 ldrd r4, r5, [r7, #144] ; 0x90
8001e42: 4629 mov r1, r5
8001e44: 008b lsls r3, r1, #2
8001e46: 4621 mov r1, r4
8001e48: ea43 7391 orr.w r3, r3, r1, lsr #30
8001e4c: 4621 mov r1, r4
8001e4e: 008a lsls r2, r1, #2
8001e50: e9d7 0126 ldrd r0, r1, [r7, #152] ; 0x98
8001e54: f7fe f9c0 bl 80001d8 <__aeabi_uldivmod>
8001e58: 4602 mov r2, r0
8001e5a: 460b mov r3, r1
8001e5c: 4b60 ldr r3, [pc, #384] ; (8001fe0 <UART_SetConfig+0x4e4>)
8001e5e: fba3 2302 umull r2, r3, r3, r2
8001e62: 095b lsrs r3, r3, #5
8001e64: 011c lsls r4, r3, #4
8001e66: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001e6a: 2200 movs r2, #0
8001e6c: f8c7 3088 str.w r3, [r7, #136] ; 0x88
8001e70: f8c7 208c str.w r2, [r7, #140] ; 0x8c
8001e74: e9d7 8922 ldrd r8, r9, [r7, #136] ; 0x88
8001e78: 4642 mov r2, r8
8001e7a: 464b mov r3, r9
8001e7c: 1891 adds r1, r2, r2
8001e7e: 61b9 str r1, [r7, #24]
8001e80: 415b adcs r3, r3
8001e82: 61fb str r3, [r7, #28]
8001e84: e9d7 2306 ldrd r2, r3, [r7, #24]
8001e88: 4641 mov r1, r8
8001e8a: 1851 adds r1, r2, r1
8001e8c: 6139 str r1, [r7, #16]
8001e8e: 4649 mov r1, r9
8001e90: 414b adcs r3, r1
8001e92: 617b str r3, [r7, #20]
8001e94: f04f 0200 mov.w r2, #0
8001e98: f04f 0300 mov.w r3, #0
8001e9c: e9d7 ab04 ldrd sl, fp, [r7, #16]
8001ea0: 4659 mov r1, fp
8001ea2: 00cb lsls r3, r1, #3
8001ea4: 4651 mov r1, sl
8001ea6: ea43 7351 orr.w r3, r3, r1, lsr #29
8001eaa: 4651 mov r1, sl
8001eac: 00ca lsls r2, r1, #3
8001eae: 4610 mov r0, r2
8001eb0: 4619 mov r1, r3
8001eb2: 4603 mov r3, r0
8001eb4: 4642 mov r2, r8
8001eb6: 189b adds r3, r3, r2
8001eb8: f8c7 3080 str.w r3, [r7, #128] ; 0x80
8001ebc: 464b mov r3, r9
8001ebe: 460a mov r2, r1
8001ec0: eb42 0303 adc.w r3, r2, r3
8001ec4: f8c7 3084 str.w r3, [r7, #132] ; 0x84
8001ec8: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001ecc: 685b ldr r3, [r3, #4]
8001ece: 2200 movs r2, #0
8001ed0: 67bb str r3, [r7, #120] ; 0x78
8001ed2: 67fa str r2, [r7, #124] ; 0x7c
8001ed4: f04f 0200 mov.w r2, #0
8001ed8: f04f 0300 mov.w r3, #0
8001edc: e9d7 891e ldrd r8, r9, [r7, #120] ; 0x78
8001ee0: 4649 mov r1, r9
8001ee2: 008b lsls r3, r1, #2
8001ee4: 4641 mov r1, r8
8001ee6: ea43 7391 orr.w r3, r3, r1, lsr #30
8001eea: 4641 mov r1, r8
8001eec: 008a lsls r2, r1, #2
8001eee: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80
8001ef2: f7fe f971 bl 80001d8 <__aeabi_uldivmod>
8001ef6: 4602 mov r2, r0
8001ef8: 460b mov r3, r1
8001efa: 4611 mov r1, r2
8001efc: 4b38 ldr r3, [pc, #224] ; (8001fe0 <UART_SetConfig+0x4e4>)
8001efe: fba3 2301 umull r2, r3, r3, r1
8001f02: 095b lsrs r3, r3, #5
8001f04: 2264 movs r2, #100 ; 0x64
8001f06: fb02 f303 mul.w r3, r2, r3
8001f0a: 1acb subs r3, r1, r3
8001f0c: 011b lsls r3, r3, #4
8001f0e: 3332 adds r3, #50 ; 0x32
8001f10: 4a33 ldr r2, [pc, #204] ; (8001fe0 <UART_SetConfig+0x4e4>)
8001f12: fba2 2303 umull r2, r3, r2, r3
8001f16: 095b lsrs r3, r3, #5
8001f18: f003 03f0 and.w r3, r3, #240 ; 0xf0
8001f1c: 441c add r4, r3
8001f1e: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001f22: 2200 movs r2, #0
8001f24: 673b str r3, [r7, #112] ; 0x70
8001f26: 677a str r2, [r7, #116] ; 0x74
8001f28: e9d7 891c ldrd r8, r9, [r7, #112] ; 0x70
8001f2c: 4642 mov r2, r8
8001f2e: 464b mov r3, r9
8001f30: 1891 adds r1, r2, r2
8001f32: 60b9 str r1, [r7, #8]
8001f34: 415b adcs r3, r3
8001f36: 60fb str r3, [r7, #12]
8001f38: e9d7 2302 ldrd r2, r3, [r7, #8]
8001f3c: 4641 mov r1, r8
8001f3e: 1851 adds r1, r2, r1
8001f40: 6039 str r1, [r7, #0]
8001f42: 4649 mov r1, r9
8001f44: 414b adcs r3, r1
8001f46: 607b str r3, [r7, #4]
8001f48: f04f 0200 mov.w r2, #0
8001f4c: f04f 0300 mov.w r3, #0
8001f50: e9d7 ab00 ldrd sl, fp, [r7]
8001f54: 4659 mov r1, fp
8001f56: 00cb lsls r3, r1, #3
8001f58: 4651 mov r1, sl
8001f5a: ea43 7351 orr.w r3, r3, r1, lsr #29
8001f5e: 4651 mov r1, sl
8001f60: 00ca lsls r2, r1, #3
8001f62: 4610 mov r0, r2
8001f64: 4619 mov r1, r3
8001f66: 4603 mov r3, r0
8001f68: 4642 mov r2, r8
8001f6a: 189b adds r3, r3, r2
8001f6c: 66bb str r3, [r7, #104] ; 0x68
8001f6e: 464b mov r3, r9
8001f70: 460a mov r2, r1
8001f72: eb42 0303 adc.w r3, r2, r3
8001f76: 66fb str r3, [r7, #108] ; 0x6c
8001f78: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001f7c: 685b ldr r3, [r3, #4]
8001f7e: 2200 movs r2, #0
8001f80: 663b str r3, [r7, #96] ; 0x60
8001f82: 667a str r2, [r7, #100] ; 0x64
8001f84: f04f 0200 mov.w r2, #0
8001f88: f04f 0300 mov.w r3, #0
8001f8c: e9d7 8918 ldrd r8, r9, [r7, #96] ; 0x60
8001f90: 4649 mov r1, r9
8001f92: 008b lsls r3, r1, #2
8001f94: 4641 mov r1, r8
8001f96: ea43 7391 orr.w r3, r3, r1, lsr #30
8001f9a: 4641 mov r1, r8
8001f9c: 008a lsls r2, r1, #2
8001f9e: e9d7 011a ldrd r0, r1, [r7, #104] ; 0x68
8001fa2: f7fe f919 bl 80001d8 <__aeabi_uldivmod>
8001fa6: 4602 mov r2, r0
8001fa8: 460b mov r3, r1
8001faa: 4b0d ldr r3, [pc, #52] ; (8001fe0 <UART_SetConfig+0x4e4>)
8001fac: fba3 1302 umull r1, r3, r3, r2
8001fb0: 095b lsrs r3, r3, #5
8001fb2: 2164 movs r1, #100 ; 0x64
8001fb4: fb01 f303 mul.w r3, r1, r3
8001fb8: 1ad3 subs r3, r2, r3
8001fba: 011b lsls r3, r3, #4
8001fbc: 3332 adds r3, #50 ; 0x32
8001fbe: 4a08 ldr r2, [pc, #32] ; (8001fe0 <UART_SetConfig+0x4e4>)
8001fc0: fba2 2303 umull r2, r3, r2, r3
8001fc4: 095b lsrs r3, r3, #5
8001fc6: f003 020f and.w r2, r3, #15
8001fca: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001fce: 681b ldr r3, [r3, #0]
8001fd0: 4422 add r2, r4
8001fd2: 609a str r2, [r3, #8]
}
8001fd4: bf00 nop
8001fd6: f507 7780 add.w r7, r7, #256 ; 0x100
8001fda: 46bd mov sp, r7
8001fdc: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8001fe0: 51eb851f .word 0x51eb851f
08001fe4 <memset>:
8001fe4: 4402 add r2, r0
8001fe6: 4603 mov r3, r0
8001fe8: 4293 cmp r3, r2
8001fea: d100 bne.n 8001fee <memset+0xa>
8001fec: 4770 bx lr
8001fee: f803 1b01 strb.w r1, [r3], #1
8001ff2: e7f9 b.n 8001fe8 <memset+0x4>
08001ff4 <__libc_init_array>:
8001ff4: b570 push {r4, r5, r6, lr}
8001ff6: 4d0d ldr r5, [pc, #52] ; (800202c <__libc_init_array+0x38>)
8001ff8: 4c0d ldr r4, [pc, #52] ; (8002030 <__libc_init_array+0x3c>)
8001ffa: 1b64 subs r4, r4, r5
8001ffc: 10a4 asrs r4, r4, #2
8001ffe: 2600 movs r6, #0
8002000: 42a6 cmp r6, r4
8002002: d109 bne.n 8002018 <__libc_init_array+0x24>
8002004: 4d0b ldr r5, [pc, #44] ; (8002034 <__libc_init_array+0x40>)
8002006: 4c0c ldr r4, [pc, #48] ; (8002038 <__libc_init_array+0x44>)
8002008: f000 f818 bl 800203c <_init>
800200c: 1b64 subs r4, r4, r5
800200e: 10a4 asrs r4, r4, #2
8002010: 2600 movs r6, #0
8002012: 42a6 cmp r6, r4
8002014: d105 bne.n 8002022 <__libc_init_array+0x2e>
8002016: bd70 pop {r4, r5, r6, pc}
8002018: f855 3b04 ldr.w r3, [r5], #4
800201c: 4798 blx r3
800201e: 3601 adds r6, #1
8002020: e7ee b.n 8002000 <__libc_init_array+0xc>
8002022: f855 3b04 ldr.w r3, [r5], #4
8002026: 4798 blx r3
8002028: 3601 adds r6, #1
800202a: e7f2 b.n 8002012 <__libc_init_array+0x1e>
800202c: 08002074 .word 0x08002074
8002030: 08002074 .word 0x08002074
8002034: 08002074 .word 0x08002074
8002038: 08002078 .word 0x08002078
0800203c <_init>:
800203c: b5f8 push {r3, r4, r5, r6, r7, lr}
800203e: bf00 nop
8002040: bcf8 pop {r3, r4, r5, r6, r7}
8002042: bc08 pop {r3}
8002044: 469e mov lr, r3
8002046: 4770 bx lr
08002048 <_fini>:
8002048: b5f8 push {r3, r4, r5, r6, r7, lr}
800204a: bf00 nop
800204c: bcf8 pop {r3, r4, r5, r6, r7}
800204e: bc08 pop {r3}
8002050: 469e mov lr, r3
8002052: 4770 bx lr