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stm32-fmt-code/access_control_stm32/Debug/access_control_stm32.list

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access_control_stm32.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000198 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00005488 080001a0 080001a0 000101a0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000090 08005628 08005628 00015628 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080056b8 080056b8 00020060 2**0
CONTENTS
4 .ARM 00000008 080056b8 080056b8 000156b8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080056c0 080056c0 00020060 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080056c0 080056c0 000156c0 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080056c4 080056c4 000156c4 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000060 20000000 080056c8 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00004bf4 20000060 08005728 00020060 2**2
ALLOC
10 ._user_heap_stack 00003004 20004c54 08005728 00024c54 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00020060 2**0
CONTENTS, READONLY
12 .comment 00000043 00000000 00000000 00020090 2**0
CONTENTS, READONLY
13 .debug_info 000175bc 00000000 00000000 000200d3 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_abbrev 0000318b 00000000 00000000 0003768f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00001390 00000000 00000000 0003a820 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_rnglists 00000f3f 00000000 00000000 0003bbb0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_macro 00003557 00000000 00000000 0003caef 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_line 000157dd 00000000 00000000 00040046 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_str 0009856e 00000000 00000000 00055823 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_frame 000055a0 00000000 00000000 000edd94 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000059 00000000 00000000 000f3334 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001a0 <__do_global_dtors_aux>:
80001a0: b510 push {r4, lr}
80001a2: 4c05 ldr r4, [pc, #20] ; (80001b8 <__do_global_dtors_aux+0x18>)
80001a4: 7823 ldrb r3, [r4, #0]
80001a6: b933 cbnz r3, 80001b6 <__do_global_dtors_aux+0x16>
80001a8: 4b04 ldr r3, [pc, #16] ; (80001bc <__do_global_dtors_aux+0x1c>)
80001aa: b113 cbz r3, 80001b2 <__do_global_dtors_aux+0x12>
80001ac: 4804 ldr r0, [pc, #16] ; (80001c0 <__do_global_dtors_aux+0x20>)
80001ae: f3af 8000 nop.w
80001b2: 2301 movs r3, #1
80001b4: 7023 strb r3, [r4, #0]
80001b6: bd10 pop {r4, pc}
80001b8: 20000060 .word 0x20000060
80001bc: 00000000 .word 0x00000000
80001c0: 08005610 .word 0x08005610
080001c4 <frame_dummy>:
80001c4: b508 push {r3, lr}
80001c6: 4b03 ldr r3, [pc, #12] ; (80001d4 <frame_dummy+0x10>)
80001c8: b11b cbz r3, 80001d2 <frame_dummy+0xe>
80001ca: 4903 ldr r1, [pc, #12] ; (80001d8 <frame_dummy+0x14>)
80001cc: 4803 ldr r0, [pc, #12] ; (80001dc <frame_dummy+0x18>)
80001ce: f3af 8000 nop.w
80001d2: bd08 pop {r3, pc}
80001d4: 00000000 .word 0x00000000
80001d8: 20000064 .word 0x20000064
80001dc: 08005610 .word 0x08005610
080001e0 <__aeabi_uldivmod>:
80001e0: b953 cbnz r3, 80001f8 <__aeabi_uldivmod+0x18>
80001e2: b94a cbnz r2, 80001f8 <__aeabi_uldivmod+0x18>
80001e4: 2900 cmp r1, #0
80001e6: bf08 it eq
80001e8: 2800 cmpeq r0, #0
80001ea: bf1c itt ne
80001ec: f04f 31ff movne.w r1, #4294967295
80001f0: f04f 30ff movne.w r0, #4294967295
80001f4: f000 b970 b.w 80004d8 <__aeabi_idiv0>
80001f8: f1ad 0c08 sub.w ip, sp, #8
80001fc: e96d ce04 strd ip, lr, [sp, #-16]!
8000200: f000 f806 bl 8000210 <__udivmoddi4>
8000204: f8dd e004 ldr.w lr, [sp, #4]
8000208: e9dd 2302 ldrd r2, r3, [sp, #8]
800020c: b004 add sp, #16
800020e: 4770 bx lr
08000210 <__udivmoddi4>:
8000210: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000214: 9e08 ldr r6, [sp, #32]
8000216: 460d mov r5, r1
8000218: 4604 mov r4, r0
800021a: 460f mov r7, r1
800021c: 2b00 cmp r3, #0
800021e: d14a bne.n 80002b6 <__udivmoddi4+0xa6>
8000220: 428a cmp r2, r1
8000222: 4694 mov ip, r2
8000224: d965 bls.n 80002f2 <__udivmoddi4+0xe2>
8000226: fab2 f382 clz r3, r2
800022a: b143 cbz r3, 800023e <__udivmoddi4+0x2e>
800022c: fa02 fc03 lsl.w ip, r2, r3
8000230: f1c3 0220 rsb r2, r3, #32
8000234: 409f lsls r7, r3
8000236: fa20 f202 lsr.w r2, r0, r2
800023a: 4317 orrs r7, r2
800023c: 409c lsls r4, r3
800023e: ea4f 4e1c mov.w lr, ip, lsr #16
8000242: fa1f f58c uxth.w r5, ip
8000246: fbb7 f1fe udiv r1, r7, lr
800024a: 0c22 lsrs r2, r4, #16
800024c: fb0e 7711 mls r7, lr, r1, r7
8000250: ea42 4207 orr.w r2, r2, r7, lsl #16
8000254: fb01 f005 mul.w r0, r1, r5
8000258: 4290 cmp r0, r2
800025a: d90a bls.n 8000272 <__udivmoddi4+0x62>
800025c: eb1c 0202 adds.w r2, ip, r2
8000260: f101 37ff add.w r7, r1, #4294967295
8000264: f080 811c bcs.w 80004a0 <__udivmoddi4+0x290>
8000268: 4290 cmp r0, r2
800026a: f240 8119 bls.w 80004a0 <__udivmoddi4+0x290>
800026e: 3902 subs r1, #2
8000270: 4462 add r2, ip
8000272: 1a12 subs r2, r2, r0
8000274: b2a4 uxth r4, r4
8000276: fbb2 f0fe udiv r0, r2, lr
800027a: fb0e 2210 mls r2, lr, r0, r2
800027e: ea44 4402 orr.w r4, r4, r2, lsl #16
8000282: fb00 f505 mul.w r5, r0, r5
8000286: 42a5 cmp r5, r4
8000288: d90a bls.n 80002a0 <__udivmoddi4+0x90>
800028a: eb1c 0404 adds.w r4, ip, r4
800028e: f100 32ff add.w r2, r0, #4294967295
8000292: f080 8107 bcs.w 80004a4 <__udivmoddi4+0x294>
8000296: 42a5 cmp r5, r4
8000298: f240 8104 bls.w 80004a4 <__udivmoddi4+0x294>
800029c: 4464 add r4, ip
800029e: 3802 subs r0, #2
80002a0: ea40 4001 orr.w r0, r0, r1, lsl #16
80002a4: 1b64 subs r4, r4, r5
80002a6: 2100 movs r1, #0
80002a8: b11e cbz r6, 80002b2 <__udivmoddi4+0xa2>
80002aa: 40dc lsrs r4, r3
80002ac: 2300 movs r3, #0
80002ae: e9c6 4300 strd r4, r3, [r6]
80002b2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002b6: 428b cmp r3, r1
80002b8: d908 bls.n 80002cc <__udivmoddi4+0xbc>
80002ba: 2e00 cmp r6, #0
80002bc: f000 80ed beq.w 800049a <__udivmoddi4+0x28a>
80002c0: 2100 movs r1, #0
80002c2: e9c6 0500 strd r0, r5, [r6]
80002c6: 4608 mov r0, r1
80002c8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002cc: fab3 f183 clz r1, r3
80002d0: 2900 cmp r1, #0
80002d2: d149 bne.n 8000368 <__udivmoddi4+0x158>
80002d4: 42ab cmp r3, r5
80002d6: d302 bcc.n 80002de <__udivmoddi4+0xce>
80002d8: 4282 cmp r2, r0
80002da: f200 80f8 bhi.w 80004ce <__udivmoddi4+0x2be>
80002de: 1a84 subs r4, r0, r2
80002e0: eb65 0203 sbc.w r2, r5, r3
80002e4: 2001 movs r0, #1
80002e6: 4617 mov r7, r2
80002e8: 2e00 cmp r6, #0
80002ea: d0e2 beq.n 80002b2 <__udivmoddi4+0xa2>
80002ec: e9c6 4700 strd r4, r7, [r6]
80002f0: e7df b.n 80002b2 <__udivmoddi4+0xa2>
80002f2: b902 cbnz r2, 80002f6 <__udivmoddi4+0xe6>
80002f4: deff udf #255 ; 0xff
80002f6: fab2 f382 clz r3, r2
80002fa: 2b00 cmp r3, #0
80002fc: f040 8090 bne.w 8000420 <__udivmoddi4+0x210>
8000300: 1a8a subs r2, r1, r2
8000302: ea4f 471c mov.w r7, ip, lsr #16
8000306: fa1f fe8c uxth.w lr, ip
800030a: 2101 movs r1, #1
800030c: fbb2 f5f7 udiv r5, r2, r7
8000310: fb07 2015 mls r0, r7, r5, r2
8000314: 0c22 lsrs r2, r4, #16
8000316: ea42 4200 orr.w r2, r2, r0, lsl #16
800031a: fb0e f005 mul.w r0, lr, r5
800031e: 4290 cmp r0, r2
8000320: d908 bls.n 8000334 <__udivmoddi4+0x124>
8000322: eb1c 0202 adds.w r2, ip, r2
8000326: f105 38ff add.w r8, r5, #4294967295
800032a: d202 bcs.n 8000332 <__udivmoddi4+0x122>
800032c: 4290 cmp r0, r2
800032e: f200 80cb bhi.w 80004c8 <__udivmoddi4+0x2b8>
8000332: 4645 mov r5, r8
8000334: 1a12 subs r2, r2, r0
8000336: b2a4 uxth r4, r4
8000338: fbb2 f0f7 udiv r0, r2, r7
800033c: fb07 2210 mls r2, r7, r0, r2
8000340: ea44 4402 orr.w r4, r4, r2, lsl #16
8000344: fb0e fe00 mul.w lr, lr, r0
8000348: 45a6 cmp lr, r4
800034a: d908 bls.n 800035e <__udivmoddi4+0x14e>
800034c: eb1c 0404 adds.w r4, ip, r4
8000350: f100 32ff add.w r2, r0, #4294967295
8000354: d202 bcs.n 800035c <__udivmoddi4+0x14c>
8000356: 45a6 cmp lr, r4
8000358: f200 80bb bhi.w 80004d2 <__udivmoddi4+0x2c2>
800035c: 4610 mov r0, r2
800035e: eba4 040e sub.w r4, r4, lr
8000362: ea40 4005 orr.w r0, r0, r5, lsl #16
8000366: e79f b.n 80002a8 <__udivmoddi4+0x98>
8000368: f1c1 0720 rsb r7, r1, #32
800036c: 408b lsls r3, r1
800036e: fa22 fc07 lsr.w ip, r2, r7
8000372: ea4c 0c03 orr.w ip, ip, r3
8000376: fa05 f401 lsl.w r4, r5, r1
800037a: fa20 f307 lsr.w r3, r0, r7
800037e: 40fd lsrs r5, r7
8000380: ea4f 491c mov.w r9, ip, lsr #16
8000384: 4323 orrs r3, r4
8000386: fbb5 f8f9 udiv r8, r5, r9
800038a: fa1f fe8c uxth.w lr, ip
800038e: fb09 5518 mls r5, r9, r8, r5
8000392: 0c1c lsrs r4, r3, #16
8000394: ea44 4405 orr.w r4, r4, r5, lsl #16
8000398: fb08 f50e mul.w r5, r8, lr
800039c: 42a5 cmp r5, r4
800039e: fa02 f201 lsl.w r2, r2, r1
80003a2: fa00 f001 lsl.w r0, r0, r1
80003a6: d90b bls.n 80003c0 <__udivmoddi4+0x1b0>
80003a8: eb1c 0404 adds.w r4, ip, r4
80003ac: f108 3aff add.w sl, r8, #4294967295
80003b0: f080 8088 bcs.w 80004c4 <__udivmoddi4+0x2b4>
80003b4: 42a5 cmp r5, r4
80003b6: f240 8085 bls.w 80004c4 <__udivmoddi4+0x2b4>
80003ba: f1a8 0802 sub.w r8, r8, #2
80003be: 4464 add r4, ip
80003c0: 1b64 subs r4, r4, r5
80003c2: b29d uxth r5, r3
80003c4: fbb4 f3f9 udiv r3, r4, r9
80003c8: fb09 4413 mls r4, r9, r3, r4
80003cc: ea45 4404 orr.w r4, r5, r4, lsl #16
80003d0: fb03 fe0e mul.w lr, r3, lr
80003d4: 45a6 cmp lr, r4
80003d6: d908 bls.n 80003ea <__udivmoddi4+0x1da>
80003d8: eb1c 0404 adds.w r4, ip, r4
80003dc: f103 35ff add.w r5, r3, #4294967295
80003e0: d26c bcs.n 80004bc <__udivmoddi4+0x2ac>
80003e2: 45a6 cmp lr, r4
80003e4: d96a bls.n 80004bc <__udivmoddi4+0x2ac>
80003e6: 3b02 subs r3, #2
80003e8: 4464 add r4, ip
80003ea: ea43 4308 orr.w r3, r3, r8, lsl #16
80003ee: fba3 9502 umull r9, r5, r3, r2
80003f2: eba4 040e sub.w r4, r4, lr
80003f6: 42ac cmp r4, r5
80003f8: 46c8 mov r8, r9
80003fa: 46ae mov lr, r5
80003fc: d356 bcc.n 80004ac <__udivmoddi4+0x29c>
80003fe: d053 beq.n 80004a8 <__udivmoddi4+0x298>
8000400: b156 cbz r6, 8000418 <__udivmoddi4+0x208>
8000402: ebb0 0208 subs.w r2, r0, r8
8000406: eb64 040e sbc.w r4, r4, lr
800040a: fa04 f707 lsl.w r7, r4, r7
800040e: 40ca lsrs r2, r1
8000410: 40cc lsrs r4, r1
8000412: 4317 orrs r7, r2
8000414: e9c6 7400 strd r7, r4, [r6]
8000418: 4618 mov r0, r3
800041a: 2100 movs r1, #0
800041c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000420: f1c3 0120 rsb r1, r3, #32
8000424: fa02 fc03 lsl.w ip, r2, r3
8000428: fa20 f201 lsr.w r2, r0, r1
800042c: fa25 f101 lsr.w r1, r5, r1
8000430: 409d lsls r5, r3
8000432: 432a orrs r2, r5
8000434: ea4f 471c mov.w r7, ip, lsr #16
8000438: fa1f fe8c uxth.w lr, ip
800043c: fbb1 f0f7 udiv r0, r1, r7
8000440: fb07 1510 mls r5, r7, r0, r1
8000444: 0c11 lsrs r1, r2, #16
8000446: ea41 4105 orr.w r1, r1, r5, lsl #16
800044a: fb00 f50e mul.w r5, r0, lr
800044e: 428d cmp r5, r1
8000450: fa04 f403 lsl.w r4, r4, r3
8000454: d908 bls.n 8000468 <__udivmoddi4+0x258>
8000456: eb1c 0101 adds.w r1, ip, r1
800045a: f100 38ff add.w r8, r0, #4294967295
800045e: d22f bcs.n 80004c0 <__udivmoddi4+0x2b0>
8000460: 428d cmp r5, r1
8000462: d92d bls.n 80004c0 <__udivmoddi4+0x2b0>
8000464: 3802 subs r0, #2
8000466: 4461 add r1, ip
8000468: 1b49 subs r1, r1, r5
800046a: b292 uxth r2, r2
800046c: fbb1 f5f7 udiv r5, r1, r7
8000470: fb07 1115 mls r1, r7, r5, r1
8000474: ea42 4201 orr.w r2, r2, r1, lsl #16
8000478: fb05 f10e mul.w r1, r5, lr
800047c: 4291 cmp r1, r2
800047e: d908 bls.n 8000492 <__udivmoddi4+0x282>
8000480: eb1c 0202 adds.w r2, ip, r2
8000484: f105 38ff add.w r8, r5, #4294967295
8000488: d216 bcs.n 80004b8 <__udivmoddi4+0x2a8>
800048a: 4291 cmp r1, r2
800048c: d914 bls.n 80004b8 <__udivmoddi4+0x2a8>
800048e: 3d02 subs r5, #2
8000490: 4462 add r2, ip
8000492: 1a52 subs r2, r2, r1
8000494: ea45 4100 orr.w r1, r5, r0, lsl #16
8000498: e738 b.n 800030c <__udivmoddi4+0xfc>
800049a: 4631 mov r1, r6
800049c: 4630 mov r0, r6
800049e: e708 b.n 80002b2 <__udivmoddi4+0xa2>
80004a0: 4639 mov r1, r7
80004a2: e6e6 b.n 8000272 <__udivmoddi4+0x62>
80004a4: 4610 mov r0, r2
80004a6: e6fb b.n 80002a0 <__udivmoddi4+0x90>
80004a8: 4548 cmp r0, r9
80004aa: d2a9 bcs.n 8000400 <__udivmoddi4+0x1f0>
80004ac: ebb9 0802 subs.w r8, r9, r2
80004b0: eb65 0e0c sbc.w lr, r5, ip
80004b4: 3b01 subs r3, #1
80004b6: e7a3 b.n 8000400 <__udivmoddi4+0x1f0>
80004b8: 4645 mov r5, r8
80004ba: e7ea b.n 8000492 <__udivmoddi4+0x282>
80004bc: 462b mov r3, r5
80004be: e794 b.n 80003ea <__udivmoddi4+0x1da>
80004c0: 4640 mov r0, r8
80004c2: e7d1 b.n 8000468 <__udivmoddi4+0x258>
80004c4: 46d0 mov r8, sl
80004c6: e77b b.n 80003c0 <__udivmoddi4+0x1b0>
80004c8: 3d02 subs r5, #2
80004ca: 4462 add r2, ip
80004cc: e732 b.n 8000334 <__udivmoddi4+0x124>
80004ce: 4608 mov r0, r1
80004d0: e70a b.n 80002e8 <__udivmoddi4+0xd8>
80004d2: 4464 add r4, ip
80004d4: 3802 subs r0, #2
80004d6: e742 b.n 800035e <__udivmoddi4+0x14e>
080004d8 <__aeabi_idiv0>:
80004d8: 4770 bx lr
80004da: bf00 nop
080004dc <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void) {
80004dc: b580 push {r7, lr}
80004de: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80004e0: f000 fb84 bl 8000bec <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80004e4: f000 f82c bl 8000540 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80004e8: f000 f8be bl 8000668 <MX_GPIO_Init>
MX_USART2_UART_Init();
80004ec: f000 f892 bl 8000614 <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
memset(uart_buffer, 0, 10);
80004f0: 220a movs r2, #10
80004f2: 2100 movs r1, #0
80004f4: 480b ldr r0, [pc, #44] ; (8000524 <main+0x48>)
80004f6: f004 ffa1 bl 800543c <memset>
/* USER CODE END 2 */
/* Init scheduler */
osKernelInitialize();
80004fa: f002 fa43 bl 8002984 <osKernelInitialize>
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* creation of mainTask */
mainTaskHandle = osThreadNew(StartMainTask, NULL, &mainTask_attributes);
80004fe: 4a0a ldr r2, [pc, #40] ; (8000528 <main+0x4c>)
8000500: 2100 movs r1, #0
8000502: 480a ldr r0, [pc, #40] ; (800052c <main+0x50>)
8000504: f002 fa88 bl 8002a18 <osThreadNew>
8000508: 4603 mov r3, r0
800050a: 4a09 ldr r2, [pc, #36] ; (8000530 <main+0x54>)
800050c: 6013 str r3, [r2, #0]
/* creation of doorHandler */
doorHandlerHandle = osThreadNew(startDoorHandleTask, NULL,
800050e: 4a09 ldr r2, [pc, #36] ; (8000534 <main+0x58>)
8000510: 2100 movs r1, #0
8000512: 4809 ldr r0, [pc, #36] ; (8000538 <main+0x5c>)
8000514: f002 fa80 bl 8002a18 <osThreadNew>
8000518: 4603 mov r3, r0
800051a: 4a08 ldr r2, [pc, #32] ; (800053c <main+0x60>)
800051c: 6013 str r3, [r2, #0]
/* USER CODE BEGIN RTOS_EVENTS */
/* add events, ... */
/* USER CODE END RTOS_EVENTS */
/* Start scheduler */
osKernelStart();
800051e: f002 fa55 bl 80029cc <osKernelStart>
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
8000522: e7fe b.n 8000522 <main+0x46>
8000524: 200000c8 .word 0x200000c8
8000528: 08005658 .word 0x08005658
800052c: 08000761 .word 0x08000761
8000530: 200000c0 .word 0x200000c0
8000534: 0800567c .word 0x0800567c
8000538: 08000839 .word 0x08000839
800053c: 200000c4 .word 0x200000c4
08000540 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void) {
8000540: b580 push {r7, lr}
8000542: b094 sub sp, #80 ; 0x50
8000544: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
8000546: f107 0320 add.w r3, r7, #32
800054a: 2230 movs r2, #48 ; 0x30
800054c: 2100 movs r1, #0
800054e: 4618 mov r0, r3
8000550: f004 ff74 bl 800543c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
8000554: f107 030c add.w r3, r7, #12
8000558: 2200 movs r2, #0
800055a: 601a str r2, [r3, #0]
800055c: 605a str r2, [r3, #4]
800055e: 609a str r2, [r3, #8]
8000560: 60da str r2, [r3, #12]
8000562: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000564: 2300 movs r3, #0
8000566: 60bb str r3, [r7, #8]
8000568: 4b28 ldr r3, [pc, #160] ; (800060c <SystemClock_Config+0xcc>)
800056a: 6c1b ldr r3, [r3, #64] ; 0x40
800056c: 4a27 ldr r2, [pc, #156] ; (800060c <SystemClock_Config+0xcc>)
800056e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000572: 6413 str r3, [r2, #64] ; 0x40
8000574: 4b25 ldr r3, [pc, #148] ; (800060c <SystemClock_Config+0xcc>)
8000576: 6c1b ldr r3, [r3, #64] ; 0x40
8000578: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800057c: 60bb str r3, [r7, #8]
800057e: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000580: 2300 movs r3, #0
8000582: 607b str r3, [r7, #4]
8000584: 4b22 ldr r3, [pc, #136] ; (8000610 <SystemClock_Config+0xd0>)
8000586: 681b ldr r3, [r3, #0]
8000588: 4a21 ldr r2, [pc, #132] ; (8000610 <SystemClock_Config+0xd0>)
800058a: f443 4340 orr.w r3, r3, #49152 ; 0xc000
800058e: 6013 str r3, [r2, #0]
8000590: 4b1f ldr r3, [pc, #124] ; (8000610 <SystemClock_Config+0xd0>)
8000592: 681b ldr r3, [r3, #0]
8000594: f403 4340 and.w r3, r3, #49152 ; 0xc000
8000598: 607b str r3, [r7, #4]
800059a: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800059c: 2302 movs r3, #2
800059e: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80005a0: 2301 movs r3, #1
80005a2: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80005a4: 2310 movs r3, #16
80005a6: 633b str r3, [r7, #48] ; 0x30
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80005a8: 2302 movs r3, #2
80005aa: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
80005ac: 2300 movs r3, #0
80005ae: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLM = 16;
80005b0: 2310 movs r3, #16
80005b2: 643b str r3, [r7, #64] ; 0x40
RCC_OscInitStruct.PLL.PLLN = 336;
80005b4: f44f 73a8 mov.w r3, #336 ; 0x150
80005b8: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
80005ba: 2304 movs r3, #4
80005bc: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLQ = 4;
80005be: 2304 movs r3, #4
80005c0: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
80005c2: f107 0320 add.w r3, r7, #32
80005c6: 4618 mov r0, r3
80005c8: f000 fdea bl 80011a0 <HAL_RCC_OscConfig>
80005cc: 4603 mov r3, r0
80005ce: 2b00 cmp r3, #0
80005d0: d001 beq.n 80005d6 <SystemClock_Config+0x96>
Error_Handler();
80005d2: f000 f9c3 bl 800095c <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
80005d6: 230f movs r3, #15
80005d8: 60fb str r3, [r7, #12]
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80005da: 2302 movs r3, #2
80005dc: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80005de: 2300 movs r3, #0
80005e0: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
80005e2: f44f 5380 mov.w r3, #4096 ; 0x1000
80005e6: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80005e8: 2300 movs r3, #0
80005ea: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
80005ec: f107 030c add.w r3, r7, #12
80005f0: 2102 movs r1, #2
80005f2: 4618 mov r0, r3
80005f4: f001 f84c bl 8001690 <HAL_RCC_ClockConfig>
80005f8: 4603 mov r3, r0
80005fa: 2b00 cmp r3, #0
80005fc: d001 beq.n 8000602 <SystemClock_Config+0xc2>
Error_Handler();
80005fe: f000 f9ad bl 800095c <Error_Handler>
}
}
8000602: bf00 nop
8000604: 3750 adds r7, #80 ; 0x50
8000606: 46bd mov sp, r7
8000608: bd80 pop {r7, pc}
800060a: bf00 nop
800060c: 40023800 .word 0x40023800
8000610: 40007000 .word 0x40007000
08000614 <MX_USART2_UART_Init>:
/**
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void) {
8000614: b580 push {r7, lr}
8000616: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
8000618: 4b11 ldr r3, [pc, #68] ; (8000660 <MX_USART2_UART_Init+0x4c>)
800061a: 4a12 ldr r2, [pc, #72] ; (8000664 <MX_USART2_UART_Init+0x50>)
800061c: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
800061e: 4b10 ldr r3, [pc, #64] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000620: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000624: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
8000626: 4b0e ldr r3, [pc, #56] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000628: 2200 movs r2, #0
800062a: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
800062c: 4b0c ldr r3, [pc, #48] ; (8000660 <MX_USART2_UART_Init+0x4c>)
800062e: 2200 movs r2, #0
8000630: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8000632: 4b0b ldr r3, [pc, #44] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000634: 2200 movs r2, #0
8000636: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
8000638: 4b09 ldr r3, [pc, #36] ; (8000660 <MX_USART2_UART_Init+0x4c>)
800063a: 220c movs r2, #12
800063c: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800063e: 4b08 ldr r3, [pc, #32] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000640: 2200 movs r2, #0
8000642: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
8000644: 4b06 ldr r3, [pc, #24] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000646: 2200 movs r2, #0
8000648: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK) {
800064a: 4805 ldr r0, [pc, #20] ; (8000660 <MX_USART2_UART_Init+0x4c>)
800064c: f001 fcf2 bl 8002034 <HAL_UART_Init>
8000650: 4603 mov r3, r0
8000652: 2b00 cmp r3, #0
8000654: d001 beq.n 800065a <MX_USART2_UART_Init+0x46>
Error_Handler();
8000656: f000 f981 bl 800095c <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
800065a: bf00 nop
800065c: bd80 pop {r7, pc}
800065e: bf00 nop
8000660: 2000007c .word 0x2000007c
8000664: 40004400 .word 0x40004400
08000668 <MX_GPIO_Init>:
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void) {
8000668: b580 push {r7, lr}
800066a: b08a sub sp, #40 ; 0x28
800066c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = { 0 };
800066e: f107 0314 add.w r3, r7, #20
8000672: 2200 movs r2, #0
8000674: 601a str r2, [r3, #0]
8000676: 605a str r2, [r3, #4]
8000678: 609a str r2, [r3, #8]
800067a: 60da str r2, [r3, #12]
800067c: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
800067e: 2300 movs r3, #0
8000680: 613b str r3, [r7, #16]
8000682: 4b34 ldr r3, [pc, #208] ; (8000754 <MX_GPIO_Init+0xec>)
8000684: 6b1b ldr r3, [r3, #48] ; 0x30
8000686: 4a33 ldr r2, [pc, #204] ; (8000754 <MX_GPIO_Init+0xec>)
8000688: f043 0304 orr.w r3, r3, #4
800068c: 6313 str r3, [r2, #48] ; 0x30
800068e: 4b31 ldr r3, [pc, #196] ; (8000754 <MX_GPIO_Init+0xec>)
8000690: 6b1b ldr r3, [r3, #48] ; 0x30
8000692: f003 0304 and.w r3, r3, #4
8000696: 613b str r3, [r7, #16]
8000698: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
800069a: 2300 movs r3, #0
800069c: 60fb str r3, [r7, #12]
800069e: 4b2d ldr r3, [pc, #180] ; (8000754 <MX_GPIO_Init+0xec>)
80006a0: 6b1b ldr r3, [r3, #48] ; 0x30
80006a2: 4a2c ldr r2, [pc, #176] ; (8000754 <MX_GPIO_Init+0xec>)
80006a4: f043 0380 orr.w r3, r3, #128 ; 0x80
80006a8: 6313 str r3, [r2, #48] ; 0x30
80006aa: 4b2a ldr r3, [pc, #168] ; (8000754 <MX_GPIO_Init+0xec>)
80006ac: 6b1b ldr r3, [r3, #48] ; 0x30
80006ae: f003 0380 and.w r3, r3, #128 ; 0x80
80006b2: 60fb str r3, [r7, #12]
80006b4: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80006b6: 2300 movs r3, #0
80006b8: 60bb str r3, [r7, #8]
80006ba: 4b26 ldr r3, [pc, #152] ; (8000754 <MX_GPIO_Init+0xec>)
80006bc: 6b1b ldr r3, [r3, #48] ; 0x30
80006be: 4a25 ldr r2, [pc, #148] ; (8000754 <MX_GPIO_Init+0xec>)
80006c0: f043 0301 orr.w r3, r3, #1
80006c4: 6313 str r3, [r2, #48] ; 0x30
80006c6: 4b23 ldr r3, [pc, #140] ; (8000754 <MX_GPIO_Init+0xec>)
80006c8: 6b1b ldr r3, [r3, #48] ; 0x30
80006ca: f003 0301 and.w r3, r3, #1
80006ce: 60bb str r3, [r7, #8]
80006d0: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
80006d2: 2300 movs r3, #0
80006d4: 607b str r3, [r7, #4]
80006d6: 4b1f ldr r3, [pc, #124] ; (8000754 <MX_GPIO_Init+0xec>)
80006d8: 6b1b ldr r3, [r3, #48] ; 0x30
80006da: 4a1e ldr r2, [pc, #120] ; (8000754 <MX_GPIO_Init+0xec>)
80006dc: f043 0302 orr.w r3, r3, #2
80006e0: 6313 str r3, [r2, #48] ; 0x30
80006e2: 4b1c ldr r3, [pc, #112] ; (8000754 <MX_GPIO_Init+0xec>)
80006e4: 6b1b ldr r3, [r3, #48] ; 0x30
80006e6: f003 0302 and.w r3, r3, #2
80006ea: 607b str r3, [r7, #4]
80006ec: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, LD2_Pin | Door_Lock_Pin, GPIO_PIN_RESET);
80006ee: 2200 movs r2, #0
80006f0: f44f 7108 mov.w r1, #544 ; 0x220
80006f4: 4818 ldr r0, [pc, #96] ; (8000758 <MX_GPIO_Init+0xf0>)
80006f6: f000 fd39 bl 800116c <HAL_GPIO_WritePin>
/*Configure GPIO pin : B1_Pin */
GPIO_InitStruct.Pin = B1_Pin;
80006fa: f44f 5300 mov.w r3, #8192 ; 0x2000
80006fe: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
8000700: f44f 1304 mov.w r3, #2162688 ; 0x210000
8000704: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000706: 2300 movs r3, #0
8000708: 61fb str r3, [r7, #28]
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
800070a: f107 0314 add.w r3, r7, #20
800070e: 4619 mov r1, r3
8000710: 4812 ldr r0, [pc, #72] ; (800075c <MX_GPIO_Init+0xf4>)
8000712: f000 fb8f bl 8000e34 <HAL_GPIO_Init>
/*Configure GPIO pins : LD2_Pin Door_Lock_Pin */
GPIO_InitStruct.Pin = LD2_Pin | Door_Lock_Pin;
8000716: f44f 7308 mov.w r3, #544 ; 0x220
800071a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800071c: 2301 movs r3, #1
800071e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000720: 2300 movs r3, #0
8000722: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000724: 2300 movs r3, #0
8000726: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000728: f107 0314 add.w r3, r7, #20
800072c: 4619 mov r1, r3
800072e: 480a ldr r0, [pc, #40] ; (8000758 <MX_GPIO_Init+0xf0>)
8000730: f000 fb80 bl 8000e34 <HAL_GPIO_Init>
/*Configure GPIO pin : Door_Sensor_Pin */
GPIO_InitStruct.Pin = Door_Sensor_Pin;
8000734: 2380 movs r3, #128 ; 0x80
8000736: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000738: 2300 movs r3, #0
800073a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
800073c: 2301 movs r3, #1
800073e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(Door_Sensor_GPIO_Port, &GPIO_InitStruct);
8000740: f107 0314 add.w r3, r7, #20
8000744: 4619 mov r1, r3
8000746: 4804 ldr r0, [pc, #16] ; (8000758 <MX_GPIO_Init+0xf0>)
8000748: f000 fb74 bl 8000e34 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
800074c: bf00 nop
800074e: 3728 adds r7, #40 ; 0x28
8000750: 46bd mov sp, r7
8000752: bd80 pop {r7, pc}
8000754: 40023800 .word 0x40023800
8000758: 40020000 .word 0x40020000
800075c: 40020800 .word 0x40020800
08000760 <StartMainTask>:
* @brief Function implementing the mainTask thread.
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_StartMainTask */
void StartMainTask(void *argument) {
8000760: b580 push {r7, lr}
8000762: b084 sub sp, #16
8000764: af00 add r7, sp, #0
8000766: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 5 */
memset(uart_buffer, 0, 10);
8000768: 220a movs r2, #10
800076a: 2100 movs r1, #0
800076c: 482c ldr r0, [pc, #176] ; (8000820 <StartMainTask+0xc0>)
800076e: f004 fe65 bl 800543c <memset>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 250)
8000772: 4b2c ldr r3, [pc, #176] ; (8000824 <StartMainTask+0xc4>)
8000774: 781b ldrb r3, [r3, #0]
8000776: 461a mov r2, r3
8000778: 4b29 ldr r3, [pc, #164] ; (8000820 <StartMainTask+0xc0>)
800077a: 18d1 adds r1, r2, r3
800077c: 23fa movs r3, #250 ; 0xfa
800077e: 2201 movs r2, #1
8000780: 4829 ldr r0, [pc, #164] ; (8000828 <StartMainTask+0xc8>)
8000782: f001 fd36 bl 80021f2 <HAL_UART_Receive>
8000786: 4603 mov r3, r0
8000788: 2b00 cmp r3, #0
800078a: d145 bne.n 8000818 <StartMainTask+0xb8>
== HAL_OK) {
uart_index++;
800078c: 4b25 ldr r3, [pc, #148] ; (8000824 <StartMainTask+0xc4>)
800078e: 781b ldrb r3, [r3, #0]
8000790: 3301 adds r3, #1
8000792: b2da uxtb r2, r3
8000794: 4b23 ldr r3, [pc, #140] ; (8000824 <StartMainTask+0xc4>)
8000796: 701a strb r2, [r3, #0]
if (uart_buffer[uart_index - 1] == 0xFF) {
8000798: 4b22 ldr r3, [pc, #136] ; (8000824 <StartMainTask+0xc4>)
800079a: 781b ldrb r3, [r3, #0]
800079c: 3b01 subs r3, #1
800079e: 4a20 ldr r2, [pc, #128] ; (8000820 <StartMainTask+0xc0>)
80007a0: 5cd3 ldrb r3, [r2, r3]
80007a2: 2bff cmp r3, #255 ; 0xff
80007a4: d138 bne.n 8000818 <StartMainTask+0xb8>
if (uart_index > 1) {
80007a6: 4b1f ldr r3, [pc, #124] ; (8000824 <StartMainTask+0xc4>)
80007a8: 781b ldrb r3, [r3, #0]
80007aa: 2b01 cmp r3, #1
80007ac: d92c bls.n 8000808 <StartMainTask+0xa8>
//Command Internal LED
if (uart_buffer[0] == 0x00) {
80007ae: 4b1c ldr r3, [pc, #112] ; (8000820 <StartMainTask+0xc0>)
80007b0: 781b ldrb r3, [r3, #0]
80007b2: 2b00 cmp r3, #0
80007b4: d107 bne.n 80007c6 <StartMainTask+0x66>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, uart_buffer[1]);
80007b6: 4b1a ldr r3, [pc, #104] ; (8000820 <StartMainTask+0xc0>)
80007b8: 785b ldrb r3, [r3, #1]
80007ba: 461a mov r2, r3
80007bc: 2120 movs r1, #32
80007be: 481b ldr r0, [pc, #108] ; (800082c <StartMainTask+0xcc>)
80007c0: f000 fcd4 bl 800116c <HAL_GPIO_WritePin>
80007c4: e020 b.n 8000808 <StartMainTask+0xa8>
}
// Get Current Door State
else if (uart_buffer[0] == 0x01) {
80007c6: 4b16 ldr r3, [pc, #88] ; (8000820 <StartMainTask+0xc0>)
80007c8: 781b ldrb r3, [r3, #0]
80007ca: 2b01 cmp r3, #1
80007cc: d10f bne.n 80007ee <StartMainTask+0x8e>
uint8_t payload[3] = { 0x01, door_state, 0xFF };
80007ce: 2301 movs r3, #1
80007d0: 733b strb r3, [r7, #12]
80007d2: 4b17 ldr r3, [pc, #92] ; (8000830 <StartMainTask+0xd0>)
80007d4: 781b ldrb r3, [r3, #0]
80007d6: 737b strb r3, [r7, #13]
80007d8: 23ff movs r3, #255 ; 0xff
80007da: 73bb strb r3, [r7, #14]
HAL_UART_Transmit(&huart2, payload, 3, 1500);
80007dc: f107 010c add.w r1, r7, #12
80007e0: f240 53dc movw r3, #1500 ; 0x5dc
80007e4: 2203 movs r2, #3
80007e6: 4810 ldr r0, [pc, #64] ; (8000828 <StartMainTask+0xc8>)
80007e8: f001 fc71 bl 80020ce <HAL_UART_Transmit>
80007ec: e00c b.n 8000808 <StartMainTask+0xa8>
}
//
else if (uart_buffer[0] == 0x02) {
80007ee: 4b0c ldr r3, [pc, #48] ; (8000820 <StartMainTask+0xc0>)
80007f0: 781b ldrb r3, [r3, #0]
80007f2: 2b02 cmp r3, #2
80007f4: d108 bne.n 8000808 <StartMainTask+0xa8>
door_lock_state_command = uart_buffer[1];
80007f6: 4b0a ldr r3, [pc, #40] ; (8000820 <StartMainTask+0xc0>)
80007f8: 785b ldrb r3, [r3, #1]
80007fa: 2b00 cmp r3, #0
80007fc: bf14 ite ne
80007fe: 2301 movne r3, #1
8000800: 2300 moveq r3, #0
8000802: b2da uxtb r2, r3
8000804: 4b0b ldr r3, [pc, #44] ; (8000834 <StartMainTask+0xd4>)
8000806: 701a strb r2, [r3, #0]
}
}
uart_index = 0;
8000808: 4b06 ldr r3, [pc, #24] ; (8000824 <StartMainTask+0xc4>)
800080a: 2200 movs r2, #0
800080c: 701a strb r2, [r3, #0]
memset(uart_buffer, 0, 10);
800080e: 220a movs r2, #10
8000810: 2100 movs r1, #0
8000812: 4803 ldr r0, [pc, #12] ; (8000820 <StartMainTask+0xc0>)
8000814: f004 fe12 bl 800543c <memset>
}
}
vTaskDelay(1);
8000818: 2001 movs r0, #1
800081a: f003 f91b bl 8003a54 <vTaskDelay>
if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 250)
800081e: e7a8 b.n 8000772 <StartMainTask+0x12>
8000820: 200000c8 .word 0x200000c8
8000824: 200000d2 .word 0x200000d2
8000828: 2000007c .word 0x2000007c
800082c: 40020000 .word 0x40020000
8000830: 200000d8 .word 0x200000d8
8000834: 200000da .word 0x200000da
08000838 <startDoorHandleTask>:
* @brief Function implementing the doorHandler thread.
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_startDoorHandleTask */
void startDoorHandleTask(void *argument) {
8000838: b580 push {r7, lr}
800083a: b082 sub sp, #8
800083c: af00 add r7, sp, #0
800083e: 6078 str r0, [r7, #4]
/* USER CODE BEGIN startDoorHandleTask */
/* Infinite loop */
for (;;) {
door_state = HAL_GPIO_ReadPin(DOOR_SENSOR_BANK, DOOR_SENSOR_PIN);
8000840: 2180 movs r1, #128 ; 0x80
8000842: 4835 ldr r0, [pc, #212] ; (8000918 <startDoorHandleTask+0xe0>)
8000844: f000 fc7a bl 800113c <HAL_GPIO_ReadPin>
8000848: 4603 mov r3, r0
800084a: 2b00 cmp r3, #0
800084c: bf14 ite ne
800084e: 2301 movne r3, #1
8000850: 2300 moveq r3, #0
8000852: b2da uxtb r2, r3
8000854: 4b31 ldr r3, [pc, #196] ; (800091c <startDoorHandleTask+0xe4>)
8000856: 701a strb r2, [r3, #0]
if (door_lock_state != door_lock_state_command) {
8000858: 4b31 ldr r3, [pc, #196] ; (8000920 <startDoorHandleTask+0xe8>)
800085a: 781a ldrb r2, [r3, #0]
800085c: 4b31 ldr r3, [pc, #196] ; (8000924 <startDoorHandleTask+0xec>)
800085e: 781b ldrb r3, [r3, #0]
8000860: 429a cmp r2, r3
8000862: d055 beq.n 8000910 <startDoorHandleTask+0xd8>
if (door_lock_state_command == DOOR_LOCK_LOCKED) {
8000864: 4b2f ldr r3, [pc, #188] ; (8000924 <startDoorHandleTask+0xec>)
8000866: 781b ldrb r3, [r3, #0]
8000868: 2b00 cmp r3, #0
800086a: d041 beq.n 80008f0 <startDoorHandleTask+0xb8>
if (door_state == DOOR_STATE_CLOSED) {
800086c: 4b2b ldr r3, [pc, #172] ; (800091c <startDoorHandleTask+0xe4>)
800086e: 781b ldrb r3, [r3, #0]
8000870: 2b00 cmp r3, #0
8000872: d009 beq.n 8000888 <startDoorHandleTask+0x50>
HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, 1);
8000874: 2201 movs r2, #1
8000876: 2100 movs r1, #0
8000878: f44f 7000 mov.w r0, #512 ; 0x200
800087c: f000 fc76 bl 800116c <HAL_GPIO_WritePin>
door_lock_state = DOOR_LOCK_LOCKED;
8000880: 4b27 ldr r3, [pc, #156] ; (8000920 <startDoorHandleTask+0xe8>)
8000882: 2201 movs r2, #1
8000884: 701a strb r2, [r3, #0]
8000886: e043 b.n 8000910 <startDoorHandleTask+0xd8>
} else {
if (!door_lock_waiting) {
8000888: 4b27 ldr r3, [pc, #156] ; (8000928 <startDoorHandleTask+0xf0>)
800088a: 781b ldrb r3, [r3, #0]
800088c: f083 0301 eor.w r3, r3, #1
8000890: b2db uxtb r3, r3
8000892: 2b00 cmp r3, #0
8000894: d008 beq.n 80008a8 <startDoorHandleTask+0x70>
door_lock_command_time = HAL_GetTick();
8000896: f000 f9df bl 8000c58 <HAL_GetTick>
800089a: 4603 mov r3, r0
800089c: 4a23 ldr r2, [pc, #140] ; (800092c <startDoorHandleTask+0xf4>)
800089e: 6013 str r3, [r2, #0]
door_lock_waiting = true;
80008a0: 4b21 ldr r3, [pc, #132] ; (8000928 <startDoorHandleTask+0xf0>)
80008a2: 2201 movs r2, #1
80008a4: 701a strb r2, [r3, #0]
80008a6: e033 b.n 8000910 <startDoorHandleTask+0xd8>
} else {
if (door_state == DOOR_STATE_OPEN) {
80008a8: 4b1c ldr r3, [pc, #112] ; (800091c <startDoorHandleTask+0xe4>)
80008aa: 781b ldrb r3, [r3, #0]
80008ac: f083 0301 eor.w r3, r3, #1
80008b0: b2db uxtb r3, r3
80008b2: 2b00 cmp r3, #0
80008b4: d012 beq.n 80008dc <startDoorHandleTask+0xa4>
if (HAL_GetTick()
80008b6: f000 f9cf bl 8000c58 <HAL_GetTick>
80008ba: 4602 mov r2, r0
- door_lock_command_time>DOOR_ERROR_ALARM_DELAY) {
80008bc: 4b1b ldr r3, [pc, #108] ; (800092c <startDoorHandleTask+0xf4>)
80008be: 681b ldr r3, [r3, #0]
80008c0: 1ad3 subs r3, r2, r3
if (HAL_GetTick()
80008c2: f242 7210 movw r2, #10000 ; 0x2710
80008c6: 4293 cmp r3, r2
80008c8: d922 bls.n 8000910 <startDoorHandleTask+0xd8>
alarm_active = true;
80008ca: 4b19 ldr r3, [pc, #100] ; (8000930 <startDoorHandleTask+0xf8>)
80008cc: 2201 movs r2, #1
80008ce: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(ALARM_BANK, ALARM_PIN, 1);
80008d0: 2201 movs r2, #1
80008d2: 2101 movs r1, #1
80008d4: 4817 ldr r0, [pc, #92] ; (8000934 <startDoorHandleTask+0xfc>)
80008d6: f000 fc49 bl 800116c <HAL_GPIO_WritePin>
80008da: e019 b.n 8000910 <startDoorHandleTask+0xd8>
}
} else {
HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, 1);
80008dc: 2201 movs r2, #1
80008de: 2100 movs r1, #0
80008e0: f44f 7000 mov.w r0, #512 ; 0x200
80008e4: f000 fc42 bl 800116c <HAL_GPIO_WritePin>
door_lock_state = DOOR_LOCK_LOCKED;
80008e8: 4b0d ldr r3, [pc, #52] ; (8000920 <startDoorHandleTask+0xe8>)
80008ea: 2201 movs r2, #1
80008ec: 701a strb r2, [r3, #0]
80008ee: e00f b.n 8000910 <startDoorHandleTask+0xd8>
}
}
}
} else if (door_lock_state_command == DOOR_LOCK_UNLOCKED) {
80008f0: 4b0c ldr r3, [pc, #48] ; (8000924 <startDoorHandleTask+0xec>)
80008f2: 781b ldrb r3, [r3, #0]
80008f4: f083 0301 eor.w r3, r3, #1
80008f8: b2db uxtb r3, r3
80008fa: 2b00 cmp r3, #0
80008fc: d008 beq.n 8000910 <startDoorHandleTask+0xd8>
HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, 0);
80008fe: 2200 movs r2, #0
8000900: 2100 movs r1, #0
8000902: f44f 7000 mov.w r0, #512 ; 0x200
8000906: f000 fc31 bl 800116c <HAL_GPIO_WritePin>
door_lock_state = DOOR_LOCK_UNLOCKED;
800090a: 4b05 ldr r3, [pc, #20] ; (8000920 <startDoorHandleTask+0xe8>)
800090c: 2200 movs r2, #0
800090e: 701a strb r2, [r3, #0]
}
}
//HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, uart_buffer[1]);
vTaskDelay(100);
8000910: 2064 movs r0, #100 ; 0x64
8000912: f003 f89f bl 8003a54 <vTaskDelay>
door_state = HAL_GPIO_ReadPin(DOOR_SENSOR_BANK, DOOR_SENSOR_PIN);
8000916: e793 b.n 8000840 <startDoorHandleTask+0x8>
8000918: 40020000 .word 0x40020000
800091c: 200000d8 .word 0x200000d8
8000920: 200000d9 .word 0x200000d9
8000924: 200000da .word 0x200000da
8000928: 200000db .word 0x200000db
800092c: 200000d4 .word 0x200000d4
8000930: 200000dc .word 0x200000dc
8000934: 40020800 .word 0x40020800
08000938 <HAL_TIM_PeriodElapsedCallback>:
* HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) {
8000938: b580 push {r7, lr}
800093a: b082 sub sp, #8
800093c: af00 add r7, sp, #0
800093e: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM1) {
8000940: 687b ldr r3, [r7, #4]
8000942: 681b ldr r3, [r3, #0]
8000944: 4a04 ldr r2, [pc, #16] ; (8000958 <HAL_TIM_PeriodElapsedCallback+0x20>)
8000946: 4293 cmp r3, r2
8000948: d101 bne.n 800094e <HAL_TIM_PeriodElapsedCallback+0x16>
HAL_IncTick();
800094a: f000 f971 bl 8000c30 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
800094e: bf00 nop
8000950: 3708 adds r7, #8
8000952: 46bd mov sp, r7
8000954: bd80 pop {r7, pc}
8000956: bf00 nop
8000958: 40010000 .word 0x40010000
0800095c <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void) {
800095c: b480 push {r7}
800095e: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000960: b672 cpsid i
}
8000962: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1) {
8000964: e7fe b.n 8000964 <Error_Handler+0x8>
...
08000968 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000968: b580 push {r7, lr}
800096a: b082 sub sp, #8
800096c: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800096e: 2300 movs r3, #0
8000970: 607b str r3, [r7, #4]
8000972: 4b12 ldr r3, [pc, #72] ; (80009bc <HAL_MspInit+0x54>)
8000974: 6c5b ldr r3, [r3, #68] ; 0x44
8000976: 4a11 ldr r2, [pc, #68] ; (80009bc <HAL_MspInit+0x54>)
8000978: f443 4380 orr.w r3, r3, #16384 ; 0x4000
800097c: 6453 str r3, [r2, #68] ; 0x44
800097e: 4b0f ldr r3, [pc, #60] ; (80009bc <HAL_MspInit+0x54>)
8000980: 6c5b ldr r3, [r3, #68] ; 0x44
8000982: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000986: 607b str r3, [r7, #4]
8000988: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
800098a: 2300 movs r3, #0
800098c: 603b str r3, [r7, #0]
800098e: 4b0b ldr r3, [pc, #44] ; (80009bc <HAL_MspInit+0x54>)
8000990: 6c1b ldr r3, [r3, #64] ; 0x40
8000992: 4a0a ldr r2, [pc, #40] ; (80009bc <HAL_MspInit+0x54>)
8000994: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000998: 6413 str r3, [r2, #64] ; 0x40
800099a: 4b08 ldr r3, [pc, #32] ; (80009bc <HAL_MspInit+0x54>)
800099c: 6c1b ldr r3, [r3, #64] ; 0x40
800099e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80009a2: 603b str r3, [r7, #0]
80009a4: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
80009a6: 2200 movs r2, #0
80009a8: 210f movs r1, #15
80009aa: f06f 0001 mvn.w r0, #1
80009ae: f000 fa17 bl 8000de0 <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80009b2: bf00 nop
80009b4: 3708 adds r7, #8
80009b6: 46bd mov sp, r7
80009b8: bd80 pop {r7, pc}
80009ba: bf00 nop
80009bc: 40023800 .word 0x40023800
080009c0 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
80009c0: b580 push {r7, lr}
80009c2: b08a sub sp, #40 ; 0x28
80009c4: af00 add r7, sp, #0
80009c6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80009c8: f107 0314 add.w r3, r7, #20
80009cc: 2200 movs r2, #0
80009ce: 601a str r2, [r3, #0]
80009d0: 605a str r2, [r3, #4]
80009d2: 609a str r2, [r3, #8]
80009d4: 60da str r2, [r3, #12]
80009d6: 611a str r2, [r3, #16]
if(huart->Instance==USART2)
80009d8: 687b ldr r3, [r7, #4]
80009da: 681b ldr r3, [r3, #0]
80009dc: 4a19 ldr r2, [pc, #100] ; (8000a44 <HAL_UART_MspInit+0x84>)
80009de: 4293 cmp r3, r2
80009e0: d12b bne.n 8000a3a <HAL_UART_MspInit+0x7a>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
80009e2: 2300 movs r3, #0
80009e4: 613b str r3, [r7, #16]
80009e6: 4b18 ldr r3, [pc, #96] ; (8000a48 <HAL_UART_MspInit+0x88>)
80009e8: 6c1b ldr r3, [r3, #64] ; 0x40
80009ea: 4a17 ldr r2, [pc, #92] ; (8000a48 <HAL_UART_MspInit+0x88>)
80009ec: f443 3300 orr.w r3, r3, #131072 ; 0x20000
80009f0: 6413 str r3, [r2, #64] ; 0x40
80009f2: 4b15 ldr r3, [pc, #84] ; (8000a48 <HAL_UART_MspInit+0x88>)
80009f4: 6c1b ldr r3, [r3, #64] ; 0x40
80009f6: f403 3300 and.w r3, r3, #131072 ; 0x20000
80009fa: 613b str r3, [r7, #16]
80009fc: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
80009fe: 2300 movs r3, #0
8000a00: 60fb str r3, [r7, #12]
8000a02: 4b11 ldr r3, [pc, #68] ; (8000a48 <HAL_UART_MspInit+0x88>)
8000a04: 6b1b ldr r3, [r3, #48] ; 0x30
8000a06: 4a10 ldr r2, [pc, #64] ; (8000a48 <HAL_UART_MspInit+0x88>)
8000a08: f043 0301 orr.w r3, r3, #1
8000a0c: 6313 str r3, [r2, #48] ; 0x30
8000a0e: 4b0e ldr r3, [pc, #56] ; (8000a48 <HAL_UART_MspInit+0x88>)
8000a10: 6b1b ldr r3, [r3, #48] ; 0x30
8000a12: f003 0301 and.w r3, r3, #1
8000a16: 60fb str r3, [r7, #12]
8000a18: 68fb ldr r3, [r7, #12]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
8000a1a: 230c movs r3, #12
8000a1c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a1e: 2302 movs r3, #2
8000a20: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a22: 2300 movs r3, #0
8000a24: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a26: 2303 movs r3, #3
8000a28: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8000a2a: 2307 movs r3, #7
8000a2c: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a2e: f107 0314 add.w r3, r7, #20
8000a32: 4619 mov r1, r3
8000a34: 4805 ldr r0, [pc, #20] ; (8000a4c <HAL_UART_MspInit+0x8c>)
8000a36: f000 f9fd bl 8000e34 <HAL_GPIO_Init>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
8000a3a: bf00 nop
8000a3c: 3728 adds r7, #40 ; 0x28
8000a3e: 46bd mov sp, r7
8000a40: bd80 pop {r7, pc}
8000a42: bf00 nop
8000a44: 40004400 .word 0x40004400
8000a48: 40023800 .word 0x40023800
8000a4c: 40020000 .word 0x40020000
08000a50 <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000a50: b580 push {r7, lr}
8000a52: b08c sub sp, #48 ; 0x30
8000a54: af00 add r7, sp, #0
8000a56: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0U;
8000a58: 2300 movs r3, #0
8000a5a: 62bb str r3, [r7, #40] ; 0x28
uint32_t uwPrescalerValue = 0U;
8000a5c: 2300 movs r3, #0
8000a5e: 627b str r3, [r7, #36] ; 0x24
uint32_t pFLatency;
HAL_StatusTypeDef status;
/* Enable TIM1 clock */
__HAL_RCC_TIM1_CLK_ENABLE();
8000a60: 2300 movs r3, #0
8000a62: 60bb str r3, [r7, #8]
8000a64: 4b2e ldr r3, [pc, #184] ; (8000b20 <HAL_InitTick+0xd0>)
8000a66: 6c5b ldr r3, [r3, #68] ; 0x44
8000a68: 4a2d ldr r2, [pc, #180] ; (8000b20 <HAL_InitTick+0xd0>)
8000a6a: f043 0301 orr.w r3, r3, #1
8000a6e: 6453 str r3, [r2, #68] ; 0x44
8000a70: 4b2b ldr r3, [pc, #172] ; (8000b20 <HAL_InitTick+0xd0>)
8000a72: 6c5b ldr r3, [r3, #68] ; 0x44
8000a74: f003 0301 and.w r3, r3, #1
8000a78: 60bb str r3, [r7, #8]
8000a7a: 68bb ldr r3, [r7, #8]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8000a7c: f107 020c add.w r2, r7, #12
8000a80: f107 0310 add.w r3, r7, #16
8000a84: 4611 mov r1, r2
8000a86: 4618 mov r0, r3
8000a88: f001 f822 bl 8001ad0 <HAL_RCC_GetClockConfig>
/* Compute TIM1 clock */
uwTimclock = HAL_RCC_GetPCLK2Freq();
8000a8c: f001 f80c bl 8001aa8 <HAL_RCC_GetPCLK2Freq>
8000a90: 62b8 str r0, [r7, #40] ; 0x28
/* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
8000a92: 6abb ldr r3, [r7, #40] ; 0x28
8000a94: 4a23 ldr r2, [pc, #140] ; (8000b24 <HAL_InitTick+0xd4>)
8000a96: fba2 2303 umull r2, r3, r2, r3
8000a9a: 0c9b lsrs r3, r3, #18
8000a9c: 3b01 subs r3, #1
8000a9e: 627b str r3, [r7, #36] ; 0x24
/* Initialize TIM1 */
htim1.Instance = TIM1;
8000aa0: 4b21 ldr r3, [pc, #132] ; (8000b28 <HAL_InitTick+0xd8>)
8000aa2: 4a22 ldr r2, [pc, #136] ; (8000b2c <HAL_InitTick+0xdc>)
8000aa4: 601a str r2, [r3, #0]
+ Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim1.Init.Period = (1000000U / 1000U) - 1U;
8000aa6: 4b20 ldr r3, [pc, #128] ; (8000b28 <HAL_InitTick+0xd8>)
8000aa8: f240 32e7 movw r2, #999 ; 0x3e7
8000aac: 60da str r2, [r3, #12]
htim1.Init.Prescaler = uwPrescalerValue;
8000aae: 4a1e ldr r2, [pc, #120] ; (8000b28 <HAL_InitTick+0xd8>)
8000ab0: 6a7b ldr r3, [r7, #36] ; 0x24
8000ab2: 6053 str r3, [r2, #4]
htim1.Init.ClockDivision = 0;
8000ab4: 4b1c ldr r3, [pc, #112] ; (8000b28 <HAL_InitTick+0xd8>)
8000ab6: 2200 movs r2, #0
8000ab8: 611a str r2, [r3, #16]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8000aba: 4b1b ldr r3, [pc, #108] ; (8000b28 <HAL_InitTick+0xd8>)
8000abc: 2200 movs r2, #0
8000abe: 609a str r2, [r3, #8]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000ac0: 4b19 ldr r3, [pc, #100] ; (8000b28 <HAL_InitTick+0xd8>)
8000ac2: 2200 movs r2, #0
8000ac4: 619a str r2, [r3, #24]
status = HAL_TIM_Base_Init(&htim1);
8000ac6: 4818 ldr r0, [pc, #96] ; (8000b28 <HAL_InitTick+0xd8>)
8000ac8: f001 f834 bl 8001b34 <HAL_TIM_Base_Init>
8000acc: 4603 mov r3, r0
8000ace: f887 302f strb.w r3, [r7, #47] ; 0x2f
if (status == HAL_OK)
8000ad2: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
8000ad6: 2b00 cmp r3, #0
8000ad8: d11b bne.n 8000b12 <HAL_InitTick+0xc2>
{
/* Start the TIM time Base generation in interrupt mode */
status = HAL_TIM_Base_Start_IT(&htim1);
8000ada: 4813 ldr r0, [pc, #76] ; (8000b28 <HAL_InitTick+0xd8>)
8000adc: f001 f884 bl 8001be8 <HAL_TIM_Base_Start_IT>
8000ae0: 4603 mov r3, r0
8000ae2: f887 302f strb.w r3, [r7, #47] ; 0x2f
if (status == HAL_OK)
8000ae6: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
8000aea: 2b00 cmp r3, #0
8000aec: d111 bne.n 8000b12 <HAL_InitTick+0xc2>
{
/* Enable the TIM1 global Interrupt */
HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
8000aee: 2019 movs r0, #25
8000af0: f000 f992 bl 8000e18 <HAL_NVIC_EnableIRQ>
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000af4: 687b ldr r3, [r7, #4]
8000af6: 2b0f cmp r3, #15
8000af8: d808 bhi.n 8000b0c <HAL_InitTick+0xbc>
{
/* Configure the TIM IRQ priority */
HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, TickPriority, 0U);
8000afa: 2200 movs r2, #0
8000afc: 6879 ldr r1, [r7, #4]
8000afe: 2019 movs r0, #25
8000b00: f000 f96e bl 8000de0 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000b04: 4a0a ldr r2, [pc, #40] ; (8000b30 <HAL_InitTick+0xe0>)
8000b06: 687b ldr r3, [r7, #4]
8000b08: 6013 str r3, [r2, #0]
8000b0a: e002 b.n 8000b12 <HAL_InitTick+0xc2>
}
else
{
status = HAL_ERROR;
8000b0c: 2301 movs r3, #1
8000b0e: f887 302f strb.w r3, [r7, #47] ; 0x2f
}
}
}
/* Return function status */
return status;
8000b12: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
}
8000b16: 4618 mov r0, r3
8000b18: 3730 adds r7, #48 ; 0x30
8000b1a: 46bd mov sp, r7
8000b1c: bd80 pop {r7, pc}
8000b1e: bf00 nop
8000b20: 40023800 .word 0x40023800
8000b24: 431bde83 .word 0x431bde83
8000b28: 200000e0 .word 0x200000e0
8000b2c: 40010000 .word 0x40010000
8000b30: 20000004 .word 0x20000004
08000b34 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000b34: b480 push {r7}
8000b36: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000b38: e7fe b.n 8000b38 <NMI_Handler+0x4>
08000b3a <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000b3a: b480 push {r7}
8000b3c: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000b3e: e7fe b.n 8000b3e <HardFault_Handler+0x4>
08000b40 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000b40: b480 push {r7}
8000b42: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000b44: e7fe b.n 8000b44 <MemManage_Handler+0x4>
08000b46 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000b46: b480 push {r7}
8000b48: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000b4a: e7fe b.n 8000b4a <BusFault_Handler+0x4>
08000b4c <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000b4c: b480 push {r7}
8000b4e: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000b50: e7fe b.n 8000b50 <UsageFault_Handler+0x4>
08000b52 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000b52: b480 push {r7}
8000b54: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000b56: bf00 nop
8000b58: 46bd mov sp, r7
8000b5a: f85d 7b04 ldr.w r7, [sp], #4
8000b5e: 4770 bx lr
08000b60 <TIM1_UP_TIM10_IRQHandler>:
/**
* @brief This function handles TIM1 update interrupt and TIM10 global interrupt.
*/
void TIM1_UP_TIM10_IRQHandler(void)
{
8000b60: b580 push {r7, lr}
8000b62: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */
/* USER CODE END TIM1_UP_TIM10_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
8000b64: 4802 ldr r0, [pc, #8] ; (8000b70 <TIM1_UP_TIM10_IRQHandler+0x10>)
8000b66: f001 f8a1 bl 8001cac <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */
/* USER CODE END TIM1_UP_TIM10_IRQn 1 */
}
8000b6a: bf00 nop
8000b6c: bd80 pop {r7, pc}
8000b6e: bf00 nop
8000b70: 200000e0 .word 0x200000e0
08000b74 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
8000b74: b480 push {r7}
8000b76: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000b78: 4b06 ldr r3, [pc, #24] ; (8000b94 <SystemInit+0x20>)
8000b7a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8000b7e: 4a05 ldr r2, [pc, #20] ; (8000b94 <SystemInit+0x20>)
8000b80: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000b84: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000b88: bf00 nop
8000b8a: 46bd mov sp, r7
8000b8c: f85d 7b04 ldr.w r7, [sp], #4
8000b90: 4770 bx lr
8000b92: bf00 nop
8000b94: e000ed00 .word 0xe000ed00
08000b98 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8000b98: f8df d034 ldr.w sp, [pc, #52] ; 8000bd0 <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000b9c: 480d ldr r0, [pc, #52] ; (8000bd4 <LoopFillZerobss+0x16>)
ldr r1, =_edata
8000b9e: 490e ldr r1, [pc, #56] ; (8000bd8 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
8000ba0: 4a0e ldr r2, [pc, #56] ; (8000bdc <LoopFillZerobss+0x1e>)
movs r3, #0
8000ba2: 2300 movs r3, #0
b LoopCopyDataInit
8000ba4: e002 b.n 8000bac <LoopCopyDataInit>
08000ba6 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000ba6: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000ba8: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000baa: 3304 adds r3, #4
08000bac <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000bac: 18c4 adds r4, r0, r3
cmp r4, r1
8000bae: 428c cmp r4, r1
bcc CopyDataInit
8000bb0: d3f9 bcc.n 8000ba6 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000bb2: 4a0b ldr r2, [pc, #44] ; (8000be0 <LoopFillZerobss+0x22>)
ldr r4, =_ebss
8000bb4: 4c0b ldr r4, [pc, #44] ; (8000be4 <LoopFillZerobss+0x26>)
movs r3, #0
8000bb6: 2300 movs r3, #0
b LoopFillZerobss
8000bb8: e001 b.n 8000bbe <LoopFillZerobss>
08000bba <FillZerobss>:
FillZerobss:
str r3, [r2]
8000bba: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000bbc: 3204 adds r2, #4
08000bbe <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000bbe: 42a2 cmp r2, r4
bcc FillZerobss
8000bc0: d3fb bcc.n 8000bba <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
8000bc2: f7ff ffd7 bl 8000b74 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000bc6: f004 fc97 bl 80054f8 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000bca: f7ff fc87 bl 80004dc <main>
bx lr
8000bce: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8000bd0: 20020000 .word 0x20020000
ldr r0, =_sdata
8000bd4: 20000000 .word 0x20000000
ldr r1, =_edata
8000bd8: 20000060 .word 0x20000060
ldr r2, =_sidata
8000bdc: 080056c8 .word 0x080056c8
ldr r2, =_sbss
8000be0: 20000060 .word 0x20000060
ldr r4, =_ebss
8000be4: 20004c54 .word 0x20004c54
08000be8 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000be8: e7fe b.n 8000be8 <ADC_IRQHandler>
...
08000bec <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000bec: b580 push {r7, lr}
8000bee: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8000bf0: 4b0e ldr r3, [pc, #56] ; (8000c2c <HAL_Init+0x40>)
8000bf2: 681b ldr r3, [r3, #0]
8000bf4: 4a0d ldr r2, [pc, #52] ; (8000c2c <HAL_Init+0x40>)
8000bf6: f443 7300 orr.w r3, r3, #512 ; 0x200
8000bfa: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8000bfc: 4b0b ldr r3, [pc, #44] ; (8000c2c <HAL_Init+0x40>)
8000bfe: 681b ldr r3, [r3, #0]
8000c00: 4a0a ldr r2, [pc, #40] ; (8000c2c <HAL_Init+0x40>)
8000c02: f443 6380 orr.w r3, r3, #1024 ; 0x400
8000c06: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000c08: 4b08 ldr r3, [pc, #32] ; (8000c2c <HAL_Init+0x40>)
8000c0a: 681b ldr r3, [r3, #0]
8000c0c: 4a07 ldr r2, [pc, #28] ; (8000c2c <HAL_Init+0x40>)
8000c0e: f443 7380 orr.w r3, r3, #256 ; 0x100
8000c12: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000c14: 2003 movs r0, #3
8000c16: f000 f8d8 bl 8000dca <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000c1a: 200f movs r0, #15
8000c1c: f7ff ff18 bl 8000a50 <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000c20: f7ff fea2 bl 8000968 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000c24: 2300 movs r3, #0
}
8000c26: 4618 mov r0, r3
8000c28: bd80 pop {r7, pc}
8000c2a: bf00 nop
8000c2c: 40023c00 .word 0x40023c00
08000c30 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000c30: b480 push {r7}
8000c32: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000c34: 4b06 ldr r3, [pc, #24] ; (8000c50 <HAL_IncTick+0x20>)
8000c36: 781b ldrb r3, [r3, #0]
8000c38: 461a mov r2, r3
8000c3a: 4b06 ldr r3, [pc, #24] ; (8000c54 <HAL_IncTick+0x24>)
8000c3c: 681b ldr r3, [r3, #0]
8000c3e: 4413 add r3, r2
8000c40: 4a04 ldr r2, [pc, #16] ; (8000c54 <HAL_IncTick+0x24>)
8000c42: 6013 str r3, [r2, #0]
}
8000c44: bf00 nop
8000c46: 46bd mov sp, r7
8000c48: f85d 7b04 ldr.w r7, [sp], #4
8000c4c: 4770 bx lr
8000c4e: bf00 nop
8000c50: 20000008 .word 0x20000008
8000c54: 20000128 .word 0x20000128
08000c58 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000c58: b480 push {r7}
8000c5a: af00 add r7, sp, #0
return uwTick;
8000c5c: 4b03 ldr r3, [pc, #12] ; (8000c6c <HAL_GetTick+0x14>)
8000c5e: 681b ldr r3, [r3, #0]
}
8000c60: 4618 mov r0, r3
8000c62: 46bd mov sp, r7
8000c64: f85d 7b04 ldr.w r7, [sp], #4
8000c68: 4770 bx lr
8000c6a: bf00 nop
8000c6c: 20000128 .word 0x20000128
08000c70 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000c70: b480 push {r7}
8000c72: b085 sub sp, #20
8000c74: af00 add r7, sp, #0
8000c76: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000c78: 687b ldr r3, [r7, #4]
8000c7a: f003 0307 and.w r3, r3, #7
8000c7e: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000c80: 4b0c ldr r3, [pc, #48] ; (8000cb4 <__NVIC_SetPriorityGrouping+0x44>)
8000c82: 68db ldr r3, [r3, #12]
8000c84: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000c86: 68ba ldr r2, [r7, #8]
8000c88: f64f 03ff movw r3, #63743 ; 0xf8ff
8000c8c: 4013 ands r3, r2
8000c8e: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000c90: 68fb ldr r3, [r7, #12]
8000c92: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000c94: 68bb ldr r3, [r7, #8]
8000c96: 4313 orrs r3, r2
reg_value = (reg_value |
8000c98: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000c9c: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000ca0: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000ca2: 4a04 ldr r2, [pc, #16] ; (8000cb4 <__NVIC_SetPriorityGrouping+0x44>)
8000ca4: 68bb ldr r3, [r7, #8]
8000ca6: 60d3 str r3, [r2, #12]
}
8000ca8: bf00 nop
8000caa: 3714 adds r7, #20
8000cac: 46bd mov sp, r7
8000cae: f85d 7b04 ldr.w r7, [sp], #4
8000cb2: 4770 bx lr
8000cb4: e000ed00 .word 0xe000ed00
08000cb8 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000cb8: b480 push {r7}
8000cba: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000cbc: 4b04 ldr r3, [pc, #16] ; (8000cd0 <__NVIC_GetPriorityGrouping+0x18>)
8000cbe: 68db ldr r3, [r3, #12]
8000cc0: 0a1b lsrs r3, r3, #8
8000cc2: f003 0307 and.w r3, r3, #7
}
8000cc6: 4618 mov r0, r3
8000cc8: 46bd mov sp, r7
8000cca: f85d 7b04 ldr.w r7, [sp], #4
8000cce: 4770 bx lr
8000cd0: e000ed00 .word 0xe000ed00
08000cd4 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000cd4: b480 push {r7}
8000cd6: b083 sub sp, #12
8000cd8: af00 add r7, sp, #0
8000cda: 4603 mov r3, r0
8000cdc: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000cde: f997 3007 ldrsb.w r3, [r7, #7]
8000ce2: 2b00 cmp r3, #0
8000ce4: db0b blt.n 8000cfe <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8000ce6: 79fb ldrb r3, [r7, #7]
8000ce8: f003 021f and.w r2, r3, #31
8000cec: 4907 ldr r1, [pc, #28] ; (8000d0c <__NVIC_EnableIRQ+0x38>)
8000cee: f997 3007 ldrsb.w r3, [r7, #7]
8000cf2: 095b lsrs r3, r3, #5
8000cf4: 2001 movs r0, #1
8000cf6: fa00 f202 lsl.w r2, r0, r2
8000cfa: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8000cfe: bf00 nop
8000d00: 370c adds r7, #12
8000d02: 46bd mov sp, r7
8000d04: f85d 7b04 ldr.w r7, [sp], #4
8000d08: 4770 bx lr
8000d0a: bf00 nop
8000d0c: e000e100 .word 0xe000e100
08000d10 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000d10: b480 push {r7}
8000d12: b083 sub sp, #12
8000d14: af00 add r7, sp, #0
8000d16: 4603 mov r3, r0
8000d18: 6039 str r1, [r7, #0]
8000d1a: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000d1c: f997 3007 ldrsb.w r3, [r7, #7]
8000d20: 2b00 cmp r3, #0
8000d22: db0a blt.n 8000d3a <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000d24: 683b ldr r3, [r7, #0]
8000d26: b2da uxtb r2, r3
8000d28: 490c ldr r1, [pc, #48] ; (8000d5c <__NVIC_SetPriority+0x4c>)
8000d2a: f997 3007 ldrsb.w r3, [r7, #7]
8000d2e: 0112 lsls r2, r2, #4
8000d30: b2d2 uxtb r2, r2
8000d32: 440b add r3, r1
8000d34: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000d38: e00a b.n 8000d50 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000d3a: 683b ldr r3, [r7, #0]
8000d3c: b2da uxtb r2, r3
8000d3e: 4908 ldr r1, [pc, #32] ; (8000d60 <__NVIC_SetPriority+0x50>)
8000d40: 79fb ldrb r3, [r7, #7]
8000d42: f003 030f and.w r3, r3, #15
8000d46: 3b04 subs r3, #4
8000d48: 0112 lsls r2, r2, #4
8000d4a: b2d2 uxtb r2, r2
8000d4c: 440b add r3, r1
8000d4e: 761a strb r2, [r3, #24]
}
8000d50: bf00 nop
8000d52: 370c adds r7, #12
8000d54: 46bd mov sp, r7
8000d56: f85d 7b04 ldr.w r7, [sp], #4
8000d5a: 4770 bx lr
8000d5c: e000e100 .word 0xe000e100
8000d60: e000ed00 .word 0xe000ed00
08000d64 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000d64: b480 push {r7}
8000d66: b089 sub sp, #36 ; 0x24
8000d68: af00 add r7, sp, #0
8000d6a: 60f8 str r0, [r7, #12]
8000d6c: 60b9 str r1, [r7, #8]
8000d6e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000d70: 68fb ldr r3, [r7, #12]
8000d72: f003 0307 and.w r3, r3, #7
8000d76: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000d78: 69fb ldr r3, [r7, #28]
8000d7a: f1c3 0307 rsb r3, r3, #7
8000d7e: 2b04 cmp r3, #4
8000d80: bf28 it cs
8000d82: 2304 movcs r3, #4
8000d84: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000d86: 69fb ldr r3, [r7, #28]
8000d88: 3304 adds r3, #4
8000d8a: 2b06 cmp r3, #6
8000d8c: d902 bls.n 8000d94 <NVIC_EncodePriority+0x30>
8000d8e: 69fb ldr r3, [r7, #28]
8000d90: 3b03 subs r3, #3
8000d92: e000 b.n 8000d96 <NVIC_EncodePriority+0x32>
8000d94: 2300 movs r3, #0
8000d96: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000d98: f04f 32ff mov.w r2, #4294967295
8000d9c: 69bb ldr r3, [r7, #24]
8000d9e: fa02 f303 lsl.w r3, r2, r3
8000da2: 43da mvns r2, r3
8000da4: 68bb ldr r3, [r7, #8]
8000da6: 401a ands r2, r3
8000da8: 697b ldr r3, [r7, #20]
8000daa: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000dac: f04f 31ff mov.w r1, #4294967295
8000db0: 697b ldr r3, [r7, #20]
8000db2: fa01 f303 lsl.w r3, r1, r3
8000db6: 43d9 mvns r1, r3
8000db8: 687b ldr r3, [r7, #4]
8000dba: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000dbc: 4313 orrs r3, r2
);
}
8000dbe: 4618 mov r0, r3
8000dc0: 3724 adds r7, #36 ; 0x24
8000dc2: 46bd mov sp, r7
8000dc4: f85d 7b04 ldr.w r7, [sp], #4
8000dc8: 4770 bx lr
08000dca <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000dca: b580 push {r7, lr}
8000dcc: b082 sub sp, #8
8000dce: af00 add r7, sp, #0
8000dd0: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000dd2: 6878 ldr r0, [r7, #4]
8000dd4: f7ff ff4c bl 8000c70 <__NVIC_SetPriorityGrouping>
}
8000dd8: bf00 nop
8000dda: 3708 adds r7, #8
8000ddc: 46bd mov sp, r7
8000dde: bd80 pop {r7, pc}
08000de0 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000de0: b580 push {r7, lr}
8000de2: b086 sub sp, #24
8000de4: af00 add r7, sp, #0
8000de6: 4603 mov r3, r0
8000de8: 60b9 str r1, [r7, #8]
8000dea: 607a str r2, [r7, #4]
8000dec: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8000dee: 2300 movs r3, #0
8000df0: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000df2: f7ff ff61 bl 8000cb8 <__NVIC_GetPriorityGrouping>
8000df6: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000df8: 687a ldr r2, [r7, #4]
8000dfa: 68b9 ldr r1, [r7, #8]
8000dfc: 6978 ldr r0, [r7, #20]
8000dfe: f7ff ffb1 bl 8000d64 <NVIC_EncodePriority>
8000e02: 4602 mov r2, r0
8000e04: f997 300f ldrsb.w r3, [r7, #15]
8000e08: 4611 mov r1, r2
8000e0a: 4618 mov r0, r3
8000e0c: f7ff ff80 bl 8000d10 <__NVIC_SetPriority>
}
8000e10: bf00 nop
8000e12: 3718 adds r7, #24
8000e14: 46bd mov sp, r7
8000e16: bd80 pop {r7, pc}
08000e18 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000e18: b580 push {r7, lr}
8000e1a: b082 sub sp, #8
8000e1c: af00 add r7, sp, #0
8000e1e: 4603 mov r3, r0
8000e20: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8000e22: f997 3007 ldrsb.w r3, [r7, #7]
8000e26: 4618 mov r0, r3
8000e28: f7ff ff54 bl 8000cd4 <__NVIC_EnableIRQ>
}
8000e2c: bf00 nop
8000e2e: 3708 adds r7, #8
8000e30: 46bd mov sp, r7
8000e32: bd80 pop {r7, pc}
08000e34 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000e34: b480 push {r7}
8000e36: b089 sub sp, #36 ; 0x24
8000e38: af00 add r7, sp, #0
8000e3a: 6078 str r0, [r7, #4]
8000e3c: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
8000e3e: 2300 movs r3, #0
8000e40: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8000e42: 2300 movs r3, #0
8000e44: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8000e46: 2300 movs r3, #0
8000e48: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
8000e4a: 2300 movs r3, #0
8000e4c: 61fb str r3, [r7, #28]
8000e4e: e159 b.n 8001104 <HAL_GPIO_Init+0x2d0>
{
/* Get the IO position */
ioposition = 0x01U << position;
8000e50: 2201 movs r2, #1
8000e52: 69fb ldr r3, [r7, #28]
8000e54: fa02 f303 lsl.w r3, r2, r3
8000e58: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8000e5a: 683b ldr r3, [r7, #0]
8000e5c: 681b ldr r3, [r3, #0]
8000e5e: 697a ldr r2, [r7, #20]
8000e60: 4013 ands r3, r2
8000e62: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8000e64: 693a ldr r2, [r7, #16]
8000e66: 697b ldr r3, [r7, #20]
8000e68: 429a cmp r2, r3
8000e6a: f040 8148 bne.w 80010fe <HAL_GPIO_Init+0x2ca>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8000e6e: 683b ldr r3, [r7, #0]
8000e70: 685b ldr r3, [r3, #4]
8000e72: f003 0303 and.w r3, r3, #3
8000e76: 2b01 cmp r3, #1
8000e78: d005 beq.n 8000e86 <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000e7a: 683b ldr r3, [r7, #0]
8000e7c: 685b ldr r3, [r3, #4]
8000e7e: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8000e82: 2b02 cmp r3, #2
8000e84: d130 bne.n 8000ee8 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000e86: 687b ldr r3, [r7, #4]
8000e88: 689b ldr r3, [r3, #8]
8000e8a: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8000e8c: 69fb ldr r3, [r7, #28]
8000e8e: 005b lsls r3, r3, #1
8000e90: 2203 movs r2, #3
8000e92: fa02 f303 lsl.w r3, r2, r3
8000e96: 43db mvns r3, r3
8000e98: 69ba ldr r2, [r7, #24]
8000e9a: 4013 ands r3, r2
8000e9c: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8000e9e: 683b ldr r3, [r7, #0]
8000ea0: 68da ldr r2, [r3, #12]
8000ea2: 69fb ldr r3, [r7, #28]
8000ea4: 005b lsls r3, r3, #1
8000ea6: fa02 f303 lsl.w r3, r2, r3
8000eaa: 69ba ldr r2, [r7, #24]
8000eac: 4313 orrs r3, r2
8000eae: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8000eb0: 687b ldr r3, [r7, #4]
8000eb2: 69ba ldr r2, [r7, #24]
8000eb4: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000eb6: 687b ldr r3, [r7, #4]
8000eb8: 685b ldr r3, [r3, #4]
8000eba: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8000ebc: 2201 movs r2, #1
8000ebe: 69fb ldr r3, [r7, #28]
8000ec0: fa02 f303 lsl.w r3, r2, r3
8000ec4: 43db mvns r3, r3
8000ec6: 69ba ldr r2, [r7, #24]
8000ec8: 4013 ands r3, r2
8000eca: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000ecc: 683b ldr r3, [r7, #0]
8000ece: 685b ldr r3, [r3, #4]
8000ed0: 091b lsrs r3, r3, #4
8000ed2: f003 0201 and.w r2, r3, #1
8000ed6: 69fb ldr r3, [r7, #28]
8000ed8: fa02 f303 lsl.w r3, r2, r3
8000edc: 69ba ldr r2, [r7, #24]
8000ede: 4313 orrs r3, r2
8000ee0: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8000ee2: 687b ldr r3, [r7, #4]
8000ee4: 69ba ldr r2, [r7, #24]
8000ee6: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000ee8: 683b ldr r3, [r7, #0]
8000eea: 685b ldr r3, [r3, #4]
8000eec: f003 0303 and.w r3, r3, #3
8000ef0: 2b03 cmp r3, #3
8000ef2: d017 beq.n 8000f24 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000ef4: 687b ldr r3, [r7, #4]
8000ef6: 68db ldr r3, [r3, #12]
8000ef8: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8000efa: 69fb ldr r3, [r7, #28]
8000efc: 005b lsls r3, r3, #1
8000efe: 2203 movs r2, #3
8000f00: fa02 f303 lsl.w r3, r2, r3
8000f04: 43db mvns r3, r3
8000f06: 69ba ldr r2, [r7, #24]
8000f08: 4013 ands r3, r2
8000f0a: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8000f0c: 683b ldr r3, [r7, #0]
8000f0e: 689a ldr r2, [r3, #8]
8000f10: 69fb ldr r3, [r7, #28]
8000f12: 005b lsls r3, r3, #1
8000f14: fa02 f303 lsl.w r3, r2, r3
8000f18: 69ba ldr r2, [r7, #24]
8000f1a: 4313 orrs r3, r2
8000f1c: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8000f1e: 687b ldr r3, [r7, #4]
8000f20: 69ba ldr r2, [r7, #24]
8000f22: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000f24: 683b ldr r3, [r7, #0]
8000f26: 685b ldr r3, [r3, #4]
8000f28: f003 0303 and.w r3, r3, #3
8000f2c: 2b02 cmp r3, #2
8000f2e: d123 bne.n 8000f78 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8000f30: 69fb ldr r3, [r7, #28]
8000f32: 08da lsrs r2, r3, #3
8000f34: 687b ldr r3, [r7, #4]
8000f36: 3208 adds r2, #8
8000f38: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8000f3c: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
8000f3e: 69fb ldr r3, [r7, #28]
8000f40: f003 0307 and.w r3, r3, #7
8000f44: 009b lsls r3, r3, #2
8000f46: 220f movs r2, #15
8000f48: fa02 f303 lsl.w r3, r2, r3
8000f4c: 43db mvns r3, r3
8000f4e: 69ba ldr r2, [r7, #24]
8000f50: 4013 ands r3, r2
8000f52: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8000f54: 683b ldr r3, [r7, #0]
8000f56: 691a ldr r2, [r3, #16]
8000f58: 69fb ldr r3, [r7, #28]
8000f5a: f003 0307 and.w r3, r3, #7
8000f5e: 009b lsls r3, r3, #2
8000f60: fa02 f303 lsl.w r3, r2, r3
8000f64: 69ba ldr r2, [r7, #24]
8000f66: 4313 orrs r3, r2
8000f68: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8000f6a: 69fb ldr r3, [r7, #28]
8000f6c: 08da lsrs r2, r3, #3
8000f6e: 687b ldr r3, [r7, #4]
8000f70: 3208 adds r2, #8
8000f72: 69b9 ldr r1, [r7, #24]
8000f74: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000f78: 687b ldr r3, [r7, #4]
8000f7a: 681b ldr r3, [r3, #0]
8000f7c: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
8000f7e: 69fb ldr r3, [r7, #28]
8000f80: 005b lsls r3, r3, #1
8000f82: 2203 movs r2, #3
8000f84: fa02 f303 lsl.w r3, r2, r3
8000f88: 43db mvns r3, r3
8000f8a: 69ba ldr r2, [r7, #24]
8000f8c: 4013 ands r3, r2
8000f8e: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8000f90: 683b ldr r3, [r7, #0]
8000f92: 685b ldr r3, [r3, #4]
8000f94: f003 0203 and.w r2, r3, #3
8000f98: 69fb ldr r3, [r7, #28]
8000f9a: 005b lsls r3, r3, #1
8000f9c: fa02 f303 lsl.w r3, r2, r3
8000fa0: 69ba ldr r2, [r7, #24]
8000fa2: 4313 orrs r3, r2
8000fa4: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8000fa6: 687b ldr r3, [r7, #4]
8000fa8: 69ba ldr r2, [r7, #24]
8000faa: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8000fac: 683b ldr r3, [r7, #0]
8000fae: 685b ldr r3, [r3, #4]
8000fb0: f403 3340 and.w r3, r3, #196608 ; 0x30000
8000fb4: 2b00 cmp r3, #0
8000fb6: f000 80a2 beq.w 80010fe <HAL_GPIO_Init+0x2ca>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000fba: 2300 movs r3, #0
8000fbc: 60fb str r3, [r7, #12]
8000fbe: 4b57 ldr r3, [pc, #348] ; (800111c <HAL_GPIO_Init+0x2e8>)
8000fc0: 6c5b ldr r3, [r3, #68] ; 0x44
8000fc2: 4a56 ldr r2, [pc, #344] ; (800111c <HAL_GPIO_Init+0x2e8>)
8000fc4: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000fc8: 6453 str r3, [r2, #68] ; 0x44
8000fca: 4b54 ldr r3, [pc, #336] ; (800111c <HAL_GPIO_Init+0x2e8>)
8000fcc: 6c5b ldr r3, [r3, #68] ; 0x44
8000fce: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000fd2: 60fb str r3, [r7, #12]
8000fd4: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8000fd6: 4a52 ldr r2, [pc, #328] ; (8001120 <HAL_GPIO_Init+0x2ec>)
8000fd8: 69fb ldr r3, [r7, #28]
8000fda: 089b lsrs r3, r3, #2
8000fdc: 3302 adds r3, #2
8000fde: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000fe2: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8000fe4: 69fb ldr r3, [r7, #28]
8000fe6: f003 0303 and.w r3, r3, #3
8000fea: 009b lsls r3, r3, #2
8000fec: 220f movs r2, #15
8000fee: fa02 f303 lsl.w r3, r2, r3
8000ff2: 43db mvns r3, r3
8000ff4: 69ba ldr r2, [r7, #24]
8000ff6: 4013 ands r3, r2
8000ff8: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8000ffa: 687b ldr r3, [r7, #4]
8000ffc: 4a49 ldr r2, [pc, #292] ; (8001124 <HAL_GPIO_Init+0x2f0>)
8000ffe: 4293 cmp r3, r2
8001000: d019 beq.n 8001036 <HAL_GPIO_Init+0x202>
8001002: 687b ldr r3, [r7, #4]
8001004: 4a48 ldr r2, [pc, #288] ; (8001128 <HAL_GPIO_Init+0x2f4>)
8001006: 4293 cmp r3, r2
8001008: d013 beq.n 8001032 <HAL_GPIO_Init+0x1fe>
800100a: 687b ldr r3, [r7, #4]
800100c: 4a47 ldr r2, [pc, #284] ; (800112c <HAL_GPIO_Init+0x2f8>)
800100e: 4293 cmp r3, r2
8001010: d00d beq.n 800102e <HAL_GPIO_Init+0x1fa>
8001012: 687b ldr r3, [r7, #4]
8001014: 4a46 ldr r2, [pc, #280] ; (8001130 <HAL_GPIO_Init+0x2fc>)
8001016: 4293 cmp r3, r2
8001018: d007 beq.n 800102a <HAL_GPIO_Init+0x1f6>
800101a: 687b ldr r3, [r7, #4]
800101c: 4a45 ldr r2, [pc, #276] ; (8001134 <HAL_GPIO_Init+0x300>)
800101e: 4293 cmp r3, r2
8001020: d101 bne.n 8001026 <HAL_GPIO_Init+0x1f2>
8001022: 2304 movs r3, #4
8001024: e008 b.n 8001038 <HAL_GPIO_Init+0x204>
8001026: 2307 movs r3, #7
8001028: e006 b.n 8001038 <HAL_GPIO_Init+0x204>
800102a: 2303 movs r3, #3
800102c: e004 b.n 8001038 <HAL_GPIO_Init+0x204>
800102e: 2302 movs r3, #2
8001030: e002 b.n 8001038 <HAL_GPIO_Init+0x204>
8001032: 2301 movs r3, #1
8001034: e000 b.n 8001038 <HAL_GPIO_Init+0x204>
8001036: 2300 movs r3, #0
8001038: 69fa ldr r2, [r7, #28]
800103a: f002 0203 and.w r2, r2, #3
800103e: 0092 lsls r2, r2, #2
8001040: 4093 lsls r3, r2
8001042: 69ba ldr r2, [r7, #24]
8001044: 4313 orrs r3, r2
8001046: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8001048: 4935 ldr r1, [pc, #212] ; (8001120 <HAL_GPIO_Init+0x2ec>)
800104a: 69fb ldr r3, [r7, #28]
800104c: 089b lsrs r3, r3, #2
800104e: 3302 adds r3, #2
8001050: 69ba ldr r2, [r7, #24]
8001052: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001056: 4b38 ldr r3, [pc, #224] ; (8001138 <HAL_GPIO_Init+0x304>)
8001058: 689b ldr r3, [r3, #8]
800105a: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800105c: 693b ldr r3, [r7, #16]
800105e: 43db mvns r3, r3
8001060: 69ba ldr r2, [r7, #24]
8001062: 4013 ands r3, r2
8001064: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8001066: 683b ldr r3, [r7, #0]
8001068: 685b ldr r3, [r3, #4]
800106a: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800106e: 2b00 cmp r3, #0
8001070: d003 beq.n 800107a <HAL_GPIO_Init+0x246>
{
temp |= iocurrent;
8001072: 69ba ldr r2, [r7, #24]
8001074: 693b ldr r3, [r7, #16]
8001076: 4313 orrs r3, r2
8001078: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
800107a: 4a2f ldr r2, [pc, #188] ; (8001138 <HAL_GPIO_Init+0x304>)
800107c: 69bb ldr r3, [r7, #24]
800107e: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8001080: 4b2d ldr r3, [pc, #180] ; (8001138 <HAL_GPIO_Init+0x304>)
8001082: 68db ldr r3, [r3, #12]
8001084: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001086: 693b ldr r3, [r7, #16]
8001088: 43db mvns r3, r3
800108a: 69ba ldr r2, [r7, #24]
800108c: 4013 ands r3, r2
800108e: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8001090: 683b ldr r3, [r7, #0]
8001092: 685b ldr r3, [r3, #4]
8001094: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8001098: 2b00 cmp r3, #0
800109a: d003 beq.n 80010a4 <HAL_GPIO_Init+0x270>
{
temp |= iocurrent;
800109c: 69ba ldr r2, [r7, #24]
800109e: 693b ldr r3, [r7, #16]
80010a0: 4313 orrs r3, r2
80010a2: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
80010a4: 4a24 ldr r2, [pc, #144] ; (8001138 <HAL_GPIO_Init+0x304>)
80010a6: 69bb ldr r3, [r7, #24]
80010a8: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
80010aa: 4b23 ldr r3, [pc, #140] ; (8001138 <HAL_GPIO_Init+0x304>)
80010ac: 685b ldr r3, [r3, #4]
80010ae: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80010b0: 693b ldr r3, [r7, #16]
80010b2: 43db mvns r3, r3
80010b4: 69ba ldr r2, [r7, #24]
80010b6: 4013 ands r3, r2
80010b8: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
80010ba: 683b ldr r3, [r7, #0]
80010bc: 685b ldr r3, [r3, #4]
80010be: f403 3300 and.w r3, r3, #131072 ; 0x20000
80010c2: 2b00 cmp r3, #0
80010c4: d003 beq.n 80010ce <HAL_GPIO_Init+0x29a>
{
temp |= iocurrent;
80010c6: 69ba ldr r2, [r7, #24]
80010c8: 693b ldr r3, [r7, #16]
80010ca: 4313 orrs r3, r2
80010cc: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
80010ce: 4a1a ldr r2, [pc, #104] ; (8001138 <HAL_GPIO_Init+0x304>)
80010d0: 69bb ldr r3, [r7, #24]
80010d2: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80010d4: 4b18 ldr r3, [pc, #96] ; (8001138 <HAL_GPIO_Init+0x304>)
80010d6: 681b ldr r3, [r3, #0]
80010d8: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80010da: 693b ldr r3, [r7, #16]
80010dc: 43db mvns r3, r3
80010de: 69ba ldr r2, [r7, #24]
80010e0: 4013 ands r3, r2
80010e2: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
80010e4: 683b ldr r3, [r7, #0]
80010e6: 685b ldr r3, [r3, #4]
80010e8: f403 3380 and.w r3, r3, #65536 ; 0x10000
80010ec: 2b00 cmp r3, #0
80010ee: d003 beq.n 80010f8 <HAL_GPIO_Init+0x2c4>
{
temp |= iocurrent;
80010f0: 69ba ldr r2, [r7, #24]
80010f2: 693b ldr r3, [r7, #16]
80010f4: 4313 orrs r3, r2
80010f6: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
80010f8: 4a0f ldr r2, [pc, #60] ; (8001138 <HAL_GPIO_Init+0x304>)
80010fa: 69bb ldr r3, [r7, #24]
80010fc: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
80010fe: 69fb ldr r3, [r7, #28]
8001100: 3301 adds r3, #1
8001102: 61fb str r3, [r7, #28]
8001104: 69fb ldr r3, [r7, #28]
8001106: 2b0f cmp r3, #15
8001108: f67f aea2 bls.w 8000e50 <HAL_GPIO_Init+0x1c>
}
}
}
}
800110c: bf00 nop
800110e: bf00 nop
8001110: 3724 adds r7, #36 ; 0x24
8001112: 46bd mov sp, r7
8001114: f85d 7b04 ldr.w r7, [sp], #4
8001118: 4770 bx lr
800111a: bf00 nop
800111c: 40023800 .word 0x40023800
8001120: 40013800 .word 0x40013800
8001124: 40020000 .word 0x40020000
8001128: 40020400 .word 0x40020400
800112c: 40020800 .word 0x40020800
8001130: 40020c00 .word 0x40020c00
8001134: 40021000 .word 0x40021000
8001138: 40013c00 .word 0x40013c00
0800113c <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
800113c: b480 push {r7}
800113e: b085 sub sp, #20
8001140: af00 add r7, sp, #0
8001142: 6078 str r0, [r7, #4]
8001144: 460b mov r3, r1
8001146: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8001148: 687b ldr r3, [r7, #4]
800114a: 691a ldr r2, [r3, #16]
800114c: 887b ldrh r3, [r7, #2]
800114e: 4013 ands r3, r2
8001150: 2b00 cmp r3, #0
8001152: d002 beq.n 800115a <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8001154: 2301 movs r3, #1
8001156: 73fb strb r3, [r7, #15]
8001158: e001 b.n 800115e <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
800115a: 2300 movs r3, #0
800115c: 73fb strb r3, [r7, #15]
}
return bitstatus;
800115e: 7bfb ldrb r3, [r7, #15]
}
8001160: 4618 mov r0, r3
8001162: 3714 adds r7, #20
8001164: 46bd mov sp, r7
8001166: f85d 7b04 ldr.w r7, [sp], #4
800116a: 4770 bx lr
0800116c <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
800116c: b480 push {r7}
800116e: b083 sub sp, #12
8001170: af00 add r7, sp, #0
8001172: 6078 str r0, [r7, #4]
8001174: 460b mov r3, r1
8001176: 807b strh r3, [r7, #2]
8001178: 4613 mov r3, r2
800117a: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
800117c: 787b ldrb r3, [r7, #1]
800117e: 2b00 cmp r3, #0
8001180: d003 beq.n 800118a <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8001182: 887a ldrh r2, [r7, #2]
8001184: 687b ldr r3, [r7, #4]
8001186: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8001188: e003 b.n 8001192 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
800118a: 887b ldrh r3, [r7, #2]
800118c: 041a lsls r2, r3, #16
800118e: 687b ldr r3, [r7, #4]
8001190: 619a str r2, [r3, #24]
}
8001192: bf00 nop
8001194: 370c adds r7, #12
8001196: 46bd mov sp, r7
8001198: f85d 7b04 ldr.w r7, [sp], #4
800119c: 4770 bx lr
...
080011a0 <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80011a0: b580 push {r7, lr}
80011a2: b086 sub sp, #24
80011a4: af00 add r7, sp, #0
80011a6: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
80011a8: 687b ldr r3, [r7, #4]
80011aa: 2b00 cmp r3, #0
80011ac: d101 bne.n 80011b2 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80011ae: 2301 movs r3, #1
80011b0: e267 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80011b2: 687b ldr r3, [r7, #4]
80011b4: 681b ldr r3, [r3, #0]
80011b6: f003 0301 and.w r3, r3, #1
80011ba: 2b00 cmp r3, #0
80011bc: d075 beq.n 80012aa <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
80011be: 4b88 ldr r3, [pc, #544] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80011c0: 689b ldr r3, [r3, #8]
80011c2: f003 030c and.w r3, r3, #12
80011c6: 2b04 cmp r3, #4
80011c8: d00c beq.n 80011e4 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80011ca: 4b85 ldr r3, [pc, #532] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80011cc: 689b ldr r3, [r3, #8]
80011ce: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
80011d2: 2b08 cmp r3, #8
80011d4: d112 bne.n 80011fc <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80011d6: 4b82 ldr r3, [pc, #520] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80011d8: 685b ldr r3, [r3, #4]
80011da: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80011de: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80011e2: d10b bne.n 80011fc <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80011e4: 4b7e ldr r3, [pc, #504] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80011e6: 681b ldr r3, [r3, #0]
80011e8: f403 3300 and.w r3, r3, #131072 ; 0x20000
80011ec: 2b00 cmp r3, #0
80011ee: d05b beq.n 80012a8 <HAL_RCC_OscConfig+0x108>
80011f0: 687b ldr r3, [r7, #4]
80011f2: 685b ldr r3, [r3, #4]
80011f4: 2b00 cmp r3, #0
80011f6: d157 bne.n 80012a8 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
80011f8: 2301 movs r3, #1
80011fa: e242 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80011fc: 687b ldr r3, [r7, #4]
80011fe: 685b ldr r3, [r3, #4]
8001200: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8001204: d106 bne.n 8001214 <HAL_RCC_OscConfig+0x74>
8001206: 4b76 ldr r3, [pc, #472] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
8001208: 681b ldr r3, [r3, #0]
800120a: 4a75 ldr r2, [pc, #468] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
800120c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001210: 6013 str r3, [r2, #0]
8001212: e01d b.n 8001250 <HAL_RCC_OscConfig+0xb0>
8001214: 687b ldr r3, [r7, #4]
8001216: 685b ldr r3, [r3, #4]
8001218: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
800121c: d10c bne.n 8001238 <HAL_RCC_OscConfig+0x98>
800121e: 4b70 ldr r3, [pc, #448] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
8001220: 681b ldr r3, [r3, #0]
8001222: 4a6f ldr r2, [pc, #444] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
8001224: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8001228: 6013 str r3, [r2, #0]
800122a: 4b6d ldr r3, [pc, #436] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
800122c: 681b ldr r3, [r3, #0]
800122e: 4a6c ldr r2, [pc, #432] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
8001230: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001234: 6013 str r3, [r2, #0]
8001236: e00b b.n 8001250 <HAL_RCC_OscConfig+0xb0>
8001238: 4b69 ldr r3, [pc, #420] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
800123a: 681b ldr r3, [r3, #0]
800123c: 4a68 ldr r2, [pc, #416] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
800123e: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001242: 6013 str r3, [r2, #0]
8001244: 4b66 ldr r3, [pc, #408] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
8001246: 681b ldr r3, [r3, #0]
8001248: 4a65 ldr r2, [pc, #404] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
800124a: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800124e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
8001250: 687b ldr r3, [r7, #4]
8001252: 685b ldr r3, [r3, #4]
8001254: 2b00 cmp r3, #0
8001256: d013 beq.n 8001280 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001258: f7ff fcfe bl 8000c58 <HAL_GetTick>
800125c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800125e: e008 b.n 8001272 <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001260: f7ff fcfa bl 8000c58 <HAL_GetTick>
8001264: 4602 mov r2, r0
8001266: 693b ldr r3, [r7, #16]
8001268: 1ad3 subs r3, r2, r3
800126a: 2b64 cmp r3, #100 ; 0x64
800126c: d901 bls.n 8001272 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
800126e: 2303 movs r3, #3
8001270: e207 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001272: 4b5b ldr r3, [pc, #364] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
8001274: 681b ldr r3, [r3, #0]
8001276: f403 3300 and.w r3, r3, #131072 ; 0x20000
800127a: 2b00 cmp r3, #0
800127c: d0f0 beq.n 8001260 <HAL_RCC_OscConfig+0xc0>
800127e: e014 b.n 80012aa <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001280: f7ff fcea bl 8000c58 <HAL_GetTick>
8001284: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8001286: e008 b.n 800129a <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001288: f7ff fce6 bl 8000c58 <HAL_GetTick>
800128c: 4602 mov r2, r0
800128e: 693b ldr r3, [r7, #16]
8001290: 1ad3 subs r3, r2, r3
8001292: 2b64 cmp r3, #100 ; 0x64
8001294: d901 bls.n 800129a <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
8001296: 2303 movs r3, #3
8001298: e1f3 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800129a: 4b51 ldr r3, [pc, #324] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
800129c: 681b ldr r3, [r3, #0]
800129e: f403 3300 and.w r3, r3, #131072 ; 0x20000
80012a2: 2b00 cmp r3, #0
80012a4: d1f0 bne.n 8001288 <HAL_RCC_OscConfig+0xe8>
80012a6: e000 b.n 80012aa <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80012a8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80012aa: 687b ldr r3, [r7, #4]
80012ac: 681b ldr r3, [r3, #0]
80012ae: f003 0302 and.w r3, r3, #2
80012b2: 2b00 cmp r3, #0
80012b4: d063 beq.n 800137e <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
80012b6: 4b4a ldr r3, [pc, #296] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80012b8: 689b ldr r3, [r3, #8]
80012ba: f003 030c and.w r3, r3, #12
80012be: 2b00 cmp r3, #0
80012c0: d00b beq.n 80012da <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80012c2: 4b47 ldr r3, [pc, #284] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80012c4: 689b ldr r3, [r3, #8]
80012c6: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
80012ca: 2b08 cmp r3, #8
80012cc: d11c bne.n 8001308 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80012ce: 4b44 ldr r3, [pc, #272] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80012d0: 685b ldr r3, [r3, #4]
80012d2: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80012d6: 2b00 cmp r3, #0
80012d8: d116 bne.n 8001308 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80012da: 4b41 ldr r3, [pc, #260] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80012dc: 681b ldr r3, [r3, #0]
80012de: f003 0302 and.w r3, r3, #2
80012e2: 2b00 cmp r3, #0
80012e4: d005 beq.n 80012f2 <HAL_RCC_OscConfig+0x152>
80012e6: 687b ldr r3, [r7, #4]
80012e8: 68db ldr r3, [r3, #12]
80012ea: 2b01 cmp r3, #1
80012ec: d001 beq.n 80012f2 <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
80012ee: 2301 movs r3, #1
80012f0: e1c7 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80012f2: 4b3b ldr r3, [pc, #236] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80012f4: 681b ldr r3, [r3, #0]
80012f6: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80012fa: 687b ldr r3, [r7, #4]
80012fc: 691b ldr r3, [r3, #16]
80012fe: 00db lsls r3, r3, #3
8001300: 4937 ldr r1, [pc, #220] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
8001302: 4313 orrs r3, r2
8001304: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001306: e03a b.n 800137e <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
8001308: 687b ldr r3, [r7, #4]
800130a: 68db ldr r3, [r3, #12]
800130c: 2b00 cmp r3, #0
800130e: d020 beq.n 8001352 <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8001310: 4b34 ldr r3, [pc, #208] ; (80013e4 <HAL_RCC_OscConfig+0x244>)
8001312: 2201 movs r2, #1
8001314: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001316: f7ff fc9f bl 8000c58 <HAL_GetTick>
800131a: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800131c: e008 b.n 8001330 <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800131e: f7ff fc9b bl 8000c58 <HAL_GetTick>
8001322: 4602 mov r2, r0
8001324: 693b ldr r3, [r7, #16]
8001326: 1ad3 subs r3, r2, r3
8001328: 2b02 cmp r3, #2
800132a: d901 bls.n 8001330 <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
800132c: 2303 movs r3, #3
800132e: e1a8 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001330: 4b2b ldr r3, [pc, #172] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
8001332: 681b ldr r3, [r3, #0]
8001334: f003 0302 and.w r3, r3, #2
8001338: 2b00 cmp r3, #0
800133a: d0f0 beq.n 800131e <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800133c: 4b28 ldr r3, [pc, #160] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
800133e: 681b ldr r3, [r3, #0]
8001340: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8001344: 687b ldr r3, [r7, #4]
8001346: 691b ldr r3, [r3, #16]
8001348: 00db lsls r3, r3, #3
800134a: 4925 ldr r1, [pc, #148] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
800134c: 4313 orrs r3, r2
800134e: 600b str r3, [r1, #0]
8001350: e015 b.n 800137e <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001352: 4b24 ldr r3, [pc, #144] ; (80013e4 <HAL_RCC_OscConfig+0x244>)
8001354: 2200 movs r2, #0
8001356: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001358: f7ff fc7e bl 8000c58 <HAL_GetTick>
800135c: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800135e: e008 b.n 8001372 <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001360: f7ff fc7a bl 8000c58 <HAL_GetTick>
8001364: 4602 mov r2, r0
8001366: 693b ldr r3, [r7, #16]
8001368: 1ad3 subs r3, r2, r3
800136a: 2b02 cmp r3, #2
800136c: d901 bls.n 8001372 <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
800136e: 2303 movs r3, #3
8001370: e187 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001372: 4b1b ldr r3, [pc, #108] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
8001374: 681b ldr r3, [r3, #0]
8001376: f003 0302 and.w r3, r3, #2
800137a: 2b00 cmp r3, #0
800137c: d1f0 bne.n 8001360 <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800137e: 687b ldr r3, [r7, #4]
8001380: 681b ldr r3, [r3, #0]
8001382: f003 0308 and.w r3, r3, #8
8001386: 2b00 cmp r3, #0
8001388: d036 beq.n 80013f8 <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
800138a: 687b ldr r3, [r7, #4]
800138c: 695b ldr r3, [r3, #20]
800138e: 2b00 cmp r3, #0
8001390: d016 beq.n 80013c0 <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001392: 4b15 ldr r3, [pc, #84] ; (80013e8 <HAL_RCC_OscConfig+0x248>)
8001394: 2201 movs r2, #1
8001396: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001398: f7ff fc5e bl 8000c58 <HAL_GetTick>
800139c: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
800139e: e008 b.n 80013b2 <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80013a0: f7ff fc5a bl 8000c58 <HAL_GetTick>
80013a4: 4602 mov r2, r0
80013a6: 693b ldr r3, [r7, #16]
80013a8: 1ad3 subs r3, r2, r3
80013aa: 2b02 cmp r3, #2
80013ac: d901 bls.n 80013b2 <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
80013ae: 2303 movs r3, #3
80013b0: e167 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80013b2: 4b0b ldr r3, [pc, #44] ; (80013e0 <HAL_RCC_OscConfig+0x240>)
80013b4: 6f5b ldr r3, [r3, #116] ; 0x74
80013b6: f003 0302 and.w r3, r3, #2
80013ba: 2b00 cmp r3, #0
80013bc: d0f0 beq.n 80013a0 <HAL_RCC_OscConfig+0x200>
80013be: e01b b.n 80013f8 <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80013c0: 4b09 ldr r3, [pc, #36] ; (80013e8 <HAL_RCC_OscConfig+0x248>)
80013c2: 2200 movs r2, #0
80013c4: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80013c6: f7ff fc47 bl 8000c58 <HAL_GetTick>
80013ca: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80013cc: e00e b.n 80013ec <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80013ce: f7ff fc43 bl 8000c58 <HAL_GetTick>
80013d2: 4602 mov r2, r0
80013d4: 693b ldr r3, [r7, #16]
80013d6: 1ad3 subs r3, r2, r3
80013d8: 2b02 cmp r3, #2
80013da: d907 bls.n 80013ec <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
80013dc: 2303 movs r3, #3
80013de: e150 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
80013e0: 40023800 .word 0x40023800
80013e4: 42470000 .word 0x42470000
80013e8: 42470e80 .word 0x42470e80
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80013ec: 4b88 ldr r3, [pc, #544] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80013ee: 6f5b ldr r3, [r3, #116] ; 0x74
80013f0: f003 0302 and.w r3, r3, #2
80013f4: 2b00 cmp r3, #0
80013f6: d1ea bne.n 80013ce <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80013f8: 687b ldr r3, [r7, #4]
80013fa: 681b ldr r3, [r3, #0]
80013fc: f003 0304 and.w r3, r3, #4
8001400: 2b00 cmp r3, #0
8001402: f000 8097 beq.w 8001534 <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
8001406: 2300 movs r3, #0
8001408: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
800140a: 4b81 ldr r3, [pc, #516] ; (8001610 <HAL_RCC_OscConfig+0x470>)
800140c: 6c1b ldr r3, [r3, #64] ; 0x40
800140e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001412: 2b00 cmp r3, #0
8001414: d10f bne.n 8001436 <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001416: 2300 movs r3, #0
8001418: 60bb str r3, [r7, #8]
800141a: 4b7d ldr r3, [pc, #500] ; (8001610 <HAL_RCC_OscConfig+0x470>)
800141c: 6c1b ldr r3, [r3, #64] ; 0x40
800141e: 4a7c ldr r2, [pc, #496] ; (8001610 <HAL_RCC_OscConfig+0x470>)
8001420: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001424: 6413 str r3, [r2, #64] ; 0x40
8001426: 4b7a ldr r3, [pc, #488] ; (8001610 <HAL_RCC_OscConfig+0x470>)
8001428: 6c1b ldr r3, [r3, #64] ; 0x40
800142a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800142e: 60bb str r3, [r7, #8]
8001430: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001432: 2301 movs r3, #1
8001434: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001436: 4b77 ldr r3, [pc, #476] ; (8001614 <HAL_RCC_OscConfig+0x474>)
8001438: 681b ldr r3, [r3, #0]
800143a: f403 7380 and.w r3, r3, #256 ; 0x100
800143e: 2b00 cmp r3, #0
8001440: d118 bne.n 8001474 <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001442: 4b74 ldr r3, [pc, #464] ; (8001614 <HAL_RCC_OscConfig+0x474>)
8001444: 681b ldr r3, [r3, #0]
8001446: 4a73 ldr r2, [pc, #460] ; (8001614 <HAL_RCC_OscConfig+0x474>)
8001448: f443 7380 orr.w r3, r3, #256 ; 0x100
800144c: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800144e: f7ff fc03 bl 8000c58 <HAL_GetTick>
8001452: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001454: e008 b.n 8001468 <HAL_RCC_OscConfig+0x2c8>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001456: f7ff fbff bl 8000c58 <HAL_GetTick>
800145a: 4602 mov r2, r0
800145c: 693b ldr r3, [r7, #16]
800145e: 1ad3 subs r3, r2, r3
8001460: 2b02 cmp r3, #2
8001462: d901 bls.n 8001468 <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
8001464: 2303 movs r3, #3
8001466: e10c b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001468: 4b6a ldr r3, [pc, #424] ; (8001614 <HAL_RCC_OscConfig+0x474>)
800146a: 681b ldr r3, [r3, #0]
800146c: f403 7380 and.w r3, r3, #256 ; 0x100
8001470: 2b00 cmp r3, #0
8001472: d0f0 beq.n 8001456 <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001474: 687b ldr r3, [r7, #4]
8001476: 689b ldr r3, [r3, #8]
8001478: 2b01 cmp r3, #1
800147a: d106 bne.n 800148a <HAL_RCC_OscConfig+0x2ea>
800147c: 4b64 ldr r3, [pc, #400] ; (8001610 <HAL_RCC_OscConfig+0x470>)
800147e: 6f1b ldr r3, [r3, #112] ; 0x70
8001480: 4a63 ldr r2, [pc, #396] ; (8001610 <HAL_RCC_OscConfig+0x470>)
8001482: f043 0301 orr.w r3, r3, #1
8001486: 6713 str r3, [r2, #112] ; 0x70
8001488: e01c b.n 80014c4 <HAL_RCC_OscConfig+0x324>
800148a: 687b ldr r3, [r7, #4]
800148c: 689b ldr r3, [r3, #8]
800148e: 2b05 cmp r3, #5
8001490: d10c bne.n 80014ac <HAL_RCC_OscConfig+0x30c>
8001492: 4b5f ldr r3, [pc, #380] ; (8001610 <HAL_RCC_OscConfig+0x470>)
8001494: 6f1b ldr r3, [r3, #112] ; 0x70
8001496: 4a5e ldr r2, [pc, #376] ; (8001610 <HAL_RCC_OscConfig+0x470>)
8001498: f043 0304 orr.w r3, r3, #4
800149c: 6713 str r3, [r2, #112] ; 0x70
800149e: 4b5c ldr r3, [pc, #368] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80014a0: 6f1b ldr r3, [r3, #112] ; 0x70
80014a2: 4a5b ldr r2, [pc, #364] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80014a4: f043 0301 orr.w r3, r3, #1
80014a8: 6713 str r3, [r2, #112] ; 0x70
80014aa: e00b b.n 80014c4 <HAL_RCC_OscConfig+0x324>
80014ac: 4b58 ldr r3, [pc, #352] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80014ae: 6f1b ldr r3, [r3, #112] ; 0x70
80014b0: 4a57 ldr r2, [pc, #348] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80014b2: f023 0301 bic.w r3, r3, #1
80014b6: 6713 str r3, [r2, #112] ; 0x70
80014b8: 4b55 ldr r3, [pc, #340] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80014ba: 6f1b ldr r3, [r3, #112] ; 0x70
80014bc: 4a54 ldr r2, [pc, #336] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80014be: f023 0304 bic.w r3, r3, #4
80014c2: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
80014c4: 687b ldr r3, [r7, #4]
80014c6: 689b ldr r3, [r3, #8]
80014c8: 2b00 cmp r3, #0
80014ca: d015 beq.n 80014f8 <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80014cc: f7ff fbc4 bl 8000c58 <HAL_GetTick>
80014d0: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80014d2: e00a b.n 80014ea <HAL_RCC_OscConfig+0x34a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80014d4: f7ff fbc0 bl 8000c58 <HAL_GetTick>
80014d8: 4602 mov r2, r0
80014da: 693b ldr r3, [r7, #16]
80014dc: 1ad3 subs r3, r2, r3
80014de: f241 3288 movw r2, #5000 ; 0x1388
80014e2: 4293 cmp r3, r2
80014e4: d901 bls.n 80014ea <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
80014e6: 2303 movs r3, #3
80014e8: e0cb b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80014ea: 4b49 ldr r3, [pc, #292] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80014ec: 6f1b ldr r3, [r3, #112] ; 0x70
80014ee: f003 0302 and.w r3, r3, #2
80014f2: 2b00 cmp r3, #0
80014f4: d0ee beq.n 80014d4 <HAL_RCC_OscConfig+0x334>
80014f6: e014 b.n 8001522 <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80014f8: f7ff fbae bl 8000c58 <HAL_GetTick>
80014fc: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80014fe: e00a b.n 8001516 <HAL_RCC_OscConfig+0x376>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8001500: f7ff fbaa bl 8000c58 <HAL_GetTick>
8001504: 4602 mov r2, r0
8001506: 693b ldr r3, [r7, #16]
8001508: 1ad3 subs r3, r2, r3
800150a: f241 3288 movw r2, #5000 ; 0x1388
800150e: 4293 cmp r3, r2
8001510: d901 bls.n 8001516 <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
8001512: 2303 movs r3, #3
8001514: e0b5 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001516: 4b3e ldr r3, [pc, #248] ; (8001610 <HAL_RCC_OscConfig+0x470>)
8001518: 6f1b ldr r3, [r3, #112] ; 0x70
800151a: f003 0302 and.w r3, r3, #2
800151e: 2b00 cmp r3, #0
8001520: d1ee bne.n 8001500 <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8001522: 7dfb ldrb r3, [r7, #23]
8001524: 2b01 cmp r3, #1
8001526: d105 bne.n 8001534 <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001528: 4b39 ldr r3, [pc, #228] ; (8001610 <HAL_RCC_OscConfig+0x470>)
800152a: 6c1b ldr r3, [r3, #64] ; 0x40
800152c: 4a38 ldr r2, [pc, #224] ; (8001610 <HAL_RCC_OscConfig+0x470>)
800152e: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8001532: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001534: 687b ldr r3, [r7, #4]
8001536: 699b ldr r3, [r3, #24]
8001538: 2b00 cmp r3, #0
800153a: f000 80a1 beq.w 8001680 <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
800153e: 4b34 ldr r3, [pc, #208] ; (8001610 <HAL_RCC_OscConfig+0x470>)
8001540: 689b ldr r3, [r3, #8]
8001542: f003 030c and.w r3, r3, #12
8001546: 2b08 cmp r3, #8
8001548: d05c beq.n 8001604 <HAL_RCC_OscConfig+0x464>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
800154a: 687b ldr r3, [r7, #4]
800154c: 699b ldr r3, [r3, #24]
800154e: 2b02 cmp r3, #2
8001550: d141 bne.n 80015d6 <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001552: 4b31 ldr r3, [pc, #196] ; (8001618 <HAL_RCC_OscConfig+0x478>)
8001554: 2200 movs r2, #0
8001556: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001558: f7ff fb7e bl 8000c58 <HAL_GetTick>
800155c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800155e: e008 b.n 8001572 <HAL_RCC_OscConfig+0x3d2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001560: f7ff fb7a bl 8000c58 <HAL_GetTick>
8001564: 4602 mov r2, r0
8001566: 693b ldr r3, [r7, #16]
8001568: 1ad3 subs r3, r2, r3
800156a: 2b02 cmp r3, #2
800156c: d901 bls.n 8001572 <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
800156e: 2303 movs r3, #3
8001570: e087 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001572: 4b27 ldr r3, [pc, #156] ; (8001610 <HAL_RCC_OscConfig+0x470>)
8001574: 681b ldr r3, [r3, #0]
8001576: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800157a: 2b00 cmp r3, #0
800157c: d1f0 bne.n 8001560 <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
800157e: 687b ldr r3, [r7, #4]
8001580: 69da ldr r2, [r3, #28]
8001582: 687b ldr r3, [r7, #4]
8001584: 6a1b ldr r3, [r3, #32]
8001586: 431a orrs r2, r3
8001588: 687b ldr r3, [r7, #4]
800158a: 6a5b ldr r3, [r3, #36] ; 0x24
800158c: 019b lsls r3, r3, #6
800158e: 431a orrs r2, r3
8001590: 687b ldr r3, [r7, #4]
8001592: 6a9b ldr r3, [r3, #40] ; 0x28
8001594: 085b lsrs r3, r3, #1
8001596: 3b01 subs r3, #1
8001598: 041b lsls r3, r3, #16
800159a: 431a orrs r2, r3
800159c: 687b ldr r3, [r7, #4]
800159e: 6adb ldr r3, [r3, #44] ; 0x2c
80015a0: 061b lsls r3, r3, #24
80015a2: 491b ldr r1, [pc, #108] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80015a4: 4313 orrs r3, r2
80015a6: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80015a8: 4b1b ldr r3, [pc, #108] ; (8001618 <HAL_RCC_OscConfig+0x478>)
80015aa: 2201 movs r2, #1
80015ac: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80015ae: f7ff fb53 bl 8000c58 <HAL_GetTick>
80015b2: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80015b4: e008 b.n 80015c8 <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80015b6: f7ff fb4f bl 8000c58 <HAL_GetTick>
80015ba: 4602 mov r2, r0
80015bc: 693b ldr r3, [r7, #16]
80015be: 1ad3 subs r3, r2, r3
80015c0: 2b02 cmp r3, #2
80015c2: d901 bls.n 80015c8 <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
80015c4: 2303 movs r3, #3
80015c6: e05c b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80015c8: 4b11 ldr r3, [pc, #68] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80015ca: 681b ldr r3, [r3, #0]
80015cc: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80015d0: 2b00 cmp r3, #0
80015d2: d0f0 beq.n 80015b6 <HAL_RCC_OscConfig+0x416>
80015d4: e054 b.n 8001680 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80015d6: 4b10 ldr r3, [pc, #64] ; (8001618 <HAL_RCC_OscConfig+0x478>)
80015d8: 2200 movs r2, #0
80015da: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80015dc: f7ff fb3c bl 8000c58 <HAL_GetTick>
80015e0: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80015e2: e008 b.n 80015f6 <HAL_RCC_OscConfig+0x456>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80015e4: f7ff fb38 bl 8000c58 <HAL_GetTick>
80015e8: 4602 mov r2, r0
80015ea: 693b ldr r3, [r7, #16]
80015ec: 1ad3 subs r3, r2, r3
80015ee: 2b02 cmp r3, #2
80015f0: d901 bls.n 80015f6 <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
80015f2: 2303 movs r3, #3
80015f4: e045 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80015f6: 4b06 ldr r3, [pc, #24] ; (8001610 <HAL_RCC_OscConfig+0x470>)
80015f8: 681b ldr r3, [r3, #0]
80015fa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80015fe: 2b00 cmp r3, #0
8001600: d1f0 bne.n 80015e4 <HAL_RCC_OscConfig+0x444>
8001602: e03d b.n 8001680 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001604: 687b ldr r3, [r7, #4]
8001606: 699b ldr r3, [r3, #24]
8001608: 2b01 cmp r3, #1
800160a: d107 bne.n 800161c <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
800160c: 2301 movs r3, #1
800160e: e038 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
8001610: 40023800 .word 0x40023800
8001614: 40007000 .word 0x40007000
8001618: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
800161c: 4b1b ldr r3, [pc, #108] ; (800168c <HAL_RCC_OscConfig+0x4ec>)
800161e: 685b ldr r3, [r3, #4]
8001620: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001622: 687b ldr r3, [r7, #4]
8001624: 699b ldr r3, [r3, #24]
8001626: 2b01 cmp r3, #1
8001628: d028 beq.n 800167c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800162a: 68fb ldr r3, [r7, #12]
800162c: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8001630: 687b ldr r3, [r7, #4]
8001632: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001634: 429a cmp r2, r3
8001636: d121 bne.n 800167c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001638: 68fb ldr r3, [r7, #12]
800163a: f003 023f and.w r2, r3, #63 ; 0x3f
800163e: 687b ldr r3, [r7, #4]
8001640: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001642: 429a cmp r2, r3
8001644: d11a bne.n 800167c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8001646: 68fa ldr r2, [r7, #12]
8001648: f647 73c0 movw r3, #32704 ; 0x7fc0
800164c: 4013 ands r3, r2
800164e: 687a ldr r2, [r7, #4]
8001650: 6a52 ldr r2, [r2, #36] ; 0x24
8001652: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001654: 4293 cmp r3, r2
8001656: d111 bne.n 800167c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8001658: 68fb ldr r3, [r7, #12]
800165a: f403 3240 and.w r2, r3, #196608 ; 0x30000
800165e: 687b ldr r3, [r7, #4]
8001660: 6a9b ldr r3, [r3, #40] ; 0x28
8001662: 085b lsrs r3, r3, #1
8001664: 3b01 subs r3, #1
8001666: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8001668: 429a cmp r2, r3
800166a: d107 bne.n 800167c <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
800166c: 68fb ldr r3, [r7, #12]
800166e: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8001672: 687b ldr r3, [r7, #4]
8001674: 6adb ldr r3, [r3, #44] ; 0x2c
8001676: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8001678: 429a cmp r2, r3
800167a: d001 beq.n 8001680 <HAL_RCC_OscConfig+0x4e0>
#endif
{
return HAL_ERROR;
800167c: 2301 movs r3, #1
800167e: e000 b.n 8001682 <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
8001680: 2300 movs r3, #0
}
8001682: 4618 mov r0, r3
8001684: 3718 adds r7, #24
8001686: 46bd mov sp, r7
8001688: bd80 pop {r7, pc}
800168a: bf00 nop
800168c: 40023800 .word 0x40023800
08001690 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001690: b580 push {r7, lr}
8001692: b084 sub sp, #16
8001694: af00 add r7, sp, #0
8001696: 6078 str r0, [r7, #4]
8001698: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
800169a: 687b ldr r3, [r7, #4]
800169c: 2b00 cmp r3, #0
800169e: d101 bne.n 80016a4 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80016a0: 2301 movs r3, #1
80016a2: e0cc b.n 800183e <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80016a4: 4b68 ldr r3, [pc, #416] ; (8001848 <HAL_RCC_ClockConfig+0x1b8>)
80016a6: 681b ldr r3, [r3, #0]
80016a8: f003 0307 and.w r3, r3, #7
80016ac: 683a ldr r2, [r7, #0]
80016ae: 429a cmp r2, r3
80016b0: d90c bls.n 80016cc <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80016b2: 4b65 ldr r3, [pc, #404] ; (8001848 <HAL_RCC_ClockConfig+0x1b8>)
80016b4: 683a ldr r2, [r7, #0]
80016b6: b2d2 uxtb r2, r2
80016b8: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80016ba: 4b63 ldr r3, [pc, #396] ; (8001848 <HAL_RCC_ClockConfig+0x1b8>)
80016bc: 681b ldr r3, [r3, #0]
80016be: f003 0307 and.w r3, r3, #7
80016c2: 683a ldr r2, [r7, #0]
80016c4: 429a cmp r2, r3
80016c6: d001 beq.n 80016cc <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
80016c8: 2301 movs r3, #1
80016ca: e0b8 b.n 800183e <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80016cc: 687b ldr r3, [r7, #4]
80016ce: 681b ldr r3, [r3, #0]
80016d0: f003 0302 and.w r3, r3, #2
80016d4: 2b00 cmp r3, #0
80016d6: d020 beq.n 800171a <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80016d8: 687b ldr r3, [r7, #4]
80016da: 681b ldr r3, [r3, #0]
80016dc: f003 0304 and.w r3, r3, #4
80016e0: 2b00 cmp r3, #0
80016e2: d005 beq.n 80016f0 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80016e4: 4b59 ldr r3, [pc, #356] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
80016e6: 689b ldr r3, [r3, #8]
80016e8: 4a58 ldr r2, [pc, #352] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
80016ea: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
80016ee: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80016f0: 687b ldr r3, [r7, #4]
80016f2: 681b ldr r3, [r3, #0]
80016f4: f003 0308 and.w r3, r3, #8
80016f8: 2b00 cmp r3, #0
80016fa: d005 beq.n 8001708 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80016fc: 4b53 ldr r3, [pc, #332] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
80016fe: 689b ldr r3, [r3, #8]
8001700: 4a52 ldr r2, [pc, #328] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
8001702: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8001706: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001708: 4b50 ldr r3, [pc, #320] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
800170a: 689b ldr r3, [r3, #8]
800170c: f023 02f0 bic.w r2, r3, #240 ; 0xf0
8001710: 687b ldr r3, [r7, #4]
8001712: 689b ldr r3, [r3, #8]
8001714: 494d ldr r1, [pc, #308] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
8001716: 4313 orrs r3, r2
8001718: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
800171a: 687b ldr r3, [r7, #4]
800171c: 681b ldr r3, [r3, #0]
800171e: f003 0301 and.w r3, r3, #1
8001722: 2b00 cmp r3, #0
8001724: d044 beq.n 80017b0 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001726: 687b ldr r3, [r7, #4]
8001728: 685b ldr r3, [r3, #4]
800172a: 2b01 cmp r3, #1
800172c: d107 bne.n 800173e <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800172e: 4b47 ldr r3, [pc, #284] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
8001730: 681b ldr r3, [r3, #0]
8001732: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001736: 2b00 cmp r3, #0
8001738: d119 bne.n 800176e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800173a: 2301 movs r3, #1
800173c: e07f b.n 800183e <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
800173e: 687b ldr r3, [r7, #4]
8001740: 685b ldr r3, [r3, #4]
8001742: 2b02 cmp r3, #2
8001744: d003 beq.n 800174e <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
8001746: 687b ldr r3, [r7, #4]
8001748: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
800174a: 2b03 cmp r3, #3
800174c: d107 bne.n 800175e <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800174e: 4b3f ldr r3, [pc, #252] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
8001750: 681b ldr r3, [r3, #0]
8001752: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001756: 2b00 cmp r3, #0
8001758: d109 bne.n 800176e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800175a: 2301 movs r3, #1
800175c: e06f b.n 800183e <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800175e: 4b3b ldr r3, [pc, #236] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
8001760: 681b ldr r3, [r3, #0]
8001762: f003 0302 and.w r3, r3, #2
8001766: 2b00 cmp r3, #0
8001768: d101 bne.n 800176e <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800176a: 2301 movs r3, #1
800176c: e067 b.n 800183e <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800176e: 4b37 ldr r3, [pc, #220] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
8001770: 689b ldr r3, [r3, #8]
8001772: f023 0203 bic.w r2, r3, #3
8001776: 687b ldr r3, [r7, #4]
8001778: 685b ldr r3, [r3, #4]
800177a: 4934 ldr r1, [pc, #208] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
800177c: 4313 orrs r3, r2
800177e: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001780: f7ff fa6a bl 8000c58 <HAL_GetTick>
8001784: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001786: e00a b.n 800179e <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8001788: f7ff fa66 bl 8000c58 <HAL_GetTick>
800178c: 4602 mov r2, r0
800178e: 68fb ldr r3, [r7, #12]
8001790: 1ad3 subs r3, r2, r3
8001792: f241 3288 movw r2, #5000 ; 0x1388
8001796: 4293 cmp r3, r2
8001798: d901 bls.n 800179e <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
800179a: 2303 movs r3, #3
800179c: e04f b.n 800183e <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800179e: 4b2b ldr r3, [pc, #172] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
80017a0: 689b ldr r3, [r3, #8]
80017a2: f003 020c and.w r2, r3, #12
80017a6: 687b ldr r3, [r7, #4]
80017a8: 685b ldr r3, [r3, #4]
80017aa: 009b lsls r3, r3, #2
80017ac: 429a cmp r2, r3
80017ae: d1eb bne.n 8001788 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80017b0: 4b25 ldr r3, [pc, #148] ; (8001848 <HAL_RCC_ClockConfig+0x1b8>)
80017b2: 681b ldr r3, [r3, #0]
80017b4: f003 0307 and.w r3, r3, #7
80017b8: 683a ldr r2, [r7, #0]
80017ba: 429a cmp r2, r3
80017bc: d20c bcs.n 80017d8 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80017be: 4b22 ldr r3, [pc, #136] ; (8001848 <HAL_RCC_ClockConfig+0x1b8>)
80017c0: 683a ldr r2, [r7, #0]
80017c2: b2d2 uxtb r2, r2
80017c4: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80017c6: 4b20 ldr r3, [pc, #128] ; (8001848 <HAL_RCC_ClockConfig+0x1b8>)
80017c8: 681b ldr r3, [r3, #0]
80017ca: f003 0307 and.w r3, r3, #7
80017ce: 683a ldr r2, [r7, #0]
80017d0: 429a cmp r2, r3
80017d2: d001 beq.n 80017d8 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
80017d4: 2301 movs r3, #1
80017d6: e032 b.n 800183e <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80017d8: 687b ldr r3, [r7, #4]
80017da: 681b ldr r3, [r3, #0]
80017dc: f003 0304 and.w r3, r3, #4
80017e0: 2b00 cmp r3, #0
80017e2: d008 beq.n 80017f6 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80017e4: 4b19 ldr r3, [pc, #100] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
80017e6: 689b ldr r3, [r3, #8]
80017e8: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
80017ec: 687b ldr r3, [r7, #4]
80017ee: 68db ldr r3, [r3, #12]
80017f0: 4916 ldr r1, [pc, #88] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
80017f2: 4313 orrs r3, r2
80017f4: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80017f6: 687b ldr r3, [r7, #4]
80017f8: 681b ldr r3, [r3, #0]
80017fa: f003 0308 and.w r3, r3, #8
80017fe: 2b00 cmp r3, #0
8001800: d009 beq.n 8001816 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8001802: 4b12 ldr r3, [pc, #72] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
8001804: 689b ldr r3, [r3, #8]
8001806: f423 4260 bic.w r2, r3, #57344 ; 0xe000
800180a: 687b ldr r3, [r7, #4]
800180c: 691b ldr r3, [r3, #16]
800180e: 00db lsls r3, r3, #3
8001810: 490e ldr r1, [pc, #56] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
8001812: 4313 orrs r3, r2
8001814: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8001816: f000 f821 bl 800185c <HAL_RCC_GetSysClockFreq>
800181a: 4602 mov r2, r0
800181c: 4b0b ldr r3, [pc, #44] ; (800184c <HAL_RCC_ClockConfig+0x1bc>)
800181e: 689b ldr r3, [r3, #8]
8001820: 091b lsrs r3, r3, #4
8001822: f003 030f and.w r3, r3, #15
8001826: 490a ldr r1, [pc, #40] ; (8001850 <HAL_RCC_ClockConfig+0x1c0>)
8001828: 5ccb ldrb r3, [r1, r3]
800182a: fa22 f303 lsr.w r3, r2, r3
800182e: 4a09 ldr r2, [pc, #36] ; (8001854 <HAL_RCC_ClockConfig+0x1c4>)
8001830: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
8001832: 4b09 ldr r3, [pc, #36] ; (8001858 <HAL_RCC_ClockConfig+0x1c8>)
8001834: 681b ldr r3, [r3, #0]
8001836: 4618 mov r0, r3
8001838: f7ff f90a bl 8000a50 <HAL_InitTick>
return HAL_OK;
800183c: 2300 movs r3, #0
}
800183e: 4618 mov r0, r3
8001840: 3710 adds r7, #16
8001842: 46bd mov sp, r7
8001844: bd80 pop {r7, pc}
8001846: bf00 nop
8001848: 40023c00 .word 0x40023c00
800184c: 40023800 .word 0x40023800
8001850: 080056a0 .word 0x080056a0
8001854: 20000000 .word 0x20000000
8001858: 20000004 .word 0x20000004
0800185c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
800185c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001860: b094 sub sp, #80 ; 0x50
8001862: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
8001864: 2300 movs r3, #0
8001866: 647b str r3, [r7, #68] ; 0x44
8001868: 2300 movs r3, #0
800186a: 64fb str r3, [r7, #76] ; 0x4c
800186c: 2300 movs r3, #0
800186e: 643b str r3, [r7, #64] ; 0x40
uint32_t sysclockfreq = 0U;
8001870: 2300 movs r3, #0
8001872: 64bb str r3, [r7, #72] ; 0x48
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8001874: 4b79 ldr r3, [pc, #484] ; (8001a5c <HAL_RCC_GetSysClockFreq+0x200>)
8001876: 689b ldr r3, [r3, #8]
8001878: f003 030c and.w r3, r3, #12
800187c: 2b08 cmp r3, #8
800187e: d00d beq.n 800189c <HAL_RCC_GetSysClockFreq+0x40>
8001880: 2b08 cmp r3, #8
8001882: f200 80e1 bhi.w 8001a48 <HAL_RCC_GetSysClockFreq+0x1ec>
8001886: 2b00 cmp r3, #0
8001888: d002 beq.n 8001890 <HAL_RCC_GetSysClockFreq+0x34>
800188a: 2b04 cmp r3, #4
800188c: d003 beq.n 8001896 <HAL_RCC_GetSysClockFreq+0x3a>
800188e: e0db b.n 8001a48 <HAL_RCC_GetSysClockFreq+0x1ec>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001890: 4b73 ldr r3, [pc, #460] ; (8001a60 <HAL_RCC_GetSysClockFreq+0x204>)
8001892: 64bb str r3, [r7, #72] ; 0x48
break;
8001894: e0db b.n 8001a4e <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
8001896: 4b73 ldr r3, [pc, #460] ; (8001a64 <HAL_RCC_GetSysClockFreq+0x208>)
8001898: 64bb str r3, [r7, #72] ; 0x48
break;
800189a: e0d8 b.n 8001a4e <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
800189c: 4b6f ldr r3, [pc, #444] ; (8001a5c <HAL_RCC_GetSysClockFreq+0x200>)
800189e: 685b ldr r3, [r3, #4]
80018a0: f003 033f and.w r3, r3, #63 ; 0x3f
80018a4: 647b str r3, [r7, #68] ; 0x44
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
80018a6: 4b6d ldr r3, [pc, #436] ; (8001a5c <HAL_RCC_GetSysClockFreq+0x200>)
80018a8: 685b ldr r3, [r3, #4]
80018aa: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80018ae: 2b00 cmp r3, #0
80018b0: d063 beq.n 800197a <HAL_RCC_GetSysClockFreq+0x11e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
80018b2: 4b6a ldr r3, [pc, #424] ; (8001a5c <HAL_RCC_GetSysClockFreq+0x200>)
80018b4: 685b ldr r3, [r3, #4]
80018b6: 099b lsrs r3, r3, #6
80018b8: 2200 movs r2, #0
80018ba: 63bb str r3, [r7, #56] ; 0x38
80018bc: 63fa str r2, [r7, #60] ; 0x3c
80018be: 6bbb ldr r3, [r7, #56] ; 0x38
80018c0: f3c3 0308 ubfx r3, r3, #0, #9
80018c4: 633b str r3, [r7, #48] ; 0x30
80018c6: 2300 movs r3, #0
80018c8: 637b str r3, [r7, #52] ; 0x34
80018ca: e9d7 450c ldrd r4, r5, [r7, #48] ; 0x30
80018ce: 4622 mov r2, r4
80018d0: 462b mov r3, r5
80018d2: f04f 0000 mov.w r0, #0
80018d6: f04f 0100 mov.w r1, #0
80018da: 0159 lsls r1, r3, #5
80018dc: ea41 61d2 orr.w r1, r1, r2, lsr #27
80018e0: 0150 lsls r0, r2, #5
80018e2: 4602 mov r2, r0
80018e4: 460b mov r3, r1
80018e6: 4621 mov r1, r4
80018e8: 1a51 subs r1, r2, r1
80018ea: 6139 str r1, [r7, #16]
80018ec: 4629 mov r1, r5
80018ee: eb63 0301 sbc.w r3, r3, r1
80018f2: 617b str r3, [r7, #20]
80018f4: f04f 0200 mov.w r2, #0
80018f8: f04f 0300 mov.w r3, #0
80018fc: e9d7 ab04 ldrd sl, fp, [r7, #16]
8001900: 4659 mov r1, fp
8001902: 018b lsls r3, r1, #6
8001904: 4651 mov r1, sl
8001906: ea43 6391 orr.w r3, r3, r1, lsr #26
800190a: 4651 mov r1, sl
800190c: 018a lsls r2, r1, #6
800190e: 4651 mov r1, sl
8001910: ebb2 0801 subs.w r8, r2, r1
8001914: 4659 mov r1, fp
8001916: eb63 0901 sbc.w r9, r3, r1
800191a: f04f 0200 mov.w r2, #0
800191e: f04f 0300 mov.w r3, #0
8001922: ea4f 03c9 mov.w r3, r9, lsl #3
8001926: ea43 7358 orr.w r3, r3, r8, lsr #29
800192a: ea4f 02c8 mov.w r2, r8, lsl #3
800192e: 4690 mov r8, r2
8001930: 4699 mov r9, r3
8001932: 4623 mov r3, r4
8001934: eb18 0303 adds.w r3, r8, r3
8001938: 60bb str r3, [r7, #8]
800193a: 462b mov r3, r5
800193c: eb49 0303 adc.w r3, r9, r3
8001940: 60fb str r3, [r7, #12]
8001942: f04f 0200 mov.w r2, #0
8001946: f04f 0300 mov.w r3, #0
800194a: e9d7 4502 ldrd r4, r5, [r7, #8]
800194e: 4629 mov r1, r5
8001950: 024b lsls r3, r1, #9
8001952: 4621 mov r1, r4
8001954: ea43 53d1 orr.w r3, r3, r1, lsr #23
8001958: 4621 mov r1, r4
800195a: 024a lsls r2, r1, #9
800195c: 4610 mov r0, r2
800195e: 4619 mov r1, r3
8001960: 6c7b ldr r3, [r7, #68] ; 0x44
8001962: 2200 movs r2, #0
8001964: 62bb str r3, [r7, #40] ; 0x28
8001966: 62fa str r2, [r7, #44] ; 0x2c
8001968: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
800196c: f7fe fc38 bl 80001e0 <__aeabi_uldivmod>
8001970: 4602 mov r2, r0
8001972: 460b mov r3, r1
8001974: 4613 mov r3, r2
8001976: 64fb str r3, [r7, #76] ; 0x4c
8001978: e058 b.n 8001a2c <HAL_RCC_GetSysClockFreq+0x1d0>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
800197a: 4b38 ldr r3, [pc, #224] ; (8001a5c <HAL_RCC_GetSysClockFreq+0x200>)
800197c: 685b ldr r3, [r3, #4]
800197e: 099b lsrs r3, r3, #6
8001980: 2200 movs r2, #0
8001982: 4618 mov r0, r3
8001984: 4611 mov r1, r2
8001986: f3c0 0308 ubfx r3, r0, #0, #9
800198a: 623b str r3, [r7, #32]
800198c: 2300 movs r3, #0
800198e: 627b str r3, [r7, #36] ; 0x24
8001990: e9d7 8908 ldrd r8, r9, [r7, #32]
8001994: 4642 mov r2, r8
8001996: 464b mov r3, r9
8001998: f04f 0000 mov.w r0, #0
800199c: f04f 0100 mov.w r1, #0
80019a0: 0159 lsls r1, r3, #5
80019a2: ea41 61d2 orr.w r1, r1, r2, lsr #27
80019a6: 0150 lsls r0, r2, #5
80019a8: 4602 mov r2, r0
80019aa: 460b mov r3, r1
80019ac: 4641 mov r1, r8
80019ae: ebb2 0a01 subs.w sl, r2, r1
80019b2: 4649 mov r1, r9
80019b4: eb63 0b01 sbc.w fp, r3, r1
80019b8: f04f 0200 mov.w r2, #0
80019bc: f04f 0300 mov.w r3, #0
80019c0: ea4f 138b mov.w r3, fp, lsl #6
80019c4: ea43 639a orr.w r3, r3, sl, lsr #26
80019c8: ea4f 128a mov.w r2, sl, lsl #6
80019cc: ebb2 040a subs.w r4, r2, sl
80019d0: eb63 050b sbc.w r5, r3, fp
80019d4: f04f 0200 mov.w r2, #0
80019d8: f04f 0300 mov.w r3, #0
80019dc: 00eb lsls r3, r5, #3
80019de: ea43 7354 orr.w r3, r3, r4, lsr #29
80019e2: 00e2 lsls r2, r4, #3
80019e4: 4614 mov r4, r2
80019e6: 461d mov r5, r3
80019e8: 4643 mov r3, r8
80019ea: 18e3 adds r3, r4, r3
80019ec: 603b str r3, [r7, #0]
80019ee: 464b mov r3, r9
80019f0: eb45 0303 adc.w r3, r5, r3
80019f4: 607b str r3, [r7, #4]
80019f6: f04f 0200 mov.w r2, #0
80019fa: f04f 0300 mov.w r3, #0
80019fe: e9d7 4500 ldrd r4, r5, [r7]
8001a02: 4629 mov r1, r5
8001a04: 028b lsls r3, r1, #10
8001a06: 4621 mov r1, r4
8001a08: ea43 5391 orr.w r3, r3, r1, lsr #22
8001a0c: 4621 mov r1, r4
8001a0e: 028a lsls r2, r1, #10
8001a10: 4610 mov r0, r2
8001a12: 4619 mov r1, r3
8001a14: 6c7b ldr r3, [r7, #68] ; 0x44
8001a16: 2200 movs r2, #0
8001a18: 61bb str r3, [r7, #24]
8001a1a: 61fa str r2, [r7, #28]
8001a1c: e9d7 2306 ldrd r2, r3, [r7, #24]
8001a20: f7fe fbde bl 80001e0 <__aeabi_uldivmod>
8001a24: 4602 mov r2, r0
8001a26: 460b mov r3, r1
8001a28: 4613 mov r3, r2
8001a2a: 64fb str r3, [r7, #76] ; 0x4c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
8001a2c: 4b0b ldr r3, [pc, #44] ; (8001a5c <HAL_RCC_GetSysClockFreq+0x200>)
8001a2e: 685b ldr r3, [r3, #4]
8001a30: 0c1b lsrs r3, r3, #16
8001a32: f003 0303 and.w r3, r3, #3
8001a36: 3301 adds r3, #1
8001a38: 005b lsls r3, r3, #1
8001a3a: 643b str r3, [r7, #64] ; 0x40
sysclockfreq = pllvco/pllp;
8001a3c: 6cfa ldr r2, [r7, #76] ; 0x4c
8001a3e: 6c3b ldr r3, [r7, #64] ; 0x40
8001a40: fbb2 f3f3 udiv r3, r2, r3
8001a44: 64bb str r3, [r7, #72] ; 0x48
break;
8001a46: e002 b.n 8001a4e <HAL_RCC_GetSysClockFreq+0x1f2>
}
default:
{
sysclockfreq = HSI_VALUE;
8001a48: 4b05 ldr r3, [pc, #20] ; (8001a60 <HAL_RCC_GetSysClockFreq+0x204>)
8001a4a: 64bb str r3, [r7, #72] ; 0x48
break;
8001a4c: bf00 nop
}
}
return sysclockfreq;
8001a4e: 6cbb ldr r3, [r7, #72] ; 0x48
}
8001a50: 4618 mov r0, r3
8001a52: 3750 adds r7, #80 ; 0x50
8001a54: 46bd mov sp, r7
8001a56: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8001a5a: bf00 nop
8001a5c: 40023800 .word 0x40023800
8001a60: 00f42400 .word 0x00f42400
8001a64: 007a1200 .word 0x007a1200
08001a68 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8001a68: b480 push {r7}
8001a6a: af00 add r7, sp, #0
return SystemCoreClock;
8001a6c: 4b03 ldr r3, [pc, #12] ; (8001a7c <HAL_RCC_GetHCLKFreq+0x14>)
8001a6e: 681b ldr r3, [r3, #0]
}
8001a70: 4618 mov r0, r3
8001a72: 46bd mov sp, r7
8001a74: f85d 7b04 ldr.w r7, [sp], #4
8001a78: 4770 bx lr
8001a7a: bf00 nop
8001a7c: 20000000 .word 0x20000000
08001a80 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8001a80: b580 push {r7, lr}
8001a82: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
8001a84: f7ff fff0 bl 8001a68 <HAL_RCC_GetHCLKFreq>
8001a88: 4602 mov r2, r0
8001a8a: 4b05 ldr r3, [pc, #20] ; (8001aa0 <HAL_RCC_GetPCLK1Freq+0x20>)
8001a8c: 689b ldr r3, [r3, #8]
8001a8e: 0a9b lsrs r3, r3, #10
8001a90: f003 0307 and.w r3, r3, #7
8001a94: 4903 ldr r1, [pc, #12] ; (8001aa4 <HAL_RCC_GetPCLK1Freq+0x24>)
8001a96: 5ccb ldrb r3, [r1, r3]
8001a98: fa22 f303 lsr.w r3, r2, r3
}
8001a9c: 4618 mov r0, r3
8001a9e: bd80 pop {r7, pc}
8001aa0: 40023800 .word 0x40023800
8001aa4: 080056b0 .word 0x080056b0
08001aa8 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8001aa8: b580 push {r7, lr}
8001aaa: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
8001aac: f7ff ffdc bl 8001a68 <HAL_RCC_GetHCLKFreq>
8001ab0: 4602 mov r2, r0
8001ab2: 4b05 ldr r3, [pc, #20] ; (8001ac8 <HAL_RCC_GetPCLK2Freq+0x20>)
8001ab4: 689b ldr r3, [r3, #8]
8001ab6: 0b5b lsrs r3, r3, #13
8001ab8: f003 0307 and.w r3, r3, #7
8001abc: 4903 ldr r1, [pc, #12] ; (8001acc <HAL_RCC_GetPCLK2Freq+0x24>)
8001abe: 5ccb ldrb r3, [r1, r3]
8001ac0: fa22 f303 lsr.w r3, r2, r3
}
8001ac4: 4618 mov r0, r3
8001ac6: bd80 pop {r7, pc}
8001ac8: 40023800 .word 0x40023800
8001acc: 080056b0 .word 0x080056b0
08001ad0 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
8001ad0: b480 push {r7}
8001ad2: b083 sub sp, #12
8001ad4: af00 add r7, sp, #0
8001ad6: 6078 str r0, [r7, #4]
8001ad8: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
8001ada: 687b ldr r3, [r7, #4]
8001adc: 220f movs r2, #15
8001ade: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
8001ae0: 4b12 ldr r3, [pc, #72] ; (8001b2c <HAL_RCC_GetClockConfig+0x5c>)
8001ae2: 689b ldr r3, [r3, #8]
8001ae4: f003 0203 and.w r2, r3, #3
8001ae8: 687b ldr r3, [r7, #4]
8001aea: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
8001aec: 4b0f ldr r3, [pc, #60] ; (8001b2c <HAL_RCC_GetClockConfig+0x5c>)
8001aee: 689b ldr r3, [r3, #8]
8001af0: f003 02f0 and.w r2, r3, #240 ; 0xf0
8001af4: 687b ldr r3, [r7, #4]
8001af6: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8001af8: 4b0c ldr r3, [pc, #48] ; (8001b2c <HAL_RCC_GetClockConfig+0x5c>)
8001afa: 689b ldr r3, [r3, #8]
8001afc: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8001b00: 687b ldr r3, [r7, #4]
8001b02: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
8001b04: 4b09 ldr r3, [pc, #36] ; (8001b2c <HAL_RCC_GetClockConfig+0x5c>)
8001b06: 689b ldr r3, [r3, #8]
8001b08: 08db lsrs r3, r3, #3
8001b0a: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8001b0e: 687b ldr r3, [r7, #4]
8001b10: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
8001b12: 4b07 ldr r3, [pc, #28] ; (8001b30 <HAL_RCC_GetClockConfig+0x60>)
8001b14: 681b ldr r3, [r3, #0]
8001b16: f003 0207 and.w r2, r3, #7
8001b1a: 683b ldr r3, [r7, #0]
8001b1c: 601a str r2, [r3, #0]
}
8001b1e: bf00 nop
8001b20: 370c adds r7, #12
8001b22: 46bd mov sp, r7
8001b24: f85d 7b04 ldr.w r7, [sp], #4
8001b28: 4770 bx lr
8001b2a: bf00 nop
8001b2c: 40023800 .word 0x40023800
8001b30: 40023c00 .word 0x40023c00
08001b34 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8001b34: b580 push {r7, lr}
8001b36: b082 sub sp, #8
8001b38: af00 add r7, sp, #0
8001b3a: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001b3c: 687b ldr r3, [r7, #4]
8001b3e: 2b00 cmp r3, #0
8001b40: d101 bne.n 8001b46 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8001b42: 2301 movs r3, #1
8001b44: e041 b.n 8001bca <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001b46: 687b ldr r3, [r7, #4]
8001b48: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001b4c: b2db uxtb r3, r3
8001b4e: 2b00 cmp r3, #0
8001b50: d106 bne.n 8001b60 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001b52: 687b ldr r3, [r7, #4]
8001b54: 2200 movs r2, #0
8001b56: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8001b5a: 6878 ldr r0, [r7, #4]
8001b5c: f000 f839 bl 8001bd2 <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001b60: 687b ldr r3, [r7, #4]
8001b62: 2202 movs r2, #2
8001b64: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001b68: 687b ldr r3, [r7, #4]
8001b6a: 681a ldr r2, [r3, #0]
8001b6c: 687b ldr r3, [r7, #4]
8001b6e: 3304 adds r3, #4
8001b70: 4619 mov r1, r3
8001b72: 4610 mov r0, r2
8001b74: f000 f9ca bl 8001f0c <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001b78: 687b ldr r3, [r7, #4]
8001b7a: 2201 movs r2, #1
8001b7c: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001b80: 687b ldr r3, [r7, #4]
8001b82: 2201 movs r2, #1
8001b84: f883 203e strb.w r2, [r3, #62] ; 0x3e
8001b88: 687b ldr r3, [r7, #4]
8001b8a: 2201 movs r2, #1
8001b8c: f883 203f strb.w r2, [r3, #63] ; 0x3f
8001b90: 687b ldr r3, [r7, #4]
8001b92: 2201 movs r2, #1
8001b94: f883 2040 strb.w r2, [r3, #64] ; 0x40
8001b98: 687b ldr r3, [r7, #4]
8001b9a: 2201 movs r2, #1
8001b9c: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001ba0: 687b ldr r3, [r7, #4]
8001ba2: 2201 movs r2, #1
8001ba4: f883 2042 strb.w r2, [r3, #66] ; 0x42
8001ba8: 687b ldr r3, [r7, #4]
8001baa: 2201 movs r2, #1
8001bac: f883 2043 strb.w r2, [r3, #67] ; 0x43
8001bb0: 687b ldr r3, [r7, #4]
8001bb2: 2201 movs r2, #1
8001bb4: f883 2044 strb.w r2, [r3, #68] ; 0x44
8001bb8: 687b ldr r3, [r7, #4]
8001bba: 2201 movs r2, #1
8001bbc: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8001bc0: 687b ldr r3, [r7, #4]
8001bc2: 2201 movs r2, #1
8001bc4: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001bc8: 2300 movs r3, #0
}
8001bca: 4618 mov r0, r3
8001bcc: 3708 adds r7, #8
8001bce: 46bd mov sp, r7
8001bd0: bd80 pop {r7, pc}
08001bd2 <HAL_TIM_Base_MspInit>:
* @brief Initializes the TIM Base MSP.
* @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
8001bd2: b480 push {r7}
8001bd4: b083 sub sp, #12
8001bd6: af00 add r7, sp, #0
8001bd8: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
8001bda: bf00 nop
8001bdc: 370c adds r7, #12
8001bde: 46bd mov sp, r7
8001be0: f85d 7b04 ldr.w r7, [sp], #4
8001be4: 4770 bx lr
...
08001be8 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8001be8: b480 push {r7}
8001bea: b085 sub sp, #20
8001bec: af00 add r7, sp, #0
8001bee: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8001bf0: 687b ldr r3, [r7, #4]
8001bf2: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001bf6: b2db uxtb r3, r3
8001bf8: 2b01 cmp r3, #1
8001bfa: d001 beq.n 8001c00 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8001bfc: 2301 movs r3, #1
8001bfe: e044 b.n 8001c8a <HAL_TIM_Base_Start_IT+0xa2>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001c00: 687b ldr r3, [r7, #4]
8001c02: 2202 movs r2, #2
8001c04: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8001c08: 687b ldr r3, [r7, #4]
8001c0a: 681b ldr r3, [r3, #0]
8001c0c: 68da ldr r2, [r3, #12]
8001c0e: 687b ldr r3, [r7, #4]
8001c10: 681b ldr r3, [r3, #0]
8001c12: f042 0201 orr.w r2, r2, #1
8001c16: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8001c18: 687b ldr r3, [r7, #4]
8001c1a: 681b ldr r3, [r3, #0]
8001c1c: 4a1e ldr r2, [pc, #120] ; (8001c98 <HAL_TIM_Base_Start_IT+0xb0>)
8001c1e: 4293 cmp r3, r2
8001c20: d018 beq.n 8001c54 <HAL_TIM_Base_Start_IT+0x6c>
8001c22: 687b ldr r3, [r7, #4]
8001c24: 681b ldr r3, [r3, #0]
8001c26: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001c2a: d013 beq.n 8001c54 <HAL_TIM_Base_Start_IT+0x6c>
8001c2c: 687b ldr r3, [r7, #4]
8001c2e: 681b ldr r3, [r3, #0]
8001c30: 4a1a ldr r2, [pc, #104] ; (8001c9c <HAL_TIM_Base_Start_IT+0xb4>)
8001c32: 4293 cmp r3, r2
8001c34: d00e beq.n 8001c54 <HAL_TIM_Base_Start_IT+0x6c>
8001c36: 687b ldr r3, [r7, #4]
8001c38: 681b ldr r3, [r3, #0]
8001c3a: 4a19 ldr r2, [pc, #100] ; (8001ca0 <HAL_TIM_Base_Start_IT+0xb8>)
8001c3c: 4293 cmp r3, r2
8001c3e: d009 beq.n 8001c54 <HAL_TIM_Base_Start_IT+0x6c>
8001c40: 687b ldr r3, [r7, #4]
8001c42: 681b ldr r3, [r3, #0]
8001c44: 4a17 ldr r2, [pc, #92] ; (8001ca4 <HAL_TIM_Base_Start_IT+0xbc>)
8001c46: 4293 cmp r3, r2
8001c48: d004 beq.n 8001c54 <HAL_TIM_Base_Start_IT+0x6c>
8001c4a: 687b ldr r3, [r7, #4]
8001c4c: 681b ldr r3, [r3, #0]
8001c4e: 4a16 ldr r2, [pc, #88] ; (8001ca8 <HAL_TIM_Base_Start_IT+0xc0>)
8001c50: 4293 cmp r3, r2
8001c52: d111 bne.n 8001c78 <HAL_TIM_Base_Start_IT+0x90>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8001c54: 687b ldr r3, [r7, #4]
8001c56: 681b ldr r3, [r3, #0]
8001c58: 689b ldr r3, [r3, #8]
8001c5a: f003 0307 and.w r3, r3, #7
8001c5e: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8001c60: 68fb ldr r3, [r7, #12]
8001c62: 2b06 cmp r3, #6
8001c64: d010 beq.n 8001c88 <HAL_TIM_Base_Start_IT+0xa0>
{
__HAL_TIM_ENABLE(htim);
8001c66: 687b ldr r3, [r7, #4]
8001c68: 681b ldr r3, [r3, #0]
8001c6a: 681a ldr r2, [r3, #0]
8001c6c: 687b ldr r3, [r7, #4]
8001c6e: 681b ldr r3, [r3, #0]
8001c70: f042 0201 orr.w r2, r2, #1
8001c74: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8001c76: e007 b.n 8001c88 <HAL_TIM_Base_Start_IT+0xa0>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8001c78: 687b ldr r3, [r7, #4]
8001c7a: 681b ldr r3, [r3, #0]
8001c7c: 681a ldr r2, [r3, #0]
8001c7e: 687b ldr r3, [r7, #4]
8001c80: 681b ldr r3, [r3, #0]
8001c82: f042 0201 orr.w r2, r2, #1
8001c86: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8001c88: 2300 movs r3, #0
}
8001c8a: 4618 mov r0, r3
8001c8c: 3714 adds r7, #20
8001c8e: 46bd mov sp, r7
8001c90: f85d 7b04 ldr.w r7, [sp], #4
8001c94: 4770 bx lr
8001c96: bf00 nop
8001c98: 40010000 .word 0x40010000
8001c9c: 40000400 .word 0x40000400
8001ca0: 40000800 .word 0x40000800
8001ca4: 40000c00 .word 0x40000c00
8001ca8: 40014000 .word 0x40014000
08001cac <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8001cac: b580 push {r7, lr}
8001cae: b082 sub sp, #8
8001cb0: af00 add r7, sp, #0
8001cb2: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8001cb4: 687b ldr r3, [r7, #4]
8001cb6: 681b ldr r3, [r3, #0]
8001cb8: 691b ldr r3, [r3, #16]
8001cba: f003 0302 and.w r3, r3, #2
8001cbe: 2b02 cmp r3, #2
8001cc0: d122 bne.n 8001d08 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8001cc2: 687b ldr r3, [r7, #4]
8001cc4: 681b ldr r3, [r3, #0]
8001cc6: 68db ldr r3, [r3, #12]
8001cc8: f003 0302 and.w r3, r3, #2
8001ccc: 2b02 cmp r3, #2
8001cce: d11b bne.n 8001d08 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8001cd0: 687b ldr r3, [r7, #4]
8001cd2: 681b ldr r3, [r3, #0]
8001cd4: f06f 0202 mvn.w r2, #2
8001cd8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8001cda: 687b ldr r3, [r7, #4]
8001cdc: 2201 movs r2, #1
8001cde: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8001ce0: 687b ldr r3, [r7, #4]
8001ce2: 681b ldr r3, [r3, #0]
8001ce4: 699b ldr r3, [r3, #24]
8001ce6: f003 0303 and.w r3, r3, #3
8001cea: 2b00 cmp r3, #0
8001cec: d003 beq.n 8001cf6 <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001cee: 6878 ldr r0, [r7, #4]
8001cf0: f000 f8ee bl 8001ed0 <HAL_TIM_IC_CaptureCallback>
8001cf4: e005 b.n 8001d02 <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001cf6: 6878 ldr r0, [r7, #4]
8001cf8: f000 f8e0 bl 8001ebc <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001cfc: 6878 ldr r0, [r7, #4]
8001cfe: f000 f8f1 bl 8001ee4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001d02: 687b ldr r3, [r7, #4]
8001d04: 2200 movs r2, #0
8001d06: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8001d08: 687b ldr r3, [r7, #4]
8001d0a: 681b ldr r3, [r3, #0]
8001d0c: 691b ldr r3, [r3, #16]
8001d0e: f003 0304 and.w r3, r3, #4
8001d12: 2b04 cmp r3, #4
8001d14: d122 bne.n 8001d5c <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8001d16: 687b ldr r3, [r7, #4]
8001d18: 681b ldr r3, [r3, #0]
8001d1a: 68db ldr r3, [r3, #12]
8001d1c: f003 0304 and.w r3, r3, #4
8001d20: 2b04 cmp r3, #4
8001d22: d11b bne.n 8001d5c <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8001d24: 687b ldr r3, [r7, #4]
8001d26: 681b ldr r3, [r3, #0]
8001d28: f06f 0204 mvn.w r2, #4
8001d2c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8001d2e: 687b ldr r3, [r7, #4]
8001d30: 2202 movs r2, #2
8001d32: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8001d34: 687b ldr r3, [r7, #4]
8001d36: 681b ldr r3, [r3, #0]
8001d38: 699b ldr r3, [r3, #24]
8001d3a: f403 7340 and.w r3, r3, #768 ; 0x300
8001d3e: 2b00 cmp r3, #0
8001d40: d003 beq.n 8001d4a <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001d42: 6878 ldr r0, [r7, #4]
8001d44: f000 f8c4 bl 8001ed0 <HAL_TIM_IC_CaptureCallback>
8001d48: e005 b.n 8001d56 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001d4a: 6878 ldr r0, [r7, #4]
8001d4c: f000 f8b6 bl 8001ebc <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001d50: 6878 ldr r0, [r7, #4]
8001d52: f000 f8c7 bl 8001ee4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001d56: 687b ldr r3, [r7, #4]
8001d58: 2200 movs r2, #0
8001d5a: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8001d5c: 687b ldr r3, [r7, #4]
8001d5e: 681b ldr r3, [r3, #0]
8001d60: 691b ldr r3, [r3, #16]
8001d62: f003 0308 and.w r3, r3, #8
8001d66: 2b08 cmp r3, #8
8001d68: d122 bne.n 8001db0 <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8001d6a: 687b ldr r3, [r7, #4]
8001d6c: 681b ldr r3, [r3, #0]
8001d6e: 68db ldr r3, [r3, #12]
8001d70: f003 0308 and.w r3, r3, #8
8001d74: 2b08 cmp r3, #8
8001d76: d11b bne.n 8001db0 <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8001d78: 687b ldr r3, [r7, #4]
8001d7a: 681b ldr r3, [r3, #0]
8001d7c: f06f 0208 mvn.w r2, #8
8001d80: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8001d82: 687b ldr r3, [r7, #4]
8001d84: 2204 movs r2, #4
8001d86: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8001d88: 687b ldr r3, [r7, #4]
8001d8a: 681b ldr r3, [r3, #0]
8001d8c: 69db ldr r3, [r3, #28]
8001d8e: f003 0303 and.w r3, r3, #3
8001d92: 2b00 cmp r3, #0
8001d94: d003 beq.n 8001d9e <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001d96: 6878 ldr r0, [r7, #4]
8001d98: f000 f89a bl 8001ed0 <HAL_TIM_IC_CaptureCallback>
8001d9c: e005 b.n 8001daa <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001d9e: 6878 ldr r0, [r7, #4]
8001da0: f000 f88c bl 8001ebc <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001da4: 6878 ldr r0, [r7, #4]
8001da6: f000 f89d bl 8001ee4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001daa: 687b ldr r3, [r7, #4]
8001dac: 2200 movs r2, #0
8001dae: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8001db0: 687b ldr r3, [r7, #4]
8001db2: 681b ldr r3, [r3, #0]
8001db4: 691b ldr r3, [r3, #16]
8001db6: f003 0310 and.w r3, r3, #16
8001dba: 2b10 cmp r3, #16
8001dbc: d122 bne.n 8001e04 <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8001dbe: 687b ldr r3, [r7, #4]
8001dc0: 681b ldr r3, [r3, #0]
8001dc2: 68db ldr r3, [r3, #12]
8001dc4: f003 0310 and.w r3, r3, #16
8001dc8: 2b10 cmp r3, #16
8001dca: d11b bne.n 8001e04 <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8001dcc: 687b ldr r3, [r7, #4]
8001dce: 681b ldr r3, [r3, #0]
8001dd0: f06f 0210 mvn.w r2, #16
8001dd4: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8001dd6: 687b ldr r3, [r7, #4]
8001dd8: 2208 movs r2, #8
8001dda: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8001ddc: 687b ldr r3, [r7, #4]
8001dde: 681b ldr r3, [r3, #0]
8001de0: 69db ldr r3, [r3, #28]
8001de2: f403 7340 and.w r3, r3, #768 ; 0x300
8001de6: 2b00 cmp r3, #0
8001de8: d003 beq.n 8001df2 <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001dea: 6878 ldr r0, [r7, #4]
8001dec: f000 f870 bl 8001ed0 <HAL_TIM_IC_CaptureCallback>
8001df0: e005 b.n 8001dfe <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001df2: 6878 ldr r0, [r7, #4]
8001df4: f000 f862 bl 8001ebc <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001df8: 6878 ldr r0, [r7, #4]
8001dfa: f000 f873 bl 8001ee4 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001dfe: 687b ldr r3, [r7, #4]
8001e00: 2200 movs r2, #0
8001e02: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8001e04: 687b ldr r3, [r7, #4]
8001e06: 681b ldr r3, [r3, #0]
8001e08: 691b ldr r3, [r3, #16]
8001e0a: f003 0301 and.w r3, r3, #1
8001e0e: 2b01 cmp r3, #1
8001e10: d10e bne.n 8001e30 <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8001e12: 687b ldr r3, [r7, #4]
8001e14: 681b ldr r3, [r3, #0]
8001e16: 68db ldr r3, [r3, #12]
8001e18: f003 0301 and.w r3, r3, #1
8001e1c: 2b01 cmp r3, #1
8001e1e: d107 bne.n 8001e30 <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8001e20: 687b ldr r3, [r7, #4]
8001e22: 681b ldr r3, [r3, #0]
8001e24: f06f 0201 mvn.w r2, #1
8001e28: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8001e2a: 6878 ldr r0, [r7, #4]
8001e2c: f7fe fd84 bl 8000938 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8001e30: 687b ldr r3, [r7, #4]
8001e32: 681b ldr r3, [r3, #0]
8001e34: 691b ldr r3, [r3, #16]
8001e36: f003 0380 and.w r3, r3, #128 ; 0x80
8001e3a: 2b80 cmp r3, #128 ; 0x80
8001e3c: d10e bne.n 8001e5c <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8001e3e: 687b ldr r3, [r7, #4]
8001e40: 681b ldr r3, [r3, #0]
8001e42: 68db ldr r3, [r3, #12]
8001e44: f003 0380 and.w r3, r3, #128 ; 0x80
8001e48: 2b80 cmp r3, #128 ; 0x80
8001e4a: d107 bne.n 8001e5c <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8001e4c: 687b ldr r3, [r7, #4]
8001e4e: 681b ldr r3, [r3, #0]
8001e50: f06f 0280 mvn.w r2, #128 ; 0x80
8001e54: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8001e56: 6878 ldr r0, [r7, #4]
8001e58: f000 f8e2 bl 8002020 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8001e5c: 687b ldr r3, [r7, #4]
8001e5e: 681b ldr r3, [r3, #0]
8001e60: 691b ldr r3, [r3, #16]
8001e62: f003 0340 and.w r3, r3, #64 ; 0x40
8001e66: 2b40 cmp r3, #64 ; 0x40
8001e68: d10e bne.n 8001e88 <HAL_TIM_IRQHandler+0x1dc>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8001e6a: 687b ldr r3, [r7, #4]
8001e6c: 681b ldr r3, [r3, #0]
8001e6e: 68db ldr r3, [r3, #12]
8001e70: f003 0340 and.w r3, r3, #64 ; 0x40
8001e74: 2b40 cmp r3, #64 ; 0x40
8001e76: d107 bne.n 8001e88 <HAL_TIM_IRQHandler+0x1dc>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8001e78: 687b ldr r3, [r7, #4]
8001e7a: 681b ldr r3, [r3, #0]
8001e7c: f06f 0240 mvn.w r2, #64 ; 0x40
8001e80: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8001e82: 6878 ldr r0, [r7, #4]
8001e84: f000 f838 bl 8001ef8 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8001e88: 687b ldr r3, [r7, #4]
8001e8a: 681b ldr r3, [r3, #0]
8001e8c: 691b ldr r3, [r3, #16]
8001e8e: f003 0320 and.w r3, r3, #32
8001e92: 2b20 cmp r3, #32
8001e94: d10e bne.n 8001eb4 <HAL_TIM_IRQHandler+0x208>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8001e96: 687b ldr r3, [r7, #4]
8001e98: 681b ldr r3, [r3, #0]
8001e9a: 68db ldr r3, [r3, #12]
8001e9c: f003 0320 and.w r3, r3, #32
8001ea0: 2b20 cmp r3, #32
8001ea2: d107 bne.n 8001eb4 <HAL_TIM_IRQHandler+0x208>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8001ea4: 687b ldr r3, [r7, #4]
8001ea6: 681b ldr r3, [r3, #0]
8001ea8: f06f 0220 mvn.w r2, #32
8001eac: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8001eae: 6878 ldr r0, [r7, #4]
8001eb0: f000 f8ac bl 800200c <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8001eb4: bf00 nop
8001eb6: 3708 adds r7, #8
8001eb8: 46bd mov sp, r7
8001eba: bd80 pop {r7, pc}
08001ebc <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8001ebc: b480 push {r7}
8001ebe: b083 sub sp, #12
8001ec0: af00 add r7, sp, #0
8001ec2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8001ec4: bf00 nop
8001ec6: 370c adds r7, #12
8001ec8: 46bd mov sp, r7
8001eca: f85d 7b04 ldr.w r7, [sp], #4
8001ece: 4770 bx lr
08001ed0 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8001ed0: b480 push {r7}
8001ed2: b083 sub sp, #12
8001ed4: af00 add r7, sp, #0
8001ed6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8001ed8: bf00 nop
8001eda: 370c adds r7, #12
8001edc: 46bd mov sp, r7
8001ede: f85d 7b04 ldr.w r7, [sp], #4
8001ee2: 4770 bx lr
08001ee4 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8001ee4: b480 push {r7}
8001ee6: b083 sub sp, #12
8001ee8: af00 add r7, sp, #0
8001eea: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8001eec: bf00 nop
8001eee: 370c adds r7, #12
8001ef0: 46bd mov sp, r7
8001ef2: f85d 7b04 ldr.w r7, [sp], #4
8001ef6: 4770 bx lr
08001ef8 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8001ef8: b480 push {r7}
8001efa: b083 sub sp, #12
8001efc: af00 add r7, sp, #0
8001efe: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8001f00: bf00 nop
8001f02: 370c adds r7, #12
8001f04: 46bd mov sp, r7
8001f06: f85d 7b04 ldr.w r7, [sp], #4
8001f0a: 4770 bx lr
08001f0c <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8001f0c: b480 push {r7}
8001f0e: b085 sub sp, #20
8001f10: af00 add r7, sp, #0
8001f12: 6078 str r0, [r7, #4]
8001f14: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8001f16: 687b ldr r3, [r7, #4]
8001f18: 681b ldr r3, [r3, #0]
8001f1a: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8001f1c: 687b ldr r3, [r7, #4]
8001f1e: 4a34 ldr r2, [pc, #208] ; (8001ff0 <TIM_Base_SetConfig+0xe4>)
8001f20: 4293 cmp r3, r2
8001f22: d00f beq.n 8001f44 <TIM_Base_SetConfig+0x38>
8001f24: 687b ldr r3, [r7, #4]
8001f26: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001f2a: d00b beq.n 8001f44 <TIM_Base_SetConfig+0x38>
8001f2c: 687b ldr r3, [r7, #4]
8001f2e: 4a31 ldr r2, [pc, #196] ; (8001ff4 <TIM_Base_SetConfig+0xe8>)
8001f30: 4293 cmp r3, r2
8001f32: d007 beq.n 8001f44 <TIM_Base_SetConfig+0x38>
8001f34: 687b ldr r3, [r7, #4]
8001f36: 4a30 ldr r2, [pc, #192] ; (8001ff8 <TIM_Base_SetConfig+0xec>)
8001f38: 4293 cmp r3, r2
8001f3a: d003 beq.n 8001f44 <TIM_Base_SetConfig+0x38>
8001f3c: 687b ldr r3, [r7, #4]
8001f3e: 4a2f ldr r2, [pc, #188] ; (8001ffc <TIM_Base_SetConfig+0xf0>)
8001f40: 4293 cmp r3, r2
8001f42: d108 bne.n 8001f56 <TIM_Base_SetConfig+0x4a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8001f44: 68fb ldr r3, [r7, #12]
8001f46: f023 0370 bic.w r3, r3, #112 ; 0x70
8001f4a: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8001f4c: 683b ldr r3, [r7, #0]
8001f4e: 685b ldr r3, [r3, #4]
8001f50: 68fa ldr r2, [r7, #12]
8001f52: 4313 orrs r3, r2
8001f54: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8001f56: 687b ldr r3, [r7, #4]
8001f58: 4a25 ldr r2, [pc, #148] ; (8001ff0 <TIM_Base_SetConfig+0xe4>)
8001f5a: 4293 cmp r3, r2
8001f5c: d01b beq.n 8001f96 <TIM_Base_SetConfig+0x8a>
8001f5e: 687b ldr r3, [r7, #4]
8001f60: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001f64: d017 beq.n 8001f96 <TIM_Base_SetConfig+0x8a>
8001f66: 687b ldr r3, [r7, #4]
8001f68: 4a22 ldr r2, [pc, #136] ; (8001ff4 <TIM_Base_SetConfig+0xe8>)
8001f6a: 4293 cmp r3, r2
8001f6c: d013 beq.n 8001f96 <TIM_Base_SetConfig+0x8a>
8001f6e: 687b ldr r3, [r7, #4]
8001f70: 4a21 ldr r2, [pc, #132] ; (8001ff8 <TIM_Base_SetConfig+0xec>)
8001f72: 4293 cmp r3, r2
8001f74: d00f beq.n 8001f96 <TIM_Base_SetConfig+0x8a>
8001f76: 687b ldr r3, [r7, #4]
8001f78: 4a20 ldr r2, [pc, #128] ; (8001ffc <TIM_Base_SetConfig+0xf0>)
8001f7a: 4293 cmp r3, r2
8001f7c: d00b beq.n 8001f96 <TIM_Base_SetConfig+0x8a>
8001f7e: 687b ldr r3, [r7, #4]
8001f80: 4a1f ldr r2, [pc, #124] ; (8002000 <TIM_Base_SetConfig+0xf4>)
8001f82: 4293 cmp r3, r2
8001f84: d007 beq.n 8001f96 <TIM_Base_SetConfig+0x8a>
8001f86: 687b ldr r3, [r7, #4]
8001f88: 4a1e ldr r2, [pc, #120] ; (8002004 <TIM_Base_SetConfig+0xf8>)
8001f8a: 4293 cmp r3, r2
8001f8c: d003 beq.n 8001f96 <TIM_Base_SetConfig+0x8a>
8001f8e: 687b ldr r3, [r7, #4]
8001f90: 4a1d ldr r2, [pc, #116] ; (8002008 <TIM_Base_SetConfig+0xfc>)
8001f92: 4293 cmp r3, r2
8001f94: d108 bne.n 8001fa8 <TIM_Base_SetConfig+0x9c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8001f96: 68fb ldr r3, [r7, #12]
8001f98: f423 7340 bic.w r3, r3, #768 ; 0x300
8001f9c: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8001f9e: 683b ldr r3, [r7, #0]
8001fa0: 68db ldr r3, [r3, #12]
8001fa2: 68fa ldr r2, [r7, #12]
8001fa4: 4313 orrs r3, r2
8001fa6: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8001fa8: 68fb ldr r3, [r7, #12]
8001faa: f023 0280 bic.w r2, r3, #128 ; 0x80
8001fae: 683b ldr r3, [r7, #0]
8001fb0: 695b ldr r3, [r3, #20]
8001fb2: 4313 orrs r3, r2
8001fb4: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8001fb6: 687b ldr r3, [r7, #4]
8001fb8: 68fa ldr r2, [r7, #12]
8001fba: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8001fbc: 683b ldr r3, [r7, #0]
8001fbe: 689a ldr r2, [r3, #8]
8001fc0: 687b ldr r3, [r7, #4]
8001fc2: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8001fc4: 683b ldr r3, [r7, #0]
8001fc6: 681a ldr r2, [r3, #0]
8001fc8: 687b ldr r3, [r7, #4]
8001fca: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8001fcc: 687b ldr r3, [r7, #4]
8001fce: 4a08 ldr r2, [pc, #32] ; (8001ff0 <TIM_Base_SetConfig+0xe4>)
8001fd0: 4293 cmp r3, r2
8001fd2: d103 bne.n 8001fdc <TIM_Base_SetConfig+0xd0>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8001fd4: 683b ldr r3, [r7, #0]
8001fd6: 691a ldr r2, [r3, #16]
8001fd8: 687b ldr r3, [r7, #4]
8001fda: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8001fdc: 687b ldr r3, [r7, #4]
8001fde: 2201 movs r2, #1
8001fe0: 615a str r2, [r3, #20]
}
8001fe2: bf00 nop
8001fe4: 3714 adds r7, #20
8001fe6: 46bd mov sp, r7
8001fe8: f85d 7b04 ldr.w r7, [sp], #4
8001fec: 4770 bx lr
8001fee: bf00 nop
8001ff0: 40010000 .word 0x40010000
8001ff4: 40000400 .word 0x40000400
8001ff8: 40000800 .word 0x40000800
8001ffc: 40000c00 .word 0x40000c00
8002000: 40014000 .word 0x40014000
8002004: 40014400 .word 0x40014400
8002008: 40014800 .word 0x40014800
0800200c <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
800200c: b480 push {r7}
800200e: b083 sub sp, #12
8002010: af00 add r7, sp, #0
8002012: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8002014: bf00 nop
8002016: 370c adds r7, #12
8002018: 46bd mov sp, r7
800201a: f85d 7b04 ldr.w r7, [sp], #4
800201e: 4770 bx lr
08002020 <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
8002020: b480 push {r7}
8002022: b083 sub sp, #12
8002024: af00 add r7, sp, #0
8002026: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8002028: bf00 nop
800202a: 370c adds r7, #12
800202c: 46bd mov sp, r7
800202e: f85d 7b04 ldr.w r7, [sp], #4
8002032: 4770 bx lr
08002034 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8002034: b580 push {r7, lr}
8002036: b082 sub sp, #8
8002038: af00 add r7, sp, #0
800203a: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
800203c: 687b ldr r3, [r7, #4]
800203e: 2b00 cmp r3, #0
8002040: d101 bne.n 8002046 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
8002042: 2301 movs r3, #1
8002044: e03f b.n 80020c6 <HAL_UART_Init+0x92>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
8002046: 687b ldr r3, [r7, #4]
8002048: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
800204c: b2db uxtb r3, r3
800204e: 2b00 cmp r3, #0
8002050: d106 bne.n 8002060 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8002052: 687b ldr r3, [r7, #4]
8002054: 2200 movs r2, #0
8002056: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
800205a: 6878 ldr r0, [r7, #4]
800205c: f7fe fcb0 bl 80009c0 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8002060: 687b ldr r3, [r7, #4]
8002062: 2224 movs r2, #36 ; 0x24
8002064: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8002068: 687b ldr r3, [r7, #4]
800206a: 681b ldr r3, [r3, #0]
800206c: 68da ldr r2, [r3, #12]
800206e: 687b ldr r3, [r7, #4]
8002070: 681b ldr r3, [r3, #0]
8002072: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8002076: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8002078: 6878 ldr r0, [r7, #4]
800207a: f000 f9cb bl 8002414 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800207e: 687b ldr r3, [r7, #4]
8002080: 681b ldr r3, [r3, #0]
8002082: 691a ldr r2, [r3, #16]
8002084: 687b ldr r3, [r7, #4]
8002086: 681b ldr r3, [r3, #0]
8002088: f422 4290 bic.w r2, r2, #18432 ; 0x4800
800208c: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800208e: 687b ldr r3, [r7, #4]
8002090: 681b ldr r3, [r3, #0]
8002092: 695a ldr r2, [r3, #20]
8002094: 687b ldr r3, [r7, #4]
8002096: 681b ldr r3, [r3, #0]
8002098: f022 022a bic.w r2, r2, #42 ; 0x2a
800209c: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
800209e: 687b ldr r3, [r7, #4]
80020a0: 681b ldr r3, [r3, #0]
80020a2: 68da ldr r2, [r3, #12]
80020a4: 687b ldr r3, [r7, #4]
80020a6: 681b ldr r3, [r3, #0]
80020a8: f442 5200 orr.w r2, r2, #8192 ; 0x2000
80020ac: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80020ae: 687b ldr r3, [r7, #4]
80020b0: 2200 movs r2, #0
80020b2: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_READY;
80020b4: 687b ldr r3, [r7, #4]
80020b6: 2220 movs r2, #32
80020b8: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80020bc: 687b ldr r3, [r7, #4]
80020be: 2220 movs r2, #32
80020c0: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
80020c4: 2300 movs r3, #0
}
80020c6: 4618 mov r0, r3
80020c8: 3708 adds r7, #8
80020ca: 46bd mov sp, r7
80020cc: bd80 pop {r7, pc}
080020ce <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
80020ce: b580 push {r7, lr}
80020d0: b08a sub sp, #40 ; 0x28
80020d2: af02 add r7, sp, #8
80020d4: 60f8 str r0, [r7, #12]
80020d6: 60b9 str r1, [r7, #8]
80020d8: 603b str r3, [r7, #0]
80020da: 4613 mov r3, r2
80020dc: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart = 0U;
80020de: 2300 movs r3, #0
80020e0: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
80020e2: 68fb ldr r3, [r7, #12]
80020e4: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80020e8: b2db uxtb r3, r3
80020ea: 2b20 cmp r3, #32
80020ec: d17c bne.n 80021e8 <HAL_UART_Transmit+0x11a>
{
if ((pData == NULL) || (Size == 0U))
80020ee: 68bb ldr r3, [r7, #8]
80020f0: 2b00 cmp r3, #0
80020f2: d002 beq.n 80020fa <HAL_UART_Transmit+0x2c>
80020f4: 88fb ldrh r3, [r7, #6]
80020f6: 2b00 cmp r3, #0
80020f8: d101 bne.n 80020fe <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
80020fa: 2301 movs r3, #1
80020fc: e075 b.n 80021ea <HAL_UART_Transmit+0x11c>
}
/* Process Locked */
__HAL_LOCK(huart);
80020fe: 68fb ldr r3, [r7, #12]
8002100: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002104: 2b01 cmp r3, #1
8002106: d101 bne.n 800210c <HAL_UART_Transmit+0x3e>
8002108: 2302 movs r3, #2
800210a: e06e b.n 80021ea <HAL_UART_Transmit+0x11c>
800210c: 68fb ldr r3, [r7, #12]
800210e: 2201 movs r2, #1
8002110: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8002114: 68fb ldr r3, [r7, #12]
8002116: 2200 movs r2, #0
8002118: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_BUSY_TX;
800211a: 68fb ldr r3, [r7, #12]
800211c: 2221 movs r2, #33 ; 0x21
800211e: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8002122: f7fe fd99 bl 8000c58 <HAL_GetTick>
8002126: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8002128: 68fb ldr r3, [r7, #12]
800212a: 88fa ldrh r2, [r7, #6]
800212c: 849a strh r2, [r3, #36] ; 0x24
huart->TxXferCount = Size;
800212e: 68fb ldr r3, [r7, #12]
8002130: 88fa ldrh r2, [r7, #6]
8002132: 84da strh r2, [r3, #38] ; 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8002134: 68fb ldr r3, [r7, #12]
8002136: 689b ldr r3, [r3, #8]
8002138: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
800213c: d108 bne.n 8002150 <HAL_UART_Transmit+0x82>
800213e: 68fb ldr r3, [r7, #12]
8002140: 691b ldr r3, [r3, #16]
8002142: 2b00 cmp r3, #0
8002144: d104 bne.n 8002150 <HAL_UART_Transmit+0x82>
{
pdata8bits = NULL;
8002146: 2300 movs r3, #0
8002148: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
800214a: 68bb ldr r3, [r7, #8]
800214c: 61bb str r3, [r7, #24]
800214e: e003 b.n 8002158 <HAL_UART_Transmit+0x8a>
}
else
{
pdata8bits = pData;
8002150: 68bb ldr r3, [r7, #8]
8002152: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8002154: 2300 movs r3, #0
8002156: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
8002158: 68fb ldr r3, [r7, #12]
800215a: 2200 movs r2, #0
800215c: f883 203c strb.w r2, [r3, #60] ; 0x3c
while (huart->TxXferCount > 0U)
8002160: e02a b.n 80021b8 <HAL_UART_Transmit+0xea>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8002162: 683b ldr r3, [r7, #0]
8002164: 9300 str r3, [sp, #0]
8002166: 697b ldr r3, [r7, #20]
8002168: 2200 movs r2, #0
800216a: 2180 movs r1, #128 ; 0x80
800216c: 68f8 ldr r0, [r7, #12]
800216e: f000 f8e2 bl 8002336 <UART_WaitOnFlagUntilTimeout>
8002172: 4603 mov r3, r0
8002174: 2b00 cmp r3, #0
8002176: d001 beq.n 800217c <HAL_UART_Transmit+0xae>
{
return HAL_TIMEOUT;
8002178: 2303 movs r3, #3
800217a: e036 b.n 80021ea <HAL_UART_Transmit+0x11c>
}
if (pdata8bits == NULL)
800217c: 69fb ldr r3, [r7, #28]
800217e: 2b00 cmp r3, #0
8002180: d10b bne.n 800219a <HAL_UART_Transmit+0xcc>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
8002182: 69bb ldr r3, [r7, #24]
8002184: 881b ldrh r3, [r3, #0]
8002186: 461a mov r2, r3
8002188: 68fb ldr r3, [r7, #12]
800218a: 681b ldr r3, [r3, #0]
800218c: f3c2 0208 ubfx r2, r2, #0, #9
8002190: 605a str r2, [r3, #4]
pdata16bits++;
8002192: 69bb ldr r3, [r7, #24]
8002194: 3302 adds r3, #2
8002196: 61bb str r3, [r7, #24]
8002198: e007 b.n 80021aa <HAL_UART_Transmit+0xdc>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
800219a: 69fb ldr r3, [r7, #28]
800219c: 781a ldrb r2, [r3, #0]
800219e: 68fb ldr r3, [r7, #12]
80021a0: 681b ldr r3, [r3, #0]
80021a2: 605a str r2, [r3, #4]
pdata8bits++;
80021a4: 69fb ldr r3, [r7, #28]
80021a6: 3301 adds r3, #1
80021a8: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
80021aa: 68fb ldr r3, [r7, #12]
80021ac: 8cdb ldrh r3, [r3, #38] ; 0x26
80021ae: b29b uxth r3, r3
80021b0: 3b01 subs r3, #1
80021b2: b29a uxth r2, r3
80021b4: 68fb ldr r3, [r7, #12]
80021b6: 84da strh r2, [r3, #38] ; 0x26
while (huart->TxXferCount > 0U)
80021b8: 68fb ldr r3, [r7, #12]
80021ba: 8cdb ldrh r3, [r3, #38] ; 0x26
80021bc: b29b uxth r3, r3
80021be: 2b00 cmp r3, #0
80021c0: d1cf bne.n 8002162 <HAL_UART_Transmit+0x94>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
80021c2: 683b ldr r3, [r7, #0]
80021c4: 9300 str r3, [sp, #0]
80021c6: 697b ldr r3, [r7, #20]
80021c8: 2200 movs r2, #0
80021ca: 2140 movs r1, #64 ; 0x40
80021cc: 68f8 ldr r0, [r7, #12]
80021ce: f000 f8b2 bl 8002336 <UART_WaitOnFlagUntilTimeout>
80021d2: 4603 mov r3, r0
80021d4: 2b00 cmp r3, #0
80021d6: d001 beq.n 80021dc <HAL_UART_Transmit+0x10e>
{
return HAL_TIMEOUT;
80021d8: 2303 movs r3, #3
80021da: e006 b.n 80021ea <HAL_UART_Transmit+0x11c>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
80021dc: 68fb ldr r3, [r7, #12]
80021de: 2220 movs r2, #32
80021e0: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
80021e4: 2300 movs r3, #0
80021e6: e000 b.n 80021ea <HAL_UART_Transmit+0x11c>
}
else
{
return HAL_BUSY;
80021e8: 2302 movs r3, #2
}
}
80021ea: 4618 mov r0, r3
80021ec: 3720 adds r7, #32
80021ee: 46bd mov sp, r7
80021f0: bd80 pop {r7, pc}
080021f2 <HAL_UART_Receive>:
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
80021f2: b580 push {r7, lr}
80021f4: b08a sub sp, #40 ; 0x28
80021f6: af02 add r7, sp, #8
80021f8: 60f8 str r0, [r7, #12]
80021fa: 60b9 str r1, [r7, #8]
80021fc: 603b str r3, [r7, #0]
80021fe: 4613 mov r3, r2
8002200: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
8002202: 2300 movs r3, #0
8002204: 617b str r3, [r7, #20]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8002206: 68fb ldr r3, [r7, #12]
8002208: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
800220c: b2db uxtb r3, r3
800220e: 2b20 cmp r3, #32
8002210: f040 808c bne.w 800232c <HAL_UART_Receive+0x13a>
{
if ((pData == NULL) || (Size == 0U))
8002214: 68bb ldr r3, [r7, #8]
8002216: 2b00 cmp r3, #0
8002218: d002 beq.n 8002220 <HAL_UART_Receive+0x2e>
800221a: 88fb ldrh r3, [r7, #6]
800221c: 2b00 cmp r3, #0
800221e: d101 bne.n 8002224 <HAL_UART_Receive+0x32>
{
return HAL_ERROR;
8002220: 2301 movs r3, #1
8002222: e084 b.n 800232e <HAL_UART_Receive+0x13c>
}
/* Process Locked */
__HAL_LOCK(huart);
8002224: 68fb ldr r3, [r7, #12]
8002226: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
800222a: 2b01 cmp r3, #1
800222c: d101 bne.n 8002232 <HAL_UART_Receive+0x40>
800222e: 2302 movs r3, #2
8002230: e07d b.n 800232e <HAL_UART_Receive+0x13c>
8002232: 68fb ldr r3, [r7, #12]
8002234: 2201 movs r2, #1
8002236: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
800223a: 68fb ldr r3, [r7, #12]
800223c: 2200 movs r2, #0
800223e: 641a str r2, [r3, #64] ; 0x40
huart->RxState = HAL_UART_STATE_BUSY_RX;
8002240: 68fb ldr r3, [r7, #12]
8002242: 2222 movs r2, #34 ; 0x22
8002244: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8002248: 68fb ldr r3, [r7, #12]
800224a: 2200 movs r2, #0
800224c: 631a str r2, [r3, #48] ; 0x30
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
800224e: f7fe fd03 bl 8000c58 <HAL_GetTick>
8002252: 6178 str r0, [r7, #20]
huart->RxXferSize = Size;
8002254: 68fb ldr r3, [r7, #12]
8002256: 88fa ldrh r2, [r7, #6]
8002258: 859a strh r2, [r3, #44] ; 0x2c
huart->RxXferCount = Size;
800225a: 68fb ldr r3, [r7, #12]
800225c: 88fa ldrh r2, [r7, #6]
800225e: 85da strh r2, [r3, #46] ; 0x2e
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8002260: 68fb ldr r3, [r7, #12]
8002262: 689b ldr r3, [r3, #8]
8002264: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8002268: d108 bne.n 800227c <HAL_UART_Receive+0x8a>
800226a: 68fb ldr r3, [r7, #12]
800226c: 691b ldr r3, [r3, #16]
800226e: 2b00 cmp r3, #0
8002270: d104 bne.n 800227c <HAL_UART_Receive+0x8a>
{
pdata8bits = NULL;
8002272: 2300 movs r3, #0
8002274: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
8002276: 68bb ldr r3, [r7, #8]
8002278: 61bb str r3, [r7, #24]
800227a: e003 b.n 8002284 <HAL_UART_Receive+0x92>
}
else
{
pdata8bits = pData;
800227c: 68bb ldr r3, [r7, #8]
800227e: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8002280: 2300 movs r3, #0
8002282: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
8002284: 68fb ldr r3, [r7, #12]
8002286: 2200 movs r2, #0
8002288: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Check the remain data to be received */
while (huart->RxXferCount > 0U)
800228c: e043 b.n 8002316 <HAL_UART_Receive+0x124>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
800228e: 683b ldr r3, [r7, #0]
8002290: 9300 str r3, [sp, #0]
8002292: 697b ldr r3, [r7, #20]
8002294: 2200 movs r2, #0
8002296: 2120 movs r1, #32
8002298: 68f8 ldr r0, [r7, #12]
800229a: f000 f84c bl 8002336 <UART_WaitOnFlagUntilTimeout>
800229e: 4603 mov r3, r0
80022a0: 2b00 cmp r3, #0
80022a2: d001 beq.n 80022a8 <HAL_UART_Receive+0xb6>
{
return HAL_TIMEOUT;
80022a4: 2303 movs r3, #3
80022a6: e042 b.n 800232e <HAL_UART_Receive+0x13c>
}
if (pdata8bits == NULL)
80022a8: 69fb ldr r3, [r7, #28]
80022aa: 2b00 cmp r3, #0
80022ac: d10c bne.n 80022c8 <HAL_UART_Receive+0xd6>
{
*pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
80022ae: 68fb ldr r3, [r7, #12]
80022b0: 681b ldr r3, [r3, #0]
80022b2: 685b ldr r3, [r3, #4]
80022b4: b29b uxth r3, r3
80022b6: f3c3 0308 ubfx r3, r3, #0, #9
80022ba: b29a uxth r2, r3
80022bc: 69bb ldr r3, [r7, #24]
80022be: 801a strh r2, [r3, #0]
pdata16bits++;
80022c0: 69bb ldr r3, [r7, #24]
80022c2: 3302 adds r3, #2
80022c4: 61bb str r3, [r7, #24]
80022c6: e01f b.n 8002308 <HAL_UART_Receive+0x116>
}
else
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
80022c8: 68fb ldr r3, [r7, #12]
80022ca: 689b ldr r3, [r3, #8]
80022cc: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80022d0: d007 beq.n 80022e2 <HAL_UART_Receive+0xf0>
80022d2: 68fb ldr r3, [r7, #12]
80022d4: 689b ldr r3, [r3, #8]
80022d6: 2b00 cmp r3, #0
80022d8: d10a bne.n 80022f0 <HAL_UART_Receive+0xfe>
80022da: 68fb ldr r3, [r7, #12]
80022dc: 691b ldr r3, [r3, #16]
80022de: 2b00 cmp r3, #0
80022e0: d106 bne.n 80022f0 <HAL_UART_Receive+0xfe>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
80022e2: 68fb ldr r3, [r7, #12]
80022e4: 681b ldr r3, [r3, #0]
80022e6: 685b ldr r3, [r3, #4]
80022e8: b2da uxtb r2, r3
80022ea: 69fb ldr r3, [r7, #28]
80022ec: 701a strb r2, [r3, #0]
80022ee: e008 b.n 8002302 <HAL_UART_Receive+0x110>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
80022f0: 68fb ldr r3, [r7, #12]
80022f2: 681b ldr r3, [r3, #0]
80022f4: 685b ldr r3, [r3, #4]
80022f6: b2db uxtb r3, r3
80022f8: f003 037f and.w r3, r3, #127 ; 0x7f
80022fc: b2da uxtb r2, r3
80022fe: 69fb ldr r3, [r7, #28]
8002300: 701a strb r2, [r3, #0]
}
pdata8bits++;
8002302: 69fb ldr r3, [r7, #28]
8002304: 3301 adds r3, #1
8002306: 61fb str r3, [r7, #28]
}
huart->RxXferCount--;
8002308: 68fb ldr r3, [r7, #12]
800230a: 8ddb ldrh r3, [r3, #46] ; 0x2e
800230c: b29b uxth r3, r3
800230e: 3b01 subs r3, #1
8002310: b29a uxth r2, r3
8002312: 68fb ldr r3, [r7, #12]
8002314: 85da strh r2, [r3, #46] ; 0x2e
while (huart->RxXferCount > 0U)
8002316: 68fb ldr r3, [r7, #12]
8002318: 8ddb ldrh r3, [r3, #46] ; 0x2e
800231a: b29b uxth r3, r3
800231c: 2b00 cmp r3, #0
800231e: d1b6 bne.n 800228e <HAL_UART_Receive+0x9c>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8002320: 68fb ldr r3, [r7, #12]
8002322: 2220 movs r2, #32
8002324: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8002328: 2300 movs r3, #0
800232a: e000 b.n 800232e <HAL_UART_Receive+0x13c>
}
else
{
return HAL_BUSY;
800232c: 2302 movs r3, #2
}
}
800232e: 4618 mov r0, r3
8002330: 3720 adds r7, #32
8002332: 46bd mov sp, r7
8002334: bd80 pop {r7, pc}
08002336 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8002336: b580 push {r7, lr}
8002338: b090 sub sp, #64 ; 0x40
800233a: af00 add r7, sp, #0
800233c: 60f8 str r0, [r7, #12]
800233e: 60b9 str r1, [r7, #8]
8002340: 603b str r3, [r7, #0]
8002342: 4613 mov r3, r2
8002344: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8002346: e050 b.n 80023ea <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8002348: 6cbb ldr r3, [r7, #72] ; 0x48
800234a: f1b3 3fff cmp.w r3, #4294967295
800234e: d04c beq.n 80023ea <UART_WaitOnFlagUntilTimeout+0xb4>
{
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
8002350: 6cbb ldr r3, [r7, #72] ; 0x48
8002352: 2b00 cmp r3, #0
8002354: d007 beq.n 8002366 <UART_WaitOnFlagUntilTimeout+0x30>
8002356: f7fe fc7f bl 8000c58 <HAL_GetTick>
800235a: 4602 mov r2, r0
800235c: 683b ldr r3, [r7, #0]
800235e: 1ad3 subs r3, r2, r3
8002360: 6cba ldr r2, [r7, #72] ; 0x48
8002362: 429a cmp r2, r3
8002364: d241 bcs.n 80023ea <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
8002366: 68fb ldr r3, [r7, #12]
8002368: 681b ldr r3, [r3, #0]
800236a: 330c adds r3, #12
800236c: 62bb str r3, [r7, #40] ; 0x28
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800236e: 6abb ldr r3, [r7, #40] ; 0x28
8002370: e853 3f00 ldrex r3, [r3]
8002374: 627b str r3, [r7, #36] ; 0x24
return(result);
8002376: 6a7b ldr r3, [r7, #36] ; 0x24
8002378: f423 73d0 bic.w r3, r3, #416 ; 0x1a0
800237c: 63fb str r3, [r7, #60] ; 0x3c
800237e: 68fb ldr r3, [r7, #12]
8002380: 681b ldr r3, [r3, #0]
8002382: 330c adds r3, #12
8002384: 6bfa ldr r2, [r7, #60] ; 0x3c
8002386: 637a str r2, [r7, #52] ; 0x34
8002388: 633b str r3, [r7, #48] ; 0x30
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800238a: 6b39 ldr r1, [r7, #48] ; 0x30
800238c: 6b7a ldr r2, [r7, #52] ; 0x34
800238e: e841 2300 strex r3, r2, [r1]
8002392: 62fb str r3, [r7, #44] ; 0x2c
return(result);
8002394: 6afb ldr r3, [r7, #44] ; 0x2c
8002396: 2b00 cmp r3, #0
8002398: d1e5 bne.n 8002366 <UART_WaitOnFlagUntilTimeout+0x30>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800239a: 68fb ldr r3, [r7, #12]
800239c: 681b ldr r3, [r3, #0]
800239e: 3314 adds r3, #20
80023a0: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80023a2: 697b ldr r3, [r7, #20]
80023a4: e853 3f00 ldrex r3, [r3]
80023a8: 613b str r3, [r7, #16]
return(result);
80023aa: 693b ldr r3, [r7, #16]
80023ac: f023 0301 bic.w r3, r3, #1
80023b0: 63bb str r3, [r7, #56] ; 0x38
80023b2: 68fb ldr r3, [r7, #12]
80023b4: 681b ldr r3, [r3, #0]
80023b6: 3314 adds r3, #20
80023b8: 6bba ldr r2, [r7, #56] ; 0x38
80023ba: 623a str r2, [r7, #32]
80023bc: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80023be: 69f9 ldr r1, [r7, #28]
80023c0: 6a3a ldr r2, [r7, #32]
80023c2: e841 2300 strex r3, r2, [r1]
80023c6: 61bb str r3, [r7, #24]
return(result);
80023c8: 69bb ldr r3, [r7, #24]
80023ca: 2b00 cmp r3, #0
80023cc: d1e5 bne.n 800239a <UART_WaitOnFlagUntilTimeout+0x64>
huart->gState = HAL_UART_STATE_READY;
80023ce: 68fb ldr r3, [r7, #12]
80023d0: 2220 movs r2, #32
80023d2: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80023d6: 68fb ldr r3, [r7, #12]
80023d8: 2220 movs r2, #32
80023da: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Process Unlocked */
__HAL_UNLOCK(huart);
80023de: 68fb ldr r3, [r7, #12]
80023e0: 2200 movs r2, #0
80023e2: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
80023e6: 2303 movs r3, #3
80023e8: e00f b.n 800240a <UART_WaitOnFlagUntilTimeout+0xd4>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80023ea: 68fb ldr r3, [r7, #12]
80023ec: 681b ldr r3, [r3, #0]
80023ee: 681a ldr r2, [r3, #0]
80023f0: 68bb ldr r3, [r7, #8]
80023f2: 4013 ands r3, r2
80023f4: 68ba ldr r2, [r7, #8]
80023f6: 429a cmp r2, r3
80023f8: bf0c ite eq
80023fa: 2301 moveq r3, #1
80023fc: 2300 movne r3, #0
80023fe: b2db uxtb r3, r3
8002400: 461a mov r2, r3
8002402: 79fb ldrb r3, [r7, #7]
8002404: 429a cmp r2, r3
8002406: d09f beq.n 8002348 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
8002408: 2300 movs r3, #0
}
800240a: 4618 mov r0, r3
800240c: 3740 adds r7, #64 ; 0x40
800240e: 46bd mov sp, r7
8002410: bd80 pop {r7, pc}
...
08002414 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8002414: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8002418: b0c0 sub sp, #256 ; 0x100
800241a: af00 add r7, sp, #0
800241c: f8c7 00f4 str.w r0, [r7, #244] ; 0xf4
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8002420: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002424: 681b ldr r3, [r3, #0]
8002426: 691b ldr r3, [r3, #16]
8002428: f423 5040 bic.w r0, r3, #12288 ; 0x3000
800242c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002430: 68d9 ldr r1, [r3, #12]
8002432: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002436: 681a ldr r2, [r3, #0]
8002438: ea40 0301 orr.w r3, r0, r1
800243c: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
800243e: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002442: 689a ldr r2, [r3, #8]
8002444: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002448: 691b ldr r3, [r3, #16]
800244a: 431a orrs r2, r3
800244c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002450: 695b ldr r3, [r3, #20]
8002452: 431a orrs r2, r3
8002454: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002458: 69db ldr r3, [r3, #28]
800245a: 4313 orrs r3, r2
800245c: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8
MODIFY_REG(huart->Instance->CR1,
8002460: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002464: 681b ldr r3, [r3, #0]
8002466: 68db ldr r3, [r3, #12]
8002468: f423 4116 bic.w r1, r3, #38400 ; 0x9600
800246c: f021 010c bic.w r1, r1, #12
8002470: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002474: 681a ldr r2, [r3, #0]
8002476: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8
800247a: 430b orrs r3, r1
800247c: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
800247e: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002482: 681b ldr r3, [r3, #0]
8002484: 695b ldr r3, [r3, #20]
8002486: f423 7040 bic.w r0, r3, #768 ; 0x300
800248a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800248e: 6999 ldr r1, [r3, #24]
8002490: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002494: 681a ldr r2, [r3, #0]
8002496: ea40 0301 orr.w r3, r0, r1
800249a: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
800249c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80024a0: 681a ldr r2, [r3, #0]
80024a2: 4b8f ldr r3, [pc, #572] ; (80026e0 <UART_SetConfig+0x2cc>)
80024a4: 429a cmp r2, r3
80024a6: d005 beq.n 80024b4 <UART_SetConfig+0xa0>
80024a8: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80024ac: 681a ldr r2, [r3, #0]
80024ae: 4b8d ldr r3, [pc, #564] ; (80026e4 <UART_SetConfig+0x2d0>)
80024b0: 429a cmp r2, r3
80024b2: d104 bne.n 80024be <UART_SetConfig+0xaa>
{
pclk = HAL_RCC_GetPCLK2Freq();
80024b4: f7ff faf8 bl 8001aa8 <HAL_RCC_GetPCLK2Freq>
80024b8: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
80024bc: e003 b.n 80024c6 <UART_SetConfig+0xb2>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
80024be: f7ff fadf bl 8001a80 <HAL_RCC_GetPCLK1Freq>
80024c2: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80024c6: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80024ca: 69db ldr r3, [r3, #28]
80024cc: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80024d0: f040 810c bne.w 80026ec <UART_SetConfig+0x2d8>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
80024d4: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
80024d8: 2200 movs r2, #0
80024da: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8
80024de: f8c7 20ec str.w r2, [r7, #236] ; 0xec
80024e2: e9d7 453a ldrd r4, r5, [r7, #232] ; 0xe8
80024e6: 4622 mov r2, r4
80024e8: 462b mov r3, r5
80024ea: 1891 adds r1, r2, r2
80024ec: 65b9 str r1, [r7, #88] ; 0x58
80024ee: 415b adcs r3, r3
80024f0: 65fb str r3, [r7, #92] ; 0x5c
80024f2: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58
80024f6: 4621 mov r1, r4
80024f8: eb12 0801 adds.w r8, r2, r1
80024fc: 4629 mov r1, r5
80024fe: eb43 0901 adc.w r9, r3, r1
8002502: f04f 0200 mov.w r2, #0
8002506: f04f 0300 mov.w r3, #0
800250a: ea4f 03c9 mov.w r3, r9, lsl #3
800250e: ea43 7358 orr.w r3, r3, r8, lsr #29
8002512: ea4f 02c8 mov.w r2, r8, lsl #3
8002516: 4690 mov r8, r2
8002518: 4699 mov r9, r3
800251a: 4623 mov r3, r4
800251c: eb18 0303 adds.w r3, r8, r3
8002520: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
8002524: 462b mov r3, r5
8002526: eb49 0303 adc.w r3, r9, r3
800252a: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
800252e: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002532: 685b ldr r3, [r3, #4]
8002534: 2200 movs r2, #0
8002536: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
800253a: f8c7 20dc str.w r2, [r7, #220] ; 0xdc
800253e: e9d7 1236 ldrd r1, r2, [r7, #216] ; 0xd8
8002542: 460b mov r3, r1
8002544: 18db adds r3, r3, r3
8002546: 653b str r3, [r7, #80] ; 0x50
8002548: 4613 mov r3, r2
800254a: eb42 0303 adc.w r3, r2, r3
800254e: 657b str r3, [r7, #84] ; 0x54
8002550: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50
8002554: e9d7 0138 ldrd r0, r1, [r7, #224] ; 0xe0
8002558: f7fd fe42 bl 80001e0 <__aeabi_uldivmod>
800255c: 4602 mov r2, r0
800255e: 460b mov r3, r1
8002560: 4b61 ldr r3, [pc, #388] ; (80026e8 <UART_SetConfig+0x2d4>)
8002562: fba3 2302 umull r2, r3, r3, r2
8002566: 095b lsrs r3, r3, #5
8002568: 011c lsls r4, r3, #4
800256a: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
800256e: 2200 movs r2, #0
8002570: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
8002574: f8c7 20d4 str.w r2, [r7, #212] ; 0xd4
8002578: e9d7 8934 ldrd r8, r9, [r7, #208] ; 0xd0
800257c: 4642 mov r2, r8
800257e: 464b mov r3, r9
8002580: 1891 adds r1, r2, r2
8002582: 64b9 str r1, [r7, #72] ; 0x48
8002584: 415b adcs r3, r3
8002586: 64fb str r3, [r7, #76] ; 0x4c
8002588: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48
800258c: 4641 mov r1, r8
800258e: eb12 0a01 adds.w sl, r2, r1
8002592: 4649 mov r1, r9
8002594: eb43 0b01 adc.w fp, r3, r1
8002598: f04f 0200 mov.w r2, #0
800259c: f04f 0300 mov.w r3, #0
80025a0: ea4f 03cb mov.w r3, fp, lsl #3
80025a4: ea43 735a orr.w r3, r3, sl, lsr #29
80025a8: ea4f 02ca mov.w r2, sl, lsl #3
80025ac: 4692 mov sl, r2
80025ae: 469b mov fp, r3
80025b0: 4643 mov r3, r8
80025b2: eb1a 0303 adds.w r3, sl, r3
80025b6: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
80025ba: 464b mov r3, r9
80025bc: eb4b 0303 adc.w r3, fp, r3
80025c0: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
80025c4: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80025c8: 685b ldr r3, [r3, #4]
80025ca: 2200 movs r2, #0
80025cc: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
80025d0: f8c7 20c4 str.w r2, [r7, #196] ; 0xc4
80025d4: e9d7 1230 ldrd r1, r2, [r7, #192] ; 0xc0
80025d8: 460b mov r3, r1
80025da: 18db adds r3, r3, r3
80025dc: 643b str r3, [r7, #64] ; 0x40
80025de: 4613 mov r3, r2
80025e0: eb42 0303 adc.w r3, r2, r3
80025e4: 647b str r3, [r7, #68] ; 0x44
80025e6: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40
80025ea: e9d7 0132 ldrd r0, r1, [r7, #200] ; 0xc8
80025ee: f7fd fdf7 bl 80001e0 <__aeabi_uldivmod>
80025f2: 4602 mov r2, r0
80025f4: 460b mov r3, r1
80025f6: 4611 mov r1, r2
80025f8: 4b3b ldr r3, [pc, #236] ; (80026e8 <UART_SetConfig+0x2d4>)
80025fa: fba3 2301 umull r2, r3, r3, r1
80025fe: 095b lsrs r3, r3, #5
8002600: 2264 movs r2, #100 ; 0x64
8002602: fb02 f303 mul.w r3, r2, r3
8002606: 1acb subs r3, r1, r3
8002608: 00db lsls r3, r3, #3
800260a: f103 0232 add.w r2, r3, #50 ; 0x32
800260e: 4b36 ldr r3, [pc, #216] ; (80026e8 <UART_SetConfig+0x2d4>)
8002610: fba3 2302 umull r2, r3, r3, r2
8002614: 095b lsrs r3, r3, #5
8002616: 005b lsls r3, r3, #1
8002618: f403 73f8 and.w r3, r3, #496 ; 0x1f0
800261c: 441c add r4, r3
800261e: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8002622: 2200 movs r2, #0
8002624: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
8002628: f8c7 20bc str.w r2, [r7, #188] ; 0xbc
800262c: e9d7 892e ldrd r8, r9, [r7, #184] ; 0xb8
8002630: 4642 mov r2, r8
8002632: 464b mov r3, r9
8002634: 1891 adds r1, r2, r2
8002636: 63b9 str r1, [r7, #56] ; 0x38
8002638: 415b adcs r3, r3
800263a: 63fb str r3, [r7, #60] ; 0x3c
800263c: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38
8002640: 4641 mov r1, r8
8002642: 1851 adds r1, r2, r1
8002644: 6339 str r1, [r7, #48] ; 0x30
8002646: 4649 mov r1, r9
8002648: 414b adcs r3, r1
800264a: 637b str r3, [r7, #52] ; 0x34
800264c: f04f 0200 mov.w r2, #0
8002650: f04f 0300 mov.w r3, #0
8002654: e9d7 ab0c ldrd sl, fp, [r7, #48] ; 0x30
8002658: 4659 mov r1, fp
800265a: 00cb lsls r3, r1, #3
800265c: 4651 mov r1, sl
800265e: ea43 7351 orr.w r3, r3, r1, lsr #29
8002662: 4651 mov r1, sl
8002664: 00ca lsls r2, r1, #3
8002666: 4610 mov r0, r2
8002668: 4619 mov r1, r3
800266a: 4603 mov r3, r0
800266c: 4642 mov r2, r8
800266e: 189b adds r3, r3, r2
8002670: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
8002674: 464b mov r3, r9
8002676: 460a mov r2, r1
8002678: eb42 0303 adc.w r3, r2, r3
800267c: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
8002680: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002684: 685b ldr r3, [r3, #4]
8002686: 2200 movs r2, #0
8002688: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
800268c: f8c7 20ac str.w r2, [r7, #172] ; 0xac
8002690: e9d7 122a ldrd r1, r2, [r7, #168] ; 0xa8
8002694: 460b mov r3, r1
8002696: 18db adds r3, r3, r3
8002698: 62bb str r3, [r7, #40] ; 0x28
800269a: 4613 mov r3, r2
800269c: eb42 0303 adc.w r3, r2, r3
80026a0: 62fb str r3, [r7, #44] ; 0x2c
80026a2: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
80026a6: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0
80026aa: f7fd fd99 bl 80001e0 <__aeabi_uldivmod>
80026ae: 4602 mov r2, r0
80026b0: 460b mov r3, r1
80026b2: 4b0d ldr r3, [pc, #52] ; (80026e8 <UART_SetConfig+0x2d4>)
80026b4: fba3 1302 umull r1, r3, r3, r2
80026b8: 095b lsrs r3, r3, #5
80026ba: 2164 movs r1, #100 ; 0x64
80026bc: fb01 f303 mul.w r3, r1, r3
80026c0: 1ad3 subs r3, r2, r3
80026c2: 00db lsls r3, r3, #3
80026c4: 3332 adds r3, #50 ; 0x32
80026c6: 4a08 ldr r2, [pc, #32] ; (80026e8 <UART_SetConfig+0x2d4>)
80026c8: fba2 2303 umull r2, r3, r2, r3
80026cc: 095b lsrs r3, r3, #5
80026ce: f003 0207 and.w r2, r3, #7
80026d2: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80026d6: 681b ldr r3, [r3, #0]
80026d8: 4422 add r2, r4
80026da: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
80026dc: e106 b.n 80028ec <UART_SetConfig+0x4d8>
80026de: bf00 nop
80026e0: 40011000 .word 0x40011000
80026e4: 40011400 .word 0x40011400
80026e8: 51eb851f .word 0x51eb851f
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
80026ec: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
80026f0: 2200 movs r2, #0
80026f2: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
80026f6: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
80026fa: e9d7 8928 ldrd r8, r9, [r7, #160] ; 0xa0
80026fe: 4642 mov r2, r8
8002700: 464b mov r3, r9
8002702: 1891 adds r1, r2, r2
8002704: 6239 str r1, [r7, #32]
8002706: 415b adcs r3, r3
8002708: 627b str r3, [r7, #36] ; 0x24
800270a: e9d7 2308 ldrd r2, r3, [r7, #32]
800270e: 4641 mov r1, r8
8002710: 1854 adds r4, r2, r1
8002712: 4649 mov r1, r9
8002714: eb43 0501 adc.w r5, r3, r1
8002718: f04f 0200 mov.w r2, #0
800271c: f04f 0300 mov.w r3, #0
8002720: 00eb lsls r3, r5, #3
8002722: ea43 7354 orr.w r3, r3, r4, lsr #29
8002726: 00e2 lsls r2, r4, #3
8002728: 4614 mov r4, r2
800272a: 461d mov r5, r3
800272c: 4643 mov r3, r8
800272e: 18e3 adds r3, r4, r3
8002730: f8c7 3098 str.w r3, [r7, #152] ; 0x98
8002734: 464b mov r3, r9
8002736: eb45 0303 adc.w r3, r5, r3
800273a: f8c7 309c str.w r3, [r7, #156] ; 0x9c
800273e: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002742: 685b ldr r3, [r3, #4]
8002744: 2200 movs r2, #0
8002746: f8c7 3090 str.w r3, [r7, #144] ; 0x90
800274a: f8c7 2094 str.w r2, [r7, #148] ; 0x94
800274e: f04f 0200 mov.w r2, #0
8002752: f04f 0300 mov.w r3, #0
8002756: e9d7 4524 ldrd r4, r5, [r7, #144] ; 0x90
800275a: 4629 mov r1, r5
800275c: 008b lsls r3, r1, #2
800275e: 4621 mov r1, r4
8002760: ea43 7391 orr.w r3, r3, r1, lsr #30
8002764: 4621 mov r1, r4
8002766: 008a lsls r2, r1, #2
8002768: e9d7 0126 ldrd r0, r1, [r7, #152] ; 0x98
800276c: f7fd fd38 bl 80001e0 <__aeabi_uldivmod>
8002770: 4602 mov r2, r0
8002772: 460b mov r3, r1
8002774: 4b60 ldr r3, [pc, #384] ; (80028f8 <UART_SetConfig+0x4e4>)
8002776: fba3 2302 umull r2, r3, r3, r2
800277a: 095b lsrs r3, r3, #5
800277c: 011c lsls r4, r3, #4
800277e: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8002782: 2200 movs r2, #0
8002784: f8c7 3088 str.w r3, [r7, #136] ; 0x88
8002788: f8c7 208c str.w r2, [r7, #140] ; 0x8c
800278c: e9d7 8922 ldrd r8, r9, [r7, #136] ; 0x88
8002790: 4642 mov r2, r8
8002792: 464b mov r3, r9
8002794: 1891 adds r1, r2, r2
8002796: 61b9 str r1, [r7, #24]
8002798: 415b adcs r3, r3
800279a: 61fb str r3, [r7, #28]
800279c: e9d7 2306 ldrd r2, r3, [r7, #24]
80027a0: 4641 mov r1, r8
80027a2: 1851 adds r1, r2, r1
80027a4: 6139 str r1, [r7, #16]
80027a6: 4649 mov r1, r9
80027a8: 414b adcs r3, r1
80027aa: 617b str r3, [r7, #20]
80027ac: f04f 0200 mov.w r2, #0
80027b0: f04f 0300 mov.w r3, #0
80027b4: e9d7 ab04 ldrd sl, fp, [r7, #16]
80027b8: 4659 mov r1, fp
80027ba: 00cb lsls r3, r1, #3
80027bc: 4651 mov r1, sl
80027be: ea43 7351 orr.w r3, r3, r1, lsr #29
80027c2: 4651 mov r1, sl
80027c4: 00ca lsls r2, r1, #3
80027c6: 4610 mov r0, r2
80027c8: 4619 mov r1, r3
80027ca: 4603 mov r3, r0
80027cc: 4642 mov r2, r8
80027ce: 189b adds r3, r3, r2
80027d0: f8c7 3080 str.w r3, [r7, #128] ; 0x80
80027d4: 464b mov r3, r9
80027d6: 460a mov r2, r1
80027d8: eb42 0303 adc.w r3, r2, r3
80027dc: f8c7 3084 str.w r3, [r7, #132] ; 0x84
80027e0: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80027e4: 685b ldr r3, [r3, #4]
80027e6: 2200 movs r2, #0
80027e8: 67bb str r3, [r7, #120] ; 0x78
80027ea: 67fa str r2, [r7, #124] ; 0x7c
80027ec: f04f 0200 mov.w r2, #0
80027f0: f04f 0300 mov.w r3, #0
80027f4: e9d7 891e ldrd r8, r9, [r7, #120] ; 0x78
80027f8: 4649 mov r1, r9
80027fa: 008b lsls r3, r1, #2
80027fc: 4641 mov r1, r8
80027fe: ea43 7391 orr.w r3, r3, r1, lsr #30
8002802: 4641 mov r1, r8
8002804: 008a lsls r2, r1, #2
8002806: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80
800280a: f7fd fce9 bl 80001e0 <__aeabi_uldivmod>
800280e: 4602 mov r2, r0
8002810: 460b mov r3, r1
8002812: 4611 mov r1, r2
8002814: 4b38 ldr r3, [pc, #224] ; (80028f8 <UART_SetConfig+0x4e4>)
8002816: fba3 2301 umull r2, r3, r3, r1
800281a: 095b lsrs r3, r3, #5
800281c: 2264 movs r2, #100 ; 0x64
800281e: fb02 f303 mul.w r3, r2, r3
8002822: 1acb subs r3, r1, r3
8002824: 011b lsls r3, r3, #4
8002826: 3332 adds r3, #50 ; 0x32
8002828: 4a33 ldr r2, [pc, #204] ; (80028f8 <UART_SetConfig+0x4e4>)
800282a: fba2 2303 umull r2, r3, r2, r3
800282e: 095b lsrs r3, r3, #5
8002830: f003 03f0 and.w r3, r3, #240 ; 0xf0
8002834: 441c add r4, r3
8002836: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
800283a: 2200 movs r2, #0
800283c: 673b str r3, [r7, #112] ; 0x70
800283e: 677a str r2, [r7, #116] ; 0x74
8002840: e9d7 891c ldrd r8, r9, [r7, #112] ; 0x70
8002844: 4642 mov r2, r8
8002846: 464b mov r3, r9
8002848: 1891 adds r1, r2, r2
800284a: 60b9 str r1, [r7, #8]
800284c: 415b adcs r3, r3
800284e: 60fb str r3, [r7, #12]
8002850: e9d7 2302 ldrd r2, r3, [r7, #8]
8002854: 4641 mov r1, r8
8002856: 1851 adds r1, r2, r1
8002858: 6039 str r1, [r7, #0]
800285a: 4649 mov r1, r9
800285c: 414b adcs r3, r1
800285e: 607b str r3, [r7, #4]
8002860: f04f 0200 mov.w r2, #0
8002864: f04f 0300 mov.w r3, #0
8002868: e9d7 ab00 ldrd sl, fp, [r7]
800286c: 4659 mov r1, fp
800286e: 00cb lsls r3, r1, #3
8002870: 4651 mov r1, sl
8002872: ea43 7351 orr.w r3, r3, r1, lsr #29
8002876: 4651 mov r1, sl
8002878: 00ca lsls r2, r1, #3
800287a: 4610 mov r0, r2
800287c: 4619 mov r1, r3
800287e: 4603 mov r3, r0
8002880: 4642 mov r2, r8
8002882: 189b adds r3, r3, r2
8002884: 66bb str r3, [r7, #104] ; 0x68
8002886: 464b mov r3, r9
8002888: 460a mov r2, r1
800288a: eb42 0303 adc.w r3, r2, r3
800288e: 66fb str r3, [r7, #108] ; 0x6c
8002890: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002894: 685b ldr r3, [r3, #4]
8002896: 2200 movs r2, #0
8002898: 663b str r3, [r7, #96] ; 0x60
800289a: 667a str r2, [r7, #100] ; 0x64
800289c: f04f 0200 mov.w r2, #0
80028a0: f04f 0300 mov.w r3, #0
80028a4: e9d7 8918 ldrd r8, r9, [r7, #96] ; 0x60
80028a8: 4649 mov r1, r9
80028aa: 008b lsls r3, r1, #2
80028ac: 4641 mov r1, r8
80028ae: ea43 7391 orr.w r3, r3, r1, lsr #30
80028b2: 4641 mov r1, r8
80028b4: 008a lsls r2, r1, #2
80028b6: e9d7 011a ldrd r0, r1, [r7, #104] ; 0x68
80028ba: f7fd fc91 bl 80001e0 <__aeabi_uldivmod>
80028be: 4602 mov r2, r0
80028c0: 460b mov r3, r1
80028c2: 4b0d ldr r3, [pc, #52] ; (80028f8 <UART_SetConfig+0x4e4>)
80028c4: fba3 1302 umull r1, r3, r3, r2
80028c8: 095b lsrs r3, r3, #5
80028ca: 2164 movs r1, #100 ; 0x64
80028cc: fb01 f303 mul.w r3, r1, r3
80028d0: 1ad3 subs r3, r2, r3
80028d2: 011b lsls r3, r3, #4
80028d4: 3332 adds r3, #50 ; 0x32
80028d6: 4a08 ldr r2, [pc, #32] ; (80028f8 <UART_SetConfig+0x4e4>)
80028d8: fba2 2303 umull r2, r3, r2, r3
80028dc: 095b lsrs r3, r3, #5
80028de: f003 020f and.w r2, r3, #15
80028e2: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80028e6: 681b ldr r3, [r3, #0]
80028e8: 4422 add r2, r4
80028ea: 609a str r2, [r3, #8]
}
80028ec: bf00 nop
80028ee: f507 7780 add.w r7, r7, #256 ; 0x100
80028f2: 46bd mov sp, r7
80028f4: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80028f8: 51eb851f .word 0x51eb851f
080028fc <__NVIC_SetPriority>:
{
80028fc: b480 push {r7}
80028fe: b083 sub sp, #12
8002900: af00 add r7, sp, #0
8002902: 4603 mov r3, r0
8002904: 6039 str r1, [r7, #0]
8002906: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002908: f997 3007 ldrsb.w r3, [r7, #7]
800290c: 2b00 cmp r3, #0
800290e: db0a blt.n 8002926 <__NVIC_SetPriority+0x2a>
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002910: 683b ldr r3, [r7, #0]
8002912: b2da uxtb r2, r3
8002914: 490c ldr r1, [pc, #48] ; (8002948 <__NVIC_SetPriority+0x4c>)
8002916: f997 3007 ldrsb.w r3, [r7, #7]
800291a: 0112 lsls r2, r2, #4
800291c: b2d2 uxtb r2, r2
800291e: 440b add r3, r1
8002920: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
8002924: e00a b.n 800293c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002926: 683b ldr r3, [r7, #0]
8002928: b2da uxtb r2, r3
800292a: 4908 ldr r1, [pc, #32] ; (800294c <__NVIC_SetPriority+0x50>)
800292c: 79fb ldrb r3, [r7, #7]
800292e: f003 030f and.w r3, r3, #15
8002932: 3b04 subs r3, #4
8002934: 0112 lsls r2, r2, #4
8002936: b2d2 uxtb r2, r2
8002938: 440b add r3, r1
800293a: 761a strb r2, [r3, #24]
}
800293c: bf00 nop
800293e: 370c adds r7, #12
8002940: 46bd mov sp, r7
8002942: f85d 7b04 ldr.w r7, [sp], #4
8002946: 4770 bx lr
8002948: e000e100 .word 0xe000e100
800294c: e000ed00 .word 0xe000ed00
08002950 <SysTick_Handler>:
/*
SysTick handler implementation that also clears overflow flag.
*/
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
8002950: b580 push {r7, lr}
8002952: af00 add r7, sp, #0
/* Clear overflow flag */
SysTick->CTRL;
8002954: 4b05 ldr r3, [pc, #20] ; (800296c <SysTick_Handler+0x1c>)
8002956: 681b ldr r3, [r3, #0]
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
8002958: f001 fd0c bl 8004374 <xTaskGetSchedulerState>
800295c: 4603 mov r3, r0
800295e: 2b01 cmp r3, #1
8002960: d001 beq.n 8002966 <SysTick_Handler+0x16>
/* Call tick handler */
xPortSysTickHandler();
8002962: f002 faf1 bl 8004f48 <xPortSysTickHandler>
}
}
8002966: bf00 nop
8002968: bd80 pop {r7, pc}
800296a: bf00 nop
800296c: e000e010 .word 0xe000e010
08002970 <SVC_Setup>:
#endif /* SysTick */
/*
Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
8002970: b580 push {r7, lr}
8002972: af00 add r7, sp, #0
#if (__ARM_ARCH_7A__ == 0U)
/* Service Call interrupt might be configured before kernel start */
/* and when its priority is lower or equal to BASEPRI, svc intruction */
/* causes a Hard Fault. */
NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
8002974: 2100 movs r1, #0
8002976: f06f 0004 mvn.w r0, #4
800297a: f7ff ffbf bl 80028fc <__NVIC_SetPriority>
#endif
}
800297e: bf00 nop
8002980: bd80 pop {r7, pc}
...
08002984 <osKernelInitialize>:
static uint32_t OS_Tick_GetOverflow (void);
/* Get OS Tick interval */
static uint32_t OS_Tick_GetInterval (void);
/*---------------------------------------------------------------------------*/
osStatus_t osKernelInitialize (void) {
8002984: b480 push {r7}
8002986: b083 sub sp, #12
8002988: af00 add r7, sp, #0
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
800298a: f3ef 8305 mrs r3, IPSR
800298e: 603b str r3, [r7, #0]
return(result);
8002990: 683b ldr r3, [r7, #0]
osStatus_t stat;
if (IS_IRQ()) {
8002992: 2b00 cmp r3, #0
8002994: d003 beq.n 800299e <osKernelInitialize+0x1a>
stat = osErrorISR;
8002996: f06f 0305 mvn.w r3, #5
800299a: 607b str r3, [r7, #4]
800299c: e00c b.n 80029b8 <osKernelInitialize+0x34>
}
else {
if (KernelState == osKernelInactive) {
800299e: 4b0a ldr r3, [pc, #40] ; (80029c8 <osKernelInitialize+0x44>)
80029a0: 681b ldr r3, [r3, #0]
80029a2: 2b00 cmp r3, #0
80029a4: d105 bne.n 80029b2 <osKernelInitialize+0x2e>
EvrFreeRTOSSetup(0U);
#endif
#if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
vPortDefineHeapRegions (configHEAP_5_REGIONS);
#endif
KernelState = osKernelReady;
80029a6: 4b08 ldr r3, [pc, #32] ; (80029c8 <osKernelInitialize+0x44>)
80029a8: 2201 movs r2, #1
80029aa: 601a str r2, [r3, #0]
stat = osOK;
80029ac: 2300 movs r3, #0
80029ae: 607b str r3, [r7, #4]
80029b0: e002 b.n 80029b8 <osKernelInitialize+0x34>
} else {
stat = osError;
80029b2: f04f 33ff mov.w r3, #4294967295
80029b6: 607b str r3, [r7, #4]
}
}
return (stat);
80029b8: 687b ldr r3, [r7, #4]
}
80029ba: 4618 mov r0, r3
80029bc: 370c adds r7, #12
80029be: 46bd mov sp, r7
80029c0: f85d 7b04 ldr.w r7, [sp], #4
80029c4: 4770 bx lr
80029c6: bf00 nop
80029c8: 2000012c .word 0x2000012c
080029cc <osKernelStart>:
}
return (state);
}
osStatus_t osKernelStart (void) {
80029cc: b580 push {r7, lr}
80029ce: b082 sub sp, #8
80029d0: af00 add r7, sp, #0
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
80029d2: f3ef 8305 mrs r3, IPSR
80029d6: 603b str r3, [r7, #0]
return(result);
80029d8: 683b ldr r3, [r7, #0]
osStatus_t stat;
if (IS_IRQ()) {
80029da: 2b00 cmp r3, #0
80029dc: d003 beq.n 80029e6 <osKernelStart+0x1a>
stat = osErrorISR;
80029de: f06f 0305 mvn.w r3, #5
80029e2: 607b str r3, [r7, #4]
80029e4: e010 b.n 8002a08 <osKernelStart+0x3c>
}
else {
if (KernelState == osKernelReady) {
80029e6: 4b0b ldr r3, [pc, #44] ; (8002a14 <osKernelStart+0x48>)
80029e8: 681b ldr r3, [r3, #0]
80029ea: 2b01 cmp r3, #1
80029ec: d109 bne.n 8002a02 <osKernelStart+0x36>
/* Ensure SVC priority is at the reset value */
SVC_Setup();
80029ee: f7ff ffbf bl 8002970 <SVC_Setup>
/* Change state to enable IRQ masking check */
KernelState = osKernelRunning;
80029f2: 4b08 ldr r3, [pc, #32] ; (8002a14 <osKernelStart+0x48>)
80029f4: 2202 movs r2, #2
80029f6: 601a str r2, [r3, #0]
/* Start the kernel scheduler */
vTaskStartScheduler();
80029f8: f001 f860 bl 8003abc <vTaskStartScheduler>
stat = osOK;
80029fc: 2300 movs r3, #0
80029fe: 607b str r3, [r7, #4]
8002a00: e002 b.n 8002a08 <osKernelStart+0x3c>
} else {
stat = osError;
8002a02: f04f 33ff mov.w r3, #4294967295
8002a06: 607b str r3, [r7, #4]
}
}
return (stat);
8002a08: 687b ldr r3, [r7, #4]
}
8002a0a: 4618 mov r0, r3
8002a0c: 3708 adds r7, #8
8002a0e: 46bd mov sp, r7
8002a10: bd80 pop {r7, pc}
8002a12: bf00 nop
8002a14: 2000012c .word 0x2000012c
08002a18 <osThreadNew>:
return (configCPU_CLOCK_HZ);
}
/*---------------------------------------------------------------------------*/
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
8002a18: b580 push {r7, lr}
8002a1a: b08e sub sp, #56 ; 0x38
8002a1c: af04 add r7, sp, #16
8002a1e: 60f8 str r0, [r7, #12]
8002a20: 60b9 str r1, [r7, #8]
8002a22: 607a str r2, [r7, #4]
uint32_t stack;
TaskHandle_t hTask;
UBaseType_t prio;
int32_t mem;
hTask = NULL;
8002a24: 2300 movs r3, #0
8002a26: 613b str r3, [r7, #16]
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
8002a28: f3ef 8305 mrs r3, IPSR
8002a2c: 617b str r3, [r7, #20]
return(result);
8002a2e: 697b ldr r3, [r7, #20]
if (!IS_IRQ() && (func != NULL)) {
8002a30: 2b00 cmp r3, #0
8002a32: d17e bne.n 8002b32 <osThreadNew+0x11a>
8002a34: 68fb ldr r3, [r7, #12]
8002a36: 2b00 cmp r3, #0
8002a38: d07b beq.n 8002b32 <osThreadNew+0x11a>
stack = configMINIMAL_STACK_SIZE;
8002a3a: 2380 movs r3, #128 ; 0x80
8002a3c: 623b str r3, [r7, #32]
prio = (UBaseType_t)osPriorityNormal;
8002a3e: 2318 movs r3, #24
8002a40: 61fb str r3, [r7, #28]
name = NULL;
8002a42: 2300 movs r3, #0
8002a44: 627b str r3, [r7, #36] ; 0x24
mem = -1;
8002a46: f04f 33ff mov.w r3, #4294967295
8002a4a: 61bb str r3, [r7, #24]
if (attr != NULL) {
8002a4c: 687b ldr r3, [r7, #4]
8002a4e: 2b00 cmp r3, #0
8002a50: d045 beq.n 8002ade <osThreadNew+0xc6>
if (attr->name != NULL) {
8002a52: 687b ldr r3, [r7, #4]
8002a54: 681b ldr r3, [r3, #0]
8002a56: 2b00 cmp r3, #0
8002a58: d002 beq.n 8002a60 <osThreadNew+0x48>
name = attr->name;
8002a5a: 687b ldr r3, [r7, #4]
8002a5c: 681b ldr r3, [r3, #0]
8002a5e: 627b str r3, [r7, #36] ; 0x24
}
if (attr->priority != osPriorityNone) {
8002a60: 687b ldr r3, [r7, #4]
8002a62: 699b ldr r3, [r3, #24]
8002a64: 2b00 cmp r3, #0
8002a66: d002 beq.n 8002a6e <osThreadNew+0x56>
prio = (UBaseType_t)attr->priority;
8002a68: 687b ldr r3, [r7, #4]
8002a6a: 699b ldr r3, [r3, #24]
8002a6c: 61fb str r3, [r7, #28]
}
if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
8002a6e: 69fb ldr r3, [r7, #28]
8002a70: 2b00 cmp r3, #0
8002a72: d008 beq.n 8002a86 <osThreadNew+0x6e>
8002a74: 69fb ldr r3, [r7, #28]
8002a76: 2b38 cmp r3, #56 ; 0x38
8002a78: d805 bhi.n 8002a86 <osThreadNew+0x6e>
8002a7a: 687b ldr r3, [r7, #4]
8002a7c: 685b ldr r3, [r3, #4]
8002a7e: f003 0301 and.w r3, r3, #1
8002a82: 2b00 cmp r3, #0
8002a84: d001 beq.n 8002a8a <osThreadNew+0x72>
return (NULL);
8002a86: 2300 movs r3, #0
8002a88: e054 b.n 8002b34 <osThreadNew+0x11c>
}
if (attr->stack_size > 0U) {
8002a8a: 687b ldr r3, [r7, #4]
8002a8c: 695b ldr r3, [r3, #20]
8002a8e: 2b00 cmp r3, #0
8002a90: d003 beq.n 8002a9a <osThreadNew+0x82>
/* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */
/* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
stack = attr->stack_size / sizeof(StackType_t);
8002a92: 687b ldr r3, [r7, #4]
8002a94: 695b ldr r3, [r3, #20]
8002a96: 089b lsrs r3, r3, #2
8002a98: 623b str r3, [r7, #32]
}
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
8002a9a: 687b ldr r3, [r7, #4]
8002a9c: 689b ldr r3, [r3, #8]
8002a9e: 2b00 cmp r3, #0
8002aa0: d00e beq.n 8002ac0 <osThreadNew+0xa8>
8002aa2: 687b ldr r3, [r7, #4]
8002aa4: 68db ldr r3, [r3, #12]
8002aa6: 2ba7 cmp r3, #167 ; 0xa7
8002aa8: d90a bls.n 8002ac0 <osThreadNew+0xa8>
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
8002aaa: 687b ldr r3, [r7, #4]
8002aac: 691b ldr r3, [r3, #16]
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
8002aae: 2b00 cmp r3, #0
8002ab0: d006 beq.n 8002ac0 <osThreadNew+0xa8>
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
8002ab2: 687b ldr r3, [r7, #4]
8002ab4: 695b ldr r3, [r3, #20]
8002ab6: 2b00 cmp r3, #0
8002ab8: d002 beq.n 8002ac0 <osThreadNew+0xa8>
mem = 1;
8002aba: 2301 movs r3, #1
8002abc: 61bb str r3, [r7, #24]
8002abe: e010 b.n 8002ae2 <osThreadNew+0xca>
}
else {
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
8002ac0: 687b ldr r3, [r7, #4]
8002ac2: 689b ldr r3, [r3, #8]
8002ac4: 2b00 cmp r3, #0
8002ac6: d10c bne.n 8002ae2 <osThreadNew+0xca>
8002ac8: 687b ldr r3, [r7, #4]
8002aca: 68db ldr r3, [r3, #12]
8002acc: 2b00 cmp r3, #0
8002ace: d108 bne.n 8002ae2 <osThreadNew+0xca>
8002ad0: 687b ldr r3, [r7, #4]
8002ad2: 691b ldr r3, [r3, #16]
8002ad4: 2b00 cmp r3, #0
8002ad6: d104 bne.n 8002ae2 <osThreadNew+0xca>
mem = 0;
8002ad8: 2300 movs r3, #0
8002ada: 61bb str r3, [r7, #24]
8002adc: e001 b.n 8002ae2 <osThreadNew+0xca>
}
}
}
else {
mem = 0;
8002ade: 2300 movs r3, #0
8002ae0: 61bb str r3, [r7, #24]
}
if (mem == 1) {
8002ae2: 69bb ldr r3, [r7, #24]
8002ae4: 2b01 cmp r3, #1
8002ae6: d110 bne.n 8002b0a <osThreadNew+0xf2>
#if (configSUPPORT_STATIC_ALLOCATION == 1)
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
8002ae8: 687b ldr r3, [r7, #4]
8002aea: 691b ldr r3, [r3, #16]
(StaticTask_t *)attr->cb_mem);
8002aec: 687a ldr r2, [r7, #4]
8002aee: 6892 ldr r2, [r2, #8]
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
8002af0: 9202 str r2, [sp, #8]
8002af2: 9301 str r3, [sp, #4]
8002af4: 69fb ldr r3, [r7, #28]
8002af6: 9300 str r3, [sp, #0]
8002af8: 68bb ldr r3, [r7, #8]
8002afa: 6a3a ldr r2, [r7, #32]
8002afc: 6a79 ldr r1, [r7, #36] ; 0x24
8002afe: 68f8 ldr r0, [r7, #12]
8002b00: f000 fdf0 bl 80036e4 <xTaskCreateStatic>
8002b04: 4603 mov r3, r0
8002b06: 613b str r3, [r7, #16]
8002b08: e013 b.n 8002b32 <osThreadNew+0x11a>
#endif
}
else {
if (mem == 0) {
8002b0a: 69bb ldr r3, [r7, #24]
8002b0c: 2b00 cmp r3, #0
8002b0e: d110 bne.n 8002b32 <osThreadNew+0x11a>
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
8002b10: 6a3b ldr r3, [r7, #32]
8002b12: b29a uxth r2, r3
8002b14: f107 0310 add.w r3, r7, #16
8002b18: 9301 str r3, [sp, #4]
8002b1a: 69fb ldr r3, [r7, #28]
8002b1c: 9300 str r3, [sp, #0]
8002b1e: 68bb ldr r3, [r7, #8]
8002b20: 6a79 ldr r1, [r7, #36] ; 0x24
8002b22: 68f8 ldr r0, [r7, #12]
8002b24: f000 fe3b bl 800379e <xTaskCreate>
8002b28: 4603 mov r3, r0
8002b2a: 2b01 cmp r3, #1
8002b2c: d001 beq.n 8002b32 <osThreadNew+0x11a>
hTask = NULL;
8002b2e: 2300 movs r3, #0
8002b30: 613b str r3, [r7, #16]
#endif
}
}
}
return ((osThreadId_t)hTask);
8002b32: 693b ldr r3, [r7, #16]
}
8002b34: 4618 mov r0, r3
8002b36: 3728 adds r7, #40 ; 0x28
8002b38: 46bd mov sp, r7
8002b3a: bd80 pop {r7, pc}
08002b3c <vApplicationGetIdleTaskMemory>:
/*
vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
8002b3c: b480 push {r7}
8002b3e: b085 sub sp, #20
8002b40: af00 add r7, sp, #0
8002b42: 60f8 str r0, [r7, #12]
8002b44: 60b9 str r1, [r7, #8]
8002b46: 607a str r2, [r7, #4]
/* Idle task control block and stack */
static StaticTask_t Idle_TCB;
static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE];
*ppxIdleTaskTCBBuffer = &Idle_TCB;
8002b48: 68fb ldr r3, [r7, #12]
8002b4a: 4a07 ldr r2, [pc, #28] ; (8002b68 <vApplicationGetIdleTaskMemory+0x2c>)
8002b4c: 601a str r2, [r3, #0]
*ppxIdleTaskStackBuffer = &Idle_Stack[0];
8002b4e: 68bb ldr r3, [r7, #8]
8002b50: 4a06 ldr r2, [pc, #24] ; (8002b6c <vApplicationGetIdleTaskMemory+0x30>)
8002b52: 601a str r2, [r3, #0]
*pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
8002b54: 687b ldr r3, [r7, #4]
8002b56: 2280 movs r2, #128 ; 0x80
8002b58: 601a str r2, [r3, #0]
}
8002b5a: bf00 nop
8002b5c: 3714 adds r7, #20
8002b5e: 46bd mov sp, r7
8002b60: f85d 7b04 ldr.w r7, [sp], #4
8002b64: 4770 bx lr
8002b66: bf00 nop
8002b68: 20000130 .word 0x20000130
8002b6c: 200001d8 .word 0x200001d8
08002b70 <vApplicationGetTimerTaskMemory>:
/*
vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
8002b70: b480 push {r7}
8002b72: b085 sub sp, #20
8002b74: af00 add r7, sp, #0
8002b76: 60f8 str r0, [r7, #12]
8002b78: 60b9 str r1, [r7, #8]
8002b7a: 607a str r2, [r7, #4]
/* Timer task control block and stack */
static StaticTask_t Timer_TCB;
static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH];
*ppxTimerTaskTCBBuffer = &Timer_TCB;
8002b7c: 68fb ldr r3, [r7, #12]
8002b7e: 4a07 ldr r2, [pc, #28] ; (8002b9c <vApplicationGetTimerTaskMemory+0x2c>)
8002b80: 601a str r2, [r3, #0]
*ppxTimerTaskStackBuffer = &Timer_Stack[0];
8002b82: 68bb ldr r3, [r7, #8]
8002b84: 4a06 ldr r2, [pc, #24] ; (8002ba0 <vApplicationGetTimerTaskMemory+0x30>)
8002b86: 601a str r2, [r3, #0]
*pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
8002b88: 687b ldr r3, [r7, #4]
8002b8a: f44f 7280 mov.w r2, #256 ; 0x100
8002b8e: 601a str r2, [r3, #0]
}
8002b90: bf00 nop
8002b92: 3714 adds r7, #20
8002b94: 46bd mov sp, r7
8002b96: f85d 7b04 ldr.w r7, [sp], #4
8002b9a: 4770 bx lr
8002b9c: 200003d8 .word 0x200003d8
8002ba0: 20000480 .word 0x20000480
08002ba4 <vListInitialise>:
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( List_t * const pxList )
{
8002ba4: b480 push {r7}
8002ba6: b083 sub sp, #12
8002ba8: af00 add r7, sp, #0
8002baa: 6078 str r0, [r7, #4]
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8002bac: 687b ldr r3, [r7, #4]
8002bae: f103 0208 add.w r2, r3, #8
8002bb2: 687b ldr r3, [r7, #4]
8002bb4: 605a str r2, [r3, #4]
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
8002bb6: 687b ldr r3, [r7, #4]
8002bb8: f04f 32ff mov.w r2, #4294967295
8002bbc: 609a str r2, [r3, #8]
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8002bbe: 687b ldr r3, [r7, #4]
8002bc0: f103 0208 add.w r2, r3, #8
8002bc4: 687b ldr r3, [r7, #4]
8002bc6: 60da str r2, [r3, #12]
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8002bc8: 687b ldr r3, [r7, #4]
8002bca: f103 0208 add.w r2, r3, #8
8002bce: 687b ldr r3, [r7, #4]
8002bd0: 611a str r2, [r3, #16]
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
8002bd2: 687b ldr r3, [r7, #4]
8002bd4: 2200 movs r2, #0
8002bd6: 601a str r2, [r3, #0]
/* Write known values into the list if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
8002bd8: bf00 nop
8002bda: 370c adds r7, #12
8002bdc: 46bd mov sp, r7
8002bde: f85d 7b04 ldr.w r7, [sp], #4
8002be2: 4770 bx lr
08002be4 <vListInitialiseItem>:
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
8002be4: b480 push {r7}
8002be6: b083 sub sp, #12
8002be8: af00 add r7, sp, #0
8002bea: 6078 str r0, [r7, #4]
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
8002bec: 687b ldr r3, [r7, #4]
8002bee: 2200 movs r2, #0
8002bf0: 611a str r2, [r3, #16]
/* Write known values into the list item if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
8002bf2: bf00 nop
8002bf4: 370c adds r7, #12
8002bf6: 46bd mov sp, r7
8002bf8: f85d 7b04 ldr.w r7, [sp], #4
8002bfc: 4770 bx lr
08002bfe <vListInsertEnd>:
/*-----------------------------------------------------------*/
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8002bfe: b480 push {r7}
8002c00: b085 sub sp, #20
8002c02: af00 add r7, sp, #0
8002c04: 6078 str r0, [r7, #4]
8002c06: 6039 str r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
8002c08: 687b ldr r3, [r7, #4]
8002c0a: 685b ldr r3, [r3, #4]
8002c0c: 60fb str r3, [r7, #12]
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
listGET_OWNER_OF_NEXT_ENTRY(). */
pxNewListItem->pxNext = pxIndex;
8002c0e: 683b ldr r3, [r7, #0]
8002c10: 68fa ldr r2, [r7, #12]
8002c12: 605a str r2, [r3, #4]
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
8002c14: 68fb ldr r3, [r7, #12]
8002c16: 689a ldr r2, [r3, #8]
8002c18: 683b ldr r3, [r7, #0]
8002c1a: 609a str r2, [r3, #8]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
pxIndex->pxPrevious->pxNext = pxNewListItem;
8002c1c: 68fb ldr r3, [r7, #12]
8002c1e: 689b ldr r3, [r3, #8]
8002c20: 683a ldr r2, [r7, #0]
8002c22: 605a str r2, [r3, #4]
pxIndex->pxPrevious = pxNewListItem;
8002c24: 68fb ldr r3, [r7, #12]
8002c26: 683a ldr r2, [r7, #0]
8002c28: 609a str r2, [r3, #8]
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
8002c2a: 683b ldr r3, [r7, #0]
8002c2c: 687a ldr r2, [r7, #4]
8002c2e: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8002c30: 687b ldr r3, [r7, #4]
8002c32: 681b ldr r3, [r3, #0]
8002c34: 1c5a adds r2, r3, #1
8002c36: 687b ldr r3, [r7, #4]
8002c38: 601a str r2, [r3, #0]
}
8002c3a: bf00 nop
8002c3c: 3714 adds r7, #20
8002c3e: 46bd mov sp, r7
8002c40: f85d 7b04 ldr.w r7, [sp], #4
8002c44: 4770 bx lr
08002c46 <vListInsert>:
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8002c46: b480 push {r7}
8002c48: b085 sub sp, #20
8002c4a: af00 add r7, sp, #0
8002c4c: 6078 str r0, [r7, #4]
8002c4e: 6039 str r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
8002c50: 683b ldr r3, [r7, #0]
8002c52: 681b ldr r3, [r3, #0]
8002c54: 60bb str r3, [r7, #8]
new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
8002c56: 68bb ldr r3, [r7, #8]
8002c58: f1b3 3fff cmp.w r3, #4294967295
8002c5c: d103 bne.n 8002c66 <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
8002c5e: 687b ldr r3, [r7, #4]
8002c60: 691b ldr r3, [r3, #16]
8002c62: 60fb str r3, [r7, #12]
8002c64: e00c b.n 8002c80 <vListInsert+0x3a>
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
8002c66: 687b ldr r3, [r7, #4]
8002c68: 3308 adds r3, #8
8002c6a: 60fb str r3, [r7, #12]
8002c6c: e002 b.n 8002c74 <vListInsert+0x2e>
8002c6e: 68fb ldr r3, [r7, #12]
8002c70: 685b ldr r3, [r3, #4]
8002c72: 60fb str r3, [r7, #12]
8002c74: 68fb ldr r3, [r7, #12]
8002c76: 685b ldr r3, [r3, #4]
8002c78: 681b ldr r3, [r3, #0]
8002c7a: 68ba ldr r2, [r7, #8]
8002c7c: 429a cmp r2, r3
8002c7e: d2f6 bcs.n 8002c6e <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
8002c80: 68fb ldr r3, [r7, #12]
8002c82: 685a ldr r2, [r3, #4]
8002c84: 683b ldr r3, [r7, #0]
8002c86: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
8002c88: 683b ldr r3, [r7, #0]
8002c8a: 685b ldr r3, [r3, #4]
8002c8c: 683a ldr r2, [r7, #0]
8002c8e: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
8002c90: 683b ldr r3, [r7, #0]
8002c92: 68fa ldr r2, [r7, #12]
8002c94: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
8002c96: 68fb ldr r3, [r7, #12]
8002c98: 683a ldr r2, [r7, #0]
8002c9a: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pxContainer = pxList;
8002c9c: 683b ldr r3, [r7, #0]
8002c9e: 687a ldr r2, [r7, #4]
8002ca0: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8002ca2: 687b ldr r3, [r7, #4]
8002ca4: 681b ldr r3, [r3, #0]
8002ca6: 1c5a adds r2, r3, #1
8002ca8: 687b ldr r3, [r7, #4]
8002caa: 601a str r2, [r3, #0]
}
8002cac: bf00 nop
8002cae: 3714 adds r7, #20
8002cb0: 46bd mov sp, r7
8002cb2: f85d 7b04 ldr.w r7, [sp], #4
8002cb6: 4770 bx lr
08002cb8 <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
8002cb8: b480 push {r7}
8002cba: b085 sub sp, #20
8002cbc: af00 add r7, sp, #0
8002cbe: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
8002cc0: 687b ldr r3, [r7, #4]
8002cc2: 691b ldr r3, [r3, #16]
8002cc4: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
8002cc6: 687b ldr r3, [r7, #4]
8002cc8: 685b ldr r3, [r3, #4]
8002cca: 687a ldr r2, [r7, #4]
8002ccc: 6892 ldr r2, [r2, #8]
8002cce: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
8002cd0: 687b ldr r3, [r7, #4]
8002cd2: 689b ldr r3, [r3, #8]
8002cd4: 687a ldr r2, [r7, #4]
8002cd6: 6852 ldr r2, [r2, #4]
8002cd8: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
8002cda: 68fb ldr r3, [r7, #12]
8002cdc: 685b ldr r3, [r3, #4]
8002cde: 687a ldr r2, [r7, #4]
8002ce0: 429a cmp r2, r3
8002ce2: d103 bne.n 8002cec <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
8002ce4: 687b ldr r3, [r7, #4]
8002ce6: 689a ldr r2, [r3, #8]
8002ce8: 68fb ldr r3, [r7, #12]
8002cea: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
8002cec: 687b ldr r3, [r7, #4]
8002cee: 2200 movs r2, #0
8002cf0: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
8002cf2: 68fb ldr r3, [r7, #12]
8002cf4: 681b ldr r3, [r3, #0]
8002cf6: 1e5a subs r2, r3, #1
8002cf8: 68fb ldr r3, [r7, #12]
8002cfa: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
8002cfc: 68fb ldr r3, [r7, #12]
8002cfe: 681b ldr r3, [r3, #0]
}
8002d00: 4618 mov r0, r3
8002d02: 3714 adds r7, #20
8002d04: 46bd mov sp, r7
8002d06: f85d 7b04 ldr.w r7, [sp], #4
8002d0a: 4770 bx lr
08002d0c <xQueueGenericReset>:
} \
taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
8002d0c: b580 push {r7, lr}
8002d0e: b084 sub sp, #16
8002d10: af00 add r7, sp, #0
8002d12: 6078 str r0, [r7, #4]
8002d14: 6039 str r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
8002d16: 687b ldr r3, [r7, #4]
8002d18: 60fb str r3, [r7, #12]
configASSERT( pxQueue );
8002d1a: 68fb ldr r3, [r7, #12]
8002d1c: 2b00 cmp r3, #0
8002d1e: d10a bne.n 8002d36 <xQueueGenericReset+0x2a>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
8002d20: f04f 0350 mov.w r3, #80 ; 0x50
8002d24: f383 8811 msr BASEPRI, r3
8002d28: f3bf 8f6f isb sy
8002d2c: f3bf 8f4f dsb sy
8002d30: 60bb str r3, [r7, #8]
" msr basepri, %0 \n" \
" isb \n" \
" dsb \n" \
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
8002d32: bf00 nop
8002d34: e7fe b.n 8002d34 <xQueueGenericReset+0x28>
taskENTER_CRITICAL();
8002d36: f002 f875 bl 8004e24 <vPortEnterCritical>
{
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8002d3a: 68fb ldr r3, [r7, #12]
8002d3c: 681a ldr r2, [r3, #0]
8002d3e: 68fb ldr r3, [r7, #12]
8002d40: 6bdb ldr r3, [r3, #60] ; 0x3c
8002d42: 68f9 ldr r1, [r7, #12]
8002d44: 6c09 ldr r1, [r1, #64] ; 0x40
8002d46: fb01 f303 mul.w r3, r1, r3
8002d4a: 441a add r2, r3
8002d4c: 68fb ldr r3, [r7, #12]
8002d4e: 609a str r2, [r3, #8]
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
8002d50: 68fb ldr r3, [r7, #12]
8002d52: 2200 movs r2, #0
8002d54: 639a str r2, [r3, #56] ; 0x38
pxQueue->pcWriteTo = pxQueue->pcHead;
8002d56: 68fb ldr r3, [r7, #12]
8002d58: 681a ldr r2, [r3, #0]
8002d5a: 68fb ldr r3, [r7, #12]
8002d5c: 605a str r2, [r3, #4]
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8002d5e: 68fb ldr r3, [r7, #12]
8002d60: 681a ldr r2, [r3, #0]
8002d62: 68fb ldr r3, [r7, #12]
8002d64: 6bdb ldr r3, [r3, #60] ; 0x3c
8002d66: 3b01 subs r3, #1
8002d68: 68f9 ldr r1, [r7, #12]
8002d6a: 6c09 ldr r1, [r1, #64] ; 0x40
8002d6c: fb01 f303 mul.w r3, r1, r3
8002d70: 441a add r2, r3
8002d72: 68fb ldr r3, [r7, #12]
8002d74: 60da str r2, [r3, #12]
pxQueue->cRxLock = queueUNLOCKED;
8002d76: 68fb ldr r3, [r7, #12]
8002d78: 22ff movs r2, #255 ; 0xff
8002d7a: f883 2044 strb.w r2, [r3, #68] ; 0x44
pxQueue->cTxLock = queueUNLOCKED;
8002d7e: 68fb ldr r3, [r7, #12]
8002d80: 22ff movs r2, #255 ; 0xff
8002d82: f883 2045 strb.w r2, [r3, #69] ; 0x45
if( xNewQueue == pdFALSE )
8002d86: 683b ldr r3, [r7, #0]
8002d88: 2b00 cmp r3, #0
8002d8a: d114 bne.n 8002db6 <xQueueGenericReset+0xaa>
/* If there are tasks blocked waiting to read from the queue, then
the tasks will remain blocked as after this function exits the queue
will still be empty. If there are tasks blocked waiting to write to
the queue, then one should be unblocked as after this function exits
it will be possible to write to it. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8002d8c: 68fb ldr r3, [r7, #12]
8002d8e: 691b ldr r3, [r3, #16]
8002d90: 2b00 cmp r3, #0
8002d92: d01a beq.n 8002dca <xQueueGenericReset+0xbe>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
8002d94: 68fb ldr r3, [r7, #12]
8002d96: 3310 adds r3, #16
8002d98: 4618 mov r0, r3
8002d9a: f001 f929 bl 8003ff0 <xTaskRemoveFromEventList>
8002d9e: 4603 mov r3, r0
8002da0: 2b00 cmp r3, #0
8002da2: d012 beq.n 8002dca <xQueueGenericReset+0xbe>
{
queueYIELD_IF_USING_PREEMPTION();
8002da4: 4b0c ldr r3, [pc, #48] ; (8002dd8 <xQueueGenericReset+0xcc>)
8002da6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8002daa: 601a str r2, [r3, #0]
8002dac: f3bf 8f4f dsb sy
8002db0: f3bf 8f6f isb sy
8002db4: e009 b.n 8002dca <xQueueGenericReset+0xbe>
}
}
else
{
/* Ensure the event queues start in the correct state. */
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
8002db6: 68fb ldr r3, [r7, #12]
8002db8: 3310 adds r3, #16
8002dba: 4618 mov r0, r3
8002dbc: f7ff fef2 bl 8002ba4 <vListInitialise>
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
8002dc0: 68fb ldr r3, [r7, #12]
8002dc2: 3324 adds r3, #36 ; 0x24
8002dc4: 4618 mov r0, r3
8002dc6: f7ff feed bl 8002ba4 <vListInitialise>
}
}
taskEXIT_CRITICAL();
8002dca: f002 f85b bl 8004e84 <vPortExitCritical>
/* A value is returned for calling semantic consistency with previous
versions. */
return pdPASS;
8002dce: 2301 movs r3, #1
}
8002dd0: 4618 mov r0, r3
8002dd2: 3710 adds r7, #16
8002dd4: 46bd mov sp, r7
8002dd6: bd80 pop {r7, pc}
8002dd8: e000ed04 .word 0xe000ed04
08002ddc <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
{
8002ddc: b580 push {r7, lr}
8002dde: b08e sub sp, #56 ; 0x38
8002de0: af02 add r7, sp, #8
8002de2: 60f8 str r0, [r7, #12]
8002de4: 60b9 str r1, [r7, #8]
8002de6: 607a str r2, [r7, #4]
8002de8: 603b str r3, [r7, #0]
Queue_t *pxNewQueue;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
8002dea: 68fb ldr r3, [r7, #12]
8002dec: 2b00 cmp r3, #0
8002dee: d10a bne.n 8002e06 <xQueueGenericCreateStatic+0x2a>
__asm volatile
8002df0: f04f 0350 mov.w r3, #80 ; 0x50
8002df4: f383 8811 msr BASEPRI, r3
8002df8: f3bf 8f6f isb sy
8002dfc: f3bf 8f4f dsb sy
8002e00: 62bb str r3, [r7, #40] ; 0x28
}
8002e02: bf00 nop
8002e04: e7fe b.n 8002e04 <xQueueGenericCreateStatic+0x28>
/* The StaticQueue_t structure and the queue storage area must be
supplied. */
configASSERT( pxStaticQueue != NULL );
8002e06: 683b ldr r3, [r7, #0]
8002e08: 2b00 cmp r3, #0
8002e0a: d10a bne.n 8002e22 <xQueueGenericCreateStatic+0x46>
__asm volatile
8002e0c: f04f 0350 mov.w r3, #80 ; 0x50
8002e10: f383 8811 msr BASEPRI, r3
8002e14: f3bf 8f6f isb sy
8002e18: f3bf 8f4f dsb sy
8002e1c: 627b str r3, [r7, #36] ; 0x24
}
8002e1e: bf00 nop
8002e20: e7fe b.n 8002e20 <xQueueGenericCreateStatic+0x44>
/* A queue storage area should be provided if the item size is not 0, and
should not be provided if the item size is 0. */
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
8002e22: 687b ldr r3, [r7, #4]
8002e24: 2b00 cmp r3, #0
8002e26: d002 beq.n 8002e2e <xQueueGenericCreateStatic+0x52>
8002e28: 68bb ldr r3, [r7, #8]
8002e2a: 2b00 cmp r3, #0
8002e2c: d001 beq.n 8002e32 <xQueueGenericCreateStatic+0x56>
8002e2e: 2301 movs r3, #1
8002e30: e000 b.n 8002e34 <xQueueGenericCreateStatic+0x58>
8002e32: 2300 movs r3, #0
8002e34: 2b00 cmp r3, #0
8002e36: d10a bne.n 8002e4e <xQueueGenericCreateStatic+0x72>
__asm volatile
8002e38: f04f 0350 mov.w r3, #80 ; 0x50
8002e3c: f383 8811 msr BASEPRI, r3
8002e40: f3bf 8f6f isb sy
8002e44: f3bf 8f4f dsb sy
8002e48: 623b str r3, [r7, #32]
}
8002e4a: bf00 nop
8002e4c: e7fe b.n 8002e4c <xQueueGenericCreateStatic+0x70>
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
8002e4e: 687b ldr r3, [r7, #4]
8002e50: 2b00 cmp r3, #0
8002e52: d102 bne.n 8002e5a <xQueueGenericCreateStatic+0x7e>
8002e54: 68bb ldr r3, [r7, #8]
8002e56: 2b00 cmp r3, #0
8002e58: d101 bne.n 8002e5e <xQueueGenericCreateStatic+0x82>
8002e5a: 2301 movs r3, #1
8002e5c: e000 b.n 8002e60 <xQueueGenericCreateStatic+0x84>
8002e5e: 2300 movs r3, #0
8002e60: 2b00 cmp r3, #0
8002e62: d10a bne.n 8002e7a <xQueueGenericCreateStatic+0x9e>
__asm volatile
8002e64: f04f 0350 mov.w r3, #80 ; 0x50
8002e68: f383 8811 msr BASEPRI, r3
8002e6c: f3bf 8f6f isb sy
8002e70: f3bf 8f4f dsb sy
8002e74: 61fb str r3, [r7, #28]
}
8002e76: bf00 nop
8002e78: e7fe b.n 8002e78 <xQueueGenericCreateStatic+0x9c>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
the real queue and semaphore structures. */
volatile size_t xSize = sizeof( StaticQueue_t );
8002e7a: 2350 movs r3, #80 ; 0x50
8002e7c: 617b str r3, [r7, #20]
configASSERT( xSize == sizeof( Queue_t ) );
8002e7e: 697b ldr r3, [r7, #20]
8002e80: 2b50 cmp r3, #80 ; 0x50
8002e82: d00a beq.n 8002e9a <xQueueGenericCreateStatic+0xbe>
__asm volatile
8002e84: f04f 0350 mov.w r3, #80 ; 0x50
8002e88: f383 8811 msr BASEPRI, r3
8002e8c: f3bf 8f6f isb sy
8002e90: f3bf 8f4f dsb sy
8002e94: 61bb str r3, [r7, #24]
}
8002e96: bf00 nop
8002e98: e7fe b.n 8002e98 <xQueueGenericCreateStatic+0xbc>
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
8002e9a: 697b ldr r3, [r7, #20]
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
The address of a statically allocated storage area was also passed in
but is already set. */
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
8002e9c: 683b ldr r3, [r7, #0]
8002e9e: 62fb str r3, [r7, #44] ; 0x2c
if( pxNewQueue != NULL )
8002ea0: 6afb ldr r3, [r7, #44] ; 0x2c
8002ea2: 2b00 cmp r3, #0
8002ea4: d00d beq.n 8002ec2 <xQueueGenericCreateStatic+0xe6>
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* Queues can be allocated wither statically or dynamically, so
note this queue was allocated statically in case the queue is
later deleted. */
pxNewQueue->ucStaticallyAllocated = pdTRUE;
8002ea6: 6afb ldr r3, [r7, #44] ; 0x2c
8002ea8: 2201 movs r2, #1
8002eaa: f883 2046 strb.w r2, [r3, #70] ; 0x46
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
8002eae: f897 2038 ldrb.w r2, [r7, #56] ; 0x38
8002eb2: 6afb ldr r3, [r7, #44] ; 0x2c
8002eb4: 9300 str r3, [sp, #0]
8002eb6: 4613 mov r3, r2
8002eb8: 687a ldr r2, [r7, #4]
8002eba: 68b9 ldr r1, [r7, #8]
8002ebc: 68f8 ldr r0, [r7, #12]
8002ebe: f000 f805 bl 8002ecc <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
8002ec2: 6afb ldr r3, [r7, #44] ; 0x2c
}
8002ec4: 4618 mov r0, r3
8002ec6: 3730 adds r7, #48 ; 0x30
8002ec8: 46bd mov sp, r7
8002eca: bd80 pop {r7, pc}
08002ecc <prvInitialiseNewQueue>:
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
8002ecc: b580 push {r7, lr}
8002ece: b084 sub sp, #16
8002ed0: af00 add r7, sp, #0
8002ed2: 60f8 str r0, [r7, #12]
8002ed4: 60b9 str r1, [r7, #8]
8002ed6: 607a str r2, [r7, #4]
8002ed8: 70fb strb r3, [r7, #3]
/* Remove compiler warnings about unused parameters should
configUSE_TRACE_FACILITY not be set to 1. */
( void ) ucQueueType;
if( uxItemSize == ( UBaseType_t ) 0 )
8002eda: 68bb ldr r3, [r7, #8]
8002edc: 2b00 cmp r3, #0
8002ede: d103 bne.n 8002ee8 <prvInitialiseNewQueue+0x1c>
{
/* No RAM was allocated for the queue storage area, but PC head cannot
be set to NULL because NULL is used as a key to say the queue is used as
a mutex. Therefore just set pcHead to point to the queue as a benign
value that is known to be within the memory map. */
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
8002ee0: 69bb ldr r3, [r7, #24]
8002ee2: 69ba ldr r2, [r7, #24]
8002ee4: 601a str r2, [r3, #0]
8002ee6: e002 b.n 8002eee <prvInitialiseNewQueue+0x22>
}
else
{
/* Set the head to the start of the queue storage area. */
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
8002ee8: 69bb ldr r3, [r7, #24]
8002eea: 687a ldr r2, [r7, #4]
8002eec: 601a str r2, [r3, #0]
}
/* Initialise the queue members as described where the queue type is
defined. */
pxNewQueue->uxLength = uxQueueLength;
8002eee: 69bb ldr r3, [r7, #24]
8002ef0: 68fa ldr r2, [r7, #12]
8002ef2: 63da str r2, [r3, #60] ; 0x3c
pxNewQueue->uxItemSize = uxItemSize;
8002ef4: 69bb ldr r3, [r7, #24]
8002ef6: 68ba ldr r2, [r7, #8]
8002ef8: 641a str r2, [r3, #64] ; 0x40
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
8002efa: 2101 movs r1, #1
8002efc: 69b8 ldr r0, [r7, #24]
8002efe: f7ff ff05 bl 8002d0c <xQueueGenericReset>
#if ( configUSE_TRACE_FACILITY == 1 )
{
pxNewQueue->ucQueueType = ucQueueType;
8002f02: 69bb ldr r3, [r7, #24]
8002f04: 78fa ldrb r2, [r7, #3]
8002f06: f883 204c strb.w r2, [r3, #76] ; 0x4c
pxNewQueue->pxQueueSetContainer = NULL;
}
#endif /* configUSE_QUEUE_SETS */
traceQUEUE_CREATE( pxNewQueue );
}
8002f0a: bf00 nop
8002f0c: 3710 adds r7, #16
8002f0e: 46bd mov sp, r7
8002f10: bd80 pop {r7, pc}
...
08002f14 <xQueueGenericSend>:
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
8002f14: b580 push {r7, lr}
8002f16: b08e sub sp, #56 ; 0x38
8002f18: af00 add r7, sp, #0
8002f1a: 60f8 str r0, [r7, #12]
8002f1c: 60b9 str r1, [r7, #8]
8002f1e: 607a str r2, [r7, #4]
8002f20: 603b str r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
8002f22: 2300 movs r3, #0
8002f24: 637b str r3, [r7, #52] ; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8002f26: 68fb ldr r3, [r7, #12]
8002f28: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
8002f2a: 6b3b ldr r3, [r7, #48] ; 0x30
8002f2c: 2b00 cmp r3, #0
8002f2e: d10a bne.n 8002f46 <xQueueGenericSend+0x32>
__asm volatile
8002f30: f04f 0350 mov.w r3, #80 ; 0x50
8002f34: f383 8811 msr BASEPRI, r3
8002f38: f3bf 8f6f isb sy
8002f3c: f3bf 8f4f dsb sy
8002f40: 62bb str r3, [r7, #40] ; 0x28
}
8002f42: bf00 nop
8002f44: e7fe b.n 8002f44 <xQueueGenericSend+0x30>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
8002f46: 68bb ldr r3, [r7, #8]
8002f48: 2b00 cmp r3, #0
8002f4a: d103 bne.n 8002f54 <xQueueGenericSend+0x40>
8002f4c: 6b3b ldr r3, [r7, #48] ; 0x30
8002f4e: 6c1b ldr r3, [r3, #64] ; 0x40
8002f50: 2b00 cmp r3, #0
8002f52: d101 bne.n 8002f58 <xQueueGenericSend+0x44>
8002f54: 2301 movs r3, #1
8002f56: e000 b.n 8002f5a <xQueueGenericSend+0x46>
8002f58: 2300 movs r3, #0
8002f5a: 2b00 cmp r3, #0
8002f5c: d10a bne.n 8002f74 <xQueueGenericSend+0x60>
__asm volatile
8002f5e: f04f 0350 mov.w r3, #80 ; 0x50
8002f62: f383 8811 msr BASEPRI, r3
8002f66: f3bf 8f6f isb sy
8002f6a: f3bf 8f4f dsb sy
8002f6e: 627b str r3, [r7, #36] ; 0x24
}
8002f70: bf00 nop
8002f72: e7fe b.n 8002f72 <xQueueGenericSend+0x5e>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
8002f74: 683b ldr r3, [r7, #0]
8002f76: 2b02 cmp r3, #2
8002f78: d103 bne.n 8002f82 <xQueueGenericSend+0x6e>
8002f7a: 6b3b ldr r3, [r7, #48] ; 0x30
8002f7c: 6bdb ldr r3, [r3, #60] ; 0x3c
8002f7e: 2b01 cmp r3, #1
8002f80: d101 bne.n 8002f86 <xQueueGenericSend+0x72>
8002f82: 2301 movs r3, #1
8002f84: e000 b.n 8002f88 <xQueueGenericSend+0x74>
8002f86: 2300 movs r3, #0
8002f88: 2b00 cmp r3, #0
8002f8a: d10a bne.n 8002fa2 <xQueueGenericSend+0x8e>
__asm volatile
8002f8c: f04f 0350 mov.w r3, #80 ; 0x50
8002f90: f383 8811 msr BASEPRI, r3
8002f94: f3bf 8f6f isb sy
8002f98: f3bf 8f4f dsb sy
8002f9c: 623b str r3, [r7, #32]
}
8002f9e: bf00 nop
8002fa0: e7fe b.n 8002fa0 <xQueueGenericSend+0x8c>
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
8002fa2: f001 f9e7 bl 8004374 <xTaskGetSchedulerState>
8002fa6: 4603 mov r3, r0
8002fa8: 2b00 cmp r3, #0
8002faa: d102 bne.n 8002fb2 <xQueueGenericSend+0x9e>
8002fac: 687b ldr r3, [r7, #4]
8002fae: 2b00 cmp r3, #0
8002fb0: d101 bne.n 8002fb6 <xQueueGenericSend+0xa2>
8002fb2: 2301 movs r3, #1
8002fb4: e000 b.n 8002fb8 <xQueueGenericSend+0xa4>
8002fb6: 2300 movs r3, #0
8002fb8: 2b00 cmp r3, #0
8002fba: d10a bne.n 8002fd2 <xQueueGenericSend+0xbe>
__asm volatile
8002fbc: f04f 0350 mov.w r3, #80 ; 0x50
8002fc0: f383 8811 msr BASEPRI, r3
8002fc4: f3bf 8f6f isb sy
8002fc8: f3bf 8f4f dsb sy
8002fcc: 61fb str r3, [r7, #28]
}
8002fce: bf00 nop
8002fd0: e7fe b.n 8002fd0 <xQueueGenericSend+0xbc>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
8002fd2: f001 ff27 bl 8004e24 <vPortEnterCritical>
{
/* Is there room on the queue now? The running task must be the
highest priority task wanting to access the queue. If the head item
in the queue is to be overwritten then it does not matter if the
queue is full. */
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
8002fd6: 6b3b ldr r3, [r7, #48] ; 0x30
8002fd8: 6b9a ldr r2, [r3, #56] ; 0x38
8002fda: 6b3b ldr r3, [r7, #48] ; 0x30
8002fdc: 6bdb ldr r3, [r3, #60] ; 0x3c
8002fde: 429a cmp r2, r3
8002fe0: d302 bcc.n 8002fe8 <xQueueGenericSend+0xd4>
8002fe2: 683b ldr r3, [r7, #0]
8002fe4: 2b02 cmp r3, #2
8002fe6: d129 bne.n 800303c <xQueueGenericSend+0x128>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
8002fe8: 683a ldr r2, [r7, #0]
8002fea: 68b9 ldr r1, [r7, #8]
8002fec: 6b38 ldr r0, [r7, #48] ; 0x30
8002fee: f000 fa0b bl 8003408 <prvCopyDataToQueue>
8002ff2: 62f8 str r0, [r7, #44] ; 0x2c
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
8002ff4: 6b3b ldr r3, [r7, #48] ; 0x30
8002ff6: 6a5b ldr r3, [r3, #36] ; 0x24
8002ff8: 2b00 cmp r3, #0
8002ffa: d010 beq.n 800301e <xQueueGenericSend+0x10a>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8002ffc: 6b3b ldr r3, [r7, #48] ; 0x30
8002ffe: 3324 adds r3, #36 ; 0x24
8003000: 4618 mov r0, r3
8003002: f000 fff5 bl 8003ff0 <xTaskRemoveFromEventList>
8003006: 4603 mov r3, r0
8003008: 2b00 cmp r3, #0
800300a: d013 beq.n 8003034 <xQueueGenericSend+0x120>
{
/* The unblocked task has a priority higher than
our own so yield immediately. Yes it is ok to do
this from within the critical section - the kernel
takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
800300c: 4b3f ldr r3, [pc, #252] ; (800310c <xQueueGenericSend+0x1f8>)
800300e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003012: 601a str r2, [r3, #0]
8003014: f3bf 8f4f dsb sy
8003018: f3bf 8f6f isb sy
800301c: e00a b.n 8003034 <xQueueGenericSend+0x120>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else if( xYieldRequired != pdFALSE )
800301e: 6afb ldr r3, [r7, #44] ; 0x2c
8003020: 2b00 cmp r3, #0
8003022: d007 beq.n 8003034 <xQueueGenericSend+0x120>
{
/* This path is a special case that will only get
executed if the task was holding multiple mutexes and
the mutexes were given back in an order that is
different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
8003024: 4b39 ldr r3, [pc, #228] ; (800310c <xQueueGenericSend+0x1f8>)
8003026: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800302a: 601a str r2, [r3, #0]
800302c: f3bf 8f4f dsb sy
8003030: f3bf 8f6f isb sy
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
8003034: f001 ff26 bl 8004e84 <vPortExitCritical>
return pdPASS;
8003038: 2301 movs r3, #1
800303a: e063 b.n 8003104 <xQueueGenericSend+0x1f0>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
800303c: 687b ldr r3, [r7, #4]
800303e: 2b00 cmp r3, #0
8003040: d103 bne.n 800304a <xQueueGenericSend+0x136>
{
/* The queue was full and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
8003042: f001 ff1f bl 8004e84 <vPortExitCritical>
/* Return to the original privilege level before exiting
the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
8003046: 2300 movs r3, #0
8003048: e05c b.n 8003104 <xQueueGenericSend+0x1f0>
}
else if( xEntryTimeSet == pdFALSE )
800304a: 6b7b ldr r3, [r7, #52] ; 0x34
800304c: 2b00 cmp r3, #0
800304e: d106 bne.n 800305e <xQueueGenericSend+0x14a>
{
/* The queue was full and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
8003050: f107 0314 add.w r3, r7, #20
8003054: 4618 mov r0, r3
8003056: f001 f82f bl 80040b8 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
800305a: 2301 movs r3, #1
800305c: 637b str r3, [r7, #52] ; 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800305e: f001 ff11 bl 8004e84 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
8003062: f000 fd9b bl 8003b9c <vTaskSuspendAll>
prvLockQueue( pxQueue );
8003066: f001 fedd bl 8004e24 <vPortEnterCritical>
800306a: 6b3b ldr r3, [r7, #48] ; 0x30
800306c: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
8003070: b25b sxtb r3, r3
8003072: f1b3 3fff cmp.w r3, #4294967295
8003076: d103 bne.n 8003080 <xQueueGenericSend+0x16c>
8003078: 6b3b ldr r3, [r7, #48] ; 0x30
800307a: 2200 movs r2, #0
800307c: f883 2044 strb.w r2, [r3, #68] ; 0x44
8003080: 6b3b ldr r3, [r7, #48] ; 0x30
8003082: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8003086: b25b sxtb r3, r3
8003088: f1b3 3fff cmp.w r3, #4294967295
800308c: d103 bne.n 8003096 <xQueueGenericSend+0x182>
800308e: 6b3b ldr r3, [r7, #48] ; 0x30
8003090: 2200 movs r2, #0
8003092: f883 2045 strb.w r2, [r3, #69] ; 0x45
8003096: f001 fef5 bl 8004e84 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
800309a: 1d3a adds r2, r7, #4
800309c: f107 0314 add.w r3, r7, #20
80030a0: 4611 mov r1, r2
80030a2: 4618 mov r0, r3
80030a4: f001 f81e bl 80040e4 <xTaskCheckForTimeOut>
80030a8: 4603 mov r3, r0
80030aa: 2b00 cmp r3, #0
80030ac: d124 bne.n 80030f8 <xQueueGenericSend+0x1e4>
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
80030ae: 6b38 ldr r0, [r7, #48] ; 0x30
80030b0: f000 faa2 bl 80035f8 <prvIsQueueFull>
80030b4: 4603 mov r3, r0
80030b6: 2b00 cmp r3, #0
80030b8: d018 beq.n 80030ec <xQueueGenericSend+0x1d8>
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
80030ba: 6b3b ldr r3, [r7, #48] ; 0x30
80030bc: 3310 adds r3, #16
80030be: 687a ldr r2, [r7, #4]
80030c0: 4611 mov r1, r2
80030c2: 4618 mov r0, r3
80030c4: f000 ff44 bl 8003f50 <vTaskPlaceOnEventList>
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
prvUnlockQueue( pxQueue );
80030c8: 6b38 ldr r0, [r7, #48] ; 0x30
80030ca: f000 fa2d bl 8003528 <prvUnlockQueue>
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
task is already in a ready list before it yields - in which
case the yield will not cause a context switch unless there
is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
80030ce: f000 fd73 bl 8003bb8 <xTaskResumeAll>
80030d2: 4603 mov r3, r0
80030d4: 2b00 cmp r3, #0
80030d6: f47f af7c bne.w 8002fd2 <xQueueGenericSend+0xbe>
{
portYIELD_WITHIN_API();
80030da: 4b0c ldr r3, [pc, #48] ; (800310c <xQueueGenericSend+0x1f8>)
80030dc: f04f 5280 mov.w r2, #268435456 ; 0x10000000
80030e0: 601a str r2, [r3, #0]
80030e2: f3bf 8f4f dsb sy
80030e6: f3bf 8f6f isb sy
80030ea: e772 b.n 8002fd2 <xQueueGenericSend+0xbe>
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
80030ec: 6b38 ldr r0, [r7, #48] ; 0x30
80030ee: f000 fa1b bl 8003528 <prvUnlockQueue>
( void ) xTaskResumeAll();
80030f2: f000 fd61 bl 8003bb8 <xTaskResumeAll>
80030f6: e76c b.n 8002fd2 <xQueueGenericSend+0xbe>
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
80030f8: 6b38 ldr r0, [r7, #48] ; 0x30
80030fa: f000 fa15 bl 8003528 <prvUnlockQueue>
( void ) xTaskResumeAll();
80030fe: f000 fd5b bl 8003bb8 <xTaskResumeAll>
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
8003102: 2300 movs r3, #0
}
} /*lint -restore */
}
8003104: 4618 mov r0, r3
8003106: 3738 adds r7, #56 ; 0x38
8003108: 46bd mov sp, r7
800310a: bd80 pop {r7, pc}
800310c: e000ed04 .word 0xe000ed04
08003110 <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
8003110: b580 push {r7, lr}
8003112: b090 sub sp, #64 ; 0x40
8003114: af00 add r7, sp, #0
8003116: 60f8 str r0, [r7, #12]
8003118: 60b9 str r1, [r7, #8]
800311a: 607a str r2, [r7, #4]
800311c: 603b str r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800311e: 68fb ldr r3, [r7, #12]
8003120: 63bb str r3, [r7, #56] ; 0x38
configASSERT( pxQueue );
8003122: 6bbb ldr r3, [r7, #56] ; 0x38
8003124: 2b00 cmp r3, #0
8003126: d10a bne.n 800313e <xQueueGenericSendFromISR+0x2e>
__asm volatile
8003128: f04f 0350 mov.w r3, #80 ; 0x50
800312c: f383 8811 msr BASEPRI, r3
8003130: f3bf 8f6f isb sy
8003134: f3bf 8f4f dsb sy
8003138: 62bb str r3, [r7, #40] ; 0x28
}
800313a: bf00 nop
800313c: e7fe b.n 800313c <xQueueGenericSendFromISR+0x2c>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800313e: 68bb ldr r3, [r7, #8]
8003140: 2b00 cmp r3, #0
8003142: d103 bne.n 800314c <xQueueGenericSendFromISR+0x3c>
8003144: 6bbb ldr r3, [r7, #56] ; 0x38
8003146: 6c1b ldr r3, [r3, #64] ; 0x40
8003148: 2b00 cmp r3, #0
800314a: d101 bne.n 8003150 <xQueueGenericSendFromISR+0x40>
800314c: 2301 movs r3, #1
800314e: e000 b.n 8003152 <xQueueGenericSendFromISR+0x42>
8003150: 2300 movs r3, #0
8003152: 2b00 cmp r3, #0
8003154: d10a bne.n 800316c <xQueueGenericSendFromISR+0x5c>
__asm volatile
8003156: f04f 0350 mov.w r3, #80 ; 0x50
800315a: f383 8811 msr BASEPRI, r3
800315e: f3bf 8f6f isb sy
8003162: f3bf 8f4f dsb sy
8003166: 627b str r3, [r7, #36] ; 0x24
}
8003168: bf00 nop
800316a: e7fe b.n 800316a <xQueueGenericSendFromISR+0x5a>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
800316c: 683b ldr r3, [r7, #0]
800316e: 2b02 cmp r3, #2
8003170: d103 bne.n 800317a <xQueueGenericSendFromISR+0x6a>
8003172: 6bbb ldr r3, [r7, #56] ; 0x38
8003174: 6bdb ldr r3, [r3, #60] ; 0x3c
8003176: 2b01 cmp r3, #1
8003178: d101 bne.n 800317e <xQueueGenericSendFromISR+0x6e>
800317a: 2301 movs r3, #1
800317c: e000 b.n 8003180 <xQueueGenericSendFromISR+0x70>
800317e: 2300 movs r3, #0
8003180: 2b00 cmp r3, #0
8003182: d10a bne.n 800319a <xQueueGenericSendFromISR+0x8a>
__asm volatile
8003184: f04f 0350 mov.w r3, #80 ; 0x50
8003188: f383 8811 msr BASEPRI, r3
800318c: f3bf 8f6f isb sy
8003190: f3bf 8f4f dsb sy
8003194: 623b str r3, [r7, #32]
}
8003196: bf00 nop
8003198: e7fe b.n 8003198 <xQueueGenericSendFromISR+0x88>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
800319a: f001 ff25 bl 8004fe8 <vPortValidateInterruptPriority>
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
800319e: f3ef 8211 mrs r2, BASEPRI
80031a2: f04f 0350 mov.w r3, #80 ; 0x50
80031a6: f383 8811 msr BASEPRI, r3
80031aa: f3bf 8f6f isb sy
80031ae: f3bf 8f4f dsb sy
80031b2: 61fa str r2, [r7, #28]
80031b4: 61bb str r3, [r7, #24]
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
/* This return will not be reached but is necessary to prevent compiler
warnings. */
return ulOriginalBASEPRI;
80031b6: 69fb ldr r3, [r7, #28]
/* Similar to xQueueGenericSend, except without blocking if there is no room
in the queue. Also don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
80031b8: 637b str r3, [r7, #52] ; 0x34
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
80031ba: 6bbb ldr r3, [r7, #56] ; 0x38
80031bc: 6b9a ldr r2, [r3, #56] ; 0x38
80031be: 6bbb ldr r3, [r7, #56] ; 0x38
80031c0: 6bdb ldr r3, [r3, #60] ; 0x3c
80031c2: 429a cmp r2, r3
80031c4: d302 bcc.n 80031cc <xQueueGenericSendFromISR+0xbc>
80031c6: 683b ldr r3, [r7, #0]
80031c8: 2b02 cmp r3, #2
80031ca: d12f bne.n 800322c <xQueueGenericSendFromISR+0x11c>
{
const int8_t cTxLock = pxQueue->cTxLock;
80031cc: 6bbb ldr r3, [r7, #56] ; 0x38
80031ce: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80031d2: f887 3033 strb.w r3, [r7, #51] ; 0x33
const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
80031d6: 6bbb ldr r3, [r7, #56] ; 0x38
80031d8: 6b9b ldr r3, [r3, #56] ; 0x38
80031da: 62fb str r3, [r7, #44] ; 0x2c
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
semaphore or mutex. That means prvCopyDataToQueue() cannot result
in a task disinheriting a priority and prvCopyDataToQueue() can be
called here even though the disinherit function does not check if
the scheduler is suspended before accessing the ready lists. */
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
80031dc: 683a ldr r2, [r7, #0]
80031de: 68b9 ldr r1, [r7, #8]
80031e0: 6bb8 ldr r0, [r7, #56] ; 0x38
80031e2: f000 f911 bl 8003408 <prvCopyDataToQueue>
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
80031e6: f997 3033 ldrsb.w r3, [r7, #51] ; 0x33
80031ea: f1b3 3fff cmp.w r3, #4294967295
80031ee: d112 bne.n 8003216 <xQueueGenericSendFromISR+0x106>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
80031f0: 6bbb ldr r3, [r7, #56] ; 0x38
80031f2: 6a5b ldr r3, [r3, #36] ; 0x24
80031f4: 2b00 cmp r3, #0
80031f6: d016 beq.n 8003226 <xQueueGenericSendFromISR+0x116>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
80031f8: 6bbb ldr r3, [r7, #56] ; 0x38
80031fa: 3324 adds r3, #36 ; 0x24
80031fc: 4618 mov r0, r3
80031fe: f000 fef7 bl 8003ff0 <xTaskRemoveFromEventList>
8003202: 4603 mov r3, r0
8003204: 2b00 cmp r3, #0
8003206: d00e beq.n 8003226 <xQueueGenericSendFromISR+0x116>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
8003208: 687b ldr r3, [r7, #4]
800320a: 2b00 cmp r3, #0
800320c: d00b beq.n 8003226 <xQueueGenericSendFromISR+0x116>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800320e: 687b ldr r3, [r7, #4]
8003210: 2201 movs r2, #1
8003212: 601a str r2, [r3, #0]
8003214: e007 b.n 8003226 <xQueueGenericSendFromISR+0x116>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
8003216: f897 3033 ldrb.w r3, [r7, #51] ; 0x33
800321a: 3301 adds r3, #1
800321c: b2db uxtb r3, r3
800321e: b25a sxtb r2, r3
8003220: 6bbb ldr r3, [r7, #56] ; 0x38
8003222: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
xReturn = pdPASS;
8003226: 2301 movs r3, #1
8003228: 63fb str r3, [r7, #60] ; 0x3c
{
800322a: e001 b.n 8003230 <xQueueGenericSendFromISR+0x120>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
800322c: 2300 movs r3, #0
800322e: 63fb str r3, [r7, #60] ; 0x3c
8003230: 6b7b ldr r3, [r7, #52] ; 0x34
8003232: 617b str r3, [r7, #20]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
8003234: 697b ldr r3, [r7, #20]
8003236: f383 8811 msr BASEPRI, r3
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
800323a: bf00 nop
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
800323c: 6bfb ldr r3, [r7, #60] ; 0x3c
}
800323e: 4618 mov r0, r3
8003240: 3740 adds r7, #64 ; 0x40
8003242: 46bd mov sp, r7
8003244: bd80 pop {r7, pc}
...
08003248 <xQueueReceive>:
return xReturn;
}
/*-----------------------------------------------------------*/
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
8003248: b580 push {r7, lr}
800324a: b08c sub sp, #48 ; 0x30
800324c: af00 add r7, sp, #0
800324e: 60f8 str r0, [r7, #12]
8003250: 60b9 str r1, [r7, #8]
8003252: 607a str r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
8003254: 2300 movs r3, #0
8003256: 62fb str r3, [r7, #44] ; 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8003258: 68fb ldr r3, [r7, #12]
800325a: 62bb str r3, [r7, #40] ; 0x28
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
800325c: 6abb ldr r3, [r7, #40] ; 0x28
800325e: 2b00 cmp r3, #0
8003260: d10a bne.n 8003278 <xQueueReceive+0x30>
__asm volatile
8003262: f04f 0350 mov.w r3, #80 ; 0x50
8003266: f383 8811 msr BASEPRI, r3
800326a: f3bf 8f6f isb sy
800326e: f3bf 8f4f dsb sy
8003272: 623b str r3, [r7, #32]
}
8003274: bf00 nop
8003276: e7fe b.n 8003276 <xQueueReceive+0x2e>
/* The buffer into which data is received can only be NULL if the data size
is zero (so no data is copied into the buffer. */
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
8003278: 68bb ldr r3, [r7, #8]
800327a: 2b00 cmp r3, #0
800327c: d103 bne.n 8003286 <xQueueReceive+0x3e>
800327e: 6abb ldr r3, [r7, #40] ; 0x28
8003280: 6c1b ldr r3, [r3, #64] ; 0x40
8003282: 2b00 cmp r3, #0
8003284: d101 bne.n 800328a <xQueueReceive+0x42>
8003286: 2301 movs r3, #1
8003288: e000 b.n 800328c <xQueueReceive+0x44>
800328a: 2300 movs r3, #0
800328c: 2b00 cmp r3, #0
800328e: d10a bne.n 80032a6 <xQueueReceive+0x5e>
__asm volatile
8003290: f04f 0350 mov.w r3, #80 ; 0x50
8003294: f383 8811 msr BASEPRI, r3
8003298: f3bf 8f6f isb sy
800329c: f3bf 8f4f dsb sy
80032a0: 61fb str r3, [r7, #28]
}
80032a2: bf00 nop
80032a4: e7fe b.n 80032a4 <xQueueReceive+0x5c>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
80032a6: f001 f865 bl 8004374 <xTaskGetSchedulerState>
80032aa: 4603 mov r3, r0
80032ac: 2b00 cmp r3, #0
80032ae: d102 bne.n 80032b6 <xQueueReceive+0x6e>
80032b0: 687b ldr r3, [r7, #4]
80032b2: 2b00 cmp r3, #0
80032b4: d101 bne.n 80032ba <xQueueReceive+0x72>
80032b6: 2301 movs r3, #1
80032b8: e000 b.n 80032bc <xQueueReceive+0x74>
80032ba: 2300 movs r3, #0
80032bc: 2b00 cmp r3, #0
80032be: d10a bne.n 80032d6 <xQueueReceive+0x8e>
__asm volatile
80032c0: f04f 0350 mov.w r3, #80 ; 0x50
80032c4: f383 8811 msr BASEPRI, r3
80032c8: f3bf 8f6f isb sy
80032cc: f3bf 8f4f dsb sy
80032d0: 61bb str r3, [r7, #24]
}
80032d2: bf00 nop
80032d4: e7fe b.n 80032d4 <xQueueReceive+0x8c>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
80032d6: f001 fda5 bl 8004e24 <vPortEnterCritical>
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
80032da: 6abb ldr r3, [r7, #40] ; 0x28
80032dc: 6b9b ldr r3, [r3, #56] ; 0x38
80032de: 627b str r3, [r7, #36] ; 0x24
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
80032e0: 6a7b ldr r3, [r7, #36] ; 0x24
80032e2: 2b00 cmp r3, #0
80032e4: d01f beq.n 8003326 <xQueueReceive+0xde>
{
/* Data available, remove one item. */
prvCopyDataFromQueue( pxQueue, pvBuffer );
80032e6: 68b9 ldr r1, [r7, #8]
80032e8: 6ab8 ldr r0, [r7, #40] ; 0x28
80032ea: f000 f8f7 bl 80034dc <prvCopyDataFromQueue>
traceQUEUE_RECEIVE( pxQueue );
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
80032ee: 6a7b ldr r3, [r7, #36] ; 0x24
80032f0: 1e5a subs r2, r3, #1
80032f2: 6abb ldr r3, [r7, #40] ; 0x28
80032f4: 639a str r2, [r3, #56] ; 0x38
/* There is now space in the queue, were any tasks waiting to
post to the queue? If so, unblock the highest priority waiting
task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
80032f6: 6abb ldr r3, [r7, #40] ; 0x28
80032f8: 691b ldr r3, [r3, #16]
80032fa: 2b00 cmp r3, #0
80032fc: d00f beq.n 800331e <xQueueReceive+0xd6>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
80032fe: 6abb ldr r3, [r7, #40] ; 0x28
8003300: 3310 adds r3, #16
8003302: 4618 mov r0, r3
8003304: f000 fe74 bl 8003ff0 <xTaskRemoveFromEventList>
8003308: 4603 mov r3, r0
800330a: 2b00 cmp r3, #0
800330c: d007 beq.n 800331e <xQueueReceive+0xd6>
{
queueYIELD_IF_USING_PREEMPTION();
800330e: 4b3d ldr r3, [pc, #244] ; (8003404 <xQueueReceive+0x1bc>)
8003310: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003314: 601a str r2, [r3, #0]
8003316: f3bf 8f4f dsb sy
800331a: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
800331e: f001 fdb1 bl 8004e84 <vPortExitCritical>
return pdPASS;
8003322: 2301 movs r3, #1
8003324: e069 b.n 80033fa <xQueueReceive+0x1b2>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
8003326: 687b ldr r3, [r7, #4]
8003328: 2b00 cmp r3, #0
800332a: d103 bne.n 8003334 <xQueueReceive+0xec>
{
/* The queue was empty and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
800332c: f001 fdaa bl 8004e84 <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
8003330: 2300 movs r3, #0
8003332: e062 b.n 80033fa <xQueueReceive+0x1b2>
}
else if( xEntryTimeSet == pdFALSE )
8003334: 6afb ldr r3, [r7, #44] ; 0x2c
8003336: 2b00 cmp r3, #0
8003338: d106 bne.n 8003348 <xQueueReceive+0x100>
{
/* The queue was empty and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
800333a: f107 0310 add.w r3, r7, #16
800333e: 4618 mov r0, r3
8003340: f000 feba bl 80040b8 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
8003344: 2301 movs r3, #1
8003346: 62fb str r3, [r7, #44] ; 0x2c
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
8003348: f001 fd9c bl 8004e84 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
800334c: f000 fc26 bl 8003b9c <vTaskSuspendAll>
prvLockQueue( pxQueue );
8003350: f001 fd68 bl 8004e24 <vPortEnterCritical>
8003354: 6abb ldr r3, [r7, #40] ; 0x28
8003356: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800335a: b25b sxtb r3, r3
800335c: f1b3 3fff cmp.w r3, #4294967295
8003360: d103 bne.n 800336a <xQueueReceive+0x122>
8003362: 6abb ldr r3, [r7, #40] ; 0x28
8003364: 2200 movs r2, #0
8003366: f883 2044 strb.w r2, [r3, #68] ; 0x44
800336a: 6abb ldr r3, [r7, #40] ; 0x28
800336c: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8003370: b25b sxtb r3, r3
8003372: f1b3 3fff cmp.w r3, #4294967295
8003376: d103 bne.n 8003380 <xQueueReceive+0x138>
8003378: 6abb ldr r3, [r7, #40] ; 0x28
800337a: 2200 movs r2, #0
800337c: f883 2045 strb.w r2, [r3, #69] ; 0x45
8003380: f001 fd80 bl 8004e84 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
8003384: 1d3a adds r2, r7, #4
8003386: f107 0310 add.w r3, r7, #16
800338a: 4611 mov r1, r2
800338c: 4618 mov r0, r3
800338e: f000 fea9 bl 80040e4 <xTaskCheckForTimeOut>
8003392: 4603 mov r3, r0
8003394: 2b00 cmp r3, #0
8003396: d123 bne.n 80033e0 <xQueueReceive+0x198>
{
/* The timeout has not expired. If the queue is still empty place
the task on the list of tasks waiting to receive from the queue. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
8003398: 6ab8 ldr r0, [r7, #40] ; 0x28
800339a: f000 f917 bl 80035cc <prvIsQueueEmpty>
800339e: 4603 mov r3, r0
80033a0: 2b00 cmp r3, #0
80033a2: d017 beq.n 80033d4 <xQueueReceive+0x18c>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
80033a4: 6abb ldr r3, [r7, #40] ; 0x28
80033a6: 3324 adds r3, #36 ; 0x24
80033a8: 687a ldr r2, [r7, #4]
80033aa: 4611 mov r1, r2
80033ac: 4618 mov r0, r3
80033ae: f000 fdcf bl 8003f50 <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
80033b2: 6ab8 ldr r0, [r7, #40] ; 0x28
80033b4: f000 f8b8 bl 8003528 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
80033b8: f000 fbfe bl 8003bb8 <xTaskResumeAll>
80033bc: 4603 mov r3, r0
80033be: 2b00 cmp r3, #0
80033c0: d189 bne.n 80032d6 <xQueueReceive+0x8e>
{
portYIELD_WITHIN_API();
80033c2: 4b10 ldr r3, [pc, #64] ; (8003404 <xQueueReceive+0x1bc>)
80033c4: f04f 5280 mov.w r2, #268435456 ; 0x10000000
80033c8: 601a str r2, [r3, #0]
80033ca: f3bf 8f4f dsb sy
80033ce: f3bf 8f6f isb sy
80033d2: e780 b.n 80032d6 <xQueueReceive+0x8e>
}
else
{
/* The queue contains data again. Loop back to try and read the
data. */
prvUnlockQueue( pxQueue );
80033d4: 6ab8 ldr r0, [r7, #40] ; 0x28
80033d6: f000 f8a7 bl 8003528 <prvUnlockQueue>
( void ) xTaskResumeAll();
80033da: f000 fbed bl 8003bb8 <xTaskResumeAll>
80033de: e77a b.n 80032d6 <xQueueReceive+0x8e>
}
else
{
/* Timed out. If there is no data in the queue exit, otherwise loop
back and attempt to read the data. */
prvUnlockQueue( pxQueue );
80033e0: 6ab8 ldr r0, [r7, #40] ; 0x28
80033e2: f000 f8a1 bl 8003528 <prvUnlockQueue>
( void ) xTaskResumeAll();
80033e6: f000 fbe7 bl 8003bb8 <xTaskResumeAll>
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
80033ea: 6ab8 ldr r0, [r7, #40] ; 0x28
80033ec: f000 f8ee bl 80035cc <prvIsQueueEmpty>
80033f0: 4603 mov r3, r0
80033f2: 2b00 cmp r3, #0
80033f4: f43f af6f beq.w 80032d6 <xQueueReceive+0x8e>
{
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
80033f8: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
80033fa: 4618 mov r0, r3
80033fc: 3730 adds r7, #48 ; 0x30
80033fe: 46bd mov sp, r7
8003400: bd80 pop {r7, pc}
8003402: bf00 nop
8003404: e000ed04 .word 0xe000ed04
08003408 <prvCopyDataToQueue>:
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
8003408: b580 push {r7, lr}
800340a: b086 sub sp, #24
800340c: af00 add r7, sp, #0
800340e: 60f8 str r0, [r7, #12]
8003410: 60b9 str r1, [r7, #8]
8003412: 607a str r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
8003414: 2300 movs r3, #0
8003416: 617b str r3, [r7, #20]
UBaseType_t uxMessagesWaiting;
/* This function is called from a critical section. */
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
8003418: 68fb ldr r3, [r7, #12]
800341a: 6b9b ldr r3, [r3, #56] ; 0x38
800341c: 613b str r3, [r7, #16]
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
800341e: 68fb ldr r3, [r7, #12]
8003420: 6c1b ldr r3, [r3, #64] ; 0x40
8003422: 2b00 cmp r3, #0
8003424: d10d bne.n 8003442 <prvCopyDataToQueue+0x3a>
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
8003426: 68fb ldr r3, [r7, #12]
8003428: 681b ldr r3, [r3, #0]
800342a: 2b00 cmp r3, #0
800342c: d14d bne.n 80034ca <prvCopyDataToQueue+0xc2>
{
/* The mutex is no longer being held. */
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
800342e: 68fb ldr r3, [r7, #12]
8003430: 689b ldr r3, [r3, #8]
8003432: 4618 mov r0, r3
8003434: f000 ffbc bl 80043b0 <xTaskPriorityDisinherit>
8003438: 6178 str r0, [r7, #20]
pxQueue->u.xSemaphore.xMutexHolder = NULL;
800343a: 68fb ldr r3, [r7, #12]
800343c: 2200 movs r2, #0
800343e: 609a str r2, [r3, #8]
8003440: e043 b.n 80034ca <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
8003442: 687b ldr r3, [r7, #4]
8003444: 2b00 cmp r3, #0
8003446: d119 bne.n 800347c <prvCopyDataToQueue+0x74>
{
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
8003448: 68fb ldr r3, [r7, #12]
800344a: 6858 ldr r0, [r3, #4]
800344c: 68fb ldr r3, [r7, #12]
800344e: 6c1b ldr r3, [r3, #64] ; 0x40
8003450: 461a mov r2, r3
8003452: 68b9 ldr r1, [r7, #8]
8003454: f002 f876 bl 8005544 <memcpy>
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
8003458: 68fb ldr r3, [r7, #12]
800345a: 685a ldr r2, [r3, #4]
800345c: 68fb ldr r3, [r7, #12]
800345e: 6c1b ldr r3, [r3, #64] ; 0x40
8003460: 441a add r2, r3
8003462: 68fb ldr r3, [r7, #12]
8003464: 605a str r2, [r3, #4]
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
8003466: 68fb ldr r3, [r7, #12]
8003468: 685a ldr r2, [r3, #4]
800346a: 68fb ldr r3, [r7, #12]
800346c: 689b ldr r3, [r3, #8]
800346e: 429a cmp r2, r3
8003470: d32b bcc.n 80034ca <prvCopyDataToQueue+0xc2>
{
pxQueue->pcWriteTo = pxQueue->pcHead;
8003472: 68fb ldr r3, [r7, #12]
8003474: 681a ldr r2, [r3, #0]
8003476: 68fb ldr r3, [r7, #12]
8003478: 605a str r2, [r3, #4]
800347a: e026 b.n 80034ca <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
800347c: 68fb ldr r3, [r7, #12]
800347e: 68d8 ldr r0, [r3, #12]
8003480: 68fb ldr r3, [r7, #12]
8003482: 6c1b ldr r3, [r3, #64] ; 0x40
8003484: 461a mov r2, r3
8003486: 68b9 ldr r1, [r7, #8]
8003488: f002 f85c bl 8005544 <memcpy>
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
800348c: 68fb ldr r3, [r7, #12]
800348e: 68da ldr r2, [r3, #12]
8003490: 68fb ldr r3, [r7, #12]
8003492: 6c1b ldr r3, [r3, #64] ; 0x40
8003494: 425b negs r3, r3
8003496: 441a add r2, r3
8003498: 68fb ldr r3, [r7, #12]
800349a: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
800349c: 68fb ldr r3, [r7, #12]
800349e: 68da ldr r2, [r3, #12]
80034a0: 68fb ldr r3, [r7, #12]
80034a2: 681b ldr r3, [r3, #0]
80034a4: 429a cmp r2, r3
80034a6: d207 bcs.n 80034b8 <prvCopyDataToQueue+0xb0>
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
80034a8: 68fb ldr r3, [r7, #12]
80034aa: 689a ldr r2, [r3, #8]
80034ac: 68fb ldr r3, [r7, #12]
80034ae: 6c1b ldr r3, [r3, #64] ; 0x40
80034b0: 425b negs r3, r3
80034b2: 441a add r2, r3
80034b4: 68fb ldr r3, [r7, #12]
80034b6: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xPosition == queueOVERWRITE )
80034b8: 687b ldr r3, [r7, #4]
80034ba: 2b02 cmp r3, #2
80034bc: d105 bne.n 80034ca <prvCopyDataToQueue+0xc2>
{
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
80034be: 693b ldr r3, [r7, #16]
80034c0: 2b00 cmp r3, #0
80034c2: d002 beq.n 80034ca <prvCopyDataToQueue+0xc2>
{
/* An item is not being added but overwritten, so subtract
one from the recorded number of items in the queue so when
one is added again below the number of recorded items remains
correct. */
--uxMessagesWaiting;
80034c4: 693b ldr r3, [r7, #16]
80034c6: 3b01 subs r3, #1
80034c8: 613b str r3, [r7, #16]
{
mtCOVERAGE_TEST_MARKER();
}
}
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
80034ca: 693b ldr r3, [r7, #16]
80034cc: 1c5a adds r2, r3, #1
80034ce: 68fb ldr r3, [r7, #12]
80034d0: 639a str r2, [r3, #56] ; 0x38
return xReturn;
80034d2: 697b ldr r3, [r7, #20]
}
80034d4: 4618 mov r0, r3
80034d6: 3718 adds r7, #24
80034d8: 46bd mov sp, r7
80034da: bd80 pop {r7, pc}
080034dc <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
80034dc: b580 push {r7, lr}
80034de: b082 sub sp, #8
80034e0: af00 add r7, sp, #0
80034e2: 6078 str r0, [r7, #4]
80034e4: 6039 str r1, [r7, #0]
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
80034e6: 687b ldr r3, [r7, #4]
80034e8: 6c1b ldr r3, [r3, #64] ; 0x40
80034ea: 2b00 cmp r3, #0
80034ec: d018 beq.n 8003520 <prvCopyDataFromQueue+0x44>
{
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
80034ee: 687b ldr r3, [r7, #4]
80034f0: 68da ldr r2, [r3, #12]
80034f2: 687b ldr r3, [r7, #4]
80034f4: 6c1b ldr r3, [r3, #64] ; 0x40
80034f6: 441a add r2, r3
80034f8: 687b ldr r3, [r7, #4]
80034fa: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
80034fc: 687b ldr r3, [r7, #4]
80034fe: 68da ldr r2, [r3, #12]
8003500: 687b ldr r3, [r7, #4]
8003502: 689b ldr r3, [r3, #8]
8003504: 429a cmp r2, r3
8003506: d303 bcc.n 8003510 <prvCopyDataFromQueue+0x34>
{
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
8003508: 687b ldr r3, [r7, #4]
800350a: 681a ldr r2, [r3, #0]
800350c: 687b ldr r3, [r7, #4]
800350e: 60da str r2, [r3, #12]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
8003510: 687b ldr r3, [r7, #4]
8003512: 68d9 ldr r1, [r3, #12]
8003514: 687b ldr r3, [r7, #4]
8003516: 6c1b ldr r3, [r3, #64] ; 0x40
8003518: 461a mov r2, r3
800351a: 6838 ldr r0, [r7, #0]
800351c: f002 f812 bl 8005544 <memcpy>
}
}
8003520: bf00 nop
8003522: 3708 adds r7, #8
8003524: 46bd mov sp, r7
8003526: bd80 pop {r7, pc}
08003528 <prvUnlockQueue>:
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
8003528: b580 push {r7, lr}
800352a: b084 sub sp, #16
800352c: af00 add r7, sp, #0
800352e: 6078 str r0, [r7, #4]
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL();
8003530: f001 fc78 bl 8004e24 <vPortEnterCritical>
{
int8_t cTxLock = pxQueue->cTxLock;
8003534: 687b ldr r3, [r7, #4]
8003536: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800353a: 73fb strb r3, [r7, #15]
/* See if data was added to the queue while it was locked. */
while( cTxLock > queueLOCKED_UNMODIFIED )
800353c: e011 b.n 8003562 <prvUnlockQueue+0x3a>
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800353e: 687b ldr r3, [r7, #4]
8003540: 6a5b ldr r3, [r3, #36] ; 0x24
8003542: 2b00 cmp r3, #0
8003544: d012 beq.n 800356c <prvUnlockQueue+0x44>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8003546: 687b ldr r3, [r7, #4]
8003548: 3324 adds r3, #36 ; 0x24
800354a: 4618 mov r0, r3
800354c: f000 fd50 bl 8003ff0 <xTaskRemoveFromEventList>
8003550: 4603 mov r3, r0
8003552: 2b00 cmp r3, #0
8003554: d001 beq.n 800355a <prvUnlockQueue+0x32>
{
/* The task waiting has a higher priority so record that
a context switch is required. */
vTaskMissedYield();
8003556: f000 fe27 bl 80041a8 <vTaskMissedYield>
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
800355a: 7bfb ldrb r3, [r7, #15]
800355c: 3b01 subs r3, #1
800355e: b2db uxtb r3, r3
8003560: 73fb strb r3, [r7, #15]
while( cTxLock > queueLOCKED_UNMODIFIED )
8003562: f997 300f ldrsb.w r3, [r7, #15]
8003566: 2b00 cmp r3, #0
8003568: dce9 bgt.n 800353e <prvUnlockQueue+0x16>
800356a: e000 b.n 800356e <prvUnlockQueue+0x46>
break;
800356c: bf00 nop
}
pxQueue->cTxLock = queueUNLOCKED;
800356e: 687b ldr r3, [r7, #4]
8003570: 22ff movs r2, #255 ; 0xff
8003572: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
taskEXIT_CRITICAL();
8003576: f001 fc85 bl 8004e84 <vPortExitCritical>
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
800357a: f001 fc53 bl 8004e24 <vPortEnterCritical>
{
int8_t cRxLock = pxQueue->cRxLock;
800357e: 687b ldr r3, [r7, #4]
8003580: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
8003584: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
8003586: e011 b.n 80035ac <prvUnlockQueue+0x84>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8003588: 687b ldr r3, [r7, #4]
800358a: 691b ldr r3, [r3, #16]
800358c: 2b00 cmp r3, #0
800358e: d012 beq.n 80035b6 <prvUnlockQueue+0x8e>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
8003590: 687b ldr r3, [r7, #4]
8003592: 3310 adds r3, #16
8003594: 4618 mov r0, r3
8003596: f000 fd2b bl 8003ff0 <xTaskRemoveFromEventList>
800359a: 4603 mov r3, r0
800359c: 2b00 cmp r3, #0
800359e: d001 beq.n 80035a4 <prvUnlockQueue+0x7c>
{
vTaskMissedYield();
80035a0: f000 fe02 bl 80041a8 <vTaskMissedYield>
else
{
mtCOVERAGE_TEST_MARKER();
}
--cRxLock;
80035a4: 7bbb ldrb r3, [r7, #14]
80035a6: 3b01 subs r3, #1
80035a8: b2db uxtb r3, r3
80035aa: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
80035ac: f997 300e ldrsb.w r3, [r7, #14]
80035b0: 2b00 cmp r3, #0
80035b2: dce9 bgt.n 8003588 <prvUnlockQueue+0x60>
80035b4: e000 b.n 80035b8 <prvUnlockQueue+0x90>
}
else
{
break;
80035b6: bf00 nop
}
}
pxQueue->cRxLock = queueUNLOCKED;
80035b8: 687b ldr r3, [r7, #4]
80035ba: 22ff movs r2, #255 ; 0xff
80035bc: f883 2044 strb.w r2, [r3, #68] ; 0x44
}
taskEXIT_CRITICAL();
80035c0: f001 fc60 bl 8004e84 <vPortExitCritical>
}
80035c4: bf00 nop
80035c6: 3710 adds r7, #16
80035c8: 46bd mov sp, r7
80035ca: bd80 pop {r7, pc}
080035cc <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
80035cc: b580 push {r7, lr}
80035ce: b084 sub sp, #16
80035d0: af00 add r7, sp, #0
80035d2: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
80035d4: f001 fc26 bl 8004e24 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
80035d8: 687b ldr r3, [r7, #4]
80035da: 6b9b ldr r3, [r3, #56] ; 0x38
80035dc: 2b00 cmp r3, #0
80035de: d102 bne.n 80035e6 <prvIsQueueEmpty+0x1a>
{
xReturn = pdTRUE;
80035e0: 2301 movs r3, #1
80035e2: 60fb str r3, [r7, #12]
80035e4: e001 b.n 80035ea <prvIsQueueEmpty+0x1e>
}
else
{
xReturn = pdFALSE;
80035e6: 2300 movs r3, #0
80035e8: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
80035ea: f001 fc4b bl 8004e84 <vPortExitCritical>
return xReturn;
80035ee: 68fb ldr r3, [r7, #12]
}
80035f0: 4618 mov r0, r3
80035f2: 3710 adds r7, #16
80035f4: 46bd mov sp, r7
80035f6: bd80 pop {r7, pc}
080035f8 <prvIsQueueFull>:
return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
80035f8: b580 push {r7, lr}
80035fa: b084 sub sp, #16
80035fc: af00 add r7, sp, #0
80035fe: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
8003600: f001 fc10 bl 8004e24 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
8003604: 687b ldr r3, [r7, #4]
8003606: 6b9a ldr r2, [r3, #56] ; 0x38
8003608: 687b ldr r3, [r7, #4]
800360a: 6bdb ldr r3, [r3, #60] ; 0x3c
800360c: 429a cmp r2, r3
800360e: d102 bne.n 8003616 <prvIsQueueFull+0x1e>
{
xReturn = pdTRUE;
8003610: 2301 movs r3, #1
8003612: 60fb str r3, [r7, #12]
8003614: e001 b.n 800361a <prvIsQueueFull+0x22>
}
else
{
xReturn = pdFALSE;
8003616: 2300 movs r3, #0
8003618: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
800361a: f001 fc33 bl 8004e84 <vPortExitCritical>
return xReturn;
800361e: 68fb ldr r3, [r7, #12]
}
8003620: 4618 mov r0, r3
8003622: 3710 adds r7, #16
8003624: 46bd mov sp, r7
8003626: bd80 pop {r7, pc}
08003628 <vQueueAddToRegistry>:
/*-----------------------------------------------------------*/
#if ( configQUEUE_REGISTRY_SIZE > 0 )
void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
{
8003628: b480 push {r7}
800362a: b085 sub sp, #20
800362c: af00 add r7, sp, #0
800362e: 6078 str r0, [r7, #4]
8003630: 6039 str r1, [r7, #0]
UBaseType_t ux;
/* See if there is an empty space in the registry. A NULL name denotes
a free slot. */
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
8003632: 2300 movs r3, #0
8003634: 60fb str r3, [r7, #12]
8003636: e014 b.n 8003662 <vQueueAddToRegistry+0x3a>
{
if( xQueueRegistry[ ux ].pcQueueName == NULL )
8003638: 4a0f ldr r2, [pc, #60] ; (8003678 <vQueueAddToRegistry+0x50>)
800363a: 68fb ldr r3, [r7, #12]
800363c: f852 3033 ldr.w r3, [r2, r3, lsl #3]
8003640: 2b00 cmp r3, #0
8003642: d10b bne.n 800365c <vQueueAddToRegistry+0x34>
{
/* Store the information on this queue. */
xQueueRegistry[ ux ].pcQueueName = pcQueueName;
8003644: 490c ldr r1, [pc, #48] ; (8003678 <vQueueAddToRegistry+0x50>)
8003646: 68fb ldr r3, [r7, #12]
8003648: 683a ldr r2, [r7, #0]
800364a: f841 2033 str.w r2, [r1, r3, lsl #3]
xQueueRegistry[ ux ].xHandle = xQueue;
800364e: 4a0a ldr r2, [pc, #40] ; (8003678 <vQueueAddToRegistry+0x50>)
8003650: 68fb ldr r3, [r7, #12]
8003652: 00db lsls r3, r3, #3
8003654: 4413 add r3, r2
8003656: 687a ldr r2, [r7, #4]
8003658: 605a str r2, [r3, #4]
traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
break;
800365a: e006 b.n 800366a <vQueueAddToRegistry+0x42>
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
800365c: 68fb ldr r3, [r7, #12]
800365e: 3301 adds r3, #1
8003660: 60fb str r3, [r7, #12]
8003662: 68fb ldr r3, [r7, #12]
8003664: 2b07 cmp r3, #7
8003666: d9e7 bls.n 8003638 <vQueueAddToRegistry+0x10>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
8003668: bf00 nop
800366a: bf00 nop
800366c: 3714 adds r7, #20
800366e: 46bd mov sp, r7
8003670: f85d 7b04 ldr.w r7, [sp], #4
8003674: 4770 bx lr
8003676: bf00 nop
8003678: 20000880 .word 0x20000880
0800367c <vQueueWaitForMessageRestricted>:
/*-----------------------------------------------------------*/
#if ( configUSE_TIMERS == 1 )
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
{
800367c: b580 push {r7, lr}
800367e: b086 sub sp, #24
8003680: af00 add r7, sp, #0
8003682: 60f8 str r0, [r7, #12]
8003684: 60b9 str r1, [r7, #8]
8003686: 607a str r2, [r7, #4]
Queue_t * const pxQueue = xQueue;
8003688: 68fb ldr r3, [r7, #12]
800368a: 617b str r3, [r7, #20]
will not actually cause the task to block, just place it on a blocked
list. It will not block until the scheduler is unlocked - at which
time a yield will be performed. If an item is added to the queue while
the queue is locked, and the calling task blocks on the queue, then the
calling task will be immediately unblocked when the queue is unlocked. */
prvLockQueue( pxQueue );
800368c: f001 fbca bl 8004e24 <vPortEnterCritical>
8003690: 697b ldr r3, [r7, #20]
8003692: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
8003696: b25b sxtb r3, r3
8003698: f1b3 3fff cmp.w r3, #4294967295
800369c: d103 bne.n 80036a6 <vQueueWaitForMessageRestricted+0x2a>
800369e: 697b ldr r3, [r7, #20]
80036a0: 2200 movs r2, #0
80036a2: f883 2044 strb.w r2, [r3, #68] ; 0x44
80036a6: 697b ldr r3, [r7, #20]
80036a8: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80036ac: b25b sxtb r3, r3
80036ae: f1b3 3fff cmp.w r3, #4294967295
80036b2: d103 bne.n 80036bc <vQueueWaitForMessageRestricted+0x40>
80036b4: 697b ldr r3, [r7, #20]
80036b6: 2200 movs r2, #0
80036b8: f883 2045 strb.w r2, [r3, #69] ; 0x45
80036bc: f001 fbe2 bl 8004e84 <vPortExitCritical>
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
80036c0: 697b ldr r3, [r7, #20]
80036c2: 6b9b ldr r3, [r3, #56] ; 0x38
80036c4: 2b00 cmp r3, #0
80036c6: d106 bne.n 80036d6 <vQueueWaitForMessageRestricted+0x5a>
{
/* There is nothing in the queue, block for the specified period. */
vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
80036c8: 697b ldr r3, [r7, #20]
80036ca: 3324 adds r3, #36 ; 0x24
80036cc: 687a ldr r2, [r7, #4]
80036ce: 68b9 ldr r1, [r7, #8]
80036d0: 4618 mov r0, r3
80036d2: f000 fc61 bl 8003f98 <vTaskPlaceOnEventListRestricted>
}
else
{
mtCOVERAGE_TEST_MARKER();
}
prvUnlockQueue( pxQueue );
80036d6: 6978 ldr r0, [r7, #20]
80036d8: f7ff ff26 bl 8003528 <prvUnlockQueue>
}
80036dc: bf00 nop
80036de: 3718 adds r7, #24
80036e0: 46bd mov sp, r7
80036e2: bd80 pop {r7, pc}
080036e4 <xTaskCreateStatic>:
const uint32_t ulStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer )
{
80036e4: b580 push {r7, lr}
80036e6: b08e sub sp, #56 ; 0x38
80036e8: af04 add r7, sp, #16
80036ea: 60f8 str r0, [r7, #12]
80036ec: 60b9 str r1, [r7, #8]
80036ee: 607a str r2, [r7, #4]
80036f0: 603b str r3, [r7, #0]
TCB_t *pxNewTCB;
TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
80036f2: 6b7b ldr r3, [r7, #52] ; 0x34
80036f4: 2b00 cmp r3, #0
80036f6: d10a bne.n 800370e <xTaskCreateStatic+0x2a>
__asm volatile
80036f8: f04f 0350 mov.w r3, #80 ; 0x50
80036fc: f383 8811 msr BASEPRI, r3
8003700: f3bf 8f6f isb sy
8003704: f3bf 8f4f dsb sy
8003708: 623b str r3, [r7, #32]
}
800370a: bf00 nop
800370c: e7fe b.n 800370c <xTaskCreateStatic+0x28>
configASSERT( pxTaskBuffer != NULL );
800370e: 6bbb ldr r3, [r7, #56] ; 0x38
8003710: 2b00 cmp r3, #0
8003712: d10a bne.n 800372a <xTaskCreateStatic+0x46>
__asm volatile
8003714: f04f 0350 mov.w r3, #80 ; 0x50
8003718: f383 8811 msr BASEPRI, r3
800371c: f3bf 8f6f isb sy
8003720: f3bf 8f4f dsb sy
8003724: 61fb str r3, [r7, #28]
}
8003726: bf00 nop
8003728: e7fe b.n 8003728 <xTaskCreateStatic+0x44>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticTask_t equals the size of the real task
structure. */
volatile size_t xSize = sizeof( StaticTask_t );
800372a: 23a8 movs r3, #168 ; 0xa8
800372c: 613b str r3, [r7, #16]
configASSERT( xSize == sizeof( TCB_t ) );
800372e: 693b ldr r3, [r7, #16]
8003730: 2ba8 cmp r3, #168 ; 0xa8
8003732: d00a beq.n 800374a <xTaskCreateStatic+0x66>
__asm volatile
8003734: f04f 0350 mov.w r3, #80 ; 0x50
8003738: f383 8811 msr BASEPRI, r3
800373c: f3bf 8f6f isb sy
8003740: f3bf 8f4f dsb sy
8003744: 61bb str r3, [r7, #24]
}
8003746: bf00 nop
8003748: e7fe b.n 8003748 <xTaskCreateStatic+0x64>
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
800374a: 693b ldr r3, [r7, #16]
}
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
800374c: 6bbb ldr r3, [r7, #56] ; 0x38
800374e: 2b00 cmp r3, #0
8003750: d01e beq.n 8003790 <xTaskCreateStatic+0xac>
8003752: 6b7b ldr r3, [r7, #52] ; 0x34
8003754: 2b00 cmp r3, #0
8003756: d01b beq.n 8003790 <xTaskCreateStatic+0xac>
{
/* The memory used for the task's TCB and stack are passed into this
function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
8003758: 6bbb ldr r3, [r7, #56] ; 0x38
800375a: 627b str r3, [r7, #36] ; 0x24
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
800375c: 6a7b ldr r3, [r7, #36] ; 0x24
800375e: 6b7a ldr r2, [r7, #52] ; 0x34
8003760: 631a str r2, [r3, #48] ; 0x30
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
8003762: 6a7b ldr r3, [r7, #36] ; 0x24
8003764: 2202 movs r2, #2
8003766: f883 20a5 strb.w r2, [r3, #165] ; 0xa5
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
800376a: 2300 movs r3, #0
800376c: 9303 str r3, [sp, #12]
800376e: 6a7b ldr r3, [r7, #36] ; 0x24
8003770: 9302 str r3, [sp, #8]
8003772: f107 0314 add.w r3, r7, #20
8003776: 9301 str r3, [sp, #4]
8003778: 6b3b ldr r3, [r7, #48] ; 0x30
800377a: 9300 str r3, [sp, #0]
800377c: 683b ldr r3, [r7, #0]
800377e: 687a ldr r2, [r7, #4]
8003780: 68b9 ldr r1, [r7, #8]
8003782: 68f8 ldr r0, [r7, #12]
8003784: f000 f850 bl 8003828 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
8003788: 6a78 ldr r0, [r7, #36] ; 0x24
800378a: f000 f8f3 bl 8003974 <prvAddNewTaskToReadyList>
800378e: e001 b.n 8003794 <xTaskCreateStatic+0xb0>
}
else
{
xReturn = NULL;
8003790: 2300 movs r3, #0
8003792: 617b str r3, [r7, #20]
}
return xReturn;
8003794: 697b ldr r3, [r7, #20]
}
8003796: 4618 mov r0, r3
8003798: 3728 adds r7, #40 ; 0x28
800379a: 46bd mov sp, r7
800379c: bd80 pop {r7, pc}
0800379e <xTaskCreate>:
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const configSTACK_DEPTH_TYPE usStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask )
{
800379e: b580 push {r7, lr}
80037a0: b08c sub sp, #48 ; 0x30
80037a2: af04 add r7, sp, #16
80037a4: 60f8 str r0, [r7, #12]
80037a6: 60b9 str r1, [r7, #8]
80037a8: 603b str r3, [r7, #0]
80037aa: 4613 mov r3, r2
80037ac: 80fb strh r3, [r7, #6]
#else /* portSTACK_GROWTH */
{
StackType_t *pxStack;
/* Allocate space for the stack used by the task being created. */
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
80037ae: 88fb ldrh r3, [r7, #6]
80037b0: 009b lsls r3, r3, #2
80037b2: 4618 mov r0, r3
80037b4: f001 fc58 bl 8005068 <pvPortMalloc>
80037b8: 6178 str r0, [r7, #20]
if( pxStack != NULL )
80037ba: 697b ldr r3, [r7, #20]
80037bc: 2b00 cmp r3, #0
80037be: d00e beq.n 80037de <xTaskCreate+0x40>
{
/* Allocate space for the TCB. */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
80037c0: 20a8 movs r0, #168 ; 0xa8
80037c2: f001 fc51 bl 8005068 <pvPortMalloc>
80037c6: 61f8 str r0, [r7, #28]
if( pxNewTCB != NULL )
80037c8: 69fb ldr r3, [r7, #28]
80037ca: 2b00 cmp r3, #0
80037cc: d003 beq.n 80037d6 <xTaskCreate+0x38>
{
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
80037ce: 69fb ldr r3, [r7, #28]
80037d0: 697a ldr r2, [r7, #20]
80037d2: 631a str r2, [r3, #48] ; 0x30
80037d4: e005 b.n 80037e2 <xTaskCreate+0x44>
}
else
{
/* The stack cannot be used as the TCB was not created. Free
it again. */
vPortFree( pxStack );
80037d6: 6978 ldr r0, [r7, #20]
80037d8: f001 fd12 bl 8005200 <vPortFree>
80037dc: e001 b.n 80037e2 <xTaskCreate+0x44>
}
}
else
{
pxNewTCB = NULL;
80037de: 2300 movs r3, #0
80037e0: 61fb str r3, [r7, #28]
}
}
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
80037e2: 69fb ldr r3, [r7, #28]
80037e4: 2b00 cmp r3, #0
80037e6: d017 beq.n 8003818 <xTaskCreate+0x7a>
{
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
80037e8: 69fb ldr r3, [r7, #28]
80037ea: 2200 movs r2, #0
80037ec: f883 20a5 strb.w r2, [r3, #165] ; 0xa5
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
80037f0: 88fa ldrh r2, [r7, #6]
80037f2: 2300 movs r3, #0
80037f4: 9303 str r3, [sp, #12]
80037f6: 69fb ldr r3, [r7, #28]
80037f8: 9302 str r3, [sp, #8]
80037fa: 6afb ldr r3, [r7, #44] ; 0x2c
80037fc: 9301 str r3, [sp, #4]
80037fe: 6abb ldr r3, [r7, #40] ; 0x28
8003800: 9300 str r3, [sp, #0]
8003802: 683b ldr r3, [r7, #0]
8003804: 68b9 ldr r1, [r7, #8]
8003806: 68f8 ldr r0, [r7, #12]
8003808: f000 f80e bl 8003828 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
800380c: 69f8 ldr r0, [r7, #28]
800380e: f000 f8b1 bl 8003974 <prvAddNewTaskToReadyList>
xReturn = pdPASS;
8003812: 2301 movs r3, #1
8003814: 61bb str r3, [r7, #24]
8003816: e002 b.n 800381e <xTaskCreate+0x80>
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
8003818: f04f 33ff mov.w r3, #4294967295
800381c: 61bb str r3, [r7, #24]
}
return xReturn;
800381e: 69bb ldr r3, [r7, #24]
}
8003820: 4618 mov r0, r3
8003822: 3720 adds r7, #32
8003824: 46bd mov sp, r7
8003826: bd80 pop {r7, pc}
08003828 <prvInitialiseNewTask>:
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
TCB_t *pxNewTCB,
const MemoryRegion_t * const xRegions )
{
8003828: b580 push {r7, lr}
800382a: b088 sub sp, #32
800382c: af00 add r7, sp, #0
800382e: 60f8 str r0, [r7, #12]
8003830: 60b9 str r1, [r7, #8]
8003832: 607a str r2, [r7, #4]
8003834: 603b str r3, [r7, #0]
/* Avoid dependency on memset() if it is not required. */
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
8003836: 6b3b ldr r3, [r7, #48] ; 0x30
8003838: 6b18 ldr r0, [r3, #48] ; 0x30
800383a: 687b ldr r3, [r7, #4]
800383c: 009b lsls r3, r3, #2
800383e: 461a mov r2, r3
8003840: 21a5 movs r1, #165 ; 0xa5
8003842: f001 fdfb bl 800543c <memset>
grows from high memory to low (as per the 80x86) or vice versa.
portSTACK_GROWTH is used to make the result positive or negative as required
by the port. */
#if( portSTACK_GROWTH < 0 )
{
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
8003846: 6b3b ldr r3, [r7, #48] ; 0x30
8003848: 6b1a ldr r2, [r3, #48] ; 0x30
800384a: 687b ldr r3, [r7, #4]
800384c: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000
8003850: 3b01 subs r3, #1
8003852: 009b lsls r3, r3, #2
8003854: 4413 add r3, r2
8003856: 61bb str r3, [r7, #24]
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
8003858: 69bb ldr r3, [r7, #24]
800385a: f023 0307 bic.w r3, r3, #7
800385e: 61bb str r3, [r7, #24]
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
8003860: 69bb ldr r3, [r7, #24]
8003862: f003 0307 and.w r3, r3, #7
8003866: 2b00 cmp r3, #0
8003868: d00a beq.n 8003880 <prvInitialiseNewTask+0x58>
__asm volatile
800386a: f04f 0350 mov.w r3, #80 ; 0x50
800386e: f383 8811 msr BASEPRI, r3
8003872: f3bf 8f6f isb sy
8003876: f3bf 8f4f dsb sy
800387a: 617b str r3, [r7, #20]
}
800387c: bf00 nop
800387e: e7fe b.n 800387e <prvInitialiseNewTask+0x56>
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
}
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
if( pcName != NULL )
8003880: 68bb ldr r3, [r7, #8]
8003882: 2b00 cmp r3, #0
8003884: d01f beq.n 80038c6 <prvInitialiseNewTask+0x9e>
{
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
8003886: 2300 movs r3, #0
8003888: 61fb str r3, [r7, #28]
800388a: e012 b.n 80038b2 <prvInitialiseNewTask+0x8a>
{
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
800388c: 68ba ldr r2, [r7, #8]
800388e: 69fb ldr r3, [r7, #28]
8003890: 4413 add r3, r2
8003892: 7819 ldrb r1, [r3, #0]
8003894: 6b3a ldr r2, [r7, #48] ; 0x30
8003896: 69fb ldr r3, [r7, #28]
8003898: 4413 add r3, r2
800389a: 3334 adds r3, #52 ; 0x34
800389c: 460a mov r2, r1
800389e: 701a strb r2, [r3, #0]
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
configMAX_TASK_NAME_LEN characters just in case the memory after the
string is not accessible (extremely unlikely). */
if( pcName[ x ] == ( char ) 0x00 )
80038a0: 68ba ldr r2, [r7, #8]
80038a2: 69fb ldr r3, [r7, #28]
80038a4: 4413 add r3, r2
80038a6: 781b ldrb r3, [r3, #0]
80038a8: 2b00 cmp r3, #0
80038aa: d006 beq.n 80038ba <prvInitialiseNewTask+0x92>
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
80038ac: 69fb ldr r3, [r7, #28]
80038ae: 3301 adds r3, #1
80038b0: 61fb str r3, [r7, #28]
80038b2: 69fb ldr r3, [r7, #28]
80038b4: 2b0f cmp r3, #15
80038b6: d9e9 bls.n 800388c <prvInitialiseNewTask+0x64>
80038b8: e000 b.n 80038bc <prvInitialiseNewTask+0x94>
{
break;
80038ba: bf00 nop
}
}
/* Ensure the name string is terminated in the case that the string length
was greater or equal to configMAX_TASK_NAME_LEN. */
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
80038bc: 6b3b ldr r3, [r7, #48] ; 0x30
80038be: 2200 movs r2, #0
80038c0: f883 2043 strb.w r2, [r3, #67] ; 0x43
80038c4: e003 b.n 80038ce <prvInitialiseNewTask+0xa6>
}
else
{
/* The task has not been given a name, so just ensure there is a NULL
terminator when it is read out. */
pxNewTCB->pcTaskName[ 0 ] = 0x00;
80038c6: 6b3b ldr r3, [r7, #48] ; 0x30
80038c8: 2200 movs r2, #0
80038ca: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
80038ce: 6abb ldr r3, [r7, #40] ; 0x28
80038d0: 2b37 cmp r3, #55 ; 0x37
80038d2: d901 bls.n 80038d8 <prvInitialiseNewTask+0xb0>
{
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
80038d4: 2337 movs r3, #55 ; 0x37
80038d6: 62bb str r3, [r7, #40] ; 0x28
else
{
mtCOVERAGE_TEST_MARKER();
}
pxNewTCB->uxPriority = uxPriority;
80038d8: 6b3b ldr r3, [r7, #48] ; 0x30
80038da: 6aba ldr r2, [r7, #40] ; 0x28
80038dc: 62da str r2, [r3, #44] ; 0x2c
#if ( configUSE_MUTEXES == 1 )
{
pxNewTCB->uxBasePriority = uxPriority;
80038de: 6b3b ldr r3, [r7, #48] ; 0x30
80038e0: 6aba ldr r2, [r7, #40] ; 0x28
80038e2: 64da str r2, [r3, #76] ; 0x4c
pxNewTCB->uxMutexesHeld = 0;
80038e4: 6b3b ldr r3, [r7, #48] ; 0x30
80038e6: 2200 movs r2, #0
80038e8: 651a str r2, [r3, #80] ; 0x50
}
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
80038ea: 6b3b ldr r3, [r7, #48] ; 0x30
80038ec: 3304 adds r3, #4
80038ee: 4618 mov r0, r3
80038f0: f7ff f978 bl 8002be4 <vListInitialiseItem>
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
80038f4: 6b3b ldr r3, [r7, #48] ; 0x30
80038f6: 3318 adds r3, #24
80038f8: 4618 mov r0, r3
80038fa: f7ff f973 bl 8002be4 <vListInitialiseItem>
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
80038fe: 6b3b ldr r3, [r7, #48] ; 0x30
8003900: 6b3a ldr r2, [r7, #48] ; 0x30
8003902: 611a str r2, [r3, #16]
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8003904: 6abb ldr r3, [r7, #40] ; 0x28
8003906: f1c3 0238 rsb r2, r3, #56 ; 0x38
800390a: 6b3b ldr r3, [r7, #48] ; 0x30
800390c: 619a str r2, [r3, #24]
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
800390e: 6b3b ldr r3, [r7, #48] ; 0x30
8003910: 6b3a ldr r2, [r7, #48] ; 0x30
8003912: 625a str r2, [r3, #36] ; 0x24
}
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
{
pxNewTCB->ulNotifiedValue = 0;
8003914: 6b3b ldr r3, [r7, #48] ; 0x30
8003916: 2200 movs r2, #0
8003918: f8c3 20a0 str.w r2, [r3, #160] ; 0xa0
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
800391c: 6b3b ldr r3, [r7, #48] ; 0x30
800391e: 2200 movs r2, #0
8003920: f883 20a4 strb.w r2, [r3, #164] ; 0xa4
#if ( configUSE_NEWLIB_REENTRANT == 1 )
{
/* Initialise this task's Newlib reent structure.
See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
for additional information. */
_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
8003924: 6b3b ldr r3, [r7, #48] ; 0x30
8003926: 3354 adds r3, #84 ; 0x54
8003928: 224c movs r2, #76 ; 0x4c
800392a: 2100 movs r1, #0
800392c: 4618 mov r0, r3
800392e: f001 fd85 bl 800543c <memset>
8003932: 6b3b ldr r3, [r7, #48] ; 0x30
8003934: 4a0c ldr r2, [pc, #48] ; (8003968 <prvInitialiseNewTask+0x140>)
8003936: 659a str r2, [r3, #88] ; 0x58
8003938: 6b3b ldr r3, [r7, #48] ; 0x30
800393a: 4a0c ldr r2, [pc, #48] ; (800396c <prvInitialiseNewTask+0x144>)
800393c: 65da str r2, [r3, #92] ; 0x5c
800393e: 6b3b ldr r3, [r7, #48] ; 0x30
8003940: 4a0b ldr r2, [pc, #44] ; (8003970 <prvInitialiseNewTask+0x148>)
8003942: 661a str r2, [r3, #96] ; 0x60
}
#endif /* portSTACK_GROWTH */
}
#else /* portHAS_STACK_OVERFLOW_CHECKING */
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
8003944: 683a ldr r2, [r7, #0]
8003946: 68f9 ldr r1, [r7, #12]
8003948: 69b8 ldr r0, [r7, #24]
800394a: f001 f941 bl 8004bd0 <pxPortInitialiseStack>
800394e: 4602 mov r2, r0
8003950: 6b3b ldr r3, [r7, #48] ; 0x30
8003952: 601a str r2, [r3, #0]
}
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
8003954: 6afb ldr r3, [r7, #44] ; 0x2c
8003956: 2b00 cmp r3, #0
8003958: d002 beq.n 8003960 <prvInitialiseNewTask+0x138>
{
/* Pass the handle out in an anonymous way. The handle can be used to
change the created task's priority, delete the created task, etc.*/
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
800395a: 6afb ldr r3, [r7, #44] ; 0x2c
800395c: 6b3a ldr r2, [r7, #48] ; 0x30
800395e: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8003960: bf00 nop
8003962: 3720 adds r7, #32
8003964: 46bd mov sp, r7
8003966: bd80 pop {r7, pc}
8003968: 20004b14 .word 0x20004b14
800396c: 20004b7c .word 0x20004b7c
8003970: 20004be4 .word 0x20004be4
08003974 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
8003974: b580 push {r7, lr}
8003976: b082 sub sp, #8
8003978: af00 add r7, sp, #0
800397a: 6078 str r0, [r7, #4]
/* Ensure interrupts don't access the task lists while the lists are being
updated. */
taskENTER_CRITICAL();
800397c: f001 fa52 bl 8004e24 <vPortEnterCritical>
{
uxCurrentNumberOfTasks++;
8003980: 4b2d ldr r3, [pc, #180] ; (8003a38 <prvAddNewTaskToReadyList+0xc4>)
8003982: 681b ldr r3, [r3, #0]
8003984: 3301 adds r3, #1
8003986: 4a2c ldr r2, [pc, #176] ; (8003a38 <prvAddNewTaskToReadyList+0xc4>)
8003988: 6013 str r3, [r2, #0]
if( pxCurrentTCB == NULL )
800398a: 4b2c ldr r3, [pc, #176] ; (8003a3c <prvAddNewTaskToReadyList+0xc8>)
800398c: 681b ldr r3, [r3, #0]
800398e: 2b00 cmp r3, #0
8003990: d109 bne.n 80039a6 <prvAddNewTaskToReadyList+0x32>
{
/* There are no other tasks, or all the other tasks are in
the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
8003992: 4a2a ldr r2, [pc, #168] ; (8003a3c <prvAddNewTaskToReadyList+0xc8>)
8003994: 687b ldr r3, [r7, #4]
8003996: 6013 str r3, [r2, #0]
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
8003998: 4b27 ldr r3, [pc, #156] ; (8003a38 <prvAddNewTaskToReadyList+0xc4>)
800399a: 681b ldr r3, [r3, #0]
800399c: 2b01 cmp r3, #1
800399e: d110 bne.n 80039c2 <prvAddNewTaskToReadyList+0x4e>
{
/* This is the first task to be created so do the preliminary
initialisation required. We will not recover if this call
fails, but we will report the failure. */
prvInitialiseTaskLists();
80039a0: f000 fc26 bl 80041f0 <prvInitialiseTaskLists>
80039a4: e00d b.n 80039c2 <prvAddNewTaskToReadyList+0x4e>
else
{
/* If the scheduler is not already running, make this task the
current task if it is the highest priority task to be created
so far. */
if( xSchedulerRunning == pdFALSE )
80039a6: 4b26 ldr r3, [pc, #152] ; (8003a40 <prvAddNewTaskToReadyList+0xcc>)
80039a8: 681b ldr r3, [r3, #0]
80039aa: 2b00 cmp r3, #0
80039ac: d109 bne.n 80039c2 <prvAddNewTaskToReadyList+0x4e>
{
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
80039ae: 4b23 ldr r3, [pc, #140] ; (8003a3c <prvAddNewTaskToReadyList+0xc8>)
80039b0: 681b ldr r3, [r3, #0]
80039b2: 6ada ldr r2, [r3, #44] ; 0x2c
80039b4: 687b ldr r3, [r7, #4]
80039b6: 6adb ldr r3, [r3, #44] ; 0x2c
80039b8: 429a cmp r2, r3
80039ba: d802 bhi.n 80039c2 <prvAddNewTaskToReadyList+0x4e>
{
pxCurrentTCB = pxNewTCB;
80039bc: 4a1f ldr r2, [pc, #124] ; (8003a3c <prvAddNewTaskToReadyList+0xc8>)
80039be: 687b ldr r3, [r7, #4]
80039c0: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
uxTaskNumber++;
80039c2: 4b20 ldr r3, [pc, #128] ; (8003a44 <prvAddNewTaskToReadyList+0xd0>)
80039c4: 681b ldr r3, [r3, #0]
80039c6: 3301 adds r3, #1
80039c8: 4a1e ldr r2, [pc, #120] ; (8003a44 <prvAddNewTaskToReadyList+0xd0>)
80039ca: 6013 str r3, [r2, #0]
#if ( configUSE_TRACE_FACILITY == 1 )
{
/* Add a counter into the TCB for tracing only. */
pxNewTCB->uxTCBNumber = uxTaskNumber;
80039cc: 4b1d ldr r3, [pc, #116] ; (8003a44 <prvAddNewTaskToReadyList+0xd0>)
80039ce: 681a ldr r2, [r3, #0]
80039d0: 687b ldr r3, [r7, #4]
80039d2: 645a str r2, [r3, #68] ; 0x44
}
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
prvAddTaskToReadyList( pxNewTCB );
80039d4: 687b ldr r3, [r7, #4]
80039d6: 6ada ldr r2, [r3, #44] ; 0x2c
80039d8: 4b1b ldr r3, [pc, #108] ; (8003a48 <prvAddNewTaskToReadyList+0xd4>)
80039da: 681b ldr r3, [r3, #0]
80039dc: 429a cmp r2, r3
80039de: d903 bls.n 80039e8 <prvAddNewTaskToReadyList+0x74>
80039e0: 687b ldr r3, [r7, #4]
80039e2: 6adb ldr r3, [r3, #44] ; 0x2c
80039e4: 4a18 ldr r2, [pc, #96] ; (8003a48 <prvAddNewTaskToReadyList+0xd4>)
80039e6: 6013 str r3, [r2, #0]
80039e8: 687b ldr r3, [r7, #4]
80039ea: 6ada ldr r2, [r3, #44] ; 0x2c
80039ec: 4613 mov r3, r2
80039ee: 009b lsls r3, r3, #2
80039f0: 4413 add r3, r2
80039f2: 009b lsls r3, r3, #2
80039f4: 4a15 ldr r2, [pc, #84] ; (8003a4c <prvAddNewTaskToReadyList+0xd8>)
80039f6: 441a add r2, r3
80039f8: 687b ldr r3, [r7, #4]
80039fa: 3304 adds r3, #4
80039fc: 4619 mov r1, r3
80039fe: 4610 mov r0, r2
8003a00: f7ff f8fd bl 8002bfe <vListInsertEnd>
portSETUP_TCB( pxNewTCB );
}
taskEXIT_CRITICAL();
8003a04: f001 fa3e bl 8004e84 <vPortExitCritical>
if( xSchedulerRunning != pdFALSE )
8003a08: 4b0d ldr r3, [pc, #52] ; (8003a40 <prvAddNewTaskToReadyList+0xcc>)
8003a0a: 681b ldr r3, [r3, #0]
8003a0c: 2b00 cmp r3, #0
8003a0e: d00e beq.n 8003a2e <prvAddNewTaskToReadyList+0xba>
{
/* If the created task is of a higher priority than the current task
then it should run now. */
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
8003a10: 4b0a ldr r3, [pc, #40] ; (8003a3c <prvAddNewTaskToReadyList+0xc8>)
8003a12: 681b ldr r3, [r3, #0]
8003a14: 6ada ldr r2, [r3, #44] ; 0x2c
8003a16: 687b ldr r3, [r7, #4]
8003a18: 6adb ldr r3, [r3, #44] ; 0x2c
8003a1a: 429a cmp r2, r3
8003a1c: d207 bcs.n 8003a2e <prvAddNewTaskToReadyList+0xba>
{
taskYIELD_IF_USING_PREEMPTION();
8003a1e: 4b0c ldr r3, [pc, #48] ; (8003a50 <prvAddNewTaskToReadyList+0xdc>)
8003a20: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003a24: 601a str r2, [r3, #0]
8003a26: f3bf 8f4f dsb sy
8003a2a: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8003a2e: bf00 nop
8003a30: 3708 adds r7, #8
8003a32: 46bd mov sp, r7
8003a34: bd80 pop {r7, pc}
8003a36: bf00 nop
8003a38: 20000d94 .word 0x20000d94
8003a3c: 200008c0 .word 0x200008c0
8003a40: 20000da0 .word 0x20000da0
8003a44: 20000db0 .word 0x20000db0
8003a48: 20000d9c .word 0x20000d9c
8003a4c: 200008c4 .word 0x200008c4
8003a50: e000ed04 .word 0xe000ed04
08003a54 <vTaskDelay>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( const TickType_t xTicksToDelay )
{
8003a54: b580 push {r7, lr}
8003a56: b084 sub sp, #16
8003a58: af00 add r7, sp, #0
8003a5a: 6078 str r0, [r7, #4]
BaseType_t xAlreadyYielded = pdFALSE;
8003a5c: 2300 movs r3, #0
8003a5e: 60fb str r3, [r7, #12]
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
8003a60: 687b ldr r3, [r7, #4]
8003a62: 2b00 cmp r3, #0
8003a64: d017 beq.n 8003a96 <vTaskDelay+0x42>
{
configASSERT( uxSchedulerSuspended == 0 );
8003a66: 4b13 ldr r3, [pc, #76] ; (8003ab4 <vTaskDelay+0x60>)
8003a68: 681b ldr r3, [r3, #0]
8003a6a: 2b00 cmp r3, #0
8003a6c: d00a beq.n 8003a84 <vTaskDelay+0x30>
__asm volatile
8003a6e: f04f 0350 mov.w r3, #80 ; 0x50
8003a72: f383 8811 msr BASEPRI, r3
8003a76: f3bf 8f6f isb sy
8003a7a: f3bf 8f4f dsb sy
8003a7e: 60bb str r3, [r7, #8]
}
8003a80: bf00 nop
8003a82: e7fe b.n 8003a82 <vTaskDelay+0x2e>
vTaskSuspendAll();
8003a84: f000 f88a bl 8003b9c <vTaskSuspendAll>
list or removed from the blocked list until the scheduler
is resumed.
This task cannot be in an event list as it is the currently
executing task. */
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
8003a88: 2100 movs r1, #0
8003a8a: 6878 ldr r0, [r7, #4]
8003a8c: f000 fcfe bl 800448c <prvAddCurrentTaskToDelayedList>
}
xAlreadyYielded = xTaskResumeAll();
8003a90: f000 f892 bl 8003bb8 <xTaskResumeAll>
8003a94: 60f8 str r0, [r7, #12]
mtCOVERAGE_TEST_MARKER();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
8003a96: 68fb ldr r3, [r7, #12]
8003a98: 2b00 cmp r3, #0
8003a9a: d107 bne.n 8003aac <vTaskDelay+0x58>
{
portYIELD_WITHIN_API();
8003a9c: 4b06 ldr r3, [pc, #24] ; (8003ab8 <vTaskDelay+0x64>)
8003a9e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003aa2: 601a str r2, [r3, #0]
8003aa4: f3bf 8f4f dsb sy
8003aa8: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8003aac: bf00 nop
8003aae: 3710 adds r7, #16
8003ab0: 46bd mov sp, r7
8003ab2: bd80 pop {r7, pc}
8003ab4: 20000dbc .word 0x20000dbc
8003ab8: e000ed04 .word 0xe000ed04
08003abc <vTaskStartScheduler>:
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/
void vTaskStartScheduler( void )
{
8003abc: b580 push {r7, lr}
8003abe: b08a sub sp, #40 ; 0x28
8003ac0: af04 add r7, sp, #16
BaseType_t xReturn;
/* Add the idle task at the lowest priority. */
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
8003ac2: 2300 movs r3, #0
8003ac4: 60bb str r3, [r7, #8]
StackType_t *pxIdleTaskStackBuffer = NULL;
8003ac6: 2300 movs r3, #0
8003ac8: 607b str r3, [r7, #4]
uint32_t ulIdleTaskStackSize;
/* The Idle task is created using user provided RAM - obtain the
address of the RAM then create the idle task. */
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
8003aca: 463a mov r2, r7
8003acc: 1d39 adds r1, r7, #4
8003ace: f107 0308 add.w r3, r7, #8
8003ad2: 4618 mov r0, r3
8003ad4: f7ff f832 bl 8002b3c <vApplicationGetIdleTaskMemory>
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
8003ad8: 6839 ldr r1, [r7, #0]
8003ada: 687b ldr r3, [r7, #4]
8003adc: 68ba ldr r2, [r7, #8]
8003ade: 9202 str r2, [sp, #8]
8003ae0: 9301 str r3, [sp, #4]
8003ae2: 2300 movs r3, #0
8003ae4: 9300 str r3, [sp, #0]
8003ae6: 2300 movs r3, #0
8003ae8: 460a mov r2, r1
8003aea: 4924 ldr r1, [pc, #144] ; (8003b7c <vTaskStartScheduler+0xc0>)
8003aec: 4824 ldr r0, [pc, #144] ; (8003b80 <vTaskStartScheduler+0xc4>)
8003aee: f7ff fdf9 bl 80036e4 <xTaskCreateStatic>
8003af2: 4603 mov r3, r0
8003af4: 4a23 ldr r2, [pc, #140] ; (8003b84 <vTaskStartScheduler+0xc8>)
8003af6: 6013 str r3, [r2, #0]
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
pxIdleTaskStackBuffer,
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
if( xIdleTaskHandle != NULL )
8003af8: 4b22 ldr r3, [pc, #136] ; (8003b84 <vTaskStartScheduler+0xc8>)
8003afa: 681b ldr r3, [r3, #0]
8003afc: 2b00 cmp r3, #0
8003afe: d002 beq.n 8003b06 <vTaskStartScheduler+0x4a>
{
xReturn = pdPASS;
8003b00: 2301 movs r3, #1
8003b02: 617b str r3, [r7, #20]
8003b04: e001 b.n 8003b0a <vTaskStartScheduler+0x4e>
}
else
{
xReturn = pdFAIL;
8003b06: 2300 movs r3, #0
8003b08: 617b str r3, [r7, #20]
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
#if ( configUSE_TIMERS == 1 )
{
if( xReturn == pdPASS )
8003b0a: 697b ldr r3, [r7, #20]
8003b0c: 2b01 cmp r3, #1
8003b0e: d102 bne.n 8003b16 <vTaskStartScheduler+0x5a>
{
xReturn = xTimerCreateTimerTask();
8003b10: f000 fd10 bl 8004534 <xTimerCreateTimerTask>
8003b14: 6178 str r0, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_TIMERS */
if( xReturn == pdPASS )
8003b16: 697b ldr r3, [r7, #20]
8003b18: 2b01 cmp r3, #1
8003b1a: d11b bne.n 8003b54 <vTaskStartScheduler+0x98>
__asm volatile
8003b1c: f04f 0350 mov.w r3, #80 ; 0x50
8003b20: f383 8811 msr BASEPRI, r3
8003b24: f3bf 8f6f isb sy
8003b28: f3bf 8f4f dsb sy
8003b2c: 613b str r3, [r7, #16]
}
8003b2e: bf00 nop
{
/* Switch Newlib's _impure_ptr variable to point to the _reent
structure specific to the task that will run first.
See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
for additional information. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
8003b30: 4b15 ldr r3, [pc, #84] ; (8003b88 <vTaskStartScheduler+0xcc>)
8003b32: 681b ldr r3, [r3, #0]
8003b34: 3354 adds r3, #84 ; 0x54
8003b36: 4a15 ldr r2, [pc, #84] ; (8003b8c <vTaskStartScheduler+0xd0>)
8003b38: 6013 str r3, [r2, #0]
}
#endif /* configUSE_NEWLIB_REENTRANT */
xNextTaskUnblockTime = portMAX_DELAY;
8003b3a: 4b15 ldr r3, [pc, #84] ; (8003b90 <vTaskStartScheduler+0xd4>)
8003b3c: f04f 32ff mov.w r2, #4294967295
8003b40: 601a str r2, [r3, #0]
xSchedulerRunning = pdTRUE;
8003b42: 4b14 ldr r3, [pc, #80] ; (8003b94 <vTaskStartScheduler+0xd8>)
8003b44: 2201 movs r2, #1
8003b46: 601a str r2, [r3, #0]
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
8003b48: 4b13 ldr r3, [pc, #76] ; (8003b98 <vTaskStartScheduler+0xdc>)
8003b4a: 2200 movs r2, #0
8003b4c: 601a str r2, [r3, #0]
traceTASK_SWITCHED_IN();
/* Setting up the timer tick is hardware specific and thus in the
portable interface. */
if( xPortStartScheduler() != pdFALSE )
8003b4e: f001 f8c7 bl 8004ce0 <xPortStartScheduler>
}
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
meaning xIdleTaskHandle is not used anywhere else. */
( void ) xIdleTaskHandle;
}
8003b52: e00e b.n 8003b72 <vTaskStartScheduler+0xb6>
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
8003b54: 697b ldr r3, [r7, #20]
8003b56: f1b3 3fff cmp.w r3, #4294967295
8003b5a: d10a bne.n 8003b72 <vTaskStartScheduler+0xb6>
__asm volatile
8003b5c: f04f 0350 mov.w r3, #80 ; 0x50
8003b60: f383 8811 msr BASEPRI, r3
8003b64: f3bf 8f6f isb sy
8003b68: f3bf 8f4f dsb sy
8003b6c: 60fb str r3, [r7, #12]
}
8003b6e: bf00 nop
8003b70: e7fe b.n 8003b70 <vTaskStartScheduler+0xb4>
}
8003b72: bf00 nop
8003b74: 3718 adds r7, #24
8003b76: 46bd mov sp, r7
8003b78: bd80 pop {r7, pc}
8003b7a: bf00 nop
8003b7c: 08005640 .word 0x08005640
8003b80: 080041c1 .word 0x080041c1
8003b84: 20000db8 .word 0x20000db8
8003b88: 200008c0 .word 0x200008c0
8003b8c: 2000005c .word 0x2000005c
8003b90: 20000db4 .word 0x20000db4
8003b94: 20000da0 .word 0x20000da0
8003b98: 20000d98 .word 0x20000d98
08003b9c <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
8003b9c: b480 push {r7}
8003b9e: af00 add r7, sp, #0
do not otherwise exhibit real time behaviour. */
portSOFTWARE_BARRIER();
/* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
is used to allow calls to vTaskSuspendAll() to nest. */
++uxSchedulerSuspended;
8003ba0: 4b04 ldr r3, [pc, #16] ; (8003bb4 <vTaskSuspendAll+0x18>)
8003ba2: 681b ldr r3, [r3, #0]
8003ba4: 3301 adds r3, #1
8003ba6: 4a03 ldr r2, [pc, #12] ; (8003bb4 <vTaskSuspendAll+0x18>)
8003ba8: 6013 str r3, [r2, #0]
/* Enforces ordering for ports and optimised compilers that may otherwise place
the above increment elsewhere. */
portMEMORY_BARRIER();
}
8003baa: bf00 nop
8003bac: 46bd mov sp, r7
8003bae: f85d 7b04 ldr.w r7, [sp], #4
8003bb2: 4770 bx lr
8003bb4: 20000dbc .word 0x20000dbc
08003bb8 <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
8003bb8: b580 push {r7, lr}
8003bba: b084 sub sp, #16
8003bbc: af00 add r7, sp, #0
TCB_t *pxTCB = NULL;
8003bbe: 2300 movs r3, #0
8003bc0: 60fb str r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
8003bc2: 2300 movs r3, #0
8003bc4: 60bb str r3, [r7, #8]
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
8003bc6: 4b42 ldr r3, [pc, #264] ; (8003cd0 <xTaskResumeAll+0x118>)
8003bc8: 681b ldr r3, [r3, #0]
8003bca: 2b00 cmp r3, #0
8003bcc: d10a bne.n 8003be4 <xTaskResumeAll+0x2c>
__asm volatile
8003bce: f04f 0350 mov.w r3, #80 ; 0x50
8003bd2: f383 8811 msr BASEPRI, r3
8003bd6: f3bf 8f6f isb sy
8003bda: f3bf 8f4f dsb sy
8003bde: 603b str r3, [r7, #0]
}
8003be0: bf00 nop
8003be2: e7fe b.n 8003be2 <xTaskResumeAll+0x2a>
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
8003be4: f001 f91e bl 8004e24 <vPortEnterCritical>
{
--uxSchedulerSuspended;
8003be8: 4b39 ldr r3, [pc, #228] ; (8003cd0 <xTaskResumeAll+0x118>)
8003bea: 681b ldr r3, [r3, #0]
8003bec: 3b01 subs r3, #1
8003bee: 4a38 ldr r2, [pc, #224] ; (8003cd0 <xTaskResumeAll+0x118>)
8003bf0: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8003bf2: 4b37 ldr r3, [pc, #220] ; (8003cd0 <xTaskResumeAll+0x118>)
8003bf4: 681b ldr r3, [r3, #0]
8003bf6: 2b00 cmp r3, #0
8003bf8: d162 bne.n 8003cc0 <xTaskResumeAll+0x108>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
8003bfa: 4b36 ldr r3, [pc, #216] ; (8003cd4 <xTaskResumeAll+0x11c>)
8003bfc: 681b ldr r3, [r3, #0]
8003bfe: 2b00 cmp r3, #0
8003c00: d05e beq.n 8003cc0 <xTaskResumeAll+0x108>
{
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
8003c02: e02f b.n 8003c64 <xTaskResumeAll+0xac>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8003c04: 4b34 ldr r3, [pc, #208] ; (8003cd8 <xTaskResumeAll+0x120>)
8003c06: 68db ldr r3, [r3, #12]
8003c08: 68db ldr r3, [r3, #12]
8003c0a: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
8003c0c: 68fb ldr r3, [r7, #12]
8003c0e: 3318 adds r3, #24
8003c10: 4618 mov r0, r3
8003c12: f7ff f851 bl 8002cb8 <uxListRemove>
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8003c16: 68fb ldr r3, [r7, #12]
8003c18: 3304 adds r3, #4
8003c1a: 4618 mov r0, r3
8003c1c: f7ff f84c bl 8002cb8 <uxListRemove>
prvAddTaskToReadyList( pxTCB );
8003c20: 68fb ldr r3, [r7, #12]
8003c22: 6ada ldr r2, [r3, #44] ; 0x2c
8003c24: 4b2d ldr r3, [pc, #180] ; (8003cdc <xTaskResumeAll+0x124>)
8003c26: 681b ldr r3, [r3, #0]
8003c28: 429a cmp r2, r3
8003c2a: d903 bls.n 8003c34 <xTaskResumeAll+0x7c>
8003c2c: 68fb ldr r3, [r7, #12]
8003c2e: 6adb ldr r3, [r3, #44] ; 0x2c
8003c30: 4a2a ldr r2, [pc, #168] ; (8003cdc <xTaskResumeAll+0x124>)
8003c32: 6013 str r3, [r2, #0]
8003c34: 68fb ldr r3, [r7, #12]
8003c36: 6ada ldr r2, [r3, #44] ; 0x2c
8003c38: 4613 mov r3, r2
8003c3a: 009b lsls r3, r3, #2
8003c3c: 4413 add r3, r2
8003c3e: 009b lsls r3, r3, #2
8003c40: 4a27 ldr r2, [pc, #156] ; (8003ce0 <xTaskResumeAll+0x128>)
8003c42: 441a add r2, r3
8003c44: 68fb ldr r3, [r7, #12]
8003c46: 3304 adds r3, #4
8003c48: 4619 mov r1, r3
8003c4a: 4610 mov r0, r2
8003c4c: f7fe ffd7 bl 8002bfe <vListInsertEnd>
/* If the moved task has a priority higher than the current
task then a yield must be performed. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
8003c50: 68fb ldr r3, [r7, #12]
8003c52: 6ada ldr r2, [r3, #44] ; 0x2c
8003c54: 4b23 ldr r3, [pc, #140] ; (8003ce4 <xTaskResumeAll+0x12c>)
8003c56: 681b ldr r3, [r3, #0]
8003c58: 6adb ldr r3, [r3, #44] ; 0x2c
8003c5a: 429a cmp r2, r3
8003c5c: d302 bcc.n 8003c64 <xTaskResumeAll+0xac>
{
xYieldPending = pdTRUE;
8003c5e: 4b22 ldr r3, [pc, #136] ; (8003ce8 <xTaskResumeAll+0x130>)
8003c60: 2201 movs r2, #1
8003c62: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
8003c64: 4b1c ldr r3, [pc, #112] ; (8003cd8 <xTaskResumeAll+0x120>)
8003c66: 681b ldr r3, [r3, #0]
8003c68: 2b00 cmp r3, #0
8003c6a: d1cb bne.n 8003c04 <xTaskResumeAll+0x4c>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
8003c6c: 68fb ldr r3, [r7, #12]
8003c6e: 2b00 cmp r3, #0
8003c70: d001 beq.n 8003c76 <xTaskResumeAll+0xbe>
which may have prevented the next unblock time from being
re-calculated, in which case re-calculate it now. Mainly
important for low power tickless implementations, where
this can prevent an unnecessary exit from low power
state. */
prvResetNextTaskUnblockTime();
8003c72: f000 fb5f bl 8004334 <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does
not slip, and that any delayed tasks are resumed at the correct
time. */
{
TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
8003c76: 4b1d ldr r3, [pc, #116] ; (8003cec <xTaskResumeAll+0x134>)
8003c78: 681b ldr r3, [r3, #0]
8003c7a: 607b str r3, [r7, #4]
if( xPendedCounts > ( TickType_t ) 0U )
8003c7c: 687b ldr r3, [r7, #4]
8003c7e: 2b00 cmp r3, #0
8003c80: d010 beq.n 8003ca4 <xTaskResumeAll+0xec>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
8003c82: f000 f847 bl 8003d14 <xTaskIncrementTick>
8003c86: 4603 mov r3, r0
8003c88: 2b00 cmp r3, #0
8003c8a: d002 beq.n 8003c92 <xTaskResumeAll+0xda>
{
xYieldPending = pdTRUE;
8003c8c: 4b16 ldr r3, [pc, #88] ; (8003ce8 <xTaskResumeAll+0x130>)
8003c8e: 2201 movs r2, #1
8003c90: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--xPendedCounts;
8003c92: 687b ldr r3, [r7, #4]
8003c94: 3b01 subs r3, #1
8003c96: 607b str r3, [r7, #4]
} while( xPendedCounts > ( TickType_t ) 0U );
8003c98: 687b ldr r3, [r7, #4]
8003c9a: 2b00 cmp r3, #0
8003c9c: d1f1 bne.n 8003c82 <xTaskResumeAll+0xca>
xPendedTicks = 0;
8003c9e: 4b13 ldr r3, [pc, #76] ; (8003cec <xTaskResumeAll+0x134>)
8003ca0: 2200 movs r2, #0
8003ca2: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
8003ca4: 4b10 ldr r3, [pc, #64] ; (8003ce8 <xTaskResumeAll+0x130>)
8003ca6: 681b ldr r3, [r3, #0]
8003ca8: 2b00 cmp r3, #0
8003caa: d009 beq.n 8003cc0 <xTaskResumeAll+0x108>
{
#if( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
8003cac: 2301 movs r3, #1
8003cae: 60bb str r3, [r7, #8]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
8003cb0: 4b0f ldr r3, [pc, #60] ; (8003cf0 <xTaskResumeAll+0x138>)
8003cb2: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003cb6: 601a str r2, [r3, #0]
8003cb8: f3bf 8f4f dsb sy
8003cbc: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8003cc0: f001 f8e0 bl 8004e84 <vPortExitCritical>
return xAlreadyYielded;
8003cc4: 68bb ldr r3, [r7, #8]
}
8003cc6: 4618 mov r0, r3
8003cc8: 3710 adds r7, #16
8003cca: 46bd mov sp, r7
8003ccc: bd80 pop {r7, pc}
8003cce: bf00 nop
8003cd0: 20000dbc .word 0x20000dbc
8003cd4: 20000d94 .word 0x20000d94
8003cd8: 20000d54 .word 0x20000d54
8003cdc: 20000d9c .word 0x20000d9c
8003ce0: 200008c4 .word 0x200008c4
8003ce4: 200008c0 .word 0x200008c0
8003ce8: 20000da8 .word 0x20000da8
8003cec: 20000da4 .word 0x20000da4
8003cf0: e000ed04 .word 0xe000ed04
08003cf4 <xTaskGetTickCount>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCount( void )
{
8003cf4: b480 push {r7}
8003cf6: b083 sub sp, #12
8003cf8: af00 add r7, sp, #0
TickType_t xTicks;
/* Critical section required if running on a 16 bit processor. */
portTICK_TYPE_ENTER_CRITICAL();
{
xTicks = xTickCount;
8003cfa: 4b05 ldr r3, [pc, #20] ; (8003d10 <xTaskGetTickCount+0x1c>)
8003cfc: 681b ldr r3, [r3, #0]
8003cfe: 607b str r3, [r7, #4]
}
portTICK_TYPE_EXIT_CRITICAL();
return xTicks;
8003d00: 687b ldr r3, [r7, #4]
}
8003d02: 4618 mov r0, r3
8003d04: 370c adds r7, #12
8003d06: 46bd mov sp, r7
8003d08: f85d 7b04 ldr.w r7, [sp], #4
8003d0c: 4770 bx lr
8003d0e: bf00 nop
8003d10: 20000d98 .word 0x20000d98
08003d14 <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
8003d14: b580 push {r7, lr}
8003d16: b086 sub sp, #24
8003d18: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
8003d1a: 2300 movs r3, #0
8003d1c: 617b str r3, [r7, #20]
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8003d1e: 4b4f ldr r3, [pc, #316] ; (8003e5c <xTaskIncrementTick+0x148>)
8003d20: 681b ldr r3, [r3, #0]
8003d22: 2b00 cmp r3, #0
8003d24: f040 808f bne.w 8003e46 <xTaskIncrementTick+0x132>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
8003d28: 4b4d ldr r3, [pc, #308] ; (8003e60 <xTaskIncrementTick+0x14c>)
8003d2a: 681b ldr r3, [r3, #0]
8003d2c: 3301 adds r3, #1
8003d2e: 613b str r3, [r7, #16]
/* Increment the RTOS tick, switching the delayed and overflowed
delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
8003d30: 4a4b ldr r2, [pc, #300] ; (8003e60 <xTaskIncrementTick+0x14c>)
8003d32: 693b ldr r3, [r7, #16]
8003d34: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
8003d36: 693b ldr r3, [r7, #16]
8003d38: 2b00 cmp r3, #0
8003d3a: d120 bne.n 8003d7e <xTaskIncrementTick+0x6a>
{
taskSWITCH_DELAYED_LISTS();
8003d3c: 4b49 ldr r3, [pc, #292] ; (8003e64 <xTaskIncrementTick+0x150>)
8003d3e: 681b ldr r3, [r3, #0]
8003d40: 681b ldr r3, [r3, #0]
8003d42: 2b00 cmp r3, #0
8003d44: d00a beq.n 8003d5c <xTaskIncrementTick+0x48>
__asm volatile
8003d46: f04f 0350 mov.w r3, #80 ; 0x50
8003d4a: f383 8811 msr BASEPRI, r3
8003d4e: f3bf 8f6f isb sy
8003d52: f3bf 8f4f dsb sy
8003d56: 603b str r3, [r7, #0]
}
8003d58: bf00 nop
8003d5a: e7fe b.n 8003d5a <xTaskIncrementTick+0x46>
8003d5c: 4b41 ldr r3, [pc, #260] ; (8003e64 <xTaskIncrementTick+0x150>)
8003d5e: 681b ldr r3, [r3, #0]
8003d60: 60fb str r3, [r7, #12]
8003d62: 4b41 ldr r3, [pc, #260] ; (8003e68 <xTaskIncrementTick+0x154>)
8003d64: 681b ldr r3, [r3, #0]
8003d66: 4a3f ldr r2, [pc, #252] ; (8003e64 <xTaskIncrementTick+0x150>)
8003d68: 6013 str r3, [r2, #0]
8003d6a: 4a3f ldr r2, [pc, #252] ; (8003e68 <xTaskIncrementTick+0x154>)
8003d6c: 68fb ldr r3, [r7, #12]
8003d6e: 6013 str r3, [r2, #0]
8003d70: 4b3e ldr r3, [pc, #248] ; (8003e6c <xTaskIncrementTick+0x158>)
8003d72: 681b ldr r3, [r3, #0]
8003d74: 3301 adds r3, #1
8003d76: 4a3d ldr r2, [pc, #244] ; (8003e6c <xTaskIncrementTick+0x158>)
8003d78: 6013 str r3, [r2, #0]
8003d7a: f000 fadb bl 8004334 <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
the queue in the order of their wake time - meaning once one task
has been found whose block time has not expired there is no need to
look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
8003d7e: 4b3c ldr r3, [pc, #240] ; (8003e70 <xTaskIncrementTick+0x15c>)
8003d80: 681b ldr r3, [r3, #0]
8003d82: 693a ldr r2, [r7, #16]
8003d84: 429a cmp r2, r3
8003d86: d349 bcc.n 8003e1c <xTaskIncrementTick+0x108>
{
for( ;; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8003d88: 4b36 ldr r3, [pc, #216] ; (8003e64 <xTaskIncrementTick+0x150>)
8003d8a: 681b ldr r3, [r3, #0]
8003d8c: 681b ldr r3, [r3, #0]
8003d8e: 2b00 cmp r3, #0
8003d90: d104 bne.n 8003d9c <xTaskIncrementTick+0x88>
/* The delayed list is empty. Set xNextTaskUnblockTime
to the maximum possible value so it is extremely
unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass
next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8003d92: 4b37 ldr r3, [pc, #220] ; (8003e70 <xTaskIncrementTick+0x15c>)
8003d94: f04f 32ff mov.w r2, #4294967295
8003d98: 601a str r2, [r3, #0]
break;
8003d9a: e03f b.n 8003e1c <xTaskIncrementTick+0x108>
{
/* The delayed list is not empty, get the value of the
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8003d9c: 4b31 ldr r3, [pc, #196] ; (8003e64 <xTaskIncrementTick+0x150>)
8003d9e: 681b ldr r3, [r3, #0]
8003da0: 68db ldr r3, [r3, #12]
8003da2: 68db ldr r3, [r3, #12]
8003da4: 60bb str r3, [r7, #8]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
8003da6: 68bb ldr r3, [r7, #8]
8003da8: 685b ldr r3, [r3, #4]
8003daa: 607b str r3, [r7, #4]
if( xConstTickCount < xItemValue )
8003dac: 693a ldr r2, [r7, #16]
8003dae: 687b ldr r3, [r7, #4]
8003db0: 429a cmp r2, r3
8003db2: d203 bcs.n 8003dbc <xTaskIncrementTick+0xa8>
/* It is not time to unblock this item yet, but the
item value is the time at which the task at the head
of the blocked list must be removed from the Blocked
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
8003db4: 4a2e ldr r2, [pc, #184] ; (8003e70 <xTaskIncrementTick+0x15c>)
8003db6: 687b ldr r3, [r7, #4]
8003db8: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
8003dba: e02f b.n 8003e1c <xTaskIncrementTick+0x108>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8003dbc: 68bb ldr r3, [r7, #8]
8003dbe: 3304 adds r3, #4
8003dc0: 4618 mov r0, r3
8003dc2: f7fe ff79 bl 8002cb8 <uxListRemove>
/* Is the task waiting on an event also? If so remove
it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
8003dc6: 68bb ldr r3, [r7, #8]
8003dc8: 6a9b ldr r3, [r3, #40] ; 0x28
8003dca: 2b00 cmp r3, #0
8003dcc: d004 beq.n 8003dd8 <xTaskIncrementTick+0xc4>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
8003dce: 68bb ldr r3, [r7, #8]
8003dd0: 3318 adds r3, #24
8003dd2: 4618 mov r0, r3
8003dd4: f7fe ff70 bl 8002cb8 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
list. */
prvAddTaskToReadyList( pxTCB );
8003dd8: 68bb ldr r3, [r7, #8]
8003dda: 6ada ldr r2, [r3, #44] ; 0x2c
8003ddc: 4b25 ldr r3, [pc, #148] ; (8003e74 <xTaskIncrementTick+0x160>)
8003dde: 681b ldr r3, [r3, #0]
8003de0: 429a cmp r2, r3
8003de2: d903 bls.n 8003dec <xTaskIncrementTick+0xd8>
8003de4: 68bb ldr r3, [r7, #8]
8003de6: 6adb ldr r3, [r3, #44] ; 0x2c
8003de8: 4a22 ldr r2, [pc, #136] ; (8003e74 <xTaskIncrementTick+0x160>)
8003dea: 6013 str r3, [r2, #0]
8003dec: 68bb ldr r3, [r7, #8]
8003dee: 6ada ldr r2, [r3, #44] ; 0x2c
8003df0: 4613 mov r3, r2
8003df2: 009b lsls r3, r3, #2
8003df4: 4413 add r3, r2
8003df6: 009b lsls r3, r3, #2
8003df8: 4a1f ldr r2, [pc, #124] ; (8003e78 <xTaskIncrementTick+0x164>)
8003dfa: 441a add r2, r3
8003dfc: 68bb ldr r3, [r7, #8]
8003dfe: 3304 adds r3, #4
8003e00: 4619 mov r1, r3
8003e02: 4610 mov r0, r2
8003e04: f7fe fefb bl 8002bfe <vListInsertEnd>
{
/* Preemption is on, but a context switch should
only be performed if the unblocked task has a
priority that is equal to or higher than the
currently executing task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
8003e08: 68bb ldr r3, [r7, #8]
8003e0a: 6ada ldr r2, [r3, #44] ; 0x2c
8003e0c: 4b1b ldr r3, [pc, #108] ; (8003e7c <xTaskIncrementTick+0x168>)
8003e0e: 681b ldr r3, [r3, #0]
8003e10: 6adb ldr r3, [r3, #44] ; 0x2c
8003e12: 429a cmp r2, r3
8003e14: d3b8 bcc.n 8003d88 <xTaskIncrementTick+0x74>
{
xSwitchRequired = pdTRUE;
8003e16: 2301 movs r3, #1
8003e18: 617b str r3, [r7, #20]
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8003e1a: e7b5 b.n 8003d88 <xTaskIncrementTick+0x74>
/* Tasks of equal priority to the currently running task will share
processing time (time slice) if preemption is on, and the application
writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
8003e1c: 4b17 ldr r3, [pc, #92] ; (8003e7c <xTaskIncrementTick+0x168>)
8003e1e: 681b ldr r3, [r3, #0]
8003e20: 6ada ldr r2, [r3, #44] ; 0x2c
8003e22: 4915 ldr r1, [pc, #84] ; (8003e78 <xTaskIncrementTick+0x164>)
8003e24: 4613 mov r3, r2
8003e26: 009b lsls r3, r3, #2
8003e28: 4413 add r3, r2
8003e2a: 009b lsls r3, r3, #2
8003e2c: 440b add r3, r1
8003e2e: 681b ldr r3, [r3, #0]
8003e30: 2b01 cmp r3, #1
8003e32: d901 bls.n 8003e38 <xTaskIncrementTick+0x124>
{
xSwitchRequired = pdTRUE;
8003e34: 2301 movs r3, #1
8003e36: 617b str r3, [r7, #20]
}
#endif /* configUSE_TICK_HOOK */
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
8003e38: 4b11 ldr r3, [pc, #68] ; (8003e80 <xTaskIncrementTick+0x16c>)
8003e3a: 681b ldr r3, [r3, #0]
8003e3c: 2b00 cmp r3, #0
8003e3e: d007 beq.n 8003e50 <xTaskIncrementTick+0x13c>
{
xSwitchRequired = pdTRUE;
8003e40: 2301 movs r3, #1
8003e42: 617b str r3, [r7, #20]
8003e44: e004 b.n 8003e50 <xTaskIncrementTick+0x13c>
}
#endif /* configUSE_PREEMPTION */
}
else
{
++xPendedTicks;
8003e46: 4b0f ldr r3, [pc, #60] ; (8003e84 <xTaskIncrementTick+0x170>)
8003e48: 681b ldr r3, [r3, #0]
8003e4a: 3301 adds r3, #1
8003e4c: 4a0d ldr r2, [pc, #52] ; (8003e84 <xTaskIncrementTick+0x170>)
8003e4e: 6013 str r3, [r2, #0]
vApplicationTickHook();
}
#endif
}
return xSwitchRequired;
8003e50: 697b ldr r3, [r7, #20]
}
8003e52: 4618 mov r0, r3
8003e54: 3718 adds r7, #24
8003e56: 46bd mov sp, r7
8003e58: bd80 pop {r7, pc}
8003e5a: bf00 nop
8003e5c: 20000dbc .word 0x20000dbc
8003e60: 20000d98 .word 0x20000d98
8003e64: 20000d4c .word 0x20000d4c
8003e68: 20000d50 .word 0x20000d50
8003e6c: 20000dac .word 0x20000dac
8003e70: 20000db4 .word 0x20000db4
8003e74: 20000d9c .word 0x20000d9c
8003e78: 200008c4 .word 0x200008c4
8003e7c: 200008c0 .word 0x200008c0
8003e80: 20000da8 .word 0x20000da8
8003e84: 20000da4 .word 0x20000da4
08003e88 <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
8003e88: b480 push {r7}
8003e8a: b085 sub sp, #20
8003e8c: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
8003e8e: 4b2a ldr r3, [pc, #168] ; (8003f38 <vTaskSwitchContext+0xb0>)
8003e90: 681b ldr r3, [r3, #0]
8003e92: 2b00 cmp r3, #0
8003e94: d003 beq.n 8003e9e <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xYieldPending = pdTRUE;
8003e96: 4b29 ldr r3, [pc, #164] ; (8003f3c <vTaskSwitchContext+0xb4>)
8003e98: 2201 movs r2, #1
8003e9a: 601a str r2, [r3, #0]
for additional information. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
}
8003e9c: e046 b.n 8003f2c <vTaskSwitchContext+0xa4>
xYieldPending = pdFALSE;
8003e9e: 4b27 ldr r3, [pc, #156] ; (8003f3c <vTaskSwitchContext+0xb4>)
8003ea0: 2200 movs r2, #0
8003ea2: 601a str r2, [r3, #0]
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8003ea4: 4b26 ldr r3, [pc, #152] ; (8003f40 <vTaskSwitchContext+0xb8>)
8003ea6: 681b ldr r3, [r3, #0]
8003ea8: 60fb str r3, [r7, #12]
8003eaa: e010 b.n 8003ece <vTaskSwitchContext+0x46>
8003eac: 68fb ldr r3, [r7, #12]
8003eae: 2b00 cmp r3, #0
8003eb0: d10a bne.n 8003ec8 <vTaskSwitchContext+0x40>
__asm volatile
8003eb2: f04f 0350 mov.w r3, #80 ; 0x50
8003eb6: f383 8811 msr BASEPRI, r3
8003eba: f3bf 8f6f isb sy
8003ebe: f3bf 8f4f dsb sy
8003ec2: 607b str r3, [r7, #4]
}
8003ec4: bf00 nop
8003ec6: e7fe b.n 8003ec6 <vTaskSwitchContext+0x3e>
8003ec8: 68fb ldr r3, [r7, #12]
8003eca: 3b01 subs r3, #1
8003ecc: 60fb str r3, [r7, #12]
8003ece: 491d ldr r1, [pc, #116] ; (8003f44 <vTaskSwitchContext+0xbc>)
8003ed0: 68fa ldr r2, [r7, #12]
8003ed2: 4613 mov r3, r2
8003ed4: 009b lsls r3, r3, #2
8003ed6: 4413 add r3, r2
8003ed8: 009b lsls r3, r3, #2
8003eda: 440b add r3, r1
8003edc: 681b ldr r3, [r3, #0]
8003ede: 2b00 cmp r3, #0
8003ee0: d0e4 beq.n 8003eac <vTaskSwitchContext+0x24>
8003ee2: 68fa ldr r2, [r7, #12]
8003ee4: 4613 mov r3, r2
8003ee6: 009b lsls r3, r3, #2
8003ee8: 4413 add r3, r2
8003eea: 009b lsls r3, r3, #2
8003eec: 4a15 ldr r2, [pc, #84] ; (8003f44 <vTaskSwitchContext+0xbc>)
8003eee: 4413 add r3, r2
8003ef0: 60bb str r3, [r7, #8]
8003ef2: 68bb ldr r3, [r7, #8]
8003ef4: 685b ldr r3, [r3, #4]
8003ef6: 685a ldr r2, [r3, #4]
8003ef8: 68bb ldr r3, [r7, #8]
8003efa: 605a str r2, [r3, #4]
8003efc: 68bb ldr r3, [r7, #8]
8003efe: 685a ldr r2, [r3, #4]
8003f00: 68bb ldr r3, [r7, #8]
8003f02: 3308 adds r3, #8
8003f04: 429a cmp r2, r3
8003f06: d104 bne.n 8003f12 <vTaskSwitchContext+0x8a>
8003f08: 68bb ldr r3, [r7, #8]
8003f0a: 685b ldr r3, [r3, #4]
8003f0c: 685a ldr r2, [r3, #4]
8003f0e: 68bb ldr r3, [r7, #8]
8003f10: 605a str r2, [r3, #4]
8003f12: 68bb ldr r3, [r7, #8]
8003f14: 685b ldr r3, [r3, #4]
8003f16: 68db ldr r3, [r3, #12]
8003f18: 4a0b ldr r2, [pc, #44] ; (8003f48 <vTaskSwitchContext+0xc0>)
8003f1a: 6013 str r3, [r2, #0]
8003f1c: 4a08 ldr r2, [pc, #32] ; (8003f40 <vTaskSwitchContext+0xb8>)
8003f1e: 68fb ldr r3, [r7, #12]
8003f20: 6013 str r3, [r2, #0]
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
8003f22: 4b09 ldr r3, [pc, #36] ; (8003f48 <vTaskSwitchContext+0xc0>)
8003f24: 681b ldr r3, [r3, #0]
8003f26: 3354 adds r3, #84 ; 0x54
8003f28: 4a08 ldr r2, [pc, #32] ; (8003f4c <vTaskSwitchContext+0xc4>)
8003f2a: 6013 str r3, [r2, #0]
}
8003f2c: bf00 nop
8003f2e: 3714 adds r7, #20
8003f30: 46bd mov sp, r7
8003f32: f85d 7b04 ldr.w r7, [sp], #4
8003f36: 4770 bx lr
8003f38: 20000dbc .word 0x20000dbc
8003f3c: 20000da8 .word 0x20000da8
8003f40: 20000d9c .word 0x20000d9c
8003f44: 200008c4 .word 0x200008c4
8003f48: 200008c0 .word 0x200008c0
8003f4c: 2000005c .word 0x2000005c
08003f50 <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
8003f50: b580 push {r7, lr}
8003f52: b084 sub sp, #16
8003f54: af00 add r7, sp, #0
8003f56: 6078 str r0, [r7, #4]
8003f58: 6039 str r1, [r7, #0]
configASSERT( pxEventList );
8003f5a: 687b ldr r3, [r7, #4]
8003f5c: 2b00 cmp r3, #0
8003f5e: d10a bne.n 8003f76 <vTaskPlaceOnEventList+0x26>
__asm volatile
8003f60: f04f 0350 mov.w r3, #80 ; 0x50
8003f64: f383 8811 msr BASEPRI, r3
8003f68: f3bf 8f6f isb sy
8003f6c: f3bf 8f4f dsb sy
8003f70: 60fb str r3, [r7, #12]
}
8003f72: bf00 nop
8003f74: e7fe b.n 8003f74 <vTaskPlaceOnEventList+0x24>
/* Place the event list item of the TCB in the appropriate event list.
This is placed in the list in priority order so the highest priority task
is the first to be woken by the event. The queue that contains the event
list is locked, preventing simultaneous access from interrupts. */
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
8003f76: 4b07 ldr r3, [pc, #28] ; (8003f94 <vTaskPlaceOnEventList+0x44>)
8003f78: 681b ldr r3, [r3, #0]
8003f7a: 3318 adds r3, #24
8003f7c: 4619 mov r1, r3
8003f7e: 6878 ldr r0, [r7, #4]
8003f80: f7fe fe61 bl 8002c46 <vListInsert>
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
8003f84: 2101 movs r1, #1
8003f86: 6838 ldr r0, [r7, #0]
8003f88: f000 fa80 bl 800448c <prvAddCurrentTaskToDelayedList>
}
8003f8c: bf00 nop
8003f8e: 3710 adds r7, #16
8003f90: 46bd mov sp, r7
8003f92: bd80 pop {r7, pc}
8003f94: 200008c0 .word 0x200008c0
08003f98 <vTaskPlaceOnEventListRestricted>:
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
{
8003f98: b580 push {r7, lr}
8003f9a: b086 sub sp, #24
8003f9c: af00 add r7, sp, #0
8003f9e: 60f8 str r0, [r7, #12]
8003fa0: 60b9 str r1, [r7, #8]
8003fa2: 607a str r2, [r7, #4]
configASSERT( pxEventList );
8003fa4: 68fb ldr r3, [r7, #12]
8003fa6: 2b00 cmp r3, #0
8003fa8: d10a bne.n 8003fc0 <vTaskPlaceOnEventListRestricted+0x28>
__asm volatile
8003faa: f04f 0350 mov.w r3, #80 ; 0x50
8003fae: f383 8811 msr BASEPRI, r3
8003fb2: f3bf 8f6f isb sy
8003fb6: f3bf 8f4f dsb sy
8003fba: 617b str r3, [r7, #20]
}
8003fbc: bf00 nop
8003fbe: e7fe b.n 8003fbe <vTaskPlaceOnEventListRestricted+0x26>
/* Place the event list item of the TCB in the appropriate event list.
In this case it is assume that this is the only task that is going to
be waiting on this event list, so the faster vListInsertEnd() function
can be used in place of vListInsert. */
vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
8003fc0: 4b0a ldr r3, [pc, #40] ; (8003fec <vTaskPlaceOnEventListRestricted+0x54>)
8003fc2: 681b ldr r3, [r3, #0]
8003fc4: 3318 adds r3, #24
8003fc6: 4619 mov r1, r3
8003fc8: 68f8 ldr r0, [r7, #12]
8003fca: f7fe fe18 bl 8002bfe <vListInsertEnd>
/* If the task should block indefinitely then set the block time to a
value that will be recognised as an indefinite delay inside the
prvAddCurrentTaskToDelayedList() function. */
if( xWaitIndefinitely != pdFALSE )
8003fce: 687b ldr r3, [r7, #4]
8003fd0: 2b00 cmp r3, #0
8003fd2: d002 beq.n 8003fda <vTaskPlaceOnEventListRestricted+0x42>
{
xTicksToWait = portMAX_DELAY;
8003fd4: f04f 33ff mov.w r3, #4294967295
8003fd8: 60bb str r3, [r7, #8]
}
traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
8003fda: 6879 ldr r1, [r7, #4]
8003fdc: 68b8 ldr r0, [r7, #8]
8003fde: f000 fa55 bl 800448c <prvAddCurrentTaskToDelayedList>
}
8003fe2: bf00 nop
8003fe4: 3718 adds r7, #24
8003fe6: 46bd mov sp, r7
8003fe8: bd80 pop {r7, pc}
8003fea: bf00 nop
8003fec: 200008c0 .word 0x200008c0
08003ff0 <xTaskRemoveFromEventList>:
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
8003ff0: b580 push {r7, lr}
8003ff2: b086 sub sp, #24
8003ff4: af00 add r7, sp, #0
8003ff6: 6078 str r0, [r7, #4]
get called - the lock count on the queue will get modified instead. This
means exclusive access to the event list is guaranteed here.
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8003ff8: 687b ldr r3, [r7, #4]
8003ffa: 68db ldr r3, [r3, #12]
8003ffc: 68db ldr r3, [r3, #12]
8003ffe: 613b str r3, [r7, #16]
configASSERT( pxUnblockedTCB );
8004000: 693b ldr r3, [r7, #16]
8004002: 2b00 cmp r3, #0
8004004: d10a bne.n 800401c <xTaskRemoveFromEventList+0x2c>
__asm volatile
8004006: f04f 0350 mov.w r3, #80 ; 0x50
800400a: f383 8811 msr BASEPRI, r3
800400e: f3bf 8f6f isb sy
8004012: f3bf 8f4f dsb sy
8004016: 60fb str r3, [r7, #12]
}
8004018: bf00 nop
800401a: e7fe b.n 800401a <xTaskRemoveFromEventList+0x2a>
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
800401c: 693b ldr r3, [r7, #16]
800401e: 3318 adds r3, #24
8004020: 4618 mov r0, r3
8004022: f7fe fe49 bl 8002cb8 <uxListRemove>
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8004026: 4b1e ldr r3, [pc, #120] ; (80040a0 <xTaskRemoveFromEventList+0xb0>)
8004028: 681b ldr r3, [r3, #0]
800402a: 2b00 cmp r3, #0
800402c: d11d bne.n 800406a <xTaskRemoveFromEventList+0x7a>
{
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
800402e: 693b ldr r3, [r7, #16]
8004030: 3304 adds r3, #4
8004032: 4618 mov r0, r3
8004034: f7fe fe40 bl 8002cb8 <uxListRemove>
prvAddTaskToReadyList( pxUnblockedTCB );
8004038: 693b ldr r3, [r7, #16]
800403a: 6ada ldr r2, [r3, #44] ; 0x2c
800403c: 4b19 ldr r3, [pc, #100] ; (80040a4 <xTaskRemoveFromEventList+0xb4>)
800403e: 681b ldr r3, [r3, #0]
8004040: 429a cmp r2, r3
8004042: d903 bls.n 800404c <xTaskRemoveFromEventList+0x5c>
8004044: 693b ldr r3, [r7, #16]
8004046: 6adb ldr r3, [r3, #44] ; 0x2c
8004048: 4a16 ldr r2, [pc, #88] ; (80040a4 <xTaskRemoveFromEventList+0xb4>)
800404a: 6013 str r3, [r2, #0]
800404c: 693b ldr r3, [r7, #16]
800404e: 6ada ldr r2, [r3, #44] ; 0x2c
8004050: 4613 mov r3, r2
8004052: 009b lsls r3, r3, #2
8004054: 4413 add r3, r2
8004056: 009b lsls r3, r3, #2
8004058: 4a13 ldr r2, [pc, #76] ; (80040a8 <xTaskRemoveFromEventList+0xb8>)
800405a: 441a add r2, r3
800405c: 693b ldr r3, [r7, #16]
800405e: 3304 adds r3, #4
8004060: 4619 mov r1, r3
8004062: 4610 mov r0, r2
8004064: f7fe fdcb bl 8002bfe <vListInsertEnd>
8004068: e005 b.n 8004076 <xTaskRemoveFromEventList+0x86>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold this task
pending until the scheduler is resumed. */
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
800406a: 693b ldr r3, [r7, #16]
800406c: 3318 adds r3, #24
800406e: 4619 mov r1, r3
8004070: 480e ldr r0, [pc, #56] ; (80040ac <xTaskRemoveFromEventList+0xbc>)
8004072: f7fe fdc4 bl 8002bfe <vListInsertEnd>
}
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
8004076: 693b ldr r3, [r7, #16]
8004078: 6ada ldr r2, [r3, #44] ; 0x2c
800407a: 4b0d ldr r3, [pc, #52] ; (80040b0 <xTaskRemoveFromEventList+0xc0>)
800407c: 681b ldr r3, [r3, #0]
800407e: 6adb ldr r3, [r3, #44] ; 0x2c
8004080: 429a cmp r2, r3
8004082: d905 bls.n 8004090 <xTaskRemoveFromEventList+0xa0>
{
/* Return true if the task removed from the event list has a higher
priority than the calling task. This allows the calling task to know if
it should force a context switch now. */
xReturn = pdTRUE;
8004084: 2301 movs r3, #1
8004086: 617b str r3, [r7, #20]
/* Mark that a yield is pending in case the user is not using the
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
xYieldPending = pdTRUE;
8004088: 4b0a ldr r3, [pc, #40] ; (80040b4 <xTaskRemoveFromEventList+0xc4>)
800408a: 2201 movs r2, #1
800408c: 601a str r2, [r3, #0]
800408e: e001 b.n 8004094 <xTaskRemoveFromEventList+0xa4>
}
else
{
xReturn = pdFALSE;
8004090: 2300 movs r3, #0
8004092: 617b str r3, [r7, #20]
}
return xReturn;
8004094: 697b ldr r3, [r7, #20]
}
8004096: 4618 mov r0, r3
8004098: 3718 adds r7, #24
800409a: 46bd mov sp, r7
800409c: bd80 pop {r7, pc}
800409e: bf00 nop
80040a0: 20000dbc .word 0x20000dbc
80040a4: 20000d9c .word 0x20000d9c
80040a8: 200008c4 .word 0x200008c4
80040ac: 20000d54 .word 0x20000d54
80040b0: 200008c0 .word 0x200008c0
80040b4: 20000da8 .word 0x20000da8
080040b8 <vTaskInternalSetTimeOutState>:
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
80040b8: b480 push {r7}
80040ba: b083 sub sp, #12
80040bc: af00 add r7, sp, #0
80040be: 6078 str r0, [r7, #4]
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
80040c0: 4b06 ldr r3, [pc, #24] ; (80040dc <vTaskInternalSetTimeOutState+0x24>)
80040c2: 681a ldr r2, [r3, #0]
80040c4: 687b ldr r3, [r7, #4]
80040c6: 601a str r2, [r3, #0]
pxTimeOut->xTimeOnEntering = xTickCount;
80040c8: 4b05 ldr r3, [pc, #20] ; (80040e0 <vTaskInternalSetTimeOutState+0x28>)
80040ca: 681a ldr r2, [r3, #0]
80040cc: 687b ldr r3, [r7, #4]
80040ce: 605a str r2, [r3, #4]
}
80040d0: bf00 nop
80040d2: 370c adds r7, #12
80040d4: 46bd mov sp, r7
80040d6: f85d 7b04 ldr.w r7, [sp], #4
80040da: 4770 bx lr
80040dc: 20000dac .word 0x20000dac
80040e0: 20000d98 .word 0x20000d98
080040e4 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
80040e4: b580 push {r7, lr}
80040e6: b088 sub sp, #32
80040e8: af00 add r7, sp, #0
80040ea: 6078 str r0, [r7, #4]
80040ec: 6039 str r1, [r7, #0]
BaseType_t xReturn;
configASSERT( pxTimeOut );
80040ee: 687b ldr r3, [r7, #4]
80040f0: 2b00 cmp r3, #0
80040f2: d10a bne.n 800410a <xTaskCheckForTimeOut+0x26>
__asm volatile
80040f4: f04f 0350 mov.w r3, #80 ; 0x50
80040f8: f383 8811 msr BASEPRI, r3
80040fc: f3bf 8f6f isb sy
8004100: f3bf 8f4f dsb sy
8004104: 613b str r3, [r7, #16]
}
8004106: bf00 nop
8004108: e7fe b.n 8004108 <xTaskCheckForTimeOut+0x24>
configASSERT( pxTicksToWait );
800410a: 683b ldr r3, [r7, #0]
800410c: 2b00 cmp r3, #0
800410e: d10a bne.n 8004126 <xTaskCheckForTimeOut+0x42>
__asm volatile
8004110: f04f 0350 mov.w r3, #80 ; 0x50
8004114: f383 8811 msr BASEPRI, r3
8004118: f3bf 8f6f isb sy
800411c: f3bf 8f4f dsb sy
8004120: 60fb str r3, [r7, #12]
}
8004122: bf00 nop
8004124: e7fe b.n 8004124 <xTaskCheckForTimeOut+0x40>
taskENTER_CRITICAL();
8004126: f000 fe7d bl 8004e24 <vPortEnterCritical>
{
/* Minor optimisation. The tick count cannot change in this block. */
const TickType_t xConstTickCount = xTickCount;
800412a: 4b1d ldr r3, [pc, #116] ; (80041a0 <xTaskCheckForTimeOut+0xbc>)
800412c: 681b ldr r3, [r3, #0]
800412e: 61bb str r3, [r7, #24]
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
8004130: 687b ldr r3, [r7, #4]
8004132: 685b ldr r3, [r3, #4]
8004134: 69ba ldr r2, [r7, #24]
8004136: 1ad3 subs r3, r2, r3
8004138: 617b str r3, [r7, #20]
}
else
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
if( *pxTicksToWait == portMAX_DELAY )
800413a: 683b ldr r3, [r7, #0]
800413c: 681b ldr r3, [r3, #0]
800413e: f1b3 3fff cmp.w r3, #4294967295
8004142: d102 bne.n 800414a <xTaskCheckForTimeOut+0x66>
{
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
specified is the maximum block time then the task should block
indefinitely, and therefore never time out. */
xReturn = pdFALSE;
8004144: 2300 movs r3, #0
8004146: 61fb str r3, [r7, #28]
8004148: e023 b.n 8004192 <xTaskCheckForTimeOut+0xae>
}
else
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
800414a: 687b ldr r3, [r7, #4]
800414c: 681a ldr r2, [r3, #0]
800414e: 4b15 ldr r3, [pc, #84] ; (80041a4 <xTaskCheckForTimeOut+0xc0>)
8004150: 681b ldr r3, [r3, #0]
8004152: 429a cmp r2, r3
8004154: d007 beq.n 8004166 <xTaskCheckForTimeOut+0x82>
8004156: 687b ldr r3, [r7, #4]
8004158: 685b ldr r3, [r3, #4]
800415a: 69ba ldr r2, [r7, #24]
800415c: 429a cmp r2, r3
800415e: d302 bcc.n 8004166 <xTaskCheckForTimeOut+0x82>
/* The tick count is greater than the time at which
vTaskSetTimeout() was called, but has also overflowed since
vTaskSetTimeOut() was called. It must have wrapped all the way
around and gone past again. This passed since vTaskSetTimeout()
was called. */
xReturn = pdTRUE;
8004160: 2301 movs r3, #1
8004162: 61fb str r3, [r7, #28]
8004164: e015 b.n 8004192 <xTaskCheckForTimeOut+0xae>
}
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
8004166: 683b ldr r3, [r7, #0]
8004168: 681b ldr r3, [r3, #0]
800416a: 697a ldr r2, [r7, #20]
800416c: 429a cmp r2, r3
800416e: d20b bcs.n 8004188 <xTaskCheckForTimeOut+0xa4>
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
8004170: 683b ldr r3, [r7, #0]
8004172: 681a ldr r2, [r3, #0]
8004174: 697b ldr r3, [r7, #20]
8004176: 1ad2 subs r2, r2, r3
8004178: 683b ldr r3, [r7, #0]
800417a: 601a str r2, [r3, #0]
vTaskInternalSetTimeOutState( pxTimeOut );
800417c: 6878 ldr r0, [r7, #4]
800417e: f7ff ff9b bl 80040b8 <vTaskInternalSetTimeOutState>
xReturn = pdFALSE;
8004182: 2300 movs r3, #0
8004184: 61fb str r3, [r7, #28]
8004186: e004 b.n 8004192 <xTaskCheckForTimeOut+0xae>
}
else
{
*pxTicksToWait = 0;
8004188: 683b ldr r3, [r7, #0]
800418a: 2200 movs r2, #0
800418c: 601a str r2, [r3, #0]
xReturn = pdTRUE;
800418e: 2301 movs r3, #1
8004190: 61fb str r3, [r7, #28]
}
}
taskEXIT_CRITICAL();
8004192: f000 fe77 bl 8004e84 <vPortExitCritical>
return xReturn;
8004196: 69fb ldr r3, [r7, #28]
}
8004198: 4618 mov r0, r3
800419a: 3720 adds r7, #32
800419c: 46bd mov sp, r7
800419e: bd80 pop {r7, pc}
80041a0: 20000d98 .word 0x20000d98
80041a4: 20000dac .word 0x20000dac
080041a8 <vTaskMissedYield>:
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
80041a8: b480 push {r7}
80041aa: af00 add r7, sp, #0
xYieldPending = pdTRUE;
80041ac: 4b03 ldr r3, [pc, #12] ; (80041bc <vTaskMissedYield+0x14>)
80041ae: 2201 movs r2, #1
80041b0: 601a str r2, [r3, #0]
}
80041b2: bf00 nop
80041b4: 46bd mov sp, r7
80041b6: f85d 7b04 ldr.w r7, [sp], #4
80041ba: 4770 bx lr
80041bc: 20000da8 .word 0x20000da8
080041c0 <prvIdleTask>:
*
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
80041c0: b580 push {r7, lr}
80041c2: b082 sub sp, #8
80041c4: af00 add r7, sp, #0
80041c6: 6078 str r0, [r7, #4]
for( ;; )
{
/* See if any tasks have deleted themselves - if so then the idle task
is responsible for freeing the deleted task's TCB and stack. */
prvCheckTasksWaitingTermination();
80041c8: f000 f852 bl 8004270 <prvCheckTasksWaitingTermination>
A critical region is not required here as we are just reading from
the list, and an occasional incorrect value will not matter. If
the ready list at the idle priority contains more than one task
then a task other than the idle task is ready to execute. */
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
80041cc: 4b06 ldr r3, [pc, #24] ; (80041e8 <prvIdleTask+0x28>)
80041ce: 681b ldr r3, [r3, #0]
80041d0: 2b01 cmp r3, #1
80041d2: d9f9 bls.n 80041c8 <prvIdleTask+0x8>
{
taskYIELD();
80041d4: 4b05 ldr r3, [pc, #20] ; (80041ec <prvIdleTask+0x2c>)
80041d6: f04f 5280 mov.w r2, #268435456 ; 0x10000000
80041da: 601a str r2, [r3, #0]
80041dc: f3bf 8f4f dsb sy
80041e0: f3bf 8f6f isb sy
prvCheckTasksWaitingTermination();
80041e4: e7f0 b.n 80041c8 <prvIdleTask+0x8>
80041e6: bf00 nop
80041e8: 200008c4 .word 0x200008c4
80041ec: e000ed04 .word 0xe000ed04
080041f0 <prvInitialiseTaskLists>:
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
static void prvInitialiseTaskLists( void )
{
80041f0: b580 push {r7, lr}
80041f2: b082 sub sp, #8
80041f4: af00 add r7, sp, #0
UBaseType_t uxPriority;
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
80041f6: 2300 movs r3, #0
80041f8: 607b str r3, [r7, #4]
80041fa: e00c b.n 8004216 <prvInitialiseTaskLists+0x26>
{
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
80041fc: 687a ldr r2, [r7, #4]
80041fe: 4613 mov r3, r2
8004200: 009b lsls r3, r3, #2
8004202: 4413 add r3, r2
8004204: 009b lsls r3, r3, #2
8004206: 4a12 ldr r2, [pc, #72] ; (8004250 <prvInitialiseTaskLists+0x60>)
8004208: 4413 add r3, r2
800420a: 4618 mov r0, r3
800420c: f7fe fcca bl 8002ba4 <vListInitialise>
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
8004210: 687b ldr r3, [r7, #4]
8004212: 3301 adds r3, #1
8004214: 607b str r3, [r7, #4]
8004216: 687b ldr r3, [r7, #4]
8004218: 2b37 cmp r3, #55 ; 0x37
800421a: d9ef bls.n 80041fc <prvInitialiseTaskLists+0xc>
}
vListInitialise( &xDelayedTaskList1 );
800421c: 480d ldr r0, [pc, #52] ; (8004254 <prvInitialiseTaskLists+0x64>)
800421e: f7fe fcc1 bl 8002ba4 <vListInitialise>
vListInitialise( &xDelayedTaskList2 );
8004222: 480d ldr r0, [pc, #52] ; (8004258 <prvInitialiseTaskLists+0x68>)
8004224: f7fe fcbe bl 8002ba4 <vListInitialise>
vListInitialise( &xPendingReadyList );
8004228: 480c ldr r0, [pc, #48] ; (800425c <prvInitialiseTaskLists+0x6c>)
800422a: f7fe fcbb bl 8002ba4 <vListInitialise>
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( &xTasksWaitingTermination );
800422e: 480c ldr r0, [pc, #48] ; (8004260 <prvInitialiseTaskLists+0x70>)
8004230: f7fe fcb8 bl 8002ba4 <vListInitialise>
}
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( &xSuspendedTaskList );
8004234: 480b ldr r0, [pc, #44] ; (8004264 <prvInitialiseTaskLists+0x74>)
8004236: f7fe fcb5 bl 8002ba4 <vListInitialise>
}
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
800423a: 4b0b ldr r3, [pc, #44] ; (8004268 <prvInitialiseTaskLists+0x78>)
800423c: 4a05 ldr r2, [pc, #20] ; (8004254 <prvInitialiseTaskLists+0x64>)
800423e: 601a str r2, [r3, #0]
pxOverflowDelayedTaskList = &xDelayedTaskList2;
8004240: 4b0a ldr r3, [pc, #40] ; (800426c <prvInitialiseTaskLists+0x7c>)
8004242: 4a05 ldr r2, [pc, #20] ; (8004258 <prvInitialiseTaskLists+0x68>)
8004244: 601a str r2, [r3, #0]
}
8004246: bf00 nop
8004248: 3708 adds r7, #8
800424a: 46bd mov sp, r7
800424c: bd80 pop {r7, pc}
800424e: bf00 nop
8004250: 200008c4 .word 0x200008c4
8004254: 20000d24 .word 0x20000d24
8004258: 20000d38 .word 0x20000d38
800425c: 20000d54 .word 0x20000d54
8004260: 20000d68 .word 0x20000d68
8004264: 20000d80 .word 0x20000d80
8004268: 20000d4c .word 0x20000d4c
800426c: 20000d50 .word 0x20000d50
08004270 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/
static void prvCheckTasksWaitingTermination( void )
{
8004270: b580 push {r7, lr}
8004272: b082 sub sp, #8
8004274: af00 add r7, sp, #0
{
TCB_t *pxTCB;
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
8004276: e019 b.n 80042ac <prvCheckTasksWaitingTermination+0x3c>
{
taskENTER_CRITICAL();
8004278: f000 fdd4 bl 8004e24 <vPortEnterCritical>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800427c: 4b10 ldr r3, [pc, #64] ; (80042c0 <prvCheckTasksWaitingTermination+0x50>)
800427e: 68db ldr r3, [r3, #12]
8004280: 68db ldr r3, [r3, #12]
8004282: 607b str r3, [r7, #4]
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8004284: 687b ldr r3, [r7, #4]
8004286: 3304 adds r3, #4
8004288: 4618 mov r0, r3
800428a: f7fe fd15 bl 8002cb8 <uxListRemove>
--uxCurrentNumberOfTasks;
800428e: 4b0d ldr r3, [pc, #52] ; (80042c4 <prvCheckTasksWaitingTermination+0x54>)
8004290: 681b ldr r3, [r3, #0]
8004292: 3b01 subs r3, #1
8004294: 4a0b ldr r2, [pc, #44] ; (80042c4 <prvCheckTasksWaitingTermination+0x54>)
8004296: 6013 str r3, [r2, #0]
--uxDeletedTasksWaitingCleanUp;
8004298: 4b0b ldr r3, [pc, #44] ; (80042c8 <prvCheckTasksWaitingTermination+0x58>)
800429a: 681b ldr r3, [r3, #0]
800429c: 3b01 subs r3, #1
800429e: 4a0a ldr r2, [pc, #40] ; (80042c8 <prvCheckTasksWaitingTermination+0x58>)
80042a0: 6013 str r3, [r2, #0]
}
taskEXIT_CRITICAL();
80042a2: f000 fdef bl 8004e84 <vPortExitCritical>
prvDeleteTCB( pxTCB );
80042a6: 6878 ldr r0, [r7, #4]
80042a8: f000 f810 bl 80042cc <prvDeleteTCB>
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
80042ac: 4b06 ldr r3, [pc, #24] ; (80042c8 <prvCheckTasksWaitingTermination+0x58>)
80042ae: 681b ldr r3, [r3, #0]
80042b0: 2b00 cmp r3, #0
80042b2: d1e1 bne.n 8004278 <prvCheckTasksWaitingTermination+0x8>
}
}
#endif /* INCLUDE_vTaskDelete */
}
80042b4: bf00 nop
80042b6: bf00 nop
80042b8: 3708 adds r7, #8
80042ba: 46bd mov sp, r7
80042bc: bd80 pop {r7, pc}
80042be: bf00 nop
80042c0: 20000d68 .word 0x20000d68
80042c4: 20000d94 .word 0x20000d94
80042c8: 20000d7c .word 0x20000d7c
080042cc <prvDeleteTCB>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( TCB_t *pxTCB )
{
80042cc: b580 push {r7, lr}
80042ce: b084 sub sp, #16
80042d0: af00 add r7, sp, #0
80042d2: 6078 str r0, [r7, #4]
to the task to free any memory allocated at the application level.
See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
for additional information. */
#if ( configUSE_NEWLIB_REENTRANT == 1 )
{
_reclaim_reent( &( pxTCB->xNewLib_reent ) );
80042d4: 687b ldr r3, [r7, #4]
80042d6: 3354 adds r3, #84 ; 0x54
80042d8: 4618 mov r0, r3
80042da: f001 f8b7 bl 800544c <_reclaim_reent>
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* The task could have been allocated statically or dynamically, so
check what was statically allocated before trying to free the
memory. */
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
80042de: 687b ldr r3, [r7, #4]
80042e0: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5
80042e4: 2b00 cmp r3, #0
80042e6: d108 bne.n 80042fa <prvDeleteTCB+0x2e>
{
/* Both the stack and TCB were allocated dynamically, so both
must be freed. */
vPortFree( pxTCB->pxStack );
80042e8: 687b ldr r3, [r7, #4]
80042ea: 6b1b ldr r3, [r3, #48] ; 0x30
80042ec: 4618 mov r0, r3
80042ee: f000 ff87 bl 8005200 <vPortFree>
vPortFree( pxTCB );
80042f2: 6878 ldr r0, [r7, #4]
80042f4: f000 ff84 bl 8005200 <vPortFree>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
80042f8: e018 b.n 800432c <prvDeleteTCB+0x60>
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
80042fa: 687b ldr r3, [r7, #4]
80042fc: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5
8004300: 2b01 cmp r3, #1
8004302: d103 bne.n 800430c <prvDeleteTCB+0x40>
vPortFree( pxTCB );
8004304: 6878 ldr r0, [r7, #4]
8004306: f000 ff7b bl 8005200 <vPortFree>
}
800430a: e00f b.n 800432c <prvDeleteTCB+0x60>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
800430c: 687b ldr r3, [r7, #4]
800430e: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5
8004312: 2b02 cmp r3, #2
8004314: d00a beq.n 800432c <prvDeleteTCB+0x60>
__asm volatile
8004316: f04f 0350 mov.w r3, #80 ; 0x50
800431a: f383 8811 msr BASEPRI, r3
800431e: f3bf 8f6f isb sy
8004322: f3bf 8f4f dsb sy
8004326: 60fb str r3, [r7, #12]
}
8004328: bf00 nop
800432a: e7fe b.n 800432a <prvDeleteTCB+0x5e>
}
800432c: bf00 nop
800432e: 3710 adds r7, #16
8004330: 46bd mov sp, r7
8004332: bd80 pop {r7, pc}
08004334 <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
8004334: b480 push {r7}
8004336: b083 sub sp, #12
8004338: af00 add r7, sp, #0
TCB_t *pxTCB;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
800433a: 4b0c ldr r3, [pc, #48] ; (800436c <prvResetNextTaskUnblockTime+0x38>)
800433c: 681b ldr r3, [r3, #0]
800433e: 681b ldr r3, [r3, #0]
8004340: 2b00 cmp r3, #0
8004342: d104 bne.n 800434e <prvResetNextTaskUnblockTime+0x1a>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
the maximum possible value so it is extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
8004344: 4b0a ldr r3, [pc, #40] ; (8004370 <prvResetNextTaskUnblockTime+0x3c>)
8004346: f04f 32ff mov.w r2, #4294967295
800434a: 601a str r2, [r3, #0]
which the task at the head of the delayed list should be removed
from the Blocked state. */
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
800434c: e008 b.n 8004360 <prvResetNextTaskUnblockTime+0x2c>
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800434e: 4b07 ldr r3, [pc, #28] ; (800436c <prvResetNextTaskUnblockTime+0x38>)
8004350: 681b ldr r3, [r3, #0]
8004352: 68db ldr r3, [r3, #12]
8004354: 68db ldr r3, [r3, #12]
8004356: 607b str r3, [r7, #4]
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
8004358: 687b ldr r3, [r7, #4]
800435a: 685b ldr r3, [r3, #4]
800435c: 4a04 ldr r2, [pc, #16] ; (8004370 <prvResetNextTaskUnblockTime+0x3c>)
800435e: 6013 str r3, [r2, #0]
}
8004360: bf00 nop
8004362: 370c adds r7, #12
8004364: 46bd mov sp, r7
8004366: f85d 7b04 ldr.w r7, [sp], #4
800436a: 4770 bx lr
800436c: 20000d4c .word 0x20000d4c
8004370: 20000db4 .word 0x20000db4
08004374 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
BaseType_t xTaskGetSchedulerState( void )
{
8004374: b480 push {r7}
8004376: b083 sub sp, #12
8004378: af00 add r7, sp, #0
BaseType_t xReturn;
if( xSchedulerRunning == pdFALSE )
800437a: 4b0b ldr r3, [pc, #44] ; (80043a8 <xTaskGetSchedulerState+0x34>)
800437c: 681b ldr r3, [r3, #0]
800437e: 2b00 cmp r3, #0
8004380: d102 bne.n 8004388 <xTaskGetSchedulerState+0x14>
{
xReturn = taskSCHEDULER_NOT_STARTED;
8004382: 2301 movs r3, #1
8004384: 607b str r3, [r7, #4]
8004386: e008 b.n 800439a <xTaskGetSchedulerState+0x26>
}
else
{
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8004388: 4b08 ldr r3, [pc, #32] ; (80043ac <xTaskGetSchedulerState+0x38>)
800438a: 681b ldr r3, [r3, #0]
800438c: 2b00 cmp r3, #0
800438e: d102 bne.n 8004396 <xTaskGetSchedulerState+0x22>
{
xReturn = taskSCHEDULER_RUNNING;
8004390: 2302 movs r3, #2
8004392: 607b str r3, [r7, #4]
8004394: e001 b.n 800439a <xTaskGetSchedulerState+0x26>
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
8004396: 2300 movs r3, #0
8004398: 607b str r3, [r7, #4]
}
}
return xReturn;
800439a: 687b ldr r3, [r7, #4]
}
800439c: 4618 mov r0, r3
800439e: 370c adds r7, #12
80043a0: 46bd mov sp, r7
80043a2: f85d 7b04 ldr.w r7, [sp], #4
80043a6: 4770 bx lr
80043a8: 20000da0 .word 0x20000da0
80043ac: 20000dbc .word 0x20000dbc
080043b0 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
80043b0: b580 push {r7, lr}
80043b2: b086 sub sp, #24
80043b4: af00 add r7, sp, #0
80043b6: 6078 str r0, [r7, #4]
TCB_t * const pxTCB = pxMutexHolder;
80043b8: 687b ldr r3, [r7, #4]
80043ba: 613b str r3, [r7, #16]
BaseType_t xReturn = pdFALSE;
80043bc: 2300 movs r3, #0
80043be: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
80043c0: 687b ldr r3, [r7, #4]
80043c2: 2b00 cmp r3, #0
80043c4: d056 beq.n 8004474 <xTaskPriorityDisinherit+0xc4>
{
/* A task can only have an inherited priority if it holds the mutex.
If the mutex is held by a task then it cannot be given from an
interrupt, and if a mutex is given by the holding task then it must
be the running state task. */
configASSERT( pxTCB == pxCurrentTCB );
80043c6: 4b2e ldr r3, [pc, #184] ; (8004480 <xTaskPriorityDisinherit+0xd0>)
80043c8: 681b ldr r3, [r3, #0]
80043ca: 693a ldr r2, [r7, #16]
80043cc: 429a cmp r2, r3
80043ce: d00a beq.n 80043e6 <xTaskPriorityDisinherit+0x36>
__asm volatile
80043d0: f04f 0350 mov.w r3, #80 ; 0x50
80043d4: f383 8811 msr BASEPRI, r3
80043d8: f3bf 8f6f isb sy
80043dc: f3bf 8f4f dsb sy
80043e0: 60fb str r3, [r7, #12]
}
80043e2: bf00 nop
80043e4: e7fe b.n 80043e4 <xTaskPriorityDisinherit+0x34>
configASSERT( pxTCB->uxMutexesHeld );
80043e6: 693b ldr r3, [r7, #16]
80043e8: 6d1b ldr r3, [r3, #80] ; 0x50
80043ea: 2b00 cmp r3, #0
80043ec: d10a bne.n 8004404 <xTaskPriorityDisinherit+0x54>
__asm volatile
80043ee: f04f 0350 mov.w r3, #80 ; 0x50
80043f2: f383 8811 msr BASEPRI, r3
80043f6: f3bf 8f6f isb sy
80043fa: f3bf 8f4f dsb sy
80043fe: 60bb str r3, [r7, #8]
}
8004400: bf00 nop
8004402: e7fe b.n 8004402 <xTaskPriorityDisinherit+0x52>
( pxTCB->uxMutexesHeld )--;
8004404: 693b ldr r3, [r7, #16]
8004406: 6d1b ldr r3, [r3, #80] ; 0x50
8004408: 1e5a subs r2, r3, #1
800440a: 693b ldr r3, [r7, #16]
800440c: 651a str r2, [r3, #80] ; 0x50
/* Has the holder of the mutex inherited the priority of another
task? */
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
800440e: 693b ldr r3, [r7, #16]
8004410: 6ada ldr r2, [r3, #44] ; 0x2c
8004412: 693b ldr r3, [r7, #16]
8004414: 6cdb ldr r3, [r3, #76] ; 0x4c
8004416: 429a cmp r2, r3
8004418: d02c beq.n 8004474 <xTaskPriorityDisinherit+0xc4>
{
/* Only disinherit if no other mutexes are held. */
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
800441a: 693b ldr r3, [r7, #16]
800441c: 6d1b ldr r3, [r3, #80] ; 0x50
800441e: 2b00 cmp r3, #0
8004420: d128 bne.n 8004474 <xTaskPriorityDisinherit+0xc4>
/* A task can only have an inherited priority if it holds
the mutex. If the mutex is held by a task then it cannot be
given from an interrupt, and if a mutex is given by the
holding task then it must be the running state task. Remove
the holding task from the ready/delayed list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
8004422: 693b ldr r3, [r7, #16]
8004424: 3304 adds r3, #4
8004426: 4618 mov r0, r3
8004428: f7fe fc46 bl 8002cb8 <uxListRemove>
}
/* Disinherit the priority before adding the task into the
new ready list. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
pxTCB->uxPriority = pxTCB->uxBasePriority;
800442c: 693b ldr r3, [r7, #16]
800442e: 6cda ldr r2, [r3, #76] ; 0x4c
8004430: 693b ldr r3, [r7, #16]
8004432: 62da str r2, [r3, #44] ; 0x2c
/* Reset the event list item value. It cannot be in use for
any other purpose if this task is running, and it must be
running to give back the mutex. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8004434: 693b ldr r3, [r7, #16]
8004436: 6adb ldr r3, [r3, #44] ; 0x2c
8004438: f1c3 0238 rsb r2, r3, #56 ; 0x38
800443c: 693b ldr r3, [r7, #16]
800443e: 619a str r2, [r3, #24]
prvAddTaskToReadyList( pxTCB );
8004440: 693b ldr r3, [r7, #16]
8004442: 6ada ldr r2, [r3, #44] ; 0x2c
8004444: 4b0f ldr r3, [pc, #60] ; (8004484 <xTaskPriorityDisinherit+0xd4>)
8004446: 681b ldr r3, [r3, #0]
8004448: 429a cmp r2, r3
800444a: d903 bls.n 8004454 <xTaskPriorityDisinherit+0xa4>
800444c: 693b ldr r3, [r7, #16]
800444e: 6adb ldr r3, [r3, #44] ; 0x2c
8004450: 4a0c ldr r2, [pc, #48] ; (8004484 <xTaskPriorityDisinherit+0xd4>)
8004452: 6013 str r3, [r2, #0]
8004454: 693b ldr r3, [r7, #16]
8004456: 6ada ldr r2, [r3, #44] ; 0x2c
8004458: 4613 mov r3, r2
800445a: 009b lsls r3, r3, #2
800445c: 4413 add r3, r2
800445e: 009b lsls r3, r3, #2
8004460: 4a09 ldr r2, [pc, #36] ; (8004488 <xTaskPriorityDisinherit+0xd8>)
8004462: 441a add r2, r3
8004464: 693b ldr r3, [r7, #16]
8004466: 3304 adds r3, #4
8004468: 4619 mov r1, r3
800446a: 4610 mov r0, r2
800446c: f7fe fbc7 bl 8002bfe <vListInsertEnd>
in an order different to that in which they were taken.
If a context switch did not occur when the first mutex was
returned, even if a task was waiting on it, then a context
switch should occur when the last mutex is returned whether
a task is waiting on it or not. */
xReturn = pdTRUE;
8004470: 2301 movs r3, #1
8004472: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
8004474: 697b ldr r3, [r7, #20]
}
8004476: 4618 mov r0, r3
8004478: 3718 adds r7, #24
800447a: 46bd mov sp, r7
800447c: bd80 pop {r7, pc}
800447e: bf00 nop
8004480: 200008c0 .word 0x200008c0
8004484: 20000d9c .word 0x20000d9c
8004488: 200008c4 .word 0x200008c4
0800448c <prvAddCurrentTaskToDelayedList>:
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
800448c: b580 push {r7, lr}
800448e: b084 sub sp, #16
8004490: af00 add r7, sp, #0
8004492: 6078 str r0, [r7, #4]
8004494: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
8004496: 4b21 ldr r3, [pc, #132] ; (800451c <prvAddCurrentTaskToDelayedList+0x90>)
8004498: 681b ldr r3, [r3, #0]
800449a: 60fb str r3, [r7, #12]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800449c: 4b20 ldr r3, [pc, #128] ; (8004520 <prvAddCurrentTaskToDelayedList+0x94>)
800449e: 681b ldr r3, [r3, #0]
80044a0: 3304 adds r3, #4
80044a2: 4618 mov r0, r3
80044a4: f7fe fc08 bl 8002cb8 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
80044a8: 687b ldr r3, [r7, #4]
80044aa: f1b3 3fff cmp.w r3, #4294967295
80044ae: d10a bne.n 80044c6 <prvAddCurrentTaskToDelayedList+0x3a>
80044b0: 683b ldr r3, [r7, #0]
80044b2: 2b00 cmp r3, #0
80044b4: d007 beq.n 80044c6 <prvAddCurrentTaskToDelayedList+0x3a>
{
/* Add the task to the suspended task list instead of a delayed task
list to ensure it is not woken by a timing event. It will block
indefinitely. */
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
80044b6: 4b1a ldr r3, [pc, #104] ; (8004520 <prvAddCurrentTaskToDelayedList+0x94>)
80044b8: 681b ldr r3, [r3, #0]
80044ba: 3304 adds r3, #4
80044bc: 4619 mov r1, r3
80044be: 4819 ldr r0, [pc, #100] ; (8004524 <prvAddCurrentTaskToDelayedList+0x98>)
80044c0: f7fe fb9d bl 8002bfe <vListInsertEnd>
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
80044c4: e026 b.n 8004514 <prvAddCurrentTaskToDelayedList+0x88>
xTimeToWake = xConstTickCount + xTicksToWait;
80044c6: 68fa ldr r2, [r7, #12]
80044c8: 687b ldr r3, [r7, #4]
80044ca: 4413 add r3, r2
80044cc: 60bb str r3, [r7, #8]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
80044ce: 4b14 ldr r3, [pc, #80] ; (8004520 <prvAddCurrentTaskToDelayedList+0x94>)
80044d0: 681b ldr r3, [r3, #0]
80044d2: 68ba ldr r2, [r7, #8]
80044d4: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
80044d6: 68ba ldr r2, [r7, #8]
80044d8: 68fb ldr r3, [r7, #12]
80044da: 429a cmp r2, r3
80044dc: d209 bcs.n 80044f2 <prvAddCurrentTaskToDelayedList+0x66>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
80044de: 4b12 ldr r3, [pc, #72] ; (8004528 <prvAddCurrentTaskToDelayedList+0x9c>)
80044e0: 681a ldr r2, [r3, #0]
80044e2: 4b0f ldr r3, [pc, #60] ; (8004520 <prvAddCurrentTaskToDelayedList+0x94>)
80044e4: 681b ldr r3, [r3, #0]
80044e6: 3304 adds r3, #4
80044e8: 4619 mov r1, r3
80044ea: 4610 mov r0, r2
80044ec: f7fe fbab bl 8002c46 <vListInsert>
}
80044f0: e010 b.n 8004514 <prvAddCurrentTaskToDelayedList+0x88>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
80044f2: 4b0e ldr r3, [pc, #56] ; (800452c <prvAddCurrentTaskToDelayedList+0xa0>)
80044f4: 681a ldr r2, [r3, #0]
80044f6: 4b0a ldr r3, [pc, #40] ; (8004520 <prvAddCurrentTaskToDelayedList+0x94>)
80044f8: 681b ldr r3, [r3, #0]
80044fa: 3304 adds r3, #4
80044fc: 4619 mov r1, r3
80044fe: 4610 mov r0, r2
8004500: f7fe fba1 bl 8002c46 <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
8004504: 4b0a ldr r3, [pc, #40] ; (8004530 <prvAddCurrentTaskToDelayedList+0xa4>)
8004506: 681b ldr r3, [r3, #0]
8004508: 68ba ldr r2, [r7, #8]
800450a: 429a cmp r2, r3
800450c: d202 bcs.n 8004514 <prvAddCurrentTaskToDelayedList+0x88>
xNextTaskUnblockTime = xTimeToWake;
800450e: 4a08 ldr r2, [pc, #32] ; (8004530 <prvAddCurrentTaskToDelayedList+0xa4>)
8004510: 68bb ldr r3, [r7, #8]
8004512: 6013 str r3, [r2, #0]
}
8004514: bf00 nop
8004516: 3710 adds r7, #16
8004518: 46bd mov sp, r7
800451a: bd80 pop {r7, pc}
800451c: 20000d98 .word 0x20000d98
8004520: 200008c0 .word 0x200008c0
8004524: 20000d80 .word 0x20000d80
8004528: 20000d50 .word 0x20000d50
800452c: 20000d4c .word 0x20000d4c
8004530: 20000db4 .word 0x20000db4
08004534 <xTimerCreateTimerTask>:
TimerCallbackFunction_t pxCallbackFunction,
Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
BaseType_t xTimerCreateTimerTask( void )
{
8004534: b580 push {r7, lr}
8004536: b08a sub sp, #40 ; 0x28
8004538: af04 add r7, sp, #16
BaseType_t xReturn = pdFAIL;
800453a: 2300 movs r3, #0
800453c: 617b str r3, [r7, #20]
/* This function is called when the scheduler is started if
configUSE_TIMERS is set to 1. Check that the infrastructure used by the
timer service task has been created/initialised. If timers have already
been created then the initialisation will already have been performed. */
prvCheckForValidListAndQueue();
800453e: f000 fb07 bl 8004b50 <prvCheckForValidListAndQueue>
if( xTimerQueue != NULL )
8004542: 4b1c ldr r3, [pc, #112] ; (80045b4 <xTimerCreateTimerTask+0x80>)
8004544: 681b ldr r3, [r3, #0]
8004546: 2b00 cmp r3, #0
8004548: d021 beq.n 800458e <xTimerCreateTimerTask+0x5a>
{
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxTimerTaskTCBBuffer = NULL;
800454a: 2300 movs r3, #0
800454c: 60fb str r3, [r7, #12]
StackType_t *pxTimerTaskStackBuffer = NULL;
800454e: 2300 movs r3, #0
8004550: 60bb str r3, [r7, #8]
uint32_t ulTimerTaskStackSize;
vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
8004552: 1d3a adds r2, r7, #4
8004554: f107 0108 add.w r1, r7, #8
8004558: f107 030c add.w r3, r7, #12
800455c: 4618 mov r0, r3
800455e: f7fe fb07 bl 8002b70 <vApplicationGetTimerTaskMemory>
xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
8004562: 6879 ldr r1, [r7, #4]
8004564: 68bb ldr r3, [r7, #8]
8004566: 68fa ldr r2, [r7, #12]
8004568: 9202 str r2, [sp, #8]
800456a: 9301 str r3, [sp, #4]
800456c: 2302 movs r3, #2
800456e: 9300 str r3, [sp, #0]
8004570: 2300 movs r3, #0
8004572: 460a mov r2, r1
8004574: 4910 ldr r1, [pc, #64] ; (80045b8 <xTimerCreateTimerTask+0x84>)
8004576: 4811 ldr r0, [pc, #68] ; (80045bc <xTimerCreateTimerTask+0x88>)
8004578: f7ff f8b4 bl 80036e4 <xTaskCreateStatic>
800457c: 4603 mov r3, r0
800457e: 4a10 ldr r2, [pc, #64] ; (80045c0 <xTimerCreateTimerTask+0x8c>)
8004580: 6013 str r3, [r2, #0]
NULL,
( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
pxTimerTaskStackBuffer,
pxTimerTaskTCBBuffer );
if( xTimerTaskHandle != NULL )
8004582: 4b0f ldr r3, [pc, #60] ; (80045c0 <xTimerCreateTimerTask+0x8c>)
8004584: 681b ldr r3, [r3, #0]
8004586: 2b00 cmp r3, #0
8004588: d001 beq.n 800458e <xTimerCreateTimerTask+0x5a>
{
xReturn = pdPASS;
800458a: 2301 movs r3, #1
800458c: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
configASSERT( xReturn );
800458e: 697b ldr r3, [r7, #20]
8004590: 2b00 cmp r3, #0
8004592: d10a bne.n 80045aa <xTimerCreateTimerTask+0x76>
__asm volatile
8004594: f04f 0350 mov.w r3, #80 ; 0x50
8004598: f383 8811 msr BASEPRI, r3
800459c: f3bf 8f6f isb sy
80045a0: f3bf 8f4f dsb sy
80045a4: 613b str r3, [r7, #16]
}
80045a6: bf00 nop
80045a8: e7fe b.n 80045a8 <xTimerCreateTimerTask+0x74>
return xReturn;
80045aa: 697b ldr r3, [r7, #20]
}
80045ac: 4618 mov r0, r3
80045ae: 3718 adds r7, #24
80045b0: 46bd mov sp, r7
80045b2: bd80 pop {r7, pc}
80045b4: 20000df0 .word 0x20000df0
80045b8: 08005648 .word 0x08005648
80045bc: 080046f9 .word 0x080046f9
80045c0: 20000df4 .word 0x20000df4
080045c4 <xTimerGenericCommand>:
}
}
/*-----------------------------------------------------------*/
BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
{
80045c4: b580 push {r7, lr}
80045c6: b08a sub sp, #40 ; 0x28
80045c8: af00 add r7, sp, #0
80045ca: 60f8 str r0, [r7, #12]
80045cc: 60b9 str r1, [r7, #8]
80045ce: 607a str r2, [r7, #4]
80045d0: 603b str r3, [r7, #0]
BaseType_t xReturn = pdFAIL;
80045d2: 2300 movs r3, #0
80045d4: 627b str r3, [r7, #36] ; 0x24
DaemonTaskMessage_t xMessage;
configASSERT( xTimer );
80045d6: 68fb ldr r3, [r7, #12]
80045d8: 2b00 cmp r3, #0
80045da: d10a bne.n 80045f2 <xTimerGenericCommand+0x2e>
__asm volatile
80045dc: f04f 0350 mov.w r3, #80 ; 0x50
80045e0: f383 8811 msr BASEPRI, r3
80045e4: f3bf 8f6f isb sy
80045e8: f3bf 8f4f dsb sy
80045ec: 623b str r3, [r7, #32]
}
80045ee: bf00 nop
80045f0: e7fe b.n 80045f0 <xTimerGenericCommand+0x2c>
/* Send a message to the timer service task to perform a particular action
on a particular timer definition. */
if( xTimerQueue != NULL )
80045f2: 4b1a ldr r3, [pc, #104] ; (800465c <xTimerGenericCommand+0x98>)
80045f4: 681b ldr r3, [r3, #0]
80045f6: 2b00 cmp r3, #0
80045f8: d02a beq.n 8004650 <xTimerGenericCommand+0x8c>
{
/* Send a command to the timer service task to start the xTimer timer. */
xMessage.xMessageID = xCommandID;
80045fa: 68bb ldr r3, [r7, #8]
80045fc: 613b str r3, [r7, #16]
xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
80045fe: 687b ldr r3, [r7, #4]
8004600: 617b str r3, [r7, #20]
xMessage.u.xTimerParameters.pxTimer = xTimer;
8004602: 68fb ldr r3, [r7, #12]
8004604: 61bb str r3, [r7, #24]
if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
8004606: 68bb ldr r3, [r7, #8]
8004608: 2b05 cmp r3, #5
800460a: dc18 bgt.n 800463e <xTimerGenericCommand+0x7a>
{
if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
800460c: f7ff feb2 bl 8004374 <xTaskGetSchedulerState>
8004610: 4603 mov r3, r0
8004612: 2b02 cmp r3, #2
8004614: d109 bne.n 800462a <xTimerGenericCommand+0x66>
{
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
8004616: 4b11 ldr r3, [pc, #68] ; (800465c <xTimerGenericCommand+0x98>)
8004618: 6818 ldr r0, [r3, #0]
800461a: f107 0110 add.w r1, r7, #16
800461e: 2300 movs r3, #0
8004620: 6b3a ldr r2, [r7, #48] ; 0x30
8004622: f7fe fc77 bl 8002f14 <xQueueGenericSend>
8004626: 6278 str r0, [r7, #36] ; 0x24
8004628: e012 b.n 8004650 <xTimerGenericCommand+0x8c>
}
else
{
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
800462a: 4b0c ldr r3, [pc, #48] ; (800465c <xTimerGenericCommand+0x98>)
800462c: 6818 ldr r0, [r3, #0]
800462e: f107 0110 add.w r1, r7, #16
8004632: 2300 movs r3, #0
8004634: 2200 movs r2, #0
8004636: f7fe fc6d bl 8002f14 <xQueueGenericSend>
800463a: 6278 str r0, [r7, #36] ; 0x24
800463c: e008 b.n 8004650 <xTimerGenericCommand+0x8c>
}
}
else
{
xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
800463e: 4b07 ldr r3, [pc, #28] ; (800465c <xTimerGenericCommand+0x98>)
8004640: 6818 ldr r0, [r3, #0]
8004642: f107 0110 add.w r1, r7, #16
8004646: 2300 movs r3, #0
8004648: 683a ldr r2, [r7, #0]
800464a: f7fe fd61 bl 8003110 <xQueueGenericSendFromISR>
800464e: 6278 str r0, [r7, #36] ; 0x24
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
8004650: 6a7b ldr r3, [r7, #36] ; 0x24
}
8004652: 4618 mov r0, r3
8004654: 3728 adds r7, #40 ; 0x28
8004656: 46bd mov sp, r7
8004658: bd80 pop {r7, pc}
800465a: bf00 nop
800465c: 20000df0 .word 0x20000df0
08004660 <prvProcessExpiredTimer>:
return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/
static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
8004660: b580 push {r7, lr}
8004662: b088 sub sp, #32
8004664: af02 add r7, sp, #8
8004666: 6078 str r0, [r7, #4]
8004668: 6039 str r1, [r7, #0]
BaseType_t xResult;
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800466a: 4b22 ldr r3, [pc, #136] ; (80046f4 <prvProcessExpiredTimer+0x94>)
800466c: 681b ldr r3, [r3, #0]
800466e: 68db ldr r3, [r3, #12]
8004670: 68db ldr r3, [r3, #12]
8004672: 617b str r3, [r7, #20]
/* Remove the timer from the list of active timers. A check has already
been performed to ensure the list is not empty. */
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8004674: 697b ldr r3, [r7, #20]
8004676: 3304 adds r3, #4
8004678: 4618 mov r0, r3
800467a: f7fe fb1d bl 8002cb8 <uxListRemove>
traceTIMER_EXPIRED( pxTimer );
/* If the timer is an auto-reload timer then calculate the next
expiry time and re-insert the timer in the list of active timers. */
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
800467e: 697b ldr r3, [r7, #20]
8004680: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
8004684: f003 0304 and.w r3, r3, #4
8004688: 2b00 cmp r3, #0
800468a: d022 beq.n 80046d2 <prvProcessExpiredTimer+0x72>
{
/* The timer is inserted into a list using a time relative to anything
other than the current time. It will therefore be inserted into the
correct list relative to the time this task thinks it is now. */
if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
800468c: 697b ldr r3, [r7, #20]
800468e: 699a ldr r2, [r3, #24]
8004690: 687b ldr r3, [r7, #4]
8004692: 18d1 adds r1, r2, r3
8004694: 687b ldr r3, [r7, #4]
8004696: 683a ldr r2, [r7, #0]
8004698: 6978 ldr r0, [r7, #20]
800469a: f000 f8d1 bl 8004840 <prvInsertTimerInActiveList>
800469e: 4603 mov r3, r0
80046a0: 2b00 cmp r3, #0
80046a2: d01f beq.n 80046e4 <prvProcessExpiredTimer+0x84>
{
/* The timer expired before it was added to the active timer
list. Reload it now. */
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
80046a4: 2300 movs r3, #0
80046a6: 9300 str r3, [sp, #0]
80046a8: 2300 movs r3, #0
80046aa: 687a ldr r2, [r7, #4]
80046ac: 2100 movs r1, #0
80046ae: 6978 ldr r0, [r7, #20]
80046b0: f7ff ff88 bl 80045c4 <xTimerGenericCommand>
80046b4: 6138 str r0, [r7, #16]
configASSERT( xResult );
80046b6: 693b ldr r3, [r7, #16]
80046b8: 2b00 cmp r3, #0
80046ba: d113 bne.n 80046e4 <prvProcessExpiredTimer+0x84>
__asm volatile
80046bc: f04f 0350 mov.w r3, #80 ; 0x50
80046c0: f383 8811 msr BASEPRI, r3
80046c4: f3bf 8f6f isb sy
80046c8: f3bf 8f4f dsb sy
80046cc: 60fb str r3, [r7, #12]
}
80046ce: bf00 nop
80046d0: e7fe b.n 80046d0 <prvProcessExpiredTimer+0x70>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
80046d2: 697b ldr r3, [r7, #20]
80046d4: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
80046d8: f023 0301 bic.w r3, r3, #1
80046dc: b2da uxtb r2, r3
80046de: 697b ldr r3, [r7, #20]
80046e0: f883 2028 strb.w r2, [r3, #40] ; 0x28
mtCOVERAGE_TEST_MARKER();
}
/* Call the timer callback. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
80046e4: 697b ldr r3, [r7, #20]
80046e6: 6a1b ldr r3, [r3, #32]
80046e8: 6978 ldr r0, [r7, #20]
80046ea: 4798 blx r3
}
80046ec: bf00 nop
80046ee: 3718 adds r7, #24
80046f0: 46bd mov sp, r7
80046f2: bd80 pop {r7, pc}
80046f4: 20000de8 .word 0x20000de8
080046f8 <prvTimerTask>:
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
80046f8: b580 push {r7, lr}
80046fa: b084 sub sp, #16
80046fc: af00 add r7, sp, #0
80046fe: 6078 str r0, [r7, #4]
for( ;; )
{
/* Query the timers list to see if it contains any timers, and if so,
obtain the time at which the next timer will expire. */
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
8004700: f107 0308 add.w r3, r7, #8
8004704: 4618 mov r0, r3
8004706: f000 f857 bl 80047b8 <prvGetNextExpireTime>
800470a: 60f8 str r0, [r7, #12]
/* If a timer has expired, process it. Otherwise, block this task
until either a timer does expire, or a command is received. */
prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
800470c: 68bb ldr r3, [r7, #8]
800470e: 4619 mov r1, r3
8004710: 68f8 ldr r0, [r7, #12]
8004712: f000 f803 bl 800471c <prvProcessTimerOrBlockTask>
/* Empty the command queue. */
prvProcessReceivedCommands();
8004716: f000 f8d5 bl 80048c4 <prvProcessReceivedCommands>
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
800471a: e7f1 b.n 8004700 <prvTimerTask+0x8>
0800471c <prvProcessTimerOrBlockTask>:
}
}
/*-----------------------------------------------------------*/
static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
800471c: b580 push {r7, lr}
800471e: b084 sub sp, #16
8004720: af00 add r7, sp, #0
8004722: 6078 str r0, [r7, #4]
8004724: 6039 str r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;
vTaskSuspendAll();
8004726: f7ff fa39 bl 8003b9c <vTaskSuspendAll>
/* Obtain the time now to make an assessment as to whether the timer
has expired or not. If obtaining the time causes the lists to switch
then don't process this timer as any timers that remained in the list
when the lists were switched will have been processed within the
prvSampleTimeNow() function. */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
800472a: f107 0308 add.w r3, r7, #8
800472e: 4618 mov r0, r3
8004730: f000 f866 bl 8004800 <prvSampleTimeNow>
8004734: 60f8 str r0, [r7, #12]
if( xTimerListsWereSwitched == pdFALSE )
8004736: 68bb ldr r3, [r7, #8]
8004738: 2b00 cmp r3, #0
800473a: d130 bne.n 800479e <prvProcessTimerOrBlockTask+0x82>
{
/* The tick count has not overflowed, has the timer expired? */
if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
800473c: 683b ldr r3, [r7, #0]
800473e: 2b00 cmp r3, #0
8004740: d10a bne.n 8004758 <prvProcessTimerOrBlockTask+0x3c>
8004742: 687a ldr r2, [r7, #4]
8004744: 68fb ldr r3, [r7, #12]
8004746: 429a cmp r2, r3
8004748: d806 bhi.n 8004758 <prvProcessTimerOrBlockTask+0x3c>
{
( void ) xTaskResumeAll();
800474a: f7ff fa35 bl 8003bb8 <xTaskResumeAll>
prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
800474e: 68f9 ldr r1, [r7, #12]
8004750: 6878 ldr r0, [r7, #4]
8004752: f7ff ff85 bl 8004660 <prvProcessExpiredTimer>
else
{
( void ) xTaskResumeAll();
}
}
}
8004756: e024 b.n 80047a2 <prvProcessTimerOrBlockTask+0x86>
if( xListWasEmpty != pdFALSE )
8004758: 683b ldr r3, [r7, #0]
800475a: 2b00 cmp r3, #0
800475c: d008 beq.n 8004770 <prvProcessTimerOrBlockTask+0x54>
xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
800475e: 4b13 ldr r3, [pc, #76] ; (80047ac <prvProcessTimerOrBlockTask+0x90>)
8004760: 681b ldr r3, [r3, #0]
8004762: 681b ldr r3, [r3, #0]
8004764: 2b00 cmp r3, #0
8004766: d101 bne.n 800476c <prvProcessTimerOrBlockTask+0x50>
8004768: 2301 movs r3, #1
800476a: e000 b.n 800476e <prvProcessTimerOrBlockTask+0x52>
800476c: 2300 movs r3, #0
800476e: 603b str r3, [r7, #0]
vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
8004770: 4b0f ldr r3, [pc, #60] ; (80047b0 <prvProcessTimerOrBlockTask+0x94>)
8004772: 6818 ldr r0, [r3, #0]
8004774: 687a ldr r2, [r7, #4]
8004776: 68fb ldr r3, [r7, #12]
8004778: 1ad3 subs r3, r2, r3
800477a: 683a ldr r2, [r7, #0]
800477c: 4619 mov r1, r3
800477e: f7fe ff7d bl 800367c <vQueueWaitForMessageRestricted>
if( xTaskResumeAll() == pdFALSE )
8004782: f7ff fa19 bl 8003bb8 <xTaskResumeAll>
8004786: 4603 mov r3, r0
8004788: 2b00 cmp r3, #0
800478a: d10a bne.n 80047a2 <prvProcessTimerOrBlockTask+0x86>
portYIELD_WITHIN_API();
800478c: 4b09 ldr r3, [pc, #36] ; (80047b4 <prvProcessTimerOrBlockTask+0x98>)
800478e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8004792: 601a str r2, [r3, #0]
8004794: f3bf 8f4f dsb sy
8004798: f3bf 8f6f isb sy
}
800479c: e001 b.n 80047a2 <prvProcessTimerOrBlockTask+0x86>
( void ) xTaskResumeAll();
800479e: f7ff fa0b bl 8003bb8 <xTaskResumeAll>
}
80047a2: bf00 nop
80047a4: 3710 adds r7, #16
80047a6: 46bd mov sp, r7
80047a8: bd80 pop {r7, pc}
80047aa: bf00 nop
80047ac: 20000dec .word 0x20000dec
80047b0: 20000df0 .word 0x20000df0
80047b4: e000ed04 .word 0xe000ed04
080047b8 <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/
static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
80047b8: b480 push {r7}
80047ba: b085 sub sp, #20
80047bc: af00 add r7, sp, #0
80047be: 6078 str r0, [r7, #4]
the timer with the nearest expiry time will expire. If there are no
active timers then just set the next expire time to 0. That will cause
this task to unblock when the tick count overflows, at which point the
timer lists will be switched and the next expiry time can be
re-assessed. */
*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
80047c0: 4b0e ldr r3, [pc, #56] ; (80047fc <prvGetNextExpireTime+0x44>)
80047c2: 681b ldr r3, [r3, #0]
80047c4: 681b ldr r3, [r3, #0]
80047c6: 2b00 cmp r3, #0
80047c8: d101 bne.n 80047ce <prvGetNextExpireTime+0x16>
80047ca: 2201 movs r2, #1
80047cc: e000 b.n 80047d0 <prvGetNextExpireTime+0x18>
80047ce: 2200 movs r2, #0
80047d0: 687b ldr r3, [r7, #4]
80047d2: 601a str r2, [r3, #0]
if( *pxListWasEmpty == pdFALSE )
80047d4: 687b ldr r3, [r7, #4]
80047d6: 681b ldr r3, [r3, #0]
80047d8: 2b00 cmp r3, #0
80047da: d105 bne.n 80047e8 <prvGetNextExpireTime+0x30>
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
80047dc: 4b07 ldr r3, [pc, #28] ; (80047fc <prvGetNextExpireTime+0x44>)
80047de: 681b ldr r3, [r3, #0]
80047e0: 68db ldr r3, [r3, #12]
80047e2: 681b ldr r3, [r3, #0]
80047e4: 60fb str r3, [r7, #12]
80047e6: e001 b.n 80047ec <prvGetNextExpireTime+0x34>
}
else
{
/* Ensure the task unblocks when the tick count rolls over. */
xNextExpireTime = ( TickType_t ) 0U;
80047e8: 2300 movs r3, #0
80047ea: 60fb str r3, [r7, #12]
}
return xNextExpireTime;
80047ec: 68fb ldr r3, [r7, #12]
}
80047ee: 4618 mov r0, r3
80047f0: 3714 adds r7, #20
80047f2: 46bd mov sp, r7
80047f4: f85d 7b04 ldr.w r7, [sp], #4
80047f8: 4770 bx lr
80047fa: bf00 nop
80047fc: 20000de8 .word 0x20000de8
08004800 <prvSampleTimeNow>:
/*-----------------------------------------------------------*/
static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
8004800: b580 push {r7, lr}
8004802: b084 sub sp, #16
8004804: af00 add r7, sp, #0
8004806: 6078 str r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
xTimeNow = xTaskGetTickCount();
8004808: f7ff fa74 bl 8003cf4 <xTaskGetTickCount>
800480c: 60f8 str r0, [r7, #12]
if( xTimeNow < xLastTime )
800480e: 4b0b ldr r3, [pc, #44] ; (800483c <prvSampleTimeNow+0x3c>)
8004810: 681b ldr r3, [r3, #0]
8004812: 68fa ldr r2, [r7, #12]
8004814: 429a cmp r2, r3
8004816: d205 bcs.n 8004824 <prvSampleTimeNow+0x24>
{
prvSwitchTimerLists();
8004818: f000 f936 bl 8004a88 <prvSwitchTimerLists>
*pxTimerListsWereSwitched = pdTRUE;
800481c: 687b ldr r3, [r7, #4]
800481e: 2201 movs r2, #1
8004820: 601a str r2, [r3, #0]
8004822: e002 b.n 800482a <prvSampleTimeNow+0x2a>
}
else
{
*pxTimerListsWereSwitched = pdFALSE;
8004824: 687b ldr r3, [r7, #4]
8004826: 2200 movs r2, #0
8004828: 601a str r2, [r3, #0]
}
xLastTime = xTimeNow;
800482a: 4a04 ldr r2, [pc, #16] ; (800483c <prvSampleTimeNow+0x3c>)
800482c: 68fb ldr r3, [r7, #12]
800482e: 6013 str r3, [r2, #0]
return xTimeNow;
8004830: 68fb ldr r3, [r7, #12]
}
8004832: 4618 mov r0, r3
8004834: 3710 adds r7, #16
8004836: 46bd mov sp, r7
8004838: bd80 pop {r7, pc}
800483a: bf00 nop
800483c: 20000df8 .word 0x20000df8
08004840 <prvInsertTimerInActiveList>:
/*-----------------------------------------------------------*/
static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
{
8004840: b580 push {r7, lr}
8004842: b086 sub sp, #24
8004844: af00 add r7, sp, #0
8004846: 60f8 str r0, [r7, #12]
8004848: 60b9 str r1, [r7, #8]
800484a: 607a str r2, [r7, #4]
800484c: 603b str r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
800484e: 2300 movs r3, #0
8004850: 617b str r3, [r7, #20]
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
8004852: 68fb ldr r3, [r7, #12]
8004854: 68ba ldr r2, [r7, #8]
8004856: 605a str r2, [r3, #4]
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
8004858: 68fb ldr r3, [r7, #12]
800485a: 68fa ldr r2, [r7, #12]
800485c: 611a str r2, [r3, #16]
if( xNextExpiryTime <= xTimeNow )
800485e: 68ba ldr r2, [r7, #8]
8004860: 687b ldr r3, [r7, #4]
8004862: 429a cmp r2, r3
8004864: d812 bhi.n 800488c <prvInsertTimerInActiveList+0x4c>
{
/* Has the expiry time elapsed between the command to start/reset a
timer was issued, and the time the command was processed? */
if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8004866: 687a ldr r2, [r7, #4]
8004868: 683b ldr r3, [r7, #0]
800486a: 1ad2 subs r2, r2, r3
800486c: 68fb ldr r3, [r7, #12]
800486e: 699b ldr r3, [r3, #24]
8004870: 429a cmp r2, r3
8004872: d302 bcc.n 800487a <prvInsertTimerInActiveList+0x3a>
{
/* The time between a command being issued and the command being
processed actually exceeds the timers period. */
xProcessTimerNow = pdTRUE;
8004874: 2301 movs r3, #1
8004876: 617b str r3, [r7, #20]
8004878: e01b b.n 80048b2 <prvInsertTimerInActiveList+0x72>
}
else
{
vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
800487a: 4b10 ldr r3, [pc, #64] ; (80048bc <prvInsertTimerInActiveList+0x7c>)
800487c: 681a ldr r2, [r3, #0]
800487e: 68fb ldr r3, [r7, #12]
8004880: 3304 adds r3, #4
8004882: 4619 mov r1, r3
8004884: 4610 mov r0, r2
8004886: f7fe f9de bl 8002c46 <vListInsert>
800488a: e012 b.n 80048b2 <prvInsertTimerInActiveList+0x72>
}
}
else
{
if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
800488c: 687a ldr r2, [r7, #4]
800488e: 683b ldr r3, [r7, #0]
8004890: 429a cmp r2, r3
8004892: d206 bcs.n 80048a2 <prvInsertTimerInActiveList+0x62>
8004894: 68ba ldr r2, [r7, #8]
8004896: 683b ldr r3, [r7, #0]
8004898: 429a cmp r2, r3
800489a: d302 bcc.n 80048a2 <prvInsertTimerInActiveList+0x62>
{
/* If, since the command was issued, the tick count has overflowed
but the expiry time has not, then the timer must have already passed
its expiry time and should be processed immediately. */
xProcessTimerNow = pdTRUE;
800489c: 2301 movs r3, #1
800489e: 617b str r3, [r7, #20]
80048a0: e007 b.n 80048b2 <prvInsertTimerInActiveList+0x72>
}
else
{
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
80048a2: 4b07 ldr r3, [pc, #28] ; (80048c0 <prvInsertTimerInActiveList+0x80>)
80048a4: 681a ldr r2, [r3, #0]
80048a6: 68fb ldr r3, [r7, #12]
80048a8: 3304 adds r3, #4
80048aa: 4619 mov r1, r3
80048ac: 4610 mov r0, r2
80048ae: f7fe f9ca bl 8002c46 <vListInsert>
}
}
return xProcessTimerNow;
80048b2: 697b ldr r3, [r7, #20]
}
80048b4: 4618 mov r0, r3
80048b6: 3718 adds r7, #24
80048b8: 46bd mov sp, r7
80048ba: bd80 pop {r7, pc}
80048bc: 20000dec .word 0x20000dec
80048c0: 20000de8 .word 0x20000de8
080048c4 <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/
static void prvProcessReceivedCommands( void )
{
80048c4: b580 push {r7, lr}
80048c6: b08e sub sp, #56 ; 0x38
80048c8: af02 add r7, sp, #8
DaemonTaskMessage_t xMessage;
Timer_t *pxTimer;
BaseType_t xTimerListsWereSwitched, xResult;
TickType_t xTimeNow;
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
80048ca: e0ca b.n 8004a62 <prvProcessReceivedCommands+0x19e>
{
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
{
/* Negative commands are pended function calls rather than timer
commands. */
if( xMessage.xMessageID < ( BaseType_t ) 0 )
80048cc: 687b ldr r3, [r7, #4]
80048ce: 2b00 cmp r3, #0
80048d0: da18 bge.n 8004904 <prvProcessReceivedCommands+0x40>
{
const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
80048d2: 1d3b adds r3, r7, #4
80048d4: 3304 adds r3, #4
80048d6: 62fb str r3, [r7, #44] ; 0x2c
/* The timer uses the xCallbackParameters member to request a
callback be executed. Check the callback is not NULL. */
configASSERT( pxCallback );
80048d8: 6afb ldr r3, [r7, #44] ; 0x2c
80048da: 2b00 cmp r3, #0
80048dc: d10a bne.n 80048f4 <prvProcessReceivedCommands+0x30>
__asm volatile
80048de: f04f 0350 mov.w r3, #80 ; 0x50
80048e2: f383 8811 msr BASEPRI, r3
80048e6: f3bf 8f6f isb sy
80048ea: f3bf 8f4f dsb sy
80048ee: 61fb str r3, [r7, #28]
}
80048f0: bf00 nop
80048f2: e7fe b.n 80048f2 <prvProcessReceivedCommands+0x2e>
/* Call the function. */
pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
80048f4: 6afb ldr r3, [r7, #44] ; 0x2c
80048f6: 681b ldr r3, [r3, #0]
80048f8: 6afa ldr r2, [r7, #44] ; 0x2c
80048fa: 6850 ldr r0, [r2, #4]
80048fc: 6afa ldr r2, [r7, #44] ; 0x2c
80048fe: 6892 ldr r2, [r2, #8]
8004900: 4611 mov r1, r2
8004902: 4798 blx r3
}
#endif /* INCLUDE_xTimerPendFunctionCall */
/* Commands that are positive are timer commands rather than pended
function calls. */
if( xMessage.xMessageID >= ( BaseType_t ) 0 )
8004904: 687b ldr r3, [r7, #4]
8004906: 2b00 cmp r3, #0
8004908: f2c0 80ab blt.w 8004a62 <prvProcessReceivedCommands+0x19e>
{
/* The messages uses the xTimerParameters member to work on a
software timer. */
pxTimer = xMessage.u.xTimerParameters.pxTimer;
800490c: 68fb ldr r3, [r7, #12]
800490e: 62bb str r3, [r7, #40] ; 0x28
if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
8004910: 6abb ldr r3, [r7, #40] ; 0x28
8004912: 695b ldr r3, [r3, #20]
8004914: 2b00 cmp r3, #0
8004916: d004 beq.n 8004922 <prvProcessReceivedCommands+0x5e>
{
/* The timer is in a list, remove it. */
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8004918: 6abb ldr r3, [r7, #40] ; 0x28
800491a: 3304 adds r3, #4
800491c: 4618 mov r0, r3
800491e: f7fe f9cb bl 8002cb8 <uxListRemove>
it must be present in the function call. prvSampleTimeNow() must be
called after the message is received from xTimerQueue so there is no
possibility of a higher priority task adding a message to the message
queue with a time that is ahead of the timer daemon task (because it
pre-empted the timer daemon task after the xTimeNow value was set). */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
8004922: 463b mov r3, r7
8004924: 4618 mov r0, r3
8004926: f7ff ff6b bl 8004800 <prvSampleTimeNow>
800492a: 6278 str r0, [r7, #36] ; 0x24
switch( xMessage.xMessageID )
800492c: 687b ldr r3, [r7, #4]
800492e: 2b09 cmp r3, #9
8004930: f200 8096 bhi.w 8004a60 <prvProcessReceivedCommands+0x19c>
8004934: a201 add r2, pc, #4 ; (adr r2, 800493c <prvProcessReceivedCommands+0x78>)
8004936: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800493a: bf00 nop
800493c: 08004965 .word 0x08004965
8004940: 08004965 .word 0x08004965
8004944: 08004965 .word 0x08004965
8004948: 080049d9 .word 0x080049d9
800494c: 080049ed .word 0x080049ed
8004950: 08004a37 .word 0x08004a37
8004954: 08004965 .word 0x08004965
8004958: 08004965 .word 0x08004965
800495c: 080049d9 .word 0x080049d9
8004960: 080049ed .word 0x080049ed
case tmrCOMMAND_START_FROM_ISR :
case tmrCOMMAND_RESET :
case tmrCOMMAND_RESET_FROM_ISR :
case tmrCOMMAND_START_DONT_TRACE :
/* Start or restart a timer. */
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
8004964: 6abb ldr r3, [r7, #40] ; 0x28
8004966: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
800496a: f043 0301 orr.w r3, r3, #1
800496e: b2da uxtb r2, r3
8004970: 6abb ldr r3, [r7, #40] ; 0x28
8004972: f883 2028 strb.w r2, [r3, #40] ; 0x28
if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
8004976: 68ba ldr r2, [r7, #8]
8004978: 6abb ldr r3, [r7, #40] ; 0x28
800497a: 699b ldr r3, [r3, #24]
800497c: 18d1 adds r1, r2, r3
800497e: 68bb ldr r3, [r7, #8]
8004980: 6a7a ldr r2, [r7, #36] ; 0x24
8004982: 6ab8 ldr r0, [r7, #40] ; 0x28
8004984: f7ff ff5c bl 8004840 <prvInsertTimerInActiveList>
8004988: 4603 mov r3, r0
800498a: 2b00 cmp r3, #0
800498c: d069 beq.n 8004a62 <prvProcessReceivedCommands+0x19e>
{
/* The timer expired before it was added to the active
timer list. Process it now. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
800498e: 6abb ldr r3, [r7, #40] ; 0x28
8004990: 6a1b ldr r3, [r3, #32]
8004992: 6ab8 ldr r0, [r7, #40] ; 0x28
8004994: 4798 blx r3
traceTIMER_EXPIRED( pxTimer );
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
8004996: 6abb ldr r3, [r7, #40] ; 0x28
8004998: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
800499c: f003 0304 and.w r3, r3, #4
80049a0: 2b00 cmp r3, #0
80049a2: d05e beq.n 8004a62 <prvProcessReceivedCommands+0x19e>
{
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
80049a4: 68ba ldr r2, [r7, #8]
80049a6: 6abb ldr r3, [r7, #40] ; 0x28
80049a8: 699b ldr r3, [r3, #24]
80049aa: 441a add r2, r3
80049ac: 2300 movs r3, #0
80049ae: 9300 str r3, [sp, #0]
80049b0: 2300 movs r3, #0
80049b2: 2100 movs r1, #0
80049b4: 6ab8 ldr r0, [r7, #40] ; 0x28
80049b6: f7ff fe05 bl 80045c4 <xTimerGenericCommand>
80049ba: 6238 str r0, [r7, #32]
configASSERT( xResult );
80049bc: 6a3b ldr r3, [r7, #32]
80049be: 2b00 cmp r3, #0
80049c0: d14f bne.n 8004a62 <prvProcessReceivedCommands+0x19e>
__asm volatile
80049c2: f04f 0350 mov.w r3, #80 ; 0x50
80049c6: f383 8811 msr BASEPRI, r3
80049ca: f3bf 8f6f isb sy
80049ce: f3bf 8f4f dsb sy
80049d2: 61bb str r3, [r7, #24]
}
80049d4: bf00 nop
80049d6: e7fe b.n 80049d6 <prvProcessReceivedCommands+0x112>
break;
case tmrCOMMAND_STOP :
case tmrCOMMAND_STOP_FROM_ISR :
/* The timer has already been removed from the active list. */
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
80049d8: 6abb ldr r3, [r7, #40] ; 0x28
80049da: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
80049de: f023 0301 bic.w r3, r3, #1
80049e2: b2da uxtb r2, r3
80049e4: 6abb ldr r3, [r7, #40] ; 0x28
80049e6: f883 2028 strb.w r2, [r3, #40] ; 0x28
break;
80049ea: e03a b.n 8004a62 <prvProcessReceivedCommands+0x19e>
case tmrCOMMAND_CHANGE_PERIOD :
case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
80049ec: 6abb ldr r3, [r7, #40] ; 0x28
80049ee: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
80049f2: f043 0301 orr.w r3, r3, #1
80049f6: b2da uxtb r2, r3
80049f8: 6abb ldr r3, [r7, #40] ; 0x28
80049fa: f883 2028 strb.w r2, [r3, #40] ; 0x28
pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
80049fe: 68ba ldr r2, [r7, #8]
8004a00: 6abb ldr r3, [r7, #40] ; 0x28
8004a02: 619a str r2, [r3, #24]
configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
8004a04: 6abb ldr r3, [r7, #40] ; 0x28
8004a06: 699b ldr r3, [r3, #24]
8004a08: 2b00 cmp r3, #0
8004a0a: d10a bne.n 8004a22 <prvProcessReceivedCommands+0x15e>
__asm volatile
8004a0c: f04f 0350 mov.w r3, #80 ; 0x50
8004a10: f383 8811 msr BASEPRI, r3
8004a14: f3bf 8f6f isb sy
8004a18: f3bf 8f4f dsb sy
8004a1c: 617b str r3, [r7, #20]
}
8004a1e: bf00 nop
8004a20: e7fe b.n 8004a20 <prvProcessReceivedCommands+0x15c>
be longer or shorter than the old one. The command time is
therefore set to the current time, and as the period cannot
be zero the next expiry time can only be in the future,
meaning (unlike for the xTimerStart() case above) there is
no fail case that needs to be handled here. */
( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
8004a22: 6abb ldr r3, [r7, #40] ; 0x28
8004a24: 699a ldr r2, [r3, #24]
8004a26: 6a7b ldr r3, [r7, #36] ; 0x24
8004a28: 18d1 adds r1, r2, r3
8004a2a: 6a7b ldr r3, [r7, #36] ; 0x24
8004a2c: 6a7a ldr r2, [r7, #36] ; 0x24
8004a2e: 6ab8 ldr r0, [r7, #40] ; 0x28
8004a30: f7ff ff06 bl 8004840 <prvInsertTimerInActiveList>
break;
8004a34: e015 b.n 8004a62 <prvProcessReceivedCommands+0x19e>
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* The timer has already been removed from the active list,
just free up the memory if the memory was dynamically
allocated. */
if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
8004a36: 6abb ldr r3, [r7, #40] ; 0x28
8004a38: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
8004a3c: f003 0302 and.w r3, r3, #2
8004a40: 2b00 cmp r3, #0
8004a42: d103 bne.n 8004a4c <prvProcessReceivedCommands+0x188>
{
vPortFree( pxTimer );
8004a44: 6ab8 ldr r0, [r7, #40] ; 0x28
8004a46: f000 fbdb bl 8005200 <vPortFree>
8004a4a: e00a b.n 8004a62 <prvProcessReceivedCommands+0x19e>
}
else
{
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
8004a4c: 6abb ldr r3, [r7, #40] ; 0x28
8004a4e: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
8004a52: f023 0301 bic.w r3, r3, #1
8004a56: b2da uxtb r2, r3
8004a58: 6abb ldr r3, [r7, #40] ; 0x28
8004a5a: f883 2028 strb.w r2, [r3, #40] ; 0x28
no need to free the memory - just mark the timer as
"not active". */
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
break;
8004a5e: e000 b.n 8004a62 <prvProcessReceivedCommands+0x19e>
default :
/* Don't expect to get here. */
break;
8004a60: bf00 nop
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
8004a62: 4b08 ldr r3, [pc, #32] ; (8004a84 <prvProcessReceivedCommands+0x1c0>)
8004a64: 681b ldr r3, [r3, #0]
8004a66: 1d39 adds r1, r7, #4
8004a68: 2200 movs r2, #0
8004a6a: 4618 mov r0, r3
8004a6c: f7fe fbec bl 8003248 <xQueueReceive>
8004a70: 4603 mov r3, r0
8004a72: 2b00 cmp r3, #0
8004a74: f47f af2a bne.w 80048cc <prvProcessReceivedCommands+0x8>
}
}
}
}
8004a78: bf00 nop
8004a7a: bf00 nop
8004a7c: 3730 adds r7, #48 ; 0x30
8004a7e: 46bd mov sp, r7
8004a80: bd80 pop {r7, pc}
8004a82: bf00 nop
8004a84: 20000df0 .word 0x20000df0
08004a88 <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/
static void prvSwitchTimerLists( void )
{
8004a88: b580 push {r7, lr}
8004a8a: b088 sub sp, #32
8004a8c: af02 add r7, sp, #8
/* The tick count has overflowed. The timer lists must be switched.
If there are any timers still referenced from the current timer list
then they must have expired and should be processed before the lists
are switched. */
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
8004a8e: e048 b.n 8004b22 <prvSwitchTimerLists+0x9a>
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
8004a90: 4b2d ldr r3, [pc, #180] ; (8004b48 <prvSwitchTimerLists+0xc0>)
8004a92: 681b ldr r3, [r3, #0]
8004a94: 68db ldr r3, [r3, #12]
8004a96: 681b ldr r3, [r3, #0]
8004a98: 613b str r3, [r7, #16]
/* Remove the timer from the list. */
pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8004a9a: 4b2b ldr r3, [pc, #172] ; (8004b48 <prvSwitchTimerLists+0xc0>)
8004a9c: 681b ldr r3, [r3, #0]
8004a9e: 68db ldr r3, [r3, #12]
8004aa0: 68db ldr r3, [r3, #12]
8004aa2: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8004aa4: 68fb ldr r3, [r7, #12]
8004aa6: 3304 adds r3, #4
8004aa8: 4618 mov r0, r3
8004aaa: f7fe f905 bl 8002cb8 <uxListRemove>
traceTIMER_EXPIRED( pxTimer );
/* Execute its callback, then send a command to restart the timer if
it is an auto-reload timer. It cannot be restarted here as the lists
have not yet been switched. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
8004aae: 68fb ldr r3, [r7, #12]
8004ab0: 6a1b ldr r3, [r3, #32]
8004ab2: 68f8 ldr r0, [r7, #12]
8004ab4: 4798 blx r3
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
8004ab6: 68fb ldr r3, [r7, #12]
8004ab8: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
8004abc: f003 0304 and.w r3, r3, #4
8004ac0: 2b00 cmp r3, #0
8004ac2: d02e beq.n 8004b22 <prvSwitchTimerLists+0x9a>
the timer going into the same timer list then it has already expired
and the timer should be re-inserted into the current list so it is
processed again within this loop. Otherwise a command should be sent
to restart the timer to ensure it is only inserted into a list after
the lists have been swapped. */
xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
8004ac4: 68fb ldr r3, [r7, #12]
8004ac6: 699b ldr r3, [r3, #24]
8004ac8: 693a ldr r2, [r7, #16]
8004aca: 4413 add r3, r2
8004acc: 60bb str r3, [r7, #8]
if( xReloadTime > xNextExpireTime )
8004ace: 68ba ldr r2, [r7, #8]
8004ad0: 693b ldr r3, [r7, #16]
8004ad2: 429a cmp r2, r3
8004ad4: d90e bls.n 8004af4 <prvSwitchTimerLists+0x6c>
{
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
8004ad6: 68fb ldr r3, [r7, #12]
8004ad8: 68ba ldr r2, [r7, #8]
8004ada: 605a str r2, [r3, #4]
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
8004adc: 68fb ldr r3, [r7, #12]
8004ade: 68fa ldr r2, [r7, #12]
8004ae0: 611a str r2, [r3, #16]
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
8004ae2: 4b19 ldr r3, [pc, #100] ; (8004b48 <prvSwitchTimerLists+0xc0>)
8004ae4: 681a ldr r2, [r3, #0]
8004ae6: 68fb ldr r3, [r7, #12]
8004ae8: 3304 adds r3, #4
8004aea: 4619 mov r1, r3
8004aec: 4610 mov r0, r2
8004aee: f7fe f8aa bl 8002c46 <vListInsert>
8004af2: e016 b.n 8004b22 <prvSwitchTimerLists+0x9a>
}
else
{
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
8004af4: 2300 movs r3, #0
8004af6: 9300 str r3, [sp, #0]
8004af8: 2300 movs r3, #0
8004afa: 693a ldr r2, [r7, #16]
8004afc: 2100 movs r1, #0
8004afe: 68f8 ldr r0, [r7, #12]
8004b00: f7ff fd60 bl 80045c4 <xTimerGenericCommand>
8004b04: 6078 str r0, [r7, #4]
configASSERT( xResult );
8004b06: 687b ldr r3, [r7, #4]
8004b08: 2b00 cmp r3, #0
8004b0a: d10a bne.n 8004b22 <prvSwitchTimerLists+0x9a>
__asm volatile
8004b0c: f04f 0350 mov.w r3, #80 ; 0x50
8004b10: f383 8811 msr BASEPRI, r3
8004b14: f3bf 8f6f isb sy
8004b18: f3bf 8f4f dsb sy
8004b1c: 603b str r3, [r7, #0]
}
8004b1e: bf00 nop
8004b20: e7fe b.n 8004b20 <prvSwitchTimerLists+0x98>
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
8004b22: 4b09 ldr r3, [pc, #36] ; (8004b48 <prvSwitchTimerLists+0xc0>)
8004b24: 681b ldr r3, [r3, #0]
8004b26: 681b ldr r3, [r3, #0]
8004b28: 2b00 cmp r3, #0
8004b2a: d1b1 bne.n 8004a90 <prvSwitchTimerLists+0x8>
{
mtCOVERAGE_TEST_MARKER();
}
}
pxTemp = pxCurrentTimerList;
8004b2c: 4b06 ldr r3, [pc, #24] ; (8004b48 <prvSwitchTimerLists+0xc0>)
8004b2e: 681b ldr r3, [r3, #0]
8004b30: 617b str r3, [r7, #20]
pxCurrentTimerList = pxOverflowTimerList;
8004b32: 4b06 ldr r3, [pc, #24] ; (8004b4c <prvSwitchTimerLists+0xc4>)
8004b34: 681b ldr r3, [r3, #0]
8004b36: 4a04 ldr r2, [pc, #16] ; (8004b48 <prvSwitchTimerLists+0xc0>)
8004b38: 6013 str r3, [r2, #0]
pxOverflowTimerList = pxTemp;
8004b3a: 4a04 ldr r2, [pc, #16] ; (8004b4c <prvSwitchTimerLists+0xc4>)
8004b3c: 697b ldr r3, [r7, #20]
8004b3e: 6013 str r3, [r2, #0]
}
8004b40: bf00 nop
8004b42: 3718 adds r7, #24
8004b44: 46bd mov sp, r7
8004b46: bd80 pop {r7, pc}
8004b48: 20000de8 .word 0x20000de8
8004b4c: 20000dec .word 0x20000dec
08004b50 <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/
static void prvCheckForValidListAndQueue( void )
{
8004b50: b580 push {r7, lr}
8004b52: b082 sub sp, #8
8004b54: af02 add r7, sp, #8
/* Check that the list from which active timers are referenced, and the
queue used to communicate with the timer service, have been
initialised. */
taskENTER_CRITICAL();
8004b56: f000 f965 bl 8004e24 <vPortEnterCritical>
{
if( xTimerQueue == NULL )
8004b5a: 4b15 ldr r3, [pc, #84] ; (8004bb0 <prvCheckForValidListAndQueue+0x60>)
8004b5c: 681b ldr r3, [r3, #0]
8004b5e: 2b00 cmp r3, #0
8004b60: d120 bne.n 8004ba4 <prvCheckForValidListAndQueue+0x54>
{
vListInitialise( &xActiveTimerList1 );
8004b62: 4814 ldr r0, [pc, #80] ; (8004bb4 <prvCheckForValidListAndQueue+0x64>)
8004b64: f7fe f81e bl 8002ba4 <vListInitialise>
vListInitialise( &xActiveTimerList2 );
8004b68: 4813 ldr r0, [pc, #76] ; (8004bb8 <prvCheckForValidListAndQueue+0x68>)
8004b6a: f7fe f81b bl 8002ba4 <vListInitialise>
pxCurrentTimerList = &xActiveTimerList1;
8004b6e: 4b13 ldr r3, [pc, #76] ; (8004bbc <prvCheckForValidListAndQueue+0x6c>)
8004b70: 4a10 ldr r2, [pc, #64] ; (8004bb4 <prvCheckForValidListAndQueue+0x64>)
8004b72: 601a str r2, [r3, #0]
pxOverflowTimerList = &xActiveTimerList2;
8004b74: 4b12 ldr r3, [pc, #72] ; (8004bc0 <prvCheckForValidListAndQueue+0x70>)
8004b76: 4a10 ldr r2, [pc, #64] ; (8004bb8 <prvCheckForValidListAndQueue+0x68>)
8004b78: 601a str r2, [r3, #0]
/* The timer queue is allocated statically in case
configSUPPORT_DYNAMIC_ALLOCATION is 0. */
static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
8004b7a: 2300 movs r3, #0
8004b7c: 9300 str r3, [sp, #0]
8004b7e: 4b11 ldr r3, [pc, #68] ; (8004bc4 <prvCheckForValidListAndQueue+0x74>)
8004b80: 4a11 ldr r2, [pc, #68] ; (8004bc8 <prvCheckForValidListAndQueue+0x78>)
8004b82: 2110 movs r1, #16
8004b84: 200a movs r0, #10
8004b86: f7fe f929 bl 8002ddc <xQueueGenericCreateStatic>
8004b8a: 4603 mov r3, r0
8004b8c: 4a08 ldr r2, [pc, #32] ; (8004bb0 <prvCheckForValidListAndQueue+0x60>)
8004b8e: 6013 str r3, [r2, #0]
}
#endif
#if ( configQUEUE_REGISTRY_SIZE > 0 )
{
if( xTimerQueue != NULL )
8004b90: 4b07 ldr r3, [pc, #28] ; (8004bb0 <prvCheckForValidListAndQueue+0x60>)
8004b92: 681b ldr r3, [r3, #0]
8004b94: 2b00 cmp r3, #0
8004b96: d005 beq.n 8004ba4 <prvCheckForValidListAndQueue+0x54>
{
vQueueAddToRegistry( xTimerQueue, "TmrQ" );
8004b98: 4b05 ldr r3, [pc, #20] ; (8004bb0 <prvCheckForValidListAndQueue+0x60>)
8004b9a: 681b ldr r3, [r3, #0]
8004b9c: 490b ldr r1, [pc, #44] ; (8004bcc <prvCheckForValidListAndQueue+0x7c>)
8004b9e: 4618 mov r0, r3
8004ba0: f7fe fd42 bl 8003628 <vQueueAddToRegistry>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8004ba4: f000 f96e bl 8004e84 <vPortExitCritical>
}
8004ba8: bf00 nop
8004baa: 46bd mov sp, r7
8004bac: bd80 pop {r7, pc}
8004bae: bf00 nop
8004bb0: 20000df0 .word 0x20000df0
8004bb4: 20000dc0 .word 0x20000dc0
8004bb8: 20000dd4 .word 0x20000dd4
8004bbc: 20000de8 .word 0x20000de8
8004bc0: 20000dec .word 0x20000dec
8004bc4: 20000e9c .word 0x20000e9c
8004bc8: 20000dfc .word 0x20000dfc
8004bcc: 08005650 .word 0x08005650
08004bd0 <pxPortInitialiseStack>:
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
8004bd0: b480 push {r7}
8004bd2: b085 sub sp, #20
8004bd4: af00 add r7, sp, #0
8004bd6: 60f8 str r0, [r7, #12]
8004bd8: 60b9 str r1, [r7, #8]
8004bda: 607a str r2, [r7, #4]
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
of interrupts, and to ensure alignment. */
pxTopOfStack--;
8004bdc: 68fb ldr r3, [r7, #12]
8004bde: 3b04 subs r3, #4
8004be0: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
8004be2: 68fb ldr r3, [r7, #12]
8004be4: f04f 7280 mov.w r2, #16777216 ; 0x1000000
8004be8: 601a str r2, [r3, #0]
pxTopOfStack--;
8004bea: 68fb ldr r3, [r7, #12]
8004bec: 3b04 subs r3, #4
8004bee: 60fb str r3, [r7, #12]
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
8004bf0: 68bb ldr r3, [r7, #8]
8004bf2: f023 0201 bic.w r2, r3, #1
8004bf6: 68fb ldr r3, [r7, #12]
8004bf8: 601a str r2, [r3, #0]
pxTopOfStack--;
8004bfa: 68fb ldr r3, [r7, #12]
8004bfc: 3b04 subs r3, #4
8004bfe: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
8004c00: 4a0c ldr r2, [pc, #48] ; (8004c34 <pxPortInitialiseStack+0x64>)
8004c02: 68fb ldr r3, [r7, #12]
8004c04: 601a str r2, [r3, #0]
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
8004c06: 68fb ldr r3, [r7, #12]
8004c08: 3b14 subs r3, #20
8004c0a: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
8004c0c: 687a ldr r2, [r7, #4]
8004c0e: 68fb ldr r3, [r7, #12]
8004c10: 601a str r2, [r3, #0]
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
8004c12: 68fb ldr r3, [r7, #12]
8004c14: 3b04 subs r3, #4
8004c16: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_EXC_RETURN;
8004c18: 68fb ldr r3, [r7, #12]
8004c1a: f06f 0202 mvn.w r2, #2
8004c1e: 601a str r2, [r3, #0]
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
8004c20: 68fb ldr r3, [r7, #12]
8004c22: 3b20 subs r3, #32
8004c24: 60fb str r3, [r7, #12]
return pxTopOfStack;
8004c26: 68fb ldr r3, [r7, #12]
}
8004c28: 4618 mov r0, r3
8004c2a: 3714 adds r7, #20
8004c2c: 46bd mov sp, r7
8004c2e: f85d 7b04 ldr.w r7, [sp], #4
8004c32: 4770 bx lr
8004c34: 08004c39 .word 0x08004c39
08004c38 <prvTaskExitError>:
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
8004c38: b480 push {r7}
8004c3a: b085 sub sp, #20
8004c3c: af00 add r7, sp, #0
volatile uint32_t ulDummy = 0;
8004c3e: 2300 movs r3, #0
8004c40: 607b str r3, [r7, #4]
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
8004c42: 4b12 ldr r3, [pc, #72] ; (8004c8c <prvTaskExitError+0x54>)
8004c44: 681b ldr r3, [r3, #0]
8004c46: f1b3 3fff cmp.w r3, #4294967295
8004c4a: d00a beq.n 8004c62 <prvTaskExitError+0x2a>
__asm volatile
8004c4c: f04f 0350 mov.w r3, #80 ; 0x50
8004c50: f383 8811 msr BASEPRI, r3
8004c54: f3bf 8f6f isb sy
8004c58: f3bf 8f4f dsb sy
8004c5c: 60fb str r3, [r7, #12]
}
8004c5e: bf00 nop
8004c60: e7fe b.n 8004c60 <prvTaskExitError+0x28>
__asm volatile
8004c62: f04f 0350 mov.w r3, #80 ; 0x50
8004c66: f383 8811 msr BASEPRI, r3
8004c6a: f3bf 8f6f isb sy
8004c6e: f3bf 8f4f dsb sy
8004c72: 60bb str r3, [r7, #8]
}
8004c74: bf00 nop
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
8004c76: bf00 nop
8004c78: 687b ldr r3, [r7, #4]
8004c7a: 2b00 cmp r3, #0
8004c7c: d0fc beq.n 8004c78 <prvTaskExitError+0x40>
about code appearing after this function is called - making ulDummy
volatile makes the compiler think the function could return and
therefore not output an 'unreachable code' warning for code that appears
after it. */
}
}
8004c7e: bf00 nop
8004c80: bf00 nop
8004c82: 3714 adds r7, #20
8004c84: 46bd mov sp, r7
8004c86: f85d 7b04 ldr.w r7, [sp], #4
8004c8a: 4770 bx lr
8004c8c: 2000000c .word 0x2000000c
08004c90 <SVC_Handler>:
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
8004c90: 4b07 ldr r3, [pc, #28] ; (8004cb0 <pxCurrentTCBConst2>)
8004c92: 6819 ldr r1, [r3, #0]
8004c94: 6808 ldr r0, [r1, #0]
8004c96: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004c9a: f380 8809 msr PSP, r0
8004c9e: f3bf 8f6f isb sy
8004ca2: f04f 0000 mov.w r0, #0
8004ca6: f380 8811 msr BASEPRI, r0
8004caa: 4770 bx lr
8004cac: f3af 8000 nop.w
08004cb0 <pxCurrentTCBConst2>:
8004cb0: 200008c0 .word 0x200008c0
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
8004cb4: bf00 nop
8004cb6: bf00 nop
08004cb8 <prvPortStartFirstTask>:
{
/* Start the first task. This also clears the bit that indicates the FPU is
in use in case the FPU was used before the scheduler was started - which
would otherwise result in the unnecessary leaving of space in the SVC stack
for lazy saving of FPU registers. */
__asm volatile(
8004cb8: 4808 ldr r0, [pc, #32] ; (8004cdc <prvPortStartFirstTask+0x24>)
8004cba: 6800 ldr r0, [r0, #0]
8004cbc: 6800 ldr r0, [r0, #0]
8004cbe: f380 8808 msr MSP, r0
8004cc2: f04f 0000 mov.w r0, #0
8004cc6: f380 8814 msr CONTROL, r0
8004cca: b662 cpsie i
8004ccc: b661 cpsie f
8004cce: f3bf 8f4f dsb sy
8004cd2: f3bf 8f6f isb sy
8004cd6: df00 svc 0
8004cd8: bf00 nop
" dsb \n"
" isb \n"
" svc 0 \n" /* System call to start first task. */
" nop \n"
);
}
8004cda: bf00 nop
8004cdc: e000ed08 .word 0xe000ed08
08004ce0 <xPortStartScheduler>:
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
8004ce0: b580 push {r7, lr}
8004ce2: b086 sub sp, #24
8004ce4: af00 add r7, sp, #0
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
/* This port can be used on all revisions of the Cortex-M7 core other than
the r0p1 parts. r0p1 parts should use the port from the
/source/portable/GCC/ARM_CM7/r0p1 directory. */
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
8004ce6: 4b46 ldr r3, [pc, #280] ; (8004e00 <xPortStartScheduler+0x120>)
8004ce8: 681b ldr r3, [r3, #0]
8004cea: 4a46 ldr r2, [pc, #280] ; (8004e04 <xPortStartScheduler+0x124>)
8004cec: 4293 cmp r3, r2
8004cee: d10a bne.n 8004d06 <xPortStartScheduler+0x26>
__asm volatile
8004cf0: f04f 0350 mov.w r3, #80 ; 0x50
8004cf4: f383 8811 msr BASEPRI, r3
8004cf8: f3bf 8f6f isb sy
8004cfc: f3bf 8f4f dsb sy
8004d00: 613b str r3, [r7, #16]
}
8004d02: bf00 nop
8004d04: e7fe b.n 8004d04 <xPortStartScheduler+0x24>
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
8004d06: 4b3e ldr r3, [pc, #248] ; (8004e00 <xPortStartScheduler+0x120>)
8004d08: 681b ldr r3, [r3, #0]
8004d0a: 4a3f ldr r2, [pc, #252] ; (8004e08 <xPortStartScheduler+0x128>)
8004d0c: 4293 cmp r3, r2
8004d0e: d10a bne.n 8004d26 <xPortStartScheduler+0x46>
__asm volatile
8004d10: f04f 0350 mov.w r3, #80 ; 0x50
8004d14: f383 8811 msr BASEPRI, r3
8004d18: f3bf 8f6f isb sy
8004d1c: f3bf 8f4f dsb sy
8004d20: 60fb str r3, [r7, #12]
}
8004d22: bf00 nop
8004d24: e7fe b.n 8004d24 <xPortStartScheduler+0x44>
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
8004d26: 4b39 ldr r3, [pc, #228] ; (8004e0c <xPortStartScheduler+0x12c>)
8004d28: 617b str r3, [r7, #20]
functions can be called. ISR safe functions are those that end in
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
ensure interrupt entry is as fast and simple as possible.
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
8004d2a: 697b ldr r3, [r7, #20]
8004d2c: 781b ldrb r3, [r3, #0]
8004d2e: b2db uxtb r3, r3
8004d30: 607b str r3, [r7, #4]
/* Determine the number of priority bits available. First write to all
possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
8004d32: 697b ldr r3, [r7, #20]
8004d34: 22ff movs r2, #255 ; 0xff
8004d36: 701a strb r2, [r3, #0]
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
8004d38: 697b ldr r3, [r7, #20]
8004d3a: 781b ldrb r3, [r3, #0]
8004d3c: b2db uxtb r3, r3
8004d3e: 70fb strb r3, [r7, #3]
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
8004d40: 78fb ldrb r3, [r7, #3]
8004d42: b2db uxtb r3, r3
8004d44: f003 0350 and.w r3, r3, #80 ; 0x50
8004d48: b2da uxtb r2, r3
8004d4a: 4b31 ldr r3, [pc, #196] ; (8004e10 <xPortStartScheduler+0x130>)
8004d4c: 701a strb r2, [r3, #0]
/* Calculate the maximum acceptable priority group value for the number
of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
8004d4e: 4b31 ldr r3, [pc, #196] ; (8004e14 <xPortStartScheduler+0x134>)
8004d50: 2207 movs r2, #7
8004d52: 601a str r2, [r3, #0]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
8004d54: e009 b.n 8004d6a <xPortStartScheduler+0x8a>
{
ulMaxPRIGROUPValue--;
8004d56: 4b2f ldr r3, [pc, #188] ; (8004e14 <xPortStartScheduler+0x134>)
8004d58: 681b ldr r3, [r3, #0]
8004d5a: 3b01 subs r3, #1
8004d5c: 4a2d ldr r2, [pc, #180] ; (8004e14 <xPortStartScheduler+0x134>)
8004d5e: 6013 str r3, [r2, #0]
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
8004d60: 78fb ldrb r3, [r7, #3]
8004d62: b2db uxtb r3, r3
8004d64: 005b lsls r3, r3, #1
8004d66: b2db uxtb r3, r3
8004d68: 70fb strb r3, [r7, #3]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
8004d6a: 78fb ldrb r3, [r7, #3]
8004d6c: b2db uxtb r3, r3
8004d6e: f003 0380 and.w r3, r3, #128 ; 0x80
8004d72: 2b80 cmp r3, #128 ; 0x80
8004d74: d0ef beq.n 8004d56 <xPortStartScheduler+0x76>
#ifdef configPRIO_BITS
{
/* Check the FreeRTOS configuration that defines the number of
priority bits matches the number of priority bits actually queried
from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
8004d76: 4b27 ldr r3, [pc, #156] ; (8004e14 <xPortStartScheduler+0x134>)
8004d78: 681b ldr r3, [r3, #0]
8004d7a: f1c3 0307 rsb r3, r3, #7
8004d7e: 2b04 cmp r3, #4
8004d80: d00a beq.n 8004d98 <xPortStartScheduler+0xb8>
__asm volatile
8004d82: f04f 0350 mov.w r3, #80 ; 0x50
8004d86: f383 8811 msr BASEPRI, r3
8004d8a: f3bf 8f6f isb sy
8004d8e: f3bf 8f4f dsb sy
8004d92: 60bb str r3, [r7, #8]
}
8004d94: bf00 nop
8004d96: e7fe b.n 8004d96 <xPortStartScheduler+0xb6>
}
#endif
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
8004d98: 4b1e ldr r3, [pc, #120] ; (8004e14 <xPortStartScheduler+0x134>)
8004d9a: 681b ldr r3, [r3, #0]
8004d9c: 021b lsls r3, r3, #8
8004d9e: 4a1d ldr r2, [pc, #116] ; (8004e14 <xPortStartScheduler+0x134>)
8004da0: 6013 str r3, [r2, #0]
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
8004da2: 4b1c ldr r3, [pc, #112] ; (8004e14 <xPortStartScheduler+0x134>)
8004da4: 681b ldr r3, [r3, #0]
8004da6: f403 63e0 and.w r3, r3, #1792 ; 0x700
8004daa: 4a1a ldr r2, [pc, #104] ; (8004e14 <xPortStartScheduler+0x134>)
8004dac: 6013 str r3, [r2, #0]
/* Restore the clobbered interrupt priority register to its original
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
8004dae: 687b ldr r3, [r7, #4]
8004db0: b2da uxtb r2, r3
8004db2: 697b ldr r3, [r7, #20]
8004db4: 701a strb r2, [r3, #0]
}
#endif /* conifgASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
8004db6: 4b18 ldr r3, [pc, #96] ; (8004e18 <xPortStartScheduler+0x138>)
8004db8: 681b ldr r3, [r3, #0]
8004dba: 4a17 ldr r2, [pc, #92] ; (8004e18 <xPortStartScheduler+0x138>)
8004dbc: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8004dc0: 6013 str r3, [r2, #0]
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
8004dc2: 4b15 ldr r3, [pc, #84] ; (8004e18 <xPortStartScheduler+0x138>)
8004dc4: 681b ldr r3, [r3, #0]
8004dc6: 4a14 ldr r2, [pc, #80] ; (8004e18 <xPortStartScheduler+0x138>)
8004dc8: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000
8004dcc: 6013 str r3, [r2, #0]
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
vPortSetupTimerInterrupt();
8004dce: f000 f8dd bl 8004f8c <vPortSetupTimerInterrupt>
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
8004dd2: 4b12 ldr r3, [pc, #72] ; (8004e1c <xPortStartScheduler+0x13c>)
8004dd4: 2200 movs r2, #0
8004dd6: 601a str r2, [r3, #0]
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
8004dd8: f000 f8fc bl 8004fd4 <vPortEnableVFP>
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
8004ddc: 4b10 ldr r3, [pc, #64] ; (8004e20 <xPortStartScheduler+0x140>)
8004dde: 681b ldr r3, [r3, #0]
8004de0: 4a0f ldr r2, [pc, #60] ; (8004e20 <xPortStartScheduler+0x140>)
8004de2: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000
8004de6: 6013 str r3, [r2, #0]
/* Start the first task. */
prvPortStartFirstTask();
8004de8: f7ff ff66 bl 8004cb8 <prvPortStartFirstTask>
exit error function to prevent compiler warnings about a static function
not being called in the case that the application writer overrides this
functionality by defining configTASK_RETURN_ADDRESS. Call
vTaskSwitchContext() so link time optimisation does not remove the
symbol. */
vTaskSwitchContext();
8004dec: f7ff f84c bl 8003e88 <vTaskSwitchContext>
prvTaskExitError();
8004df0: f7ff ff22 bl 8004c38 <prvTaskExitError>
/* Should not get here! */
return 0;
8004df4: 2300 movs r3, #0
}
8004df6: 4618 mov r0, r3
8004df8: 3718 adds r7, #24
8004dfa: 46bd mov sp, r7
8004dfc: bd80 pop {r7, pc}
8004dfe: bf00 nop
8004e00: e000ed00 .word 0xe000ed00
8004e04: 410fc271 .word 0x410fc271
8004e08: 410fc270 .word 0x410fc270
8004e0c: e000e400 .word 0xe000e400
8004e10: 20000eec .word 0x20000eec
8004e14: 20000ef0 .word 0x20000ef0
8004e18: e000ed20 .word 0xe000ed20
8004e1c: 2000000c .word 0x2000000c
8004e20: e000ef34 .word 0xe000ef34
08004e24 <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
8004e24: b480 push {r7}
8004e26: b083 sub sp, #12
8004e28: af00 add r7, sp, #0
__asm volatile
8004e2a: f04f 0350 mov.w r3, #80 ; 0x50
8004e2e: f383 8811 msr BASEPRI, r3
8004e32: f3bf 8f6f isb sy
8004e36: f3bf 8f4f dsb sy
8004e3a: 607b str r3, [r7, #4]
}
8004e3c: bf00 nop
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
8004e3e: 4b0f ldr r3, [pc, #60] ; (8004e7c <vPortEnterCritical+0x58>)
8004e40: 681b ldr r3, [r3, #0]
8004e42: 3301 adds r3, #1
8004e44: 4a0d ldr r2, [pc, #52] ; (8004e7c <vPortEnterCritical+0x58>)
8004e46: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
8004e48: 4b0c ldr r3, [pc, #48] ; (8004e7c <vPortEnterCritical+0x58>)
8004e4a: 681b ldr r3, [r3, #0]
8004e4c: 2b01 cmp r3, #1
8004e4e: d10f bne.n 8004e70 <vPortEnterCritical+0x4c>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
8004e50: 4b0b ldr r3, [pc, #44] ; (8004e80 <vPortEnterCritical+0x5c>)
8004e52: 681b ldr r3, [r3, #0]
8004e54: b2db uxtb r3, r3
8004e56: 2b00 cmp r3, #0
8004e58: d00a beq.n 8004e70 <vPortEnterCritical+0x4c>
__asm volatile
8004e5a: f04f 0350 mov.w r3, #80 ; 0x50
8004e5e: f383 8811 msr BASEPRI, r3
8004e62: f3bf 8f6f isb sy
8004e66: f3bf 8f4f dsb sy
8004e6a: 603b str r3, [r7, #0]
}
8004e6c: bf00 nop
8004e6e: e7fe b.n 8004e6e <vPortEnterCritical+0x4a>
}
}
8004e70: bf00 nop
8004e72: 370c adds r7, #12
8004e74: 46bd mov sp, r7
8004e76: f85d 7b04 ldr.w r7, [sp], #4
8004e7a: 4770 bx lr
8004e7c: 2000000c .word 0x2000000c
8004e80: e000ed04 .word 0xe000ed04
08004e84 <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
8004e84: b480 push {r7}
8004e86: b083 sub sp, #12
8004e88: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
8004e8a: 4b12 ldr r3, [pc, #72] ; (8004ed4 <vPortExitCritical+0x50>)
8004e8c: 681b ldr r3, [r3, #0]
8004e8e: 2b00 cmp r3, #0
8004e90: d10a bne.n 8004ea8 <vPortExitCritical+0x24>
__asm volatile
8004e92: f04f 0350 mov.w r3, #80 ; 0x50
8004e96: f383 8811 msr BASEPRI, r3
8004e9a: f3bf 8f6f isb sy
8004e9e: f3bf 8f4f dsb sy
8004ea2: 607b str r3, [r7, #4]
}
8004ea4: bf00 nop
8004ea6: e7fe b.n 8004ea6 <vPortExitCritical+0x22>
uxCriticalNesting--;
8004ea8: 4b0a ldr r3, [pc, #40] ; (8004ed4 <vPortExitCritical+0x50>)
8004eaa: 681b ldr r3, [r3, #0]
8004eac: 3b01 subs r3, #1
8004eae: 4a09 ldr r2, [pc, #36] ; (8004ed4 <vPortExitCritical+0x50>)
8004eb0: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
8004eb2: 4b08 ldr r3, [pc, #32] ; (8004ed4 <vPortExitCritical+0x50>)
8004eb4: 681b ldr r3, [r3, #0]
8004eb6: 2b00 cmp r3, #0
8004eb8: d105 bne.n 8004ec6 <vPortExitCritical+0x42>
8004eba: 2300 movs r3, #0
8004ebc: 603b str r3, [r7, #0]
__asm volatile
8004ebe: 683b ldr r3, [r7, #0]
8004ec0: f383 8811 msr BASEPRI, r3
}
8004ec4: bf00 nop
{
portENABLE_INTERRUPTS();
}
}
8004ec6: bf00 nop
8004ec8: 370c adds r7, #12
8004eca: 46bd mov sp, r7
8004ecc: f85d 7b04 ldr.w r7, [sp], #4
8004ed0: 4770 bx lr
8004ed2: bf00 nop
8004ed4: 2000000c .word 0x2000000c
...
08004ee0 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
8004ee0: f3ef 8009 mrs r0, PSP
8004ee4: f3bf 8f6f isb sy
8004ee8: 4b15 ldr r3, [pc, #84] ; (8004f40 <pxCurrentTCBConst>)
8004eea: 681a ldr r2, [r3, #0]
8004eec: f01e 0f10 tst.w lr, #16
8004ef0: bf08 it eq
8004ef2: ed20 8a10 vstmdbeq r0!, {s16-s31}
8004ef6: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004efa: 6010 str r0, [r2, #0]
8004efc: e92d 0009 stmdb sp!, {r0, r3}
8004f00: f04f 0050 mov.w r0, #80 ; 0x50
8004f04: f380 8811 msr BASEPRI, r0
8004f08: f3bf 8f4f dsb sy
8004f0c: f3bf 8f6f isb sy
8004f10: f7fe ffba bl 8003e88 <vTaskSwitchContext>
8004f14: f04f 0000 mov.w r0, #0
8004f18: f380 8811 msr BASEPRI, r0
8004f1c: bc09 pop {r0, r3}
8004f1e: 6819 ldr r1, [r3, #0]
8004f20: 6808 ldr r0, [r1, #0]
8004f22: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004f26: f01e 0f10 tst.w lr, #16
8004f2a: bf08 it eq
8004f2c: ecb0 8a10 vldmiaeq r0!, {s16-s31}
8004f30: f380 8809 msr PSP, r0
8004f34: f3bf 8f6f isb sy
8004f38: 4770 bx lr
8004f3a: bf00 nop
8004f3c: f3af 8000 nop.w
08004f40 <pxCurrentTCBConst>:
8004f40: 200008c0 .word 0x200008c0
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
8004f44: bf00 nop
8004f46: bf00 nop
08004f48 <xPortSysTickHandler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
8004f48: b580 push {r7, lr}
8004f4a: b082 sub sp, #8
8004f4c: af00 add r7, sp, #0
__asm volatile
8004f4e: f04f 0350 mov.w r3, #80 ; 0x50
8004f52: f383 8811 msr BASEPRI, r3
8004f56: f3bf 8f6f isb sy
8004f5a: f3bf 8f4f dsb sy
8004f5e: 607b str r3, [r7, #4]
}
8004f60: bf00 nop
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
8004f62: f7fe fed7 bl 8003d14 <xTaskIncrementTick>
8004f66: 4603 mov r3, r0
8004f68: 2b00 cmp r3, #0
8004f6a: d003 beq.n 8004f74 <xPortSysTickHandler+0x2c>
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
8004f6c: 4b06 ldr r3, [pc, #24] ; (8004f88 <xPortSysTickHandler+0x40>)
8004f6e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8004f72: 601a str r2, [r3, #0]
8004f74: 2300 movs r3, #0
8004f76: 603b str r3, [r7, #0]
__asm volatile
8004f78: 683b ldr r3, [r7, #0]
8004f7a: f383 8811 msr BASEPRI, r3
}
8004f7e: bf00 nop
}
}
portENABLE_INTERRUPTS();
}
8004f80: bf00 nop
8004f82: 3708 adds r7, #8
8004f84: 46bd mov sp, r7
8004f86: bd80 pop {r7, pc}
8004f88: e000ed04 .word 0xe000ed04
08004f8c <vPortSetupTimerInterrupt>:
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
8004f8c: b480 push {r7}
8004f8e: af00 add r7, sp, #0
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
8004f90: 4b0b ldr r3, [pc, #44] ; (8004fc0 <vPortSetupTimerInterrupt+0x34>)
8004f92: 2200 movs r2, #0
8004f94: 601a str r2, [r3, #0]
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
8004f96: 4b0b ldr r3, [pc, #44] ; (8004fc4 <vPortSetupTimerInterrupt+0x38>)
8004f98: 2200 movs r2, #0
8004f9a: 601a str r2, [r3, #0]
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
8004f9c: 4b0a ldr r3, [pc, #40] ; (8004fc8 <vPortSetupTimerInterrupt+0x3c>)
8004f9e: 681b ldr r3, [r3, #0]
8004fa0: 4a0a ldr r2, [pc, #40] ; (8004fcc <vPortSetupTimerInterrupt+0x40>)
8004fa2: fba2 2303 umull r2, r3, r2, r3
8004fa6: 099b lsrs r3, r3, #6
8004fa8: 4a09 ldr r2, [pc, #36] ; (8004fd0 <vPortSetupTimerInterrupt+0x44>)
8004faa: 3b01 subs r3, #1
8004fac: 6013 str r3, [r2, #0]
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
8004fae: 4b04 ldr r3, [pc, #16] ; (8004fc0 <vPortSetupTimerInterrupt+0x34>)
8004fb0: 2207 movs r2, #7
8004fb2: 601a str r2, [r3, #0]
}
8004fb4: bf00 nop
8004fb6: 46bd mov sp, r7
8004fb8: f85d 7b04 ldr.w r7, [sp], #4
8004fbc: 4770 bx lr
8004fbe: bf00 nop
8004fc0: e000e010 .word 0xe000e010
8004fc4: e000e018 .word 0xe000e018
8004fc8: 20000000 .word 0x20000000
8004fcc: 10624dd3 .word 0x10624dd3
8004fd0: e000e014 .word 0xe000e014
08004fd4 <vPortEnableVFP>:
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm volatile
8004fd4: f8df 000c ldr.w r0, [pc, #12] ; 8004fe4 <vPortEnableVFP+0x10>
8004fd8: 6801 ldr r1, [r0, #0]
8004fda: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
8004fde: 6001 str r1, [r0, #0]
8004fe0: 4770 bx lr
" \n"
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n"
" bx r14 "
);
}
8004fe2: bf00 nop
8004fe4: e000ed88 .word 0xe000ed88
08004fe8 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
8004fe8: b480 push {r7}
8004fea: b085 sub sp, #20
8004fec: af00 add r7, sp, #0
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
8004fee: f3ef 8305 mrs r3, IPSR
8004ff2: 60fb str r3, [r7, #12]
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
8004ff4: 68fb ldr r3, [r7, #12]
8004ff6: 2b0f cmp r3, #15
8004ff8: d914 bls.n 8005024 <vPortValidateInterruptPriority+0x3c>
{
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
8004ffa: 4a17 ldr r2, [pc, #92] ; (8005058 <vPortValidateInterruptPriority+0x70>)
8004ffc: 68fb ldr r3, [r7, #12]
8004ffe: 4413 add r3, r2
8005000: 781b ldrb r3, [r3, #0]
8005002: 72fb strb r3, [r7, #11]
interrupt entry is as fast and simple as possible.
The following links provide detailed information:
http://www.freertos.org/RTOS-Cortex-M3-M4.html
http://www.freertos.org/FAQHelp.html */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
8005004: 4b15 ldr r3, [pc, #84] ; (800505c <vPortValidateInterruptPriority+0x74>)
8005006: 781b ldrb r3, [r3, #0]
8005008: 7afa ldrb r2, [r7, #11]
800500a: 429a cmp r2, r3
800500c: d20a bcs.n 8005024 <vPortValidateInterruptPriority+0x3c>
__asm volatile
800500e: f04f 0350 mov.w r3, #80 ; 0x50
8005012: f383 8811 msr BASEPRI, r3
8005016: f3bf 8f6f isb sy
800501a: f3bf 8f4f dsb sy
800501e: 607b str r3, [r7, #4]
}
8005020: bf00 nop
8005022: e7fe b.n 8005022 <vPortValidateInterruptPriority+0x3a>
configuration then the correct setting can be achieved on all Cortex-M
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
8005024: 4b0e ldr r3, [pc, #56] ; (8005060 <vPortValidateInterruptPriority+0x78>)
8005026: 681b ldr r3, [r3, #0]
8005028: f403 62e0 and.w r2, r3, #1792 ; 0x700
800502c: 4b0d ldr r3, [pc, #52] ; (8005064 <vPortValidateInterruptPriority+0x7c>)
800502e: 681b ldr r3, [r3, #0]
8005030: 429a cmp r2, r3
8005032: d90a bls.n 800504a <vPortValidateInterruptPriority+0x62>
__asm volatile
8005034: f04f 0350 mov.w r3, #80 ; 0x50
8005038: f383 8811 msr BASEPRI, r3
800503c: f3bf 8f6f isb sy
8005040: f3bf 8f4f dsb sy
8005044: 603b str r3, [r7, #0]
}
8005046: bf00 nop
8005048: e7fe b.n 8005048 <vPortValidateInterruptPriority+0x60>
}
800504a: bf00 nop
800504c: 3714 adds r7, #20
800504e: 46bd mov sp, r7
8005050: f85d 7b04 ldr.w r7, [sp], #4
8005054: 4770 bx lr
8005056: bf00 nop
8005058: e000e3f0 .word 0xe000e3f0
800505c: 20000eec .word 0x20000eec
8005060: e000ed0c .word 0xe000ed0c
8005064: 20000ef0 .word 0x20000ef0
08005068 <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc( size_t xWantedSize )
{
8005068: b580 push {r7, lr}
800506a: b08a sub sp, #40 ; 0x28
800506c: af00 add r7, sp, #0
800506e: 6078 str r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
8005070: 2300 movs r3, #0
8005072: 61fb str r3, [r7, #28]
vTaskSuspendAll();
8005074: f7fe fd92 bl 8003b9c <vTaskSuspendAll>
{
/* If this is the first call to malloc then the heap will require
initialisation to setup the list of free blocks. */
if( pxEnd == NULL )
8005078: 4b5b ldr r3, [pc, #364] ; (80051e8 <pvPortMalloc+0x180>)
800507a: 681b ldr r3, [r3, #0]
800507c: 2b00 cmp r3, #0
800507e: d101 bne.n 8005084 <pvPortMalloc+0x1c>
{
prvHeapInit();
8005080: f000 f920 bl 80052c4 <prvHeapInit>
/* Check the requested block size is not so large that the top bit is
set. The top bit of the block size member of the BlockLink_t structure
is used to determine who owns the block - the application or the
kernel, so it must be free. */
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
8005084: 4b59 ldr r3, [pc, #356] ; (80051ec <pvPortMalloc+0x184>)
8005086: 681a ldr r2, [r3, #0]
8005088: 687b ldr r3, [r7, #4]
800508a: 4013 ands r3, r2
800508c: 2b00 cmp r3, #0
800508e: f040 8093 bne.w 80051b8 <pvPortMalloc+0x150>
{
/* The wanted size is increased so it can contain a BlockLink_t
structure in addition to the requested amount of bytes. */
if( xWantedSize > 0 )
8005092: 687b ldr r3, [r7, #4]
8005094: 2b00 cmp r3, #0
8005096: d01d beq.n 80050d4 <pvPortMalloc+0x6c>
{
xWantedSize += xHeapStructSize;
8005098: 2208 movs r2, #8
800509a: 687b ldr r3, [r7, #4]
800509c: 4413 add r3, r2
800509e: 607b str r3, [r7, #4]
/* Ensure that blocks are always aligned to the required number
of bytes. */
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
80050a0: 687b ldr r3, [r7, #4]
80050a2: f003 0307 and.w r3, r3, #7
80050a6: 2b00 cmp r3, #0
80050a8: d014 beq.n 80050d4 <pvPortMalloc+0x6c>
{
/* Byte alignment required. */
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
80050aa: 687b ldr r3, [r7, #4]
80050ac: f023 0307 bic.w r3, r3, #7
80050b0: 3308 adds r3, #8
80050b2: 607b str r3, [r7, #4]
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
80050b4: 687b ldr r3, [r7, #4]
80050b6: f003 0307 and.w r3, r3, #7
80050ba: 2b00 cmp r3, #0
80050bc: d00a beq.n 80050d4 <pvPortMalloc+0x6c>
__asm volatile
80050be: f04f 0350 mov.w r3, #80 ; 0x50
80050c2: f383 8811 msr BASEPRI, r3
80050c6: f3bf 8f6f isb sy
80050ca: f3bf 8f4f dsb sy
80050ce: 617b str r3, [r7, #20]
}
80050d0: bf00 nop
80050d2: e7fe b.n 80050d2 <pvPortMalloc+0x6a>
else
{
mtCOVERAGE_TEST_MARKER();
}
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
80050d4: 687b ldr r3, [r7, #4]
80050d6: 2b00 cmp r3, #0
80050d8: d06e beq.n 80051b8 <pvPortMalloc+0x150>
80050da: 4b45 ldr r3, [pc, #276] ; (80051f0 <pvPortMalloc+0x188>)
80050dc: 681b ldr r3, [r3, #0]
80050de: 687a ldr r2, [r7, #4]
80050e0: 429a cmp r2, r3
80050e2: d869 bhi.n 80051b8 <pvPortMalloc+0x150>
{
/* Traverse the list from the start (lowest address) block until
one of adequate size is found. */
pxPreviousBlock = &xStart;
80050e4: 4b43 ldr r3, [pc, #268] ; (80051f4 <pvPortMalloc+0x18c>)
80050e6: 623b str r3, [r7, #32]
pxBlock = xStart.pxNextFreeBlock;
80050e8: 4b42 ldr r3, [pc, #264] ; (80051f4 <pvPortMalloc+0x18c>)
80050ea: 681b ldr r3, [r3, #0]
80050ec: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
80050ee: e004 b.n 80050fa <pvPortMalloc+0x92>
{
pxPreviousBlock = pxBlock;
80050f0: 6a7b ldr r3, [r7, #36] ; 0x24
80050f2: 623b str r3, [r7, #32]
pxBlock = pxBlock->pxNextFreeBlock;
80050f4: 6a7b ldr r3, [r7, #36] ; 0x24
80050f6: 681b ldr r3, [r3, #0]
80050f8: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
80050fa: 6a7b ldr r3, [r7, #36] ; 0x24
80050fc: 685b ldr r3, [r3, #4]
80050fe: 687a ldr r2, [r7, #4]
8005100: 429a cmp r2, r3
8005102: d903 bls.n 800510c <pvPortMalloc+0xa4>
8005104: 6a7b ldr r3, [r7, #36] ; 0x24
8005106: 681b ldr r3, [r3, #0]
8005108: 2b00 cmp r3, #0
800510a: d1f1 bne.n 80050f0 <pvPortMalloc+0x88>
}
/* If the end marker was reached then a block of adequate size
was not found. */
if( pxBlock != pxEnd )
800510c: 4b36 ldr r3, [pc, #216] ; (80051e8 <pvPortMalloc+0x180>)
800510e: 681b ldr r3, [r3, #0]
8005110: 6a7a ldr r2, [r7, #36] ; 0x24
8005112: 429a cmp r2, r3
8005114: d050 beq.n 80051b8 <pvPortMalloc+0x150>
{
/* Return the memory space pointed to - jumping over the
BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
8005116: 6a3b ldr r3, [r7, #32]
8005118: 681b ldr r3, [r3, #0]
800511a: 2208 movs r2, #8
800511c: 4413 add r3, r2
800511e: 61fb str r3, [r7, #28]
/* This block is being returned for use so must be taken out
of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
8005120: 6a7b ldr r3, [r7, #36] ; 0x24
8005122: 681a ldr r2, [r3, #0]
8005124: 6a3b ldr r3, [r7, #32]
8005126: 601a str r2, [r3, #0]
/* If the block is larger than required it can be split into
two. */
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
8005128: 6a7b ldr r3, [r7, #36] ; 0x24
800512a: 685a ldr r2, [r3, #4]
800512c: 687b ldr r3, [r7, #4]
800512e: 1ad2 subs r2, r2, r3
8005130: 2308 movs r3, #8
8005132: 005b lsls r3, r3, #1
8005134: 429a cmp r2, r3
8005136: d91f bls.n 8005178 <pvPortMalloc+0x110>
{
/* This block is to be split into two. Create a new
block following the number of bytes requested. The void
cast is used to prevent byte alignment warnings from the
compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
8005138: 6a7a ldr r2, [r7, #36] ; 0x24
800513a: 687b ldr r3, [r7, #4]
800513c: 4413 add r3, r2
800513e: 61bb str r3, [r7, #24]
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
8005140: 69bb ldr r3, [r7, #24]
8005142: f003 0307 and.w r3, r3, #7
8005146: 2b00 cmp r3, #0
8005148: d00a beq.n 8005160 <pvPortMalloc+0xf8>
__asm volatile
800514a: f04f 0350 mov.w r3, #80 ; 0x50
800514e: f383 8811 msr BASEPRI, r3
8005152: f3bf 8f6f isb sy
8005156: f3bf 8f4f dsb sy
800515a: 613b str r3, [r7, #16]
}
800515c: bf00 nop
800515e: e7fe b.n 800515e <pvPortMalloc+0xf6>
/* Calculate the sizes of two blocks split from the
single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
8005160: 6a7b ldr r3, [r7, #36] ; 0x24
8005162: 685a ldr r2, [r3, #4]
8005164: 687b ldr r3, [r7, #4]
8005166: 1ad2 subs r2, r2, r3
8005168: 69bb ldr r3, [r7, #24]
800516a: 605a str r2, [r3, #4]
pxBlock->xBlockSize = xWantedSize;
800516c: 6a7b ldr r3, [r7, #36] ; 0x24
800516e: 687a ldr r2, [r7, #4]
8005170: 605a str r2, [r3, #4]
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
8005172: 69b8 ldr r0, [r7, #24]
8005174: f000 f908 bl 8005388 <prvInsertBlockIntoFreeList>
else
{
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
8005178: 4b1d ldr r3, [pc, #116] ; (80051f0 <pvPortMalloc+0x188>)
800517a: 681a ldr r2, [r3, #0]
800517c: 6a7b ldr r3, [r7, #36] ; 0x24
800517e: 685b ldr r3, [r3, #4]
8005180: 1ad3 subs r3, r2, r3
8005182: 4a1b ldr r2, [pc, #108] ; (80051f0 <pvPortMalloc+0x188>)
8005184: 6013 str r3, [r2, #0]
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
8005186: 4b1a ldr r3, [pc, #104] ; (80051f0 <pvPortMalloc+0x188>)
8005188: 681a ldr r2, [r3, #0]
800518a: 4b1b ldr r3, [pc, #108] ; (80051f8 <pvPortMalloc+0x190>)
800518c: 681b ldr r3, [r3, #0]
800518e: 429a cmp r2, r3
8005190: d203 bcs.n 800519a <pvPortMalloc+0x132>
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
8005192: 4b17 ldr r3, [pc, #92] ; (80051f0 <pvPortMalloc+0x188>)
8005194: 681b ldr r3, [r3, #0]
8005196: 4a18 ldr r2, [pc, #96] ; (80051f8 <pvPortMalloc+0x190>)
8005198: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
/* The block is being returned - it is allocated and owned
by the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
800519a: 6a7b ldr r3, [r7, #36] ; 0x24
800519c: 685a ldr r2, [r3, #4]
800519e: 4b13 ldr r3, [pc, #76] ; (80051ec <pvPortMalloc+0x184>)
80051a0: 681b ldr r3, [r3, #0]
80051a2: 431a orrs r2, r3
80051a4: 6a7b ldr r3, [r7, #36] ; 0x24
80051a6: 605a str r2, [r3, #4]
pxBlock->pxNextFreeBlock = NULL;
80051a8: 6a7b ldr r3, [r7, #36] ; 0x24
80051aa: 2200 movs r2, #0
80051ac: 601a str r2, [r3, #0]
xNumberOfSuccessfulAllocations++;
80051ae: 4b13 ldr r3, [pc, #76] ; (80051fc <pvPortMalloc+0x194>)
80051b0: 681b ldr r3, [r3, #0]
80051b2: 3301 adds r3, #1
80051b4: 4a11 ldr r2, [pc, #68] ; (80051fc <pvPortMalloc+0x194>)
80051b6: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
traceMALLOC( pvReturn, xWantedSize );
}
( void ) xTaskResumeAll();
80051b8: f7fe fcfe bl 8003bb8 <xTaskResumeAll>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
80051bc: 69fb ldr r3, [r7, #28]
80051be: f003 0307 and.w r3, r3, #7
80051c2: 2b00 cmp r3, #0
80051c4: d00a beq.n 80051dc <pvPortMalloc+0x174>
__asm volatile
80051c6: f04f 0350 mov.w r3, #80 ; 0x50
80051ca: f383 8811 msr BASEPRI, r3
80051ce: f3bf 8f6f isb sy
80051d2: f3bf 8f4f dsb sy
80051d6: 60fb str r3, [r7, #12]
}
80051d8: bf00 nop
80051da: e7fe b.n 80051da <pvPortMalloc+0x172>
return pvReturn;
80051dc: 69fb ldr r3, [r7, #28]
}
80051de: 4618 mov r0, r3
80051e0: 3728 adds r7, #40 ; 0x28
80051e2: 46bd mov sp, r7
80051e4: bd80 pop {r7, pc}
80051e6: bf00 nop
80051e8: 20004afc .word 0x20004afc
80051ec: 20004b10 .word 0x20004b10
80051f0: 20004b00 .word 0x20004b00
80051f4: 20004af4 .word 0x20004af4
80051f8: 20004b04 .word 0x20004b04
80051fc: 20004b08 .word 0x20004b08
08005200 <vPortFree>:
/*-----------------------------------------------------------*/
void vPortFree( void *pv )
{
8005200: b580 push {r7, lr}
8005202: b086 sub sp, #24
8005204: af00 add r7, sp, #0
8005206: 6078 str r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
8005208: 687b ldr r3, [r7, #4]
800520a: 617b str r3, [r7, #20]
BlockLink_t *pxLink;
if( pv != NULL )
800520c: 687b ldr r3, [r7, #4]
800520e: 2b00 cmp r3, #0
8005210: d04d beq.n 80052ae <vPortFree+0xae>
{
/* The memory being freed will have an BlockLink_t structure immediately
before it. */
puc -= xHeapStructSize;
8005212: 2308 movs r3, #8
8005214: 425b negs r3, r3
8005216: 697a ldr r2, [r7, #20]
8005218: 4413 add r3, r2
800521a: 617b str r3, [r7, #20]
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
800521c: 697b ldr r3, [r7, #20]
800521e: 613b str r3, [r7, #16]
/* Check the block is actually allocated. */
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
8005220: 693b ldr r3, [r7, #16]
8005222: 685a ldr r2, [r3, #4]
8005224: 4b24 ldr r3, [pc, #144] ; (80052b8 <vPortFree+0xb8>)
8005226: 681b ldr r3, [r3, #0]
8005228: 4013 ands r3, r2
800522a: 2b00 cmp r3, #0
800522c: d10a bne.n 8005244 <vPortFree+0x44>
__asm volatile
800522e: f04f 0350 mov.w r3, #80 ; 0x50
8005232: f383 8811 msr BASEPRI, r3
8005236: f3bf 8f6f isb sy
800523a: f3bf 8f4f dsb sy
800523e: 60fb str r3, [r7, #12]
}
8005240: bf00 nop
8005242: e7fe b.n 8005242 <vPortFree+0x42>
configASSERT( pxLink->pxNextFreeBlock == NULL );
8005244: 693b ldr r3, [r7, #16]
8005246: 681b ldr r3, [r3, #0]
8005248: 2b00 cmp r3, #0
800524a: d00a beq.n 8005262 <vPortFree+0x62>
__asm volatile
800524c: f04f 0350 mov.w r3, #80 ; 0x50
8005250: f383 8811 msr BASEPRI, r3
8005254: f3bf 8f6f isb sy
8005258: f3bf 8f4f dsb sy
800525c: 60bb str r3, [r7, #8]
}
800525e: bf00 nop
8005260: e7fe b.n 8005260 <vPortFree+0x60>
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
8005262: 693b ldr r3, [r7, #16]
8005264: 685a ldr r2, [r3, #4]
8005266: 4b14 ldr r3, [pc, #80] ; (80052b8 <vPortFree+0xb8>)
8005268: 681b ldr r3, [r3, #0]
800526a: 4013 ands r3, r2
800526c: 2b00 cmp r3, #0
800526e: d01e beq.n 80052ae <vPortFree+0xae>
{
if( pxLink->pxNextFreeBlock == NULL )
8005270: 693b ldr r3, [r7, #16]
8005272: 681b ldr r3, [r3, #0]
8005274: 2b00 cmp r3, #0
8005276: d11a bne.n 80052ae <vPortFree+0xae>
{
/* The block is being returned to the heap - it is no longer
allocated. */
pxLink->xBlockSize &= ~xBlockAllocatedBit;
8005278: 693b ldr r3, [r7, #16]
800527a: 685a ldr r2, [r3, #4]
800527c: 4b0e ldr r3, [pc, #56] ; (80052b8 <vPortFree+0xb8>)
800527e: 681b ldr r3, [r3, #0]
8005280: 43db mvns r3, r3
8005282: 401a ands r2, r3
8005284: 693b ldr r3, [r7, #16]
8005286: 605a str r2, [r3, #4]
vTaskSuspendAll();
8005288: f7fe fc88 bl 8003b9c <vTaskSuspendAll>
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
800528c: 693b ldr r3, [r7, #16]
800528e: 685a ldr r2, [r3, #4]
8005290: 4b0a ldr r3, [pc, #40] ; (80052bc <vPortFree+0xbc>)
8005292: 681b ldr r3, [r3, #0]
8005294: 4413 add r3, r2
8005296: 4a09 ldr r2, [pc, #36] ; (80052bc <vPortFree+0xbc>)
8005298: 6013 str r3, [r2, #0]
traceFREE( pv, pxLink->xBlockSize );
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
800529a: 6938 ldr r0, [r7, #16]
800529c: f000 f874 bl 8005388 <prvInsertBlockIntoFreeList>
xNumberOfSuccessfulFrees++;
80052a0: 4b07 ldr r3, [pc, #28] ; (80052c0 <vPortFree+0xc0>)
80052a2: 681b ldr r3, [r3, #0]
80052a4: 3301 adds r3, #1
80052a6: 4a06 ldr r2, [pc, #24] ; (80052c0 <vPortFree+0xc0>)
80052a8: 6013 str r3, [r2, #0]
}
( void ) xTaskResumeAll();
80052aa: f7fe fc85 bl 8003bb8 <xTaskResumeAll>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
80052ae: bf00 nop
80052b0: 3718 adds r7, #24
80052b2: 46bd mov sp, r7
80052b4: bd80 pop {r7, pc}
80052b6: bf00 nop
80052b8: 20004b10 .word 0x20004b10
80052bc: 20004b00 .word 0x20004b00
80052c0: 20004b0c .word 0x20004b0c
080052c4 <prvHeapInit>:
/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
80052c4: b480 push {r7}
80052c6: b085 sub sp, #20
80052c8: af00 add r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
80052ca: f44f 5370 mov.w r3, #15360 ; 0x3c00
80052ce: 60bb str r3, [r7, #8]
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
80052d0: 4b27 ldr r3, [pc, #156] ; (8005370 <prvHeapInit+0xac>)
80052d2: 60fb str r3, [r7, #12]
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
80052d4: 68fb ldr r3, [r7, #12]
80052d6: f003 0307 and.w r3, r3, #7
80052da: 2b00 cmp r3, #0
80052dc: d00c beq.n 80052f8 <prvHeapInit+0x34>
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
80052de: 68fb ldr r3, [r7, #12]
80052e0: 3307 adds r3, #7
80052e2: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
80052e4: 68fb ldr r3, [r7, #12]
80052e6: f023 0307 bic.w r3, r3, #7
80052ea: 60fb str r3, [r7, #12]
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
80052ec: 68ba ldr r2, [r7, #8]
80052ee: 68fb ldr r3, [r7, #12]
80052f0: 1ad3 subs r3, r2, r3
80052f2: 4a1f ldr r2, [pc, #124] ; (8005370 <prvHeapInit+0xac>)
80052f4: 4413 add r3, r2
80052f6: 60bb str r3, [r7, #8]
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
80052f8: 68fb ldr r3, [r7, #12]
80052fa: 607b str r3, [r7, #4]
/* xStart is used to hold a pointer to the first item in the list of free
blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
80052fc: 4a1d ldr r2, [pc, #116] ; (8005374 <prvHeapInit+0xb0>)
80052fe: 687b ldr r3, [r7, #4]
8005300: 6013 str r3, [r2, #0]
xStart.xBlockSize = ( size_t ) 0;
8005302: 4b1c ldr r3, [pc, #112] ; (8005374 <prvHeapInit+0xb0>)
8005304: 2200 movs r2, #0
8005306: 605a str r2, [r3, #4]
/* pxEnd is used to mark the end of the list of free blocks and is inserted
at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
8005308: 687b ldr r3, [r7, #4]
800530a: 68ba ldr r2, [r7, #8]
800530c: 4413 add r3, r2
800530e: 60fb str r3, [r7, #12]
uxAddress -= xHeapStructSize;
8005310: 2208 movs r2, #8
8005312: 68fb ldr r3, [r7, #12]
8005314: 1a9b subs r3, r3, r2
8005316: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
8005318: 68fb ldr r3, [r7, #12]
800531a: f023 0307 bic.w r3, r3, #7
800531e: 60fb str r3, [r7, #12]
pxEnd = ( void * ) uxAddress;
8005320: 68fb ldr r3, [r7, #12]
8005322: 4a15 ldr r2, [pc, #84] ; (8005378 <prvHeapInit+0xb4>)
8005324: 6013 str r3, [r2, #0]
pxEnd->xBlockSize = 0;
8005326: 4b14 ldr r3, [pc, #80] ; (8005378 <prvHeapInit+0xb4>)
8005328: 681b ldr r3, [r3, #0]
800532a: 2200 movs r2, #0
800532c: 605a str r2, [r3, #4]
pxEnd->pxNextFreeBlock = NULL;
800532e: 4b12 ldr r3, [pc, #72] ; (8005378 <prvHeapInit+0xb4>)
8005330: 681b ldr r3, [r3, #0]
8005332: 2200 movs r2, #0
8005334: 601a str r2, [r3, #0]
/* To start with there is a single free block that is sized to take up the
entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
8005336: 687b ldr r3, [r7, #4]
8005338: 603b str r3, [r7, #0]
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
800533a: 683b ldr r3, [r7, #0]
800533c: 68fa ldr r2, [r7, #12]
800533e: 1ad2 subs r2, r2, r3
8005340: 683b ldr r3, [r7, #0]
8005342: 605a str r2, [r3, #4]
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
8005344: 4b0c ldr r3, [pc, #48] ; (8005378 <prvHeapInit+0xb4>)
8005346: 681a ldr r2, [r3, #0]
8005348: 683b ldr r3, [r7, #0]
800534a: 601a str r2, [r3, #0]
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800534c: 683b ldr r3, [r7, #0]
800534e: 685b ldr r3, [r3, #4]
8005350: 4a0a ldr r2, [pc, #40] ; (800537c <prvHeapInit+0xb8>)
8005352: 6013 str r3, [r2, #0]
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
8005354: 683b ldr r3, [r7, #0]
8005356: 685b ldr r3, [r3, #4]
8005358: 4a09 ldr r2, [pc, #36] ; (8005380 <prvHeapInit+0xbc>)
800535a: 6013 str r3, [r2, #0]
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
800535c: 4b09 ldr r3, [pc, #36] ; (8005384 <prvHeapInit+0xc0>)
800535e: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
8005362: 601a str r2, [r3, #0]
}
8005364: bf00 nop
8005366: 3714 adds r7, #20
8005368: 46bd mov sp, r7
800536a: f85d 7b04 ldr.w r7, [sp], #4
800536e: 4770 bx lr
8005370: 20000ef4 .word 0x20000ef4
8005374: 20004af4 .word 0x20004af4
8005378: 20004afc .word 0x20004afc
800537c: 20004b04 .word 0x20004b04
8005380: 20004b00 .word 0x20004b00
8005384: 20004b10 .word 0x20004b10
08005388 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
8005388: b480 push {r7}
800538a: b085 sub sp, #20
800538c: af00 add r7, sp, #0
800538e: 6078 str r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;
/* Iterate through the list until a block is found that has a higher address
than the block being inserted. */
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
8005390: 4b28 ldr r3, [pc, #160] ; (8005434 <prvInsertBlockIntoFreeList+0xac>)
8005392: 60fb str r3, [r7, #12]
8005394: e002 b.n 800539c <prvInsertBlockIntoFreeList+0x14>
8005396: 68fb ldr r3, [r7, #12]
8005398: 681b ldr r3, [r3, #0]
800539a: 60fb str r3, [r7, #12]
800539c: 68fb ldr r3, [r7, #12]
800539e: 681b ldr r3, [r3, #0]
80053a0: 687a ldr r2, [r7, #4]
80053a2: 429a cmp r2, r3
80053a4: d8f7 bhi.n 8005396 <prvInsertBlockIntoFreeList+0xe>
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
80053a6: 68fb ldr r3, [r7, #12]
80053a8: 60bb str r3, [r7, #8]
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
80053aa: 68fb ldr r3, [r7, #12]
80053ac: 685b ldr r3, [r3, #4]
80053ae: 68ba ldr r2, [r7, #8]
80053b0: 4413 add r3, r2
80053b2: 687a ldr r2, [r7, #4]
80053b4: 429a cmp r2, r3
80053b6: d108 bne.n 80053ca <prvInsertBlockIntoFreeList+0x42>
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
80053b8: 68fb ldr r3, [r7, #12]
80053ba: 685a ldr r2, [r3, #4]
80053bc: 687b ldr r3, [r7, #4]
80053be: 685b ldr r3, [r3, #4]
80053c0: 441a add r2, r3
80053c2: 68fb ldr r3, [r7, #12]
80053c4: 605a str r2, [r3, #4]
pxBlockToInsert = pxIterator;
80053c6: 68fb ldr r3, [r7, #12]
80053c8: 607b str r3, [r7, #4]
mtCOVERAGE_TEST_MARKER();
}
/* Do the block being inserted, and the block it is being inserted before
make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
80053ca: 687b ldr r3, [r7, #4]
80053cc: 60bb str r3, [r7, #8]
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
80053ce: 687b ldr r3, [r7, #4]
80053d0: 685b ldr r3, [r3, #4]
80053d2: 68ba ldr r2, [r7, #8]
80053d4: 441a add r2, r3
80053d6: 68fb ldr r3, [r7, #12]
80053d8: 681b ldr r3, [r3, #0]
80053da: 429a cmp r2, r3
80053dc: d118 bne.n 8005410 <prvInsertBlockIntoFreeList+0x88>
{
if( pxIterator->pxNextFreeBlock != pxEnd )
80053de: 68fb ldr r3, [r7, #12]
80053e0: 681a ldr r2, [r3, #0]
80053e2: 4b15 ldr r3, [pc, #84] ; (8005438 <prvInsertBlockIntoFreeList+0xb0>)
80053e4: 681b ldr r3, [r3, #0]
80053e6: 429a cmp r2, r3
80053e8: d00d beq.n 8005406 <prvInsertBlockIntoFreeList+0x7e>
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
80053ea: 687b ldr r3, [r7, #4]
80053ec: 685a ldr r2, [r3, #4]
80053ee: 68fb ldr r3, [r7, #12]
80053f0: 681b ldr r3, [r3, #0]
80053f2: 685b ldr r3, [r3, #4]
80053f4: 441a add r2, r3
80053f6: 687b ldr r3, [r7, #4]
80053f8: 605a str r2, [r3, #4]
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
80053fa: 68fb ldr r3, [r7, #12]
80053fc: 681b ldr r3, [r3, #0]
80053fe: 681a ldr r2, [r3, #0]
8005400: 687b ldr r3, [r7, #4]
8005402: 601a str r2, [r3, #0]
8005404: e008 b.n 8005418 <prvInsertBlockIntoFreeList+0x90>
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
8005406: 4b0c ldr r3, [pc, #48] ; (8005438 <prvInsertBlockIntoFreeList+0xb0>)
8005408: 681a ldr r2, [r3, #0]
800540a: 687b ldr r3, [r7, #4]
800540c: 601a str r2, [r3, #0]
800540e: e003 b.n 8005418 <prvInsertBlockIntoFreeList+0x90>
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
8005410: 68fb ldr r3, [r7, #12]
8005412: 681a ldr r2, [r3, #0]
8005414: 687b ldr r3, [r7, #4]
8005416: 601a str r2, [r3, #0]
/* If the block being inserted plugged a gab, so was merged with the block
before and the block after, then it's pxNextFreeBlock pointer will have
already been set, and should not be set here as that would make it point
to itself. */
if( pxIterator != pxBlockToInsert )
8005418: 68fa ldr r2, [r7, #12]
800541a: 687b ldr r3, [r7, #4]
800541c: 429a cmp r2, r3
800541e: d002 beq.n 8005426 <prvInsertBlockIntoFreeList+0x9e>
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
8005420: 68fb ldr r3, [r7, #12]
8005422: 687a ldr r2, [r7, #4]
8005424: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8005426: bf00 nop
8005428: 3714 adds r7, #20
800542a: 46bd mov sp, r7
800542c: f85d 7b04 ldr.w r7, [sp], #4
8005430: 4770 bx lr
8005432: bf00 nop
8005434: 20004af4 .word 0x20004af4
8005438: 20004afc .word 0x20004afc
0800543c <memset>:
800543c: 4402 add r2, r0
800543e: 4603 mov r3, r0
8005440: 4293 cmp r3, r2
8005442: d100 bne.n 8005446 <memset+0xa>
8005444: 4770 bx lr
8005446: f803 1b01 strb.w r1, [r3], #1
800544a: e7f9 b.n 8005440 <memset+0x4>
0800544c <_reclaim_reent>:
800544c: 4b29 ldr r3, [pc, #164] ; (80054f4 <_reclaim_reent+0xa8>)
800544e: 681b ldr r3, [r3, #0]
8005450: 4283 cmp r3, r0
8005452: b570 push {r4, r5, r6, lr}
8005454: 4604 mov r4, r0
8005456: d04b beq.n 80054f0 <_reclaim_reent+0xa4>
8005458: 69c3 ldr r3, [r0, #28]
800545a: b143 cbz r3, 800546e <_reclaim_reent+0x22>
800545c: 68db ldr r3, [r3, #12]
800545e: 2b00 cmp r3, #0
8005460: d144 bne.n 80054ec <_reclaim_reent+0xa0>
8005462: 69e3 ldr r3, [r4, #28]
8005464: 6819 ldr r1, [r3, #0]
8005466: b111 cbz r1, 800546e <_reclaim_reent+0x22>
8005468: 4620 mov r0, r4
800546a: f000 f879 bl 8005560 <_free_r>
800546e: 6961 ldr r1, [r4, #20]
8005470: b111 cbz r1, 8005478 <_reclaim_reent+0x2c>
8005472: 4620 mov r0, r4
8005474: f000 f874 bl 8005560 <_free_r>
8005478: 69e1 ldr r1, [r4, #28]
800547a: b111 cbz r1, 8005482 <_reclaim_reent+0x36>
800547c: 4620 mov r0, r4
800547e: f000 f86f bl 8005560 <_free_r>
8005482: 6b21 ldr r1, [r4, #48] ; 0x30
8005484: b111 cbz r1, 800548c <_reclaim_reent+0x40>
8005486: 4620 mov r0, r4
8005488: f000 f86a bl 8005560 <_free_r>
800548c: 6b61 ldr r1, [r4, #52] ; 0x34
800548e: b111 cbz r1, 8005496 <_reclaim_reent+0x4a>
8005490: 4620 mov r0, r4
8005492: f000 f865 bl 8005560 <_free_r>
8005496: 6ba1 ldr r1, [r4, #56] ; 0x38
8005498: b111 cbz r1, 80054a0 <_reclaim_reent+0x54>
800549a: 4620 mov r0, r4
800549c: f000 f860 bl 8005560 <_free_r>
80054a0: 6ca1 ldr r1, [r4, #72] ; 0x48
80054a2: b111 cbz r1, 80054aa <_reclaim_reent+0x5e>
80054a4: 4620 mov r0, r4
80054a6: f000 f85b bl 8005560 <_free_r>
80054aa: 6c61 ldr r1, [r4, #68] ; 0x44
80054ac: b111 cbz r1, 80054b4 <_reclaim_reent+0x68>
80054ae: 4620 mov r0, r4
80054b0: f000 f856 bl 8005560 <_free_r>
80054b4: 6ae1 ldr r1, [r4, #44] ; 0x2c
80054b6: b111 cbz r1, 80054be <_reclaim_reent+0x72>
80054b8: 4620 mov r0, r4
80054ba: f000 f851 bl 8005560 <_free_r>
80054be: 6a23 ldr r3, [r4, #32]
80054c0: b1b3 cbz r3, 80054f0 <_reclaim_reent+0xa4>
80054c2: 4620 mov r0, r4
80054c4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
80054c8: 4718 bx r3
80054ca: 5949 ldr r1, [r1, r5]
80054cc: b941 cbnz r1, 80054e0 <_reclaim_reent+0x94>
80054ce: 3504 adds r5, #4
80054d0: 69e3 ldr r3, [r4, #28]
80054d2: 2d80 cmp r5, #128 ; 0x80
80054d4: 68d9 ldr r1, [r3, #12]
80054d6: d1f8 bne.n 80054ca <_reclaim_reent+0x7e>
80054d8: 4620 mov r0, r4
80054da: f000 f841 bl 8005560 <_free_r>
80054de: e7c0 b.n 8005462 <_reclaim_reent+0x16>
80054e0: 680e ldr r6, [r1, #0]
80054e2: 4620 mov r0, r4
80054e4: f000 f83c bl 8005560 <_free_r>
80054e8: 4631 mov r1, r6
80054ea: e7ef b.n 80054cc <_reclaim_reent+0x80>
80054ec: 2500 movs r5, #0
80054ee: e7ef b.n 80054d0 <_reclaim_reent+0x84>
80054f0: bd70 pop {r4, r5, r6, pc}
80054f2: bf00 nop
80054f4: 2000005c .word 0x2000005c
080054f8 <__libc_init_array>:
80054f8: b570 push {r4, r5, r6, lr}
80054fa: 4d0d ldr r5, [pc, #52] ; (8005530 <__libc_init_array+0x38>)
80054fc: 4c0d ldr r4, [pc, #52] ; (8005534 <__libc_init_array+0x3c>)
80054fe: 1b64 subs r4, r4, r5
8005500: 10a4 asrs r4, r4, #2
8005502: 2600 movs r6, #0
8005504: 42a6 cmp r6, r4
8005506: d109 bne.n 800551c <__libc_init_array+0x24>
8005508: 4d0b ldr r5, [pc, #44] ; (8005538 <__libc_init_array+0x40>)
800550a: 4c0c ldr r4, [pc, #48] ; (800553c <__libc_init_array+0x44>)
800550c: f000 f880 bl 8005610 <_init>
8005510: 1b64 subs r4, r4, r5
8005512: 10a4 asrs r4, r4, #2
8005514: 2600 movs r6, #0
8005516: 42a6 cmp r6, r4
8005518: d105 bne.n 8005526 <__libc_init_array+0x2e>
800551a: bd70 pop {r4, r5, r6, pc}
800551c: f855 3b04 ldr.w r3, [r5], #4
8005520: 4798 blx r3
8005522: 3601 adds r6, #1
8005524: e7ee b.n 8005504 <__libc_init_array+0xc>
8005526: f855 3b04 ldr.w r3, [r5], #4
800552a: 4798 blx r3
800552c: 3601 adds r6, #1
800552e: e7f2 b.n 8005516 <__libc_init_array+0x1e>
8005530: 080056c0 .word 0x080056c0
8005534: 080056c0 .word 0x080056c0
8005538: 080056c0 .word 0x080056c0
800553c: 080056c4 .word 0x080056c4
08005540 <__retarget_lock_acquire_recursive>:
8005540: 4770 bx lr
08005542 <__retarget_lock_release_recursive>:
8005542: 4770 bx lr
08005544 <memcpy>:
8005544: 440a add r2, r1
8005546: 4291 cmp r1, r2
8005548: f100 33ff add.w r3, r0, #4294967295
800554c: d100 bne.n 8005550 <memcpy+0xc>
800554e: 4770 bx lr
8005550: b510 push {r4, lr}
8005552: f811 4b01 ldrb.w r4, [r1], #1
8005556: f803 4f01 strb.w r4, [r3, #1]!
800555a: 4291 cmp r1, r2
800555c: d1f9 bne.n 8005552 <memcpy+0xe>
800555e: bd10 pop {r4, pc}
08005560 <_free_r>:
8005560: b537 push {r0, r1, r2, r4, r5, lr}
8005562: 2900 cmp r1, #0
8005564: d044 beq.n 80055f0 <_free_r+0x90>
8005566: f851 3c04 ldr.w r3, [r1, #-4]
800556a: 9001 str r0, [sp, #4]
800556c: 2b00 cmp r3, #0
800556e: f1a1 0404 sub.w r4, r1, #4
8005572: bfb8 it lt
8005574: 18e4 addlt r4, r4, r3
8005576: f000 f83f bl 80055f8 <__malloc_lock>
800557a: 4a1e ldr r2, [pc, #120] ; (80055f4 <_free_r+0x94>)
800557c: 9801 ldr r0, [sp, #4]
800557e: 6813 ldr r3, [r2, #0]
8005580: b933 cbnz r3, 8005590 <_free_r+0x30>
8005582: 6063 str r3, [r4, #4]
8005584: 6014 str r4, [r2, #0]
8005586: b003 add sp, #12
8005588: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
800558c: f000 b83a b.w 8005604 <__malloc_unlock>
8005590: 42a3 cmp r3, r4
8005592: d908 bls.n 80055a6 <_free_r+0x46>
8005594: 6825 ldr r5, [r4, #0]
8005596: 1961 adds r1, r4, r5
8005598: 428b cmp r3, r1
800559a: bf01 itttt eq
800559c: 6819 ldreq r1, [r3, #0]
800559e: 685b ldreq r3, [r3, #4]
80055a0: 1949 addeq r1, r1, r5
80055a2: 6021 streq r1, [r4, #0]
80055a4: e7ed b.n 8005582 <_free_r+0x22>
80055a6: 461a mov r2, r3
80055a8: 685b ldr r3, [r3, #4]
80055aa: b10b cbz r3, 80055b0 <_free_r+0x50>
80055ac: 42a3 cmp r3, r4
80055ae: d9fa bls.n 80055a6 <_free_r+0x46>
80055b0: 6811 ldr r1, [r2, #0]
80055b2: 1855 adds r5, r2, r1
80055b4: 42a5 cmp r5, r4
80055b6: d10b bne.n 80055d0 <_free_r+0x70>
80055b8: 6824 ldr r4, [r4, #0]
80055ba: 4421 add r1, r4
80055bc: 1854 adds r4, r2, r1
80055be: 42a3 cmp r3, r4
80055c0: 6011 str r1, [r2, #0]
80055c2: d1e0 bne.n 8005586 <_free_r+0x26>
80055c4: 681c ldr r4, [r3, #0]
80055c6: 685b ldr r3, [r3, #4]
80055c8: 6053 str r3, [r2, #4]
80055ca: 440c add r4, r1
80055cc: 6014 str r4, [r2, #0]
80055ce: e7da b.n 8005586 <_free_r+0x26>
80055d0: d902 bls.n 80055d8 <_free_r+0x78>
80055d2: 230c movs r3, #12
80055d4: 6003 str r3, [r0, #0]
80055d6: e7d6 b.n 8005586 <_free_r+0x26>
80055d8: 6825 ldr r5, [r4, #0]
80055da: 1961 adds r1, r4, r5
80055dc: 428b cmp r3, r1
80055de: bf04 itt eq
80055e0: 6819 ldreq r1, [r3, #0]
80055e2: 685b ldreq r3, [r3, #4]
80055e4: 6063 str r3, [r4, #4]
80055e6: bf04 itt eq
80055e8: 1949 addeq r1, r1, r5
80055ea: 6021 streq r1, [r4, #0]
80055ec: 6054 str r4, [r2, #4]
80055ee: e7ca b.n 8005586 <_free_r+0x26>
80055f0: b003 add sp, #12
80055f2: bd30 pop {r4, r5, pc}
80055f4: 20004c50 .word 0x20004c50
080055f8 <__malloc_lock>:
80055f8: 4801 ldr r0, [pc, #4] ; (8005600 <__malloc_lock+0x8>)
80055fa: f7ff bfa1 b.w 8005540 <__retarget_lock_acquire_recursive>
80055fe: bf00 nop
8005600: 20004c4c .word 0x20004c4c
08005604 <__malloc_unlock>:
8005604: 4801 ldr r0, [pc, #4] ; (800560c <__malloc_unlock+0x8>)
8005606: f7ff bf9c b.w 8005542 <__retarget_lock_release_recursive>
800560a: bf00 nop
800560c: 20004c4c .word 0x20004c4c
08005610 <_init>:
8005610: b5f8 push {r3, r4, r5, r6, r7, lr}
8005612: bf00 nop
8005614: bcf8 pop {r3, r4, r5, r6, r7}
8005616: bc08 pop {r3}
8005618: 469e mov lr, r3
800561a: 4770 bx lr
0800561c <_fini>:
800561c: b5f8 push {r3, r4, r5, r6, r7, lr}
800561e: bf00 nop
8005620: bcf8 pop {r3, r4, r5, r6, r7}
8005622: bc08 pop {r3}
8005624: 469e mov lr, r3
8005626: 4770 bx lr
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