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stm32-fmt-code/access_control_stm32/Debug/access_control_stm32.list

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access_control_stm32.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000198 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000054a8 080001a0 080001a0 000101a0 2**4
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000090 08005648 08005648 00015648 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080056d8 080056d8 00020060 2**0
CONTENTS
4 .ARM 00000008 080056d8 080056d8 000156d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080056e0 080056e0 00020060 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080056e0 080056e0 000156e0 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 080056e4 080056e4 000156e4 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 00000060 20000000 080056e8 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00004bf4 20000060 08005748 00020060 2**2
ALLOC
10 ._user_heap_stack 00003004 20004c54 08005748 00024c54 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00020060 2**0
CONTENTS, READONLY
12 .comment 00000043 00000000 00000000 00020090 2**0
CONTENTS, READONLY
13 .debug_info 000175bc 00000000 00000000 000200d3 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_abbrev 0000318b 00000000 00000000 0003768f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00001390 00000000 00000000 0003a820 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_rnglists 00000f3f 00000000 00000000 0003bbb0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_macro 00003557 00000000 00000000 0003caef 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_line 000157ed 00000000 00000000 00040046 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_str 0009856e 00000000 00000000 00055833 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_frame 000055a0 00000000 00000000 000edda4 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000059 00000000 00000000 000f3344 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001a0 <__do_global_dtors_aux>:
80001a0: b510 push {r4, lr}
80001a2: 4c05 ldr r4, [pc, #20] ; (80001b8 <__do_global_dtors_aux+0x18>)
80001a4: 7823 ldrb r3, [r4, #0]
80001a6: b933 cbnz r3, 80001b6 <__do_global_dtors_aux+0x16>
80001a8: 4b04 ldr r3, [pc, #16] ; (80001bc <__do_global_dtors_aux+0x1c>)
80001aa: b113 cbz r3, 80001b2 <__do_global_dtors_aux+0x12>
80001ac: 4804 ldr r0, [pc, #16] ; (80001c0 <__do_global_dtors_aux+0x20>)
80001ae: f3af 8000 nop.w
80001b2: 2301 movs r3, #1
80001b4: 7023 strb r3, [r4, #0]
80001b6: bd10 pop {r4, pc}
80001b8: 20000060 .word 0x20000060
80001bc: 00000000 .word 0x00000000
80001c0: 08005630 .word 0x08005630
080001c4 <frame_dummy>:
80001c4: b508 push {r3, lr}
80001c6: 4b03 ldr r3, [pc, #12] ; (80001d4 <frame_dummy+0x10>)
80001c8: b11b cbz r3, 80001d2 <frame_dummy+0xe>
80001ca: 4903 ldr r1, [pc, #12] ; (80001d8 <frame_dummy+0x14>)
80001cc: 4803 ldr r0, [pc, #12] ; (80001dc <frame_dummy+0x18>)
80001ce: f3af 8000 nop.w
80001d2: bd08 pop {r3, pc}
80001d4: 00000000 .word 0x00000000
80001d8: 20000064 .word 0x20000064
80001dc: 08005630 .word 0x08005630
080001e0 <__aeabi_uldivmod>:
80001e0: b953 cbnz r3, 80001f8 <__aeabi_uldivmod+0x18>
80001e2: b94a cbnz r2, 80001f8 <__aeabi_uldivmod+0x18>
80001e4: 2900 cmp r1, #0
80001e6: bf08 it eq
80001e8: 2800 cmpeq r0, #0
80001ea: bf1c itt ne
80001ec: f04f 31ff movne.w r1, #4294967295
80001f0: f04f 30ff movne.w r0, #4294967295
80001f4: f000 b970 b.w 80004d8 <__aeabi_idiv0>
80001f8: f1ad 0c08 sub.w ip, sp, #8
80001fc: e96d ce04 strd ip, lr, [sp, #-16]!
8000200: f000 f806 bl 8000210 <__udivmoddi4>
8000204: f8dd e004 ldr.w lr, [sp, #4]
8000208: e9dd 2302 ldrd r2, r3, [sp, #8]
800020c: b004 add sp, #16
800020e: 4770 bx lr
08000210 <__udivmoddi4>:
8000210: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000214: 9e08 ldr r6, [sp, #32]
8000216: 460d mov r5, r1
8000218: 4604 mov r4, r0
800021a: 460f mov r7, r1
800021c: 2b00 cmp r3, #0
800021e: d14a bne.n 80002b6 <__udivmoddi4+0xa6>
8000220: 428a cmp r2, r1
8000222: 4694 mov ip, r2
8000224: d965 bls.n 80002f2 <__udivmoddi4+0xe2>
8000226: fab2 f382 clz r3, r2
800022a: b143 cbz r3, 800023e <__udivmoddi4+0x2e>
800022c: fa02 fc03 lsl.w ip, r2, r3
8000230: f1c3 0220 rsb r2, r3, #32
8000234: 409f lsls r7, r3
8000236: fa20 f202 lsr.w r2, r0, r2
800023a: 4317 orrs r7, r2
800023c: 409c lsls r4, r3
800023e: ea4f 4e1c mov.w lr, ip, lsr #16
8000242: fa1f f58c uxth.w r5, ip
8000246: fbb7 f1fe udiv r1, r7, lr
800024a: 0c22 lsrs r2, r4, #16
800024c: fb0e 7711 mls r7, lr, r1, r7
8000250: ea42 4207 orr.w r2, r2, r7, lsl #16
8000254: fb01 f005 mul.w r0, r1, r5
8000258: 4290 cmp r0, r2
800025a: d90a bls.n 8000272 <__udivmoddi4+0x62>
800025c: eb1c 0202 adds.w r2, ip, r2
8000260: f101 37ff add.w r7, r1, #4294967295
8000264: f080 811c bcs.w 80004a0 <__udivmoddi4+0x290>
8000268: 4290 cmp r0, r2
800026a: f240 8119 bls.w 80004a0 <__udivmoddi4+0x290>
800026e: 3902 subs r1, #2
8000270: 4462 add r2, ip
8000272: 1a12 subs r2, r2, r0
8000274: b2a4 uxth r4, r4
8000276: fbb2 f0fe udiv r0, r2, lr
800027a: fb0e 2210 mls r2, lr, r0, r2
800027e: ea44 4402 orr.w r4, r4, r2, lsl #16
8000282: fb00 f505 mul.w r5, r0, r5
8000286: 42a5 cmp r5, r4
8000288: d90a bls.n 80002a0 <__udivmoddi4+0x90>
800028a: eb1c 0404 adds.w r4, ip, r4
800028e: f100 32ff add.w r2, r0, #4294967295
8000292: f080 8107 bcs.w 80004a4 <__udivmoddi4+0x294>
8000296: 42a5 cmp r5, r4
8000298: f240 8104 bls.w 80004a4 <__udivmoddi4+0x294>
800029c: 4464 add r4, ip
800029e: 3802 subs r0, #2
80002a0: ea40 4001 orr.w r0, r0, r1, lsl #16
80002a4: 1b64 subs r4, r4, r5
80002a6: 2100 movs r1, #0
80002a8: b11e cbz r6, 80002b2 <__udivmoddi4+0xa2>
80002aa: 40dc lsrs r4, r3
80002ac: 2300 movs r3, #0
80002ae: e9c6 4300 strd r4, r3, [r6]
80002b2: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002b6: 428b cmp r3, r1
80002b8: d908 bls.n 80002cc <__udivmoddi4+0xbc>
80002ba: 2e00 cmp r6, #0
80002bc: f000 80ed beq.w 800049a <__udivmoddi4+0x28a>
80002c0: 2100 movs r1, #0
80002c2: e9c6 0500 strd r0, r5, [r6]
80002c6: 4608 mov r0, r1
80002c8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002cc: fab3 f183 clz r1, r3
80002d0: 2900 cmp r1, #0
80002d2: d149 bne.n 8000368 <__udivmoddi4+0x158>
80002d4: 42ab cmp r3, r5
80002d6: d302 bcc.n 80002de <__udivmoddi4+0xce>
80002d8: 4282 cmp r2, r0
80002da: f200 80f8 bhi.w 80004ce <__udivmoddi4+0x2be>
80002de: 1a84 subs r4, r0, r2
80002e0: eb65 0203 sbc.w r2, r5, r3
80002e4: 2001 movs r0, #1
80002e6: 4617 mov r7, r2
80002e8: 2e00 cmp r6, #0
80002ea: d0e2 beq.n 80002b2 <__udivmoddi4+0xa2>
80002ec: e9c6 4700 strd r4, r7, [r6]
80002f0: e7df b.n 80002b2 <__udivmoddi4+0xa2>
80002f2: b902 cbnz r2, 80002f6 <__udivmoddi4+0xe6>
80002f4: deff udf #255 ; 0xff
80002f6: fab2 f382 clz r3, r2
80002fa: 2b00 cmp r3, #0
80002fc: f040 8090 bne.w 8000420 <__udivmoddi4+0x210>
8000300: 1a8a subs r2, r1, r2
8000302: ea4f 471c mov.w r7, ip, lsr #16
8000306: fa1f fe8c uxth.w lr, ip
800030a: 2101 movs r1, #1
800030c: fbb2 f5f7 udiv r5, r2, r7
8000310: fb07 2015 mls r0, r7, r5, r2
8000314: 0c22 lsrs r2, r4, #16
8000316: ea42 4200 orr.w r2, r2, r0, lsl #16
800031a: fb0e f005 mul.w r0, lr, r5
800031e: 4290 cmp r0, r2
8000320: d908 bls.n 8000334 <__udivmoddi4+0x124>
8000322: eb1c 0202 adds.w r2, ip, r2
8000326: f105 38ff add.w r8, r5, #4294967295
800032a: d202 bcs.n 8000332 <__udivmoddi4+0x122>
800032c: 4290 cmp r0, r2
800032e: f200 80cb bhi.w 80004c8 <__udivmoddi4+0x2b8>
8000332: 4645 mov r5, r8
8000334: 1a12 subs r2, r2, r0
8000336: b2a4 uxth r4, r4
8000338: fbb2 f0f7 udiv r0, r2, r7
800033c: fb07 2210 mls r2, r7, r0, r2
8000340: ea44 4402 orr.w r4, r4, r2, lsl #16
8000344: fb0e fe00 mul.w lr, lr, r0
8000348: 45a6 cmp lr, r4
800034a: d908 bls.n 800035e <__udivmoddi4+0x14e>
800034c: eb1c 0404 adds.w r4, ip, r4
8000350: f100 32ff add.w r2, r0, #4294967295
8000354: d202 bcs.n 800035c <__udivmoddi4+0x14c>
8000356: 45a6 cmp lr, r4
8000358: f200 80bb bhi.w 80004d2 <__udivmoddi4+0x2c2>
800035c: 4610 mov r0, r2
800035e: eba4 040e sub.w r4, r4, lr
8000362: ea40 4005 orr.w r0, r0, r5, lsl #16
8000366: e79f b.n 80002a8 <__udivmoddi4+0x98>
8000368: f1c1 0720 rsb r7, r1, #32
800036c: 408b lsls r3, r1
800036e: fa22 fc07 lsr.w ip, r2, r7
8000372: ea4c 0c03 orr.w ip, ip, r3
8000376: fa05 f401 lsl.w r4, r5, r1
800037a: fa20 f307 lsr.w r3, r0, r7
800037e: 40fd lsrs r5, r7
8000380: ea4f 491c mov.w r9, ip, lsr #16
8000384: 4323 orrs r3, r4
8000386: fbb5 f8f9 udiv r8, r5, r9
800038a: fa1f fe8c uxth.w lr, ip
800038e: fb09 5518 mls r5, r9, r8, r5
8000392: 0c1c lsrs r4, r3, #16
8000394: ea44 4405 orr.w r4, r4, r5, lsl #16
8000398: fb08 f50e mul.w r5, r8, lr
800039c: 42a5 cmp r5, r4
800039e: fa02 f201 lsl.w r2, r2, r1
80003a2: fa00 f001 lsl.w r0, r0, r1
80003a6: d90b bls.n 80003c0 <__udivmoddi4+0x1b0>
80003a8: eb1c 0404 adds.w r4, ip, r4
80003ac: f108 3aff add.w sl, r8, #4294967295
80003b0: f080 8088 bcs.w 80004c4 <__udivmoddi4+0x2b4>
80003b4: 42a5 cmp r5, r4
80003b6: f240 8085 bls.w 80004c4 <__udivmoddi4+0x2b4>
80003ba: f1a8 0802 sub.w r8, r8, #2
80003be: 4464 add r4, ip
80003c0: 1b64 subs r4, r4, r5
80003c2: b29d uxth r5, r3
80003c4: fbb4 f3f9 udiv r3, r4, r9
80003c8: fb09 4413 mls r4, r9, r3, r4
80003cc: ea45 4404 orr.w r4, r5, r4, lsl #16
80003d0: fb03 fe0e mul.w lr, r3, lr
80003d4: 45a6 cmp lr, r4
80003d6: d908 bls.n 80003ea <__udivmoddi4+0x1da>
80003d8: eb1c 0404 adds.w r4, ip, r4
80003dc: f103 35ff add.w r5, r3, #4294967295
80003e0: d26c bcs.n 80004bc <__udivmoddi4+0x2ac>
80003e2: 45a6 cmp lr, r4
80003e4: d96a bls.n 80004bc <__udivmoddi4+0x2ac>
80003e6: 3b02 subs r3, #2
80003e8: 4464 add r4, ip
80003ea: ea43 4308 orr.w r3, r3, r8, lsl #16
80003ee: fba3 9502 umull r9, r5, r3, r2
80003f2: eba4 040e sub.w r4, r4, lr
80003f6: 42ac cmp r4, r5
80003f8: 46c8 mov r8, r9
80003fa: 46ae mov lr, r5
80003fc: d356 bcc.n 80004ac <__udivmoddi4+0x29c>
80003fe: d053 beq.n 80004a8 <__udivmoddi4+0x298>
8000400: b156 cbz r6, 8000418 <__udivmoddi4+0x208>
8000402: ebb0 0208 subs.w r2, r0, r8
8000406: eb64 040e sbc.w r4, r4, lr
800040a: fa04 f707 lsl.w r7, r4, r7
800040e: 40ca lsrs r2, r1
8000410: 40cc lsrs r4, r1
8000412: 4317 orrs r7, r2
8000414: e9c6 7400 strd r7, r4, [r6]
8000418: 4618 mov r0, r3
800041a: 2100 movs r1, #0
800041c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000420: f1c3 0120 rsb r1, r3, #32
8000424: fa02 fc03 lsl.w ip, r2, r3
8000428: fa20 f201 lsr.w r2, r0, r1
800042c: fa25 f101 lsr.w r1, r5, r1
8000430: 409d lsls r5, r3
8000432: 432a orrs r2, r5
8000434: ea4f 471c mov.w r7, ip, lsr #16
8000438: fa1f fe8c uxth.w lr, ip
800043c: fbb1 f0f7 udiv r0, r1, r7
8000440: fb07 1510 mls r5, r7, r0, r1
8000444: 0c11 lsrs r1, r2, #16
8000446: ea41 4105 orr.w r1, r1, r5, lsl #16
800044a: fb00 f50e mul.w r5, r0, lr
800044e: 428d cmp r5, r1
8000450: fa04 f403 lsl.w r4, r4, r3
8000454: d908 bls.n 8000468 <__udivmoddi4+0x258>
8000456: eb1c 0101 adds.w r1, ip, r1
800045a: f100 38ff add.w r8, r0, #4294967295
800045e: d22f bcs.n 80004c0 <__udivmoddi4+0x2b0>
8000460: 428d cmp r5, r1
8000462: d92d bls.n 80004c0 <__udivmoddi4+0x2b0>
8000464: 3802 subs r0, #2
8000466: 4461 add r1, ip
8000468: 1b49 subs r1, r1, r5
800046a: b292 uxth r2, r2
800046c: fbb1 f5f7 udiv r5, r1, r7
8000470: fb07 1115 mls r1, r7, r5, r1
8000474: ea42 4201 orr.w r2, r2, r1, lsl #16
8000478: fb05 f10e mul.w r1, r5, lr
800047c: 4291 cmp r1, r2
800047e: d908 bls.n 8000492 <__udivmoddi4+0x282>
8000480: eb1c 0202 adds.w r2, ip, r2
8000484: f105 38ff add.w r8, r5, #4294967295
8000488: d216 bcs.n 80004b8 <__udivmoddi4+0x2a8>
800048a: 4291 cmp r1, r2
800048c: d914 bls.n 80004b8 <__udivmoddi4+0x2a8>
800048e: 3d02 subs r5, #2
8000490: 4462 add r2, ip
8000492: 1a52 subs r2, r2, r1
8000494: ea45 4100 orr.w r1, r5, r0, lsl #16
8000498: e738 b.n 800030c <__udivmoddi4+0xfc>
800049a: 4631 mov r1, r6
800049c: 4630 mov r0, r6
800049e: e708 b.n 80002b2 <__udivmoddi4+0xa2>
80004a0: 4639 mov r1, r7
80004a2: e6e6 b.n 8000272 <__udivmoddi4+0x62>
80004a4: 4610 mov r0, r2
80004a6: e6fb b.n 80002a0 <__udivmoddi4+0x90>
80004a8: 4548 cmp r0, r9
80004aa: d2a9 bcs.n 8000400 <__udivmoddi4+0x1f0>
80004ac: ebb9 0802 subs.w r8, r9, r2
80004b0: eb65 0e0c sbc.w lr, r5, ip
80004b4: 3b01 subs r3, #1
80004b6: e7a3 b.n 8000400 <__udivmoddi4+0x1f0>
80004b8: 4645 mov r5, r8
80004ba: e7ea b.n 8000492 <__udivmoddi4+0x282>
80004bc: 462b mov r3, r5
80004be: e794 b.n 80003ea <__udivmoddi4+0x1da>
80004c0: 4640 mov r0, r8
80004c2: e7d1 b.n 8000468 <__udivmoddi4+0x258>
80004c4: 46d0 mov r8, sl
80004c6: e77b b.n 80003c0 <__udivmoddi4+0x1b0>
80004c8: 3d02 subs r5, #2
80004ca: 4462 add r2, ip
80004cc: e732 b.n 8000334 <__udivmoddi4+0x124>
80004ce: 4608 mov r0, r1
80004d0: e70a b.n 80002e8 <__udivmoddi4+0xd8>
80004d2: 4464 add r4, ip
80004d4: 3802 subs r0, #2
80004d6: e742 b.n 800035e <__udivmoddi4+0x14e>
080004d8 <__aeabi_idiv0>:
80004d8: 4770 bx lr
80004da: bf00 nop
080004dc <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
80004dc: b580 push {r7, lr}
80004de: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80004e0: f000 fb92 bl 8000c08 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80004e4: f000 f82c bl 8000540 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80004e8: f000 f8be bl 8000668 <MX_GPIO_Init>
MX_USART2_UART_Init();
80004ec: f000 f892 bl 8000614 <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
memset(uart_buffer, 0, 10);
80004f0: 220a movs r2, #10
80004f2: 2100 movs r1, #0
80004f4: 480b ldr r0, [pc, #44] ; (8000524 <main+0x48>)
80004f6: f004 ffb1 bl 800545c <memset>
/* USER CODE END 2 */
/* Init scheduler */
osKernelInitialize();
80004fa: f002 fa51 bl 80029a0 <osKernelInitialize>
/* add queues, ... */
/* USER CODE END RTOS_QUEUES */
/* Create the thread(s) */
/* creation of mainTask */
mainTaskHandle = osThreadNew(StartMainTask, NULL, &mainTask_attributes);
80004fe: 4a0a ldr r2, [pc, #40] ; (8000528 <main+0x4c>)
8000500: 2100 movs r1, #0
8000502: 480a ldr r0, [pc, #40] ; (800052c <main+0x50>)
8000504: f002 fa96 bl 8002a34 <osThreadNew>
8000508: 4603 mov r3, r0
800050a: 4a09 ldr r2, [pc, #36] ; (8000530 <main+0x54>)
800050c: 6013 str r3, [r2, #0]
/* creation of doorHandler */
doorHandlerHandle = osThreadNew(startDoorHandleTask, NULL, &doorHandler_attributes);
800050e: 4a09 ldr r2, [pc, #36] ; (8000534 <main+0x58>)
8000510: 2100 movs r1, #0
8000512: 4809 ldr r0, [pc, #36] ; (8000538 <main+0x5c>)
8000514: f002 fa8e bl 8002a34 <osThreadNew>
8000518: 4603 mov r3, r0
800051a: 4a08 ldr r2, [pc, #32] ; (800053c <main+0x60>)
800051c: 6013 str r3, [r2, #0]
/* USER CODE BEGIN RTOS_EVENTS */
/* add events, ... */
/* USER CODE END RTOS_EVENTS */
/* Start scheduler */
osKernelStart();
800051e: f002 fa63 bl 80029e8 <osKernelStart>
/* We should never get here as control is now taken by the scheduler */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
8000522: e7fe b.n 8000522 <main+0x46>
8000524: 200000c8 .word 0x200000c8
8000528: 08005678 .word 0x08005678
800052c: 08000761 .word 0x08000761
8000530: 200000c0 .word 0x200000c0
8000534: 0800569c .word 0x0800569c
8000538: 08000855 .word 0x08000855
800053c: 200000c4 .word 0x200000c4
08000540 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000540: b580 push {r7, lr}
8000542: b094 sub sp, #80 ; 0x50
8000544: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000546: f107 0320 add.w r3, r7, #32
800054a: 2230 movs r2, #48 ; 0x30
800054c: 2100 movs r1, #0
800054e: 4618 mov r0, r3
8000550: f004 ff84 bl 800545c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000554: f107 030c add.w r3, r7, #12
8000558: 2200 movs r2, #0
800055a: 601a str r2, [r3, #0]
800055c: 605a str r2, [r3, #4]
800055e: 609a str r2, [r3, #8]
8000560: 60da str r2, [r3, #12]
8000562: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8000564: 2300 movs r3, #0
8000566: 60bb str r3, [r7, #8]
8000568: 4b28 ldr r3, [pc, #160] ; (800060c <SystemClock_Config+0xcc>)
800056a: 6c1b ldr r3, [r3, #64] ; 0x40
800056c: 4a27 ldr r2, [pc, #156] ; (800060c <SystemClock_Config+0xcc>)
800056e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8000572: 6413 str r3, [r2, #64] ; 0x40
8000574: 4b25 ldr r3, [pc, #148] ; (800060c <SystemClock_Config+0xcc>)
8000576: 6c1b ldr r3, [r3, #64] ; 0x40
8000578: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800057c: 60bb str r3, [r7, #8]
800057e: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8000580: 2300 movs r3, #0
8000582: 607b str r3, [r7, #4]
8000584: 4b22 ldr r3, [pc, #136] ; (8000610 <SystemClock_Config+0xd0>)
8000586: 681b ldr r3, [r3, #0]
8000588: 4a21 ldr r2, [pc, #132] ; (8000610 <SystemClock_Config+0xd0>)
800058a: f443 4340 orr.w r3, r3, #49152 ; 0xc000
800058e: 6013 str r3, [r2, #0]
8000590: 4b1f ldr r3, [pc, #124] ; (8000610 <SystemClock_Config+0xd0>)
8000592: 681b ldr r3, [r3, #0]
8000594: f403 4340 and.w r3, r3, #49152 ; 0xc000
8000598: 607b str r3, [r7, #4]
800059a: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
800059c: 2302 movs r3, #2
800059e: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80005a0: 2301 movs r3, #1
80005a2: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80005a4: 2310 movs r3, #16
80005a6: 633b str r3, [r7, #48] ; 0x30
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80005a8: 2302 movs r3, #2
80005aa: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
80005ac: 2300 movs r3, #0
80005ae: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLM = 16;
80005b0: 2310 movs r3, #16
80005b2: 643b str r3, [r7, #64] ; 0x40
RCC_OscInitStruct.PLL.PLLN = 336;
80005b4: f44f 73a8 mov.w r3, #336 ; 0x150
80005b8: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
80005ba: 2304 movs r3, #4
80005bc: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLQ = 4;
80005be: 2304 movs r3, #4
80005c0: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80005c2: f107 0320 add.w r3, r7, #32
80005c6: 4618 mov r0, r3
80005c8: f000 fdf8 bl 80011bc <HAL_RCC_OscConfig>
80005cc: 4603 mov r3, r0
80005ce: 2b00 cmp r3, #0
80005d0: d001 beq.n 80005d6 <SystemClock_Config+0x96>
{
Error_Handler();
80005d2: f000 f9d1 bl 8000978 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80005d6: 230f movs r3, #15
80005d8: 60fb str r3, [r7, #12]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80005da: 2302 movs r3, #2
80005dc: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80005de: 2300 movs r3, #0
80005e0: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
80005e2: f44f 5380 mov.w r3, #4096 ; 0x1000
80005e6: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80005e8: 2300 movs r3, #0
80005ea: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
80005ec: f107 030c add.w r3, r7, #12
80005f0: 2102 movs r1, #2
80005f2: 4618 mov r0, r3
80005f4: f001 f85a bl 80016ac <HAL_RCC_ClockConfig>
80005f8: 4603 mov r3, r0
80005fa: 2b00 cmp r3, #0
80005fc: d001 beq.n 8000602 <SystemClock_Config+0xc2>
{
Error_Handler();
80005fe: f000 f9bb bl 8000978 <Error_Handler>
}
}
8000602: bf00 nop
8000604: 3750 adds r7, #80 ; 0x50
8000606: 46bd mov sp, r7
8000608: bd80 pop {r7, pc}
800060a: bf00 nop
800060c: 40023800 .word 0x40023800
8000610: 40007000 .word 0x40007000
08000614 <MX_USART2_UART_Init>:
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void)
{
8000614: b580 push {r7, lr}
8000616: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
8000618: 4b11 ldr r3, [pc, #68] ; (8000660 <MX_USART2_UART_Init+0x4c>)
800061a: 4a12 ldr r2, [pc, #72] ; (8000664 <MX_USART2_UART_Init+0x50>)
800061c: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 9600;
800061e: 4b10 ldr r3, [pc, #64] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000620: f44f 5216 mov.w r2, #9600 ; 0x2580
8000624: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
8000626: 4b0e ldr r3, [pc, #56] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000628: 2200 movs r2, #0
800062a: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
800062c: 4b0c ldr r3, [pc, #48] ; (8000660 <MX_USART2_UART_Init+0x4c>)
800062e: 2200 movs r2, #0
8000630: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8000632: 4b0b ldr r3, [pc, #44] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000634: 2200 movs r2, #0
8000636: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
8000638: 4b09 ldr r3, [pc, #36] ; (8000660 <MX_USART2_UART_Init+0x4c>)
800063a: 220c movs r2, #12
800063c: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
800063e: 4b08 ldr r3, [pc, #32] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000640: 2200 movs r2, #0
8000642: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
8000644: 4b06 ldr r3, [pc, #24] ; (8000660 <MX_USART2_UART_Init+0x4c>)
8000646: 2200 movs r2, #0
8000648: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK)
800064a: 4805 ldr r0, [pc, #20] ; (8000660 <MX_USART2_UART_Init+0x4c>)
800064c: f001 fd00 bl 8002050 <HAL_UART_Init>
8000650: 4603 mov r3, r0
8000652: 2b00 cmp r3, #0
8000654: d001 beq.n 800065a <MX_USART2_UART_Init+0x46>
{
Error_Handler();
8000656: f000 f98f bl 8000978 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
800065a: bf00 nop
800065c: bd80 pop {r7, pc}
800065e: bf00 nop
8000660: 2000007c .word 0x2000007c
8000664: 40004400 .word 0x40004400
08000668 <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
8000668: b580 push {r7, lr}
800066a: b08a sub sp, #40 ; 0x28
800066c: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
800066e: f107 0314 add.w r3, r7, #20
8000672: 2200 movs r2, #0
8000674: 601a str r2, [r3, #0]
8000676: 605a str r2, [r3, #4]
8000678: 609a str r2, [r3, #8]
800067a: 60da str r2, [r3, #12]
800067c: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
800067e: 2300 movs r3, #0
8000680: 613b str r3, [r7, #16]
8000682: 4b34 ldr r3, [pc, #208] ; (8000754 <MX_GPIO_Init+0xec>)
8000684: 6b1b ldr r3, [r3, #48] ; 0x30
8000686: 4a33 ldr r2, [pc, #204] ; (8000754 <MX_GPIO_Init+0xec>)
8000688: f043 0304 orr.w r3, r3, #4
800068c: 6313 str r3, [r2, #48] ; 0x30
800068e: 4b31 ldr r3, [pc, #196] ; (8000754 <MX_GPIO_Init+0xec>)
8000690: 6b1b ldr r3, [r3, #48] ; 0x30
8000692: f003 0304 and.w r3, r3, #4
8000696: 613b str r3, [r7, #16]
8000698: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
800069a: 2300 movs r3, #0
800069c: 60fb str r3, [r7, #12]
800069e: 4b2d ldr r3, [pc, #180] ; (8000754 <MX_GPIO_Init+0xec>)
80006a0: 6b1b ldr r3, [r3, #48] ; 0x30
80006a2: 4a2c ldr r2, [pc, #176] ; (8000754 <MX_GPIO_Init+0xec>)
80006a4: f043 0380 orr.w r3, r3, #128 ; 0x80
80006a8: 6313 str r3, [r2, #48] ; 0x30
80006aa: 4b2a ldr r3, [pc, #168] ; (8000754 <MX_GPIO_Init+0xec>)
80006ac: 6b1b ldr r3, [r3, #48] ; 0x30
80006ae: f003 0380 and.w r3, r3, #128 ; 0x80
80006b2: 60fb str r3, [r7, #12]
80006b4: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
80006b6: 2300 movs r3, #0
80006b8: 60bb str r3, [r7, #8]
80006ba: 4b26 ldr r3, [pc, #152] ; (8000754 <MX_GPIO_Init+0xec>)
80006bc: 6b1b ldr r3, [r3, #48] ; 0x30
80006be: 4a25 ldr r2, [pc, #148] ; (8000754 <MX_GPIO_Init+0xec>)
80006c0: f043 0301 orr.w r3, r3, #1
80006c4: 6313 str r3, [r2, #48] ; 0x30
80006c6: 4b23 ldr r3, [pc, #140] ; (8000754 <MX_GPIO_Init+0xec>)
80006c8: 6b1b ldr r3, [r3, #48] ; 0x30
80006ca: f003 0301 and.w r3, r3, #1
80006ce: 60bb str r3, [r7, #8]
80006d0: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
80006d2: 2300 movs r3, #0
80006d4: 607b str r3, [r7, #4]
80006d6: 4b1f ldr r3, [pc, #124] ; (8000754 <MX_GPIO_Init+0xec>)
80006d8: 6b1b ldr r3, [r3, #48] ; 0x30
80006da: 4a1e ldr r2, [pc, #120] ; (8000754 <MX_GPIO_Init+0xec>)
80006dc: f043 0302 orr.w r3, r3, #2
80006e0: 6313 str r3, [r2, #48] ; 0x30
80006e2: 4b1c ldr r3, [pc, #112] ; (8000754 <MX_GPIO_Init+0xec>)
80006e4: 6b1b ldr r3, [r3, #48] ; 0x30
80006e6: f003 0302 and.w r3, r3, #2
80006ea: 607b str r3, [r7, #4]
80006ec: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, LD2_Pin|Door_Lock_Pin, GPIO_PIN_RESET);
80006ee: 2200 movs r2, #0
80006f0: f44f 7108 mov.w r1, #544 ; 0x220
80006f4: 4818 ldr r0, [pc, #96] ; (8000758 <MX_GPIO_Init+0xf0>)
80006f6: f000 fd47 bl 8001188 <HAL_GPIO_WritePin>
/*Configure GPIO pin : B1_Pin */
GPIO_InitStruct.Pin = B1_Pin;
80006fa: f44f 5300 mov.w r3, #8192 ; 0x2000
80006fe: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
8000700: f44f 1304 mov.w r3, #2162688 ; 0x210000
8000704: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000706: 2300 movs r3, #0
8000708: 61fb str r3, [r7, #28]
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
800070a: f107 0314 add.w r3, r7, #20
800070e: 4619 mov r1, r3
8000710: 4812 ldr r0, [pc, #72] ; (800075c <MX_GPIO_Init+0xf4>)
8000712: f000 fb9d bl 8000e50 <HAL_GPIO_Init>
/*Configure GPIO pins : LD2_Pin Door_Lock_Pin */
GPIO_InitStruct.Pin = LD2_Pin|Door_Lock_Pin;
8000716: f44f 7308 mov.w r3, #544 ; 0x220
800071a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800071c: 2301 movs r3, #1
800071e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000720: 2300 movs r3, #0
8000722: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000724: 2300 movs r3, #0
8000726: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000728: f107 0314 add.w r3, r7, #20
800072c: 4619 mov r1, r3
800072e: 480a ldr r0, [pc, #40] ; (8000758 <MX_GPIO_Init+0xf0>)
8000730: f000 fb8e bl 8000e50 <HAL_GPIO_Init>
/*Configure GPIO pin : Door_Sensor_Pin */
GPIO_InitStruct.Pin = Door_Sensor_Pin;
8000734: 2380 movs r3, #128 ; 0x80
8000736: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000738: 2300 movs r3, #0
800073a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
800073c: 2301 movs r3, #1
800073e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(Door_Sensor_GPIO_Port, &GPIO_InitStruct);
8000740: f107 0314 add.w r3, r7, #20
8000744: 4619 mov r1, r3
8000746: 4804 ldr r0, [pc, #16] ; (8000758 <MX_GPIO_Init+0xf0>)
8000748: f000 fb82 bl 8000e50 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
800074c: bf00 nop
800074e: 3728 adds r7, #40 ; 0x28
8000750: 46bd mov sp, r7
8000752: bd80 pop {r7, pc}
8000754: 40023800 .word 0x40023800
8000758: 40020000 .word 0x40020000
800075c: 40020800 .word 0x40020800
08000760 <StartMainTask>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_StartMainTask */
void StartMainTask(void *argument)
{
8000760: b580 push {r7, lr}
8000762: b084 sub sp, #16
8000764: af00 add r7, sp, #0
8000766: 6078 str r0, [r7, #4]
/* USER CODE BEGIN 5 */
memset(uart_buffer, 0, 10);
8000768: 220a movs r2, #10
800076a: 2100 movs r1, #0
800076c: 4833 ldr r0, [pc, #204] ; (800083c <StartMainTask+0xdc>)
800076e: f004 fe75 bl 800545c <memset>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 1000)
8000772: 4b33 ldr r3, [pc, #204] ; (8000840 <StartMainTask+0xe0>)
8000774: 781b ldrb r3, [r3, #0]
8000776: 461a mov r2, r3
8000778: 4b30 ldr r3, [pc, #192] ; (800083c <StartMainTask+0xdc>)
800077a: 18d1 adds r1, r2, r3
800077c: f44f 737a mov.w r3, #1000 ; 0x3e8
8000780: 2201 movs r2, #1
8000782: 4830 ldr r0, [pc, #192] ; (8000844 <StartMainTask+0xe4>)
8000784: f001 fd43 bl 800220e <HAL_UART_Receive>
8000788: 4603 mov r3, r0
800078a: 2b00 cmp r3, #0
800078c: d152 bne.n 8000834 <StartMainTask+0xd4>
== HAL_OK) {
uart_index++;
800078e: 4b2c ldr r3, [pc, #176] ; (8000840 <StartMainTask+0xe0>)
8000790: 781b ldrb r3, [r3, #0]
8000792: 3301 adds r3, #1
8000794: b2da uxtb r2, r3
8000796: 4b2a ldr r3, [pc, #168] ; (8000840 <StartMainTask+0xe0>)
8000798: 701a strb r2, [r3, #0]
if (uart_buffer[uart_index - 1] == 0xFF) {
800079a: 4b29 ldr r3, [pc, #164] ; (8000840 <StartMainTask+0xe0>)
800079c: 781b ldrb r3, [r3, #0]
800079e: 3b01 subs r3, #1
80007a0: 4a26 ldr r2, [pc, #152] ; (800083c <StartMainTask+0xdc>)
80007a2: 5cd3 ldrb r3, [r2, r3]
80007a4: 2bff cmp r3, #255 ; 0xff
80007a6: d139 bne.n 800081c <StartMainTask+0xbc>
if (uart_index > 1) {
80007a8: 4b25 ldr r3, [pc, #148] ; (8000840 <StartMainTask+0xe0>)
80007aa: 781b ldrb r3, [r3, #0]
80007ac: 2b01 cmp r3, #1
80007ae: d92c bls.n 800080a <StartMainTask+0xaa>
//Command Internal LED
if (uart_buffer[0] == 0x00) {
80007b0: 4b22 ldr r3, [pc, #136] ; (800083c <StartMainTask+0xdc>)
80007b2: 781b ldrb r3, [r3, #0]
80007b4: 2b00 cmp r3, #0
80007b6: d107 bne.n 80007c8 <StartMainTask+0x68>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, uart_buffer[1]);
80007b8: 4b20 ldr r3, [pc, #128] ; (800083c <StartMainTask+0xdc>)
80007ba: 785b ldrb r3, [r3, #1]
80007bc: 461a mov r2, r3
80007be: 2120 movs r1, #32
80007c0: 4821 ldr r0, [pc, #132] ; (8000848 <StartMainTask+0xe8>)
80007c2: f000 fce1 bl 8001188 <HAL_GPIO_WritePin>
80007c6: e020 b.n 800080a <StartMainTask+0xaa>
}
// Get Current Door State
else if (uart_buffer[0] == 0x01) {
80007c8: 4b1c ldr r3, [pc, #112] ; (800083c <StartMainTask+0xdc>)
80007ca: 781b ldrb r3, [r3, #0]
80007cc: 2b01 cmp r3, #1
80007ce: d10f bne.n 80007f0 <StartMainTask+0x90>
uint8_t payload[3] = { 0x01, door_state, 0xFF };
80007d0: 2301 movs r3, #1
80007d2: 733b strb r3, [r7, #12]
80007d4: 4b1d ldr r3, [pc, #116] ; (800084c <StartMainTask+0xec>)
80007d6: 781b ldrb r3, [r3, #0]
80007d8: 737b strb r3, [r7, #13]
80007da: 23ff movs r3, #255 ; 0xff
80007dc: 73bb strb r3, [r7, #14]
HAL_UART_Transmit(&huart2, payload, 3, 1500);
80007de: f107 010c add.w r1, r7, #12
80007e2: f240 53dc movw r3, #1500 ; 0x5dc
80007e6: 2203 movs r2, #3
80007e8: 4816 ldr r0, [pc, #88] ; (8000844 <StartMainTask+0xe4>)
80007ea: f001 fc7e bl 80020ea <HAL_UART_Transmit>
80007ee: e00c b.n 800080a <StartMainTask+0xaa>
}
//
else if (uart_buffer[0] == 0x02) {
80007f0: 4b12 ldr r3, [pc, #72] ; (800083c <StartMainTask+0xdc>)
80007f2: 781b ldrb r3, [r3, #0]
80007f4: 2b02 cmp r3, #2
80007f6: d108 bne.n 800080a <StartMainTask+0xaa>
door_lock_state_command = uart_buffer[1];
80007f8: 4b10 ldr r3, [pc, #64] ; (800083c <StartMainTask+0xdc>)
80007fa: 785b ldrb r3, [r3, #1]
80007fc: 2b00 cmp r3, #0
80007fe: bf14 ite ne
8000800: 2301 movne r3, #1
8000802: 2300 moveq r3, #0
8000804: b2da uxtb r2, r3
8000806: 4b12 ldr r3, [pc, #72] ; (8000850 <StartMainTask+0xf0>)
8000808: 701a strb r2, [r3, #0]
}
}
uart_index = 0;
800080a: 4b0d ldr r3, [pc, #52] ; (8000840 <StartMainTask+0xe0>)
800080c: 2200 movs r2, #0
800080e: 701a strb r2, [r3, #0]
memset(uart_buffer, 0, 10);
8000810: 220a movs r2, #10
8000812: 2100 movs r1, #0
8000814: 4809 ldr r0, [pc, #36] ; (800083c <StartMainTask+0xdc>)
8000816: f004 fe21 bl 800545c <memset>
800081a: e00b b.n 8000834 <StartMainTask+0xd4>
} else if (uart_index > sizeof(uart_buffer)-1) {
800081c: 4b08 ldr r3, [pc, #32] ; (8000840 <StartMainTask+0xe0>)
800081e: 781b ldrb r3, [r3, #0]
8000820: 2b09 cmp r3, #9
8000822: d907 bls.n 8000834 <StartMainTask+0xd4>
memset(uart_buffer, 0, 10);
8000824: 220a movs r2, #10
8000826: 2100 movs r1, #0
8000828: 4804 ldr r0, [pc, #16] ; (800083c <StartMainTask+0xdc>)
800082a: f004 fe17 bl 800545c <memset>
uart_index=0;
800082e: 4b04 ldr r3, [pc, #16] ; (8000840 <StartMainTask+0xe0>)
8000830: 2200 movs r2, #0
8000832: 701a strb r2, [r3, #0]
}
}
vTaskDelay(1);
8000834: 2001 movs r0, #1
8000836: f003 f91b bl 8003a70 <vTaskDelay>
if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 1000)
800083a: e79a b.n 8000772 <StartMainTask+0x12>
800083c: 200000c8 .word 0x200000c8
8000840: 200000d2 .word 0x200000d2
8000844: 2000007c .word 0x2000007c
8000848: 40020000 .word 0x40020000
800084c: 200000d8 .word 0x200000d8
8000850: 200000da .word 0x200000da
08000854 <startDoorHandleTask>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_startDoorHandleTask */
void startDoorHandleTask(void *argument)
{
8000854: b580 push {r7, lr}
8000856: b082 sub sp, #8
8000858: af00 add r7, sp, #0
800085a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN startDoorHandleTask */
/* Infinite loop */
for (;;) {
door_state = HAL_GPIO_ReadPin(DOOR_SENSOR_BANK, DOOR_SENSOR_PIN);
800085c: 2180 movs r1, #128 ; 0x80
800085e: 4835 ldr r0, [pc, #212] ; (8000934 <startDoorHandleTask+0xe0>)
8000860: f000 fc7a bl 8001158 <HAL_GPIO_ReadPin>
8000864: 4603 mov r3, r0
8000866: 2b00 cmp r3, #0
8000868: bf14 ite ne
800086a: 2301 movne r3, #1
800086c: 2300 moveq r3, #0
800086e: b2da uxtb r2, r3
8000870: 4b31 ldr r3, [pc, #196] ; (8000938 <startDoorHandleTask+0xe4>)
8000872: 701a strb r2, [r3, #0]
if (door_lock_state != door_lock_state_command) {
8000874: 4b31 ldr r3, [pc, #196] ; (800093c <startDoorHandleTask+0xe8>)
8000876: 781a ldrb r2, [r3, #0]
8000878: 4b31 ldr r3, [pc, #196] ; (8000940 <startDoorHandleTask+0xec>)
800087a: 781b ldrb r3, [r3, #0]
800087c: 429a cmp r2, r3
800087e: d055 beq.n 800092c <startDoorHandleTask+0xd8>
if (door_lock_state_command == DOOR_LOCK_LOCKED) {
8000880: 4b2f ldr r3, [pc, #188] ; (8000940 <startDoorHandleTask+0xec>)
8000882: 781b ldrb r3, [r3, #0]
8000884: 2b00 cmp r3, #0
8000886: d041 beq.n 800090c <startDoorHandleTask+0xb8>
if (door_state == DOOR_STATE_CLOSED) {
8000888: 4b2b ldr r3, [pc, #172] ; (8000938 <startDoorHandleTask+0xe4>)
800088a: 781b ldrb r3, [r3, #0]
800088c: 2b00 cmp r3, #0
800088e: d009 beq.n 80008a4 <startDoorHandleTask+0x50>
HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, 1);
8000890: 2201 movs r2, #1
8000892: 2100 movs r1, #0
8000894: f44f 7000 mov.w r0, #512 ; 0x200
8000898: f000 fc76 bl 8001188 <HAL_GPIO_WritePin>
door_lock_state = DOOR_LOCK_LOCKED;
800089c: 4b27 ldr r3, [pc, #156] ; (800093c <startDoorHandleTask+0xe8>)
800089e: 2201 movs r2, #1
80008a0: 701a strb r2, [r3, #0]
80008a2: e043 b.n 800092c <startDoorHandleTask+0xd8>
} else {
if (!door_lock_waiting) {
80008a4: 4b27 ldr r3, [pc, #156] ; (8000944 <startDoorHandleTask+0xf0>)
80008a6: 781b ldrb r3, [r3, #0]
80008a8: f083 0301 eor.w r3, r3, #1
80008ac: b2db uxtb r3, r3
80008ae: 2b00 cmp r3, #0
80008b0: d008 beq.n 80008c4 <startDoorHandleTask+0x70>
door_lock_command_time = HAL_GetTick();
80008b2: f000 f9df bl 8000c74 <HAL_GetTick>
80008b6: 4603 mov r3, r0
80008b8: 4a23 ldr r2, [pc, #140] ; (8000948 <startDoorHandleTask+0xf4>)
80008ba: 6013 str r3, [r2, #0]
door_lock_waiting = true;
80008bc: 4b21 ldr r3, [pc, #132] ; (8000944 <startDoorHandleTask+0xf0>)
80008be: 2201 movs r2, #1
80008c0: 701a strb r2, [r3, #0]
80008c2: e033 b.n 800092c <startDoorHandleTask+0xd8>
} else {
if (door_state == DOOR_STATE_OPEN) {
80008c4: 4b1c ldr r3, [pc, #112] ; (8000938 <startDoorHandleTask+0xe4>)
80008c6: 781b ldrb r3, [r3, #0]
80008c8: f083 0301 eor.w r3, r3, #1
80008cc: b2db uxtb r3, r3
80008ce: 2b00 cmp r3, #0
80008d0: d012 beq.n 80008f8 <startDoorHandleTask+0xa4>
if (HAL_GetTick()
80008d2: f000 f9cf bl 8000c74 <HAL_GetTick>
80008d6: 4602 mov r2, r0
- door_lock_command_time>DOOR_ERROR_ALARM_DELAY) {
80008d8: 4b1b ldr r3, [pc, #108] ; (8000948 <startDoorHandleTask+0xf4>)
80008da: 681b ldr r3, [r3, #0]
80008dc: 1ad3 subs r3, r2, r3
if (HAL_GetTick()
80008de: f242 7210 movw r2, #10000 ; 0x2710
80008e2: 4293 cmp r3, r2
80008e4: d922 bls.n 800092c <startDoorHandleTask+0xd8>
alarm_active = true;
80008e6: 4b19 ldr r3, [pc, #100] ; (800094c <startDoorHandleTask+0xf8>)
80008e8: 2201 movs r2, #1
80008ea: 701a strb r2, [r3, #0]
HAL_GPIO_WritePin(ALARM_BANK, ALARM_PIN, 1);
80008ec: 2201 movs r2, #1
80008ee: 2101 movs r1, #1
80008f0: 4817 ldr r0, [pc, #92] ; (8000950 <startDoorHandleTask+0xfc>)
80008f2: f000 fc49 bl 8001188 <HAL_GPIO_WritePin>
80008f6: e019 b.n 800092c <startDoorHandleTask+0xd8>
}
} else {
HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, 1);
80008f8: 2201 movs r2, #1
80008fa: 2100 movs r1, #0
80008fc: f44f 7000 mov.w r0, #512 ; 0x200
8000900: f000 fc42 bl 8001188 <HAL_GPIO_WritePin>
door_lock_state = DOOR_LOCK_LOCKED;
8000904: 4b0d ldr r3, [pc, #52] ; (800093c <startDoorHandleTask+0xe8>)
8000906: 2201 movs r2, #1
8000908: 701a strb r2, [r3, #0]
800090a: e00f b.n 800092c <startDoorHandleTask+0xd8>
}
}
}
} else if (door_lock_state_command == DOOR_LOCK_UNLOCKED) {
800090c: 4b0c ldr r3, [pc, #48] ; (8000940 <startDoorHandleTask+0xec>)
800090e: 781b ldrb r3, [r3, #0]
8000910: f083 0301 eor.w r3, r3, #1
8000914: b2db uxtb r3, r3
8000916: 2b00 cmp r3, #0
8000918: d008 beq.n 800092c <startDoorHandleTask+0xd8>
HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, 0);
800091a: 2200 movs r2, #0
800091c: 2100 movs r1, #0
800091e: f44f 7000 mov.w r0, #512 ; 0x200
8000922: f000 fc31 bl 8001188 <HAL_GPIO_WritePin>
door_lock_state = DOOR_LOCK_UNLOCKED;
8000926: 4b05 ldr r3, [pc, #20] ; (800093c <startDoorHandleTask+0xe8>)
8000928: 2200 movs r2, #0
800092a: 701a strb r2, [r3, #0]
}
}
//HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, uart_buffer[1]);
vTaskDelay(100);
800092c: 2064 movs r0, #100 ; 0x64
800092e: f003 f89f bl 8003a70 <vTaskDelay>
door_state = HAL_GPIO_ReadPin(DOOR_SENSOR_BANK, DOOR_SENSOR_PIN);
8000932: e793 b.n 800085c <startDoorHandleTask+0x8>
8000934: 40020000 .word 0x40020000
8000938: 200000d8 .word 0x200000d8
800093c: 200000d9 .word 0x200000d9
8000940: 200000da .word 0x200000da
8000944: 200000db .word 0x200000db
8000948: 200000d4 .word 0x200000d4
800094c: 200000dc .word 0x200000dc
8000950: 40020800 .word 0x40020800
08000954 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8000954: b580 push {r7, lr}
8000956: b082 sub sp, #8
8000958: af00 add r7, sp, #0
800095a: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM1) {
800095c: 687b ldr r3, [r7, #4]
800095e: 681b ldr r3, [r3, #0]
8000960: 4a04 ldr r2, [pc, #16] ; (8000974 <HAL_TIM_PeriodElapsedCallback+0x20>)
8000962: 4293 cmp r3, r2
8000964: d101 bne.n 800096a <HAL_TIM_PeriodElapsedCallback+0x16>
HAL_IncTick();
8000966: f000 f971 bl 8000c4c <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
800096a: bf00 nop
800096c: 3708 adds r7, #8
800096e: 46bd mov sp, r7
8000970: bd80 pop {r7, pc}
8000972: bf00 nop
8000974: 40010000 .word 0x40010000
08000978 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8000978: b480 push {r7}
800097a: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
800097c: b672 cpsid i
}
800097e: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1) {
8000980: e7fe b.n 8000980 <Error_Handler+0x8>
...
08000984 <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8000984: b580 push {r7, lr}
8000986: b082 sub sp, #8
8000988: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
800098a: 2300 movs r3, #0
800098c: 607b str r3, [r7, #4]
800098e: 4b12 ldr r3, [pc, #72] ; (80009d8 <HAL_MspInit+0x54>)
8000990: 6c5b ldr r3, [r3, #68] ; 0x44
8000992: 4a11 ldr r2, [pc, #68] ; (80009d8 <HAL_MspInit+0x54>)
8000994: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000998: 6453 str r3, [r2, #68] ; 0x44
800099a: 4b0f ldr r3, [pc, #60] ; (80009d8 <HAL_MspInit+0x54>)
800099c: 6c5b ldr r3, [r3, #68] ; 0x44
800099e: f403 4380 and.w r3, r3, #16384 ; 0x4000
80009a2: 607b str r3, [r7, #4]
80009a4: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80009a6: 2300 movs r3, #0
80009a8: 603b str r3, [r7, #0]
80009aa: 4b0b ldr r3, [pc, #44] ; (80009d8 <HAL_MspInit+0x54>)
80009ac: 6c1b ldr r3, [r3, #64] ; 0x40
80009ae: 4a0a ldr r2, [pc, #40] ; (80009d8 <HAL_MspInit+0x54>)
80009b0: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80009b4: 6413 str r3, [r2, #64] ; 0x40
80009b6: 4b08 ldr r3, [pc, #32] ; (80009d8 <HAL_MspInit+0x54>)
80009b8: 6c1b ldr r3, [r3, #64] ; 0x40
80009ba: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80009be: 603b str r3, [r7, #0]
80009c0: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* PendSV_IRQn interrupt configuration */
HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
80009c2: 2200 movs r2, #0
80009c4: 210f movs r1, #15
80009c6: f06f 0001 mvn.w r0, #1
80009ca: f000 fa17 bl 8000dfc <HAL_NVIC_SetPriority>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80009ce: bf00 nop
80009d0: 3708 adds r7, #8
80009d2: 46bd mov sp, r7
80009d4: bd80 pop {r7, pc}
80009d6: bf00 nop
80009d8: 40023800 .word 0x40023800
080009dc <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
80009dc: b580 push {r7, lr}
80009de: b08a sub sp, #40 ; 0x28
80009e0: af00 add r7, sp, #0
80009e2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80009e4: f107 0314 add.w r3, r7, #20
80009e8: 2200 movs r2, #0
80009ea: 601a str r2, [r3, #0]
80009ec: 605a str r2, [r3, #4]
80009ee: 609a str r2, [r3, #8]
80009f0: 60da str r2, [r3, #12]
80009f2: 611a str r2, [r3, #16]
if(huart->Instance==USART2)
80009f4: 687b ldr r3, [r7, #4]
80009f6: 681b ldr r3, [r3, #0]
80009f8: 4a19 ldr r2, [pc, #100] ; (8000a60 <HAL_UART_MspInit+0x84>)
80009fa: 4293 cmp r3, r2
80009fc: d12b bne.n 8000a56 <HAL_UART_MspInit+0x7a>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
80009fe: 2300 movs r3, #0
8000a00: 613b str r3, [r7, #16]
8000a02: 4b18 ldr r3, [pc, #96] ; (8000a64 <HAL_UART_MspInit+0x88>)
8000a04: 6c1b ldr r3, [r3, #64] ; 0x40
8000a06: 4a17 ldr r2, [pc, #92] ; (8000a64 <HAL_UART_MspInit+0x88>)
8000a08: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000a0c: 6413 str r3, [r2, #64] ; 0x40
8000a0e: 4b15 ldr r3, [pc, #84] ; (8000a64 <HAL_UART_MspInit+0x88>)
8000a10: 6c1b ldr r3, [r3, #64] ; 0x40
8000a12: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000a16: 613b str r3, [r7, #16]
8000a18: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000a1a: 2300 movs r3, #0
8000a1c: 60fb str r3, [r7, #12]
8000a1e: 4b11 ldr r3, [pc, #68] ; (8000a64 <HAL_UART_MspInit+0x88>)
8000a20: 6b1b ldr r3, [r3, #48] ; 0x30
8000a22: 4a10 ldr r2, [pc, #64] ; (8000a64 <HAL_UART_MspInit+0x88>)
8000a24: f043 0301 orr.w r3, r3, #1
8000a28: 6313 str r3, [r2, #48] ; 0x30
8000a2a: 4b0e ldr r3, [pc, #56] ; (8000a64 <HAL_UART_MspInit+0x88>)
8000a2c: 6b1b ldr r3, [r3, #48] ; 0x30
8000a2e: f003 0301 and.w r3, r3, #1
8000a32: 60fb str r3, [r7, #12]
8000a34: 68fb ldr r3, [r7, #12]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
8000a36: 230c movs r3, #12
8000a38: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000a3a: 2302 movs r3, #2
8000a3c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000a3e: 2300 movs r3, #0
8000a40: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000a42: 2303 movs r3, #3
8000a44: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8000a46: 2307 movs r3, #7
8000a48: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000a4a: f107 0314 add.w r3, r7, #20
8000a4e: 4619 mov r1, r3
8000a50: 4805 ldr r0, [pc, #20] ; (8000a68 <HAL_UART_MspInit+0x8c>)
8000a52: f000 f9fd bl 8000e50 <HAL_GPIO_Init>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
8000a56: bf00 nop
8000a58: 3728 adds r7, #40 ; 0x28
8000a5a: 46bd mov sp, r7
8000a5c: bd80 pop {r7, pc}
8000a5e: bf00 nop
8000a60: 40004400 .word 0x40004400
8000a64: 40023800 .word 0x40023800
8000a68: 40020000 .word 0x40020000
08000a6c <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8000a6c: b580 push {r7, lr}
8000a6e: b08c sub sp, #48 ; 0x30
8000a70: af00 add r7, sp, #0
8000a72: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock = 0U;
8000a74: 2300 movs r3, #0
8000a76: 62bb str r3, [r7, #40] ; 0x28
uint32_t uwPrescalerValue = 0U;
8000a78: 2300 movs r3, #0
8000a7a: 627b str r3, [r7, #36] ; 0x24
uint32_t pFLatency;
HAL_StatusTypeDef status;
/* Enable TIM1 clock */
__HAL_RCC_TIM1_CLK_ENABLE();
8000a7c: 2300 movs r3, #0
8000a7e: 60bb str r3, [r7, #8]
8000a80: 4b2e ldr r3, [pc, #184] ; (8000b3c <HAL_InitTick+0xd0>)
8000a82: 6c5b ldr r3, [r3, #68] ; 0x44
8000a84: 4a2d ldr r2, [pc, #180] ; (8000b3c <HAL_InitTick+0xd0>)
8000a86: f043 0301 orr.w r3, r3, #1
8000a8a: 6453 str r3, [r2, #68] ; 0x44
8000a8c: 4b2b ldr r3, [pc, #172] ; (8000b3c <HAL_InitTick+0xd0>)
8000a8e: 6c5b ldr r3, [r3, #68] ; 0x44
8000a90: f003 0301 and.w r3, r3, #1
8000a94: 60bb str r3, [r7, #8]
8000a96: 68bb ldr r3, [r7, #8]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8000a98: f107 020c add.w r2, r7, #12
8000a9c: f107 0310 add.w r3, r7, #16
8000aa0: 4611 mov r1, r2
8000aa2: 4618 mov r0, r3
8000aa4: f001 f822 bl 8001aec <HAL_RCC_GetClockConfig>
/* Compute TIM1 clock */
uwTimclock = HAL_RCC_GetPCLK2Freq();
8000aa8: f001 f80c bl 8001ac4 <HAL_RCC_GetPCLK2Freq>
8000aac: 62b8 str r0, [r7, #40] ; 0x28
/* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
8000aae: 6abb ldr r3, [r7, #40] ; 0x28
8000ab0: 4a23 ldr r2, [pc, #140] ; (8000b40 <HAL_InitTick+0xd4>)
8000ab2: fba2 2303 umull r2, r3, r2, r3
8000ab6: 0c9b lsrs r3, r3, #18
8000ab8: 3b01 subs r3, #1
8000aba: 627b str r3, [r7, #36] ; 0x24
/* Initialize TIM1 */
htim1.Instance = TIM1;
8000abc: 4b21 ldr r3, [pc, #132] ; (8000b44 <HAL_InitTick+0xd8>)
8000abe: 4a22 ldr r2, [pc, #136] ; (8000b48 <HAL_InitTick+0xdc>)
8000ac0: 601a str r2, [r3, #0]
+ Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim1.Init.Period = (1000000U / 1000U) - 1U;
8000ac2: 4b20 ldr r3, [pc, #128] ; (8000b44 <HAL_InitTick+0xd8>)
8000ac4: f240 32e7 movw r2, #999 ; 0x3e7
8000ac8: 60da str r2, [r3, #12]
htim1.Init.Prescaler = uwPrescalerValue;
8000aca: 4a1e ldr r2, [pc, #120] ; (8000b44 <HAL_InitTick+0xd8>)
8000acc: 6a7b ldr r3, [r7, #36] ; 0x24
8000ace: 6053 str r3, [r2, #4]
htim1.Init.ClockDivision = 0;
8000ad0: 4b1c ldr r3, [pc, #112] ; (8000b44 <HAL_InitTick+0xd8>)
8000ad2: 2200 movs r2, #0
8000ad4: 611a str r2, [r3, #16]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8000ad6: 4b1b ldr r3, [pc, #108] ; (8000b44 <HAL_InitTick+0xd8>)
8000ad8: 2200 movs r2, #0
8000ada: 609a str r2, [r3, #8]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000adc: 4b19 ldr r3, [pc, #100] ; (8000b44 <HAL_InitTick+0xd8>)
8000ade: 2200 movs r2, #0
8000ae0: 619a str r2, [r3, #24]
status = HAL_TIM_Base_Init(&htim1);
8000ae2: 4818 ldr r0, [pc, #96] ; (8000b44 <HAL_InitTick+0xd8>)
8000ae4: f001 f834 bl 8001b50 <HAL_TIM_Base_Init>
8000ae8: 4603 mov r3, r0
8000aea: f887 302f strb.w r3, [r7, #47] ; 0x2f
if (status == HAL_OK)
8000aee: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
8000af2: 2b00 cmp r3, #0
8000af4: d11b bne.n 8000b2e <HAL_InitTick+0xc2>
{
/* Start the TIM time Base generation in interrupt mode */
status = HAL_TIM_Base_Start_IT(&htim1);
8000af6: 4813 ldr r0, [pc, #76] ; (8000b44 <HAL_InitTick+0xd8>)
8000af8: f001 f884 bl 8001c04 <HAL_TIM_Base_Start_IT>
8000afc: 4603 mov r3, r0
8000afe: f887 302f strb.w r3, [r7, #47] ; 0x2f
if (status == HAL_OK)
8000b02: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
8000b06: 2b00 cmp r3, #0
8000b08: d111 bne.n 8000b2e <HAL_InitTick+0xc2>
{
/* Enable the TIM1 global Interrupt */
HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
8000b0a: 2019 movs r0, #25
8000b0c: f000 f992 bl 8000e34 <HAL_NVIC_EnableIRQ>
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8000b10: 687b ldr r3, [r7, #4]
8000b12: 2b0f cmp r3, #15
8000b14: d808 bhi.n 8000b28 <HAL_InitTick+0xbc>
{
/* Configure the TIM IRQ priority */
HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, TickPriority, 0U);
8000b16: 2200 movs r2, #0
8000b18: 6879 ldr r1, [r7, #4]
8000b1a: 2019 movs r0, #25
8000b1c: f000 f96e bl 8000dfc <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8000b20: 4a0a ldr r2, [pc, #40] ; (8000b4c <HAL_InitTick+0xe0>)
8000b22: 687b ldr r3, [r7, #4]
8000b24: 6013 str r3, [r2, #0]
8000b26: e002 b.n 8000b2e <HAL_InitTick+0xc2>
}
else
{
status = HAL_ERROR;
8000b28: 2301 movs r3, #1
8000b2a: f887 302f strb.w r3, [r7, #47] ; 0x2f
}
}
}
/* Return function status */
return status;
8000b2e: f897 302f ldrb.w r3, [r7, #47] ; 0x2f
}
8000b32: 4618 mov r0, r3
8000b34: 3730 adds r7, #48 ; 0x30
8000b36: 46bd mov sp, r7
8000b38: bd80 pop {r7, pc}
8000b3a: bf00 nop
8000b3c: 40023800 .word 0x40023800
8000b40: 431bde83 .word 0x431bde83
8000b44: 200000e0 .word 0x200000e0
8000b48: 40010000 .word 0x40010000
8000b4c: 20000004 .word 0x20000004
08000b50 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8000b50: b480 push {r7}
8000b52: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8000b54: e7fe b.n 8000b54 <NMI_Handler+0x4>
08000b56 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
8000b56: b480 push {r7}
8000b58: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8000b5a: e7fe b.n 8000b5a <HardFault_Handler+0x4>
08000b5c <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8000b5c: b480 push {r7}
8000b5e: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8000b60: e7fe b.n 8000b60 <MemManage_Handler+0x4>
08000b62 <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
8000b62: b480 push {r7}
8000b64: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8000b66: e7fe b.n 8000b66 <BusFault_Handler+0x4>
08000b68 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8000b68: b480 push {r7}
8000b6a: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8000b6c: e7fe b.n 8000b6c <UsageFault_Handler+0x4>
08000b6e <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
8000b6e: b480 push {r7}
8000b70: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
8000b72: bf00 nop
8000b74: 46bd mov sp, r7
8000b76: f85d 7b04 ldr.w r7, [sp], #4
8000b7a: 4770 bx lr
08000b7c <TIM1_UP_TIM10_IRQHandler>:
/**
* @brief This function handles TIM1 update interrupt and TIM10 global interrupt.
*/
void TIM1_UP_TIM10_IRQHandler(void)
{
8000b7c: b580 push {r7, lr}
8000b7e: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */
/* USER CODE END TIM1_UP_TIM10_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
8000b80: 4802 ldr r0, [pc, #8] ; (8000b8c <TIM1_UP_TIM10_IRQHandler+0x10>)
8000b82: f001 f8a1 bl 8001cc8 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */
/* USER CODE END TIM1_UP_TIM10_IRQn 1 */
}
8000b86: bf00 nop
8000b88: bd80 pop {r7, pc}
8000b8a: bf00 nop
8000b8c: 200000e0 .word 0x200000e0
08000b90 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
8000b90: b480 push {r7}
8000b92: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
8000b94: 4b06 ldr r3, [pc, #24] ; (8000bb0 <SystemInit+0x20>)
8000b96: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
8000b9a: 4a05 ldr r2, [pc, #20] ; (8000bb0 <SystemInit+0x20>)
8000b9c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000ba0: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000ba4: bf00 nop
8000ba6: 46bd mov sp, r7
8000ba8: f85d 7b04 ldr.w r7, [sp], #4
8000bac: 4770 bx lr
8000bae: bf00 nop
8000bb0: e000ed00 .word 0xe000ed00
08000bb4 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8000bb4: f8df d034 ldr.w sp, [pc, #52] ; 8000bec <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000bb8: 480d ldr r0, [pc, #52] ; (8000bf0 <LoopFillZerobss+0x16>)
ldr r1, =_edata
8000bba: 490e ldr r1, [pc, #56] ; (8000bf4 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
8000bbc: 4a0e ldr r2, [pc, #56] ; (8000bf8 <LoopFillZerobss+0x1e>)
movs r3, #0
8000bbe: 2300 movs r3, #0
b LoopCopyDataInit
8000bc0: e002 b.n 8000bc8 <LoopCopyDataInit>
08000bc2 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000bc2: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000bc4: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000bc6: 3304 adds r3, #4
08000bc8 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000bc8: 18c4 adds r4, r0, r3
cmp r4, r1
8000bca: 428c cmp r4, r1
bcc CopyDataInit
8000bcc: d3f9 bcc.n 8000bc2 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8000bce: 4a0b ldr r2, [pc, #44] ; (8000bfc <LoopFillZerobss+0x22>)
ldr r4, =_ebss
8000bd0: 4c0b ldr r4, [pc, #44] ; (8000c00 <LoopFillZerobss+0x26>)
movs r3, #0
8000bd2: 2300 movs r3, #0
b LoopFillZerobss
8000bd4: e001 b.n 8000bda <LoopFillZerobss>
08000bd6 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000bd6: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000bd8: 3204 adds r2, #4
08000bda <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8000bda: 42a2 cmp r2, r4
bcc FillZerobss
8000bdc: d3fb bcc.n 8000bd6 <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
8000bde: f7ff ffd7 bl 8000b90 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000be2: f004 fc99 bl 8005518 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000be6: f7ff fc79 bl 80004dc <main>
bx lr
8000bea: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8000bec: 20020000 .word 0x20020000
ldr r0, =_sdata
8000bf0: 20000000 .word 0x20000000
ldr r1, =_edata
8000bf4: 20000060 .word 0x20000060
ldr r2, =_sidata
8000bf8: 080056e8 .word 0x080056e8
ldr r2, =_sbss
8000bfc: 20000060 .word 0x20000060
ldr r4, =_ebss
8000c00: 20004c54 .word 0x20004c54
08000c04 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000c04: e7fe b.n 8000c04 <ADC_IRQHandler>
...
08000c08 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000c08: b580 push {r7, lr}
8000c0a: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8000c0c: 4b0e ldr r3, [pc, #56] ; (8000c48 <HAL_Init+0x40>)
8000c0e: 681b ldr r3, [r3, #0]
8000c10: 4a0d ldr r2, [pc, #52] ; (8000c48 <HAL_Init+0x40>)
8000c12: f443 7300 orr.w r3, r3, #512 ; 0x200
8000c16: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8000c18: 4b0b ldr r3, [pc, #44] ; (8000c48 <HAL_Init+0x40>)
8000c1a: 681b ldr r3, [r3, #0]
8000c1c: 4a0a ldr r2, [pc, #40] ; (8000c48 <HAL_Init+0x40>)
8000c1e: f443 6380 orr.w r3, r3, #1024 ; 0x400
8000c22: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000c24: 4b08 ldr r3, [pc, #32] ; (8000c48 <HAL_Init+0x40>)
8000c26: 681b ldr r3, [r3, #0]
8000c28: 4a07 ldr r2, [pc, #28] ; (8000c48 <HAL_Init+0x40>)
8000c2a: f443 7380 orr.w r3, r3, #256 ; 0x100
8000c2e: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000c30: 2003 movs r0, #3
8000c32: f000 f8d8 bl 8000de6 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000c36: 200f movs r0, #15
8000c38: f7ff ff18 bl 8000a6c <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8000c3c: f7ff fea2 bl 8000984 <HAL_MspInit>
/* Return function status */
return HAL_OK;
8000c40: 2300 movs r3, #0
}
8000c42: 4618 mov r0, r3
8000c44: bd80 pop {r7, pc}
8000c46: bf00 nop
8000c48: 40023c00 .word 0x40023c00
08000c4c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000c4c: b480 push {r7}
8000c4e: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000c50: 4b06 ldr r3, [pc, #24] ; (8000c6c <HAL_IncTick+0x20>)
8000c52: 781b ldrb r3, [r3, #0]
8000c54: 461a mov r2, r3
8000c56: 4b06 ldr r3, [pc, #24] ; (8000c70 <HAL_IncTick+0x24>)
8000c58: 681b ldr r3, [r3, #0]
8000c5a: 4413 add r3, r2
8000c5c: 4a04 ldr r2, [pc, #16] ; (8000c70 <HAL_IncTick+0x24>)
8000c5e: 6013 str r3, [r2, #0]
}
8000c60: bf00 nop
8000c62: 46bd mov sp, r7
8000c64: f85d 7b04 ldr.w r7, [sp], #4
8000c68: 4770 bx lr
8000c6a: bf00 nop
8000c6c: 20000008 .word 0x20000008
8000c70: 20000128 .word 0x20000128
08000c74 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000c74: b480 push {r7}
8000c76: af00 add r7, sp, #0
return uwTick;
8000c78: 4b03 ldr r3, [pc, #12] ; (8000c88 <HAL_GetTick+0x14>)
8000c7a: 681b ldr r3, [r3, #0]
}
8000c7c: 4618 mov r0, r3
8000c7e: 46bd mov sp, r7
8000c80: f85d 7b04 ldr.w r7, [sp], #4
8000c84: 4770 bx lr
8000c86: bf00 nop
8000c88: 20000128 .word 0x20000128
08000c8c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000c8c: b480 push {r7}
8000c8e: b085 sub sp, #20
8000c90: af00 add r7, sp, #0
8000c92: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000c94: 687b ldr r3, [r7, #4]
8000c96: f003 0307 and.w r3, r3, #7
8000c9a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000c9c: 4b0c ldr r3, [pc, #48] ; (8000cd0 <__NVIC_SetPriorityGrouping+0x44>)
8000c9e: 68db ldr r3, [r3, #12]
8000ca0: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000ca2: 68ba ldr r2, [r7, #8]
8000ca4: f64f 03ff movw r3, #63743 ; 0xf8ff
8000ca8: 4013 ands r3, r2
8000caa: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000cac: 68fb ldr r3, [r7, #12]
8000cae: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000cb0: 68bb ldr r3, [r7, #8]
8000cb2: 4313 orrs r3, r2
reg_value = (reg_value |
8000cb4: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000cb8: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000cbc: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000cbe: 4a04 ldr r2, [pc, #16] ; (8000cd0 <__NVIC_SetPriorityGrouping+0x44>)
8000cc0: 68bb ldr r3, [r7, #8]
8000cc2: 60d3 str r3, [r2, #12]
}
8000cc4: bf00 nop
8000cc6: 3714 adds r7, #20
8000cc8: 46bd mov sp, r7
8000cca: f85d 7b04 ldr.w r7, [sp], #4
8000cce: 4770 bx lr
8000cd0: e000ed00 .word 0xe000ed00
08000cd4 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000cd4: b480 push {r7}
8000cd6: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000cd8: 4b04 ldr r3, [pc, #16] ; (8000cec <__NVIC_GetPriorityGrouping+0x18>)
8000cda: 68db ldr r3, [r3, #12]
8000cdc: 0a1b lsrs r3, r3, #8
8000cde: f003 0307 and.w r3, r3, #7
}
8000ce2: 4618 mov r0, r3
8000ce4: 46bd mov sp, r7
8000ce6: f85d 7b04 ldr.w r7, [sp], #4
8000cea: 4770 bx lr
8000cec: e000ed00 .word 0xe000ed00
08000cf0 <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000cf0: b480 push {r7}
8000cf2: b083 sub sp, #12
8000cf4: af00 add r7, sp, #0
8000cf6: 4603 mov r3, r0
8000cf8: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000cfa: f997 3007 ldrsb.w r3, [r7, #7]
8000cfe: 2b00 cmp r3, #0
8000d00: db0b blt.n 8000d1a <__NVIC_EnableIRQ+0x2a>
{
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8000d02: 79fb ldrb r3, [r7, #7]
8000d04: f003 021f and.w r2, r3, #31
8000d08: 4907 ldr r1, [pc, #28] ; (8000d28 <__NVIC_EnableIRQ+0x38>)
8000d0a: f997 3007 ldrsb.w r3, [r7, #7]
8000d0e: 095b lsrs r3, r3, #5
8000d10: 2001 movs r0, #1
8000d12: fa00 f202 lsl.w r2, r0, r2
8000d16: f841 2023 str.w r2, [r1, r3, lsl #2]
}
}
8000d1a: bf00 nop
8000d1c: 370c adds r7, #12
8000d1e: 46bd mov sp, r7
8000d20: f85d 7b04 ldr.w r7, [sp], #4
8000d24: 4770 bx lr
8000d26: bf00 nop
8000d28: e000e100 .word 0xe000e100
08000d2c <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000d2c: b480 push {r7}
8000d2e: b083 sub sp, #12
8000d30: af00 add r7, sp, #0
8000d32: 4603 mov r3, r0
8000d34: 6039 str r1, [r7, #0]
8000d36: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000d38: f997 3007 ldrsb.w r3, [r7, #7]
8000d3c: 2b00 cmp r3, #0
8000d3e: db0a blt.n 8000d56 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000d40: 683b ldr r3, [r7, #0]
8000d42: b2da uxtb r2, r3
8000d44: 490c ldr r1, [pc, #48] ; (8000d78 <__NVIC_SetPriority+0x4c>)
8000d46: f997 3007 ldrsb.w r3, [r7, #7]
8000d4a: 0112 lsls r2, r2, #4
8000d4c: b2d2 uxtb r2, r2
8000d4e: 440b add r3, r1
8000d50: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000d54: e00a b.n 8000d6c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000d56: 683b ldr r3, [r7, #0]
8000d58: b2da uxtb r2, r3
8000d5a: 4908 ldr r1, [pc, #32] ; (8000d7c <__NVIC_SetPriority+0x50>)
8000d5c: 79fb ldrb r3, [r7, #7]
8000d5e: f003 030f and.w r3, r3, #15
8000d62: 3b04 subs r3, #4
8000d64: 0112 lsls r2, r2, #4
8000d66: b2d2 uxtb r2, r2
8000d68: 440b add r3, r1
8000d6a: 761a strb r2, [r3, #24]
}
8000d6c: bf00 nop
8000d6e: 370c adds r7, #12
8000d70: 46bd mov sp, r7
8000d72: f85d 7b04 ldr.w r7, [sp], #4
8000d76: 4770 bx lr
8000d78: e000e100 .word 0xe000e100
8000d7c: e000ed00 .word 0xe000ed00
08000d80 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000d80: b480 push {r7}
8000d82: b089 sub sp, #36 ; 0x24
8000d84: af00 add r7, sp, #0
8000d86: 60f8 str r0, [r7, #12]
8000d88: 60b9 str r1, [r7, #8]
8000d8a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000d8c: 68fb ldr r3, [r7, #12]
8000d8e: f003 0307 and.w r3, r3, #7
8000d92: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000d94: 69fb ldr r3, [r7, #28]
8000d96: f1c3 0307 rsb r3, r3, #7
8000d9a: 2b04 cmp r3, #4
8000d9c: bf28 it cs
8000d9e: 2304 movcs r3, #4
8000da0: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000da2: 69fb ldr r3, [r7, #28]
8000da4: 3304 adds r3, #4
8000da6: 2b06 cmp r3, #6
8000da8: d902 bls.n 8000db0 <NVIC_EncodePriority+0x30>
8000daa: 69fb ldr r3, [r7, #28]
8000dac: 3b03 subs r3, #3
8000dae: e000 b.n 8000db2 <NVIC_EncodePriority+0x32>
8000db0: 2300 movs r3, #0
8000db2: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000db4: f04f 32ff mov.w r2, #4294967295
8000db8: 69bb ldr r3, [r7, #24]
8000dba: fa02 f303 lsl.w r3, r2, r3
8000dbe: 43da mvns r2, r3
8000dc0: 68bb ldr r3, [r7, #8]
8000dc2: 401a ands r2, r3
8000dc4: 697b ldr r3, [r7, #20]
8000dc6: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000dc8: f04f 31ff mov.w r1, #4294967295
8000dcc: 697b ldr r3, [r7, #20]
8000dce: fa01 f303 lsl.w r3, r1, r3
8000dd2: 43d9 mvns r1, r3
8000dd4: 687b ldr r3, [r7, #4]
8000dd6: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000dd8: 4313 orrs r3, r2
);
}
8000dda: 4618 mov r0, r3
8000ddc: 3724 adds r7, #36 ; 0x24
8000dde: 46bd mov sp, r7
8000de0: f85d 7b04 ldr.w r7, [sp], #4
8000de4: 4770 bx lr
08000de6 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000de6: b580 push {r7, lr}
8000de8: b082 sub sp, #8
8000dea: af00 add r7, sp, #0
8000dec: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000dee: 6878 ldr r0, [r7, #4]
8000df0: f7ff ff4c bl 8000c8c <__NVIC_SetPriorityGrouping>
}
8000df4: bf00 nop
8000df6: 3708 adds r7, #8
8000df8: 46bd mov sp, r7
8000dfa: bd80 pop {r7, pc}
08000dfc <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000dfc: b580 push {r7, lr}
8000dfe: b086 sub sp, #24
8000e00: af00 add r7, sp, #0
8000e02: 4603 mov r3, r0
8000e04: 60b9 str r1, [r7, #8]
8000e06: 607a str r2, [r7, #4]
8000e08: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8000e0a: 2300 movs r3, #0
8000e0c: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000e0e: f7ff ff61 bl 8000cd4 <__NVIC_GetPriorityGrouping>
8000e12: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000e14: 687a ldr r2, [r7, #4]
8000e16: 68b9 ldr r1, [r7, #8]
8000e18: 6978 ldr r0, [r7, #20]
8000e1a: f7ff ffb1 bl 8000d80 <NVIC_EncodePriority>
8000e1e: 4602 mov r2, r0
8000e20: f997 300f ldrsb.w r3, [r7, #15]
8000e24: 4611 mov r1, r2
8000e26: 4618 mov r0, r3
8000e28: f7ff ff80 bl 8000d2c <__NVIC_SetPriority>
}
8000e2c: bf00 nop
8000e2e: 3718 adds r7, #24
8000e30: 46bd mov sp, r7
8000e32: bd80 pop {r7, pc}
08000e34 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8000e34: b580 push {r7, lr}
8000e36: b082 sub sp, #8
8000e38: af00 add r7, sp, #0
8000e3a: 4603 mov r3, r0
8000e3c: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8000e3e: f997 3007 ldrsb.w r3, [r7, #7]
8000e42: 4618 mov r0, r3
8000e44: f7ff ff54 bl 8000cf0 <__NVIC_EnableIRQ>
}
8000e48: bf00 nop
8000e4a: 3708 adds r7, #8
8000e4c: 46bd mov sp, r7
8000e4e: bd80 pop {r7, pc}
08000e50 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000e50: b480 push {r7}
8000e52: b089 sub sp, #36 ; 0x24
8000e54: af00 add r7, sp, #0
8000e56: 6078 str r0, [r7, #4]
8000e58: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
8000e5a: 2300 movs r3, #0
8000e5c: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8000e5e: 2300 movs r3, #0
8000e60: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8000e62: 2300 movs r3, #0
8000e64: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
8000e66: 2300 movs r3, #0
8000e68: 61fb str r3, [r7, #28]
8000e6a: e159 b.n 8001120 <HAL_GPIO_Init+0x2d0>
{
/* Get the IO position */
ioposition = 0x01U << position;
8000e6c: 2201 movs r2, #1
8000e6e: 69fb ldr r3, [r7, #28]
8000e70: fa02 f303 lsl.w r3, r2, r3
8000e74: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8000e76: 683b ldr r3, [r7, #0]
8000e78: 681b ldr r3, [r3, #0]
8000e7a: 697a ldr r2, [r7, #20]
8000e7c: 4013 ands r3, r2
8000e7e: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8000e80: 693a ldr r2, [r7, #16]
8000e82: 697b ldr r3, [r7, #20]
8000e84: 429a cmp r2, r3
8000e86: f040 8148 bne.w 800111a <HAL_GPIO_Init+0x2ca>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8000e8a: 683b ldr r3, [r7, #0]
8000e8c: 685b ldr r3, [r3, #4]
8000e8e: f003 0303 and.w r3, r3, #3
8000e92: 2b01 cmp r3, #1
8000e94: d005 beq.n 8000ea2 <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000e96: 683b ldr r3, [r7, #0]
8000e98: 685b ldr r3, [r3, #4]
8000e9a: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8000e9e: 2b02 cmp r3, #2
8000ea0: d130 bne.n 8000f04 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000ea2: 687b ldr r3, [r7, #4]
8000ea4: 689b ldr r3, [r3, #8]
8000ea6: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8000ea8: 69fb ldr r3, [r7, #28]
8000eaa: 005b lsls r3, r3, #1
8000eac: 2203 movs r2, #3
8000eae: fa02 f303 lsl.w r3, r2, r3
8000eb2: 43db mvns r3, r3
8000eb4: 69ba ldr r2, [r7, #24]
8000eb6: 4013 ands r3, r2
8000eb8: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8000eba: 683b ldr r3, [r7, #0]
8000ebc: 68da ldr r2, [r3, #12]
8000ebe: 69fb ldr r3, [r7, #28]
8000ec0: 005b lsls r3, r3, #1
8000ec2: fa02 f303 lsl.w r3, r2, r3
8000ec6: 69ba ldr r2, [r7, #24]
8000ec8: 4313 orrs r3, r2
8000eca: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8000ecc: 687b ldr r3, [r7, #4]
8000ece: 69ba ldr r2, [r7, #24]
8000ed0: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000ed2: 687b ldr r3, [r7, #4]
8000ed4: 685b ldr r3, [r3, #4]
8000ed6: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8000ed8: 2201 movs r2, #1
8000eda: 69fb ldr r3, [r7, #28]
8000edc: fa02 f303 lsl.w r3, r2, r3
8000ee0: 43db mvns r3, r3
8000ee2: 69ba ldr r2, [r7, #24]
8000ee4: 4013 ands r3, r2
8000ee6: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000ee8: 683b ldr r3, [r7, #0]
8000eea: 685b ldr r3, [r3, #4]
8000eec: 091b lsrs r3, r3, #4
8000eee: f003 0201 and.w r2, r3, #1
8000ef2: 69fb ldr r3, [r7, #28]
8000ef4: fa02 f303 lsl.w r3, r2, r3
8000ef8: 69ba ldr r2, [r7, #24]
8000efa: 4313 orrs r3, r2
8000efc: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8000efe: 687b ldr r3, [r7, #4]
8000f00: 69ba ldr r2, [r7, #24]
8000f02: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000f04: 683b ldr r3, [r7, #0]
8000f06: 685b ldr r3, [r3, #4]
8000f08: f003 0303 and.w r3, r3, #3
8000f0c: 2b03 cmp r3, #3
8000f0e: d017 beq.n 8000f40 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000f10: 687b ldr r3, [r7, #4]
8000f12: 68db ldr r3, [r3, #12]
8000f14: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8000f16: 69fb ldr r3, [r7, #28]
8000f18: 005b lsls r3, r3, #1
8000f1a: 2203 movs r2, #3
8000f1c: fa02 f303 lsl.w r3, r2, r3
8000f20: 43db mvns r3, r3
8000f22: 69ba ldr r2, [r7, #24]
8000f24: 4013 ands r3, r2
8000f26: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8000f28: 683b ldr r3, [r7, #0]
8000f2a: 689a ldr r2, [r3, #8]
8000f2c: 69fb ldr r3, [r7, #28]
8000f2e: 005b lsls r3, r3, #1
8000f30: fa02 f303 lsl.w r3, r2, r3
8000f34: 69ba ldr r2, [r7, #24]
8000f36: 4313 orrs r3, r2
8000f38: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8000f3a: 687b ldr r3, [r7, #4]
8000f3c: 69ba ldr r2, [r7, #24]
8000f3e: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000f40: 683b ldr r3, [r7, #0]
8000f42: 685b ldr r3, [r3, #4]
8000f44: f003 0303 and.w r3, r3, #3
8000f48: 2b02 cmp r3, #2
8000f4a: d123 bne.n 8000f94 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8000f4c: 69fb ldr r3, [r7, #28]
8000f4e: 08da lsrs r2, r3, #3
8000f50: 687b ldr r3, [r7, #4]
8000f52: 3208 adds r2, #8
8000f54: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8000f58: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
8000f5a: 69fb ldr r3, [r7, #28]
8000f5c: f003 0307 and.w r3, r3, #7
8000f60: 009b lsls r3, r3, #2
8000f62: 220f movs r2, #15
8000f64: fa02 f303 lsl.w r3, r2, r3
8000f68: 43db mvns r3, r3
8000f6a: 69ba ldr r2, [r7, #24]
8000f6c: 4013 ands r3, r2
8000f6e: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8000f70: 683b ldr r3, [r7, #0]
8000f72: 691a ldr r2, [r3, #16]
8000f74: 69fb ldr r3, [r7, #28]
8000f76: f003 0307 and.w r3, r3, #7
8000f7a: 009b lsls r3, r3, #2
8000f7c: fa02 f303 lsl.w r3, r2, r3
8000f80: 69ba ldr r2, [r7, #24]
8000f82: 4313 orrs r3, r2
8000f84: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8000f86: 69fb ldr r3, [r7, #28]
8000f88: 08da lsrs r2, r3, #3
8000f8a: 687b ldr r3, [r7, #4]
8000f8c: 3208 adds r2, #8
8000f8e: 69b9 ldr r1, [r7, #24]
8000f90: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000f94: 687b ldr r3, [r7, #4]
8000f96: 681b ldr r3, [r3, #0]
8000f98: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
8000f9a: 69fb ldr r3, [r7, #28]
8000f9c: 005b lsls r3, r3, #1
8000f9e: 2203 movs r2, #3
8000fa0: fa02 f303 lsl.w r3, r2, r3
8000fa4: 43db mvns r3, r3
8000fa6: 69ba ldr r2, [r7, #24]
8000fa8: 4013 ands r3, r2
8000faa: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8000fac: 683b ldr r3, [r7, #0]
8000fae: 685b ldr r3, [r3, #4]
8000fb0: f003 0203 and.w r2, r3, #3
8000fb4: 69fb ldr r3, [r7, #28]
8000fb6: 005b lsls r3, r3, #1
8000fb8: fa02 f303 lsl.w r3, r2, r3
8000fbc: 69ba ldr r2, [r7, #24]
8000fbe: 4313 orrs r3, r2
8000fc0: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8000fc2: 687b ldr r3, [r7, #4]
8000fc4: 69ba ldr r2, [r7, #24]
8000fc6: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8000fc8: 683b ldr r3, [r7, #0]
8000fca: 685b ldr r3, [r3, #4]
8000fcc: f403 3340 and.w r3, r3, #196608 ; 0x30000
8000fd0: 2b00 cmp r3, #0
8000fd2: f000 80a2 beq.w 800111a <HAL_GPIO_Init+0x2ca>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000fd6: 2300 movs r3, #0
8000fd8: 60fb str r3, [r7, #12]
8000fda: 4b57 ldr r3, [pc, #348] ; (8001138 <HAL_GPIO_Init+0x2e8>)
8000fdc: 6c5b ldr r3, [r3, #68] ; 0x44
8000fde: 4a56 ldr r2, [pc, #344] ; (8001138 <HAL_GPIO_Init+0x2e8>)
8000fe0: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000fe4: 6453 str r3, [r2, #68] ; 0x44
8000fe6: 4b54 ldr r3, [pc, #336] ; (8001138 <HAL_GPIO_Init+0x2e8>)
8000fe8: 6c5b ldr r3, [r3, #68] ; 0x44
8000fea: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000fee: 60fb str r3, [r7, #12]
8000ff0: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8000ff2: 4a52 ldr r2, [pc, #328] ; (800113c <HAL_GPIO_Init+0x2ec>)
8000ff4: 69fb ldr r3, [r7, #28]
8000ff6: 089b lsrs r3, r3, #2
8000ff8: 3302 adds r3, #2
8000ffa: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000ffe: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8001000: 69fb ldr r3, [r7, #28]
8001002: f003 0303 and.w r3, r3, #3
8001006: 009b lsls r3, r3, #2
8001008: 220f movs r2, #15
800100a: fa02 f303 lsl.w r3, r2, r3
800100e: 43db mvns r3, r3
8001010: 69ba ldr r2, [r7, #24]
8001012: 4013 ands r3, r2
8001014: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8001016: 687b ldr r3, [r7, #4]
8001018: 4a49 ldr r2, [pc, #292] ; (8001140 <HAL_GPIO_Init+0x2f0>)
800101a: 4293 cmp r3, r2
800101c: d019 beq.n 8001052 <HAL_GPIO_Init+0x202>
800101e: 687b ldr r3, [r7, #4]
8001020: 4a48 ldr r2, [pc, #288] ; (8001144 <HAL_GPIO_Init+0x2f4>)
8001022: 4293 cmp r3, r2
8001024: d013 beq.n 800104e <HAL_GPIO_Init+0x1fe>
8001026: 687b ldr r3, [r7, #4]
8001028: 4a47 ldr r2, [pc, #284] ; (8001148 <HAL_GPIO_Init+0x2f8>)
800102a: 4293 cmp r3, r2
800102c: d00d beq.n 800104a <HAL_GPIO_Init+0x1fa>
800102e: 687b ldr r3, [r7, #4]
8001030: 4a46 ldr r2, [pc, #280] ; (800114c <HAL_GPIO_Init+0x2fc>)
8001032: 4293 cmp r3, r2
8001034: d007 beq.n 8001046 <HAL_GPIO_Init+0x1f6>
8001036: 687b ldr r3, [r7, #4]
8001038: 4a45 ldr r2, [pc, #276] ; (8001150 <HAL_GPIO_Init+0x300>)
800103a: 4293 cmp r3, r2
800103c: d101 bne.n 8001042 <HAL_GPIO_Init+0x1f2>
800103e: 2304 movs r3, #4
8001040: e008 b.n 8001054 <HAL_GPIO_Init+0x204>
8001042: 2307 movs r3, #7
8001044: e006 b.n 8001054 <HAL_GPIO_Init+0x204>
8001046: 2303 movs r3, #3
8001048: e004 b.n 8001054 <HAL_GPIO_Init+0x204>
800104a: 2302 movs r3, #2
800104c: e002 b.n 8001054 <HAL_GPIO_Init+0x204>
800104e: 2301 movs r3, #1
8001050: e000 b.n 8001054 <HAL_GPIO_Init+0x204>
8001052: 2300 movs r3, #0
8001054: 69fa ldr r2, [r7, #28]
8001056: f002 0203 and.w r2, r2, #3
800105a: 0092 lsls r2, r2, #2
800105c: 4093 lsls r3, r2
800105e: 69ba ldr r2, [r7, #24]
8001060: 4313 orrs r3, r2
8001062: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8001064: 4935 ldr r1, [pc, #212] ; (800113c <HAL_GPIO_Init+0x2ec>)
8001066: 69fb ldr r3, [r7, #28]
8001068: 089b lsrs r3, r3, #2
800106a: 3302 adds r3, #2
800106c: 69ba ldr r2, [r7, #24]
800106e: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8001072: 4b38 ldr r3, [pc, #224] ; (8001154 <HAL_GPIO_Init+0x304>)
8001074: 689b ldr r3, [r3, #8]
8001076: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8001078: 693b ldr r3, [r7, #16]
800107a: 43db mvns r3, r3
800107c: 69ba ldr r2, [r7, #24]
800107e: 4013 ands r3, r2
8001080: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8001082: 683b ldr r3, [r7, #0]
8001084: 685b ldr r3, [r3, #4]
8001086: f403 1380 and.w r3, r3, #1048576 ; 0x100000
800108a: 2b00 cmp r3, #0
800108c: d003 beq.n 8001096 <HAL_GPIO_Init+0x246>
{
temp |= iocurrent;
800108e: 69ba ldr r2, [r7, #24]
8001090: 693b ldr r3, [r7, #16]
8001092: 4313 orrs r3, r2
8001094: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8001096: 4a2f ldr r2, [pc, #188] ; (8001154 <HAL_GPIO_Init+0x304>)
8001098: 69bb ldr r3, [r7, #24]
800109a: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
800109c: 4b2d ldr r3, [pc, #180] ; (8001154 <HAL_GPIO_Init+0x304>)
800109e: 68db ldr r3, [r3, #12]
80010a0: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80010a2: 693b ldr r3, [r7, #16]
80010a4: 43db mvns r3, r3
80010a6: 69ba ldr r2, [r7, #24]
80010a8: 4013 ands r3, r2
80010aa: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
80010ac: 683b ldr r3, [r7, #0]
80010ae: 685b ldr r3, [r3, #4]
80010b0: f403 1300 and.w r3, r3, #2097152 ; 0x200000
80010b4: 2b00 cmp r3, #0
80010b6: d003 beq.n 80010c0 <HAL_GPIO_Init+0x270>
{
temp |= iocurrent;
80010b8: 69ba ldr r2, [r7, #24]
80010ba: 693b ldr r3, [r7, #16]
80010bc: 4313 orrs r3, r2
80010be: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
80010c0: 4a24 ldr r2, [pc, #144] ; (8001154 <HAL_GPIO_Init+0x304>)
80010c2: 69bb ldr r3, [r7, #24]
80010c4: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
80010c6: 4b23 ldr r3, [pc, #140] ; (8001154 <HAL_GPIO_Init+0x304>)
80010c8: 685b ldr r3, [r3, #4]
80010ca: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80010cc: 693b ldr r3, [r7, #16]
80010ce: 43db mvns r3, r3
80010d0: 69ba ldr r2, [r7, #24]
80010d2: 4013 ands r3, r2
80010d4: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
80010d6: 683b ldr r3, [r7, #0]
80010d8: 685b ldr r3, [r3, #4]
80010da: f403 3300 and.w r3, r3, #131072 ; 0x20000
80010de: 2b00 cmp r3, #0
80010e0: d003 beq.n 80010ea <HAL_GPIO_Init+0x29a>
{
temp |= iocurrent;
80010e2: 69ba ldr r2, [r7, #24]
80010e4: 693b ldr r3, [r7, #16]
80010e6: 4313 orrs r3, r2
80010e8: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
80010ea: 4a1a ldr r2, [pc, #104] ; (8001154 <HAL_GPIO_Init+0x304>)
80010ec: 69bb ldr r3, [r7, #24]
80010ee: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
80010f0: 4b18 ldr r3, [pc, #96] ; (8001154 <HAL_GPIO_Init+0x304>)
80010f2: 681b ldr r3, [r3, #0]
80010f4: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80010f6: 693b ldr r3, [r7, #16]
80010f8: 43db mvns r3, r3
80010fa: 69ba ldr r2, [r7, #24]
80010fc: 4013 ands r3, r2
80010fe: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8001100: 683b ldr r3, [r7, #0]
8001102: 685b ldr r3, [r3, #4]
8001104: f403 3380 and.w r3, r3, #65536 ; 0x10000
8001108: 2b00 cmp r3, #0
800110a: d003 beq.n 8001114 <HAL_GPIO_Init+0x2c4>
{
temp |= iocurrent;
800110c: 69ba ldr r2, [r7, #24]
800110e: 693b ldr r3, [r7, #16]
8001110: 4313 orrs r3, r2
8001112: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8001114: 4a0f ldr r2, [pc, #60] ; (8001154 <HAL_GPIO_Init+0x304>)
8001116: 69bb ldr r3, [r7, #24]
8001118: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
800111a: 69fb ldr r3, [r7, #28]
800111c: 3301 adds r3, #1
800111e: 61fb str r3, [r7, #28]
8001120: 69fb ldr r3, [r7, #28]
8001122: 2b0f cmp r3, #15
8001124: f67f aea2 bls.w 8000e6c <HAL_GPIO_Init+0x1c>
}
}
}
}
8001128: bf00 nop
800112a: bf00 nop
800112c: 3724 adds r7, #36 ; 0x24
800112e: 46bd mov sp, r7
8001130: f85d 7b04 ldr.w r7, [sp], #4
8001134: 4770 bx lr
8001136: bf00 nop
8001138: 40023800 .word 0x40023800
800113c: 40013800 .word 0x40013800
8001140: 40020000 .word 0x40020000
8001144: 40020400 .word 0x40020400
8001148: 40020800 .word 0x40020800
800114c: 40020c00 .word 0x40020c00
8001150: 40021000 .word 0x40021000
8001154: 40013c00 .word 0x40013c00
08001158 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8001158: b480 push {r7}
800115a: b085 sub sp, #20
800115c: af00 add r7, sp, #0
800115e: 6078 str r0, [r7, #4]
8001160: 460b mov r3, r1
8001162: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8001164: 687b ldr r3, [r7, #4]
8001166: 691a ldr r2, [r3, #16]
8001168: 887b ldrh r3, [r7, #2]
800116a: 4013 ands r3, r2
800116c: 2b00 cmp r3, #0
800116e: d002 beq.n 8001176 <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8001170: 2301 movs r3, #1
8001172: 73fb strb r3, [r7, #15]
8001174: e001 b.n 800117a <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8001176: 2300 movs r3, #0
8001178: 73fb strb r3, [r7, #15]
}
return bitstatus;
800117a: 7bfb ldrb r3, [r7, #15]
}
800117c: 4618 mov r0, r3
800117e: 3714 adds r7, #20
8001180: 46bd mov sp, r7
8001182: f85d 7b04 ldr.w r7, [sp], #4
8001186: 4770 bx lr
08001188 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8001188: b480 push {r7}
800118a: b083 sub sp, #12
800118c: af00 add r7, sp, #0
800118e: 6078 str r0, [r7, #4]
8001190: 460b mov r3, r1
8001192: 807b strh r3, [r7, #2]
8001194: 4613 mov r3, r2
8001196: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8001198: 787b ldrb r3, [r7, #1]
800119a: 2b00 cmp r3, #0
800119c: d003 beq.n 80011a6 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
800119e: 887a ldrh r2, [r7, #2]
80011a0: 687b ldr r3, [r7, #4]
80011a2: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
80011a4: e003 b.n 80011ae <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
80011a6: 887b ldrh r3, [r7, #2]
80011a8: 041a lsls r2, r3, #16
80011aa: 687b ldr r3, [r7, #4]
80011ac: 619a str r2, [r3, #24]
}
80011ae: bf00 nop
80011b0: 370c adds r7, #12
80011b2: 46bd mov sp, r7
80011b4: f85d 7b04 ldr.w r7, [sp], #4
80011b8: 4770 bx lr
...
080011bc <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80011bc: b580 push {r7, lr}
80011be: b086 sub sp, #24
80011c0: af00 add r7, sp, #0
80011c2: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
80011c4: 687b ldr r3, [r7, #4]
80011c6: 2b00 cmp r3, #0
80011c8: d101 bne.n 80011ce <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80011ca: 2301 movs r3, #1
80011cc: e267 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80011ce: 687b ldr r3, [r7, #4]
80011d0: 681b ldr r3, [r3, #0]
80011d2: f003 0301 and.w r3, r3, #1
80011d6: 2b00 cmp r3, #0
80011d8: d075 beq.n 80012c6 <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
80011da: 4b88 ldr r3, [pc, #544] ; (80013fc <HAL_RCC_OscConfig+0x240>)
80011dc: 689b ldr r3, [r3, #8]
80011de: f003 030c and.w r3, r3, #12
80011e2: 2b04 cmp r3, #4
80011e4: d00c beq.n 8001200 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80011e6: 4b85 ldr r3, [pc, #532] ; (80013fc <HAL_RCC_OscConfig+0x240>)
80011e8: 689b ldr r3, [r3, #8]
80011ea: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
80011ee: 2b08 cmp r3, #8
80011f0: d112 bne.n 8001218 <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
80011f2: 4b82 ldr r3, [pc, #520] ; (80013fc <HAL_RCC_OscConfig+0x240>)
80011f4: 685b ldr r3, [r3, #4]
80011f6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80011fa: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
80011fe: d10b bne.n 8001218 <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8001200: 4b7e ldr r3, [pc, #504] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001202: 681b ldr r3, [r3, #0]
8001204: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001208: 2b00 cmp r3, #0
800120a: d05b beq.n 80012c4 <HAL_RCC_OscConfig+0x108>
800120c: 687b ldr r3, [r7, #4]
800120e: 685b ldr r3, [r3, #4]
8001210: 2b00 cmp r3, #0
8001212: d157 bne.n 80012c4 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8001214: 2301 movs r3, #1
8001216: e242 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8001218: 687b ldr r3, [r7, #4]
800121a: 685b ldr r3, [r3, #4]
800121c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8001220: d106 bne.n 8001230 <HAL_RCC_OscConfig+0x74>
8001222: 4b76 ldr r3, [pc, #472] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001224: 681b ldr r3, [r3, #0]
8001226: 4a75 ldr r2, [pc, #468] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001228: f443 3380 orr.w r3, r3, #65536 ; 0x10000
800122c: 6013 str r3, [r2, #0]
800122e: e01d b.n 800126c <HAL_RCC_OscConfig+0xb0>
8001230: 687b ldr r3, [r7, #4]
8001232: 685b ldr r3, [r3, #4]
8001234: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8001238: d10c bne.n 8001254 <HAL_RCC_OscConfig+0x98>
800123a: 4b70 ldr r3, [pc, #448] ; (80013fc <HAL_RCC_OscConfig+0x240>)
800123c: 681b ldr r3, [r3, #0]
800123e: 4a6f ldr r2, [pc, #444] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001240: f443 2380 orr.w r3, r3, #262144 ; 0x40000
8001244: 6013 str r3, [r2, #0]
8001246: 4b6d ldr r3, [pc, #436] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001248: 681b ldr r3, [r3, #0]
800124a: 4a6c ldr r2, [pc, #432] ; (80013fc <HAL_RCC_OscConfig+0x240>)
800124c: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001250: 6013 str r3, [r2, #0]
8001252: e00b b.n 800126c <HAL_RCC_OscConfig+0xb0>
8001254: 4b69 ldr r3, [pc, #420] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001256: 681b ldr r3, [r3, #0]
8001258: 4a68 ldr r2, [pc, #416] ; (80013fc <HAL_RCC_OscConfig+0x240>)
800125a: f423 3380 bic.w r3, r3, #65536 ; 0x10000
800125e: 6013 str r3, [r2, #0]
8001260: 4b66 ldr r3, [pc, #408] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001262: 681b ldr r3, [r3, #0]
8001264: 4a65 ldr r2, [pc, #404] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001266: f423 2380 bic.w r3, r3, #262144 ; 0x40000
800126a: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
800126c: 687b ldr r3, [r7, #4]
800126e: 685b ldr r3, [r3, #4]
8001270: 2b00 cmp r3, #0
8001272: d013 beq.n 800129c <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001274: f7ff fcfe bl 8000c74 <HAL_GetTick>
8001278: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800127a: e008 b.n 800128e <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800127c: f7ff fcfa bl 8000c74 <HAL_GetTick>
8001280: 4602 mov r2, r0
8001282: 693b ldr r3, [r7, #16]
8001284: 1ad3 subs r3, r2, r3
8001286: 2b64 cmp r3, #100 ; 0x64
8001288: d901 bls.n 800128e <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
800128a: 2303 movs r3, #3
800128c: e207 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800128e: 4b5b ldr r3, [pc, #364] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001290: 681b ldr r3, [r3, #0]
8001292: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001296: 2b00 cmp r3, #0
8001298: d0f0 beq.n 800127c <HAL_RCC_OscConfig+0xc0>
800129a: e014 b.n 80012c6 <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800129c: f7ff fcea bl 8000c74 <HAL_GetTick>
80012a0: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80012a2: e008 b.n 80012b6 <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
80012a4: f7ff fce6 bl 8000c74 <HAL_GetTick>
80012a8: 4602 mov r2, r0
80012aa: 693b ldr r3, [r7, #16]
80012ac: 1ad3 subs r3, r2, r3
80012ae: 2b64 cmp r3, #100 ; 0x64
80012b0: d901 bls.n 80012b6 <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
80012b2: 2303 movs r3, #3
80012b4: e1f3 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
80012b6: 4b51 ldr r3, [pc, #324] ; (80013fc <HAL_RCC_OscConfig+0x240>)
80012b8: 681b ldr r3, [r3, #0]
80012ba: f403 3300 and.w r3, r3, #131072 ; 0x20000
80012be: 2b00 cmp r3, #0
80012c0: d1f0 bne.n 80012a4 <HAL_RCC_OscConfig+0xe8>
80012c2: e000 b.n 80012c6 <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80012c4: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80012c6: 687b ldr r3, [r7, #4]
80012c8: 681b ldr r3, [r3, #0]
80012ca: f003 0302 and.w r3, r3, #2
80012ce: 2b00 cmp r3, #0
80012d0: d063 beq.n 800139a <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
80012d2: 4b4a ldr r3, [pc, #296] ; (80013fc <HAL_RCC_OscConfig+0x240>)
80012d4: 689b ldr r3, [r3, #8]
80012d6: f003 030c and.w r3, r3, #12
80012da: 2b00 cmp r3, #0
80012dc: d00b beq.n 80012f6 <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80012de: 4b47 ldr r3, [pc, #284] ; (80013fc <HAL_RCC_OscConfig+0x240>)
80012e0: 689b ldr r3, [r3, #8]
80012e2: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
80012e6: 2b08 cmp r3, #8
80012e8: d11c bne.n 8001324 <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80012ea: 4b44 ldr r3, [pc, #272] ; (80013fc <HAL_RCC_OscConfig+0x240>)
80012ec: 685b ldr r3, [r3, #4]
80012ee: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80012f2: 2b00 cmp r3, #0
80012f4: d116 bne.n 8001324 <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80012f6: 4b41 ldr r3, [pc, #260] ; (80013fc <HAL_RCC_OscConfig+0x240>)
80012f8: 681b ldr r3, [r3, #0]
80012fa: f003 0302 and.w r3, r3, #2
80012fe: 2b00 cmp r3, #0
8001300: d005 beq.n 800130e <HAL_RCC_OscConfig+0x152>
8001302: 687b ldr r3, [r7, #4]
8001304: 68db ldr r3, [r3, #12]
8001306: 2b01 cmp r3, #1
8001308: d001 beq.n 800130e <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
800130a: 2301 movs r3, #1
800130c: e1c7 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
800130e: 4b3b ldr r3, [pc, #236] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001310: 681b ldr r3, [r3, #0]
8001312: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8001316: 687b ldr r3, [r7, #4]
8001318: 691b ldr r3, [r3, #16]
800131a: 00db lsls r3, r3, #3
800131c: 4937 ldr r1, [pc, #220] ; (80013fc <HAL_RCC_OscConfig+0x240>)
800131e: 4313 orrs r3, r2
8001320: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8001322: e03a b.n 800139a <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
8001324: 687b ldr r3, [r7, #4]
8001326: 68db ldr r3, [r3, #12]
8001328: 2b00 cmp r3, #0
800132a: d020 beq.n 800136e <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
800132c: 4b34 ldr r3, [pc, #208] ; (8001400 <HAL_RCC_OscConfig+0x244>)
800132e: 2201 movs r2, #1
8001330: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001332: f7ff fc9f bl 8000c74 <HAL_GetTick>
8001336: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001338: e008 b.n 800134c <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800133a: f7ff fc9b bl 8000c74 <HAL_GetTick>
800133e: 4602 mov r2, r0
8001340: 693b ldr r3, [r7, #16]
8001342: 1ad3 subs r3, r2, r3
8001344: 2b02 cmp r3, #2
8001346: d901 bls.n 800134c <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
8001348: 2303 movs r3, #3
800134a: e1a8 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800134c: 4b2b ldr r3, [pc, #172] ; (80013fc <HAL_RCC_OscConfig+0x240>)
800134e: 681b ldr r3, [r3, #0]
8001350: f003 0302 and.w r3, r3, #2
8001354: 2b00 cmp r3, #0
8001356: d0f0 beq.n 800133a <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001358: 4b28 ldr r3, [pc, #160] ; (80013fc <HAL_RCC_OscConfig+0x240>)
800135a: 681b ldr r3, [r3, #0]
800135c: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8001360: 687b ldr r3, [r7, #4]
8001362: 691b ldr r3, [r3, #16]
8001364: 00db lsls r3, r3, #3
8001366: 4925 ldr r1, [pc, #148] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001368: 4313 orrs r3, r2
800136a: 600b str r3, [r1, #0]
800136c: e015 b.n 800139a <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
800136e: 4b24 ldr r3, [pc, #144] ; (8001400 <HAL_RCC_OscConfig+0x244>)
8001370: 2200 movs r2, #0
8001372: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001374: f7ff fc7e bl 8000c74 <HAL_GetTick>
8001378: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800137a: e008 b.n 800138e <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
800137c: f7ff fc7a bl 8000c74 <HAL_GetTick>
8001380: 4602 mov r2, r0
8001382: 693b ldr r3, [r7, #16]
8001384: 1ad3 subs r3, r2, r3
8001386: 2b02 cmp r3, #2
8001388: d901 bls.n 800138e <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
800138a: 2303 movs r3, #3
800138c: e187 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
800138e: 4b1b ldr r3, [pc, #108] ; (80013fc <HAL_RCC_OscConfig+0x240>)
8001390: 681b ldr r3, [r3, #0]
8001392: f003 0302 and.w r3, r3, #2
8001396: 2b00 cmp r3, #0
8001398: d1f0 bne.n 800137c <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
800139a: 687b ldr r3, [r7, #4]
800139c: 681b ldr r3, [r3, #0]
800139e: f003 0308 and.w r3, r3, #8
80013a2: 2b00 cmp r3, #0
80013a4: d036 beq.n 8001414 <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
80013a6: 687b ldr r3, [r7, #4]
80013a8: 695b ldr r3, [r3, #20]
80013aa: 2b00 cmp r3, #0
80013ac: d016 beq.n 80013dc <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80013ae: 4b15 ldr r3, [pc, #84] ; (8001404 <HAL_RCC_OscConfig+0x248>)
80013b0: 2201 movs r2, #1
80013b2: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80013b4: f7ff fc5e bl 8000c74 <HAL_GetTick>
80013b8: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80013ba: e008 b.n 80013ce <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80013bc: f7ff fc5a bl 8000c74 <HAL_GetTick>
80013c0: 4602 mov r2, r0
80013c2: 693b ldr r3, [r7, #16]
80013c4: 1ad3 subs r3, r2, r3
80013c6: 2b02 cmp r3, #2
80013c8: d901 bls.n 80013ce <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
80013ca: 2303 movs r3, #3
80013cc: e167 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
80013ce: 4b0b ldr r3, [pc, #44] ; (80013fc <HAL_RCC_OscConfig+0x240>)
80013d0: 6f5b ldr r3, [r3, #116] ; 0x74
80013d2: f003 0302 and.w r3, r3, #2
80013d6: 2b00 cmp r3, #0
80013d8: d0f0 beq.n 80013bc <HAL_RCC_OscConfig+0x200>
80013da: e01b b.n 8001414 <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80013dc: 4b09 ldr r3, [pc, #36] ; (8001404 <HAL_RCC_OscConfig+0x248>)
80013de: 2200 movs r2, #0
80013e0: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80013e2: f7ff fc47 bl 8000c74 <HAL_GetTick>
80013e6: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80013e8: e00e b.n 8001408 <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80013ea: f7ff fc43 bl 8000c74 <HAL_GetTick>
80013ee: 4602 mov r2, r0
80013f0: 693b ldr r3, [r7, #16]
80013f2: 1ad3 subs r3, r2, r3
80013f4: 2b02 cmp r3, #2
80013f6: d907 bls.n 8001408 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
80013f8: 2303 movs r3, #3
80013fa: e150 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
80013fc: 40023800 .word 0x40023800
8001400: 42470000 .word 0x42470000
8001404: 42470e80 .word 0x42470e80
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8001408: 4b88 ldr r3, [pc, #544] ; (800162c <HAL_RCC_OscConfig+0x470>)
800140a: 6f5b ldr r3, [r3, #116] ; 0x74
800140c: f003 0302 and.w r3, r3, #2
8001410: 2b00 cmp r3, #0
8001412: d1ea bne.n 80013ea <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8001414: 687b ldr r3, [r7, #4]
8001416: 681b ldr r3, [r3, #0]
8001418: f003 0304 and.w r3, r3, #4
800141c: 2b00 cmp r3, #0
800141e: f000 8097 beq.w 8001550 <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
8001422: 2300 movs r3, #0
8001424: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8001426: 4b81 ldr r3, [pc, #516] ; (800162c <HAL_RCC_OscConfig+0x470>)
8001428: 6c1b ldr r3, [r3, #64] ; 0x40
800142a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800142e: 2b00 cmp r3, #0
8001430: d10f bne.n 8001452 <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
8001432: 2300 movs r3, #0
8001434: 60bb str r3, [r7, #8]
8001436: 4b7d ldr r3, [pc, #500] ; (800162c <HAL_RCC_OscConfig+0x470>)
8001438: 6c1b ldr r3, [r3, #64] ; 0x40
800143a: 4a7c ldr r2, [pc, #496] ; (800162c <HAL_RCC_OscConfig+0x470>)
800143c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001440: 6413 str r3, [r2, #64] ; 0x40
8001442: 4b7a ldr r3, [pc, #488] ; (800162c <HAL_RCC_OscConfig+0x470>)
8001444: 6c1b ldr r3, [r3, #64] ; 0x40
8001446: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
800144a: 60bb str r3, [r7, #8]
800144c: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
800144e: 2301 movs r3, #1
8001450: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001452: 4b77 ldr r3, [pc, #476] ; (8001630 <HAL_RCC_OscConfig+0x474>)
8001454: 681b ldr r3, [r3, #0]
8001456: f403 7380 and.w r3, r3, #256 ; 0x100
800145a: 2b00 cmp r3, #0
800145c: d118 bne.n 8001490 <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
800145e: 4b74 ldr r3, [pc, #464] ; (8001630 <HAL_RCC_OscConfig+0x474>)
8001460: 681b ldr r3, [r3, #0]
8001462: 4a73 ldr r2, [pc, #460] ; (8001630 <HAL_RCC_OscConfig+0x474>)
8001464: f443 7380 orr.w r3, r3, #256 ; 0x100
8001468: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
800146a: f7ff fc03 bl 8000c74 <HAL_GetTick>
800146e: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001470: e008 b.n 8001484 <HAL_RCC_OscConfig+0x2c8>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8001472: f7ff fbff bl 8000c74 <HAL_GetTick>
8001476: 4602 mov r2, r0
8001478: 693b ldr r3, [r7, #16]
800147a: 1ad3 subs r3, r2, r3
800147c: 2b02 cmp r3, #2
800147e: d901 bls.n 8001484 <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
8001480: 2303 movs r3, #3
8001482: e10c b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001484: 4b6a ldr r3, [pc, #424] ; (8001630 <HAL_RCC_OscConfig+0x474>)
8001486: 681b ldr r3, [r3, #0]
8001488: f403 7380 and.w r3, r3, #256 ; 0x100
800148c: 2b00 cmp r3, #0
800148e: d0f0 beq.n 8001472 <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001490: 687b ldr r3, [r7, #4]
8001492: 689b ldr r3, [r3, #8]
8001494: 2b01 cmp r3, #1
8001496: d106 bne.n 80014a6 <HAL_RCC_OscConfig+0x2ea>
8001498: 4b64 ldr r3, [pc, #400] ; (800162c <HAL_RCC_OscConfig+0x470>)
800149a: 6f1b ldr r3, [r3, #112] ; 0x70
800149c: 4a63 ldr r2, [pc, #396] ; (800162c <HAL_RCC_OscConfig+0x470>)
800149e: f043 0301 orr.w r3, r3, #1
80014a2: 6713 str r3, [r2, #112] ; 0x70
80014a4: e01c b.n 80014e0 <HAL_RCC_OscConfig+0x324>
80014a6: 687b ldr r3, [r7, #4]
80014a8: 689b ldr r3, [r3, #8]
80014aa: 2b05 cmp r3, #5
80014ac: d10c bne.n 80014c8 <HAL_RCC_OscConfig+0x30c>
80014ae: 4b5f ldr r3, [pc, #380] ; (800162c <HAL_RCC_OscConfig+0x470>)
80014b0: 6f1b ldr r3, [r3, #112] ; 0x70
80014b2: 4a5e ldr r2, [pc, #376] ; (800162c <HAL_RCC_OscConfig+0x470>)
80014b4: f043 0304 orr.w r3, r3, #4
80014b8: 6713 str r3, [r2, #112] ; 0x70
80014ba: 4b5c ldr r3, [pc, #368] ; (800162c <HAL_RCC_OscConfig+0x470>)
80014bc: 6f1b ldr r3, [r3, #112] ; 0x70
80014be: 4a5b ldr r2, [pc, #364] ; (800162c <HAL_RCC_OscConfig+0x470>)
80014c0: f043 0301 orr.w r3, r3, #1
80014c4: 6713 str r3, [r2, #112] ; 0x70
80014c6: e00b b.n 80014e0 <HAL_RCC_OscConfig+0x324>
80014c8: 4b58 ldr r3, [pc, #352] ; (800162c <HAL_RCC_OscConfig+0x470>)
80014ca: 6f1b ldr r3, [r3, #112] ; 0x70
80014cc: 4a57 ldr r2, [pc, #348] ; (800162c <HAL_RCC_OscConfig+0x470>)
80014ce: f023 0301 bic.w r3, r3, #1
80014d2: 6713 str r3, [r2, #112] ; 0x70
80014d4: 4b55 ldr r3, [pc, #340] ; (800162c <HAL_RCC_OscConfig+0x470>)
80014d6: 6f1b ldr r3, [r3, #112] ; 0x70
80014d8: 4a54 ldr r2, [pc, #336] ; (800162c <HAL_RCC_OscConfig+0x470>)
80014da: f023 0304 bic.w r3, r3, #4
80014de: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
80014e0: 687b ldr r3, [r7, #4]
80014e2: 689b ldr r3, [r3, #8]
80014e4: 2b00 cmp r3, #0
80014e6: d015 beq.n 8001514 <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80014e8: f7ff fbc4 bl 8000c74 <HAL_GetTick>
80014ec: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80014ee: e00a b.n 8001506 <HAL_RCC_OscConfig+0x34a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80014f0: f7ff fbc0 bl 8000c74 <HAL_GetTick>
80014f4: 4602 mov r2, r0
80014f6: 693b ldr r3, [r7, #16]
80014f8: 1ad3 subs r3, r2, r3
80014fa: f241 3288 movw r2, #5000 ; 0x1388
80014fe: 4293 cmp r3, r2
8001500: d901 bls.n 8001506 <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
8001502: 2303 movs r3, #3
8001504: e0cb b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8001506: 4b49 ldr r3, [pc, #292] ; (800162c <HAL_RCC_OscConfig+0x470>)
8001508: 6f1b ldr r3, [r3, #112] ; 0x70
800150a: f003 0302 and.w r3, r3, #2
800150e: 2b00 cmp r3, #0
8001510: d0ee beq.n 80014f0 <HAL_RCC_OscConfig+0x334>
8001512: e014 b.n 800153e <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001514: f7ff fbae bl 8000c74 <HAL_GetTick>
8001518: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800151a: e00a b.n 8001532 <HAL_RCC_OscConfig+0x376>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
800151c: f7ff fbaa bl 8000c74 <HAL_GetTick>
8001520: 4602 mov r2, r0
8001522: 693b ldr r3, [r7, #16]
8001524: 1ad3 subs r3, r2, r3
8001526: f241 3288 movw r2, #5000 ; 0x1388
800152a: 4293 cmp r3, r2
800152c: d901 bls.n 8001532 <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
800152e: 2303 movs r3, #3
8001530: e0b5 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8001532: 4b3e ldr r3, [pc, #248] ; (800162c <HAL_RCC_OscConfig+0x470>)
8001534: 6f1b ldr r3, [r3, #112] ; 0x70
8001536: f003 0302 and.w r3, r3, #2
800153a: 2b00 cmp r3, #0
800153c: d1ee bne.n 800151c <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
800153e: 7dfb ldrb r3, [r7, #23]
8001540: 2b01 cmp r3, #1
8001542: d105 bne.n 8001550 <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
8001544: 4b39 ldr r3, [pc, #228] ; (800162c <HAL_RCC_OscConfig+0x470>)
8001546: 6c1b ldr r3, [r3, #64] ; 0x40
8001548: 4a38 ldr r2, [pc, #224] ; (800162c <HAL_RCC_OscConfig+0x470>)
800154a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
800154e: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001550: 687b ldr r3, [r7, #4]
8001552: 699b ldr r3, [r3, #24]
8001554: 2b00 cmp r3, #0
8001556: f000 80a1 beq.w 800169c <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
800155a: 4b34 ldr r3, [pc, #208] ; (800162c <HAL_RCC_OscConfig+0x470>)
800155c: 689b ldr r3, [r3, #8]
800155e: f003 030c and.w r3, r3, #12
8001562: 2b08 cmp r3, #8
8001564: d05c beq.n 8001620 <HAL_RCC_OscConfig+0x464>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8001566: 687b ldr r3, [r7, #4]
8001568: 699b ldr r3, [r3, #24]
800156a: 2b02 cmp r3, #2
800156c: d141 bne.n 80015f2 <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800156e: 4b31 ldr r3, [pc, #196] ; (8001634 <HAL_RCC_OscConfig+0x478>)
8001570: 2200 movs r2, #0
8001572: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001574: f7ff fb7e bl 8000c74 <HAL_GetTick>
8001578: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800157a: e008 b.n 800158e <HAL_RCC_OscConfig+0x3d2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800157c: f7ff fb7a bl 8000c74 <HAL_GetTick>
8001580: 4602 mov r2, r0
8001582: 693b ldr r3, [r7, #16]
8001584: 1ad3 subs r3, r2, r3
8001586: 2b02 cmp r3, #2
8001588: d901 bls.n 800158e <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
800158a: 2303 movs r3, #3
800158c: e087 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800158e: 4b27 ldr r3, [pc, #156] ; (800162c <HAL_RCC_OscConfig+0x470>)
8001590: 681b ldr r3, [r3, #0]
8001592: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001596: 2b00 cmp r3, #0
8001598: d1f0 bne.n 800157c <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
800159a: 687b ldr r3, [r7, #4]
800159c: 69da ldr r2, [r3, #28]
800159e: 687b ldr r3, [r7, #4]
80015a0: 6a1b ldr r3, [r3, #32]
80015a2: 431a orrs r2, r3
80015a4: 687b ldr r3, [r7, #4]
80015a6: 6a5b ldr r3, [r3, #36] ; 0x24
80015a8: 019b lsls r3, r3, #6
80015aa: 431a orrs r2, r3
80015ac: 687b ldr r3, [r7, #4]
80015ae: 6a9b ldr r3, [r3, #40] ; 0x28
80015b0: 085b lsrs r3, r3, #1
80015b2: 3b01 subs r3, #1
80015b4: 041b lsls r3, r3, #16
80015b6: 431a orrs r2, r3
80015b8: 687b ldr r3, [r7, #4]
80015ba: 6adb ldr r3, [r3, #44] ; 0x2c
80015bc: 061b lsls r3, r3, #24
80015be: 491b ldr r1, [pc, #108] ; (800162c <HAL_RCC_OscConfig+0x470>)
80015c0: 4313 orrs r3, r2
80015c2: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80015c4: 4b1b ldr r3, [pc, #108] ; (8001634 <HAL_RCC_OscConfig+0x478>)
80015c6: 2201 movs r2, #1
80015c8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80015ca: f7ff fb53 bl 8000c74 <HAL_GetTick>
80015ce: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80015d0: e008 b.n 80015e4 <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80015d2: f7ff fb4f bl 8000c74 <HAL_GetTick>
80015d6: 4602 mov r2, r0
80015d8: 693b ldr r3, [r7, #16]
80015da: 1ad3 subs r3, r2, r3
80015dc: 2b02 cmp r3, #2
80015de: d901 bls.n 80015e4 <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
80015e0: 2303 movs r3, #3
80015e2: e05c b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80015e4: 4b11 ldr r3, [pc, #68] ; (800162c <HAL_RCC_OscConfig+0x470>)
80015e6: 681b ldr r3, [r3, #0]
80015e8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80015ec: 2b00 cmp r3, #0
80015ee: d0f0 beq.n 80015d2 <HAL_RCC_OscConfig+0x416>
80015f0: e054 b.n 800169c <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80015f2: 4b10 ldr r3, [pc, #64] ; (8001634 <HAL_RCC_OscConfig+0x478>)
80015f4: 2200 movs r2, #0
80015f6: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80015f8: f7ff fb3c bl 8000c74 <HAL_GetTick>
80015fc: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80015fe: e008 b.n 8001612 <HAL_RCC_OscConfig+0x456>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001600: f7ff fb38 bl 8000c74 <HAL_GetTick>
8001604: 4602 mov r2, r0
8001606: 693b ldr r3, [r7, #16]
8001608: 1ad3 subs r3, r2, r3
800160a: 2b02 cmp r3, #2
800160c: d901 bls.n 8001612 <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
800160e: 2303 movs r3, #3
8001610: e045 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001612: 4b06 ldr r3, [pc, #24] ; (800162c <HAL_RCC_OscConfig+0x470>)
8001614: 681b ldr r3, [r3, #0]
8001616: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800161a: 2b00 cmp r3, #0
800161c: d1f0 bne.n 8001600 <HAL_RCC_OscConfig+0x444>
800161e: e03d b.n 800169c <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8001620: 687b ldr r3, [r7, #4]
8001622: 699b ldr r3, [r3, #24]
8001624: 2b01 cmp r3, #1
8001626: d107 bne.n 8001638 <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
8001628: 2301 movs r3, #1
800162a: e038 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
800162c: 40023800 .word 0x40023800
8001630: 40007000 .word 0x40007000
8001634: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8001638: 4b1b ldr r3, [pc, #108] ; (80016a8 <HAL_RCC_OscConfig+0x4ec>)
800163a: 685b ldr r3, [r3, #4]
800163c: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
800163e: 687b ldr r3, [r7, #4]
8001640: 699b ldr r3, [r3, #24]
8001642: 2b01 cmp r3, #1
8001644: d028 beq.n 8001698 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001646: 68fb ldr r3, [r7, #12]
8001648: f403 0280 and.w r2, r3, #4194304 ; 0x400000
800164c: 687b ldr r3, [r7, #4]
800164e: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001650: 429a cmp r2, r3
8001652: d121 bne.n 8001698 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001654: 68fb ldr r3, [r7, #12]
8001656: f003 023f and.w r2, r3, #63 ; 0x3f
800165a: 687b ldr r3, [r7, #4]
800165c: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800165e: 429a cmp r2, r3
8001660: d11a bne.n 8001698 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8001662: 68fa ldr r2, [r7, #12]
8001664: f647 73c0 movw r3, #32704 ; 0x7fc0
8001668: 4013 ands r3, r2
800166a: 687a ldr r2, [r7, #4]
800166c: 6a52 ldr r2, [r2, #36] ; 0x24
800166e: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001670: 4293 cmp r3, r2
8001672: d111 bne.n 8001698 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8001674: 68fb ldr r3, [r7, #12]
8001676: f403 3240 and.w r2, r3, #196608 ; 0x30000
800167a: 687b ldr r3, [r7, #4]
800167c: 6a9b ldr r3, [r3, #40] ; 0x28
800167e: 085b lsrs r3, r3, #1
8001680: 3b01 subs r3, #1
8001682: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8001684: 429a cmp r2, r3
8001686: d107 bne.n 8001698 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8001688: 68fb ldr r3, [r7, #12]
800168a: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
800168e: 687b ldr r3, [r7, #4]
8001690: 6adb ldr r3, [r3, #44] ; 0x2c
8001692: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8001694: 429a cmp r2, r3
8001696: d001 beq.n 800169c <HAL_RCC_OscConfig+0x4e0>
#endif
{
return HAL_ERROR;
8001698: 2301 movs r3, #1
800169a: e000 b.n 800169e <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
800169c: 2300 movs r3, #0
}
800169e: 4618 mov r0, r3
80016a0: 3718 adds r7, #24
80016a2: 46bd mov sp, r7
80016a4: bd80 pop {r7, pc}
80016a6: bf00 nop
80016a8: 40023800 .word 0x40023800
080016ac <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
80016ac: b580 push {r7, lr}
80016ae: b084 sub sp, #16
80016b0: af00 add r7, sp, #0
80016b2: 6078 str r0, [r7, #4]
80016b4: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
80016b6: 687b ldr r3, [r7, #4]
80016b8: 2b00 cmp r3, #0
80016ba: d101 bne.n 80016c0 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80016bc: 2301 movs r3, #1
80016be: e0cc b.n 800185a <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80016c0: 4b68 ldr r3, [pc, #416] ; (8001864 <HAL_RCC_ClockConfig+0x1b8>)
80016c2: 681b ldr r3, [r3, #0]
80016c4: f003 0307 and.w r3, r3, #7
80016c8: 683a ldr r2, [r7, #0]
80016ca: 429a cmp r2, r3
80016cc: d90c bls.n 80016e8 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80016ce: 4b65 ldr r3, [pc, #404] ; (8001864 <HAL_RCC_ClockConfig+0x1b8>)
80016d0: 683a ldr r2, [r7, #0]
80016d2: b2d2 uxtb r2, r2
80016d4: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80016d6: 4b63 ldr r3, [pc, #396] ; (8001864 <HAL_RCC_ClockConfig+0x1b8>)
80016d8: 681b ldr r3, [r3, #0]
80016da: f003 0307 and.w r3, r3, #7
80016de: 683a ldr r2, [r7, #0]
80016e0: 429a cmp r2, r3
80016e2: d001 beq.n 80016e8 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
80016e4: 2301 movs r3, #1
80016e6: e0b8 b.n 800185a <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80016e8: 687b ldr r3, [r7, #4]
80016ea: 681b ldr r3, [r3, #0]
80016ec: f003 0302 and.w r3, r3, #2
80016f0: 2b00 cmp r3, #0
80016f2: d020 beq.n 8001736 <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80016f4: 687b ldr r3, [r7, #4]
80016f6: 681b ldr r3, [r3, #0]
80016f8: f003 0304 and.w r3, r3, #4
80016fc: 2b00 cmp r3, #0
80016fe: d005 beq.n 800170c <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8001700: 4b59 ldr r3, [pc, #356] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
8001702: 689b ldr r3, [r3, #8]
8001704: 4a58 ldr r2, [pc, #352] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
8001706: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
800170a: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
800170c: 687b ldr r3, [r7, #4]
800170e: 681b ldr r3, [r3, #0]
8001710: f003 0308 and.w r3, r3, #8
8001714: 2b00 cmp r3, #0
8001716: d005 beq.n 8001724 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8001718: 4b53 ldr r3, [pc, #332] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
800171a: 689b ldr r3, [r3, #8]
800171c: 4a52 ldr r2, [pc, #328] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
800171e: f443 4360 orr.w r3, r3, #57344 ; 0xe000
8001722: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8001724: 4b50 ldr r3, [pc, #320] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
8001726: 689b ldr r3, [r3, #8]
8001728: f023 02f0 bic.w r2, r3, #240 ; 0xf0
800172c: 687b ldr r3, [r7, #4]
800172e: 689b ldr r3, [r3, #8]
8001730: 494d ldr r1, [pc, #308] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
8001732: 4313 orrs r3, r2
8001734: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8001736: 687b ldr r3, [r7, #4]
8001738: 681b ldr r3, [r3, #0]
800173a: f003 0301 and.w r3, r3, #1
800173e: 2b00 cmp r3, #0
8001740: d044 beq.n 80017cc <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8001742: 687b ldr r3, [r7, #4]
8001744: 685b ldr r3, [r3, #4]
8001746: 2b01 cmp r3, #1
8001748: d107 bne.n 800175a <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800174a: 4b47 ldr r3, [pc, #284] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
800174c: 681b ldr r3, [r3, #0]
800174e: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001752: 2b00 cmp r3, #0
8001754: d119 bne.n 800178a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001756: 2301 movs r3, #1
8001758: e07f b.n 800185a <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
800175a: 687b ldr r3, [r7, #4]
800175c: 685b ldr r3, [r3, #4]
800175e: 2b02 cmp r3, #2
8001760: d003 beq.n 800176a <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
8001762: 687b ldr r3, [r7, #4]
8001764: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8001766: 2b03 cmp r3, #3
8001768: d107 bne.n 800177a <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800176a: 4b3f ldr r3, [pc, #252] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
800176c: 681b ldr r3, [r3, #0]
800176e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
8001772: 2b00 cmp r3, #0
8001774: d109 bne.n 800178a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001776: 2301 movs r3, #1
8001778: e06f b.n 800185a <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800177a: 4b3b ldr r3, [pc, #236] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
800177c: 681b ldr r3, [r3, #0]
800177e: f003 0302 and.w r3, r3, #2
8001782: 2b00 cmp r3, #0
8001784: d101 bne.n 800178a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8001786: 2301 movs r3, #1
8001788: e067 b.n 800185a <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800178a: 4b37 ldr r3, [pc, #220] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
800178c: 689b ldr r3, [r3, #8]
800178e: f023 0203 bic.w r2, r3, #3
8001792: 687b ldr r3, [r7, #4]
8001794: 685b ldr r3, [r3, #4]
8001796: 4934 ldr r1, [pc, #208] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
8001798: 4313 orrs r3, r2
800179a: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
800179c: f7ff fa6a bl 8000c74 <HAL_GetTick>
80017a0: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80017a2: e00a b.n 80017ba <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
80017a4: f7ff fa66 bl 8000c74 <HAL_GetTick>
80017a8: 4602 mov r2, r0
80017aa: 68fb ldr r3, [r7, #12]
80017ac: 1ad3 subs r3, r2, r3
80017ae: f241 3288 movw r2, #5000 ; 0x1388
80017b2: 4293 cmp r3, r2
80017b4: d901 bls.n 80017ba <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80017b6: 2303 movs r3, #3
80017b8: e04f b.n 800185a <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80017ba: 4b2b ldr r3, [pc, #172] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
80017bc: 689b ldr r3, [r3, #8]
80017be: f003 020c and.w r2, r3, #12
80017c2: 687b ldr r3, [r7, #4]
80017c4: 685b ldr r3, [r3, #4]
80017c6: 009b lsls r3, r3, #2
80017c8: 429a cmp r2, r3
80017ca: d1eb bne.n 80017a4 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80017cc: 4b25 ldr r3, [pc, #148] ; (8001864 <HAL_RCC_ClockConfig+0x1b8>)
80017ce: 681b ldr r3, [r3, #0]
80017d0: f003 0307 and.w r3, r3, #7
80017d4: 683a ldr r2, [r7, #0]
80017d6: 429a cmp r2, r3
80017d8: d20c bcs.n 80017f4 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80017da: 4b22 ldr r3, [pc, #136] ; (8001864 <HAL_RCC_ClockConfig+0x1b8>)
80017dc: 683a ldr r2, [r7, #0]
80017de: b2d2 uxtb r2, r2
80017e0: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80017e2: 4b20 ldr r3, [pc, #128] ; (8001864 <HAL_RCC_ClockConfig+0x1b8>)
80017e4: 681b ldr r3, [r3, #0]
80017e6: f003 0307 and.w r3, r3, #7
80017ea: 683a ldr r2, [r7, #0]
80017ec: 429a cmp r2, r3
80017ee: d001 beq.n 80017f4 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
80017f0: 2301 movs r3, #1
80017f2: e032 b.n 800185a <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80017f4: 687b ldr r3, [r7, #4]
80017f6: 681b ldr r3, [r3, #0]
80017f8: f003 0304 and.w r3, r3, #4
80017fc: 2b00 cmp r3, #0
80017fe: d008 beq.n 8001812 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8001800: 4b19 ldr r3, [pc, #100] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
8001802: 689b ldr r3, [r3, #8]
8001804: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
8001808: 687b ldr r3, [r7, #4]
800180a: 68db ldr r3, [r3, #12]
800180c: 4916 ldr r1, [pc, #88] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
800180e: 4313 orrs r3, r2
8001810: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8001812: 687b ldr r3, [r7, #4]
8001814: 681b ldr r3, [r3, #0]
8001816: f003 0308 and.w r3, r3, #8
800181a: 2b00 cmp r3, #0
800181c: d009 beq.n 8001832 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
800181e: 4b12 ldr r3, [pc, #72] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
8001820: 689b ldr r3, [r3, #8]
8001822: f423 4260 bic.w r2, r3, #57344 ; 0xe000
8001826: 687b ldr r3, [r7, #4]
8001828: 691b ldr r3, [r3, #16]
800182a: 00db lsls r3, r3, #3
800182c: 490e ldr r1, [pc, #56] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
800182e: 4313 orrs r3, r2
8001830: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8001832: f000 f821 bl 8001878 <HAL_RCC_GetSysClockFreq>
8001836: 4602 mov r2, r0
8001838: 4b0b ldr r3, [pc, #44] ; (8001868 <HAL_RCC_ClockConfig+0x1bc>)
800183a: 689b ldr r3, [r3, #8]
800183c: 091b lsrs r3, r3, #4
800183e: f003 030f and.w r3, r3, #15
8001842: 490a ldr r1, [pc, #40] ; (800186c <HAL_RCC_ClockConfig+0x1c0>)
8001844: 5ccb ldrb r3, [r1, r3]
8001846: fa22 f303 lsr.w r3, r2, r3
800184a: 4a09 ldr r2, [pc, #36] ; (8001870 <HAL_RCC_ClockConfig+0x1c4>)
800184c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
800184e: 4b09 ldr r3, [pc, #36] ; (8001874 <HAL_RCC_ClockConfig+0x1c8>)
8001850: 681b ldr r3, [r3, #0]
8001852: 4618 mov r0, r3
8001854: f7ff f90a bl 8000a6c <HAL_InitTick>
return HAL_OK;
8001858: 2300 movs r3, #0
}
800185a: 4618 mov r0, r3
800185c: 3710 adds r7, #16
800185e: 46bd mov sp, r7
8001860: bd80 pop {r7, pc}
8001862: bf00 nop
8001864: 40023c00 .word 0x40023c00
8001868: 40023800 .word 0x40023800
800186c: 080056c0 .word 0x080056c0
8001870: 20000000 .word 0x20000000
8001874: 20000004 .word 0x20000004
08001878 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001878: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
800187c: b094 sub sp, #80 ; 0x50
800187e: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
8001880: 2300 movs r3, #0
8001882: 647b str r3, [r7, #68] ; 0x44
8001884: 2300 movs r3, #0
8001886: 64fb str r3, [r7, #76] ; 0x4c
8001888: 2300 movs r3, #0
800188a: 643b str r3, [r7, #64] ; 0x40
uint32_t sysclockfreq = 0U;
800188c: 2300 movs r3, #0
800188e: 64bb str r3, [r7, #72] ; 0x48
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8001890: 4b79 ldr r3, [pc, #484] ; (8001a78 <HAL_RCC_GetSysClockFreq+0x200>)
8001892: 689b ldr r3, [r3, #8]
8001894: f003 030c and.w r3, r3, #12
8001898: 2b08 cmp r3, #8
800189a: d00d beq.n 80018b8 <HAL_RCC_GetSysClockFreq+0x40>
800189c: 2b08 cmp r3, #8
800189e: f200 80e1 bhi.w 8001a64 <HAL_RCC_GetSysClockFreq+0x1ec>
80018a2: 2b00 cmp r3, #0
80018a4: d002 beq.n 80018ac <HAL_RCC_GetSysClockFreq+0x34>
80018a6: 2b04 cmp r3, #4
80018a8: d003 beq.n 80018b2 <HAL_RCC_GetSysClockFreq+0x3a>
80018aa: e0db b.n 8001a64 <HAL_RCC_GetSysClockFreq+0x1ec>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
80018ac: 4b73 ldr r3, [pc, #460] ; (8001a7c <HAL_RCC_GetSysClockFreq+0x204>)
80018ae: 64bb str r3, [r7, #72] ; 0x48
break;
80018b0: e0db b.n 8001a6a <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
80018b2: 4b73 ldr r3, [pc, #460] ; (8001a80 <HAL_RCC_GetSysClockFreq+0x208>)
80018b4: 64bb str r3, [r7, #72] ; 0x48
break;
80018b6: e0d8 b.n 8001a6a <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
80018b8: 4b6f ldr r3, [pc, #444] ; (8001a78 <HAL_RCC_GetSysClockFreq+0x200>)
80018ba: 685b ldr r3, [r3, #4]
80018bc: f003 033f and.w r3, r3, #63 ; 0x3f
80018c0: 647b str r3, [r7, #68] ; 0x44
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
80018c2: 4b6d ldr r3, [pc, #436] ; (8001a78 <HAL_RCC_GetSysClockFreq+0x200>)
80018c4: 685b ldr r3, [r3, #4]
80018c6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80018ca: 2b00 cmp r3, #0
80018cc: d063 beq.n 8001996 <HAL_RCC_GetSysClockFreq+0x11e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
80018ce: 4b6a ldr r3, [pc, #424] ; (8001a78 <HAL_RCC_GetSysClockFreq+0x200>)
80018d0: 685b ldr r3, [r3, #4]
80018d2: 099b lsrs r3, r3, #6
80018d4: 2200 movs r2, #0
80018d6: 63bb str r3, [r7, #56] ; 0x38
80018d8: 63fa str r2, [r7, #60] ; 0x3c
80018da: 6bbb ldr r3, [r7, #56] ; 0x38
80018dc: f3c3 0308 ubfx r3, r3, #0, #9
80018e0: 633b str r3, [r7, #48] ; 0x30
80018e2: 2300 movs r3, #0
80018e4: 637b str r3, [r7, #52] ; 0x34
80018e6: e9d7 450c ldrd r4, r5, [r7, #48] ; 0x30
80018ea: 4622 mov r2, r4
80018ec: 462b mov r3, r5
80018ee: f04f 0000 mov.w r0, #0
80018f2: f04f 0100 mov.w r1, #0
80018f6: 0159 lsls r1, r3, #5
80018f8: ea41 61d2 orr.w r1, r1, r2, lsr #27
80018fc: 0150 lsls r0, r2, #5
80018fe: 4602 mov r2, r0
8001900: 460b mov r3, r1
8001902: 4621 mov r1, r4
8001904: 1a51 subs r1, r2, r1
8001906: 6139 str r1, [r7, #16]
8001908: 4629 mov r1, r5
800190a: eb63 0301 sbc.w r3, r3, r1
800190e: 617b str r3, [r7, #20]
8001910: f04f 0200 mov.w r2, #0
8001914: f04f 0300 mov.w r3, #0
8001918: e9d7 ab04 ldrd sl, fp, [r7, #16]
800191c: 4659 mov r1, fp
800191e: 018b lsls r3, r1, #6
8001920: 4651 mov r1, sl
8001922: ea43 6391 orr.w r3, r3, r1, lsr #26
8001926: 4651 mov r1, sl
8001928: 018a lsls r2, r1, #6
800192a: 4651 mov r1, sl
800192c: ebb2 0801 subs.w r8, r2, r1
8001930: 4659 mov r1, fp
8001932: eb63 0901 sbc.w r9, r3, r1
8001936: f04f 0200 mov.w r2, #0
800193a: f04f 0300 mov.w r3, #0
800193e: ea4f 03c9 mov.w r3, r9, lsl #3
8001942: ea43 7358 orr.w r3, r3, r8, lsr #29
8001946: ea4f 02c8 mov.w r2, r8, lsl #3
800194a: 4690 mov r8, r2
800194c: 4699 mov r9, r3
800194e: 4623 mov r3, r4
8001950: eb18 0303 adds.w r3, r8, r3
8001954: 60bb str r3, [r7, #8]
8001956: 462b mov r3, r5
8001958: eb49 0303 adc.w r3, r9, r3
800195c: 60fb str r3, [r7, #12]
800195e: f04f 0200 mov.w r2, #0
8001962: f04f 0300 mov.w r3, #0
8001966: e9d7 4502 ldrd r4, r5, [r7, #8]
800196a: 4629 mov r1, r5
800196c: 024b lsls r3, r1, #9
800196e: 4621 mov r1, r4
8001970: ea43 53d1 orr.w r3, r3, r1, lsr #23
8001974: 4621 mov r1, r4
8001976: 024a lsls r2, r1, #9
8001978: 4610 mov r0, r2
800197a: 4619 mov r1, r3
800197c: 6c7b ldr r3, [r7, #68] ; 0x44
800197e: 2200 movs r2, #0
8001980: 62bb str r3, [r7, #40] ; 0x28
8001982: 62fa str r2, [r7, #44] ; 0x2c
8001984: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
8001988: f7fe fc2a bl 80001e0 <__aeabi_uldivmod>
800198c: 4602 mov r2, r0
800198e: 460b mov r3, r1
8001990: 4613 mov r3, r2
8001992: 64fb str r3, [r7, #76] ; 0x4c
8001994: e058 b.n 8001a48 <HAL_RCC_GetSysClockFreq+0x1d0>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001996: 4b38 ldr r3, [pc, #224] ; (8001a78 <HAL_RCC_GetSysClockFreq+0x200>)
8001998: 685b ldr r3, [r3, #4]
800199a: 099b lsrs r3, r3, #6
800199c: 2200 movs r2, #0
800199e: 4618 mov r0, r3
80019a0: 4611 mov r1, r2
80019a2: f3c0 0308 ubfx r3, r0, #0, #9
80019a6: 623b str r3, [r7, #32]
80019a8: 2300 movs r3, #0
80019aa: 627b str r3, [r7, #36] ; 0x24
80019ac: e9d7 8908 ldrd r8, r9, [r7, #32]
80019b0: 4642 mov r2, r8
80019b2: 464b mov r3, r9
80019b4: f04f 0000 mov.w r0, #0
80019b8: f04f 0100 mov.w r1, #0
80019bc: 0159 lsls r1, r3, #5
80019be: ea41 61d2 orr.w r1, r1, r2, lsr #27
80019c2: 0150 lsls r0, r2, #5
80019c4: 4602 mov r2, r0
80019c6: 460b mov r3, r1
80019c8: 4641 mov r1, r8
80019ca: ebb2 0a01 subs.w sl, r2, r1
80019ce: 4649 mov r1, r9
80019d0: eb63 0b01 sbc.w fp, r3, r1
80019d4: f04f 0200 mov.w r2, #0
80019d8: f04f 0300 mov.w r3, #0
80019dc: ea4f 138b mov.w r3, fp, lsl #6
80019e0: ea43 639a orr.w r3, r3, sl, lsr #26
80019e4: ea4f 128a mov.w r2, sl, lsl #6
80019e8: ebb2 040a subs.w r4, r2, sl
80019ec: eb63 050b sbc.w r5, r3, fp
80019f0: f04f 0200 mov.w r2, #0
80019f4: f04f 0300 mov.w r3, #0
80019f8: 00eb lsls r3, r5, #3
80019fa: ea43 7354 orr.w r3, r3, r4, lsr #29
80019fe: 00e2 lsls r2, r4, #3
8001a00: 4614 mov r4, r2
8001a02: 461d mov r5, r3
8001a04: 4643 mov r3, r8
8001a06: 18e3 adds r3, r4, r3
8001a08: 603b str r3, [r7, #0]
8001a0a: 464b mov r3, r9
8001a0c: eb45 0303 adc.w r3, r5, r3
8001a10: 607b str r3, [r7, #4]
8001a12: f04f 0200 mov.w r2, #0
8001a16: f04f 0300 mov.w r3, #0
8001a1a: e9d7 4500 ldrd r4, r5, [r7]
8001a1e: 4629 mov r1, r5
8001a20: 028b lsls r3, r1, #10
8001a22: 4621 mov r1, r4
8001a24: ea43 5391 orr.w r3, r3, r1, lsr #22
8001a28: 4621 mov r1, r4
8001a2a: 028a lsls r2, r1, #10
8001a2c: 4610 mov r0, r2
8001a2e: 4619 mov r1, r3
8001a30: 6c7b ldr r3, [r7, #68] ; 0x44
8001a32: 2200 movs r2, #0
8001a34: 61bb str r3, [r7, #24]
8001a36: 61fa str r2, [r7, #28]
8001a38: e9d7 2306 ldrd r2, r3, [r7, #24]
8001a3c: f7fe fbd0 bl 80001e0 <__aeabi_uldivmod>
8001a40: 4602 mov r2, r0
8001a42: 460b mov r3, r1
8001a44: 4613 mov r3, r2
8001a46: 64fb str r3, [r7, #76] ; 0x4c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
8001a48: 4b0b ldr r3, [pc, #44] ; (8001a78 <HAL_RCC_GetSysClockFreq+0x200>)
8001a4a: 685b ldr r3, [r3, #4]
8001a4c: 0c1b lsrs r3, r3, #16
8001a4e: f003 0303 and.w r3, r3, #3
8001a52: 3301 adds r3, #1
8001a54: 005b lsls r3, r3, #1
8001a56: 643b str r3, [r7, #64] ; 0x40
sysclockfreq = pllvco/pllp;
8001a58: 6cfa ldr r2, [r7, #76] ; 0x4c
8001a5a: 6c3b ldr r3, [r7, #64] ; 0x40
8001a5c: fbb2 f3f3 udiv r3, r2, r3
8001a60: 64bb str r3, [r7, #72] ; 0x48
break;
8001a62: e002 b.n 8001a6a <HAL_RCC_GetSysClockFreq+0x1f2>
}
default:
{
sysclockfreq = HSI_VALUE;
8001a64: 4b05 ldr r3, [pc, #20] ; (8001a7c <HAL_RCC_GetSysClockFreq+0x204>)
8001a66: 64bb str r3, [r7, #72] ; 0x48
break;
8001a68: bf00 nop
}
}
return sysclockfreq;
8001a6a: 6cbb ldr r3, [r7, #72] ; 0x48
}
8001a6c: 4618 mov r0, r3
8001a6e: 3750 adds r7, #80 ; 0x50
8001a70: 46bd mov sp, r7
8001a72: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8001a76: bf00 nop
8001a78: 40023800 .word 0x40023800
8001a7c: 00f42400 .word 0x00f42400
8001a80: 007a1200 .word 0x007a1200
08001a84 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8001a84: b480 push {r7}
8001a86: af00 add r7, sp, #0
return SystemCoreClock;
8001a88: 4b03 ldr r3, [pc, #12] ; (8001a98 <HAL_RCC_GetHCLKFreq+0x14>)
8001a8a: 681b ldr r3, [r3, #0]
}
8001a8c: 4618 mov r0, r3
8001a8e: 46bd mov sp, r7
8001a90: f85d 7b04 ldr.w r7, [sp], #4
8001a94: 4770 bx lr
8001a96: bf00 nop
8001a98: 20000000 .word 0x20000000
08001a9c <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8001a9c: b580 push {r7, lr}
8001a9e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
8001aa0: f7ff fff0 bl 8001a84 <HAL_RCC_GetHCLKFreq>
8001aa4: 4602 mov r2, r0
8001aa6: 4b05 ldr r3, [pc, #20] ; (8001abc <HAL_RCC_GetPCLK1Freq+0x20>)
8001aa8: 689b ldr r3, [r3, #8]
8001aaa: 0a9b lsrs r3, r3, #10
8001aac: f003 0307 and.w r3, r3, #7
8001ab0: 4903 ldr r1, [pc, #12] ; (8001ac0 <HAL_RCC_GetPCLK1Freq+0x24>)
8001ab2: 5ccb ldrb r3, [r1, r3]
8001ab4: fa22 f303 lsr.w r3, r2, r3
}
8001ab8: 4618 mov r0, r3
8001aba: bd80 pop {r7, pc}
8001abc: 40023800 .word 0x40023800
8001ac0: 080056d0 .word 0x080056d0
08001ac4 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8001ac4: b580 push {r7, lr}
8001ac6: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
8001ac8: f7ff ffdc bl 8001a84 <HAL_RCC_GetHCLKFreq>
8001acc: 4602 mov r2, r0
8001ace: 4b05 ldr r3, [pc, #20] ; (8001ae4 <HAL_RCC_GetPCLK2Freq+0x20>)
8001ad0: 689b ldr r3, [r3, #8]
8001ad2: 0b5b lsrs r3, r3, #13
8001ad4: f003 0307 and.w r3, r3, #7
8001ad8: 4903 ldr r1, [pc, #12] ; (8001ae8 <HAL_RCC_GetPCLK2Freq+0x24>)
8001ada: 5ccb ldrb r3, [r1, r3]
8001adc: fa22 f303 lsr.w r3, r2, r3
}
8001ae0: 4618 mov r0, r3
8001ae2: bd80 pop {r7, pc}
8001ae4: 40023800 .word 0x40023800
8001ae8: 080056d0 .word 0x080056d0
08001aec <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
8001aec: b480 push {r7}
8001aee: b083 sub sp, #12
8001af0: af00 add r7, sp, #0
8001af2: 6078 str r0, [r7, #4]
8001af4: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
8001af6: 687b ldr r3, [r7, #4]
8001af8: 220f movs r2, #15
8001afa: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
8001afc: 4b12 ldr r3, [pc, #72] ; (8001b48 <HAL_RCC_GetClockConfig+0x5c>)
8001afe: 689b ldr r3, [r3, #8]
8001b00: f003 0203 and.w r2, r3, #3
8001b04: 687b ldr r3, [r7, #4]
8001b06: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
8001b08: 4b0f ldr r3, [pc, #60] ; (8001b48 <HAL_RCC_GetClockConfig+0x5c>)
8001b0a: 689b ldr r3, [r3, #8]
8001b0c: f003 02f0 and.w r2, r3, #240 ; 0xf0
8001b10: 687b ldr r3, [r7, #4]
8001b12: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
8001b14: 4b0c ldr r3, [pc, #48] ; (8001b48 <HAL_RCC_GetClockConfig+0x5c>)
8001b16: 689b ldr r3, [r3, #8]
8001b18: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8001b1c: 687b ldr r3, [r7, #4]
8001b1e: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
8001b20: 4b09 ldr r3, [pc, #36] ; (8001b48 <HAL_RCC_GetClockConfig+0x5c>)
8001b22: 689b ldr r3, [r3, #8]
8001b24: 08db lsrs r3, r3, #3
8001b26: f403 52e0 and.w r2, r3, #7168 ; 0x1c00
8001b2a: 687b ldr r3, [r7, #4]
8001b2c: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
8001b2e: 4b07 ldr r3, [pc, #28] ; (8001b4c <HAL_RCC_GetClockConfig+0x60>)
8001b30: 681b ldr r3, [r3, #0]
8001b32: f003 0207 and.w r2, r3, #7
8001b36: 683b ldr r3, [r7, #0]
8001b38: 601a str r2, [r3, #0]
}
8001b3a: bf00 nop
8001b3c: 370c adds r7, #12
8001b3e: 46bd mov sp, r7
8001b40: f85d 7b04 ldr.w r7, [sp], #4
8001b44: 4770 bx lr
8001b46: bf00 nop
8001b48: 40023800 .word 0x40023800
8001b4c: 40023c00 .word 0x40023c00
08001b50 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8001b50: b580 push {r7, lr}
8001b52: b082 sub sp, #8
8001b54: af00 add r7, sp, #0
8001b56: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8001b58: 687b ldr r3, [r7, #4]
8001b5a: 2b00 cmp r3, #0
8001b5c: d101 bne.n 8001b62 <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8001b5e: 2301 movs r3, #1
8001b60: e041 b.n 8001be6 <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
8001b62: 687b ldr r3, [r7, #4]
8001b64: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001b68: b2db uxtb r3, r3
8001b6a: 2b00 cmp r3, #0
8001b6c: d106 bne.n 8001b7c <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8001b6e: 687b ldr r3, [r7, #4]
8001b70: 2200 movs r2, #0
8001b72: f883 203c strb.w r2, [r3, #60] ; 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
8001b76: 6878 ldr r0, [r7, #4]
8001b78: f000 f839 bl 8001bee <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001b7c: 687b ldr r3, [r7, #4]
8001b7e: 2202 movs r2, #2
8001b80: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8001b84: 687b ldr r3, [r7, #4]
8001b86: 681a ldr r2, [r3, #0]
8001b88: 687b ldr r3, [r7, #4]
8001b8a: 3304 adds r3, #4
8001b8c: 4619 mov r1, r3
8001b8e: 4610 mov r0, r2
8001b90: f000 f9ca bl 8001f28 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8001b94: 687b ldr r3, [r7, #4]
8001b96: 2201 movs r2, #1
8001b98: f883 2046 strb.w r2, [r3, #70] ; 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001b9c: 687b ldr r3, [r7, #4]
8001b9e: 2201 movs r2, #1
8001ba0: f883 203e strb.w r2, [r3, #62] ; 0x3e
8001ba4: 687b ldr r3, [r7, #4]
8001ba6: 2201 movs r2, #1
8001ba8: f883 203f strb.w r2, [r3, #63] ; 0x3f
8001bac: 687b ldr r3, [r7, #4]
8001bae: 2201 movs r2, #1
8001bb0: f883 2040 strb.w r2, [r3, #64] ; 0x40
8001bb4: 687b ldr r3, [r7, #4]
8001bb6: 2201 movs r2, #1
8001bb8: f883 2041 strb.w r2, [r3, #65] ; 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8001bbc: 687b ldr r3, [r7, #4]
8001bbe: 2201 movs r2, #1
8001bc0: f883 2042 strb.w r2, [r3, #66] ; 0x42
8001bc4: 687b ldr r3, [r7, #4]
8001bc6: 2201 movs r2, #1
8001bc8: f883 2043 strb.w r2, [r3, #67] ; 0x43
8001bcc: 687b ldr r3, [r7, #4]
8001bce: 2201 movs r2, #1
8001bd0: f883 2044 strb.w r2, [r3, #68] ; 0x44
8001bd4: 687b ldr r3, [r7, #4]
8001bd6: 2201 movs r2, #1
8001bd8: f883 2045 strb.w r2, [r3, #69] ; 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8001bdc: 687b ldr r3, [r7, #4]
8001bde: 2201 movs r2, #1
8001be0: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001be4: 2300 movs r3, #0
}
8001be6: 4618 mov r0, r3
8001be8: 3708 adds r7, #8
8001bea: 46bd mov sp, r7
8001bec: bd80 pop {r7, pc}
08001bee <HAL_TIM_Base_MspInit>:
* @brief Initializes the TIM Base MSP.
* @param htim TIM Base handle
* @retval None
*/
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
8001bee: b480 push {r7}
8001bf0: b083 sub sp, #12
8001bf2: af00 add r7, sp, #0
8001bf4: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_Base_MspInit could be implemented in the user file
*/
}
8001bf6: bf00 nop
8001bf8: 370c adds r7, #12
8001bfa: 46bd mov sp, r7
8001bfc: f85d 7b04 ldr.w r7, [sp], #4
8001c00: 4770 bx lr
...
08001c04 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
8001c04: b480 push {r7}
8001c06: b085 sub sp, #20
8001c08: af00 add r7, sp, #0
8001c0a: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
8001c0c: 687b ldr r3, [r7, #4]
8001c0e: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001c12: b2db uxtb r3, r3
8001c14: 2b01 cmp r3, #1
8001c16: d001 beq.n 8001c1c <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
8001c18: 2301 movs r3, #1
8001c1a: e044 b.n 8001ca6 <HAL_TIM_Base_Start_IT+0xa2>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8001c1c: 687b ldr r3, [r7, #4]
8001c1e: 2202 movs r2, #2
8001c20: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8001c24: 687b ldr r3, [r7, #4]
8001c26: 681b ldr r3, [r3, #0]
8001c28: 68da ldr r2, [r3, #12]
8001c2a: 687b ldr r3, [r7, #4]
8001c2c: 681b ldr r3, [r3, #0]
8001c2e: f042 0201 orr.w r2, r2, #1
8001c32: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8001c34: 687b ldr r3, [r7, #4]
8001c36: 681b ldr r3, [r3, #0]
8001c38: 4a1e ldr r2, [pc, #120] ; (8001cb4 <HAL_TIM_Base_Start_IT+0xb0>)
8001c3a: 4293 cmp r3, r2
8001c3c: d018 beq.n 8001c70 <HAL_TIM_Base_Start_IT+0x6c>
8001c3e: 687b ldr r3, [r7, #4]
8001c40: 681b ldr r3, [r3, #0]
8001c42: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001c46: d013 beq.n 8001c70 <HAL_TIM_Base_Start_IT+0x6c>
8001c48: 687b ldr r3, [r7, #4]
8001c4a: 681b ldr r3, [r3, #0]
8001c4c: 4a1a ldr r2, [pc, #104] ; (8001cb8 <HAL_TIM_Base_Start_IT+0xb4>)
8001c4e: 4293 cmp r3, r2
8001c50: d00e beq.n 8001c70 <HAL_TIM_Base_Start_IT+0x6c>
8001c52: 687b ldr r3, [r7, #4]
8001c54: 681b ldr r3, [r3, #0]
8001c56: 4a19 ldr r2, [pc, #100] ; (8001cbc <HAL_TIM_Base_Start_IT+0xb8>)
8001c58: 4293 cmp r3, r2
8001c5a: d009 beq.n 8001c70 <HAL_TIM_Base_Start_IT+0x6c>
8001c5c: 687b ldr r3, [r7, #4]
8001c5e: 681b ldr r3, [r3, #0]
8001c60: 4a17 ldr r2, [pc, #92] ; (8001cc0 <HAL_TIM_Base_Start_IT+0xbc>)
8001c62: 4293 cmp r3, r2
8001c64: d004 beq.n 8001c70 <HAL_TIM_Base_Start_IT+0x6c>
8001c66: 687b ldr r3, [r7, #4]
8001c68: 681b ldr r3, [r3, #0]
8001c6a: 4a16 ldr r2, [pc, #88] ; (8001cc4 <HAL_TIM_Base_Start_IT+0xc0>)
8001c6c: 4293 cmp r3, r2
8001c6e: d111 bne.n 8001c94 <HAL_TIM_Base_Start_IT+0x90>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8001c70: 687b ldr r3, [r7, #4]
8001c72: 681b ldr r3, [r3, #0]
8001c74: 689b ldr r3, [r3, #8]
8001c76: f003 0307 and.w r3, r3, #7
8001c7a: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8001c7c: 68fb ldr r3, [r7, #12]
8001c7e: 2b06 cmp r3, #6
8001c80: d010 beq.n 8001ca4 <HAL_TIM_Base_Start_IT+0xa0>
{
__HAL_TIM_ENABLE(htim);
8001c82: 687b ldr r3, [r7, #4]
8001c84: 681b ldr r3, [r3, #0]
8001c86: 681a ldr r2, [r3, #0]
8001c88: 687b ldr r3, [r7, #4]
8001c8a: 681b ldr r3, [r3, #0]
8001c8c: f042 0201 orr.w r2, r2, #1
8001c90: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8001c92: e007 b.n 8001ca4 <HAL_TIM_Base_Start_IT+0xa0>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8001c94: 687b ldr r3, [r7, #4]
8001c96: 681b ldr r3, [r3, #0]
8001c98: 681a ldr r2, [r3, #0]
8001c9a: 687b ldr r3, [r7, #4]
8001c9c: 681b ldr r3, [r3, #0]
8001c9e: f042 0201 orr.w r2, r2, #1
8001ca2: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
8001ca4: 2300 movs r3, #0
}
8001ca6: 4618 mov r0, r3
8001ca8: 3714 adds r7, #20
8001caa: 46bd mov sp, r7
8001cac: f85d 7b04 ldr.w r7, [sp], #4
8001cb0: 4770 bx lr
8001cb2: bf00 nop
8001cb4: 40010000 .word 0x40010000
8001cb8: 40000400 .word 0x40000400
8001cbc: 40000800 .word 0x40000800
8001cc0: 40000c00 .word 0x40000c00
8001cc4: 40014000 .word 0x40014000
08001cc8 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8001cc8: b580 push {r7, lr}
8001cca: b082 sub sp, #8
8001ccc: af00 add r7, sp, #0
8001cce: 6078 str r0, [r7, #4]
/* Capture compare 1 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
8001cd0: 687b ldr r3, [r7, #4]
8001cd2: 681b ldr r3, [r3, #0]
8001cd4: 691b ldr r3, [r3, #16]
8001cd6: f003 0302 and.w r3, r3, #2
8001cda: 2b02 cmp r3, #2
8001cdc: d122 bne.n 8001d24 <HAL_TIM_IRQHandler+0x5c>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
8001cde: 687b ldr r3, [r7, #4]
8001ce0: 681b ldr r3, [r3, #0]
8001ce2: 68db ldr r3, [r3, #12]
8001ce4: f003 0302 and.w r3, r3, #2
8001ce8: 2b02 cmp r3, #2
8001cea: d11b bne.n 8001d24 <HAL_TIM_IRQHandler+0x5c>
{
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
8001cec: 687b ldr r3, [r7, #4]
8001cee: 681b ldr r3, [r3, #0]
8001cf0: f06f 0202 mvn.w r2, #2
8001cf4: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8001cf6: 687b ldr r3, [r7, #4]
8001cf8: 2201 movs r2, #1
8001cfa: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8001cfc: 687b ldr r3, [r7, #4]
8001cfe: 681b ldr r3, [r3, #0]
8001d00: 699b ldr r3, [r3, #24]
8001d02: f003 0303 and.w r3, r3, #3
8001d06: 2b00 cmp r3, #0
8001d08: d003 beq.n 8001d12 <HAL_TIM_IRQHandler+0x4a>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001d0a: 6878 ldr r0, [r7, #4]
8001d0c: f000 f8ee bl 8001eec <HAL_TIM_IC_CaptureCallback>
8001d10: e005 b.n 8001d1e <HAL_TIM_IRQHandler+0x56>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001d12: 6878 ldr r0, [r7, #4]
8001d14: f000 f8e0 bl 8001ed8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001d18: 6878 ldr r0, [r7, #4]
8001d1a: f000 f8f1 bl 8001f00 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001d1e: 687b ldr r3, [r7, #4]
8001d20: 2200 movs r2, #0
8001d22: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
8001d24: 687b ldr r3, [r7, #4]
8001d26: 681b ldr r3, [r3, #0]
8001d28: 691b ldr r3, [r3, #16]
8001d2a: f003 0304 and.w r3, r3, #4
8001d2e: 2b04 cmp r3, #4
8001d30: d122 bne.n 8001d78 <HAL_TIM_IRQHandler+0xb0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
8001d32: 687b ldr r3, [r7, #4]
8001d34: 681b ldr r3, [r3, #0]
8001d36: 68db ldr r3, [r3, #12]
8001d38: f003 0304 and.w r3, r3, #4
8001d3c: 2b04 cmp r3, #4
8001d3e: d11b bne.n 8001d78 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
8001d40: 687b ldr r3, [r7, #4]
8001d42: 681b ldr r3, [r3, #0]
8001d44: f06f 0204 mvn.w r2, #4
8001d48: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8001d4a: 687b ldr r3, [r7, #4]
8001d4c: 2202 movs r2, #2
8001d4e: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8001d50: 687b ldr r3, [r7, #4]
8001d52: 681b ldr r3, [r3, #0]
8001d54: 699b ldr r3, [r3, #24]
8001d56: f403 7340 and.w r3, r3, #768 ; 0x300
8001d5a: 2b00 cmp r3, #0
8001d5c: d003 beq.n 8001d66 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001d5e: 6878 ldr r0, [r7, #4]
8001d60: f000 f8c4 bl 8001eec <HAL_TIM_IC_CaptureCallback>
8001d64: e005 b.n 8001d72 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001d66: 6878 ldr r0, [r7, #4]
8001d68: f000 f8b6 bl 8001ed8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001d6c: 6878 ldr r0, [r7, #4]
8001d6e: f000 f8c7 bl 8001f00 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001d72: 687b ldr r3, [r7, #4]
8001d74: 2200 movs r2, #0
8001d76: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
8001d78: 687b ldr r3, [r7, #4]
8001d7a: 681b ldr r3, [r3, #0]
8001d7c: 691b ldr r3, [r3, #16]
8001d7e: f003 0308 and.w r3, r3, #8
8001d82: 2b08 cmp r3, #8
8001d84: d122 bne.n 8001dcc <HAL_TIM_IRQHandler+0x104>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
8001d86: 687b ldr r3, [r7, #4]
8001d88: 681b ldr r3, [r3, #0]
8001d8a: 68db ldr r3, [r3, #12]
8001d8c: f003 0308 and.w r3, r3, #8
8001d90: 2b08 cmp r3, #8
8001d92: d11b bne.n 8001dcc <HAL_TIM_IRQHandler+0x104>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
8001d94: 687b ldr r3, [r7, #4]
8001d96: 681b ldr r3, [r3, #0]
8001d98: f06f 0208 mvn.w r2, #8
8001d9c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8001d9e: 687b ldr r3, [r7, #4]
8001da0: 2204 movs r2, #4
8001da2: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8001da4: 687b ldr r3, [r7, #4]
8001da6: 681b ldr r3, [r3, #0]
8001da8: 69db ldr r3, [r3, #28]
8001daa: f003 0303 and.w r3, r3, #3
8001dae: 2b00 cmp r3, #0
8001db0: d003 beq.n 8001dba <HAL_TIM_IRQHandler+0xf2>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001db2: 6878 ldr r0, [r7, #4]
8001db4: f000 f89a bl 8001eec <HAL_TIM_IC_CaptureCallback>
8001db8: e005 b.n 8001dc6 <HAL_TIM_IRQHandler+0xfe>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001dba: 6878 ldr r0, [r7, #4]
8001dbc: f000 f88c bl 8001ed8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001dc0: 6878 ldr r0, [r7, #4]
8001dc2: f000 f89d bl 8001f00 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001dc6: 687b ldr r3, [r7, #4]
8001dc8: 2200 movs r2, #0
8001dca: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
8001dcc: 687b ldr r3, [r7, #4]
8001dce: 681b ldr r3, [r3, #0]
8001dd0: 691b ldr r3, [r3, #16]
8001dd2: f003 0310 and.w r3, r3, #16
8001dd6: 2b10 cmp r3, #16
8001dd8: d122 bne.n 8001e20 <HAL_TIM_IRQHandler+0x158>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
8001dda: 687b ldr r3, [r7, #4]
8001ddc: 681b ldr r3, [r3, #0]
8001dde: 68db ldr r3, [r3, #12]
8001de0: f003 0310 and.w r3, r3, #16
8001de4: 2b10 cmp r3, #16
8001de6: d11b bne.n 8001e20 <HAL_TIM_IRQHandler+0x158>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
8001de8: 687b ldr r3, [r7, #4]
8001dea: 681b ldr r3, [r3, #0]
8001dec: f06f 0210 mvn.w r2, #16
8001df0: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8001df2: 687b ldr r3, [r7, #4]
8001df4: 2208 movs r2, #8
8001df6: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8001df8: 687b ldr r3, [r7, #4]
8001dfa: 681b ldr r3, [r3, #0]
8001dfc: 69db ldr r3, [r3, #28]
8001dfe: f403 7340 and.w r3, r3, #768 ; 0x300
8001e02: 2b00 cmp r3, #0
8001e04: d003 beq.n 8001e0e <HAL_TIM_IRQHandler+0x146>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8001e06: 6878 ldr r0, [r7, #4]
8001e08: f000 f870 bl 8001eec <HAL_TIM_IC_CaptureCallback>
8001e0c: e005 b.n 8001e1a <HAL_TIM_IRQHandler+0x152>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8001e0e: 6878 ldr r0, [r7, #4]
8001e10: f000 f862 bl 8001ed8 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8001e14: 6878 ldr r0, [r7, #4]
8001e16: f000 f873 bl 8001f00 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8001e1a: 687b ldr r3, [r7, #4]
8001e1c: 2200 movs r2, #0
8001e1e: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
8001e20: 687b ldr r3, [r7, #4]
8001e22: 681b ldr r3, [r3, #0]
8001e24: 691b ldr r3, [r3, #16]
8001e26: f003 0301 and.w r3, r3, #1
8001e2a: 2b01 cmp r3, #1
8001e2c: d10e bne.n 8001e4c <HAL_TIM_IRQHandler+0x184>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
8001e2e: 687b ldr r3, [r7, #4]
8001e30: 681b ldr r3, [r3, #0]
8001e32: 68db ldr r3, [r3, #12]
8001e34: f003 0301 and.w r3, r3, #1
8001e38: 2b01 cmp r3, #1
8001e3a: d107 bne.n 8001e4c <HAL_TIM_IRQHandler+0x184>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
8001e3c: 687b ldr r3, [r7, #4]
8001e3e: 681b ldr r3, [r3, #0]
8001e40: f06f 0201 mvn.w r2, #1
8001e44: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
8001e46: 6878 ldr r0, [r7, #4]
8001e48: f7fe fd84 bl 8000954 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
8001e4c: 687b ldr r3, [r7, #4]
8001e4e: 681b ldr r3, [r3, #0]
8001e50: 691b ldr r3, [r3, #16]
8001e52: f003 0380 and.w r3, r3, #128 ; 0x80
8001e56: 2b80 cmp r3, #128 ; 0x80
8001e58: d10e bne.n 8001e78 <HAL_TIM_IRQHandler+0x1b0>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
8001e5a: 687b ldr r3, [r7, #4]
8001e5c: 681b ldr r3, [r3, #0]
8001e5e: 68db ldr r3, [r3, #12]
8001e60: f003 0380 and.w r3, r3, #128 ; 0x80
8001e64: 2b80 cmp r3, #128 ; 0x80
8001e66: d107 bne.n 8001e78 <HAL_TIM_IRQHandler+0x1b0>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
8001e68: 687b ldr r3, [r7, #4]
8001e6a: 681b ldr r3, [r3, #0]
8001e6c: f06f 0280 mvn.w r2, #128 ; 0x80
8001e70: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
8001e72: 6878 ldr r0, [r7, #4]
8001e74: f000 f8e2 bl 800203c <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
8001e78: 687b ldr r3, [r7, #4]
8001e7a: 681b ldr r3, [r3, #0]
8001e7c: 691b ldr r3, [r3, #16]
8001e7e: f003 0340 and.w r3, r3, #64 ; 0x40
8001e82: 2b40 cmp r3, #64 ; 0x40
8001e84: d10e bne.n 8001ea4 <HAL_TIM_IRQHandler+0x1dc>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
8001e86: 687b ldr r3, [r7, #4]
8001e88: 681b ldr r3, [r3, #0]
8001e8a: 68db ldr r3, [r3, #12]
8001e8c: f003 0340 and.w r3, r3, #64 ; 0x40
8001e90: 2b40 cmp r3, #64 ; 0x40
8001e92: d107 bne.n 8001ea4 <HAL_TIM_IRQHandler+0x1dc>
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
8001e94: 687b ldr r3, [r7, #4]
8001e96: 681b ldr r3, [r3, #0]
8001e98: f06f 0240 mvn.w r2, #64 ; 0x40
8001e9c: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8001e9e: 6878 ldr r0, [r7, #4]
8001ea0: f000 f838 bl 8001f14 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
8001ea4: 687b ldr r3, [r7, #4]
8001ea6: 681b ldr r3, [r3, #0]
8001ea8: 691b ldr r3, [r3, #16]
8001eaa: f003 0320 and.w r3, r3, #32
8001eae: 2b20 cmp r3, #32
8001eb0: d10e bne.n 8001ed0 <HAL_TIM_IRQHandler+0x208>
{
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
8001eb2: 687b ldr r3, [r7, #4]
8001eb4: 681b ldr r3, [r3, #0]
8001eb6: 68db ldr r3, [r3, #12]
8001eb8: f003 0320 and.w r3, r3, #32
8001ebc: 2b20 cmp r3, #32
8001ebe: d107 bne.n 8001ed0 <HAL_TIM_IRQHandler+0x208>
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
8001ec0: 687b ldr r3, [r7, #4]
8001ec2: 681b ldr r3, [r3, #0]
8001ec4: f06f 0220 mvn.w r2, #32
8001ec8: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8001eca: 6878 ldr r0, [r7, #4]
8001ecc: f000 f8ac bl 8002028 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8001ed0: bf00 nop
8001ed2: 3708 adds r7, #8
8001ed4: 46bd mov sp, r7
8001ed6: bd80 pop {r7, pc}
08001ed8 <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8001ed8: b480 push {r7}
8001eda: b083 sub sp, #12
8001edc: af00 add r7, sp, #0
8001ede: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8001ee0: bf00 nop
8001ee2: 370c adds r7, #12
8001ee4: 46bd mov sp, r7
8001ee6: f85d 7b04 ldr.w r7, [sp], #4
8001eea: 4770 bx lr
08001eec <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8001eec: b480 push {r7}
8001eee: b083 sub sp, #12
8001ef0: af00 add r7, sp, #0
8001ef2: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8001ef4: bf00 nop
8001ef6: 370c adds r7, #12
8001ef8: 46bd mov sp, r7
8001efa: f85d 7b04 ldr.w r7, [sp], #4
8001efe: 4770 bx lr
08001f00 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8001f00: b480 push {r7}
8001f02: b083 sub sp, #12
8001f04: af00 add r7, sp, #0
8001f06: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8001f08: bf00 nop
8001f0a: 370c adds r7, #12
8001f0c: 46bd mov sp, r7
8001f0e: f85d 7b04 ldr.w r7, [sp], #4
8001f12: 4770 bx lr
08001f14 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8001f14: b480 push {r7}
8001f16: b083 sub sp, #12
8001f18: af00 add r7, sp, #0
8001f1a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8001f1c: bf00 nop
8001f1e: 370c adds r7, #12
8001f20: 46bd mov sp, r7
8001f22: f85d 7b04 ldr.w r7, [sp], #4
8001f26: 4770 bx lr
08001f28 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
8001f28: b480 push {r7}
8001f2a: b085 sub sp, #20
8001f2c: af00 add r7, sp, #0
8001f2e: 6078 str r0, [r7, #4]
8001f30: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8001f32: 687b ldr r3, [r7, #4]
8001f34: 681b ldr r3, [r3, #0]
8001f36: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8001f38: 687b ldr r3, [r7, #4]
8001f3a: 4a34 ldr r2, [pc, #208] ; (800200c <TIM_Base_SetConfig+0xe4>)
8001f3c: 4293 cmp r3, r2
8001f3e: d00f beq.n 8001f60 <TIM_Base_SetConfig+0x38>
8001f40: 687b ldr r3, [r7, #4]
8001f42: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001f46: d00b beq.n 8001f60 <TIM_Base_SetConfig+0x38>
8001f48: 687b ldr r3, [r7, #4]
8001f4a: 4a31 ldr r2, [pc, #196] ; (8002010 <TIM_Base_SetConfig+0xe8>)
8001f4c: 4293 cmp r3, r2
8001f4e: d007 beq.n 8001f60 <TIM_Base_SetConfig+0x38>
8001f50: 687b ldr r3, [r7, #4]
8001f52: 4a30 ldr r2, [pc, #192] ; (8002014 <TIM_Base_SetConfig+0xec>)
8001f54: 4293 cmp r3, r2
8001f56: d003 beq.n 8001f60 <TIM_Base_SetConfig+0x38>
8001f58: 687b ldr r3, [r7, #4]
8001f5a: 4a2f ldr r2, [pc, #188] ; (8002018 <TIM_Base_SetConfig+0xf0>)
8001f5c: 4293 cmp r3, r2
8001f5e: d108 bne.n 8001f72 <TIM_Base_SetConfig+0x4a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8001f60: 68fb ldr r3, [r7, #12]
8001f62: f023 0370 bic.w r3, r3, #112 ; 0x70
8001f66: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8001f68: 683b ldr r3, [r7, #0]
8001f6a: 685b ldr r3, [r3, #4]
8001f6c: 68fa ldr r2, [r7, #12]
8001f6e: 4313 orrs r3, r2
8001f70: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8001f72: 687b ldr r3, [r7, #4]
8001f74: 4a25 ldr r2, [pc, #148] ; (800200c <TIM_Base_SetConfig+0xe4>)
8001f76: 4293 cmp r3, r2
8001f78: d01b beq.n 8001fb2 <TIM_Base_SetConfig+0x8a>
8001f7a: 687b ldr r3, [r7, #4]
8001f7c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000
8001f80: d017 beq.n 8001fb2 <TIM_Base_SetConfig+0x8a>
8001f82: 687b ldr r3, [r7, #4]
8001f84: 4a22 ldr r2, [pc, #136] ; (8002010 <TIM_Base_SetConfig+0xe8>)
8001f86: 4293 cmp r3, r2
8001f88: d013 beq.n 8001fb2 <TIM_Base_SetConfig+0x8a>
8001f8a: 687b ldr r3, [r7, #4]
8001f8c: 4a21 ldr r2, [pc, #132] ; (8002014 <TIM_Base_SetConfig+0xec>)
8001f8e: 4293 cmp r3, r2
8001f90: d00f beq.n 8001fb2 <TIM_Base_SetConfig+0x8a>
8001f92: 687b ldr r3, [r7, #4]
8001f94: 4a20 ldr r2, [pc, #128] ; (8002018 <TIM_Base_SetConfig+0xf0>)
8001f96: 4293 cmp r3, r2
8001f98: d00b beq.n 8001fb2 <TIM_Base_SetConfig+0x8a>
8001f9a: 687b ldr r3, [r7, #4]
8001f9c: 4a1f ldr r2, [pc, #124] ; (800201c <TIM_Base_SetConfig+0xf4>)
8001f9e: 4293 cmp r3, r2
8001fa0: d007 beq.n 8001fb2 <TIM_Base_SetConfig+0x8a>
8001fa2: 687b ldr r3, [r7, #4]
8001fa4: 4a1e ldr r2, [pc, #120] ; (8002020 <TIM_Base_SetConfig+0xf8>)
8001fa6: 4293 cmp r3, r2
8001fa8: d003 beq.n 8001fb2 <TIM_Base_SetConfig+0x8a>
8001faa: 687b ldr r3, [r7, #4]
8001fac: 4a1d ldr r2, [pc, #116] ; (8002024 <TIM_Base_SetConfig+0xfc>)
8001fae: 4293 cmp r3, r2
8001fb0: d108 bne.n 8001fc4 <TIM_Base_SetConfig+0x9c>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8001fb2: 68fb ldr r3, [r7, #12]
8001fb4: f423 7340 bic.w r3, r3, #768 ; 0x300
8001fb8: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8001fba: 683b ldr r3, [r7, #0]
8001fbc: 68db ldr r3, [r3, #12]
8001fbe: 68fa ldr r2, [r7, #12]
8001fc0: 4313 orrs r3, r2
8001fc2: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8001fc4: 68fb ldr r3, [r7, #12]
8001fc6: f023 0280 bic.w r2, r3, #128 ; 0x80
8001fca: 683b ldr r3, [r7, #0]
8001fcc: 695b ldr r3, [r3, #20]
8001fce: 4313 orrs r3, r2
8001fd0: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8001fd2: 687b ldr r3, [r7, #4]
8001fd4: 68fa ldr r2, [r7, #12]
8001fd6: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8001fd8: 683b ldr r3, [r7, #0]
8001fda: 689a ldr r2, [r3, #8]
8001fdc: 687b ldr r3, [r7, #4]
8001fde: 62da str r2, [r3, #44] ; 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8001fe0: 683b ldr r3, [r7, #0]
8001fe2: 681a ldr r2, [r3, #0]
8001fe4: 687b ldr r3, [r7, #4]
8001fe6: 629a str r2, [r3, #40] ; 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8001fe8: 687b ldr r3, [r7, #4]
8001fea: 4a08 ldr r2, [pc, #32] ; (800200c <TIM_Base_SetConfig+0xe4>)
8001fec: 4293 cmp r3, r2
8001fee: d103 bne.n 8001ff8 <TIM_Base_SetConfig+0xd0>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8001ff0: 683b ldr r3, [r7, #0]
8001ff2: 691a ldr r2, [r3, #16]
8001ff4: 687b ldr r3, [r7, #4]
8001ff6: 631a str r2, [r3, #48] ; 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8001ff8: 687b ldr r3, [r7, #4]
8001ffa: 2201 movs r2, #1
8001ffc: 615a str r2, [r3, #20]
}
8001ffe: bf00 nop
8002000: 3714 adds r7, #20
8002002: 46bd mov sp, r7
8002004: f85d 7b04 ldr.w r7, [sp], #4
8002008: 4770 bx lr
800200a: bf00 nop
800200c: 40010000 .word 0x40010000
8002010: 40000400 .word 0x40000400
8002014: 40000800 .word 0x40000800
8002018: 40000c00 .word 0x40000c00
800201c: 40014000 .word 0x40014000
8002020: 40014400 .word 0x40014400
8002024: 40014800 .word 0x40014800
08002028 <HAL_TIMEx_CommutCallback>:
* @brief Hall commutation changed callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8002028: b480 push {r7}
800202a: b083 sub sp, #12
800202c: af00 add r7, sp, #0
800202e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8002030: bf00 nop
8002032: 370c adds r7, #12
8002034: 46bd mov sp, r7
8002036: f85d 7b04 ldr.w r7, [sp], #4
800203a: 4770 bx lr
0800203c <HAL_TIMEx_BreakCallback>:
* @brief Hall Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
800203c: b480 push {r7}
800203e: b083 sub sp, #12
8002040: af00 add r7, sp, #0
8002042: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8002044: bf00 nop
8002046: 370c adds r7, #12
8002048: 46bd mov sp, r7
800204a: f85d 7b04 ldr.w r7, [sp], #4
800204e: 4770 bx lr
08002050 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8002050: b580 push {r7, lr}
8002052: b082 sub sp, #8
8002054: af00 add r7, sp, #0
8002056: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8002058: 687b ldr r3, [r7, #4]
800205a: 2b00 cmp r3, #0
800205c: d101 bne.n 8002062 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800205e: 2301 movs r3, #1
8002060: e03f b.n 80020e2 <HAL_UART_Init+0x92>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
8002062: 687b ldr r3, [r7, #4]
8002064: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8002068: b2db uxtb r3, r3
800206a: 2b00 cmp r3, #0
800206c: d106 bne.n 800207c <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
800206e: 687b ldr r3, [r7, #4]
8002070: 2200 movs r2, #0
8002072: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8002076: 6878 ldr r0, [r7, #4]
8002078: f7fe fcb0 bl 80009dc <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
800207c: 687b ldr r3, [r7, #4]
800207e: 2224 movs r2, #36 ; 0x24
8002080: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8002084: 687b ldr r3, [r7, #4]
8002086: 681b ldr r3, [r3, #0]
8002088: 68da ldr r2, [r3, #12]
800208a: 687b ldr r3, [r7, #4]
800208c: 681b ldr r3, [r3, #0]
800208e: f422 5200 bic.w r2, r2, #8192 ; 0x2000
8002092: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8002094: 6878 ldr r0, [r7, #4]
8002096: f000 f9cb bl 8002430 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800209a: 687b ldr r3, [r7, #4]
800209c: 681b ldr r3, [r3, #0]
800209e: 691a ldr r2, [r3, #16]
80020a0: 687b ldr r3, [r7, #4]
80020a2: 681b ldr r3, [r3, #0]
80020a4: f422 4290 bic.w r2, r2, #18432 ; 0x4800
80020a8: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80020aa: 687b ldr r3, [r7, #4]
80020ac: 681b ldr r3, [r3, #0]
80020ae: 695a ldr r2, [r3, #20]
80020b0: 687b ldr r3, [r7, #4]
80020b2: 681b ldr r3, [r3, #0]
80020b4: f022 022a bic.w r2, r2, #42 ; 0x2a
80020b8: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
80020ba: 687b ldr r3, [r7, #4]
80020bc: 681b ldr r3, [r3, #0]
80020be: 68da ldr r2, [r3, #12]
80020c0: 687b ldr r3, [r7, #4]
80020c2: 681b ldr r3, [r3, #0]
80020c4: f442 5200 orr.w r2, r2, #8192 ; 0x2000
80020c8: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80020ca: 687b ldr r3, [r7, #4]
80020cc: 2200 movs r2, #0
80020ce: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_READY;
80020d0: 687b ldr r3, [r7, #4]
80020d2: 2220 movs r2, #32
80020d4: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80020d8: 687b ldr r3, [r7, #4]
80020da: 2220 movs r2, #32
80020dc: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
80020e0: 2300 movs r3, #0
}
80020e2: 4618 mov r0, r3
80020e4: 3708 adds r7, #8
80020e6: 46bd mov sp, r7
80020e8: bd80 pop {r7, pc}
080020ea <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
80020ea: b580 push {r7, lr}
80020ec: b08a sub sp, #40 ; 0x28
80020ee: af02 add r7, sp, #8
80020f0: 60f8 str r0, [r7, #12]
80020f2: 60b9 str r1, [r7, #8]
80020f4: 603b str r3, [r7, #0]
80020f6: 4613 mov r3, r2
80020f8: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart = 0U;
80020fa: 2300 movs r3, #0
80020fc: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
80020fe: 68fb ldr r3, [r7, #12]
8002100: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8002104: b2db uxtb r3, r3
8002106: 2b20 cmp r3, #32
8002108: d17c bne.n 8002204 <HAL_UART_Transmit+0x11a>
{
if ((pData == NULL) || (Size == 0U))
800210a: 68bb ldr r3, [r7, #8]
800210c: 2b00 cmp r3, #0
800210e: d002 beq.n 8002116 <HAL_UART_Transmit+0x2c>
8002110: 88fb ldrh r3, [r7, #6]
8002112: 2b00 cmp r3, #0
8002114: d101 bne.n 800211a <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
8002116: 2301 movs r3, #1
8002118: e075 b.n 8002206 <HAL_UART_Transmit+0x11c>
}
/* Process Locked */
__HAL_LOCK(huart);
800211a: 68fb ldr r3, [r7, #12]
800211c: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002120: 2b01 cmp r3, #1
8002122: d101 bne.n 8002128 <HAL_UART_Transmit+0x3e>
8002124: 2302 movs r3, #2
8002126: e06e b.n 8002206 <HAL_UART_Transmit+0x11c>
8002128: 68fb ldr r3, [r7, #12]
800212a: 2201 movs r2, #1
800212c: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8002130: 68fb ldr r3, [r7, #12]
8002132: 2200 movs r2, #0
8002134: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_BUSY_TX;
8002136: 68fb ldr r3, [r7, #12]
8002138: 2221 movs r2, #33 ; 0x21
800213a: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
800213e: f7fe fd99 bl 8000c74 <HAL_GetTick>
8002142: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8002144: 68fb ldr r3, [r7, #12]
8002146: 88fa ldrh r2, [r7, #6]
8002148: 849a strh r2, [r3, #36] ; 0x24
huart->TxXferCount = Size;
800214a: 68fb ldr r3, [r7, #12]
800214c: 88fa ldrh r2, [r7, #6]
800214e: 84da strh r2, [r3, #38] ; 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8002150: 68fb ldr r3, [r7, #12]
8002152: 689b ldr r3, [r3, #8]
8002154: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8002158: d108 bne.n 800216c <HAL_UART_Transmit+0x82>
800215a: 68fb ldr r3, [r7, #12]
800215c: 691b ldr r3, [r3, #16]
800215e: 2b00 cmp r3, #0
8002160: d104 bne.n 800216c <HAL_UART_Transmit+0x82>
{
pdata8bits = NULL;
8002162: 2300 movs r3, #0
8002164: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
8002166: 68bb ldr r3, [r7, #8]
8002168: 61bb str r3, [r7, #24]
800216a: e003 b.n 8002174 <HAL_UART_Transmit+0x8a>
}
else
{
pdata8bits = pData;
800216c: 68bb ldr r3, [r7, #8]
800216e: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8002170: 2300 movs r3, #0
8002172: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
8002174: 68fb ldr r3, [r7, #12]
8002176: 2200 movs r2, #0
8002178: f883 203c strb.w r2, [r3, #60] ; 0x3c
while (huart->TxXferCount > 0U)
800217c: e02a b.n 80021d4 <HAL_UART_Transmit+0xea>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
800217e: 683b ldr r3, [r7, #0]
8002180: 9300 str r3, [sp, #0]
8002182: 697b ldr r3, [r7, #20]
8002184: 2200 movs r2, #0
8002186: 2180 movs r1, #128 ; 0x80
8002188: 68f8 ldr r0, [r7, #12]
800218a: f000 f8e2 bl 8002352 <UART_WaitOnFlagUntilTimeout>
800218e: 4603 mov r3, r0
8002190: 2b00 cmp r3, #0
8002192: d001 beq.n 8002198 <HAL_UART_Transmit+0xae>
{
return HAL_TIMEOUT;
8002194: 2303 movs r3, #3
8002196: e036 b.n 8002206 <HAL_UART_Transmit+0x11c>
}
if (pdata8bits == NULL)
8002198: 69fb ldr r3, [r7, #28]
800219a: 2b00 cmp r3, #0
800219c: d10b bne.n 80021b6 <HAL_UART_Transmit+0xcc>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
800219e: 69bb ldr r3, [r7, #24]
80021a0: 881b ldrh r3, [r3, #0]
80021a2: 461a mov r2, r3
80021a4: 68fb ldr r3, [r7, #12]
80021a6: 681b ldr r3, [r3, #0]
80021a8: f3c2 0208 ubfx r2, r2, #0, #9
80021ac: 605a str r2, [r3, #4]
pdata16bits++;
80021ae: 69bb ldr r3, [r7, #24]
80021b0: 3302 adds r3, #2
80021b2: 61bb str r3, [r7, #24]
80021b4: e007 b.n 80021c6 <HAL_UART_Transmit+0xdc>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
80021b6: 69fb ldr r3, [r7, #28]
80021b8: 781a ldrb r2, [r3, #0]
80021ba: 68fb ldr r3, [r7, #12]
80021bc: 681b ldr r3, [r3, #0]
80021be: 605a str r2, [r3, #4]
pdata8bits++;
80021c0: 69fb ldr r3, [r7, #28]
80021c2: 3301 adds r3, #1
80021c4: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
80021c6: 68fb ldr r3, [r7, #12]
80021c8: 8cdb ldrh r3, [r3, #38] ; 0x26
80021ca: b29b uxth r3, r3
80021cc: 3b01 subs r3, #1
80021ce: b29a uxth r2, r3
80021d0: 68fb ldr r3, [r7, #12]
80021d2: 84da strh r2, [r3, #38] ; 0x26
while (huart->TxXferCount > 0U)
80021d4: 68fb ldr r3, [r7, #12]
80021d6: 8cdb ldrh r3, [r3, #38] ; 0x26
80021d8: b29b uxth r3, r3
80021da: 2b00 cmp r3, #0
80021dc: d1cf bne.n 800217e <HAL_UART_Transmit+0x94>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
80021de: 683b ldr r3, [r7, #0]
80021e0: 9300 str r3, [sp, #0]
80021e2: 697b ldr r3, [r7, #20]
80021e4: 2200 movs r2, #0
80021e6: 2140 movs r1, #64 ; 0x40
80021e8: 68f8 ldr r0, [r7, #12]
80021ea: f000 f8b2 bl 8002352 <UART_WaitOnFlagUntilTimeout>
80021ee: 4603 mov r3, r0
80021f0: 2b00 cmp r3, #0
80021f2: d001 beq.n 80021f8 <HAL_UART_Transmit+0x10e>
{
return HAL_TIMEOUT;
80021f4: 2303 movs r3, #3
80021f6: e006 b.n 8002206 <HAL_UART_Transmit+0x11c>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
80021f8: 68fb ldr r3, [r7, #12]
80021fa: 2220 movs r2, #32
80021fc: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8002200: 2300 movs r3, #0
8002202: e000 b.n 8002206 <HAL_UART_Transmit+0x11c>
}
else
{
return HAL_BUSY;
8002204: 2302 movs r3, #2
}
}
8002206: 4618 mov r0, r3
8002208: 3720 adds r7, #32
800220a: 46bd mov sp, r7
800220c: bd80 pop {r7, pc}
0800220e <HAL_UART_Receive>:
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800220e: b580 push {r7, lr}
8002210: b08a sub sp, #40 ; 0x28
8002212: af02 add r7, sp, #8
8002214: 60f8 str r0, [r7, #12]
8002216: 60b9 str r1, [r7, #8]
8002218: 603b str r3, [r7, #0]
800221a: 4613 mov r3, r2
800221c: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
800221e: 2300 movs r3, #0
8002220: 617b str r3, [r7, #20]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8002222: 68fb ldr r3, [r7, #12]
8002224: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8002228: b2db uxtb r3, r3
800222a: 2b20 cmp r3, #32
800222c: f040 808c bne.w 8002348 <HAL_UART_Receive+0x13a>
{
if ((pData == NULL) || (Size == 0U))
8002230: 68bb ldr r3, [r7, #8]
8002232: 2b00 cmp r3, #0
8002234: d002 beq.n 800223c <HAL_UART_Receive+0x2e>
8002236: 88fb ldrh r3, [r7, #6]
8002238: 2b00 cmp r3, #0
800223a: d101 bne.n 8002240 <HAL_UART_Receive+0x32>
{
return HAL_ERROR;
800223c: 2301 movs r3, #1
800223e: e084 b.n 800234a <HAL_UART_Receive+0x13c>
}
/* Process Locked */
__HAL_LOCK(huart);
8002240: 68fb ldr r3, [r7, #12]
8002242: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8002246: 2b01 cmp r3, #1
8002248: d101 bne.n 800224e <HAL_UART_Receive+0x40>
800224a: 2302 movs r3, #2
800224c: e07d b.n 800234a <HAL_UART_Receive+0x13c>
800224e: 68fb ldr r3, [r7, #12]
8002250: 2201 movs r2, #1
8002252: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8002256: 68fb ldr r3, [r7, #12]
8002258: 2200 movs r2, #0
800225a: 641a str r2, [r3, #64] ; 0x40
huart->RxState = HAL_UART_STATE_BUSY_RX;
800225c: 68fb ldr r3, [r7, #12]
800225e: 2222 movs r2, #34 ; 0x22
8002260: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8002264: 68fb ldr r3, [r7, #12]
8002266: 2200 movs r2, #0
8002268: 631a str r2, [r3, #48] ; 0x30
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
800226a: f7fe fd03 bl 8000c74 <HAL_GetTick>
800226e: 6178 str r0, [r7, #20]
huart->RxXferSize = Size;
8002270: 68fb ldr r3, [r7, #12]
8002272: 88fa ldrh r2, [r7, #6]
8002274: 859a strh r2, [r3, #44] ; 0x2c
huart->RxXferCount = Size;
8002276: 68fb ldr r3, [r7, #12]
8002278: 88fa ldrh r2, [r7, #6]
800227a: 85da strh r2, [r3, #46] ; 0x2e
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
800227c: 68fb ldr r3, [r7, #12]
800227e: 689b ldr r3, [r3, #8]
8002280: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8002284: d108 bne.n 8002298 <HAL_UART_Receive+0x8a>
8002286: 68fb ldr r3, [r7, #12]
8002288: 691b ldr r3, [r3, #16]
800228a: 2b00 cmp r3, #0
800228c: d104 bne.n 8002298 <HAL_UART_Receive+0x8a>
{
pdata8bits = NULL;
800228e: 2300 movs r3, #0
8002290: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
8002292: 68bb ldr r3, [r7, #8]
8002294: 61bb str r3, [r7, #24]
8002296: e003 b.n 80022a0 <HAL_UART_Receive+0x92>
}
else
{
pdata8bits = pData;
8002298: 68bb ldr r3, [r7, #8]
800229a: 61fb str r3, [r7, #28]
pdata16bits = NULL;
800229c: 2300 movs r3, #0
800229e: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
80022a0: 68fb ldr r3, [r7, #12]
80022a2: 2200 movs r2, #0
80022a4: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Check the remain data to be received */
while (huart->RxXferCount > 0U)
80022a8: e043 b.n 8002332 <HAL_UART_Receive+0x124>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
80022aa: 683b ldr r3, [r7, #0]
80022ac: 9300 str r3, [sp, #0]
80022ae: 697b ldr r3, [r7, #20]
80022b0: 2200 movs r2, #0
80022b2: 2120 movs r1, #32
80022b4: 68f8 ldr r0, [r7, #12]
80022b6: f000 f84c bl 8002352 <UART_WaitOnFlagUntilTimeout>
80022ba: 4603 mov r3, r0
80022bc: 2b00 cmp r3, #0
80022be: d001 beq.n 80022c4 <HAL_UART_Receive+0xb6>
{
return HAL_TIMEOUT;
80022c0: 2303 movs r3, #3
80022c2: e042 b.n 800234a <HAL_UART_Receive+0x13c>
}
if (pdata8bits == NULL)
80022c4: 69fb ldr r3, [r7, #28]
80022c6: 2b00 cmp r3, #0
80022c8: d10c bne.n 80022e4 <HAL_UART_Receive+0xd6>
{
*pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
80022ca: 68fb ldr r3, [r7, #12]
80022cc: 681b ldr r3, [r3, #0]
80022ce: 685b ldr r3, [r3, #4]
80022d0: b29b uxth r3, r3
80022d2: f3c3 0308 ubfx r3, r3, #0, #9
80022d6: b29a uxth r2, r3
80022d8: 69bb ldr r3, [r7, #24]
80022da: 801a strh r2, [r3, #0]
pdata16bits++;
80022dc: 69bb ldr r3, [r7, #24]
80022de: 3302 adds r3, #2
80022e0: 61bb str r3, [r7, #24]
80022e2: e01f b.n 8002324 <HAL_UART_Receive+0x116>
}
else
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
80022e4: 68fb ldr r3, [r7, #12]
80022e6: 689b ldr r3, [r3, #8]
80022e8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80022ec: d007 beq.n 80022fe <HAL_UART_Receive+0xf0>
80022ee: 68fb ldr r3, [r7, #12]
80022f0: 689b ldr r3, [r3, #8]
80022f2: 2b00 cmp r3, #0
80022f4: d10a bne.n 800230c <HAL_UART_Receive+0xfe>
80022f6: 68fb ldr r3, [r7, #12]
80022f8: 691b ldr r3, [r3, #16]
80022fa: 2b00 cmp r3, #0
80022fc: d106 bne.n 800230c <HAL_UART_Receive+0xfe>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
80022fe: 68fb ldr r3, [r7, #12]
8002300: 681b ldr r3, [r3, #0]
8002302: 685b ldr r3, [r3, #4]
8002304: b2da uxtb r2, r3
8002306: 69fb ldr r3, [r7, #28]
8002308: 701a strb r2, [r3, #0]
800230a: e008 b.n 800231e <HAL_UART_Receive+0x110>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
800230c: 68fb ldr r3, [r7, #12]
800230e: 681b ldr r3, [r3, #0]
8002310: 685b ldr r3, [r3, #4]
8002312: b2db uxtb r3, r3
8002314: f003 037f and.w r3, r3, #127 ; 0x7f
8002318: b2da uxtb r2, r3
800231a: 69fb ldr r3, [r7, #28]
800231c: 701a strb r2, [r3, #0]
}
pdata8bits++;
800231e: 69fb ldr r3, [r7, #28]
8002320: 3301 adds r3, #1
8002322: 61fb str r3, [r7, #28]
}
huart->RxXferCount--;
8002324: 68fb ldr r3, [r7, #12]
8002326: 8ddb ldrh r3, [r3, #46] ; 0x2e
8002328: b29b uxth r3, r3
800232a: 3b01 subs r3, #1
800232c: b29a uxth r2, r3
800232e: 68fb ldr r3, [r7, #12]
8002330: 85da strh r2, [r3, #46] ; 0x2e
while (huart->RxXferCount > 0U)
8002332: 68fb ldr r3, [r7, #12]
8002334: 8ddb ldrh r3, [r3, #46] ; 0x2e
8002336: b29b uxth r3, r3
8002338: 2b00 cmp r3, #0
800233a: d1b6 bne.n 80022aa <HAL_UART_Receive+0x9c>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800233c: 68fb ldr r3, [r7, #12]
800233e: 2220 movs r2, #32
8002340: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8002344: 2300 movs r3, #0
8002346: e000 b.n 800234a <HAL_UART_Receive+0x13c>
}
else
{
return HAL_BUSY;
8002348: 2302 movs r3, #2
}
}
800234a: 4618 mov r0, r3
800234c: 3720 adds r7, #32
800234e: 46bd mov sp, r7
8002350: bd80 pop {r7, pc}
08002352 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8002352: b580 push {r7, lr}
8002354: b090 sub sp, #64 ; 0x40
8002356: af00 add r7, sp, #0
8002358: 60f8 str r0, [r7, #12]
800235a: 60b9 str r1, [r7, #8]
800235c: 603b str r3, [r7, #0]
800235e: 4613 mov r3, r2
8002360: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8002362: e050 b.n 8002406 <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8002364: 6cbb ldr r3, [r7, #72] ; 0x48
8002366: f1b3 3fff cmp.w r3, #4294967295
800236a: d04c beq.n 8002406 <UART_WaitOnFlagUntilTimeout+0xb4>
{
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
800236c: 6cbb ldr r3, [r7, #72] ; 0x48
800236e: 2b00 cmp r3, #0
8002370: d007 beq.n 8002382 <UART_WaitOnFlagUntilTimeout+0x30>
8002372: f7fe fc7f bl 8000c74 <HAL_GetTick>
8002376: 4602 mov r2, r0
8002378: 683b ldr r3, [r7, #0]
800237a: 1ad3 subs r3, r2, r3
800237c: 6cba ldr r2, [r7, #72] ; 0x48
800237e: 429a cmp r2, r3
8002380: d241 bcs.n 8002406 <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
8002382: 68fb ldr r3, [r7, #12]
8002384: 681b ldr r3, [r3, #0]
8002386: 330c adds r3, #12
8002388: 62bb str r3, [r7, #40] ; 0x28
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800238a: 6abb ldr r3, [r7, #40] ; 0x28
800238c: e853 3f00 ldrex r3, [r3]
8002390: 627b str r3, [r7, #36] ; 0x24
return(result);
8002392: 6a7b ldr r3, [r7, #36] ; 0x24
8002394: f423 73d0 bic.w r3, r3, #416 ; 0x1a0
8002398: 63fb str r3, [r7, #60] ; 0x3c
800239a: 68fb ldr r3, [r7, #12]
800239c: 681b ldr r3, [r3, #0]
800239e: 330c adds r3, #12
80023a0: 6bfa ldr r2, [r7, #60] ; 0x3c
80023a2: 637a str r2, [r7, #52] ; 0x34
80023a4: 633b str r3, [r7, #48] ; 0x30
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80023a6: 6b39 ldr r1, [r7, #48] ; 0x30
80023a8: 6b7a ldr r2, [r7, #52] ; 0x34
80023aa: e841 2300 strex r3, r2, [r1]
80023ae: 62fb str r3, [r7, #44] ; 0x2c
return(result);
80023b0: 6afb ldr r3, [r7, #44] ; 0x2c
80023b2: 2b00 cmp r3, #0
80023b4: d1e5 bne.n 8002382 <UART_WaitOnFlagUntilTimeout+0x30>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
80023b6: 68fb ldr r3, [r7, #12]
80023b8: 681b ldr r3, [r3, #0]
80023ba: 3314 adds r3, #20
80023bc: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80023be: 697b ldr r3, [r7, #20]
80023c0: e853 3f00 ldrex r3, [r3]
80023c4: 613b str r3, [r7, #16]
return(result);
80023c6: 693b ldr r3, [r7, #16]
80023c8: f023 0301 bic.w r3, r3, #1
80023cc: 63bb str r3, [r7, #56] ; 0x38
80023ce: 68fb ldr r3, [r7, #12]
80023d0: 681b ldr r3, [r3, #0]
80023d2: 3314 adds r3, #20
80023d4: 6bba ldr r2, [r7, #56] ; 0x38
80023d6: 623a str r2, [r7, #32]
80023d8: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80023da: 69f9 ldr r1, [r7, #28]
80023dc: 6a3a ldr r2, [r7, #32]
80023de: e841 2300 strex r3, r2, [r1]
80023e2: 61bb str r3, [r7, #24]
return(result);
80023e4: 69bb ldr r3, [r7, #24]
80023e6: 2b00 cmp r3, #0
80023e8: d1e5 bne.n 80023b6 <UART_WaitOnFlagUntilTimeout+0x64>
huart->gState = HAL_UART_STATE_READY;
80023ea: 68fb ldr r3, [r7, #12]
80023ec: 2220 movs r2, #32
80023ee: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
80023f2: 68fb ldr r3, [r7, #12]
80023f4: 2220 movs r2, #32
80023f6: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Process Unlocked */
__HAL_UNLOCK(huart);
80023fa: 68fb ldr r3, [r7, #12]
80023fc: 2200 movs r2, #0
80023fe: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
8002402: 2303 movs r3, #3
8002404: e00f b.n 8002426 <UART_WaitOnFlagUntilTimeout+0xd4>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8002406: 68fb ldr r3, [r7, #12]
8002408: 681b ldr r3, [r3, #0]
800240a: 681a ldr r2, [r3, #0]
800240c: 68bb ldr r3, [r7, #8]
800240e: 4013 ands r3, r2
8002410: 68ba ldr r2, [r7, #8]
8002412: 429a cmp r2, r3
8002414: bf0c ite eq
8002416: 2301 moveq r3, #1
8002418: 2300 movne r3, #0
800241a: b2db uxtb r3, r3
800241c: 461a mov r2, r3
800241e: 79fb ldrb r3, [r7, #7]
8002420: 429a cmp r2, r3
8002422: d09f beq.n 8002364 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
8002424: 2300 movs r3, #0
}
8002426: 4618 mov r0, r3
8002428: 3740 adds r7, #64 ; 0x40
800242a: 46bd mov sp, r7
800242c: bd80 pop {r7, pc}
...
08002430 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8002430: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8002434: b0c0 sub sp, #256 ; 0x100
8002436: af00 add r7, sp, #0
8002438: f8c7 00f4 str.w r0, [r7, #244] ; 0xf4
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
800243c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002440: 681b ldr r3, [r3, #0]
8002442: 691b ldr r3, [r3, #16]
8002444: f423 5040 bic.w r0, r3, #12288 ; 0x3000
8002448: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800244c: 68d9 ldr r1, [r3, #12]
800244e: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002452: 681a ldr r2, [r3, #0]
8002454: ea40 0301 orr.w r3, r0, r1
8002458: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
800245a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800245e: 689a ldr r2, [r3, #8]
8002460: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002464: 691b ldr r3, [r3, #16]
8002466: 431a orrs r2, r3
8002468: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800246c: 695b ldr r3, [r3, #20]
800246e: 431a orrs r2, r3
8002470: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002474: 69db ldr r3, [r3, #28]
8002476: 4313 orrs r3, r2
8002478: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8
MODIFY_REG(huart->Instance->CR1,
800247c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002480: 681b ldr r3, [r3, #0]
8002482: 68db ldr r3, [r3, #12]
8002484: f423 4116 bic.w r1, r3, #38400 ; 0x9600
8002488: f021 010c bic.w r1, r1, #12
800248c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002490: 681a ldr r2, [r3, #0]
8002492: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8
8002496: 430b orrs r3, r1
8002498: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
800249a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800249e: 681b ldr r3, [r3, #0]
80024a0: 695b ldr r3, [r3, #20]
80024a2: f423 7040 bic.w r0, r3, #768 ; 0x300
80024a6: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80024aa: 6999 ldr r1, [r3, #24]
80024ac: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80024b0: 681a ldr r2, [r3, #0]
80024b2: ea40 0301 orr.w r3, r0, r1
80024b6: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
80024b8: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80024bc: 681a ldr r2, [r3, #0]
80024be: 4b8f ldr r3, [pc, #572] ; (80026fc <UART_SetConfig+0x2cc>)
80024c0: 429a cmp r2, r3
80024c2: d005 beq.n 80024d0 <UART_SetConfig+0xa0>
80024c4: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80024c8: 681a ldr r2, [r3, #0]
80024ca: 4b8d ldr r3, [pc, #564] ; (8002700 <UART_SetConfig+0x2d0>)
80024cc: 429a cmp r2, r3
80024ce: d104 bne.n 80024da <UART_SetConfig+0xaa>
{
pclk = HAL_RCC_GetPCLK2Freq();
80024d0: f7ff faf8 bl 8001ac4 <HAL_RCC_GetPCLK2Freq>
80024d4: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
80024d8: e003 b.n 80024e2 <UART_SetConfig+0xb2>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
80024da: f7ff fadf bl 8001a9c <HAL_RCC_GetPCLK1Freq>
80024de: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
80024e2: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80024e6: 69db ldr r3, [r3, #28]
80024e8: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
80024ec: f040 810c bne.w 8002708 <UART_SetConfig+0x2d8>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
80024f0: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
80024f4: 2200 movs r2, #0
80024f6: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8
80024fa: f8c7 20ec str.w r2, [r7, #236] ; 0xec
80024fe: e9d7 453a ldrd r4, r5, [r7, #232] ; 0xe8
8002502: 4622 mov r2, r4
8002504: 462b mov r3, r5
8002506: 1891 adds r1, r2, r2
8002508: 65b9 str r1, [r7, #88] ; 0x58
800250a: 415b adcs r3, r3
800250c: 65fb str r3, [r7, #92] ; 0x5c
800250e: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58
8002512: 4621 mov r1, r4
8002514: eb12 0801 adds.w r8, r2, r1
8002518: 4629 mov r1, r5
800251a: eb43 0901 adc.w r9, r3, r1
800251e: f04f 0200 mov.w r2, #0
8002522: f04f 0300 mov.w r3, #0
8002526: ea4f 03c9 mov.w r3, r9, lsl #3
800252a: ea43 7358 orr.w r3, r3, r8, lsr #29
800252e: ea4f 02c8 mov.w r2, r8, lsl #3
8002532: 4690 mov r8, r2
8002534: 4699 mov r9, r3
8002536: 4623 mov r3, r4
8002538: eb18 0303 adds.w r3, r8, r3
800253c: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
8002540: 462b mov r3, r5
8002542: eb49 0303 adc.w r3, r9, r3
8002546: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
800254a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800254e: 685b ldr r3, [r3, #4]
8002550: 2200 movs r2, #0
8002552: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
8002556: f8c7 20dc str.w r2, [r7, #220] ; 0xdc
800255a: e9d7 1236 ldrd r1, r2, [r7, #216] ; 0xd8
800255e: 460b mov r3, r1
8002560: 18db adds r3, r3, r3
8002562: 653b str r3, [r7, #80] ; 0x50
8002564: 4613 mov r3, r2
8002566: eb42 0303 adc.w r3, r2, r3
800256a: 657b str r3, [r7, #84] ; 0x54
800256c: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50
8002570: e9d7 0138 ldrd r0, r1, [r7, #224] ; 0xe0
8002574: f7fd fe34 bl 80001e0 <__aeabi_uldivmod>
8002578: 4602 mov r2, r0
800257a: 460b mov r3, r1
800257c: 4b61 ldr r3, [pc, #388] ; (8002704 <UART_SetConfig+0x2d4>)
800257e: fba3 2302 umull r2, r3, r3, r2
8002582: 095b lsrs r3, r3, #5
8002584: 011c lsls r4, r3, #4
8002586: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
800258a: 2200 movs r2, #0
800258c: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
8002590: f8c7 20d4 str.w r2, [r7, #212] ; 0xd4
8002594: e9d7 8934 ldrd r8, r9, [r7, #208] ; 0xd0
8002598: 4642 mov r2, r8
800259a: 464b mov r3, r9
800259c: 1891 adds r1, r2, r2
800259e: 64b9 str r1, [r7, #72] ; 0x48
80025a0: 415b adcs r3, r3
80025a2: 64fb str r3, [r7, #76] ; 0x4c
80025a4: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48
80025a8: 4641 mov r1, r8
80025aa: eb12 0a01 adds.w sl, r2, r1
80025ae: 4649 mov r1, r9
80025b0: eb43 0b01 adc.w fp, r3, r1
80025b4: f04f 0200 mov.w r2, #0
80025b8: f04f 0300 mov.w r3, #0
80025bc: ea4f 03cb mov.w r3, fp, lsl #3
80025c0: ea43 735a orr.w r3, r3, sl, lsr #29
80025c4: ea4f 02ca mov.w r2, sl, lsl #3
80025c8: 4692 mov sl, r2
80025ca: 469b mov fp, r3
80025cc: 4643 mov r3, r8
80025ce: eb1a 0303 adds.w r3, sl, r3
80025d2: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
80025d6: 464b mov r3, r9
80025d8: eb4b 0303 adc.w r3, fp, r3
80025dc: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
80025e0: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80025e4: 685b ldr r3, [r3, #4]
80025e6: 2200 movs r2, #0
80025e8: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
80025ec: f8c7 20c4 str.w r2, [r7, #196] ; 0xc4
80025f0: e9d7 1230 ldrd r1, r2, [r7, #192] ; 0xc0
80025f4: 460b mov r3, r1
80025f6: 18db adds r3, r3, r3
80025f8: 643b str r3, [r7, #64] ; 0x40
80025fa: 4613 mov r3, r2
80025fc: eb42 0303 adc.w r3, r2, r3
8002600: 647b str r3, [r7, #68] ; 0x44
8002602: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40
8002606: e9d7 0132 ldrd r0, r1, [r7, #200] ; 0xc8
800260a: f7fd fde9 bl 80001e0 <__aeabi_uldivmod>
800260e: 4602 mov r2, r0
8002610: 460b mov r3, r1
8002612: 4611 mov r1, r2
8002614: 4b3b ldr r3, [pc, #236] ; (8002704 <UART_SetConfig+0x2d4>)
8002616: fba3 2301 umull r2, r3, r3, r1
800261a: 095b lsrs r3, r3, #5
800261c: 2264 movs r2, #100 ; 0x64
800261e: fb02 f303 mul.w r3, r2, r3
8002622: 1acb subs r3, r1, r3
8002624: 00db lsls r3, r3, #3
8002626: f103 0232 add.w r2, r3, #50 ; 0x32
800262a: 4b36 ldr r3, [pc, #216] ; (8002704 <UART_SetConfig+0x2d4>)
800262c: fba3 2302 umull r2, r3, r3, r2
8002630: 095b lsrs r3, r3, #5
8002632: 005b lsls r3, r3, #1
8002634: f403 73f8 and.w r3, r3, #496 ; 0x1f0
8002638: 441c add r4, r3
800263a: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
800263e: 2200 movs r2, #0
8002640: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
8002644: f8c7 20bc str.w r2, [r7, #188] ; 0xbc
8002648: e9d7 892e ldrd r8, r9, [r7, #184] ; 0xb8
800264c: 4642 mov r2, r8
800264e: 464b mov r3, r9
8002650: 1891 adds r1, r2, r2
8002652: 63b9 str r1, [r7, #56] ; 0x38
8002654: 415b adcs r3, r3
8002656: 63fb str r3, [r7, #60] ; 0x3c
8002658: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38
800265c: 4641 mov r1, r8
800265e: 1851 adds r1, r2, r1
8002660: 6339 str r1, [r7, #48] ; 0x30
8002662: 4649 mov r1, r9
8002664: 414b adcs r3, r1
8002666: 637b str r3, [r7, #52] ; 0x34
8002668: f04f 0200 mov.w r2, #0
800266c: f04f 0300 mov.w r3, #0
8002670: e9d7 ab0c ldrd sl, fp, [r7, #48] ; 0x30
8002674: 4659 mov r1, fp
8002676: 00cb lsls r3, r1, #3
8002678: 4651 mov r1, sl
800267a: ea43 7351 orr.w r3, r3, r1, lsr #29
800267e: 4651 mov r1, sl
8002680: 00ca lsls r2, r1, #3
8002682: 4610 mov r0, r2
8002684: 4619 mov r1, r3
8002686: 4603 mov r3, r0
8002688: 4642 mov r2, r8
800268a: 189b adds r3, r3, r2
800268c: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
8002690: 464b mov r3, r9
8002692: 460a mov r2, r1
8002694: eb42 0303 adc.w r3, r2, r3
8002698: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
800269c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80026a0: 685b ldr r3, [r3, #4]
80026a2: 2200 movs r2, #0
80026a4: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
80026a8: f8c7 20ac str.w r2, [r7, #172] ; 0xac
80026ac: e9d7 122a ldrd r1, r2, [r7, #168] ; 0xa8
80026b0: 460b mov r3, r1
80026b2: 18db adds r3, r3, r3
80026b4: 62bb str r3, [r7, #40] ; 0x28
80026b6: 4613 mov r3, r2
80026b8: eb42 0303 adc.w r3, r2, r3
80026bc: 62fb str r3, [r7, #44] ; 0x2c
80026be: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
80026c2: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0
80026c6: f7fd fd8b bl 80001e0 <__aeabi_uldivmod>
80026ca: 4602 mov r2, r0
80026cc: 460b mov r3, r1
80026ce: 4b0d ldr r3, [pc, #52] ; (8002704 <UART_SetConfig+0x2d4>)
80026d0: fba3 1302 umull r1, r3, r3, r2
80026d4: 095b lsrs r3, r3, #5
80026d6: 2164 movs r1, #100 ; 0x64
80026d8: fb01 f303 mul.w r3, r1, r3
80026dc: 1ad3 subs r3, r2, r3
80026de: 00db lsls r3, r3, #3
80026e0: 3332 adds r3, #50 ; 0x32
80026e2: 4a08 ldr r2, [pc, #32] ; (8002704 <UART_SetConfig+0x2d4>)
80026e4: fba2 2303 umull r2, r3, r2, r3
80026e8: 095b lsrs r3, r3, #5
80026ea: f003 0207 and.w r2, r3, #7
80026ee: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80026f2: 681b ldr r3, [r3, #0]
80026f4: 4422 add r2, r4
80026f6: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
80026f8: e106 b.n 8002908 <UART_SetConfig+0x4d8>
80026fa: bf00 nop
80026fc: 40011000 .word 0x40011000
8002700: 40011400 .word 0x40011400
8002704: 51eb851f .word 0x51eb851f
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8002708: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
800270c: 2200 movs r2, #0
800270e: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
8002712: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
8002716: e9d7 8928 ldrd r8, r9, [r7, #160] ; 0xa0
800271a: 4642 mov r2, r8
800271c: 464b mov r3, r9
800271e: 1891 adds r1, r2, r2
8002720: 6239 str r1, [r7, #32]
8002722: 415b adcs r3, r3
8002724: 627b str r3, [r7, #36] ; 0x24
8002726: e9d7 2308 ldrd r2, r3, [r7, #32]
800272a: 4641 mov r1, r8
800272c: 1854 adds r4, r2, r1
800272e: 4649 mov r1, r9
8002730: eb43 0501 adc.w r5, r3, r1
8002734: f04f 0200 mov.w r2, #0
8002738: f04f 0300 mov.w r3, #0
800273c: 00eb lsls r3, r5, #3
800273e: ea43 7354 orr.w r3, r3, r4, lsr #29
8002742: 00e2 lsls r2, r4, #3
8002744: 4614 mov r4, r2
8002746: 461d mov r5, r3
8002748: 4643 mov r3, r8
800274a: 18e3 adds r3, r4, r3
800274c: f8c7 3098 str.w r3, [r7, #152] ; 0x98
8002750: 464b mov r3, r9
8002752: eb45 0303 adc.w r3, r5, r3
8002756: f8c7 309c str.w r3, [r7, #156] ; 0x9c
800275a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
800275e: 685b ldr r3, [r3, #4]
8002760: 2200 movs r2, #0
8002762: f8c7 3090 str.w r3, [r7, #144] ; 0x90
8002766: f8c7 2094 str.w r2, [r7, #148] ; 0x94
800276a: f04f 0200 mov.w r2, #0
800276e: f04f 0300 mov.w r3, #0
8002772: e9d7 4524 ldrd r4, r5, [r7, #144] ; 0x90
8002776: 4629 mov r1, r5
8002778: 008b lsls r3, r1, #2
800277a: 4621 mov r1, r4
800277c: ea43 7391 orr.w r3, r3, r1, lsr #30
8002780: 4621 mov r1, r4
8002782: 008a lsls r2, r1, #2
8002784: e9d7 0126 ldrd r0, r1, [r7, #152] ; 0x98
8002788: f7fd fd2a bl 80001e0 <__aeabi_uldivmod>
800278c: 4602 mov r2, r0
800278e: 460b mov r3, r1
8002790: 4b60 ldr r3, [pc, #384] ; (8002914 <UART_SetConfig+0x4e4>)
8002792: fba3 2302 umull r2, r3, r3, r2
8002796: 095b lsrs r3, r3, #5
8002798: 011c lsls r4, r3, #4
800279a: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
800279e: 2200 movs r2, #0
80027a0: f8c7 3088 str.w r3, [r7, #136] ; 0x88
80027a4: f8c7 208c str.w r2, [r7, #140] ; 0x8c
80027a8: e9d7 8922 ldrd r8, r9, [r7, #136] ; 0x88
80027ac: 4642 mov r2, r8
80027ae: 464b mov r3, r9
80027b0: 1891 adds r1, r2, r2
80027b2: 61b9 str r1, [r7, #24]
80027b4: 415b adcs r3, r3
80027b6: 61fb str r3, [r7, #28]
80027b8: e9d7 2306 ldrd r2, r3, [r7, #24]
80027bc: 4641 mov r1, r8
80027be: 1851 adds r1, r2, r1
80027c0: 6139 str r1, [r7, #16]
80027c2: 4649 mov r1, r9
80027c4: 414b adcs r3, r1
80027c6: 617b str r3, [r7, #20]
80027c8: f04f 0200 mov.w r2, #0
80027cc: f04f 0300 mov.w r3, #0
80027d0: e9d7 ab04 ldrd sl, fp, [r7, #16]
80027d4: 4659 mov r1, fp
80027d6: 00cb lsls r3, r1, #3
80027d8: 4651 mov r1, sl
80027da: ea43 7351 orr.w r3, r3, r1, lsr #29
80027de: 4651 mov r1, sl
80027e0: 00ca lsls r2, r1, #3
80027e2: 4610 mov r0, r2
80027e4: 4619 mov r1, r3
80027e6: 4603 mov r3, r0
80027e8: 4642 mov r2, r8
80027ea: 189b adds r3, r3, r2
80027ec: f8c7 3080 str.w r3, [r7, #128] ; 0x80
80027f0: 464b mov r3, r9
80027f2: 460a mov r2, r1
80027f4: eb42 0303 adc.w r3, r2, r3
80027f8: f8c7 3084 str.w r3, [r7, #132] ; 0x84
80027fc: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002800: 685b ldr r3, [r3, #4]
8002802: 2200 movs r2, #0
8002804: 67bb str r3, [r7, #120] ; 0x78
8002806: 67fa str r2, [r7, #124] ; 0x7c
8002808: f04f 0200 mov.w r2, #0
800280c: f04f 0300 mov.w r3, #0
8002810: e9d7 891e ldrd r8, r9, [r7, #120] ; 0x78
8002814: 4649 mov r1, r9
8002816: 008b lsls r3, r1, #2
8002818: 4641 mov r1, r8
800281a: ea43 7391 orr.w r3, r3, r1, lsr #30
800281e: 4641 mov r1, r8
8002820: 008a lsls r2, r1, #2
8002822: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80
8002826: f7fd fcdb bl 80001e0 <__aeabi_uldivmod>
800282a: 4602 mov r2, r0
800282c: 460b mov r3, r1
800282e: 4611 mov r1, r2
8002830: 4b38 ldr r3, [pc, #224] ; (8002914 <UART_SetConfig+0x4e4>)
8002832: fba3 2301 umull r2, r3, r3, r1
8002836: 095b lsrs r3, r3, #5
8002838: 2264 movs r2, #100 ; 0x64
800283a: fb02 f303 mul.w r3, r2, r3
800283e: 1acb subs r3, r1, r3
8002840: 011b lsls r3, r3, #4
8002842: 3332 adds r3, #50 ; 0x32
8002844: 4a33 ldr r2, [pc, #204] ; (8002914 <UART_SetConfig+0x4e4>)
8002846: fba2 2303 umull r2, r3, r2, r3
800284a: 095b lsrs r3, r3, #5
800284c: f003 03f0 and.w r3, r3, #240 ; 0xf0
8002850: 441c add r4, r3
8002852: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8002856: 2200 movs r2, #0
8002858: 673b str r3, [r7, #112] ; 0x70
800285a: 677a str r2, [r7, #116] ; 0x74
800285c: e9d7 891c ldrd r8, r9, [r7, #112] ; 0x70
8002860: 4642 mov r2, r8
8002862: 464b mov r3, r9
8002864: 1891 adds r1, r2, r2
8002866: 60b9 str r1, [r7, #8]
8002868: 415b adcs r3, r3
800286a: 60fb str r3, [r7, #12]
800286c: e9d7 2302 ldrd r2, r3, [r7, #8]
8002870: 4641 mov r1, r8
8002872: 1851 adds r1, r2, r1
8002874: 6039 str r1, [r7, #0]
8002876: 4649 mov r1, r9
8002878: 414b adcs r3, r1
800287a: 607b str r3, [r7, #4]
800287c: f04f 0200 mov.w r2, #0
8002880: f04f 0300 mov.w r3, #0
8002884: e9d7 ab00 ldrd sl, fp, [r7]
8002888: 4659 mov r1, fp
800288a: 00cb lsls r3, r1, #3
800288c: 4651 mov r1, sl
800288e: ea43 7351 orr.w r3, r3, r1, lsr #29
8002892: 4651 mov r1, sl
8002894: 00ca lsls r2, r1, #3
8002896: 4610 mov r0, r2
8002898: 4619 mov r1, r3
800289a: 4603 mov r3, r0
800289c: 4642 mov r2, r8
800289e: 189b adds r3, r3, r2
80028a0: 66bb str r3, [r7, #104] ; 0x68
80028a2: 464b mov r3, r9
80028a4: 460a mov r2, r1
80028a6: eb42 0303 adc.w r3, r2, r3
80028aa: 66fb str r3, [r7, #108] ; 0x6c
80028ac: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
80028b0: 685b ldr r3, [r3, #4]
80028b2: 2200 movs r2, #0
80028b4: 663b str r3, [r7, #96] ; 0x60
80028b6: 667a str r2, [r7, #100] ; 0x64
80028b8: f04f 0200 mov.w r2, #0
80028bc: f04f 0300 mov.w r3, #0
80028c0: e9d7 8918 ldrd r8, r9, [r7, #96] ; 0x60
80028c4: 4649 mov r1, r9
80028c6: 008b lsls r3, r1, #2
80028c8: 4641 mov r1, r8
80028ca: ea43 7391 orr.w r3, r3, r1, lsr #30
80028ce: 4641 mov r1, r8
80028d0: 008a lsls r2, r1, #2
80028d2: e9d7 011a ldrd r0, r1, [r7, #104] ; 0x68
80028d6: f7fd fc83 bl 80001e0 <__aeabi_uldivmod>
80028da: 4602 mov r2, r0
80028dc: 460b mov r3, r1
80028de: 4b0d ldr r3, [pc, #52] ; (8002914 <UART_SetConfig+0x4e4>)
80028e0: fba3 1302 umull r1, r3, r3, r2
80028e4: 095b lsrs r3, r3, #5
80028e6: 2164 movs r1, #100 ; 0x64
80028e8: fb01 f303 mul.w r3, r1, r3
80028ec: 1ad3 subs r3, r2, r3
80028ee: 011b lsls r3, r3, #4
80028f0: 3332 adds r3, #50 ; 0x32
80028f2: 4a08 ldr r2, [pc, #32] ; (8002914 <UART_SetConfig+0x4e4>)
80028f4: fba2 2303 umull r2, r3, r2, r3
80028f8: 095b lsrs r3, r3, #5
80028fa: f003 020f and.w r2, r3, #15
80028fe: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002902: 681b ldr r3, [r3, #0]
8002904: 4422 add r2, r4
8002906: 609a str r2, [r3, #8]
}
8002908: bf00 nop
800290a: f507 7780 add.w r7, r7, #256 ; 0x100
800290e: 46bd mov sp, r7
8002910: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8002914: 51eb851f .word 0x51eb851f
08002918 <__NVIC_SetPriority>:
{
8002918: b480 push {r7}
800291a: b083 sub sp, #12
800291c: af00 add r7, sp, #0
800291e: 4603 mov r3, r0
8002920: 6039 str r1, [r7, #0]
8002922: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002924: f997 3007 ldrsb.w r3, [r7, #7]
8002928: 2b00 cmp r3, #0
800292a: db0a blt.n 8002942 <__NVIC_SetPriority+0x2a>
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
800292c: 683b ldr r3, [r7, #0]
800292e: b2da uxtb r2, r3
8002930: 490c ldr r1, [pc, #48] ; (8002964 <__NVIC_SetPriority+0x4c>)
8002932: f997 3007 ldrsb.w r3, [r7, #7]
8002936: 0112 lsls r2, r2, #4
8002938: b2d2 uxtb r2, r2
800293a: 440b add r3, r1
800293c: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
8002940: e00a b.n 8002958 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002942: 683b ldr r3, [r7, #0]
8002944: b2da uxtb r2, r3
8002946: 4908 ldr r1, [pc, #32] ; (8002968 <__NVIC_SetPriority+0x50>)
8002948: 79fb ldrb r3, [r7, #7]
800294a: f003 030f and.w r3, r3, #15
800294e: 3b04 subs r3, #4
8002950: 0112 lsls r2, r2, #4
8002952: b2d2 uxtb r2, r2
8002954: 440b add r3, r1
8002956: 761a strb r2, [r3, #24]
}
8002958: bf00 nop
800295a: 370c adds r7, #12
800295c: 46bd mov sp, r7
800295e: f85d 7b04 ldr.w r7, [sp], #4
8002962: 4770 bx lr
8002964: e000e100 .word 0xe000e100
8002968: e000ed00 .word 0xe000ed00
0800296c <SysTick_Handler>:
/*
SysTick handler implementation that also clears overflow flag.
*/
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
800296c: b580 push {r7, lr}
800296e: af00 add r7, sp, #0
/* Clear overflow flag */
SysTick->CTRL;
8002970: 4b05 ldr r3, [pc, #20] ; (8002988 <SysTick_Handler+0x1c>)
8002972: 681b ldr r3, [r3, #0]
if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
8002974: f001 fd0c bl 8004390 <xTaskGetSchedulerState>
8002978: 4603 mov r3, r0
800297a: 2b01 cmp r3, #1
800297c: d001 beq.n 8002982 <SysTick_Handler+0x16>
/* Call tick handler */
xPortSysTickHandler();
800297e: f002 faf3 bl 8004f68 <xPortSysTickHandler>
}
}
8002982: bf00 nop
8002984: bd80 pop {r7, pc}
8002986: bf00 nop
8002988: e000e010 .word 0xe000e010
0800298c <SVC_Setup>:
#endif /* SysTick */
/*
Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
800298c: b580 push {r7, lr}
800298e: af00 add r7, sp, #0
#if (__ARM_ARCH_7A__ == 0U)
/* Service Call interrupt might be configured before kernel start */
/* and when its priority is lower or equal to BASEPRI, svc intruction */
/* causes a Hard Fault. */
NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
8002990: 2100 movs r1, #0
8002992: f06f 0004 mvn.w r0, #4
8002996: f7ff ffbf bl 8002918 <__NVIC_SetPriority>
#endif
}
800299a: bf00 nop
800299c: bd80 pop {r7, pc}
...
080029a0 <osKernelInitialize>:
static uint32_t OS_Tick_GetOverflow (void);
/* Get OS Tick interval */
static uint32_t OS_Tick_GetInterval (void);
/*---------------------------------------------------------------------------*/
osStatus_t osKernelInitialize (void) {
80029a0: b480 push {r7}
80029a2: b083 sub sp, #12
80029a4: af00 add r7, sp, #0
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
80029a6: f3ef 8305 mrs r3, IPSR
80029aa: 603b str r3, [r7, #0]
return(result);
80029ac: 683b ldr r3, [r7, #0]
osStatus_t stat;
if (IS_IRQ()) {
80029ae: 2b00 cmp r3, #0
80029b0: d003 beq.n 80029ba <osKernelInitialize+0x1a>
stat = osErrorISR;
80029b2: f06f 0305 mvn.w r3, #5
80029b6: 607b str r3, [r7, #4]
80029b8: e00c b.n 80029d4 <osKernelInitialize+0x34>
}
else {
if (KernelState == osKernelInactive) {
80029ba: 4b0a ldr r3, [pc, #40] ; (80029e4 <osKernelInitialize+0x44>)
80029bc: 681b ldr r3, [r3, #0]
80029be: 2b00 cmp r3, #0
80029c0: d105 bne.n 80029ce <osKernelInitialize+0x2e>
EvrFreeRTOSSetup(0U);
#endif
#if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
vPortDefineHeapRegions (configHEAP_5_REGIONS);
#endif
KernelState = osKernelReady;
80029c2: 4b08 ldr r3, [pc, #32] ; (80029e4 <osKernelInitialize+0x44>)
80029c4: 2201 movs r2, #1
80029c6: 601a str r2, [r3, #0]
stat = osOK;
80029c8: 2300 movs r3, #0
80029ca: 607b str r3, [r7, #4]
80029cc: e002 b.n 80029d4 <osKernelInitialize+0x34>
} else {
stat = osError;
80029ce: f04f 33ff mov.w r3, #4294967295
80029d2: 607b str r3, [r7, #4]
}
}
return (stat);
80029d4: 687b ldr r3, [r7, #4]
}
80029d6: 4618 mov r0, r3
80029d8: 370c adds r7, #12
80029da: 46bd mov sp, r7
80029dc: f85d 7b04 ldr.w r7, [sp], #4
80029e0: 4770 bx lr
80029e2: bf00 nop
80029e4: 2000012c .word 0x2000012c
080029e8 <osKernelStart>:
}
return (state);
}
osStatus_t osKernelStart (void) {
80029e8: b580 push {r7, lr}
80029ea: b082 sub sp, #8
80029ec: af00 add r7, sp, #0
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
80029ee: f3ef 8305 mrs r3, IPSR
80029f2: 603b str r3, [r7, #0]
return(result);
80029f4: 683b ldr r3, [r7, #0]
osStatus_t stat;
if (IS_IRQ()) {
80029f6: 2b00 cmp r3, #0
80029f8: d003 beq.n 8002a02 <osKernelStart+0x1a>
stat = osErrorISR;
80029fa: f06f 0305 mvn.w r3, #5
80029fe: 607b str r3, [r7, #4]
8002a00: e010 b.n 8002a24 <osKernelStart+0x3c>
}
else {
if (KernelState == osKernelReady) {
8002a02: 4b0b ldr r3, [pc, #44] ; (8002a30 <osKernelStart+0x48>)
8002a04: 681b ldr r3, [r3, #0]
8002a06: 2b01 cmp r3, #1
8002a08: d109 bne.n 8002a1e <osKernelStart+0x36>
/* Ensure SVC priority is at the reset value */
SVC_Setup();
8002a0a: f7ff ffbf bl 800298c <SVC_Setup>
/* Change state to enable IRQ masking check */
KernelState = osKernelRunning;
8002a0e: 4b08 ldr r3, [pc, #32] ; (8002a30 <osKernelStart+0x48>)
8002a10: 2202 movs r2, #2
8002a12: 601a str r2, [r3, #0]
/* Start the kernel scheduler */
vTaskStartScheduler();
8002a14: f001 f860 bl 8003ad8 <vTaskStartScheduler>
stat = osOK;
8002a18: 2300 movs r3, #0
8002a1a: 607b str r3, [r7, #4]
8002a1c: e002 b.n 8002a24 <osKernelStart+0x3c>
} else {
stat = osError;
8002a1e: f04f 33ff mov.w r3, #4294967295
8002a22: 607b str r3, [r7, #4]
}
}
return (stat);
8002a24: 687b ldr r3, [r7, #4]
}
8002a26: 4618 mov r0, r3
8002a28: 3708 adds r7, #8
8002a2a: 46bd mov sp, r7
8002a2c: bd80 pop {r7, pc}
8002a2e: bf00 nop
8002a30: 2000012c .word 0x2000012c
08002a34 <osThreadNew>:
return (configCPU_CLOCK_HZ);
}
/*---------------------------------------------------------------------------*/
osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
8002a34: b580 push {r7, lr}
8002a36: b08e sub sp, #56 ; 0x38
8002a38: af04 add r7, sp, #16
8002a3a: 60f8 str r0, [r7, #12]
8002a3c: 60b9 str r1, [r7, #8]
8002a3e: 607a str r2, [r7, #4]
uint32_t stack;
TaskHandle_t hTask;
UBaseType_t prio;
int32_t mem;
hTask = NULL;
8002a40: 2300 movs r3, #0
8002a42: 613b str r3, [r7, #16]
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
8002a44: f3ef 8305 mrs r3, IPSR
8002a48: 617b str r3, [r7, #20]
return(result);
8002a4a: 697b ldr r3, [r7, #20]
if (!IS_IRQ() && (func != NULL)) {
8002a4c: 2b00 cmp r3, #0
8002a4e: d17e bne.n 8002b4e <osThreadNew+0x11a>
8002a50: 68fb ldr r3, [r7, #12]
8002a52: 2b00 cmp r3, #0
8002a54: d07b beq.n 8002b4e <osThreadNew+0x11a>
stack = configMINIMAL_STACK_SIZE;
8002a56: 2380 movs r3, #128 ; 0x80
8002a58: 623b str r3, [r7, #32]
prio = (UBaseType_t)osPriorityNormal;
8002a5a: 2318 movs r3, #24
8002a5c: 61fb str r3, [r7, #28]
name = NULL;
8002a5e: 2300 movs r3, #0
8002a60: 627b str r3, [r7, #36] ; 0x24
mem = -1;
8002a62: f04f 33ff mov.w r3, #4294967295
8002a66: 61bb str r3, [r7, #24]
if (attr != NULL) {
8002a68: 687b ldr r3, [r7, #4]
8002a6a: 2b00 cmp r3, #0
8002a6c: d045 beq.n 8002afa <osThreadNew+0xc6>
if (attr->name != NULL) {
8002a6e: 687b ldr r3, [r7, #4]
8002a70: 681b ldr r3, [r3, #0]
8002a72: 2b00 cmp r3, #0
8002a74: d002 beq.n 8002a7c <osThreadNew+0x48>
name = attr->name;
8002a76: 687b ldr r3, [r7, #4]
8002a78: 681b ldr r3, [r3, #0]
8002a7a: 627b str r3, [r7, #36] ; 0x24
}
if (attr->priority != osPriorityNone) {
8002a7c: 687b ldr r3, [r7, #4]
8002a7e: 699b ldr r3, [r3, #24]
8002a80: 2b00 cmp r3, #0
8002a82: d002 beq.n 8002a8a <osThreadNew+0x56>
prio = (UBaseType_t)attr->priority;
8002a84: 687b ldr r3, [r7, #4]
8002a86: 699b ldr r3, [r3, #24]
8002a88: 61fb str r3, [r7, #28]
}
if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
8002a8a: 69fb ldr r3, [r7, #28]
8002a8c: 2b00 cmp r3, #0
8002a8e: d008 beq.n 8002aa2 <osThreadNew+0x6e>
8002a90: 69fb ldr r3, [r7, #28]
8002a92: 2b38 cmp r3, #56 ; 0x38
8002a94: d805 bhi.n 8002aa2 <osThreadNew+0x6e>
8002a96: 687b ldr r3, [r7, #4]
8002a98: 685b ldr r3, [r3, #4]
8002a9a: f003 0301 and.w r3, r3, #1
8002a9e: 2b00 cmp r3, #0
8002aa0: d001 beq.n 8002aa6 <osThreadNew+0x72>
return (NULL);
8002aa2: 2300 movs r3, #0
8002aa4: e054 b.n 8002b50 <osThreadNew+0x11c>
}
if (attr->stack_size > 0U) {
8002aa6: 687b ldr r3, [r7, #4]
8002aa8: 695b ldr r3, [r3, #20]
8002aaa: 2b00 cmp r3, #0
8002aac: d003 beq.n 8002ab6 <osThreadNew+0x82>
/* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */
/* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
stack = attr->stack_size / sizeof(StackType_t);
8002aae: 687b ldr r3, [r7, #4]
8002ab0: 695b ldr r3, [r3, #20]
8002ab2: 089b lsrs r3, r3, #2
8002ab4: 623b str r3, [r7, #32]
}
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
8002ab6: 687b ldr r3, [r7, #4]
8002ab8: 689b ldr r3, [r3, #8]
8002aba: 2b00 cmp r3, #0
8002abc: d00e beq.n 8002adc <osThreadNew+0xa8>
8002abe: 687b ldr r3, [r7, #4]
8002ac0: 68db ldr r3, [r3, #12]
8002ac2: 2ba7 cmp r3, #167 ; 0xa7
8002ac4: d90a bls.n 8002adc <osThreadNew+0xa8>
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
8002ac6: 687b ldr r3, [r7, #4]
8002ac8: 691b ldr r3, [r3, #16]
if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) &&
8002aca: 2b00 cmp r3, #0
8002acc: d006 beq.n 8002adc <osThreadNew+0xa8>
(attr->stack_mem != NULL) && (attr->stack_size > 0U)) {
8002ace: 687b ldr r3, [r7, #4]
8002ad0: 695b ldr r3, [r3, #20]
8002ad2: 2b00 cmp r3, #0
8002ad4: d002 beq.n 8002adc <osThreadNew+0xa8>
mem = 1;
8002ad6: 2301 movs r3, #1
8002ad8: 61bb str r3, [r7, #24]
8002ada: e010 b.n 8002afe <osThreadNew+0xca>
}
else {
if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
8002adc: 687b ldr r3, [r7, #4]
8002ade: 689b ldr r3, [r3, #8]
8002ae0: 2b00 cmp r3, #0
8002ae2: d10c bne.n 8002afe <osThreadNew+0xca>
8002ae4: 687b ldr r3, [r7, #4]
8002ae6: 68db ldr r3, [r3, #12]
8002ae8: 2b00 cmp r3, #0
8002aea: d108 bne.n 8002afe <osThreadNew+0xca>
8002aec: 687b ldr r3, [r7, #4]
8002aee: 691b ldr r3, [r3, #16]
8002af0: 2b00 cmp r3, #0
8002af2: d104 bne.n 8002afe <osThreadNew+0xca>
mem = 0;
8002af4: 2300 movs r3, #0
8002af6: 61bb str r3, [r7, #24]
8002af8: e001 b.n 8002afe <osThreadNew+0xca>
}
}
}
else {
mem = 0;
8002afa: 2300 movs r3, #0
8002afc: 61bb str r3, [r7, #24]
}
if (mem == 1) {
8002afe: 69bb ldr r3, [r7, #24]
8002b00: 2b01 cmp r3, #1
8002b02: d110 bne.n 8002b26 <osThreadNew+0xf2>
#if (configSUPPORT_STATIC_ALLOCATION == 1)
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
8002b04: 687b ldr r3, [r7, #4]
8002b06: 691b ldr r3, [r3, #16]
(StaticTask_t *)attr->cb_mem);
8002b08: 687a ldr r2, [r7, #4]
8002b0a: 6892 ldr r2, [r2, #8]
hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem,
8002b0c: 9202 str r2, [sp, #8]
8002b0e: 9301 str r3, [sp, #4]
8002b10: 69fb ldr r3, [r7, #28]
8002b12: 9300 str r3, [sp, #0]
8002b14: 68bb ldr r3, [r7, #8]
8002b16: 6a3a ldr r2, [r7, #32]
8002b18: 6a79 ldr r1, [r7, #36] ; 0x24
8002b1a: 68f8 ldr r0, [r7, #12]
8002b1c: f000 fdf0 bl 8003700 <xTaskCreateStatic>
8002b20: 4603 mov r3, r0
8002b22: 613b str r3, [r7, #16]
8002b24: e013 b.n 8002b4e <osThreadNew+0x11a>
#endif
}
else {
if (mem == 0) {
8002b26: 69bb ldr r3, [r7, #24]
8002b28: 2b00 cmp r3, #0
8002b2a: d110 bne.n 8002b4e <osThreadNew+0x11a>
#if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
8002b2c: 6a3b ldr r3, [r7, #32]
8002b2e: b29a uxth r2, r3
8002b30: f107 0310 add.w r3, r7, #16
8002b34: 9301 str r3, [sp, #4]
8002b36: 69fb ldr r3, [r7, #28]
8002b38: 9300 str r3, [sp, #0]
8002b3a: 68bb ldr r3, [r7, #8]
8002b3c: 6a79 ldr r1, [r7, #36] ; 0x24
8002b3e: 68f8 ldr r0, [r7, #12]
8002b40: f000 fe3b bl 80037ba <xTaskCreate>
8002b44: 4603 mov r3, r0
8002b46: 2b01 cmp r3, #1
8002b48: d001 beq.n 8002b4e <osThreadNew+0x11a>
hTask = NULL;
8002b4a: 2300 movs r3, #0
8002b4c: 613b str r3, [r7, #16]
#endif
}
}
}
return ((osThreadId_t)hTask);
8002b4e: 693b ldr r3, [r7, #16]
}
8002b50: 4618 mov r0, r3
8002b52: 3728 adds r7, #40 ; 0x28
8002b54: 46bd mov sp, r7
8002b56: bd80 pop {r7, pc}
08002b58 <vApplicationGetIdleTaskMemory>:
/*
vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
8002b58: b480 push {r7}
8002b5a: b085 sub sp, #20
8002b5c: af00 add r7, sp, #0
8002b5e: 60f8 str r0, [r7, #12]
8002b60: 60b9 str r1, [r7, #8]
8002b62: 607a str r2, [r7, #4]
/* Idle task control block and stack */
static StaticTask_t Idle_TCB;
static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE];
*ppxIdleTaskTCBBuffer = &Idle_TCB;
8002b64: 68fb ldr r3, [r7, #12]
8002b66: 4a07 ldr r2, [pc, #28] ; (8002b84 <vApplicationGetIdleTaskMemory+0x2c>)
8002b68: 601a str r2, [r3, #0]
*ppxIdleTaskStackBuffer = &Idle_Stack[0];
8002b6a: 68bb ldr r3, [r7, #8]
8002b6c: 4a06 ldr r2, [pc, #24] ; (8002b88 <vApplicationGetIdleTaskMemory+0x30>)
8002b6e: 601a str r2, [r3, #0]
*pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE;
8002b70: 687b ldr r3, [r7, #4]
8002b72: 2280 movs r2, #128 ; 0x80
8002b74: 601a str r2, [r3, #0]
}
8002b76: bf00 nop
8002b78: 3714 adds r7, #20
8002b7a: 46bd mov sp, r7
8002b7c: f85d 7b04 ldr.w r7, [sp], #4
8002b80: 4770 bx lr
8002b82: bf00 nop
8002b84: 20000130 .word 0x20000130
8002b88: 200001d8 .word 0x200001d8
08002b8c <vApplicationGetTimerTaskMemory>:
/*
vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
8002b8c: b480 push {r7}
8002b8e: b085 sub sp, #20
8002b90: af00 add r7, sp, #0
8002b92: 60f8 str r0, [r7, #12]
8002b94: 60b9 str r1, [r7, #8]
8002b96: 607a str r2, [r7, #4]
/* Timer task control block and stack */
static StaticTask_t Timer_TCB;
static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH];
*ppxTimerTaskTCBBuffer = &Timer_TCB;
8002b98: 68fb ldr r3, [r7, #12]
8002b9a: 4a07 ldr r2, [pc, #28] ; (8002bb8 <vApplicationGetTimerTaskMemory+0x2c>)
8002b9c: 601a str r2, [r3, #0]
*ppxTimerTaskStackBuffer = &Timer_Stack[0];
8002b9e: 68bb ldr r3, [r7, #8]
8002ba0: 4a06 ldr r2, [pc, #24] ; (8002bbc <vApplicationGetTimerTaskMemory+0x30>)
8002ba2: 601a str r2, [r3, #0]
*pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH;
8002ba4: 687b ldr r3, [r7, #4]
8002ba6: f44f 7280 mov.w r2, #256 ; 0x100
8002baa: 601a str r2, [r3, #0]
}
8002bac: bf00 nop
8002bae: 3714 adds r7, #20
8002bb0: 46bd mov sp, r7
8002bb2: f85d 7b04 ldr.w r7, [sp], #4
8002bb6: 4770 bx lr
8002bb8: 200003d8 .word 0x200003d8
8002bbc: 20000480 .word 0x20000480
08002bc0 <vListInitialise>:
/*-----------------------------------------------------------
* PUBLIC LIST API documented in list.h
*----------------------------------------------------------*/
void vListInitialise( List_t * const pxList )
{
8002bc0: b480 push {r7}
8002bc2: b083 sub sp, #12
8002bc4: af00 add r7, sp, #0
8002bc6: 6078 str r0, [r7, #4]
/* The list structure contains a list item which is used to mark the
end of the list. To initialise the list the list end is inserted
as the only list entry. */
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8002bc8: 687b ldr r3, [r7, #4]
8002bca: f103 0208 add.w r2, r3, #8
8002bce: 687b ldr r3, [r7, #4]
8002bd0: 605a str r2, [r3, #4]
/* The list end value is the highest possible value in the list to
ensure it remains at the end of the list. */
pxList->xListEnd.xItemValue = portMAX_DELAY;
8002bd2: 687b ldr r3, [r7, #4]
8002bd4: f04f 32ff mov.w r2, #4294967295
8002bd8: 609a str r2, [r3, #8]
/* The list end next and previous pointers point to itself so we know
when the list is empty. */
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8002bda: 687b ldr r3, [r7, #4]
8002bdc: f103 0208 add.w r2, r3, #8
8002be0: 687b ldr r3, [r7, #4]
8002be2: 60da str r2, [r3, #12]
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
8002be4: 687b ldr r3, [r7, #4]
8002be6: f103 0208 add.w r2, r3, #8
8002bea: 687b ldr r3, [r7, #4]
8002bec: 611a str r2, [r3, #16]
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
8002bee: 687b ldr r3, [r7, #4]
8002bf0: 2200 movs r2, #0
8002bf2: 601a str r2, [r3, #0]
/* Write known values into the list if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
8002bf4: bf00 nop
8002bf6: 370c adds r7, #12
8002bf8: 46bd mov sp, r7
8002bfa: f85d 7b04 ldr.w r7, [sp], #4
8002bfe: 4770 bx lr
08002c00 <vListInitialiseItem>:
/*-----------------------------------------------------------*/
void vListInitialiseItem( ListItem_t * const pxItem )
{
8002c00: b480 push {r7}
8002c02: b083 sub sp, #12
8002c04: af00 add r7, sp, #0
8002c06: 6078 str r0, [r7, #4]
/* Make sure the list item is not recorded as being on a list. */
pxItem->pxContainer = NULL;
8002c08: 687b ldr r3, [r7, #4]
8002c0a: 2200 movs r2, #0
8002c0c: 611a str r2, [r3, #16]
/* Write known values into the list item if
configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
8002c0e: bf00 nop
8002c10: 370c adds r7, #12
8002c12: 46bd mov sp, r7
8002c14: f85d 7b04 ldr.w r7, [sp], #4
8002c18: 4770 bx lr
08002c1a <vListInsertEnd>:
/*-----------------------------------------------------------*/
void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8002c1a: b480 push {r7}
8002c1c: b085 sub sp, #20
8002c1e: af00 add r7, sp, #0
8002c20: 6078 str r0, [r7, #4]
8002c22: 6039 str r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
8002c24: 687b ldr r3, [r7, #4]
8002c26: 685b ldr r3, [r3, #4]
8002c28: 60fb str r3, [r7, #12]
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
/* Insert a new list item into pxList, but rather than sort the list,
makes the new list item the last item to be removed by a call to
listGET_OWNER_OF_NEXT_ENTRY(). */
pxNewListItem->pxNext = pxIndex;
8002c2a: 683b ldr r3, [r7, #0]
8002c2c: 68fa ldr r2, [r7, #12]
8002c2e: 605a str r2, [r3, #4]
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
8002c30: 68fb ldr r3, [r7, #12]
8002c32: 689a ldr r2, [r3, #8]
8002c34: 683b ldr r3, [r7, #0]
8002c36: 609a str r2, [r3, #8]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
pxIndex->pxPrevious->pxNext = pxNewListItem;
8002c38: 68fb ldr r3, [r7, #12]
8002c3a: 689b ldr r3, [r3, #8]
8002c3c: 683a ldr r2, [r7, #0]
8002c3e: 605a str r2, [r3, #4]
pxIndex->pxPrevious = pxNewListItem;
8002c40: 68fb ldr r3, [r7, #12]
8002c42: 683a ldr r2, [r7, #0]
8002c44: 609a str r2, [r3, #8]
/* Remember which list the item is in. */
pxNewListItem->pxContainer = pxList;
8002c46: 683b ldr r3, [r7, #0]
8002c48: 687a ldr r2, [r7, #4]
8002c4a: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8002c4c: 687b ldr r3, [r7, #4]
8002c4e: 681b ldr r3, [r3, #0]
8002c50: 1c5a adds r2, r3, #1
8002c52: 687b ldr r3, [r7, #4]
8002c54: 601a str r2, [r3, #0]
}
8002c56: bf00 nop
8002c58: 3714 adds r7, #20
8002c5a: 46bd mov sp, r7
8002c5c: f85d 7b04 ldr.w r7, [sp], #4
8002c60: 4770 bx lr
08002c62 <vListInsert>:
/*-----------------------------------------------------------*/
void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
8002c62: b480 push {r7}
8002c64: b085 sub sp, #20
8002c66: af00 add r7, sp, #0
8002c68: 6078 str r0, [r7, #4]
8002c6a: 6039 str r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
8002c6c: 683b ldr r3, [r7, #0]
8002c6e: 681b ldr r3, [r3, #0]
8002c70: 60bb str r3, [r7, #8]
new list item should be placed after it. This ensures that TCBs which are
stored in ready lists (all of which have the same xItemValue value) get a
share of the CPU. However, if the xItemValue is the same as the back marker
the iteration loop below will not end. Therefore the value is checked
first, and the algorithm slightly modified if necessary. */
if( xValueOfInsertion == portMAX_DELAY )
8002c72: 68bb ldr r3, [r7, #8]
8002c74: f1b3 3fff cmp.w r3, #4294967295
8002c78: d103 bne.n 8002c82 <vListInsert+0x20>
{
pxIterator = pxList->xListEnd.pxPrevious;
8002c7a: 687b ldr r3, [r7, #4]
8002c7c: 691b ldr r3, [r3, #16]
8002c7e: 60fb str r3, [r7, #12]
8002c80: e00c b.n 8002c9c <vListInsert+0x3a>
4) Using a queue or semaphore before it has been initialised or
before the scheduler has been started (are interrupts firing
before vTaskStartScheduler() has been called?).
**********************************************************************/
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
8002c82: 687b ldr r3, [r7, #4]
8002c84: 3308 adds r3, #8
8002c86: 60fb str r3, [r7, #12]
8002c88: e002 b.n 8002c90 <vListInsert+0x2e>
8002c8a: 68fb ldr r3, [r7, #12]
8002c8c: 685b ldr r3, [r3, #4]
8002c8e: 60fb str r3, [r7, #12]
8002c90: 68fb ldr r3, [r7, #12]
8002c92: 685b ldr r3, [r3, #4]
8002c94: 681b ldr r3, [r3, #0]
8002c96: 68ba ldr r2, [r7, #8]
8002c98: 429a cmp r2, r3
8002c9a: d2f6 bcs.n 8002c8a <vListInsert+0x28>
/* There is nothing to do here, just iterating to the wanted
insertion position. */
}
}
pxNewListItem->pxNext = pxIterator->pxNext;
8002c9c: 68fb ldr r3, [r7, #12]
8002c9e: 685a ldr r2, [r3, #4]
8002ca0: 683b ldr r3, [r7, #0]
8002ca2: 605a str r2, [r3, #4]
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
8002ca4: 683b ldr r3, [r7, #0]
8002ca6: 685b ldr r3, [r3, #4]
8002ca8: 683a ldr r2, [r7, #0]
8002caa: 609a str r2, [r3, #8]
pxNewListItem->pxPrevious = pxIterator;
8002cac: 683b ldr r3, [r7, #0]
8002cae: 68fa ldr r2, [r7, #12]
8002cb0: 609a str r2, [r3, #8]
pxIterator->pxNext = pxNewListItem;
8002cb2: 68fb ldr r3, [r7, #12]
8002cb4: 683a ldr r2, [r7, #0]
8002cb6: 605a str r2, [r3, #4]
/* Remember which list the item is in. This allows fast removal of the
item later. */
pxNewListItem->pxContainer = pxList;
8002cb8: 683b ldr r3, [r7, #0]
8002cba: 687a ldr r2, [r7, #4]
8002cbc: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )++;
8002cbe: 687b ldr r3, [r7, #4]
8002cc0: 681b ldr r3, [r3, #0]
8002cc2: 1c5a adds r2, r3, #1
8002cc4: 687b ldr r3, [r7, #4]
8002cc6: 601a str r2, [r3, #0]
}
8002cc8: bf00 nop
8002cca: 3714 adds r7, #20
8002ccc: 46bd mov sp, r7
8002cce: f85d 7b04 ldr.w r7, [sp], #4
8002cd2: 4770 bx lr
08002cd4 <uxListRemove>:
/*-----------------------------------------------------------*/
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
8002cd4: b480 push {r7}
8002cd6: b085 sub sp, #20
8002cd8: af00 add r7, sp, #0
8002cda: 6078 str r0, [r7, #4]
/* The list item knows which list it is in. Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
8002cdc: 687b ldr r3, [r7, #4]
8002cde: 691b ldr r3, [r3, #16]
8002ce0: 60fb str r3, [r7, #12]
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
8002ce2: 687b ldr r3, [r7, #4]
8002ce4: 685b ldr r3, [r3, #4]
8002ce6: 687a ldr r2, [r7, #4]
8002ce8: 6892 ldr r2, [r2, #8]
8002cea: 609a str r2, [r3, #8]
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
8002cec: 687b ldr r3, [r7, #4]
8002cee: 689b ldr r3, [r3, #8]
8002cf0: 687a ldr r2, [r7, #4]
8002cf2: 6852 ldr r2, [r2, #4]
8002cf4: 605a str r2, [r3, #4]
/* Only used during decision coverage testing. */
mtCOVERAGE_TEST_DELAY();
/* Make sure the index is left pointing to a valid item. */
if( pxList->pxIndex == pxItemToRemove )
8002cf6: 68fb ldr r3, [r7, #12]
8002cf8: 685b ldr r3, [r3, #4]
8002cfa: 687a ldr r2, [r7, #4]
8002cfc: 429a cmp r2, r3
8002cfe: d103 bne.n 8002d08 <uxListRemove+0x34>
{
pxList->pxIndex = pxItemToRemove->pxPrevious;
8002d00: 687b ldr r3, [r7, #4]
8002d02: 689a ldr r2, [r3, #8]
8002d04: 68fb ldr r3, [r7, #12]
8002d06: 605a str r2, [r3, #4]
else
{
mtCOVERAGE_TEST_MARKER();
}
pxItemToRemove->pxContainer = NULL;
8002d08: 687b ldr r3, [r7, #4]
8002d0a: 2200 movs r2, #0
8002d0c: 611a str r2, [r3, #16]
( pxList->uxNumberOfItems )--;
8002d0e: 68fb ldr r3, [r7, #12]
8002d10: 681b ldr r3, [r3, #0]
8002d12: 1e5a subs r2, r3, #1
8002d14: 68fb ldr r3, [r7, #12]
8002d16: 601a str r2, [r3, #0]
return pxList->uxNumberOfItems;
8002d18: 68fb ldr r3, [r7, #12]
8002d1a: 681b ldr r3, [r3, #0]
}
8002d1c: 4618 mov r0, r3
8002d1e: 3714 adds r7, #20
8002d20: 46bd mov sp, r7
8002d22: f85d 7b04 ldr.w r7, [sp], #4
8002d26: 4770 bx lr
08002d28 <xQueueGenericReset>:
} \
taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
8002d28: b580 push {r7, lr}
8002d2a: b084 sub sp, #16
8002d2c: af00 add r7, sp, #0
8002d2e: 6078 str r0, [r7, #4]
8002d30: 6039 str r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
8002d32: 687b ldr r3, [r7, #4]
8002d34: 60fb str r3, [r7, #12]
configASSERT( pxQueue );
8002d36: 68fb ldr r3, [r7, #12]
8002d38: 2b00 cmp r3, #0
8002d3a: d10a bne.n 8002d52 <xQueueGenericReset+0x2a>
portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;
__asm volatile
8002d3c: f04f 0350 mov.w r3, #80 ; 0x50
8002d40: f383 8811 msr BASEPRI, r3
8002d44: f3bf 8f6f isb sy
8002d48: f3bf 8f4f dsb sy
8002d4c: 60bb str r3, [r7, #8]
" msr basepri, %0 \n" \
" isb \n" \
" dsb \n" \
:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
}
8002d4e: bf00 nop
8002d50: e7fe b.n 8002d50 <xQueueGenericReset+0x28>
taskENTER_CRITICAL();
8002d52: f002 f877 bl 8004e44 <vPortEnterCritical>
{
pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8002d56: 68fb ldr r3, [r7, #12]
8002d58: 681a ldr r2, [r3, #0]
8002d5a: 68fb ldr r3, [r7, #12]
8002d5c: 6bdb ldr r3, [r3, #60] ; 0x3c
8002d5e: 68f9 ldr r1, [r7, #12]
8002d60: 6c09 ldr r1, [r1, #64] ; 0x40
8002d62: fb01 f303 mul.w r3, r1, r3
8002d66: 441a add r2, r3
8002d68: 68fb ldr r3, [r7, #12]
8002d6a: 609a str r2, [r3, #8]
pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
8002d6c: 68fb ldr r3, [r7, #12]
8002d6e: 2200 movs r2, #0
8002d70: 639a str r2, [r3, #56] ; 0x38
pxQueue->pcWriteTo = pxQueue->pcHead;
8002d72: 68fb ldr r3, [r7, #12]
8002d74: 681a ldr r2, [r3, #0]
8002d76: 68fb ldr r3, [r7, #12]
8002d78: 605a str r2, [r3, #4]
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
8002d7a: 68fb ldr r3, [r7, #12]
8002d7c: 681a ldr r2, [r3, #0]
8002d7e: 68fb ldr r3, [r7, #12]
8002d80: 6bdb ldr r3, [r3, #60] ; 0x3c
8002d82: 3b01 subs r3, #1
8002d84: 68f9 ldr r1, [r7, #12]
8002d86: 6c09 ldr r1, [r1, #64] ; 0x40
8002d88: fb01 f303 mul.w r3, r1, r3
8002d8c: 441a add r2, r3
8002d8e: 68fb ldr r3, [r7, #12]
8002d90: 60da str r2, [r3, #12]
pxQueue->cRxLock = queueUNLOCKED;
8002d92: 68fb ldr r3, [r7, #12]
8002d94: 22ff movs r2, #255 ; 0xff
8002d96: f883 2044 strb.w r2, [r3, #68] ; 0x44
pxQueue->cTxLock = queueUNLOCKED;
8002d9a: 68fb ldr r3, [r7, #12]
8002d9c: 22ff movs r2, #255 ; 0xff
8002d9e: f883 2045 strb.w r2, [r3, #69] ; 0x45
if( xNewQueue == pdFALSE )
8002da2: 683b ldr r3, [r7, #0]
8002da4: 2b00 cmp r3, #0
8002da6: d114 bne.n 8002dd2 <xQueueGenericReset+0xaa>
/* If there are tasks blocked waiting to read from the queue, then
the tasks will remain blocked as after this function exits the queue
will still be empty. If there are tasks blocked waiting to write to
the queue, then one should be unblocked as after this function exits
it will be possible to write to it. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8002da8: 68fb ldr r3, [r7, #12]
8002daa: 691b ldr r3, [r3, #16]
8002dac: 2b00 cmp r3, #0
8002dae: d01a beq.n 8002de6 <xQueueGenericReset+0xbe>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
8002db0: 68fb ldr r3, [r7, #12]
8002db2: 3310 adds r3, #16
8002db4: 4618 mov r0, r3
8002db6: f001 f929 bl 800400c <xTaskRemoveFromEventList>
8002dba: 4603 mov r3, r0
8002dbc: 2b00 cmp r3, #0
8002dbe: d012 beq.n 8002de6 <xQueueGenericReset+0xbe>
{
queueYIELD_IF_USING_PREEMPTION();
8002dc0: 4b0c ldr r3, [pc, #48] ; (8002df4 <xQueueGenericReset+0xcc>)
8002dc2: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8002dc6: 601a str r2, [r3, #0]
8002dc8: f3bf 8f4f dsb sy
8002dcc: f3bf 8f6f isb sy
8002dd0: e009 b.n 8002de6 <xQueueGenericReset+0xbe>
}
}
else
{
/* Ensure the event queues start in the correct state. */
vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
8002dd2: 68fb ldr r3, [r7, #12]
8002dd4: 3310 adds r3, #16
8002dd6: 4618 mov r0, r3
8002dd8: f7ff fef2 bl 8002bc0 <vListInitialise>
vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
8002ddc: 68fb ldr r3, [r7, #12]
8002dde: 3324 adds r3, #36 ; 0x24
8002de0: 4618 mov r0, r3
8002de2: f7ff feed bl 8002bc0 <vListInitialise>
}
}
taskEXIT_CRITICAL();
8002de6: f002 f85d bl 8004ea4 <vPortExitCritical>
/* A value is returned for calling semantic consistency with previous
versions. */
return pdPASS;
8002dea: 2301 movs r3, #1
}
8002dec: 4618 mov r0, r3
8002dee: 3710 adds r7, #16
8002df0: 46bd mov sp, r7
8002df2: bd80 pop {r7, pc}
8002df4: e000ed04 .word 0xe000ed04
08002df8 <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
{
8002df8: b580 push {r7, lr}
8002dfa: b08e sub sp, #56 ; 0x38
8002dfc: af02 add r7, sp, #8
8002dfe: 60f8 str r0, [r7, #12]
8002e00: 60b9 str r1, [r7, #8]
8002e02: 607a str r2, [r7, #4]
8002e04: 603b str r3, [r7, #0]
Queue_t *pxNewQueue;
configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
8002e06: 68fb ldr r3, [r7, #12]
8002e08: 2b00 cmp r3, #0
8002e0a: d10a bne.n 8002e22 <xQueueGenericCreateStatic+0x2a>
__asm volatile
8002e0c: f04f 0350 mov.w r3, #80 ; 0x50
8002e10: f383 8811 msr BASEPRI, r3
8002e14: f3bf 8f6f isb sy
8002e18: f3bf 8f4f dsb sy
8002e1c: 62bb str r3, [r7, #40] ; 0x28
}
8002e1e: bf00 nop
8002e20: e7fe b.n 8002e20 <xQueueGenericCreateStatic+0x28>
/* The StaticQueue_t structure and the queue storage area must be
supplied. */
configASSERT( pxStaticQueue != NULL );
8002e22: 683b ldr r3, [r7, #0]
8002e24: 2b00 cmp r3, #0
8002e26: d10a bne.n 8002e3e <xQueueGenericCreateStatic+0x46>
__asm volatile
8002e28: f04f 0350 mov.w r3, #80 ; 0x50
8002e2c: f383 8811 msr BASEPRI, r3
8002e30: f3bf 8f6f isb sy
8002e34: f3bf 8f4f dsb sy
8002e38: 627b str r3, [r7, #36] ; 0x24
}
8002e3a: bf00 nop
8002e3c: e7fe b.n 8002e3c <xQueueGenericCreateStatic+0x44>
/* A queue storage area should be provided if the item size is not 0, and
should not be provided if the item size is 0. */
configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
8002e3e: 687b ldr r3, [r7, #4]
8002e40: 2b00 cmp r3, #0
8002e42: d002 beq.n 8002e4a <xQueueGenericCreateStatic+0x52>
8002e44: 68bb ldr r3, [r7, #8]
8002e46: 2b00 cmp r3, #0
8002e48: d001 beq.n 8002e4e <xQueueGenericCreateStatic+0x56>
8002e4a: 2301 movs r3, #1
8002e4c: e000 b.n 8002e50 <xQueueGenericCreateStatic+0x58>
8002e4e: 2300 movs r3, #0
8002e50: 2b00 cmp r3, #0
8002e52: d10a bne.n 8002e6a <xQueueGenericCreateStatic+0x72>
__asm volatile
8002e54: f04f 0350 mov.w r3, #80 ; 0x50
8002e58: f383 8811 msr BASEPRI, r3
8002e5c: f3bf 8f6f isb sy
8002e60: f3bf 8f4f dsb sy
8002e64: 623b str r3, [r7, #32]
}
8002e66: bf00 nop
8002e68: e7fe b.n 8002e68 <xQueueGenericCreateStatic+0x70>
configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
8002e6a: 687b ldr r3, [r7, #4]
8002e6c: 2b00 cmp r3, #0
8002e6e: d102 bne.n 8002e76 <xQueueGenericCreateStatic+0x7e>
8002e70: 68bb ldr r3, [r7, #8]
8002e72: 2b00 cmp r3, #0
8002e74: d101 bne.n 8002e7a <xQueueGenericCreateStatic+0x82>
8002e76: 2301 movs r3, #1
8002e78: e000 b.n 8002e7c <xQueueGenericCreateStatic+0x84>
8002e7a: 2300 movs r3, #0
8002e7c: 2b00 cmp r3, #0
8002e7e: d10a bne.n 8002e96 <xQueueGenericCreateStatic+0x9e>
__asm volatile
8002e80: f04f 0350 mov.w r3, #80 ; 0x50
8002e84: f383 8811 msr BASEPRI, r3
8002e88: f3bf 8f6f isb sy
8002e8c: f3bf 8f4f dsb sy
8002e90: 61fb str r3, [r7, #28]
}
8002e92: bf00 nop
8002e94: e7fe b.n 8002e94 <xQueueGenericCreateStatic+0x9c>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticQueue_t or StaticSemaphore_t equals the size of
the real queue and semaphore structures. */
volatile size_t xSize = sizeof( StaticQueue_t );
8002e96: 2350 movs r3, #80 ; 0x50
8002e98: 617b str r3, [r7, #20]
configASSERT( xSize == sizeof( Queue_t ) );
8002e9a: 697b ldr r3, [r7, #20]
8002e9c: 2b50 cmp r3, #80 ; 0x50
8002e9e: d00a beq.n 8002eb6 <xQueueGenericCreateStatic+0xbe>
__asm volatile
8002ea0: f04f 0350 mov.w r3, #80 ; 0x50
8002ea4: f383 8811 msr BASEPRI, r3
8002ea8: f3bf 8f6f isb sy
8002eac: f3bf 8f4f dsb sy
8002eb0: 61bb str r3, [r7, #24]
}
8002eb2: bf00 nop
8002eb4: e7fe b.n 8002eb4 <xQueueGenericCreateStatic+0xbc>
( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
8002eb6: 697b ldr r3, [r7, #20]
#endif /* configASSERT_DEFINED */
/* The address of a statically allocated queue was passed in, use it.
The address of a statically allocated storage area was also passed in
but is already set. */
pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
8002eb8: 683b ldr r3, [r7, #0]
8002eba: 62fb str r3, [r7, #44] ; 0x2c
if( pxNewQueue != NULL )
8002ebc: 6afb ldr r3, [r7, #44] ; 0x2c
8002ebe: 2b00 cmp r3, #0
8002ec0: d00d beq.n 8002ede <xQueueGenericCreateStatic+0xe6>
#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* Queues can be allocated wither statically or dynamically, so
note this queue was allocated statically in case the queue is
later deleted. */
pxNewQueue->ucStaticallyAllocated = pdTRUE;
8002ec2: 6afb ldr r3, [r7, #44] ; 0x2c
8002ec4: 2201 movs r2, #1
8002ec6: f883 2046 strb.w r2, [r3, #70] ; 0x46
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
8002eca: f897 2038 ldrb.w r2, [r7, #56] ; 0x38
8002ece: 6afb ldr r3, [r7, #44] ; 0x2c
8002ed0: 9300 str r3, [sp, #0]
8002ed2: 4613 mov r3, r2
8002ed4: 687a ldr r2, [r7, #4]
8002ed6: 68b9 ldr r1, [r7, #8]
8002ed8: 68f8 ldr r0, [r7, #12]
8002eda: f000 f805 bl 8002ee8 <prvInitialiseNewQueue>
{
traceQUEUE_CREATE_FAILED( ucQueueType );
mtCOVERAGE_TEST_MARKER();
}
return pxNewQueue;
8002ede: 6afb ldr r3, [r7, #44] ; 0x2c
}
8002ee0: 4618 mov r0, r3
8002ee2: 3730 adds r7, #48 ; 0x30
8002ee4: 46bd mov sp, r7
8002ee6: bd80 pop {r7, pc}
08002ee8 <prvInitialiseNewQueue>:
#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/
static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
8002ee8: b580 push {r7, lr}
8002eea: b084 sub sp, #16
8002eec: af00 add r7, sp, #0
8002eee: 60f8 str r0, [r7, #12]
8002ef0: 60b9 str r1, [r7, #8]
8002ef2: 607a str r2, [r7, #4]
8002ef4: 70fb strb r3, [r7, #3]
/* Remove compiler warnings about unused parameters should
configUSE_TRACE_FACILITY not be set to 1. */
( void ) ucQueueType;
if( uxItemSize == ( UBaseType_t ) 0 )
8002ef6: 68bb ldr r3, [r7, #8]
8002ef8: 2b00 cmp r3, #0
8002efa: d103 bne.n 8002f04 <prvInitialiseNewQueue+0x1c>
{
/* No RAM was allocated for the queue storage area, but PC head cannot
be set to NULL because NULL is used as a key to say the queue is used as
a mutex. Therefore just set pcHead to point to the queue as a benign
value that is known to be within the memory map. */
pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
8002efc: 69bb ldr r3, [r7, #24]
8002efe: 69ba ldr r2, [r7, #24]
8002f00: 601a str r2, [r3, #0]
8002f02: e002 b.n 8002f0a <prvInitialiseNewQueue+0x22>
}
else
{
/* Set the head to the start of the queue storage area. */
pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
8002f04: 69bb ldr r3, [r7, #24]
8002f06: 687a ldr r2, [r7, #4]
8002f08: 601a str r2, [r3, #0]
}
/* Initialise the queue members as described where the queue type is
defined. */
pxNewQueue->uxLength = uxQueueLength;
8002f0a: 69bb ldr r3, [r7, #24]
8002f0c: 68fa ldr r2, [r7, #12]
8002f0e: 63da str r2, [r3, #60] ; 0x3c
pxNewQueue->uxItemSize = uxItemSize;
8002f10: 69bb ldr r3, [r7, #24]
8002f12: 68ba ldr r2, [r7, #8]
8002f14: 641a str r2, [r3, #64] ; 0x40
( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
8002f16: 2101 movs r1, #1
8002f18: 69b8 ldr r0, [r7, #24]
8002f1a: f7ff ff05 bl 8002d28 <xQueueGenericReset>
#if ( configUSE_TRACE_FACILITY == 1 )
{
pxNewQueue->ucQueueType = ucQueueType;
8002f1e: 69bb ldr r3, [r7, #24]
8002f20: 78fa ldrb r2, [r7, #3]
8002f22: f883 204c strb.w r2, [r3, #76] ; 0x4c
pxNewQueue->pxQueueSetContainer = NULL;
}
#endif /* configUSE_QUEUE_SETS */
traceQUEUE_CREATE( pxNewQueue );
}
8002f26: bf00 nop
8002f28: 3710 adds r7, #16
8002f2a: 46bd mov sp, r7
8002f2c: bd80 pop {r7, pc}
...
08002f30 <xQueueGenericSend>:
#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
8002f30: b580 push {r7, lr}
8002f32: b08e sub sp, #56 ; 0x38
8002f34: af00 add r7, sp, #0
8002f36: 60f8 str r0, [r7, #12]
8002f38: 60b9 str r1, [r7, #8]
8002f3a: 607a str r2, [r7, #4]
8002f3c: 603b str r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
8002f3e: 2300 movs r3, #0
8002f40: 637b str r3, [r7, #52] ; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8002f42: 68fb ldr r3, [r7, #12]
8002f44: 633b str r3, [r7, #48] ; 0x30
configASSERT( pxQueue );
8002f46: 6b3b ldr r3, [r7, #48] ; 0x30
8002f48: 2b00 cmp r3, #0
8002f4a: d10a bne.n 8002f62 <xQueueGenericSend+0x32>
__asm volatile
8002f4c: f04f 0350 mov.w r3, #80 ; 0x50
8002f50: f383 8811 msr BASEPRI, r3
8002f54: f3bf 8f6f isb sy
8002f58: f3bf 8f4f dsb sy
8002f5c: 62bb str r3, [r7, #40] ; 0x28
}
8002f5e: bf00 nop
8002f60: e7fe b.n 8002f60 <xQueueGenericSend+0x30>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
8002f62: 68bb ldr r3, [r7, #8]
8002f64: 2b00 cmp r3, #0
8002f66: d103 bne.n 8002f70 <xQueueGenericSend+0x40>
8002f68: 6b3b ldr r3, [r7, #48] ; 0x30
8002f6a: 6c1b ldr r3, [r3, #64] ; 0x40
8002f6c: 2b00 cmp r3, #0
8002f6e: d101 bne.n 8002f74 <xQueueGenericSend+0x44>
8002f70: 2301 movs r3, #1
8002f72: e000 b.n 8002f76 <xQueueGenericSend+0x46>
8002f74: 2300 movs r3, #0
8002f76: 2b00 cmp r3, #0
8002f78: d10a bne.n 8002f90 <xQueueGenericSend+0x60>
__asm volatile
8002f7a: f04f 0350 mov.w r3, #80 ; 0x50
8002f7e: f383 8811 msr BASEPRI, r3
8002f82: f3bf 8f6f isb sy
8002f86: f3bf 8f4f dsb sy
8002f8a: 627b str r3, [r7, #36] ; 0x24
}
8002f8c: bf00 nop
8002f8e: e7fe b.n 8002f8e <xQueueGenericSend+0x5e>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
8002f90: 683b ldr r3, [r7, #0]
8002f92: 2b02 cmp r3, #2
8002f94: d103 bne.n 8002f9e <xQueueGenericSend+0x6e>
8002f96: 6b3b ldr r3, [r7, #48] ; 0x30
8002f98: 6bdb ldr r3, [r3, #60] ; 0x3c
8002f9a: 2b01 cmp r3, #1
8002f9c: d101 bne.n 8002fa2 <xQueueGenericSend+0x72>
8002f9e: 2301 movs r3, #1
8002fa0: e000 b.n 8002fa4 <xQueueGenericSend+0x74>
8002fa2: 2300 movs r3, #0
8002fa4: 2b00 cmp r3, #0
8002fa6: d10a bne.n 8002fbe <xQueueGenericSend+0x8e>
__asm volatile
8002fa8: f04f 0350 mov.w r3, #80 ; 0x50
8002fac: f383 8811 msr BASEPRI, r3
8002fb0: f3bf 8f6f isb sy
8002fb4: f3bf 8f4f dsb sy
8002fb8: 623b str r3, [r7, #32]
}
8002fba: bf00 nop
8002fbc: e7fe b.n 8002fbc <xQueueGenericSend+0x8c>
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
8002fbe: f001 f9e7 bl 8004390 <xTaskGetSchedulerState>
8002fc2: 4603 mov r3, r0
8002fc4: 2b00 cmp r3, #0
8002fc6: d102 bne.n 8002fce <xQueueGenericSend+0x9e>
8002fc8: 687b ldr r3, [r7, #4]
8002fca: 2b00 cmp r3, #0
8002fcc: d101 bne.n 8002fd2 <xQueueGenericSend+0xa2>
8002fce: 2301 movs r3, #1
8002fd0: e000 b.n 8002fd4 <xQueueGenericSend+0xa4>
8002fd2: 2300 movs r3, #0
8002fd4: 2b00 cmp r3, #0
8002fd6: d10a bne.n 8002fee <xQueueGenericSend+0xbe>
__asm volatile
8002fd8: f04f 0350 mov.w r3, #80 ; 0x50
8002fdc: f383 8811 msr BASEPRI, r3
8002fe0: f3bf 8f6f isb sy
8002fe4: f3bf 8f4f dsb sy
8002fe8: 61fb str r3, [r7, #28]
}
8002fea: bf00 nop
8002fec: e7fe b.n 8002fec <xQueueGenericSend+0xbc>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
8002fee: f001 ff29 bl 8004e44 <vPortEnterCritical>
{
/* Is there room on the queue now? The running task must be the
highest priority task wanting to access the queue. If the head item
in the queue is to be overwritten then it does not matter if the
queue is full. */
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
8002ff2: 6b3b ldr r3, [r7, #48] ; 0x30
8002ff4: 6b9a ldr r2, [r3, #56] ; 0x38
8002ff6: 6b3b ldr r3, [r7, #48] ; 0x30
8002ff8: 6bdb ldr r3, [r3, #60] ; 0x3c
8002ffa: 429a cmp r2, r3
8002ffc: d302 bcc.n 8003004 <xQueueGenericSend+0xd4>
8002ffe: 683b ldr r3, [r7, #0]
8003000: 2b02 cmp r3, #2
8003002: d129 bne.n 8003058 <xQueueGenericSend+0x128>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
8003004: 683a ldr r2, [r7, #0]
8003006: 68b9 ldr r1, [r7, #8]
8003008: 6b38 ldr r0, [r7, #48] ; 0x30
800300a: f000 fa0b bl 8003424 <prvCopyDataToQueue>
800300e: 62f8 str r0, [r7, #44] ; 0x2c
/* If there was a task waiting for data to arrive on the
queue then unblock it now. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
8003010: 6b3b ldr r3, [r7, #48] ; 0x30
8003012: 6a5b ldr r3, [r3, #36] ; 0x24
8003014: 2b00 cmp r3, #0
8003016: d010 beq.n 800303a <xQueueGenericSend+0x10a>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8003018: 6b3b ldr r3, [r7, #48] ; 0x30
800301a: 3324 adds r3, #36 ; 0x24
800301c: 4618 mov r0, r3
800301e: f000 fff5 bl 800400c <xTaskRemoveFromEventList>
8003022: 4603 mov r3, r0
8003024: 2b00 cmp r3, #0
8003026: d013 beq.n 8003050 <xQueueGenericSend+0x120>
{
/* The unblocked task has a priority higher than
our own so yield immediately. Yes it is ok to do
this from within the critical section - the kernel
takes care of that. */
queueYIELD_IF_USING_PREEMPTION();
8003028: 4b3f ldr r3, [pc, #252] ; (8003128 <xQueueGenericSend+0x1f8>)
800302a: f04f 5280 mov.w r2, #268435456 ; 0x10000000
800302e: 601a str r2, [r3, #0]
8003030: f3bf 8f4f dsb sy
8003034: f3bf 8f6f isb sy
8003038: e00a b.n 8003050 <xQueueGenericSend+0x120>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
else if( xYieldRequired != pdFALSE )
800303a: 6afb ldr r3, [r7, #44] ; 0x2c
800303c: 2b00 cmp r3, #0
800303e: d007 beq.n 8003050 <xQueueGenericSend+0x120>
{
/* This path is a special case that will only get
executed if the task was holding multiple mutexes and
the mutexes were given back in an order that is
different to that in which they were taken. */
queueYIELD_IF_USING_PREEMPTION();
8003040: 4b39 ldr r3, [pc, #228] ; (8003128 <xQueueGenericSend+0x1f8>)
8003042: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003046: 601a str r2, [r3, #0]
8003048: f3bf 8f4f dsb sy
800304c: f3bf 8f6f isb sy
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_QUEUE_SETS */
taskEXIT_CRITICAL();
8003050: f001 ff28 bl 8004ea4 <vPortExitCritical>
return pdPASS;
8003054: 2301 movs r3, #1
8003056: e063 b.n 8003120 <xQueueGenericSend+0x1f0>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
8003058: 687b ldr r3, [r7, #4]
800305a: 2b00 cmp r3, #0
800305c: d103 bne.n 8003066 <xQueueGenericSend+0x136>
{
/* The queue was full and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
800305e: f001 ff21 bl 8004ea4 <vPortExitCritical>
/* Return to the original privilege level before exiting
the function. */
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
8003062: 2300 movs r3, #0
8003064: e05c b.n 8003120 <xQueueGenericSend+0x1f0>
}
else if( xEntryTimeSet == pdFALSE )
8003066: 6b7b ldr r3, [r7, #52] ; 0x34
8003068: 2b00 cmp r3, #0
800306a: d106 bne.n 800307a <xQueueGenericSend+0x14a>
{
/* The queue was full and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
800306c: f107 0314 add.w r3, r7, #20
8003070: 4618 mov r0, r3
8003072: f001 f82f bl 80040d4 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
8003076: 2301 movs r3, #1
8003078: 637b str r3, [r7, #52] ; 0x34
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
800307a: f001 ff13 bl 8004ea4 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
800307e: f000 fd9b bl 8003bb8 <vTaskSuspendAll>
prvLockQueue( pxQueue );
8003082: f001 fedf bl 8004e44 <vPortEnterCritical>
8003086: 6b3b ldr r3, [r7, #48] ; 0x30
8003088: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
800308c: b25b sxtb r3, r3
800308e: f1b3 3fff cmp.w r3, #4294967295
8003092: d103 bne.n 800309c <xQueueGenericSend+0x16c>
8003094: 6b3b ldr r3, [r7, #48] ; 0x30
8003096: 2200 movs r2, #0
8003098: f883 2044 strb.w r2, [r3, #68] ; 0x44
800309c: 6b3b ldr r3, [r7, #48] ; 0x30
800309e: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80030a2: b25b sxtb r3, r3
80030a4: f1b3 3fff cmp.w r3, #4294967295
80030a8: d103 bne.n 80030b2 <xQueueGenericSend+0x182>
80030aa: 6b3b ldr r3, [r7, #48] ; 0x30
80030ac: 2200 movs r2, #0
80030ae: f883 2045 strb.w r2, [r3, #69] ; 0x45
80030b2: f001 fef7 bl 8004ea4 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
80030b6: 1d3a adds r2, r7, #4
80030b8: f107 0314 add.w r3, r7, #20
80030bc: 4611 mov r1, r2
80030be: 4618 mov r0, r3
80030c0: f001 f81e bl 8004100 <xTaskCheckForTimeOut>
80030c4: 4603 mov r3, r0
80030c6: 2b00 cmp r3, #0
80030c8: d124 bne.n 8003114 <xQueueGenericSend+0x1e4>
{
if( prvIsQueueFull( pxQueue ) != pdFALSE )
80030ca: 6b38 ldr r0, [r7, #48] ; 0x30
80030cc: f000 faa2 bl 8003614 <prvIsQueueFull>
80030d0: 4603 mov r3, r0
80030d2: 2b00 cmp r3, #0
80030d4: d018 beq.n 8003108 <xQueueGenericSend+0x1d8>
{
traceBLOCKING_ON_QUEUE_SEND( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
80030d6: 6b3b ldr r3, [r7, #48] ; 0x30
80030d8: 3310 adds r3, #16
80030da: 687a ldr r2, [r7, #4]
80030dc: 4611 mov r1, r2
80030de: 4618 mov r0, r3
80030e0: f000 ff44 bl 8003f6c <vTaskPlaceOnEventList>
/* Unlocking the queue means queue events can effect the
event list. It is possible that interrupts occurring now
remove this task from the event list again - but as the
scheduler is suspended the task will go onto the pending
ready last instead of the actual ready list. */
prvUnlockQueue( pxQueue );
80030e4: 6b38 ldr r0, [r7, #48] ; 0x30
80030e6: f000 fa2d bl 8003544 <prvUnlockQueue>
/* Resuming the scheduler will move tasks from the pending
ready list into the ready list - so it is feasible that this
task is already in a ready list before it yields - in which
case the yield will not cause a context switch unless there
is also a higher priority task in the pending ready list. */
if( xTaskResumeAll() == pdFALSE )
80030ea: f000 fd73 bl 8003bd4 <xTaskResumeAll>
80030ee: 4603 mov r3, r0
80030f0: 2b00 cmp r3, #0
80030f2: f47f af7c bne.w 8002fee <xQueueGenericSend+0xbe>
{
portYIELD_WITHIN_API();
80030f6: 4b0c ldr r3, [pc, #48] ; (8003128 <xQueueGenericSend+0x1f8>)
80030f8: f04f 5280 mov.w r2, #268435456 ; 0x10000000
80030fc: 601a str r2, [r3, #0]
80030fe: f3bf 8f4f dsb sy
8003102: f3bf 8f6f isb sy
8003106: e772 b.n 8002fee <xQueueGenericSend+0xbe>
}
}
else
{
/* Try again. */
prvUnlockQueue( pxQueue );
8003108: 6b38 ldr r0, [r7, #48] ; 0x30
800310a: f000 fa1b bl 8003544 <prvUnlockQueue>
( void ) xTaskResumeAll();
800310e: f000 fd61 bl 8003bd4 <xTaskResumeAll>
8003112: e76c b.n 8002fee <xQueueGenericSend+0xbe>
}
}
else
{
/* The timeout has expired. */
prvUnlockQueue( pxQueue );
8003114: 6b38 ldr r0, [r7, #48] ; 0x30
8003116: f000 fa15 bl 8003544 <prvUnlockQueue>
( void ) xTaskResumeAll();
800311a: f000 fd5b bl 8003bd4 <xTaskResumeAll>
traceQUEUE_SEND_FAILED( pxQueue );
return errQUEUE_FULL;
800311e: 2300 movs r3, #0
}
} /*lint -restore */
}
8003120: 4618 mov r0, r3
8003122: 3738 adds r7, #56 ; 0x38
8003124: 46bd mov sp, r7
8003126: bd80 pop {r7, pc}
8003128: e000ed04 .word 0xe000ed04
0800312c <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/
BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
800312c: b580 push {r7, lr}
800312e: b090 sub sp, #64 ; 0x40
8003130: af00 add r7, sp, #0
8003132: 60f8 str r0, [r7, #12]
8003134: 60b9 str r1, [r7, #8]
8003136: 607a str r2, [r7, #4]
8003138: 603b str r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
800313a: 68fb ldr r3, [r7, #12]
800313c: 63bb str r3, [r7, #56] ; 0x38
configASSERT( pxQueue );
800313e: 6bbb ldr r3, [r7, #56] ; 0x38
8003140: 2b00 cmp r3, #0
8003142: d10a bne.n 800315a <xQueueGenericSendFromISR+0x2e>
__asm volatile
8003144: f04f 0350 mov.w r3, #80 ; 0x50
8003148: f383 8811 msr BASEPRI, r3
800314c: f3bf 8f6f isb sy
8003150: f3bf 8f4f dsb sy
8003154: 62bb str r3, [r7, #40] ; 0x28
}
8003156: bf00 nop
8003158: e7fe b.n 8003158 <xQueueGenericSendFromISR+0x2c>
configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
800315a: 68bb ldr r3, [r7, #8]
800315c: 2b00 cmp r3, #0
800315e: d103 bne.n 8003168 <xQueueGenericSendFromISR+0x3c>
8003160: 6bbb ldr r3, [r7, #56] ; 0x38
8003162: 6c1b ldr r3, [r3, #64] ; 0x40
8003164: 2b00 cmp r3, #0
8003166: d101 bne.n 800316c <xQueueGenericSendFromISR+0x40>
8003168: 2301 movs r3, #1
800316a: e000 b.n 800316e <xQueueGenericSendFromISR+0x42>
800316c: 2300 movs r3, #0
800316e: 2b00 cmp r3, #0
8003170: d10a bne.n 8003188 <xQueueGenericSendFromISR+0x5c>
__asm volatile
8003172: f04f 0350 mov.w r3, #80 ; 0x50
8003176: f383 8811 msr BASEPRI, r3
800317a: f3bf 8f6f isb sy
800317e: f3bf 8f4f dsb sy
8003182: 627b str r3, [r7, #36] ; 0x24
}
8003184: bf00 nop
8003186: e7fe b.n 8003186 <xQueueGenericSendFromISR+0x5a>
configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
8003188: 683b ldr r3, [r7, #0]
800318a: 2b02 cmp r3, #2
800318c: d103 bne.n 8003196 <xQueueGenericSendFromISR+0x6a>
800318e: 6bbb ldr r3, [r7, #56] ; 0x38
8003190: 6bdb ldr r3, [r3, #60] ; 0x3c
8003192: 2b01 cmp r3, #1
8003194: d101 bne.n 800319a <xQueueGenericSendFromISR+0x6e>
8003196: 2301 movs r3, #1
8003198: e000 b.n 800319c <xQueueGenericSendFromISR+0x70>
800319a: 2300 movs r3, #0
800319c: 2b00 cmp r3, #0
800319e: d10a bne.n 80031b6 <xQueueGenericSendFromISR+0x8a>
__asm volatile
80031a0: f04f 0350 mov.w r3, #80 ; 0x50
80031a4: f383 8811 msr BASEPRI, r3
80031a8: f3bf 8f6f isb sy
80031ac: f3bf 8f4f dsb sy
80031b0: 623b str r3, [r7, #32]
}
80031b2: bf00 nop
80031b4: e7fe b.n 80031b4 <xQueueGenericSendFromISR+0x88>
that have been assigned a priority at or (logically) below the maximum
system call interrupt priority. FreeRTOS maintains a separate interrupt
safe API to ensure interrupt entry is as fast and as simple as possible.
More information (albeit Cortex-M specific) is provided on the following
link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
80031b6: f001 ff27 bl 8005008 <vPortValidateInterruptPriority>
portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
__asm volatile
80031ba: f3ef 8211 mrs r2, BASEPRI
80031be: f04f 0350 mov.w r3, #80 ; 0x50
80031c2: f383 8811 msr BASEPRI, r3
80031c6: f3bf 8f6f isb sy
80031ca: f3bf 8f4f dsb sy
80031ce: 61fa str r2, [r7, #28]
80031d0: 61bb str r3, [r7, #24]
:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
);
/* This return will not be reached but is necessary to prevent compiler
warnings. */
return ulOriginalBASEPRI;
80031d2: 69fb ldr r3, [r7, #28]
/* Similar to xQueueGenericSend, except without blocking if there is no room
in the queue. Also don't directly wake a task that was blocked on a queue
read, instead return a flag to say whether a context switch is required or
not (i.e. has a task with a higher priority than us been woken by this
post). */
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
80031d4: 637b str r3, [r7, #52] ; 0x34
{
if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
80031d6: 6bbb ldr r3, [r7, #56] ; 0x38
80031d8: 6b9a ldr r2, [r3, #56] ; 0x38
80031da: 6bbb ldr r3, [r7, #56] ; 0x38
80031dc: 6bdb ldr r3, [r3, #60] ; 0x3c
80031de: 429a cmp r2, r3
80031e0: d302 bcc.n 80031e8 <xQueueGenericSendFromISR+0xbc>
80031e2: 683b ldr r3, [r7, #0]
80031e4: 2b02 cmp r3, #2
80031e6: d12f bne.n 8003248 <xQueueGenericSendFromISR+0x11c>
{
const int8_t cTxLock = pxQueue->cTxLock;
80031e8: 6bbb ldr r3, [r7, #56] ; 0x38
80031ea: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80031ee: f887 3033 strb.w r3, [r7, #51] ; 0x33
const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
80031f2: 6bbb ldr r3, [r7, #56] ; 0x38
80031f4: 6b9b ldr r3, [r3, #56] ; 0x38
80031f6: 62fb str r3, [r7, #44] ; 0x2c
/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
semaphore or mutex. That means prvCopyDataToQueue() cannot result
in a task disinheriting a priority and prvCopyDataToQueue() can be
called here even though the disinherit function does not check if
the scheduler is suspended before accessing the ready lists. */
( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
80031f8: 683a ldr r2, [r7, #0]
80031fa: 68b9 ldr r1, [r7, #8]
80031fc: 6bb8 ldr r0, [r7, #56] ; 0x38
80031fe: f000 f911 bl 8003424 <prvCopyDataToQueue>
/* The event list is not altered if the queue is locked. This will
be done when the queue is unlocked later. */
if( cTxLock == queueUNLOCKED )
8003202: f997 3033 ldrsb.w r3, [r7, #51] ; 0x33
8003206: f1b3 3fff cmp.w r3, #4294967295
800320a: d112 bne.n 8003232 <xQueueGenericSendFromISR+0x106>
}
}
}
#else /* configUSE_QUEUE_SETS */
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800320c: 6bbb ldr r3, [r7, #56] ; 0x38
800320e: 6a5b ldr r3, [r3, #36] ; 0x24
8003210: 2b00 cmp r3, #0
8003212: d016 beq.n 8003242 <xQueueGenericSendFromISR+0x116>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8003214: 6bbb ldr r3, [r7, #56] ; 0x38
8003216: 3324 adds r3, #36 ; 0x24
8003218: 4618 mov r0, r3
800321a: f000 fef7 bl 800400c <xTaskRemoveFromEventList>
800321e: 4603 mov r3, r0
8003220: 2b00 cmp r3, #0
8003222: d00e beq.n 8003242 <xQueueGenericSendFromISR+0x116>
{
/* The task waiting has a higher priority so record that a
context switch is required. */
if( pxHigherPriorityTaskWoken != NULL )
8003224: 687b ldr r3, [r7, #4]
8003226: 2b00 cmp r3, #0
8003228: d00b beq.n 8003242 <xQueueGenericSendFromISR+0x116>
{
*pxHigherPriorityTaskWoken = pdTRUE;
800322a: 687b ldr r3, [r7, #4]
800322c: 2201 movs r2, #1
800322e: 601a str r2, [r3, #0]
8003230: e007 b.n 8003242 <xQueueGenericSendFromISR+0x116>
}
else
{
/* Increment the lock count so the task that unlocks the queue
knows that data was posted while it was locked. */
pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
8003232: f897 3033 ldrb.w r3, [r7, #51] ; 0x33
8003236: 3301 adds r3, #1
8003238: b2db uxtb r3, r3
800323a: b25a sxtb r2, r3
800323c: 6bbb ldr r3, [r7, #56] ; 0x38
800323e: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
xReturn = pdPASS;
8003242: 2301 movs r3, #1
8003244: 63fb str r3, [r7, #60] ; 0x3c
{
8003246: e001 b.n 800324c <xQueueGenericSendFromISR+0x120>
}
else
{
traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
xReturn = errQUEUE_FULL;
8003248: 2300 movs r3, #0
800324a: 63fb str r3, [r7, #60] ; 0x3c
800324c: 6b7b ldr r3, [r7, #52] ; 0x34
800324e: 617b str r3, [r7, #20]
}
/*-----------------------------------------------------------*/
portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
__asm volatile
8003250: 697b ldr r3, [r7, #20]
8003252: f383 8811 msr BASEPRI, r3
(
" msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory"
);
}
8003256: bf00 nop
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
return xReturn;
8003258: 6bfb ldr r3, [r7, #60] ; 0x3c
}
800325a: 4618 mov r0, r3
800325c: 3740 adds r7, #64 ; 0x40
800325e: 46bd mov sp, r7
8003260: bd80 pop {r7, pc}
...
08003264 <xQueueReceive>:
return xReturn;
}
/*-----------------------------------------------------------*/
BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
8003264: b580 push {r7, lr}
8003266: b08c sub sp, #48 ; 0x30
8003268: af00 add r7, sp, #0
800326a: 60f8 str r0, [r7, #12]
800326c: 60b9 str r1, [r7, #8]
800326e: 607a str r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
8003270: 2300 movs r3, #0
8003272: 62fb str r3, [r7, #44] ; 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
8003274: 68fb ldr r3, [r7, #12]
8003276: 62bb str r3, [r7, #40] ; 0x28
/* Check the pointer is not NULL. */
configASSERT( ( pxQueue ) );
8003278: 6abb ldr r3, [r7, #40] ; 0x28
800327a: 2b00 cmp r3, #0
800327c: d10a bne.n 8003294 <xQueueReceive+0x30>
__asm volatile
800327e: f04f 0350 mov.w r3, #80 ; 0x50
8003282: f383 8811 msr BASEPRI, r3
8003286: f3bf 8f6f isb sy
800328a: f3bf 8f4f dsb sy
800328e: 623b str r3, [r7, #32]
}
8003290: bf00 nop
8003292: e7fe b.n 8003292 <xQueueReceive+0x2e>
/* The buffer into which data is received can only be NULL if the data size
is zero (so no data is copied into the buffer. */
configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
8003294: 68bb ldr r3, [r7, #8]
8003296: 2b00 cmp r3, #0
8003298: d103 bne.n 80032a2 <xQueueReceive+0x3e>
800329a: 6abb ldr r3, [r7, #40] ; 0x28
800329c: 6c1b ldr r3, [r3, #64] ; 0x40
800329e: 2b00 cmp r3, #0
80032a0: d101 bne.n 80032a6 <xQueueReceive+0x42>
80032a2: 2301 movs r3, #1
80032a4: e000 b.n 80032a8 <xQueueReceive+0x44>
80032a6: 2300 movs r3, #0
80032a8: 2b00 cmp r3, #0
80032aa: d10a bne.n 80032c2 <xQueueReceive+0x5e>
__asm volatile
80032ac: f04f 0350 mov.w r3, #80 ; 0x50
80032b0: f383 8811 msr BASEPRI, r3
80032b4: f3bf 8f6f isb sy
80032b8: f3bf 8f4f dsb sy
80032bc: 61fb str r3, [r7, #28]
}
80032be: bf00 nop
80032c0: e7fe b.n 80032c0 <xQueueReceive+0x5c>
/* Cannot block if the scheduler is suspended. */
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
{
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
80032c2: f001 f865 bl 8004390 <xTaskGetSchedulerState>
80032c6: 4603 mov r3, r0
80032c8: 2b00 cmp r3, #0
80032ca: d102 bne.n 80032d2 <xQueueReceive+0x6e>
80032cc: 687b ldr r3, [r7, #4]
80032ce: 2b00 cmp r3, #0
80032d0: d101 bne.n 80032d6 <xQueueReceive+0x72>
80032d2: 2301 movs r3, #1
80032d4: e000 b.n 80032d8 <xQueueReceive+0x74>
80032d6: 2300 movs r3, #0
80032d8: 2b00 cmp r3, #0
80032da: d10a bne.n 80032f2 <xQueueReceive+0x8e>
__asm volatile
80032dc: f04f 0350 mov.w r3, #80 ; 0x50
80032e0: f383 8811 msr BASEPRI, r3
80032e4: f3bf 8f6f isb sy
80032e8: f3bf 8f4f dsb sy
80032ec: 61bb str r3, [r7, #24]
}
80032ee: bf00 nop
80032f0: e7fe b.n 80032f0 <xQueueReceive+0x8c>
/*lint -save -e904 This function relaxes the coding standard somewhat to
allow return statements within the function itself. This is done in the
interest of execution time efficiency. */
for( ;; )
{
taskENTER_CRITICAL();
80032f2: f001 fda7 bl 8004e44 <vPortEnterCritical>
{
const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
80032f6: 6abb ldr r3, [r7, #40] ; 0x28
80032f8: 6b9b ldr r3, [r3, #56] ; 0x38
80032fa: 627b str r3, [r7, #36] ; 0x24
/* Is there data in the queue now? To be running the calling task
must be the highest priority task wanting to access the queue. */
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
80032fc: 6a7b ldr r3, [r7, #36] ; 0x24
80032fe: 2b00 cmp r3, #0
8003300: d01f beq.n 8003342 <xQueueReceive+0xde>
{
/* Data available, remove one item. */
prvCopyDataFromQueue( pxQueue, pvBuffer );
8003302: 68b9 ldr r1, [r7, #8]
8003304: 6ab8 ldr r0, [r7, #40] ; 0x28
8003306: f000 f8f7 bl 80034f8 <prvCopyDataFromQueue>
traceQUEUE_RECEIVE( pxQueue );
pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
800330a: 6a7b ldr r3, [r7, #36] ; 0x24
800330c: 1e5a subs r2, r3, #1
800330e: 6abb ldr r3, [r7, #40] ; 0x28
8003310: 639a str r2, [r3, #56] ; 0x38
/* There is now space in the queue, were any tasks waiting to
post to the queue? If so, unblock the highest priority waiting
task. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
8003312: 6abb ldr r3, [r7, #40] ; 0x28
8003314: 691b ldr r3, [r3, #16]
8003316: 2b00 cmp r3, #0
8003318: d00f beq.n 800333a <xQueueReceive+0xd6>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
800331a: 6abb ldr r3, [r7, #40] ; 0x28
800331c: 3310 adds r3, #16
800331e: 4618 mov r0, r3
8003320: f000 fe74 bl 800400c <xTaskRemoveFromEventList>
8003324: 4603 mov r3, r0
8003326: 2b00 cmp r3, #0
8003328: d007 beq.n 800333a <xQueueReceive+0xd6>
{
queueYIELD_IF_USING_PREEMPTION();
800332a: 4b3d ldr r3, [pc, #244] ; (8003420 <xQueueReceive+0x1bc>)
800332c: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003330: 601a str r2, [r3, #0]
8003332: f3bf 8f4f dsb sy
8003336: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
taskEXIT_CRITICAL();
800333a: f001 fdb3 bl 8004ea4 <vPortExitCritical>
return pdPASS;
800333e: 2301 movs r3, #1
8003340: e069 b.n 8003416 <xQueueReceive+0x1b2>
}
else
{
if( xTicksToWait == ( TickType_t ) 0 )
8003342: 687b ldr r3, [r7, #4]
8003344: 2b00 cmp r3, #0
8003346: d103 bne.n 8003350 <xQueueReceive+0xec>
{
/* The queue was empty and no block time is specified (or
the block time has expired) so leave now. */
taskEXIT_CRITICAL();
8003348: f001 fdac bl 8004ea4 <vPortExitCritical>
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
800334c: 2300 movs r3, #0
800334e: e062 b.n 8003416 <xQueueReceive+0x1b2>
}
else if( xEntryTimeSet == pdFALSE )
8003350: 6afb ldr r3, [r7, #44] ; 0x2c
8003352: 2b00 cmp r3, #0
8003354: d106 bne.n 8003364 <xQueueReceive+0x100>
{
/* The queue was empty and a block time was specified so
configure the timeout structure. */
vTaskInternalSetTimeOutState( &xTimeOut );
8003356: f107 0310 add.w r3, r7, #16
800335a: 4618 mov r0, r3
800335c: f000 feba bl 80040d4 <vTaskInternalSetTimeOutState>
xEntryTimeSet = pdTRUE;
8003360: 2301 movs r3, #1
8003362: 62fb str r3, [r7, #44] ; 0x2c
/* Entry time was already set. */
mtCOVERAGE_TEST_MARKER();
}
}
}
taskEXIT_CRITICAL();
8003364: f001 fd9e bl 8004ea4 <vPortExitCritical>
/* Interrupts and other tasks can send to and receive from the queue
now the critical section has been exited. */
vTaskSuspendAll();
8003368: f000 fc26 bl 8003bb8 <vTaskSuspendAll>
prvLockQueue( pxQueue );
800336c: f001 fd6a bl 8004e44 <vPortEnterCritical>
8003370: 6abb ldr r3, [r7, #40] ; 0x28
8003372: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
8003376: b25b sxtb r3, r3
8003378: f1b3 3fff cmp.w r3, #4294967295
800337c: d103 bne.n 8003386 <xQueueReceive+0x122>
800337e: 6abb ldr r3, [r7, #40] ; 0x28
8003380: 2200 movs r2, #0
8003382: f883 2044 strb.w r2, [r3, #68] ; 0x44
8003386: 6abb ldr r3, [r7, #40] ; 0x28
8003388: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
800338c: b25b sxtb r3, r3
800338e: f1b3 3fff cmp.w r3, #4294967295
8003392: d103 bne.n 800339c <xQueueReceive+0x138>
8003394: 6abb ldr r3, [r7, #40] ; 0x28
8003396: 2200 movs r2, #0
8003398: f883 2045 strb.w r2, [r3, #69] ; 0x45
800339c: f001 fd82 bl 8004ea4 <vPortExitCritical>
/* Update the timeout state to see if it has expired yet. */
if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
80033a0: 1d3a adds r2, r7, #4
80033a2: f107 0310 add.w r3, r7, #16
80033a6: 4611 mov r1, r2
80033a8: 4618 mov r0, r3
80033aa: f000 fea9 bl 8004100 <xTaskCheckForTimeOut>
80033ae: 4603 mov r3, r0
80033b0: 2b00 cmp r3, #0
80033b2: d123 bne.n 80033fc <xQueueReceive+0x198>
{
/* The timeout has not expired. If the queue is still empty place
the task on the list of tasks waiting to receive from the queue. */
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
80033b4: 6ab8 ldr r0, [r7, #40] ; 0x28
80033b6: f000 f917 bl 80035e8 <prvIsQueueEmpty>
80033ba: 4603 mov r3, r0
80033bc: 2b00 cmp r3, #0
80033be: d017 beq.n 80033f0 <xQueueReceive+0x18c>
{
traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
80033c0: 6abb ldr r3, [r7, #40] ; 0x28
80033c2: 3324 adds r3, #36 ; 0x24
80033c4: 687a ldr r2, [r7, #4]
80033c6: 4611 mov r1, r2
80033c8: 4618 mov r0, r3
80033ca: f000 fdcf bl 8003f6c <vTaskPlaceOnEventList>
prvUnlockQueue( pxQueue );
80033ce: 6ab8 ldr r0, [r7, #40] ; 0x28
80033d0: f000 f8b8 bl 8003544 <prvUnlockQueue>
if( xTaskResumeAll() == pdFALSE )
80033d4: f000 fbfe bl 8003bd4 <xTaskResumeAll>
80033d8: 4603 mov r3, r0
80033da: 2b00 cmp r3, #0
80033dc: d189 bne.n 80032f2 <xQueueReceive+0x8e>
{
portYIELD_WITHIN_API();
80033de: 4b10 ldr r3, [pc, #64] ; (8003420 <xQueueReceive+0x1bc>)
80033e0: f04f 5280 mov.w r2, #268435456 ; 0x10000000
80033e4: 601a str r2, [r3, #0]
80033e6: f3bf 8f4f dsb sy
80033ea: f3bf 8f6f isb sy
80033ee: e780 b.n 80032f2 <xQueueReceive+0x8e>
}
else
{
/* The queue contains data again. Loop back to try and read the
data. */
prvUnlockQueue( pxQueue );
80033f0: 6ab8 ldr r0, [r7, #40] ; 0x28
80033f2: f000 f8a7 bl 8003544 <prvUnlockQueue>
( void ) xTaskResumeAll();
80033f6: f000 fbed bl 8003bd4 <xTaskResumeAll>
80033fa: e77a b.n 80032f2 <xQueueReceive+0x8e>
}
else
{
/* Timed out. If there is no data in the queue exit, otherwise loop
back and attempt to read the data. */
prvUnlockQueue( pxQueue );
80033fc: 6ab8 ldr r0, [r7, #40] ; 0x28
80033fe: f000 f8a1 bl 8003544 <prvUnlockQueue>
( void ) xTaskResumeAll();
8003402: f000 fbe7 bl 8003bd4 <xTaskResumeAll>
if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
8003406: 6ab8 ldr r0, [r7, #40] ; 0x28
8003408: f000 f8ee bl 80035e8 <prvIsQueueEmpty>
800340c: 4603 mov r3, r0
800340e: 2b00 cmp r3, #0
8003410: f43f af6f beq.w 80032f2 <xQueueReceive+0x8e>
{
traceQUEUE_RECEIVE_FAILED( pxQueue );
return errQUEUE_EMPTY;
8003414: 2300 movs r3, #0
{
mtCOVERAGE_TEST_MARKER();
}
}
} /*lint -restore */
}
8003416: 4618 mov r0, r3
8003418: 3730 adds r7, #48 ; 0x30
800341a: 46bd mov sp, r7
800341c: bd80 pop {r7, pc}
800341e: bf00 nop
8003420: e000ed04 .word 0xe000ed04
08003424 <prvCopyDataToQueue>:
#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/
static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
8003424: b580 push {r7, lr}
8003426: b086 sub sp, #24
8003428: af00 add r7, sp, #0
800342a: 60f8 str r0, [r7, #12]
800342c: 60b9 str r1, [r7, #8]
800342e: 607a str r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
8003430: 2300 movs r3, #0
8003432: 617b str r3, [r7, #20]
UBaseType_t uxMessagesWaiting;
/* This function is called from a critical section. */
uxMessagesWaiting = pxQueue->uxMessagesWaiting;
8003434: 68fb ldr r3, [r7, #12]
8003436: 6b9b ldr r3, [r3, #56] ; 0x38
8003438: 613b str r3, [r7, #16]
if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
800343a: 68fb ldr r3, [r7, #12]
800343c: 6c1b ldr r3, [r3, #64] ; 0x40
800343e: 2b00 cmp r3, #0
8003440: d10d bne.n 800345e <prvCopyDataToQueue+0x3a>
{
#if ( configUSE_MUTEXES == 1 )
{
if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
8003442: 68fb ldr r3, [r7, #12]
8003444: 681b ldr r3, [r3, #0]
8003446: 2b00 cmp r3, #0
8003448: d14d bne.n 80034e6 <prvCopyDataToQueue+0xc2>
{
/* The mutex is no longer being held. */
xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
800344a: 68fb ldr r3, [r7, #12]
800344c: 689b ldr r3, [r3, #8]
800344e: 4618 mov r0, r3
8003450: f000 ffbc bl 80043cc <xTaskPriorityDisinherit>
8003454: 6178 str r0, [r7, #20]
pxQueue->u.xSemaphore.xMutexHolder = NULL;
8003456: 68fb ldr r3, [r7, #12]
8003458: 2200 movs r2, #0
800345a: 609a str r2, [r3, #8]
800345c: e043 b.n 80034e6 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_MUTEXES */
}
else if( xPosition == queueSEND_TO_BACK )
800345e: 687b ldr r3, [r7, #4]
8003460: 2b00 cmp r3, #0
8003462: d119 bne.n 8003498 <prvCopyDataToQueue+0x74>
{
( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
8003464: 68fb ldr r3, [r7, #12]
8003466: 6858 ldr r0, [r3, #4]
8003468: 68fb ldr r3, [r7, #12]
800346a: 6c1b ldr r3, [r3, #64] ; 0x40
800346c: 461a mov r2, r3
800346e: 68b9 ldr r1, [r7, #8]
8003470: f002 f878 bl 8005564 <memcpy>
pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
8003474: 68fb ldr r3, [r7, #12]
8003476: 685a ldr r2, [r3, #4]
8003478: 68fb ldr r3, [r7, #12]
800347a: 6c1b ldr r3, [r3, #64] ; 0x40
800347c: 441a add r2, r3
800347e: 68fb ldr r3, [r7, #12]
8003480: 605a str r2, [r3, #4]
if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
8003482: 68fb ldr r3, [r7, #12]
8003484: 685a ldr r2, [r3, #4]
8003486: 68fb ldr r3, [r7, #12]
8003488: 689b ldr r3, [r3, #8]
800348a: 429a cmp r2, r3
800348c: d32b bcc.n 80034e6 <prvCopyDataToQueue+0xc2>
{
pxQueue->pcWriteTo = pxQueue->pcHead;
800348e: 68fb ldr r3, [r7, #12]
8003490: 681a ldr r2, [r3, #0]
8003492: 68fb ldr r3, [r7, #12]
8003494: 605a str r2, [r3, #4]
8003496: e026 b.n 80034e6 <prvCopyDataToQueue+0xc2>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */
8003498: 68fb ldr r3, [r7, #12]
800349a: 68d8 ldr r0, [r3, #12]
800349c: 68fb ldr r3, [r7, #12]
800349e: 6c1b ldr r3, [r3, #64] ; 0x40
80034a0: 461a mov r2, r3
80034a2: 68b9 ldr r1, [r7, #8]
80034a4: f002 f85e bl 8005564 <memcpy>
pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
80034a8: 68fb ldr r3, [r7, #12]
80034aa: 68da ldr r2, [r3, #12]
80034ac: 68fb ldr r3, [r7, #12]
80034ae: 6c1b ldr r3, [r3, #64] ; 0x40
80034b0: 425b negs r3, r3
80034b2: 441a add r2, r3
80034b4: 68fb ldr r3, [r7, #12]
80034b6: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
80034b8: 68fb ldr r3, [r7, #12]
80034ba: 68da ldr r2, [r3, #12]
80034bc: 68fb ldr r3, [r7, #12]
80034be: 681b ldr r3, [r3, #0]
80034c0: 429a cmp r2, r3
80034c2: d207 bcs.n 80034d4 <prvCopyDataToQueue+0xb0>
{
pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
80034c4: 68fb ldr r3, [r7, #12]
80034c6: 689a ldr r2, [r3, #8]
80034c8: 68fb ldr r3, [r7, #12]
80034ca: 6c1b ldr r3, [r3, #64] ; 0x40
80034cc: 425b negs r3, r3
80034ce: 441a add r2, r3
80034d0: 68fb ldr r3, [r7, #12]
80034d2: 60da str r2, [r3, #12]
else
{
mtCOVERAGE_TEST_MARKER();
}
if( xPosition == queueOVERWRITE )
80034d4: 687b ldr r3, [r7, #4]
80034d6: 2b02 cmp r3, #2
80034d8: d105 bne.n 80034e6 <prvCopyDataToQueue+0xc2>
{
if( uxMessagesWaiting > ( UBaseType_t ) 0 )
80034da: 693b ldr r3, [r7, #16]
80034dc: 2b00 cmp r3, #0
80034de: d002 beq.n 80034e6 <prvCopyDataToQueue+0xc2>
{
/* An item is not being added but overwritten, so subtract
one from the recorded number of items in the queue so when
one is added again below the number of recorded items remains
correct. */
--uxMessagesWaiting;
80034e0: 693b ldr r3, [r7, #16]
80034e2: 3b01 subs r3, #1
80034e4: 613b str r3, [r7, #16]
{
mtCOVERAGE_TEST_MARKER();
}
}
pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
80034e6: 693b ldr r3, [r7, #16]
80034e8: 1c5a adds r2, r3, #1
80034ea: 68fb ldr r3, [r7, #12]
80034ec: 639a str r2, [r3, #56] ; 0x38
return xReturn;
80034ee: 697b ldr r3, [r7, #20]
}
80034f0: 4618 mov r0, r3
80034f2: 3718 adds r7, #24
80034f4: 46bd mov sp, r7
80034f6: bd80 pop {r7, pc}
080034f8 <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/
static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
80034f8: b580 push {r7, lr}
80034fa: b082 sub sp, #8
80034fc: af00 add r7, sp, #0
80034fe: 6078 str r0, [r7, #4]
8003500: 6039 str r1, [r7, #0]
if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
8003502: 687b ldr r3, [r7, #4]
8003504: 6c1b ldr r3, [r3, #64] ; 0x40
8003506: 2b00 cmp r3, #0
8003508: d018 beq.n 800353c <prvCopyDataFromQueue+0x44>
{
pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
800350a: 687b ldr r3, [r7, #4]
800350c: 68da ldr r2, [r3, #12]
800350e: 687b ldr r3, [r7, #4]
8003510: 6c1b ldr r3, [r3, #64] ; 0x40
8003512: 441a add r2, r3
8003514: 687b ldr r3, [r7, #4]
8003516: 60da str r2, [r3, #12]
if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
8003518: 687b ldr r3, [r7, #4]
800351a: 68da ldr r2, [r3, #12]
800351c: 687b ldr r3, [r7, #4]
800351e: 689b ldr r3, [r3, #8]
8003520: 429a cmp r2, r3
8003522: d303 bcc.n 800352c <prvCopyDataFromQueue+0x34>
{
pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
8003524: 687b ldr r3, [r7, #4]
8003526: 681a ldr r2, [r3, #0]
8003528: 687b ldr r3, [r7, #4]
800352a: 60da str r2, [r3, #12]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
800352c: 687b ldr r3, [r7, #4]
800352e: 68d9 ldr r1, [r3, #12]
8003530: 687b ldr r3, [r7, #4]
8003532: 6c1b ldr r3, [r3, #64] ; 0x40
8003534: 461a mov r2, r3
8003536: 6838 ldr r0, [r7, #0]
8003538: f002 f814 bl 8005564 <memcpy>
}
}
800353c: bf00 nop
800353e: 3708 adds r7, #8
8003540: 46bd mov sp, r7
8003542: bd80 pop {r7, pc}
08003544 <prvUnlockQueue>:
/*-----------------------------------------------------------*/
static void prvUnlockQueue( Queue_t * const pxQueue )
{
8003544: b580 push {r7, lr}
8003546: b084 sub sp, #16
8003548: af00 add r7, sp, #0
800354a: 6078 str r0, [r7, #4]
/* The lock counts contains the number of extra data items placed or
removed from the queue while the queue was locked. When a queue is
locked items can be added or removed, but the event lists cannot be
updated. */
taskENTER_CRITICAL();
800354c: f001 fc7a bl 8004e44 <vPortEnterCritical>
{
int8_t cTxLock = pxQueue->cTxLock;
8003550: 687b ldr r3, [r7, #4]
8003552: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
8003556: 73fb strb r3, [r7, #15]
/* See if data was added to the queue while it was locked. */
while( cTxLock > queueLOCKED_UNMODIFIED )
8003558: e011 b.n 800357e <prvUnlockQueue+0x3a>
}
#else /* configUSE_QUEUE_SETS */
{
/* Tasks that are removed from the event list will get added to
the pending ready list as the scheduler is still suspended. */
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
800355a: 687b ldr r3, [r7, #4]
800355c: 6a5b ldr r3, [r3, #36] ; 0x24
800355e: 2b00 cmp r3, #0
8003560: d012 beq.n 8003588 <prvUnlockQueue+0x44>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
8003562: 687b ldr r3, [r7, #4]
8003564: 3324 adds r3, #36 ; 0x24
8003566: 4618 mov r0, r3
8003568: f000 fd50 bl 800400c <xTaskRemoveFromEventList>
800356c: 4603 mov r3, r0
800356e: 2b00 cmp r3, #0
8003570: d001 beq.n 8003576 <prvUnlockQueue+0x32>
{
/* The task waiting has a higher priority so record that
a context switch is required. */
vTaskMissedYield();
8003572: f000 fe27 bl 80041c4 <vTaskMissedYield>
break;
}
}
#endif /* configUSE_QUEUE_SETS */
--cTxLock;
8003576: 7bfb ldrb r3, [r7, #15]
8003578: 3b01 subs r3, #1
800357a: b2db uxtb r3, r3
800357c: 73fb strb r3, [r7, #15]
while( cTxLock > queueLOCKED_UNMODIFIED )
800357e: f997 300f ldrsb.w r3, [r7, #15]
8003582: 2b00 cmp r3, #0
8003584: dce9 bgt.n 800355a <prvUnlockQueue+0x16>
8003586: e000 b.n 800358a <prvUnlockQueue+0x46>
break;
8003588: bf00 nop
}
pxQueue->cTxLock = queueUNLOCKED;
800358a: 687b ldr r3, [r7, #4]
800358c: 22ff movs r2, #255 ; 0xff
800358e: f883 2045 strb.w r2, [r3, #69] ; 0x45
}
taskEXIT_CRITICAL();
8003592: f001 fc87 bl 8004ea4 <vPortExitCritical>
/* Do the same for the Rx lock. */
taskENTER_CRITICAL();
8003596: f001 fc55 bl 8004e44 <vPortEnterCritical>
{
int8_t cRxLock = pxQueue->cRxLock;
800359a: 687b ldr r3, [r7, #4]
800359c: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
80035a0: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
80035a2: e011 b.n 80035c8 <prvUnlockQueue+0x84>
{
if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
80035a4: 687b ldr r3, [r7, #4]
80035a6: 691b ldr r3, [r3, #16]
80035a8: 2b00 cmp r3, #0
80035aa: d012 beq.n 80035d2 <prvUnlockQueue+0x8e>
{
if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
80035ac: 687b ldr r3, [r7, #4]
80035ae: 3310 adds r3, #16
80035b0: 4618 mov r0, r3
80035b2: f000 fd2b bl 800400c <xTaskRemoveFromEventList>
80035b6: 4603 mov r3, r0
80035b8: 2b00 cmp r3, #0
80035ba: d001 beq.n 80035c0 <prvUnlockQueue+0x7c>
{
vTaskMissedYield();
80035bc: f000 fe02 bl 80041c4 <vTaskMissedYield>
else
{
mtCOVERAGE_TEST_MARKER();
}
--cRxLock;
80035c0: 7bbb ldrb r3, [r7, #14]
80035c2: 3b01 subs r3, #1
80035c4: b2db uxtb r3, r3
80035c6: 73bb strb r3, [r7, #14]
while( cRxLock > queueLOCKED_UNMODIFIED )
80035c8: f997 300e ldrsb.w r3, [r7, #14]
80035cc: 2b00 cmp r3, #0
80035ce: dce9 bgt.n 80035a4 <prvUnlockQueue+0x60>
80035d0: e000 b.n 80035d4 <prvUnlockQueue+0x90>
}
else
{
break;
80035d2: bf00 nop
}
}
pxQueue->cRxLock = queueUNLOCKED;
80035d4: 687b ldr r3, [r7, #4]
80035d6: 22ff movs r2, #255 ; 0xff
80035d8: f883 2044 strb.w r2, [r3, #68] ; 0x44
}
taskEXIT_CRITICAL();
80035dc: f001 fc62 bl 8004ea4 <vPortExitCritical>
}
80035e0: bf00 nop
80035e2: 3710 adds r7, #16
80035e4: 46bd mov sp, r7
80035e6: bd80 pop {r7, pc}
080035e8 <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
80035e8: b580 push {r7, lr}
80035ea: b084 sub sp, #16
80035ec: af00 add r7, sp, #0
80035ee: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
80035f0: f001 fc28 bl 8004e44 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
80035f4: 687b ldr r3, [r7, #4]
80035f6: 6b9b ldr r3, [r3, #56] ; 0x38
80035f8: 2b00 cmp r3, #0
80035fa: d102 bne.n 8003602 <prvIsQueueEmpty+0x1a>
{
xReturn = pdTRUE;
80035fc: 2301 movs r3, #1
80035fe: 60fb str r3, [r7, #12]
8003600: e001 b.n 8003606 <prvIsQueueEmpty+0x1e>
}
else
{
xReturn = pdFALSE;
8003602: 2300 movs r3, #0
8003604: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
8003606: f001 fc4d bl 8004ea4 <vPortExitCritical>
return xReturn;
800360a: 68fb ldr r3, [r7, #12]
}
800360c: 4618 mov r0, r3
800360e: 3710 adds r7, #16
8003610: 46bd mov sp, r7
8003612: bd80 pop {r7, pc}
08003614 <prvIsQueueFull>:
return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/
static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
8003614: b580 push {r7, lr}
8003616: b084 sub sp, #16
8003618: af00 add r7, sp, #0
800361a: 6078 str r0, [r7, #4]
BaseType_t xReturn;
taskENTER_CRITICAL();
800361c: f001 fc12 bl 8004e44 <vPortEnterCritical>
{
if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
8003620: 687b ldr r3, [r7, #4]
8003622: 6b9a ldr r2, [r3, #56] ; 0x38
8003624: 687b ldr r3, [r7, #4]
8003626: 6bdb ldr r3, [r3, #60] ; 0x3c
8003628: 429a cmp r2, r3
800362a: d102 bne.n 8003632 <prvIsQueueFull+0x1e>
{
xReturn = pdTRUE;
800362c: 2301 movs r3, #1
800362e: 60fb str r3, [r7, #12]
8003630: e001 b.n 8003636 <prvIsQueueFull+0x22>
}
else
{
xReturn = pdFALSE;
8003632: 2300 movs r3, #0
8003634: 60fb str r3, [r7, #12]
}
}
taskEXIT_CRITICAL();
8003636: f001 fc35 bl 8004ea4 <vPortExitCritical>
return xReturn;
800363a: 68fb ldr r3, [r7, #12]
}
800363c: 4618 mov r0, r3
800363e: 3710 adds r7, #16
8003640: 46bd mov sp, r7
8003642: bd80 pop {r7, pc}
08003644 <vQueueAddToRegistry>:
/*-----------------------------------------------------------*/
#if ( configQUEUE_REGISTRY_SIZE > 0 )
void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
{
8003644: b480 push {r7}
8003646: b085 sub sp, #20
8003648: af00 add r7, sp, #0
800364a: 6078 str r0, [r7, #4]
800364c: 6039 str r1, [r7, #0]
UBaseType_t ux;
/* See if there is an empty space in the registry. A NULL name denotes
a free slot. */
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
800364e: 2300 movs r3, #0
8003650: 60fb str r3, [r7, #12]
8003652: e014 b.n 800367e <vQueueAddToRegistry+0x3a>
{
if( xQueueRegistry[ ux ].pcQueueName == NULL )
8003654: 4a0f ldr r2, [pc, #60] ; (8003694 <vQueueAddToRegistry+0x50>)
8003656: 68fb ldr r3, [r7, #12]
8003658: f852 3033 ldr.w r3, [r2, r3, lsl #3]
800365c: 2b00 cmp r3, #0
800365e: d10b bne.n 8003678 <vQueueAddToRegistry+0x34>
{
/* Store the information on this queue. */
xQueueRegistry[ ux ].pcQueueName = pcQueueName;
8003660: 490c ldr r1, [pc, #48] ; (8003694 <vQueueAddToRegistry+0x50>)
8003662: 68fb ldr r3, [r7, #12]
8003664: 683a ldr r2, [r7, #0]
8003666: f841 2033 str.w r2, [r1, r3, lsl #3]
xQueueRegistry[ ux ].xHandle = xQueue;
800366a: 4a0a ldr r2, [pc, #40] ; (8003694 <vQueueAddToRegistry+0x50>)
800366c: 68fb ldr r3, [r7, #12]
800366e: 00db lsls r3, r3, #3
8003670: 4413 add r3, r2
8003672: 687a ldr r2, [r7, #4]
8003674: 605a str r2, [r3, #4]
traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
break;
8003676: e006 b.n 8003686 <vQueueAddToRegistry+0x42>
for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
8003678: 68fb ldr r3, [r7, #12]
800367a: 3301 adds r3, #1
800367c: 60fb str r3, [r7, #12]
800367e: 68fb ldr r3, [r7, #12]
8003680: 2b07 cmp r3, #7
8003682: d9e7 bls.n 8003654 <vQueueAddToRegistry+0x10>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
8003684: bf00 nop
8003686: bf00 nop
8003688: 3714 adds r7, #20
800368a: 46bd mov sp, r7
800368c: f85d 7b04 ldr.w r7, [sp], #4
8003690: 4770 bx lr
8003692: bf00 nop
8003694: 20000880 .word 0x20000880
08003698 <vQueueWaitForMessageRestricted>:
/*-----------------------------------------------------------*/
#if ( configUSE_TIMERS == 1 )
void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
{
8003698: b580 push {r7, lr}
800369a: b086 sub sp, #24
800369c: af00 add r7, sp, #0
800369e: 60f8 str r0, [r7, #12]
80036a0: 60b9 str r1, [r7, #8]
80036a2: 607a str r2, [r7, #4]
Queue_t * const pxQueue = xQueue;
80036a4: 68fb ldr r3, [r7, #12]
80036a6: 617b str r3, [r7, #20]
will not actually cause the task to block, just place it on a blocked
list. It will not block until the scheduler is unlocked - at which
time a yield will be performed. If an item is added to the queue while
the queue is locked, and the calling task blocks on the queue, then the
calling task will be immediately unblocked when the queue is unlocked. */
prvLockQueue( pxQueue );
80036a8: f001 fbcc bl 8004e44 <vPortEnterCritical>
80036ac: 697b ldr r3, [r7, #20]
80036ae: f893 3044 ldrb.w r3, [r3, #68] ; 0x44
80036b2: b25b sxtb r3, r3
80036b4: f1b3 3fff cmp.w r3, #4294967295
80036b8: d103 bne.n 80036c2 <vQueueWaitForMessageRestricted+0x2a>
80036ba: 697b ldr r3, [r7, #20]
80036bc: 2200 movs r2, #0
80036be: f883 2044 strb.w r2, [r3, #68] ; 0x44
80036c2: 697b ldr r3, [r7, #20]
80036c4: f893 3045 ldrb.w r3, [r3, #69] ; 0x45
80036c8: b25b sxtb r3, r3
80036ca: f1b3 3fff cmp.w r3, #4294967295
80036ce: d103 bne.n 80036d8 <vQueueWaitForMessageRestricted+0x40>
80036d0: 697b ldr r3, [r7, #20]
80036d2: 2200 movs r2, #0
80036d4: f883 2045 strb.w r2, [r3, #69] ; 0x45
80036d8: f001 fbe4 bl 8004ea4 <vPortExitCritical>
if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
80036dc: 697b ldr r3, [r7, #20]
80036de: 6b9b ldr r3, [r3, #56] ; 0x38
80036e0: 2b00 cmp r3, #0
80036e2: d106 bne.n 80036f2 <vQueueWaitForMessageRestricted+0x5a>
{
/* There is nothing in the queue, block for the specified period. */
vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
80036e4: 697b ldr r3, [r7, #20]
80036e6: 3324 adds r3, #36 ; 0x24
80036e8: 687a ldr r2, [r7, #4]
80036ea: 68b9 ldr r1, [r7, #8]
80036ec: 4618 mov r0, r3
80036ee: f000 fc61 bl 8003fb4 <vTaskPlaceOnEventListRestricted>
}
else
{
mtCOVERAGE_TEST_MARKER();
}
prvUnlockQueue( pxQueue );
80036f2: 6978 ldr r0, [r7, #20]
80036f4: f7ff ff26 bl 8003544 <prvUnlockQueue>
}
80036f8: bf00 nop
80036fa: 3718 adds r7, #24
80036fc: 46bd mov sp, r7
80036fe: bd80 pop {r7, pc}
08003700 <xTaskCreateStatic>:
const uint32_t ulStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
StackType_t * const puxStackBuffer,
StaticTask_t * const pxTaskBuffer )
{
8003700: b580 push {r7, lr}
8003702: b08e sub sp, #56 ; 0x38
8003704: af04 add r7, sp, #16
8003706: 60f8 str r0, [r7, #12]
8003708: 60b9 str r1, [r7, #8]
800370a: 607a str r2, [r7, #4]
800370c: 603b str r3, [r7, #0]
TCB_t *pxNewTCB;
TaskHandle_t xReturn;
configASSERT( puxStackBuffer != NULL );
800370e: 6b7b ldr r3, [r7, #52] ; 0x34
8003710: 2b00 cmp r3, #0
8003712: d10a bne.n 800372a <xTaskCreateStatic+0x2a>
__asm volatile
8003714: f04f 0350 mov.w r3, #80 ; 0x50
8003718: f383 8811 msr BASEPRI, r3
800371c: f3bf 8f6f isb sy
8003720: f3bf 8f4f dsb sy
8003724: 623b str r3, [r7, #32]
}
8003726: bf00 nop
8003728: e7fe b.n 8003728 <xTaskCreateStatic+0x28>
configASSERT( pxTaskBuffer != NULL );
800372a: 6bbb ldr r3, [r7, #56] ; 0x38
800372c: 2b00 cmp r3, #0
800372e: d10a bne.n 8003746 <xTaskCreateStatic+0x46>
__asm volatile
8003730: f04f 0350 mov.w r3, #80 ; 0x50
8003734: f383 8811 msr BASEPRI, r3
8003738: f3bf 8f6f isb sy
800373c: f3bf 8f4f dsb sy
8003740: 61fb str r3, [r7, #28]
}
8003742: bf00 nop
8003744: e7fe b.n 8003744 <xTaskCreateStatic+0x44>
#if( configASSERT_DEFINED == 1 )
{
/* Sanity check that the size of the structure used to declare a
variable of type StaticTask_t equals the size of the real task
structure. */
volatile size_t xSize = sizeof( StaticTask_t );
8003746: 23a8 movs r3, #168 ; 0xa8
8003748: 613b str r3, [r7, #16]
configASSERT( xSize == sizeof( TCB_t ) );
800374a: 693b ldr r3, [r7, #16]
800374c: 2ba8 cmp r3, #168 ; 0xa8
800374e: d00a beq.n 8003766 <xTaskCreateStatic+0x66>
__asm volatile
8003750: f04f 0350 mov.w r3, #80 ; 0x50
8003754: f383 8811 msr BASEPRI, r3
8003758: f3bf 8f6f isb sy
800375c: f3bf 8f4f dsb sy
8003760: 61bb str r3, [r7, #24]
}
8003762: bf00 nop
8003764: e7fe b.n 8003764 <xTaskCreateStatic+0x64>
( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
8003766: 693b ldr r3, [r7, #16]
}
#endif /* configASSERT_DEFINED */
if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
8003768: 6bbb ldr r3, [r7, #56] ; 0x38
800376a: 2b00 cmp r3, #0
800376c: d01e beq.n 80037ac <xTaskCreateStatic+0xac>
800376e: 6b7b ldr r3, [r7, #52] ; 0x34
8003770: 2b00 cmp r3, #0
8003772: d01b beq.n 80037ac <xTaskCreateStatic+0xac>
{
/* The memory used for the task's TCB and stack are passed into this
function - use them. */
pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
8003774: 6bbb ldr r3, [r7, #56] ; 0x38
8003776: 627b str r3, [r7, #36] ; 0x24
pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
8003778: 6a7b ldr r3, [r7, #36] ; 0x24
800377a: 6b7a ldr r2, [r7, #52] ; 0x34
800377c: 631a str r2, [r3, #48] ; 0x30
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created statically in case the task is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
800377e: 6a7b ldr r3, [r7, #36] ; 0x24
8003780: 2202 movs r2, #2
8003782: f883 20a5 strb.w r2, [r3, #165] ; 0xa5
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
8003786: 2300 movs r3, #0
8003788: 9303 str r3, [sp, #12]
800378a: 6a7b ldr r3, [r7, #36] ; 0x24
800378c: 9302 str r3, [sp, #8]
800378e: f107 0314 add.w r3, r7, #20
8003792: 9301 str r3, [sp, #4]
8003794: 6b3b ldr r3, [r7, #48] ; 0x30
8003796: 9300 str r3, [sp, #0]
8003798: 683b ldr r3, [r7, #0]
800379a: 687a ldr r2, [r7, #4]
800379c: 68b9 ldr r1, [r7, #8]
800379e: 68f8 ldr r0, [r7, #12]
80037a0: f000 f850 bl 8003844 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
80037a4: 6a78 ldr r0, [r7, #36] ; 0x24
80037a6: f000 f8f3 bl 8003990 <prvAddNewTaskToReadyList>
80037aa: e001 b.n 80037b0 <xTaskCreateStatic+0xb0>
}
else
{
xReturn = NULL;
80037ac: 2300 movs r3, #0
80037ae: 617b str r3, [r7, #20]
}
return xReturn;
80037b0: 697b ldr r3, [r7, #20]
}
80037b2: 4618 mov r0, r3
80037b4: 3728 adds r7, #40 ; 0x28
80037b6: 46bd mov sp, r7
80037b8: bd80 pop {r7, pc}
080037ba <xTaskCreate>:
const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
const configSTACK_DEPTH_TYPE usStackDepth,
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask )
{
80037ba: b580 push {r7, lr}
80037bc: b08c sub sp, #48 ; 0x30
80037be: af04 add r7, sp, #16
80037c0: 60f8 str r0, [r7, #12]
80037c2: 60b9 str r1, [r7, #8]
80037c4: 603b str r3, [r7, #0]
80037c6: 4613 mov r3, r2
80037c8: 80fb strh r3, [r7, #6]
#else /* portSTACK_GROWTH */
{
StackType_t *pxStack;
/* Allocate space for the stack used by the task being created. */
pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
80037ca: 88fb ldrh r3, [r7, #6]
80037cc: 009b lsls r3, r3, #2
80037ce: 4618 mov r0, r3
80037d0: f001 fc5a bl 8005088 <pvPortMalloc>
80037d4: 6178 str r0, [r7, #20]
if( pxStack != NULL )
80037d6: 697b ldr r3, [r7, #20]
80037d8: 2b00 cmp r3, #0
80037da: d00e beq.n 80037fa <xTaskCreate+0x40>
{
/* Allocate space for the TCB. */
pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
80037dc: 20a8 movs r0, #168 ; 0xa8
80037de: f001 fc53 bl 8005088 <pvPortMalloc>
80037e2: 61f8 str r0, [r7, #28]
if( pxNewTCB != NULL )
80037e4: 69fb ldr r3, [r7, #28]
80037e6: 2b00 cmp r3, #0
80037e8: d003 beq.n 80037f2 <xTaskCreate+0x38>
{
/* Store the stack location in the TCB. */
pxNewTCB->pxStack = pxStack;
80037ea: 69fb ldr r3, [r7, #28]
80037ec: 697a ldr r2, [r7, #20]
80037ee: 631a str r2, [r3, #48] ; 0x30
80037f0: e005 b.n 80037fe <xTaskCreate+0x44>
}
else
{
/* The stack cannot be used as the TCB was not created. Free
it again. */
vPortFree( pxStack );
80037f2: 6978 ldr r0, [r7, #20]
80037f4: f001 fd14 bl 8005220 <vPortFree>
80037f8: e001 b.n 80037fe <xTaskCreate+0x44>
}
}
else
{
pxNewTCB = NULL;
80037fa: 2300 movs r3, #0
80037fc: 61fb str r3, [r7, #28]
}
}
#endif /* portSTACK_GROWTH */
if( pxNewTCB != NULL )
80037fe: 69fb ldr r3, [r7, #28]
8003800: 2b00 cmp r3, #0
8003802: d017 beq.n 8003834 <xTaskCreate+0x7a>
{
#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
{
/* Tasks can be created statically or dynamically, so note this
task was created dynamically in case it is later deleted. */
pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
8003804: 69fb ldr r3, [r7, #28]
8003806: 2200 movs r2, #0
8003808: f883 20a5 strb.w r2, [r3, #165] ; 0xa5
}
#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
800380c: 88fa ldrh r2, [r7, #6]
800380e: 2300 movs r3, #0
8003810: 9303 str r3, [sp, #12]
8003812: 69fb ldr r3, [r7, #28]
8003814: 9302 str r3, [sp, #8]
8003816: 6afb ldr r3, [r7, #44] ; 0x2c
8003818: 9301 str r3, [sp, #4]
800381a: 6abb ldr r3, [r7, #40] ; 0x28
800381c: 9300 str r3, [sp, #0]
800381e: 683b ldr r3, [r7, #0]
8003820: 68b9 ldr r1, [r7, #8]
8003822: 68f8 ldr r0, [r7, #12]
8003824: f000 f80e bl 8003844 <prvInitialiseNewTask>
prvAddNewTaskToReadyList( pxNewTCB );
8003828: 69f8 ldr r0, [r7, #28]
800382a: f000 f8b1 bl 8003990 <prvAddNewTaskToReadyList>
xReturn = pdPASS;
800382e: 2301 movs r3, #1
8003830: 61bb str r3, [r7, #24]
8003832: e002 b.n 800383a <xTaskCreate+0x80>
}
else
{
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
8003834: f04f 33ff mov.w r3, #4294967295
8003838: 61bb str r3, [r7, #24]
}
return xReturn;
800383a: 69bb ldr r3, [r7, #24]
}
800383c: 4618 mov r0, r3
800383e: 3720 adds r7, #32
8003840: 46bd mov sp, r7
8003842: bd80 pop {r7, pc}
08003844 <prvInitialiseNewTask>:
void * const pvParameters,
UBaseType_t uxPriority,
TaskHandle_t * const pxCreatedTask,
TCB_t *pxNewTCB,
const MemoryRegion_t * const xRegions )
{
8003844: b580 push {r7, lr}
8003846: b088 sub sp, #32
8003848: af00 add r7, sp, #0
800384a: 60f8 str r0, [r7, #12]
800384c: 60b9 str r1, [r7, #8]
800384e: 607a str r2, [r7, #4]
8003850: 603b str r3, [r7, #0]
/* Avoid dependency on memset() if it is not required. */
#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
{
/* Fill the stack with a known value to assist debugging. */
( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
8003852: 6b3b ldr r3, [r7, #48] ; 0x30
8003854: 6b18 ldr r0, [r3, #48] ; 0x30
8003856: 687b ldr r3, [r7, #4]
8003858: 009b lsls r3, r3, #2
800385a: 461a mov r2, r3
800385c: 21a5 movs r1, #165 ; 0xa5
800385e: f001 fdfd bl 800545c <memset>
grows from high memory to low (as per the 80x86) or vice versa.
portSTACK_GROWTH is used to make the result positive or negative as required
by the port. */
#if( portSTACK_GROWTH < 0 )
{
pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
8003862: 6b3b ldr r3, [r7, #48] ; 0x30
8003864: 6b1a ldr r2, [r3, #48] ; 0x30
8003866: 687b ldr r3, [r7, #4]
8003868: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000
800386c: 3b01 subs r3, #1
800386e: 009b lsls r3, r3, #2
8003870: 4413 add r3, r2
8003872: 61bb str r3, [r7, #24]
pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */
8003874: 69bb ldr r3, [r7, #24]
8003876: f023 0307 bic.w r3, r3, #7
800387a: 61bb str r3, [r7, #24]
/* Check the alignment of the calculated top of stack is correct. */
configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
800387c: 69bb ldr r3, [r7, #24]
800387e: f003 0307 and.w r3, r3, #7
8003882: 2b00 cmp r3, #0
8003884: d00a beq.n 800389c <prvInitialiseNewTask+0x58>
__asm volatile
8003886: f04f 0350 mov.w r3, #80 ; 0x50
800388a: f383 8811 msr BASEPRI, r3
800388e: f3bf 8f6f isb sy
8003892: f3bf 8f4f dsb sy
8003896: 617b str r3, [r7, #20]
}
8003898: bf00 nop
800389a: e7fe b.n 800389a <prvInitialiseNewTask+0x56>
pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
}
#endif /* portSTACK_GROWTH */
/* Store the task name in the TCB. */
if( pcName != NULL )
800389c: 68bb ldr r3, [r7, #8]
800389e: 2b00 cmp r3, #0
80038a0: d01f beq.n 80038e2 <prvInitialiseNewTask+0x9e>
{
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
80038a2: 2300 movs r3, #0
80038a4: 61fb str r3, [r7, #28]
80038a6: e012 b.n 80038ce <prvInitialiseNewTask+0x8a>
{
pxNewTCB->pcTaskName[ x ] = pcName[ x ];
80038a8: 68ba ldr r2, [r7, #8]
80038aa: 69fb ldr r3, [r7, #28]
80038ac: 4413 add r3, r2
80038ae: 7819 ldrb r1, [r3, #0]
80038b0: 6b3a ldr r2, [r7, #48] ; 0x30
80038b2: 69fb ldr r3, [r7, #28]
80038b4: 4413 add r3, r2
80038b6: 3334 adds r3, #52 ; 0x34
80038b8: 460a mov r2, r1
80038ba: 701a strb r2, [r3, #0]
/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
configMAX_TASK_NAME_LEN characters just in case the memory after the
string is not accessible (extremely unlikely). */
if( pcName[ x ] == ( char ) 0x00 )
80038bc: 68ba ldr r2, [r7, #8]
80038be: 69fb ldr r3, [r7, #28]
80038c0: 4413 add r3, r2
80038c2: 781b ldrb r3, [r3, #0]
80038c4: 2b00 cmp r3, #0
80038c6: d006 beq.n 80038d6 <prvInitialiseNewTask+0x92>
for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
80038c8: 69fb ldr r3, [r7, #28]
80038ca: 3301 adds r3, #1
80038cc: 61fb str r3, [r7, #28]
80038ce: 69fb ldr r3, [r7, #28]
80038d0: 2b0f cmp r3, #15
80038d2: d9e9 bls.n 80038a8 <prvInitialiseNewTask+0x64>
80038d4: e000 b.n 80038d8 <prvInitialiseNewTask+0x94>
{
break;
80038d6: bf00 nop
}
}
/* Ensure the name string is terminated in the case that the string length
was greater or equal to configMAX_TASK_NAME_LEN. */
pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
80038d8: 6b3b ldr r3, [r7, #48] ; 0x30
80038da: 2200 movs r2, #0
80038dc: f883 2043 strb.w r2, [r3, #67] ; 0x43
80038e0: e003 b.n 80038ea <prvInitialiseNewTask+0xa6>
}
else
{
/* The task has not been given a name, so just ensure there is a NULL
terminator when it is read out. */
pxNewTCB->pcTaskName[ 0 ] = 0x00;
80038e2: 6b3b ldr r3, [r7, #48] ; 0x30
80038e4: 2200 movs r2, #0
80038e6: f883 2034 strb.w r2, [r3, #52] ; 0x34
}
/* This is used as an array index so must ensure it's not too large. First
remove the privilege bit if one is present. */
if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
80038ea: 6abb ldr r3, [r7, #40] ; 0x28
80038ec: 2b37 cmp r3, #55 ; 0x37
80038ee: d901 bls.n 80038f4 <prvInitialiseNewTask+0xb0>
{
uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
80038f0: 2337 movs r3, #55 ; 0x37
80038f2: 62bb str r3, [r7, #40] ; 0x28
else
{
mtCOVERAGE_TEST_MARKER();
}
pxNewTCB->uxPriority = uxPriority;
80038f4: 6b3b ldr r3, [r7, #48] ; 0x30
80038f6: 6aba ldr r2, [r7, #40] ; 0x28
80038f8: 62da str r2, [r3, #44] ; 0x2c
#if ( configUSE_MUTEXES == 1 )
{
pxNewTCB->uxBasePriority = uxPriority;
80038fa: 6b3b ldr r3, [r7, #48] ; 0x30
80038fc: 6aba ldr r2, [r7, #40] ; 0x28
80038fe: 64da str r2, [r3, #76] ; 0x4c
pxNewTCB->uxMutexesHeld = 0;
8003900: 6b3b ldr r3, [r7, #48] ; 0x30
8003902: 2200 movs r2, #0
8003904: 651a str r2, [r3, #80] ; 0x50
}
#endif /* configUSE_MUTEXES */
vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
8003906: 6b3b ldr r3, [r7, #48] ; 0x30
8003908: 3304 adds r3, #4
800390a: 4618 mov r0, r3
800390c: f7ff f978 bl 8002c00 <vListInitialiseItem>
vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
8003910: 6b3b ldr r3, [r7, #48] ; 0x30
8003912: 3318 adds r3, #24
8003914: 4618 mov r0, r3
8003916: f7ff f973 bl 8002c00 <vListInitialiseItem>
/* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get
back to the containing TCB from a generic item in a list. */
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
800391a: 6b3b ldr r3, [r7, #48] ; 0x30
800391c: 6b3a ldr r2, [r7, #48] ; 0x30
800391e: 611a str r2, [r3, #16]
/* Event lists are always in priority order. */
listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8003920: 6abb ldr r3, [r7, #40] ; 0x28
8003922: f1c3 0238 rsb r2, r3, #56 ; 0x38
8003926: 6b3b ldr r3, [r7, #48] ; 0x30
8003928: 619a str r2, [r3, #24]
listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
800392a: 6b3b ldr r3, [r7, #48] ; 0x30
800392c: 6b3a ldr r2, [r7, #48] ; 0x30
800392e: 625a str r2, [r3, #36] ; 0x24
}
#endif
#if ( configUSE_TASK_NOTIFICATIONS == 1 )
{
pxNewTCB->ulNotifiedValue = 0;
8003930: 6b3b ldr r3, [r7, #48] ; 0x30
8003932: 2200 movs r2, #0
8003934: f8c3 20a0 str.w r2, [r3, #160] ; 0xa0
pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
8003938: 6b3b ldr r3, [r7, #48] ; 0x30
800393a: 2200 movs r2, #0
800393c: f883 20a4 strb.w r2, [r3, #164] ; 0xa4
#if ( configUSE_NEWLIB_REENTRANT == 1 )
{
/* Initialise this task's Newlib reent structure.
See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
for additional information. */
_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
8003940: 6b3b ldr r3, [r7, #48] ; 0x30
8003942: 3354 adds r3, #84 ; 0x54
8003944: 224c movs r2, #76 ; 0x4c
8003946: 2100 movs r1, #0
8003948: 4618 mov r0, r3
800394a: f001 fd87 bl 800545c <memset>
800394e: 6b3b ldr r3, [r7, #48] ; 0x30
8003950: 4a0c ldr r2, [pc, #48] ; (8003984 <prvInitialiseNewTask+0x140>)
8003952: 659a str r2, [r3, #88] ; 0x58
8003954: 6b3b ldr r3, [r7, #48] ; 0x30
8003956: 4a0c ldr r2, [pc, #48] ; (8003988 <prvInitialiseNewTask+0x144>)
8003958: 65da str r2, [r3, #92] ; 0x5c
800395a: 6b3b ldr r3, [r7, #48] ; 0x30
800395c: 4a0b ldr r2, [pc, #44] ; (800398c <prvInitialiseNewTask+0x148>)
800395e: 661a str r2, [r3, #96] ; 0x60
}
#endif /* portSTACK_GROWTH */
}
#else /* portHAS_STACK_OVERFLOW_CHECKING */
{
pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
8003960: 683a ldr r2, [r7, #0]
8003962: 68f9 ldr r1, [r7, #12]
8003964: 69b8 ldr r0, [r7, #24]
8003966: f001 f941 bl 8004bec <pxPortInitialiseStack>
800396a: 4602 mov r2, r0
800396c: 6b3b ldr r3, [r7, #48] ; 0x30
800396e: 601a str r2, [r3, #0]
}
#endif /* portHAS_STACK_OVERFLOW_CHECKING */
}
#endif /* portUSING_MPU_WRAPPERS */
if( pxCreatedTask != NULL )
8003970: 6afb ldr r3, [r7, #44] ; 0x2c
8003972: 2b00 cmp r3, #0
8003974: d002 beq.n 800397c <prvInitialiseNewTask+0x138>
{
/* Pass the handle out in an anonymous way. The handle can be used to
change the created task's priority, delete the created task, etc.*/
*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
8003976: 6afb ldr r3, [r7, #44] ; 0x2c
8003978: 6b3a ldr r2, [r7, #48] ; 0x30
800397a: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
800397c: bf00 nop
800397e: 3720 adds r7, #32
8003980: 46bd mov sp, r7
8003982: bd80 pop {r7, pc}
8003984: 20004b14 .word 0x20004b14
8003988: 20004b7c .word 0x20004b7c
800398c: 20004be4 .word 0x20004be4
08003990 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/
static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
8003990: b580 push {r7, lr}
8003992: b082 sub sp, #8
8003994: af00 add r7, sp, #0
8003996: 6078 str r0, [r7, #4]
/* Ensure interrupts don't access the task lists while the lists are being
updated. */
taskENTER_CRITICAL();
8003998: f001 fa54 bl 8004e44 <vPortEnterCritical>
{
uxCurrentNumberOfTasks++;
800399c: 4b2d ldr r3, [pc, #180] ; (8003a54 <prvAddNewTaskToReadyList+0xc4>)
800399e: 681b ldr r3, [r3, #0]
80039a0: 3301 adds r3, #1
80039a2: 4a2c ldr r2, [pc, #176] ; (8003a54 <prvAddNewTaskToReadyList+0xc4>)
80039a4: 6013 str r3, [r2, #0]
if( pxCurrentTCB == NULL )
80039a6: 4b2c ldr r3, [pc, #176] ; (8003a58 <prvAddNewTaskToReadyList+0xc8>)
80039a8: 681b ldr r3, [r3, #0]
80039aa: 2b00 cmp r3, #0
80039ac: d109 bne.n 80039c2 <prvAddNewTaskToReadyList+0x32>
{
/* There are no other tasks, or all the other tasks are in
the suspended state - make this the current task. */
pxCurrentTCB = pxNewTCB;
80039ae: 4a2a ldr r2, [pc, #168] ; (8003a58 <prvAddNewTaskToReadyList+0xc8>)
80039b0: 687b ldr r3, [r7, #4]
80039b2: 6013 str r3, [r2, #0]
if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
80039b4: 4b27 ldr r3, [pc, #156] ; (8003a54 <prvAddNewTaskToReadyList+0xc4>)
80039b6: 681b ldr r3, [r3, #0]
80039b8: 2b01 cmp r3, #1
80039ba: d110 bne.n 80039de <prvAddNewTaskToReadyList+0x4e>
{
/* This is the first task to be created so do the preliminary
initialisation required. We will not recover if this call
fails, but we will report the failure. */
prvInitialiseTaskLists();
80039bc: f000 fc26 bl 800420c <prvInitialiseTaskLists>
80039c0: e00d b.n 80039de <prvAddNewTaskToReadyList+0x4e>
else
{
/* If the scheduler is not already running, make this task the
current task if it is the highest priority task to be created
so far. */
if( xSchedulerRunning == pdFALSE )
80039c2: 4b26 ldr r3, [pc, #152] ; (8003a5c <prvAddNewTaskToReadyList+0xcc>)
80039c4: 681b ldr r3, [r3, #0]
80039c6: 2b00 cmp r3, #0
80039c8: d109 bne.n 80039de <prvAddNewTaskToReadyList+0x4e>
{
if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
80039ca: 4b23 ldr r3, [pc, #140] ; (8003a58 <prvAddNewTaskToReadyList+0xc8>)
80039cc: 681b ldr r3, [r3, #0]
80039ce: 6ada ldr r2, [r3, #44] ; 0x2c
80039d0: 687b ldr r3, [r7, #4]
80039d2: 6adb ldr r3, [r3, #44] ; 0x2c
80039d4: 429a cmp r2, r3
80039d6: d802 bhi.n 80039de <prvAddNewTaskToReadyList+0x4e>
{
pxCurrentTCB = pxNewTCB;
80039d8: 4a1f ldr r2, [pc, #124] ; (8003a58 <prvAddNewTaskToReadyList+0xc8>)
80039da: 687b ldr r3, [r7, #4]
80039dc: 6013 str r3, [r2, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
uxTaskNumber++;
80039de: 4b20 ldr r3, [pc, #128] ; (8003a60 <prvAddNewTaskToReadyList+0xd0>)
80039e0: 681b ldr r3, [r3, #0]
80039e2: 3301 adds r3, #1
80039e4: 4a1e ldr r2, [pc, #120] ; (8003a60 <prvAddNewTaskToReadyList+0xd0>)
80039e6: 6013 str r3, [r2, #0]
#if ( configUSE_TRACE_FACILITY == 1 )
{
/* Add a counter into the TCB for tracing only. */
pxNewTCB->uxTCBNumber = uxTaskNumber;
80039e8: 4b1d ldr r3, [pc, #116] ; (8003a60 <prvAddNewTaskToReadyList+0xd0>)
80039ea: 681a ldr r2, [r3, #0]
80039ec: 687b ldr r3, [r7, #4]
80039ee: 645a str r2, [r3, #68] ; 0x44
}
#endif /* configUSE_TRACE_FACILITY */
traceTASK_CREATE( pxNewTCB );
prvAddTaskToReadyList( pxNewTCB );
80039f0: 687b ldr r3, [r7, #4]
80039f2: 6ada ldr r2, [r3, #44] ; 0x2c
80039f4: 4b1b ldr r3, [pc, #108] ; (8003a64 <prvAddNewTaskToReadyList+0xd4>)
80039f6: 681b ldr r3, [r3, #0]
80039f8: 429a cmp r2, r3
80039fa: d903 bls.n 8003a04 <prvAddNewTaskToReadyList+0x74>
80039fc: 687b ldr r3, [r7, #4]
80039fe: 6adb ldr r3, [r3, #44] ; 0x2c
8003a00: 4a18 ldr r2, [pc, #96] ; (8003a64 <prvAddNewTaskToReadyList+0xd4>)
8003a02: 6013 str r3, [r2, #0]
8003a04: 687b ldr r3, [r7, #4]
8003a06: 6ada ldr r2, [r3, #44] ; 0x2c
8003a08: 4613 mov r3, r2
8003a0a: 009b lsls r3, r3, #2
8003a0c: 4413 add r3, r2
8003a0e: 009b lsls r3, r3, #2
8003a10: 4a15 ldr r2, [pc, #84] ; (8003a68 <prvAddNewTaskToReadyList+0xd8>)
8003a12: 441a add r2, r3
8003a14: 687b ldr r3, [r7, #4]
8003a16: 3304 adds r3, #4
8003a18: 4619 mov r1, r3
8003a1a: 4610 mov r0, r2
8003a1c: f7ff f8fd bl 8002c1a <vListInsertEnd>
portSETUP_TCB( pxNewTCB );
}
taskEXIT_CRITICAL();
8003a20: f001 fa40 bl 8004ea4 <vPortExitCritical>
if( xSchedulerRunning != pdFALSE )
8003a24: 4b0d ldr r3, [pc, #52] ; (8003a5c <prvAddNewTaskToReadyList+0xcc>)
8003a26: 681b ldr r3, [r3, #0]
8003a28: 2b00 cmp r3, #0
8003a2a: d00e beq.n 8003a4a <prvAddNewTaskToReadyList+0xba>
{
/* If the created task is of a higher priority than the current task
then it should run now. */
if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
8003a2c: 4b0a ldr r3, [pc, #40] ; (8003a58 <prvAddNewTaskToReadyList+0xc8>)
8003a2e: 681b ldr r3, [r3, #0]
8003a30: 6ada ldr r2, [r3, #44] ; 0x2c
8003a32: 687b ldr r3, [r7, #4]
8003a34: 6adb ldr r3, [r3, #44] ; 0x2c
8003a36: 429a cmp r2, r3
8003a38: d207 bcs.n 8003a4a <prvAddNewTaskToReadyList+0xba>
{
taskYIELD_IF_USING_PREEMPTION();
8003a3a: 4b0c ldr r3, [pc, #48] ; (8003a6c <prvAddNewTaskToReadyList+0xdc>)
8003a3c: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003a40: 601a str r2, [r3, #0]
8003a42: f3bf 8f4f dsb sy
8003a46: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8003a4a: bf00 nop
8003a4c: 3708 adds r7, #8
8003a4e: 46bd mov sp, r7
8003a50: bd80 pop {r7, pc}
8003a52: bf00 nop
8003a54: 20000d94 .word 0x20000d94
8003a58: 200008c0 .word 0x200008c0
8003a5c: 20000da0 .word 0x20000da0
8003a60: 20000db0 .word 0x20000db0
8003a64: 20000d9c .word 0x20000d9c
8003a68: 200008c4 .word 0x200008c4
8003a6c: e000ed04 .word 0xe000ed04
08003a70 <vTaskDelay>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelay == 1 )
void vTaskDelay( const TickType_t xTicksToDelay )
{
8003a70: b580 push {r7, lr}
8003a72: b084 sub sp, #16
8003a74: af00 add r7, sp, #0
8003a76: 6078 str r0, [r7, #4]
BaseType_t xAlreadyYielded = pdFALSE;
8003a78: 2300 movs r3, #0
8003a7a: 60fb str r3, [r7, #12]
/* A delay time of zero just forces a reschedule. */
if( xTicksToDelay > ( TickType_t ) 0U )
8003a7c: 687b ldr r3, [r7, #4]
8003a7e: 2b00 cmp r3, #0
8003a80: d017 beq.n 8003ab2 <vTaskDelay+0x42>
{
configASSERT( uxSchedulerSuspended == 0 );
8003a82: 4b13 ldr r3, [pc, #76] ; (8003ad0 <vTaskDelay+0x60>)
8003a84: 681b ldr r3, [r3, #0]
8003a86: 2b00 cmp r3, #0
8003a88: d00a beq.n 8003aa0 <vTaskDelay+0x30>
__asm volatile
8003a8a: f04f 0350 mov.w r3, #80 ; 0x50
8003a8e: f383 8811 msr BASEPRI, r3
8003a92: f3bf 8f6f isb sy
8003a96: f3bf 8f4f dsb sy
8003a9a: 60bb str r3, [r7, #8]
}
8003a9c: bf00 nop
8003a9e: e7fe b.n 8003a9e <vTaskDelay+0x2e>
vTaskSuspendAll();
8003aa0: f000 f88a bl 8003bb8 <vTaskSuspendAll>
list or removed from the blocked list until the scheduler
is resumed.
This task cannot be in an event list as it is the currently
executing task. */
prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
8003aa4: 2100 movs r1, #0
8003aa6: 6878 ldr r0, [r7, #4]
8003aa8: f000 fcfe bl 80044a8 <prvAddCurrentTaskToDelayedList>
}
xAlreadyYielded = xTaskResumeAll();
8003aac: f000 f892 bl 8003bd4 <xTaskResumeAll>
8003ab0: 60f8 str r0, [r7, #12]
mtCOVERAGE_TEST_MARKER();
}
/* Force a reschedule if xTaskResumeAll has not already done so, we may
have put ourselves to sleep. */
if( xAlreadyYielded == pdFALSE )
8003ab2: 68fb ldr r3, [r7, #12]
8003ab4: 2b00 cmp r3, #0
8003ab6: d107 bne.n 8003ac8 <vTaskDelay+0x58>
{
portYIELD_WITHIN_API();
8003ab8: 4b06 ldr r3, [pc, #24] ; (8003ad4 <vTaskDelay+0x64>)
8003aba: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003abe: 601a str r2, [r3, #0]
8003ac0: f3bf 8f4f dsb sy
8003ac4: f3bf 8f6f isb sy
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8003ac8: bf00 nop
8003aca: 3710 adds r7, #16
8003acc: 46bd mov sp, r7
8003ace: bd80 pop {r7, pc}
8003ad0: 20000dbc .word 0x20000dbc
8003ad4: e000ed04 .word 0xe000ed04
08003ad8 <vTaskStartScheduler>:
#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/
void vTaskStartScheduler( void )
{
8003ad8: b580 push {r7, lr}
8003ada: b08a sub sp, #40 ; 0x28
8003adc: af04 add r7, sp, #16
BaseType_t xReturn;
/* Add the idle task at the lowest priority. */
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxIdleTaskTCBBuffer = NULL;
8003ade: 2300 movs r3, #0
8003ae0: 60bb str r3, [r7, #8]
StackType_t *pxIdleTaskStackBuffer = NULL;
8003ae2: 2300 movs r3, #0
8003ae4: 607b str r3, [r7, #4]
uint32_t ulIdleTaskStackSize;
/* The Idle task is created using user provided RAM - obtain the
address of the RAM then create the idle task. */
vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
8003ae6: 463a mov r2, r7
8003ae8: 1d39 adds r1, r7, #4
8003aea: f107 0308 add.w r3, r7, #8
8003aee: 4618 mov r0, r3
8003af0: f7ff f832 bl 8002b58 <vApplicationGetIdleTaskMemory>
xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
8003af4: 6839 ldr r1, [r7, #0]
8003af6: 687b ldr r3, [r7, #4]
8003af8: 68ba ldr r2, [r7, #8]
8003afa: 9202 str r2, [sp, #8]
8003afc: 9301 str r3, [sp, #4]
8003afe: 2300 movs r3, #0
8003b00: 9300 str r3, [sp, #0]
8003b02: 2300 movs r3, #0
8003b04: 460a mov r2, r1
8003b06: 4924 ldr r1, [pc, #144] ; (8003b98 <vTaskStartScheduler+0xc0>)
8003b08: 4824 ldr r0, [pc, #144] ; (8003b9c <vTaskStartScheduler+0xc4>)
8003b0a: f7ff fdf9 bl 8003700 <xTaskCreateStatic>
8003b0e: 4603 mov r3, r0
8003b10: 4a23 ldr r2, [pc, #140] ; (8003ba0 <vTaskStartScheduler+0xc8>)
8003b12: 6013 str r3, [r2, #0]
( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */
portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
pxIdleTaskStackBuffer,
pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
if( xIdleTaskHandle != NULL )
8003b14: 4b22 ldr r3, [pc, #136] ; (8003ba0 <vTaskStartScheduler+0xc8>)
8003b16: 681b ldr r3, [r3, #0]
8003b18: 2b00 cmp r3, #0
8003b1a: d002 beq.n 8003b22 <vTaskStartScheduler+0x4a>
{
xReturn = pdPASS;
8003b1c: 2301 movs r3, #1
8003b1e: 617b str r3, [r7, #20]
8003b20: e001 b.n 8003b26 <vTaskStartScheduler+0x4e>
}
else
{
xReturn = pdFAIL;
8003b22: 2300 movs r3, #0
8003b24: 617b str r3, [r7, #20]
}
#endif /* configSUPPORT_STATIC_ALLOCATION */
#if ( configUSE_TIMERS == 1 )
{
if( xReturn == pdPASS )
8003b26: 697b ldr r3, [r7, #20]
8003b28: 2b01 cmp r3, #1
8003b2a: d102 bne.n 8003b32 <vTaskStartScheduler+0x5a>
{
xReturn = xTimerCreateTimerTask();
8003b2c: f000 fd10 bl 8004550 <xTimerCreateTimerTask>
8003b30: 6178 str r0, [r7, #20]
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configUSE_TIMERS */
if( xReturn == pdPASS )
8003b32: 697b ldr r3, [r7, #20]
8003b34: 2b01 cmp r3, #1
8003b36: d11b bne.n 8003b70 <vTaskStartScheduler+0x98>
__asm volatile
8003b38: f04f 0350 mov.w r3, #80 ; 0x50
8003b3c: f383 8811 msr BASEPRI, r3
8003b40: f3bf 8f6f isb sy
8003b44: f3bf 8f4f dsb sy
8003b48: 613b str r3, [r7, #16]
}
8003b4a: bf00 nop
{
/* Switch Newlib's _impure_ptr variable to point to the _reent
structure specific to the task that will run first.
See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
for additional information. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
8003b4c: 4b15 ldr r3, [pc, #84] ; (8003ba4 <vTaskStartScheduler+0xcc>)
8003b4e: 681b ldr r3, [r3, #0]
8003b50: 3354 adds r3, #84 ; 0x54
8003b52: 4a15 ldr r2, [pc, #84] ; (8003ba8 <vTaskStartScheduler+0xd0>)
8003b54: 6013 str r3, [r2, #0]
}
#endif /* configUSE_NEWLIB_REENTRANT */
xNextTaskUnblockTime = portMAX_DELAY;
8003b56: 4b15 ldr r3, [pc, #84] ; (8003bac <vTaskStartScheduler+0xd4>)
8003b58: f04f 32ff mov.w r2, #4294967295
8003b5c: 601a str r2, [r3, #0]
xSchedulerRunning = pdTRUE;
8003b5e: 4b14 ldr r3, [pc, #80] ; (8003bb0 <vTaskStartScheduler+0xd8>)
8003b60: 2201 movs r2, #1
8003b62: 601a str r2, [r3, #0]
xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
8003b64: 4b13 ldr r3, [pc, #76] ; (8003bb4 <vTaskStartScheduler+0xdc>)
8003b66: 2200 movs r2, #0
8003b68: 601a str r2, [r3, #0]
traceTASK_SWITCHED_IN();
/* Setting up the timer tick is hardware specific and thus in the
portable interface. */
if( xPortStartScheduler() != pdFALSE )
8003b6a: f001 f8c9 bl 8004d00 <xPortStartScheduler>
}
/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
meaning xIdleTaskHandle is not used anywhere else. */
( void ) xIdleTaskHandle;
}
8003b6e: e00e b.n 8003b8e <vTaskStartScheduler+0xb6>
configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
8003b70: 697b ldr r3, [r7, #20]
8003b72: f1b3 3fff cmp.w r3, #4294967295
8003b76: d10a bne.n 8003b8e <vTaskStartScheduler+0xb6>
__asm volatile
8003b78: f04f 0350 mov.w r3, #80 ; 0x50
8003b7c: f383 8811 msr BASEPRI, r3
8003b80: f3bf 8f6f isb sy
8003b84: f3bf 8f4f dsb sy
8003b88: 60fb str r3, [r7, #12]
}
8003b8a: bf00 nop
8003b8c: e7fe b.n 8003b8c <vTaskStartScheduler+0xb4>
}
8003b8e: bf00 nop
8003b90: 3718 adds r7, #24
8003b92: 46bd mov sp, r7
8003b94: bd80 pop {r7, pc}
8003b96: bf00 nop
8003b98: 08005660 .word 0x08005660
8003b9c: 080041dd .word 0x080041dd
8003ba0: 20000db8 .word 0x20000db8
8003ba4: 200008c0 .word 0x200008c0
8003ba8: 2000005c .word 0x2000005c
8003bac: 20000db4 .word 0x20000db4
8003bb0: 20000da0 .word 0x20000da0
8003bb4: 20000d98 .word 0x20000d98
08003bb8 <vTaskSuspendAll>:
vPortEndScheduler();
}
/*----------------------------------------------------------*/
void vTaskSuspendAll( void )
{
8003bb8: b480 push {r7}
8003bba: af00 add r7, sp, #0
do not otherwise exhibit real time behaviour. */
portSOFTWARE_BARRIER();
/* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment
is used to allow calls to vTaskSuspendAll() to nest. */
++uxSchedulerSuspended;
8003bbc: 4b04 ldr r3, [pc, #16] ; (8003bd0 <vTaskSuspendAll+0x18>)
8003bbe: 681b ldr r3, [r3, #0]
8003bc0: 3301 adds r3, #1
8003bc2: 4a03 ldr r2, [pc, #12] ; (8003bd0 <vTaskSuspendAll+0x18>)
8003bc4: 6013 str r3, [r2, #0]
/* Enforces ordering for ports and optimised compilers that may otherwise place
the above increment elsewhere. */
portMEMORY_BARRIER();
}
8003bc6: bf00 nop
8003bc8: 46bd mov sp, r7
8003bca: f85d 7b04 ldr.w r7, [sp], #4
8003bce: 4770 bx lr
8003bd0: 20000dbc .word 0x20000dbc
08003bd4 <xTaskResumeAll>:
#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/
BaseType_t xTaskResumeAll( void )
{
8003bd4: b580 push {r7, lr}
8003bd6: b084 sub sp, #16
8003bd8: af00 add r7, sp, #0
TCB_t *pxTCB = NULL;
8003bda: 2300 movs r3, #0
8003bdc: 60fb str r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
8003bde: 2300 movs r3, #0
8003be0: 60bb str r3, [r7, #8]
/* If uxSchedulerSuspended is zero then this function does not match a
previous call to vTaskSuspendAll(). */
configASSERT( uxSchedulerSuspended );
8003be2: 4b42 ldr r3, [pc, #264] ; (8003cec <xTaskResumeAll+0x118>)
8003be4: 681b ldr r3, [r3, #0]
8003be6: 2b00 cmp r3, #0
8003be8: d10a bne.n 8003c00 <xTaskResumeAll+0x2c>
__asm volatile
8003bea: f04f 0350 mov.w r3, #80 ; 0x50
8003bee: f383 8811 msr BASEPRI, r3
8003bf2: f3bf 8f6f isb sy
8003bf6: f3bf 8f4f dsb sy
8003bfa: 603b str r3, [r7, #0]
}
8003bfc: bf00 nop
8003bfe: e7fe b.n 8003bfe <xTaskResumeAll+0x2a>
/* It is possible that an ISR caused a task to be removed from an event
list while the scheduler was suspended. If this was the case then the
removed task will have been added to the xPendingReadyList. Once the
scheduler has been resumed it is safe to move all the pending ready
tasks from this list into their appropriate ready list. */
taskENTER_CRITICAL();
8003c00: f001 f920 bl 8004e44 <vPortEnterCritical>
{
--uxSchedulerSuspended;
8003c04: 4b39 ldr r3, [pc, #228] ; (8003cec <xTaskResumeAll+0x118>)
8003c06: 681b ldr r3, [r3, #0]
8003c08: 3b01 subs r3, #1
8003c0a: 4a38 ldr r2, [pc, #224] ; (8003cec <xTaskResumeAll+0x118>)
8003c0c: 6013 str r3, [r2, #0]
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8003c0e: 4b37 ldr r3, [pc, #220] ; (8003cec <xTaskResumeAll+0x118>)
8003c10: 681b ldr r3, [r3, #0]
8003c12: 2b00 cmp r3, #0
8003c14: d162 bne.n 8003cdc <xTaskResumeAll+0x108>
{
if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
8003c16: 4b36 ldr r3, [pc, #216] ; (8003cf0 <xTaskResumeAll+0x11c>)
8003c18: 681b ldr r3, [r3, #0]
8003c1a: 2b00 cmp r3, #0
8003c1c: d05e beq.n 8003cdc <xTaskResumeAll+0x108>
{
/* Move any readied tasks from the pending list into the
appropriate ready list. */
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
8003c1e: e02f b.n 8003c80 <xTaskResumeAll+0xac>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8003c20: 4b34 ldr r3, [pc, #208] ; (8003cf4 <xTaskResumeAll+0x120>)
8003c22: 68db ldr r3, [r3, #12]
8003c24: 68db ldr r3, [r3, #12]
8003c26: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
8003c28: 68fb ldr r3, [r7, #12]
8003c2a: 3318 adds r3, #24
8003c2c: 4618 mov r0, r3
8003c2e: f7ff f851 bl 8002cd4 <uxListRemove>
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8003c32: 68fb ldr r3, [r7, #12]
8003c34: 3304 adds r3, #4
8003c36: 4618 mov r0, r3
8003c38: f7ff f84c bl 8002cd4 <uxListRemove>
prvAddTaskToReadyList( pxTCB );
8003c3c: 68fb ldr r3, [r7, #12]
8003c3e: 6ada ldr r2, [r3, #44] ; 0x2c
8003c40: 4b2d ldr r3, [pc, #180] ; (8003cf8 <xTaskResumeAll+0x124>)
8003c42: 681b ldr r3, [r3, #0]
8003c44: 429a cmp r2, r3
8003c46: d903 bls.n 8003c50 <xTaskResumeAll+0x7c>
8003c48: 68fb ldr r3, [r7, #12]
8003c4a: 6adb ldr r3, [r3, #44] ; 0x2c
8003c4c: 4a2a ldr r2, [pc, #168] ; (8003cf8 <xTaskResumeAll+0x124>)
8003c4e: 6013 str r3, [r2, #0]
8003c50: 68fb ldr r3, [r7, #12]
8003c52: 6ada ldr r2, [r3, #44] ; 0x2c
8003c54: 4613 mov r3, r2
8003c56: 009b lsls r3, r3, #2
8003c58: 4413 add r3, r2
8003c5a: 009b lsls r3, r3, #2
8003c5c: 4a27 ldr r2, [pc, #156] ; (8003cfc <xTaskResumeAll+0x128>)
8003c5e: 441a add r2, r3
8003c60: 68fb ldr r3, [r7, #12]
8003c62: 3304 adds r3, #4
8003c64: 4619 mov r1, r3
8003c66: 4610 mov r0, r2
8003c68: f7fe ffd7 bl 8002c1a <vListInsertEnd>
/* If the moved task has a priority higher than the current
task then a yield must be performed. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
8003c6c: 68fb ldr r3, [r7, #12]
8003c6e: 6ada ldr r2, [r3, #44] ; 0x2c
8003c70: 4b23 ldr r3, [pc, #140] ; (8003d00 <xTaskResumeAll+0x12c>)
8003c72: 681b ldr r3, [r3, #0]
8003c74: 6adb ldr r3, [r3, #44] ; 0x2c
8003c76: 429a cmp r2, r3
8003c78: d302 bcc.n 8003c80 <xTaskResumeAll+0xac>
{
xYieldPending = pdTRUE;
8003c7a: 4b22 ldr r3, [pc, #136] ; (8003d04 <xTaskResumeAll+0x130>)
8003c7c: 2201 movs r2, #1
8003c7e: 601a str r2, [r3, #0]
while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
8003c80: 4b1c ldr r3, [pc, #112] ; (8003cf4 <xTaskResumeAll+0x120>)
8003c82: 681b ldr r3, [r3, #0]
8003c84: 2b00 cmp r3, #0
8003c86: d1cb bne.n 8003c20 <xTaskResumeAll+0x4c>
{
mtCOVERAGE_TEST_MARKER();
}
}
if( pxTCB != NULL )
8003c88: 68fb ldr r3, [r7, #12]
8003c8a: 2b00 cmp r3, #0
8003c8c: d001 beq.n 8003c92 <xTaskResumeAll+0xbe>
which may have prevented the next unblock time from being
re-calculated, in which case re-calculate it now. Mainly
important for low power tickless implementations, where
this can prevent an unnecessary exit from low power
state. */
prvResetNextTaskUnblockTime();
8003c8e: f000 fb5f bl 8004350 <prvResetNextTaskUnblockTime>
/* If any ticks occurred while the scheduler was suspended then
they should be processed now. This ensures the tick count does
not slip, and that any delayed tasks are resumed at the correct
time. */
{
TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
8003c92: 4b1d ldr r3, [pc, #116] ; (8003d08 <xTaskResumeAll+0x134>)
8003c94: 681b ldr r3, [r3, #0]
8003c96: 607b str r3, [r7, #4]
if( xPendedCounts > ( TickType_t ) 0U )
8003c98: 687b ldr r3, [r7, #4]
8003c9a: 2b00 cmp r3, #0
8003c9c: d010 beq.n 8003cc0 <xTaskResumeAll+0xec>
{
do
{
if( xTaskIncrementTick() != pdFALSE )
8003c9e: f000 f847 bl 8003d30 <xTaskIncrementTick>
8003ca2: 4603 mov r3, r0
8003ca4: 2b00 cmp r3, #0
8003ca6: d002 beq.n 8003cae <xTaskResumeAll+0xda>
{
xYieldPending = pdTRUE;
8003ca8: 4b16 ldr r3, [pc, #88] ; (8003d04 <xTaskResumeAll+0x130>)
8003caa: 2201 movs r2, #1
8003cac: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
--xPendedCounts;
8003cae: 687b ldr r3, [r7, #4]
8003cb0: 3b01 subs r3, #1
8003cb2: 607b str r3, [r7, #4]
} while( xPendedCounts > ( TickType_t ) 0U );
8003cb4: 687b ldr r3, [r7, #4]
8003cb6: 2b00 cmp r3, #0
8003cb8: d1f1 bne.n 8003c9e <xTaskResumeAll+0xca>
xPendedTicks = 0;
8003cba: 4b13 ldr r3, [pc, #76] ; (8003d08 <xTaskResumeAll+0x134>)
8003cbc: 2200 movs r2, #0
8003cbe: 601a str r2, [r3, #0]
{
mtCOVERAGE_TEST_MARKER();
}
}
if( xYieldPending != pdFALSE )
8003cc0: 4b10 ldr r3, [pc, #64] ; (8003d04 <xTaskResumeAll+0x130>)
8003cc2: 681b ldr r3, [r3, #0]
8003cc4: 2b00 cmp r3, #0
8003cc6: d009 beq.n 8003cdc <xTaskResumeAll+0x108>
{
#if( configUSE_PREEMPTION != 0 )
{
xAlreadyYielded = pdTRUE;
8003cc8: 2301 movs r3, #1
8003cca: 60bb str r3, [r7, #8]
}
#endif
taskYIELD_IF_USING_PREEMPTION();
8003ccc: 4b0f ldr r3, [pc, #60] ; (8003d0c <xTaskResumeAll+0x138>)
8003cce: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8003cd2: 601a str r2, [r3, #0]
8003cd4: f3bf 8f4f dsb sy
8003cd8: f3bf 8f6f isb sy
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8003cdc: f001 f8e2 bl 8004ea4 <vPortExitCritical>
return xAlreadyYielded;
8003ce0: 68bb ldr r3, [r7, #8]
}
8003ce2: 4618 mov r0, r3
8003ce4: 3710 adds r7, #16
8003ce6: 46bd mov sp, r7
8003ce8: bd80 pop {r7, pc}
8003cea: bf00 nop
8003cec: 20000dbc .word 0x20000dbc
8003cf0: 20000d94 .word 0x20000d94
8003cf4: 20000d54 .word 0x20000d54
8003cf8: 20000d9c .word 0x20000d9c
8003cfc: 200008c4 .word 0x200008c4
8003d00: 200008c0 .word 0x200008c0
8003d04: 20000da8 .word 0x20000da8
8003d08: 20000da4 .word 0x20000da4
8003d0c: e000ed04 .word 0xe000ed04
08003d10 <xTaskGetTickCount>:
/*-----------------------------------------------------------*/
TickType_t xTaskGetTickCount( void )
{
8003d10: b480 push {r7}
8003d12: b083 sub sp, #12
8003d14: af00 add r7, sp, #0
TickType_t xTicks;
/* Critical section required if running on a 16 bit processor. */
portTICK_TYPE_ENTER_CRITICAL();
{
xTicks = xTickCount;
8003d16: 4b05 ldr r3, [pc, #20] ; (8003d2c <xTaskGetTickCount+0x1c>)
8003d18: 681b ldr r3, [r3, #0]
8003d1a: 607b str r3, [r7, #4]
}
portTICK_TYPE_EXIT_CRITICAL();
return xTicks;
8003d1c: 687b ldr r3, [r7, #4]
}
8003d1e: 4618 mov r0, r3
8003d20: 370c adds r7, #12
8003d22: 46bd mov sp, r7
8003d24: f85d 7b04 ldr.w r7, [sp], #4
8003d28: 4770 bx lr
8003d2a: bf00 nop
8003d2c: 20000d98 .word 0x20000d98
08003d30 <xTaskIncrementTick>:
#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/
BaseType_t xTaskIncrementTick( void )
{
8003d30: b580 push {r7, lr}
8003d32: b086 sub sp, #24
8003d34: af00 add r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
8003d36: 2300 movs r3, #0
8003d38: 617b str r3, [r7, #20]
/* Called by the portable layer each time a tick interrupt occurs.
Increments the tick then checks to see if the new tick value will cause any
tasks to be unblocked. */
traceTASK_INCREMENT_TICK( xTickCount );
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8003d3a: 4b4f ldr r3, [pc, #316] ; (8003e78 <xTaskIncrementTick+0x148>)
8003d3c: 681b ldr r3, [r3, #0]
8003d3e: 2b00 cmp r3, #0
8003d40: f040 808f bne.w 8003e62 <xTaskIncrementTick+0x132>
{
/* Minor optimisation. The tick count cannot change in this
block. */
const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
8003d44: 4b4d ldr r3, [pc, #308] ; (8003e7c <xTaskIncrementTick+0x14c>)
8003d46: 681b ldr r3, [r3, #0]
8003d48: 3301 adds r3, #1
8003d4a: 613b str r3, [r7, #16]
/* Increment the RTOS tick, switching the delayed and overflowed
delayed lists if it wraps to 0. */
xTickCount = xConstTickCount;
8003d4c: 4a4b ldr r2, [pc, #300] ; (8003e7c <xTaskIncrementTick+0x14c>)
8003d4e: 693b ldr r3, [r7, #16]
8003d50: 6013 str r3, [r2, #0]
if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
8003d52: 693b ldr r3, [r7, #16]
8003d54: 2b00 cmp r3, #0
8003d56: d120 bne.n 8003d9a <xTaskIncrementTick+0x6a>
{
taskSWITCH_DELAYED_LISTS();
8003d58: 4b49 ldr r3, [pc, #292] ; (8003e80 <xTaskIncrementTick+0x150>)
8003d5a: 681b ldr r3, [r3, #0]
8003d5c: 681b ldr r3, [r3, #0]
8003d5e: 2b00 cmp r3, #0
8003d60: d00a beq.n 8003d78 <xTaskIncrementTick+0x48>
__asm volatile
8003d62: f04f 0350 mov.w r3, #80 ; 0x50
8003d66: f383 8811 msr BASEPRI, r3
8003d6a: f3bf 8f6f isb sy
8003d6e: f3bf 8f4f dsb sy
8003d72: 603b str r3, [r7, #0]
}
8003d74: bf00 nop
8003d76: e7fe b.n 8003d76 <xTaskIncrementTick+0x46>
8003d78: 4b41 ldr r3, [pc, #260] ; (8003e80 <xTaskIncrementTick+0x150>)
8003d7a: 681b ldr r3, [r3, #0]
8003d7c: 60fb str r3, [r7, #12]
8003d7e: 4b41 ldr r3, [pc, #260] ; (8003e84 <xTaskIncrementTick+0x154>)
8003d80: 681b ldr r3, [r3, #0]
8003d82: 4a3f ldr r2, [pc, #252] ; (8003e80 <xTaskIncrementTick+0x150>)
8003d84: 6013 str r3, [r2, #0]
8003d86: 4a3f ldr r2, [pc, #252] ; (8003e84 <xTaskIncrementTick+0x154>)
8003d88: 68fb ldr r3, [r7, #12]
8003d8a: 6013 str r3, [r2, #0]
8003d8c: 4b3e ldr r3, [pc, #248] ; (8003e88 <xTaskIncrementTick+0x158>)
8003d8e: 681b ldr r3, [r3, #0]
8003d90: 3301 adds r3, #1
8003d92: 4a3d ldr r2, [pc, #244] ; (8003e88 <xTaskIncrementTick+0x158>)
8003d94: 6013 str r3, [r2, #0]
8003d96: f000 fadb bl 8004350 <prvResetNextTaskUnblockTime>
/* See if this tick has made a timeout expire. Tasks are stored in
the queue in the order of their wake time - meaning once one task
has been found whose block time has not expired there is no need to
look any further down the list. */
if( xConstTickCount >= xNextTaskUnblockTime )
8003d9a: 4b3c ldr r3, [pc, #240] ; (8003e8c <xTaskIncrementTick+0x15c>)
8003d9c: 681b ldr r3, [r3, #0]
8003d9e: 693a ldr r2, [r7, #16]
8003da0: 429a cmp r2, r3
8003da2: d349 bcc.n 8003e38 <xTaskIncrementTick+0x108>
{
for( ;; )
{
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8003da4: 4b36 ldr r3, [pc, #216] ; (8003e80 <xTaskIncrementTick+0x150>)
8003da6: 681b ldr r3, [r3, #0]
8003da8: 681b ldr r3, [r3, #0]
8003daa: 2b00 cmp r3, #0
8003dac: d104 bne.n 8003db8 <xTaskIncrementTick+0x88>
/* The delayed list is empty. Set xNextTaskUnblockTime
to the maximum possible value so it is extremely
unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass
next time through. */
xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8003dae: 4b37 ldr r3, [pc, #220] ; (8003e8c <xTaskIncrementTick+0x15c>)
8003db0: f04f 32ff mov.w r2, #4294967295
8003db4: 601a str r2, [r3, #0]
break;
8003db6: e03f b.n 8003e38 <xTaskIncrementTick+0x108>
{
/* The delayed list is not empty, get the value of the
item at the head of the delayed list. This is the time
at which the task at the head of the delayed list must
be removed from the Blocked state. */
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8003db8: 4b31 ldr r3, [pc, #196] ; (8003e80 <xTaskIncrementTick+0x150>)
8003dba: 681b ldr r3, [r3, #0]
8003dbc: 68db ldr r3, [r3, #12]
8003dbe: 68db ldr r3, [r3, #12]
8003dc0: 60bb str r3, [r7, #8]
xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
8003dc2: 68bb ldr r3, [r7, #8]
8003dc4: 685b ldr r3, [r3, #4]
8003dc6: 607b str r3, [r7, #4]
if( xConstTickCount < xItemValue )
8003dc8: 693a ldr r2, [r7, #16]
8003dca: 687b ldr r3, [r7, #4]
8003dcc: 429a cmp r2, r3
8003dce: d203 bcs.n 8003dd8 <xTaskIncrementTick+0xa8>
/* It is not time to unblock this item yet, but the
item value is the time at which the task at the head
of the blocked list must be removed from the Blocked
state - so record the item value in
xNextTaskUnblockTime. */
xNextTaskUnblockTime = xItemValue;
8003dd0: 4a2e ldr r2, [pc, #184] ; (8003e8c <xTaskIncrementTick+0x15c>)
8003dd2: 687b ldr r3, [r7, #4]
8003dd4: 6013 str r3, [r2, #0]
break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
8003dd6: e02f b.n 8003e38 <xTaskIncrementTick+0x108>
{
mtCOVERAGE_TEST_MARKER();
}
/* It is time to remove the item from the Blocked state. */
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
8003dd8: 68bb ldr r3, [r7, #8]
8003dda: 3304 adds r3, #4
8003ddc: 4618 mov r0, r3
8003dde: f7fe ff79 bl 8002cd4 <uxListRemove>
/* Is the task waiting on an event also? If so remove
it from the event list. */
if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
8003de2: 68bb ldr r3, [r7, #8]
8003de4: 6a9b ldr r3, [r3, #40] ; 0x28
8003de6: 2b00 cmp r3, #0
8003de8: d004 beq.n 8003df4 <xTaskIncrementTick+0xc4>
{
( void ) uxListRemove( &( pxTCB->xEventListItem ) );
8003dea: 68bb ldr r3, [r7, #8]
8003dec: 3318 adds r3, #24
8003dee: 4618 mov r0, r3
8003df0: f7fe ff70 bl 8002cd4 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
/* Place the unblocked task into the appropriate ready
list. */
prvAddTaskToReadyList( pxTCB );
8003df4: 68bb ldr r3, [r7, #8]
8003df6: 6ada ldr r2, [r3, #44] ; 0x2c
8003df8: 4b25 ldr r3, [pc, #148] ; (8003e90 <xTaskIncrementTick+0x160>)
8003dfa: 681b ldr r3, [r3, #0]
8003dfc: 429a cmp r2, r3
8003dfe: d903 bls.n 8003e08 <xTaskIncrementTick+0xd8>
8003e00: 68bb ldr r3, [r7, #8]
8003e02: 6adb ldr r3, [r3, #44] ; 0x2c
8003e04: 4a22 ldr r2, [pc, #136] ; (8003e90 <xTaskIncrementTick+0x160>)
8003e06: 6013 str r3, [r2, #0]
8003e08: 68bb ldr r3, [r7, #8]
8003e0a: 6ada ldr r2, [r3, #44] ; 0x2c
8003e0c: 4613 mov r3, r2
8003e0e: 009b lsls r3, r3, #2
8003e10: 4413 add r3, r2
8003e12: 009b lsls r3, r3, #2
8003e14: 4a1f ldr r2, [pc, #124] ; (8003e94 <xTaskIncrementTick+0x164>)
8003e16: 441a add r2, r3
8003e18: 68bb ldr r3, [r7, #8]
8003e1a: 3304 adds r3, #4
8003e1c: 4619 mov r1, r3
8003e1e: 4610 mov r0, r2
8003e20: f7fe fefb bl 8002c1a <vListInsertEnd>
{
/* Preemption is on, but a context switch should
only be performed if the unblocked task has a
priority that is equal to or higher than the
currently executing task. */
if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
8003e24: 68bb ldr r3, [r7, #8]
8003e26: 6ada ldr r2, [r3, #44] ; 0x2c
8003e28: 4b1b ldr r3, [pc, #108] ; (8003e98 <xTaskIncrementTick+0x168>)
8003e2a: 681b ldr r3, [r3, #0]
8003e2c: 6adb ldr r3, [r3, #44] ; 0x2c
8003e2e: 429a cmp r2, r3
8003e30: d3b8 bcc.n 8003da4 <xTaskIncrementTick+0x74>
{
xSwitchRequired = pdTRUE;
8003e32: 2301 movs r3, #1
8003e34: 617b str r3, [r7, #20]
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8003e36: e7b5 b.n 8003da4 <xTaskIncrementTick+0x74>
/* Tasks of equal priority to the currently running task will share
processing time (time slice) if preemption is on, and the application
writer has not explicitly turned time slicing off. */
#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
{
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
8003e38: 4b17 ldr r3, [pc, #92] ; (8003e98 <xTaskIncrementTick+0x168>)
8003e3a: 681b ldr r3, [r3, #0]
8003e3c: 6ada ldr r2, [r3, #44] ; 0x2c
8003e3e: 4915 ldr r1, [pc, #84] ; (8003e94 <xTaskIncrementTick+0x164>)
8003e40: 4613 mov r3, r2
8003e42: 009b lsls r3, r3, #2
8003e44: 4413 add r3, r2
8003e46: 009b lsls r3, r3, #2
8003e48: 440b add r3, r1
8003e4a: 681b ldr r3, [r3, #0]
8003e4c: 2b01 cmp r3, #1
8003e4e: d901 bls.n 8003e54 <xTaskIncrementTick+0x124>
{
xSwitchRequired = pdTRUE;
8003e50: 2301 movs r3, #1
8003e52: 617b str r3, [r7, #20]
}
#endif /* configUSE_TICK_HOOK */
#if ( configUSE_PREEMPTION == 1 )
{
if( xYieldPending != pdFALSE )
8003e54: 4b11 ldr r3, [pc, #68] ; (8003e9c <xTaskIncrementTick+0x16c>)
8003e56: 681b ldr r3, [r3, #0]
8003e58: 2b00 cmp r3, #0
8003e5a: d007 beq.n 8003e6c <xTaskIncrementTick+0x13c>
{
xSwitchRequired = pdTRUE;
8003e5c: 2301 movs r3, #1
8003e5e: 617b str r3, [r7, #20]
8003e60: e004 b.n 8003e6c <xTaskIncrementTick+0x13c>
}
#endif /* configUSE_PREEMPTION */
}
else
{
++xPendedTicks;
8003e62: 4b0f ldr r3, [pc, #60] ; (8003ea0 <xTaskIncrementTick+0x170>)
8003e64: 681b ldr r3, [r3, #0]
8003e66: 3301 adds r3, #1
8003e68: 4a0d ldr r2, [pc, #52] ; (8003ea0 <xTaskIncrementTick+0x170>)
8003e6a: 6013 str r3, [r2, #0]
vApplicationTickHook();
}
#endif
}
return xSwitchRequired;
8003e6c: 697b ldr r3, [r7, #20]
}
8003e6e: 4618 mov r0, r3
8003e70: 3718 adds r7, #24
8003e72: 46bd mov sp, r7
8003e74: bd80 pop {r7, pc}
8003e76: bf00 nop
8003e78: 20000dbc .word 0x20000dbc
8003e7c: 20000d98 .word 0x20000d98
8003e80: 20000d4c .word 0x20000d4c
8003e84: 20000d50 .word 0x20000d50
8003e88: 20000dac .word 0x20000dac
8003e8c: 20000db4 .word 0x20000db4
8003e90: 20000d9c .word 0x20000d9c
8003e94: 200008c4 .word 0x200008c4
8003e98: 200008c0 .word 0x200008c0
8003e9c: 20000da8 .word 0x20000da8
8003ea0: 20000da4 .word 0x20000da4
08003ea4 <vTaskSwitchContext>:
#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/
void vTaskSwitchContext( void )
{
8003ea4: b480 push {r7}
8003ea6: b085 sub sp, #20
8003ea8: af00 add r7, sp, #0
if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
8003eaa: 4b2a ldr r3, [pc, #168] ; (8003f54 <vTaskSwitchContext+0xb0>)
8003eac: 681b ldr r3, [r3, #0]
8003eae: 2b00 cmp r3, #0
8003eb0: d003 beq.n 8003eba <vTaskSwitchContext+0x16>
{
/* The scheduler is currently suspended - do not allow a context
switch. */
xYieldPending = pdTRUE;
8003eb2: 4b29 ldr r3, [pc, #164] ; (8003f58 <vTaskSwitchContext+0xb4>)
8003eb4: 2201 movs r2, #1
8003eb6: 601a str r2, [r3, #0]
for additional information. */
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
}
#endif /* configUSE_NEWLIB_REENTRANT */
}
}
8003eb8: e046 b.n 8003f48 <vTaskSwitchContext+0xa4>
xYieldPending = pdFALSE;
8003eba: 4b27 ldr r3, [pc, #156] ; (8003f58 <vTaskSwitchContext+0xb4>)
8003ebc: 2200 movs r2, #0
8003ebe: 601a str r2, [r3, #0]
taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8003ec0: 4b26 ldr r3, [pc, #152] ; (8003f5c <vTaskSwitchContext+0xb8>)
8003ec2: 681b ldr r3, [r3, #0]
8003ec4: 60fb str r3, [r7, #12]
8003ec6: e010 b.n 8003eea <vTaskSwitchContext+0x46>
8003ec8: 68fb ldr r3, [r7, #12]
8003eca: 2b00 cmp r3, #0
8003ecc: d10a bne.n 8003ee4 <vTaskSwitchContext+0x40>
__asm volatile
8003ece: f04f 0350 mov.w r3, #80 ; 0x50
8003ed2: f383 8811 msr BASEPRI, r3
8003ed6: f3bf 8f6f isb sy
8003eda: f3bf 8f4f dsb sy
8003ede: 607b str r3, [r7, #4]
}
8003ee0: bf00 nop
8003ee2: e7fe b.n 8003ee2 <vTaskSwitchContext+0x3e>
8003ee4: 68fb ldr r3, [r7, #12]
8003ee6: 3b01 subs r3, #1
8003ee8: 60fb str r3, [r7, #12]
8003eea: 491d ldr r1, [pc, #116] ; (8003f60 <vTaskSwitchContext+0xbc>)
8003eec: 68fa ldr r2, [r7, #12]
8003eee: 4613 mov r3, r2
8003ef0: 009b lsls r3, r3, #2
8003ef2: 4413 add r3, r2
8003ef4: 009b lsls r3, r3, #2
8003ef6: 440b add r3, r1
8003ef8: 681b ldr r3, [r3, #0]
8003efa: 2b00 cmp r3, #0
8003efc: d0e4 beq.n 8003ec8 <vTaskSwitchContext+0x24>
8003efe: 68fa ldr r2, [r7, #12]
8003f00: 4613 mov r3, r2
8003f02: 009b lsls r3, r3, #2
8003f04: 4413 add r3, r2
8003f06: 009b lsls r3, r3, #2
8003f08: 4a15 ldr r2, [pc, #84] ; (8003f60 <vTaskSwitchContext+0xbc>)
8003f0a: 4413 add r3, r2
8003f0c: 60bb str r3, [r7, #8]
8003f0e: 68bb ldr r3, [r7, #8]
8003f10: 685b ldr r3, [r3, #4]
8003f12: 685a ldr r2, [r3, #4]
8003f14: 68bb ldr r3, [r7, #8]
8003f16: 605a str r2, [r3, #4]
8003f18: 68bb ldr r3, [r7, #8]
8003f1a: 685a ldr r2, [r3, #4]
8003f1c: 68bb ldr r3, [r7, #8]
8003f1e: 3308 adds r3, #8
8003f20: 429a cmp r2, r3
8003f22: d104 bne.n 8003f2e <vTaskSwitchContext+0x8a>
8003f24: 68bb ldr r3, [r7, #8]
8003f26: 685b ldr r3, [r3, #4]
8003f28: 685a ldr r2, [r3, #4]
8003f2a: 68bb ldr r3, [r7, #8]
8003f2c: 605a str r2, [r3, #4]
8003f2e: 68bb ldr r3, [r7, #8]
8003f30: 685b ldr r3, [r3, #4]
8003f32: 68db ldr r3, [r3, #12]
8003f34: 4a0b ldr r2, [pc, #44] ; (8003f64 <vTaskSwitchContext+0xc0>)
8003f36: 6013 str r3, [r2, #0]
8003f38: 4a08 ldr r2, [pc, #32] ; (8003f5c <vTaskSwitchContext+0xb8>)
8003f3a: 68fb ldr r3, [r7, #12]
8003f3c: 6013 str r3, [r2, #0]
_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
8003f3e: 4b09 ldr r3, [pc, #36] ; (8003f64 <vTaskSwitchContext+0xc0>)
8003f40: 681b ldr r3, [r3, #0]
8003f42: 3354 adds r3, #84 ; 0x54
8003f44: 4a08 ldr r2, [pc, #32] ; (8003f68 <vTaskSwitchContext+0xc4>)
8003f46: 6013 str r3, [r2, #0]
}
8003f48: bf00 nop
8003f4a: 3714 adds r7, #20
8003f4c: 46bd mov sp, r7
8003f4e: f85d 7b04 ldr.w r7, [sp], #4
8003f52: 4770 bx lr
8003f54: 20000dbc .word 0x20000dbc
8003f58: 20000da8 .word 0x20000da8
8003f5c: 20000d9c .word 0x20000d9c
8003f60: 200008c4 .word 0x200008c4
8003f64: 200008c0 .word 0x200008c0
8003f68: 2000005c .word 0x2000005c
08003f6c <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/
void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
8003f6c: b580 push {r7, lr}
8003f6e: b084 sub sp, #16
8003f70: af00 add r7, sp, #0
8003f72: 6078 str r0, [r7, #4]
8003f74: 6039 str r1, [r7, #0]
configASSERT( pxEventList );
8003f76: 687b ldr r3, [r7, #4]
8003f78: 2b00 cmp r3, #0
8003f7a: d10a bne.n 8003f92 <vTaskPlaceOnEventList+0x26>
__asm volatile
8003f7c: f04f 0350 mov.w r3, #80 ; 0x50
8003f80: f383 8811 msr BASEPRI, r3
8003f84: f3bf 8f6f isb sy
8003f88: f3bf 8f4f dsb sy
8003f8c: 60fb str r3, [r7, #12]
}
8003f8e: bf00 nop
8003f90: e7fe b.n 8003f90 <vTaskPlaceOnEventList+0x24>
/* Place the event list item of the TCB in the appropriate event list.
This is placed in the list in priority order so the highest priority task
is the first to be woken by the event. The queue that contains the event
list is locked, preventing simultaneous access from interrupts. */
vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
8003f92: 4b07 ldr r3, [pc, #28] ; (8003fb0 <vTaskPlaceOnEventList+0x44>)
8003f94: 681b ldr r3, [r3, #0]
8003f96: 3318 adds r3, #24
8003f98: 4619 mov r1, r3
8003f9a: 6878 ldr r0, [r7, #4]
8003f9c: f7fe fe61 bl 8002c62 <vListInsert>
prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
8003fa0: 2101 movs r1, #1
8003fa2: 6838 ldr r0, [r7, #0]
8003fa4: f000 fa80 bl 80044a8 <prvAddCurrentTaskToDelayedList>
}
8003fa8: bf00 nop
8003faa: 3710 adds r7, #16
8003fac: 46bd mov sp, r7
8003fae: bd80 pop {r7, pc}
8003fb0: 200008c0 .word 0x200008c0
08003fb4 <vTaskPlaceOnEventListRestricted>:
/*-----------------------------------------------------------*/
#if( configUSE_TIMERS == 1 )
void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
{
8003fb4: b580 push {r7, lr}
8003fb6: b086 sub sp, #24
8003fb8: af00 add r7, sp, #0
8003fba: 60f8 str r0, [r7, #12]
8003fbc: 60b9 str r1, [r7, #8]
8003fbe: 607a str r2, [r7, #4]
configASSERT( pxEventList );
8003fc0: 68fb ldr r3, [r7, #12]
8003fc2: 2b00 cmp r3, #0
8003fc4: d10a bne.n 8003fdc <vTaskPlaceOnEventListRestricted+0x28>
__asm volatile
8003fc6: f04f 0350 mov.w r3, #80 ; 0x50
8003fca: f383 8811 msr BASEPRI, r3
8003fce: f3bf 8f6f isb sy
8003fd2: f3bf 8f4f dsb sy
8003fd6: 617b str r3, [r7, #20]
}
8003fd8: bf00 nop
8003fda: e7fe b.n 8003fda <vTaskPlaceOnEventListRestricted+0x26>
/* Place the event list item of the TCB in the appropriate event list.
In this case it is assume that this is the only task that is going to
be waiting on this event list, so the faster vListInsertEnd() function
can be used in place of vListInsert. */
vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
8003fdc: 4b0a ldr r3, [pc, #40] ; (8004008 <vTaskPlaceOnEventListRestricted+0x54>)
8003fde: 681b ldr r3, [r3, #0]
8003fe0: 3318 adds r3, #24
8003fe2: 4619 mov r1, r3
8003fe4: 68f8 ldr r0, [r7, #12]
8003fe6: f7fe fe18 bl 8002c1a <vListInsertEnd>
/* If the task should block indefinitely then set the block time to a
value that will be recognised as an indefinite delay inside the
prvAddCurrentTaskToDelayedList() function. */
if( xWaitIndefinitely != pdFALSE )
8003fea: 687b ldr r3, [r7, #4]
8003fec: 2b00 cmp r3, #0
8003fee: d002 beq.n 8003ff6 <vTaskPlaceOnEventListRestricted+0x42>
{
xTicksToWait = portMAX_DELAY;
8003ff0: f04f 33ff mov.w r3, #4294967295
8003ff4: 60bb str r3, [r7, #8]
}
traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
8003ff6: 6879 ldr r1, [r7, #4]
8003ff8: 68b8 ldr r0, [r7, #8]
8003ffa: f000 fa55 bl 80044a8 <prvAddCurrentTaskToDelayedList>
}
8003ffe: bf00 nop
8004000: 3718 adds r7, #24
8004002: 46bd mov sp, r7
8004004: bd80 pop {r7, pc}
8004006: bf00 nop
8004008: 200008c0 .word 0x200008c0
0800400c <xTaskRemoveFromEventList>:
#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/
BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
800400c: b580 push {r7, lr}
800400e: b086 sub sp, #24
8004010: af00 add r7, sp, #0
8004012: 6078 str r0, [r7, #4]
get called - the lock count on the queue will get modified instead. This
means exclusive access to the event list is guaranteed here.
This function assumes that a check has already been made to ensure that
pxEventList is not empty. */
pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8004014: 687b ldr r3, [r7, #4]
8004016: 68db ldr r3, [r3, #12]
8004018: 68db ldr r3, [r3, #12]
800401a: 613b str r3, [r7, #16]
configASSERT( pxUnblockedTCB );
800401c: 693b ldr r3, [r7, #16]
800401e: 2b00 cmp r3, #0
8004020: d10a bne.n 8004038 <xTaskRemoveFromEventList+0x2c>
__asm volatile
8004022: f04f 0350 mov.w r3, #80 ; 0x50
8004026: f383 8811 msr BASEPRI, r3
800402a: f3bf 8f6f isb sy
800402e: f3bf 8f4f dsb sy
8004032: 60fb str r3, [r7, #12]
}
8004034: bf00 nop
8004036: e7fe b.n 8004036 <xTaskRemoveFromEventList+0x2a>
( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
8004038: 693b ldr r3, [r7, #16]
800403a: 3318 adds r3, #24
800403c: 4618 mov r0, r3
800403e: f7fe fe49 bl 8002cd4 <uxListRemove>
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
8004042: 4b1e ldr r3, [pc, #120] ; (80040bc <xTaskRemoveFromEventList+0xb0>)
8004044: 681b ldr r3, [r3, #0]
8004046: 2b00 cmp r3, #0
8004048: d11d bne.n 8004086 <xTaskRemoveFromEventList+0x7a>
{
( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
800404a: 693b ldr r3, [r7, #16]
800404c: 3304 adds r3, #4
800404e: 4618 mov r0, r3
8004050: f7fe fe40 bl 8002cd4 <uxListRemove>
prvAddTaskToReadyList( pxUnblockedTCB );
8004054: 693b ldr r3, [r7, #16]
8004056: 6ada ldr r2, [r3, #44] ; 0x2c
8004058: 4b19 ldr r3, [pc, #100] ; (80040c0 <xTaskRemoveFromEventList+0xb4>)
800405a: 681b ldr r3, [r3, #0]
800405c: 429a cmp r2, r3
800405e: d903 bls.n 8004068 <xTaskRemoveFromEventList+0x5c>
8004060: 693b ldr r3, [r7, #16]
8004062: 6adb ldr r3, [r3, #44] ; 0x2c
8004064: 4a16 ldr r2, [pc, #88] ; (80040c0 <xTaskRemoveFromEventList+0xb4>)
8004066: 6013 str r3, [r2, #0]
8004068: 693b ldr r3, [r7, #16]
800406a: 6ada ldr r2, [r3, #44] ; 0x2c
800406c: 4613 mov r3, r2
800406e: 009b lsls r3, r3, #2
8004070: 4413 add r3, r2
8004072: 009b lsls r3, r3, #2
8004074: 4a13 ldr r2, [pc, #76] ; (80040c4 <xTaskRemoveFromEventList+0xb8>)
8004076: 441a add r2, r3
8004078: 693b ldr r3, [r7, #16]
800407a: 3304 adds r3, #4
800407c: 4619 mov r1, r3
800407e: 4610 mov r0, r2
8004080: f7fe fdcb bl 8002c1a <vListInsertEnd>
8004084: e005 b.n 8004092 <xTaskRemoveFromEventList+0x86>
}
else
{
/* The delayed and ready lists cannot be accessed, so hold this task
pending until the scheduler is resumed. */
vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
8004086: 693b ldr r3, [r7, #16]
8004088: 3318 adds r3, #24
800408a: 4619 mov r1, r3
800408c: 480e ldr r0, [pc, #56] ; (80040c8 <xTaskRemoveFromEventList+0xbc>)
800408e: f7fe fdc4 bl 8002c1a <vListInsertEnd>
}
if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
8004092: 693b ldr r3, [r7, #16]
8004094: 6ada ldr r2, [r3, #44] ; 0x2c
8004096: 4b0d ldr r3, [pc, #52] ; (80040cc <xTaskRemoveFromEventList+0xc0>)
8004098: 681b ldr r3, [r3, #0]
800409a: 6adb ldr r3, [r3, #44] ; 0x2c
800409c: 429a cmp r2, r3
800409e: d905 bls.n 80040ac <xTaskRemoveFromEventList+0xa0>
{
/* Return true if the task removed from the event list has a higher
priority than the calling task. This allows the calling task to know if
it should force a context switch now. */
xReturn = pdTRUE;
80040a0: 2301 movs r3, #1
80040a2: 617b str r3, [r7, #20]
/* Mark that a yield is pending in case the user is not using the
"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
xYieldPending = pdTRUE;
80040a4: 4b0a ldr r3, [pc, #40] ; (80040d0 <xTaskRemoveFromEventList+0xc4>)
80040a6: 2201 movs r2, #1
80040a8: 601a str r2, [r3, #0]
80040aa: e001 b.n 80040b0 <xTaskRemoveFromEventList+0xa4>
}
else
{
xReturn = pdFALSE;
80040ac: 2300 movs r3, #0
80040ae: 617b str r3, [r7, #20]
}
return xReturn;
80040b0: 697b ldr r3, [r7, #20]
}
80040b2: 4618 mov r0, r3
80040b4: 3718 adds r7, #24
80040b6: 46bd mov sp, r7
80040b8: bd80 pop {r7, pc}
80040ba: bf00 nop
80040bc: 20000dbc .word 0x20000dbc
80040c0: 20000d9c .word 0x20000d9c
80040c4: 200008c4 .word 0x200008c4
80040c8: 20000d54 .word 0x20000d54
80040cc: 200008c0 .word 0x200008c0
80040d0: 20000da8 .word 0x20000da8
080040d4 <vTaskInternalSetTimeOutState>:
taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/
void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
80040d4: b480 push {r7}
80040d6: b083 sub sp, #12
80040d8: af00 add r7, sp, #0
80040da: 6078 str r0, [r7, #4]
/* For internal use only as it does not use a critical section. */
pxTimeOut->xOverflowCount = xNumOfOverflows;
80040dc: 4b06 ldr r3, [pc, #24] ; (80040f8 <vTaskInternalSetTimeOutState+0x24>)
80040de: 681a ldr r2, [r3, #0]
80040e0: 687b ldr r3, [r7, #4]
80040e2: 601a str r2, [r3, #0]
pxTimeOut->xTimeOnEntering = xTickCount;
80040e4: 4b05 ldr r3, [pc, #20] ; (80040fc <vTaskInternalSetTimeOutState+0x28>)
80040e6: 681a ldr r2, [r3, #0]
80040e8: 687b ldr r3, [r7, #4]
80040ea: 605a str r2, [r3, #4]
}
80040ec: bf00 nop
80040ee: 370c adds r7, #12
80040f0: 46bd mov sp, r7
80040f2: f85d 7b04 ldr.w r7, [sp], #4
80040f6: 4770 bx lr
80040f8: 20000dac .word 0x20000dac
80040fc: 20000d98 .word 0x20000d98
08004100 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/
BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
8004100: b580 push {r7, lr}
8004102: b088 sub sp, #32
8004104: af00 add r7, sp, #0
8004106: 6078 str r0, [r7, #4]
8004108: 6039 str r1, [r7, #0]
BaseType_t xReturn;
configASSERT( pxTimeOut );
800410a: 687b ldr r3, [r7, #4]
800410c: 2b00 cmp r3, #0
800410e: d10a bne.n 8004126 <xTaskCheckForTimeOut+0x26>
__asm volatile
8004110: f04f 0350 mov.w r3, #80 ; 0x50
8004114: f383 8811 msr BASEPRI, r3
8004118: f3bf 8f6f isb sy
800411c: f3bf 8f4f dsb sy
8004120: 613b str r3, [r7, #16]
}
8004122: bf00 nop
8004124: e7fe b.n 8004124 <xTaskCheckForTimeOut+0x24>
configASSERT( pxTicksToWait );
8004126: 683b ldr r3, [r7, #0]
8004128: 2b00 cmp r3, #0
800412a: d10a bne.n 8004142 <xTaskCheckForTimeOut+0x42>
__asm volatile
800412c: f04f 0350 mov.w r3, #80 ; 0x50
8004130: f383 8811 msr BASEPRI, r3
8004134: f3bf 8f6f isb sy
8004138: f3bf 8f4f dsb sy
800413c: 60fb str r3, [r7, #12]
}
800413e: bf00 nop
8004140: e7fe b.n 8004140 <xTaskCheckForTimeOut+0x40>
taskENTER_CRITICAL();
8004142: f000 fe7f bl 8004e44 <vPortEnterCritical>
{
/* Minor optimisation. The tick count cannot change in this block. */
const TickType_t xConstTickCount = xTickCount;
8004146: 4b1d ldr r3, [pc, #116] ; (80041bc <xTaskCheckForTimeOut+0xbc>)
8004148: 681b ldr r3, [r3, #0]
800414a: 61bb str r3, [r7, #24]
const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
800414c: 687b ldr r3, [r7, #4]
800414e: 685b ldr r3, [r3, #4]
8004150: 69ba ldr r2, [r7, #24]
8004152: 1ad3 subs r3, r2, r3
8004154: 617b str r3, [r7, #20]
}
else
#endif
#if ( INCLUDE_vTaskSuspend == 1 )
if( *pxTicksToWait == portMAX_DELAY )
8004156: 683b ldr r3, [r7, #0]
8004158: 681b ldr r3, [r3, #0]
800415a: f1b3 3fff cmp.w r3, #4294967295
800415e: d102 bne.n 8004166 <xTaskCheckForTimeOut+0x66>
{
/* If INCLUDE_vTaskSuspend is set to 1 and the block time
specified is the maximum block time then the task should block
indefinitely, and therefore never time out. */
xReturn = pdFALSE;
8004160: 2300 movs r3, #0
8004162: 61fb str r3, [r7, #28]
8004164: e023 b.n 80041ae <xTaskCheckForTimeOut+0xae>
}
else
#endif
if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
8004166: 687b ldr r3, [r7, #4]
8004168: 681a ldr r2, [r3, #0]
800416a: 4b15 ldr r3, [pc, #84] ; (80041c0 <xTaskCheckForTimeOut+0xc0>)
800416c: 681b ldr r3, [r3, #0]
800416e: 429a cmp r2, r3
8004170: d007 beq.n 8004182 <xTaskCheckForTimeOut+0x82>
8004172: 687b ldr r3, [r7, #4]
8004174: 685b ldr r3, [r3, #4]
8004176: 69ba ldr r2, [r7, #24]
8004178: 429a cmp r2, r3
800417a: d302 bcc.n 8004182 <xTaskCheckForTimeOut+0x82>
/* The tick count is greater than the time at which
vTaskSetTimeout() was called, but has also overflowed since
vTaskSetTimeOut() was called. It must have wrapped all the way
around and gone past again. This passed since vTaskSetTimeout()
was called. */
xReturn = pdTRUE;
800417c: 2301 movs r3, #1
800417e: 61fb str r3, [r7, #28]
8004180: e015 b.n 80041ae <xTaskCheckForTimeOut+0xae>
}
else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
8004182: 683b ldr r3, [r7, #0]
8004184: 681b ldr r3, [r3, #0]
8004186: 697a ldr r2, [r7, #20]
8004188: 429a cmp r2, r3
800418a: d20b bcs.n 80041a4 <xTaskCheckForTimeOut+0xa4>
{
/* Not a genuine timeout. Adjust parameters for time remaining. */
*pxTicksToWait -= xElapsedTime;
800418c: 683b ldr r3, [r7, #0]
800418e: 681a ldr r2, [r3, #0]
8004190: 697b ldr r3, [r7, #20]
8004192: 1ad2 subs r2, r2, r3
8004194: 683b ldr r3, [r7, #0]
8004196: 601a str r2, [r3, #0]
vTaskInternalSetTimeOutState( pxTimeOut );
8004198: 6878 ldr r0, [r7, #4]
800419a: f7ff ff9b bl 80040d4 <vTaskInternalSetTimeOutState>
xReturn = pdFALSE;
800419e: 2300 movs r3, #0
80041a0: 61fb str r3, [r7, #28]
80041a2: e004 b.n 80041ae <xTaskCheckForTimeOut+0xae>
}
else
{
*pxTicksToWait = 0;
80041a4: 683b ldr r3, [r7, #0]
80041a6: 2200 movs r2, #0
80041a8: 601a str r2, [r3, #0]
xReturn = pdTRUE;
80041aa: 2301 movs r3, #1
80041ac: 61fb str r3, [r7, #28]
}
}
taskEXIT_CRITICAL();
80041ae: f000 fe79 bl 8004ea4 <vPortExitCritical>
return xReturn;
80041b2: 69fb ldr r3, [r7, #28]
}
80041b4: 4618 mov r0, r3
80041b6: 3720 adds r7, #32
80041b8: 46bd mov sp, r7
80041ba: bd80 pop {r7, pc}
80041bc: 20000d98 .word 0x20000d98
80041c0: 20000dac .word 0x20000dac
080041c4 <vTaskMissedYield>:
/*-----------------------------------------------------------*/
void vTaskMissedYield( void )
{
80041c4: b480 push {r7}
80041c6: af00 add r7, sp, #0
xYieldPending = pdTRUE;
80041c8: 4b03 ldr r3, [pc, #12] ; (80041d8 <vTaskMissedYield+0x14>)
80041ca: 2201 movs r2, #1
80041cc: 601a str r2, [r3, #0]
}
80041ce: bf00 nop
80041d0: 46bd mov sp, r7
80041d2: f85d 7b04 ldr.w r7, [sp], #4
80041d6: 4770 bx lr
80041d8: 20000da8 .word 0x20000da8
080041dc <prvIdleTask>:
*
* void prvIdleTask( void *pvParameters );
*
*/
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
80041dc: b580 push {r7, lr}
80041de: b082 sub sp, #8
80041e0: af00 add r7, sp, #0
80041e2: 6078 str r0, [r7, #4]
for( ;; )
{
/* See if any tasks have deleted themselves - if so then the idle task
is responsible for freeing the deleted task's TCB and stack. */
prvCheckTasksWaitingTermination();
80041e4: f000 f852 bl 800428c <prvCheckTasksWaitingTermination>
A critical region is not required here as we are just reading from
the list, and an occasional incorrect value will not matter. If
the ready list at the idle priority contains more than one task
then a task other than the idle task is ready to execute. */
if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
80041e8: 4b06 ldr r3, [pc, #24] ; (8004204 <prvIdleTask+0x28>)
80041ea: 681b ldr r3, [r3, #0]
80041ec: 2b01 cmp r3, #1
80041ee: d9f9 bls.n 80041e4 <prvIdleTask+0x8>
{
taskYIELD();
80041f0: 4b05 ldr r3, [pc, #20] ; (8004208 <prvIdleTask+0x2c>)
80041f2: f04f 5280 mov.w r2, #268435456 ; 0x10000000
80041f6: 601a str r2, [r3, #0]
80041f8: f3bf 8f4f dsb sy
80041fc: f3bf 8f6f isb sy
prvCheckTasksWaitingTermination();
8004200: e7f0 b.n 80041e4 <prvIdleTask+0x8>
8004202: bf00 nop
8004204: 200008c4 .word 0x200008c4
8004208: e000ed04 .word 0xe000ed04
0800420c <prvInitialiseTaskLists>:
#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/
static void prvInitialiseTaskLists( void )
{
800420c: b580 push {r7, lr}
800420e: b082 sub sp, #8
8004210: af00 add r7, sp, #0
UBaseType_t uxPriority;
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
8004212: 2300 movs r3, #0
8004214: 607b str r3, [r7, #4]
8004216: e00c b.n 8004232 <prvInitialiseTaskLists+0x26>
{
vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
8004218: 687a ldr r2, [r7, #4]
800421a: 4613 mov r3, r2
800421c: 009b lsls r3, r3, #2
800421e: 4413 add r3, r2
8004220: 009b lsls r3, r3, #2
8004222: 4a12 ldr r2, [pc, #72] ; (800426c <prvInitialiseTaskLists+0x60>)
8004224: 4413 add r3, r2
8004226: 4618 mov r0, r3
8004228: f7fe fcca bl 8002bc0 <vListInitialise>
for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
800422c: 687b ldr r3, [r7, #4]
800422e: 3301 adds r3, #1
8004230: 607b str r3, [r7, #4]
8004232: 687b ldr r3, [r7, #4]
8004234: 2b37 cmp r3, #55 ; 0x37
8004236: d9ef bls.n 8004218 <prvInitialiseTaskLists+0xc>
}
vListInitialise( &xDelayedTaskList1 );
8004238: 480d ldr r0, [pc, #52] ; (8004270 <prvInitialiseTaskLists+0x64>)
800423a: f7fe fcc1 bl 8002bc0 <vListInitialise>
vListInitialise( &xDelayedTaskList2 );
800423e: 480d ldr r0, [pc, #52] ; (8004274 <prvInitialiseTaskLists+0x68>)
8004240: f7fe fcbe bl 8002bc0 <vListInitialise>
vListInitialise( &xPendingReadyList );
8004244: 480c ldr r0, [pc, #48] ; (8004278 <prvInitialiseTaskLists+0x6c>)
8004246: f7fe fcbb bl 8002bc0 <vListInitialise>
#if ( INCLUDE_vTaskDelete == 1 )
{
vListInitialise( &xTasksWaitingTermination );
800424a: 480c ldr r0, [pc, #48] ; (800427c <prvInitialiseTaskLists+0x70>)
800424c: f7fe fcb8 bl 8002bc0 <vListInitialise>
}
#endif /* INCLUDE_vTaskDelete */
#if ( INCLUDE_vTaskSuspend == 1 )
{
vListInitialise( &xSuspendedTaskList );
8004250: 480b ldr r0, [pc, #44] ; (8004280 <prvInitialiseTaskLists+0x74>)
8004252: f7fe fcb5 bl 8002bc0 <vListInitialise>
}
#endif /* INCLUDE_vTaskSuspend */
/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
using list2. */
pxDelayedTaskList = &xDelayedTaskList1;
8004256: 4b0b ldr r3, [pc, #44] ; (8004284 <prvInitialiseTaskLists+0x78>)
8004258: 4a05 ldr r2, [pc, #20] ; (8004270 <prvInitialiseTaskLists+0x64>)
800425a: 601a str r2, [r3, #0]
pxOverflowDelayedTaskList = &xDelayedTaskList2;
800425c: 4b0a ldr r3, [pc, #40] ; (8004288 <prvInitialiseTaskLists+0x7c>)
800425e: 4a05 ldr r2, [pc, #20] ; (8004274 <prvInitialiseTaskLists+0x68>)
8004260: 601a str r2, [r3, #0]
}
8004262: bf00 nop
8004264: 3708 adds r7, #8
8004266: 46bd mov sp, r7
8004268: bd80 pop {r7, pc}
800426a: bf00 nop
800426c: 200008c4 .word 0x200008c4
8004270: 20000d24 .word 0x20000d24
8004274: 20000d38 .word 0x20000d38
8004278: 20000d54 .word 0x20000d54
800427c: 20000d68 .word 0x20000d68
8004280: 20000d80 .word 0x20000d80
8004284: 20000d4c .word 0x20000d4c
8004288: 20000d50 .word 0x20000d50
0800428c <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/
static void prvCheckTasksWaitingTermination( void )
{
800428c: b580 push {r7, lr}
800428e: b082 sub sp, #8
8004290: af00 add r7, sp, #0
{
TCB_t *pxTCB;
/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
being called too often in the idle task. */
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
8004292: e019 b.n 80042c8 <prvCheckTasksWaitingTermination+0x3c>
{
taskENTER_CRITICAL();
8004294: f000 fdd6 bl 8004e44 <vPortEnterCritical>
{
pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8004298: 4b10 ldr r3, [pc, #64] ; (80042dc <prvCheckTasksWaitingTermination+0x50>)
800429a: 68db ldr r3, [r3, #12]
800429c: 68db ldr r3, [r3, #12]
800429e: 607b str r3, [r7, #4]
( void ) uxListRemove( &( pxTCB->xStateListItem ) );
80042a0: 687b ldr r3, [r7, #4]
80042a2: 3304 adds r3, #4
80042a4: 4618 mov r0, r3
80042a6: f7fe fd15 bl 8002cd4 <uxListRemove>
--uxCurrentNumberOfTasks;
80042aa: 4b0d ldr r3, [pc, #52] ; (80042e0 <prvCheckTasksWaitingTermination+0x54>)
80042ac: 681b ldr r3, [r3, #0]
80042ae: 3b01 subs r3, #1
80042b0: 4a0b ldr r2, [pc, #44] ; (80042e0 <prvCheckTasksWaitingTermination+0x54>)
80042b2: 6013 str r3, [r2, #0]
--uxDeletedTasksWaitingCleanUp;
80042b4: 4b0b ldr r3, [pc, #44] ; (80042e4 <prvCheckTasksWaitingTermination+0x58>)
80042b6: 681b ldr r3, [r3, #0]
80042b8: 3b01 subs r3, #1
80042ba: 4a0a ldr r2, [pc, #40] ; (80042e4 <prvCheckTasksWaitingTermination+0x58>)
80042bc: 6013 str r3, [r2, #0]
}
taskEXIT_CRITICAL();
80042be: f000 fdf1 bl 8004ea4 <vPortExitCritical>
prvDeleteTCB( pxTCB );
80042c2: 6878 ldr r0, [r7, #4]
80042c4: f000 f810 bl 80042e8 <prvDeleteTCB>
while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
80042c8: 4b06 ldr r3, [pc, #24] ; (80042e4 <prvCheckTasksWaitingTermination+0x58>)
80042ca: 681b ldr r3, [r3, #0]
80042cc: 2b00 cmp r3, #0
80042ce: d1e1 bne.n 8004294 <prvCheckTasksWaitingTermination+0x8>
}
}
#endif /* INCLUDE_vTaskDelete */
}
80042d0: bf00 nop
80042d2: bf00 nop
80042d4: 3708 adds r7, #8
80042d6: 46bd mov sp, r7
80042d8: bd80 pop {r7, pc}
80042da: bf00 nop
80042dc: 20000d68 .word 0x20000d68
80042e0: 20000d94 .word 0x20000d94
80042e4: 20000d7c .word 0x20000d7c
080042e8 <prvDeleteTCB>:
/*-----------------------------------------------------------*/
#if ( INCLUDE_vTaskDelete == 1 )
static void prvDeleteTCB( TCB_t *pxTCB )
{
80042e8: b580 push {r7, lr}
80042ea: b084 sub sp, #16
80042ec: af00 add r7, sp, #0
80042ee: 6078 str r0, [r7, #4]
to the task to free any memory allocated at the application level.
See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
for additional information. */
#if ( configUSE_NEWLIB_REENTRANT == 1 )
{
_reclaim_reent( &( pxTCB->xNewLib_reent ) );
80042f0: 687b ldr r3, [r7, #4]
80042f2: 3354 adds r3, #84 ; 0x54
80042f4: 4618 mov r0, r3
80042f6: f001 f8b9 bl 800546c <_reclaim_reent>
#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
{
/* The task could have been allocated statically or dynamically, so
check what was statically allocated before trying to free the
memory. */
if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
80042fa: 687b ldr r3, [r7, #4]
80042fc: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5
8004300: 2b00 cmp r3, #0
8004302: d108 bne.n 8004316 <prvDeleteTCB+0x2e>
{
/* Both the stack and TCB were allocated dynamically, so both
must be freed. */
vPortFree( pxTCB->pxStack );
8004304: 687b ldr r3, [r7, #4]
8004306: 6b1b ldr r3, [r3, #48] ; 0x30
8004308: 4618 mov r0, r3
800430a: f000 ff89 bl 8005220 <vPortFree>
vPortFree( pxTCB );
800430e: 6878 ldr r0, [r7, #4]
8004310: f000 ff86 bl 8005220 <vPortFree>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
mtCOVERAGE_TEST_MARKER();
}
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
}
8004314: e018 b.n 8004348 <prvDeleteTCB+0x60>
else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
8004316: 687b ldr r3, [r7, #4]
8004318: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5
800431c: 2b01 cmp r3, #1
800431e: d103 bne.n 8004328 <prvDeleteTCB+0x40>
vPortFree( pxTCB );
8004320: 6878 ldr r0, [r7, #4]
8004322: f000 ff7d bl 8005220 <vPortFree>
}
8004326: e00f b.n 8004348 <prvDeleteTCB+0x60>
configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
8004328: 687b ldr r3, [r7, #4]
800432a: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5
800432e: 2b02 cmp r3, #2
8004330: d00a beq.n 8004348 <prvDeleteTCB+0x60>
__asm volatile
8004332: f04f 0350 mov.w r3, #80 ; 0x50
8004336: f383 8811 msr BASEPRI, r3
800433a: f3bf 8f6f isb sy
800433e: f3bf 8f4f dsb sy
8004342: 60fb str r3, [r7, #12]
}
8004344: bf00 nop
8004346: e7fe b.n 8004346 <prvDeleteTCB+0x5e>
}
8004348: bf00 nop
800434a: 3710 adds r7, #16
800434c: 46bd mov sp, r7
800434e: bd80 pop {r7, pc}
08004350 <prvResetNextTaskUnblockTime>:
#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/
static void prvResetNextTaskUnblockTime( void )
{
8004350: b480 push {r7}
8004352: b083 sub sp, #12
8004354: af00 add r7, sp, #0
TCB_t *pxTCB;
if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
8004356: 4b0c ldr r3, [pc, #48] ; (8004388 <prvResetNextTaskUnblockTime+0x38>)
8004358: 681b ldr r3, [r3, #0]
800435a: 681b ldr r3, [r3, #0]
800435c: 2b00 cmp r3, #0
800435e: d104 bne.n 800436a <prvResetNextTaskUnblockTime+0x1a>
{
/* The new current delayed list is empty. Set xNextTaskUnblockTime to
the maximum possible value so it is extremely unlikely that the
if( xTickCount >= xNextTaskUnblockTime ) test will pass until
there is an item in the delayed list. */
xNextTaskUnblockTime = portMAX_DELAY;
8004360: 4b0a ldr r3, [pc, #40] ; (800438c <prvResetNextTaskUnblockTime+0x3c>)
8004362: f04f 32ff mov.w r2, #4294967295
8004366: 601a str r2, [r3, #0]
which the task at the head of the delayed list should be removed
from the Blocked state. */
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
}
}
8004368: e008 b.n 800437c <prvResetNextTaskUnblockTime+0x2c>
( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
800436a: 4b07 ldr r3, [pc, #28] ; (8004388 <prvResetNextTaskUnblockTime+0x38>)
800436c: 681b ldr r3, [r3, #0]
800436e: 68db ldr r3, [r3, #12]
8004370: 68db ldr r3, [r3, #12]
8004372: 607b str r3, [r7, #4]
xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
8004374: 687b ldr r3, [r7, #4]
8004376: 685b ldr r3, [r3, #4]
8004378: 4a04 ldr r2, [pc, #16] ; (800438c <prvResetNextTaskUnblockTime+0x3c>)
800437a: 6013 str r3, [r2, #0]
}
800437c: bf00 nop
800437e: 370c adds r7, #12
8004380: 46bd mov sp, r7
8004382: f85d 7b04 ldr.w r7, [sp], #4
8004386: 4770 bx lr
8004388: 20000d4c .word 0x20000d4c
800438c: 20000db4 .word 0x20000db4
08004390 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
BaseType_t xTaskGetSchedulerState( void )
{
8004390: b480 push {r7}
8004392: b083 sub sp, #12
8004394: af00 add r7, sp, #0
BaseType_t xReturn;
if( xSchedulerRunning == pdFALSE )
8004396: 4b0b ldr r3, [pc, #44] ; (80043c4 <xTaskGetSchedulerState+0x34>)
8004398: 681b ldr r3, [r3, #0]
800439a: 2b00 cmp r3, #0
800439c: d102 bne.n 80043a4 <xTaskGetSchedulerState+0x14>
{
xReturn = taskSCHEDULER_NOT_STARTED;
800439e: 2301 movs r3, #1
80043a0: 607b str r3, [r7, #4]
80043a2: e008 b.n 80043b6 <xTaskGetSchedulerState+0x26>
}
else
{
if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
80043a4: 4b08 ldr r3, [pc, #32] ; (80043c8 <xTaskGetSchedulerState+0x38>)
80043a6: 681b ldr r3, [r3, #0]
80043a8: 2b00 cmp r3, #0
80043aa: d102 bne.n 80043b2 <xTaskGetSchedulerState+0x22>
{
xReturn = taskSCHEDULER_RUNNING;
80043ac: 2302 movs r3, #2
80043ae: 607b str r3, [r7, #4]
80043b0: e001 b.n 80043b6 <xTaskGetSchedulerState+0x26>
}
else
{
xReturn = taskSCHEDULER_SUSPENDED;
80043b2: 2300 movs r3, #0
80043b4: 607b str r3, [r7, #4]
}
}
return xReturn;
80043b6: 687b ldr r3, [r7, #4]
}
80043b8: 4618 mov r0, r3
80043ba: 370c adds r7, #12
80043bc: 46bd mov sp, r7
80043be: f85d 7b04 ldr.w r7, [sp], #4
80043c2: 4770 bx lr
80043c4: 20000da0 .word 0x20000da0
80043c8: 20000dbc .word 0x20000dbc
080043cc <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/
#if ( configUSE_MUTEXES == 1 )
BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
{
80043cc: b580 push {r7, lr}
80043ce: b086 sub sp, #24
80043d0: af00 add r7, sp, #0
80043d2: 6078 str r0, [r7, #4]
TCB_t * const pxTCB = pxMutexHolder;
80043d4: 687b ldr r3, [r7, #4]
80043d6: 613b str r3, [r7, #16]
BaseType_t xReturn = pdFALSE;
80043d8: 2300 movs r3, #0
80043da: 617b str r3, [r7, #20]
if( pxMutexHolder != NULL )
80043dc: 687b ldr r3, [r7, #4]
80043de: 2b00 cmp r3, #0
80043e0: d056 beq.n 8004490 <xTaskPriorityDisinherit+0xc4>
{
/* A task can only have an inherited priority if it holds the mutex.
If the mutex is held by a task then it cannot be given from an
interrupt, and if a mutex is given by the holding task then it must
be the running state task. */
configASSERT( pxTCB == pxCurrentTCB );
80043e2: 4b2e ldr r3, [pc, #184] ; (800449c <xTaskPriorityDisinherit+0xd0>)
80043e4: 681b ldr r3, [r3, #0]
80043e6: 693a ldr r2, [r7, #16]
80043e8: 429a cmp r2, r3
80043ea: d00a beq.n 8004402 <xTaskPriorityDisinherit+0x36>
__asm volatile
80043ec: f04f 0350 mov.w r3, #80 ; 0x50
80043f0: f383 8811 msr BASEPRI, r3
80043f4: f3bf 8f6f isb sy
80043f8: f3bf 8f4f dsb sy
80043fc: 60fb str r3, [r7, #12]
}
80043fe: bf00 nop
8004400: e7fe b.n 8004400 <xTaskPriorityDisinherit+0x34>
configASSERT( pxTCB->uxMutexesHeld );
8004402: 693b ldr r3, [r7, #16]
8004404: 6d1b ldr r3, [r3, #80] ; 0x50
8004406: 2b00 cmp r3, #0
8004408: d10a bne.n 8004420 <xTaskPriorityDisinherit+0x54>
__asm volatile
800440a: f04f 0350 mov.w r3, #80 ; 0x50
800440e: f383 8811 msr BASEPRI, r3
8004412: f3bf 8f6f isb sy
8004416: f3bf 8f4f dsb sy
800441a: 60bb str r3, [r7, #8]
}
800441c: bf00 nop
800441e: e7fe b.n 800441e <xTaskPriorityDisinherit+0x52>
( pxTCB->uxMutexesHeld )--;
8004420: 693b ldr r3, [r7, #16]
8004422: 6d1b ldr r3, [r3, #80] ; 0x50
8004424: 1e5a subs r2, r3, #1
8004426: 693b ldr r3, [r7, #16]
8004428: 651a str r2, [r3, #80] ; 0x50
/* Has the holder of the mutex inherited the priority of another
task? */
if( pxTCB->uxPriority != pxTCB->uxBasePriority )
800442a: 693b ldr r3, [r7, #16]
800442c: 6ada ldr r2, [r3, #44] ; 0x2c
800442e: 693b ldr r3, [r7, #16]
8004430: 6cdb ldr r3, [r3, #76] ; 0x4c
8004432: 429a cmp r2, r3
8004434: d02c beq.n 8004490 <xTaskPriorityDisinherit+0xc4>
{
/* Only disinherit if no other mutexes are held. */
if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
8004436: 693b ldr r3, [r7, #16]
8004438: 6d1b ldr r3, [r3, #80] ; 0x50
800443a: 2b00 cmp r3, #0
800443c: d128 bne.n 8004490 <xTaskPriorityDisinherit+0xc4>
/* A task can only have an inherited priority if it holds
the mutex. If the mutex is held by a task then it cannot be
given from an interrupt, and if a mutex is given by the
holding task then it must be the running state task. Remove
the holding task from the ready/delayed list. */
if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
800443e: 693b ldr r3, [r7, #16]
8004440: 3304 adds r3, #4
8004442: 4618 mov r0, r3
8004444: f7fe fc46 bl 8002cd4 <uxListRemove>
}
/* Disinherit the priority before adding the task into the
new ready list. */
traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
pxTCB->uxPriority = pxTCB->uxBasePriority;
8004448: 693b ldr r3, [r7, #16]
800444a: 6cda ldr r2, [r3, #76] ; 0x4c
800444c: 693b ldr r3, [r7, #16]
800444e: 62da str r2, [r3, #44] ; 0x2c
/* Reset the event list item value. It cannot be in use for
any other purpose if this task is running, and it must be
running to give back the mutex. */
listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8004450: 693b ldr r3, [r7, #16]
8004452: 6adb ldr r3, [r3, #44] ; 0x2c
8004454: f1c3 0238 rsb r2, r3, #56 ; 0x38
8004458: 693b ldr r3, [r7, #16]
800445a: 619a str r2, [r3, #24]
prvAddTaskToReadyList( pxTCB );
800445c: 693b ldr r3, [r7, #16]
800445e: 6ada ldr r2, [r3, #44] ; 0x2c
8004460: 4b0f ldr r3, [pc, #60] ; (80044a0 <xTaskPriorityDisinherit+0xd4>)
8004462: 681b ldr r3, [r3, #0]
8004464: 429a cmp r2, r3
8004466: d903 bls.n 8004470 <xTaskPriorityDisinherit+0xa4>
8004468: 693b ldr r3, [r7, #16]
800446a: 6adb ldr r3, [r3, #44] ; 0x2c
800446c: 4a0c ldr r2, [pc, #48] ; (80044a0 <xTaskPriorityDisinherit+0xd4>)
800446e: 6013 str r3, [r2, #0]
8004470: 693b ldr r3, [r7, #16]
8004472: 6ada ldr r2, [r3, #44] ; 0x2c
8004474: 4613 mov r3, r2
8004476: 009b lsls r3, r3, #2
8004478: 4413 add r3, r2
800447a: 009b lsls r3, r3, #2
800447c: 4a09 ldr r2, [pc, #36] ; (80044a4 <xTaskPriorityDisinherit+0xd8>)
800447e: 441a add r2, r3
8004480: 693b ldr r3, [r7, #16]
8004482: 3304 adds r3, #4
8004484: 4619 mov r1, r3
8004486: 4610 mov r0, r2
8004488: f7fe fbc7 bl 8002c1a <vListInsertEnd>
in an order different to that in which they were taken.
If a context switch did not occur when the first mutex was
returned, even if a task was waiting on it, then a context
switch should occur when the last mutex is returned whether
a task is waiting on it or not. */
xReturn = pdTRUE;
800448c: 2301 movs r3, #1
800448e: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
8004490: 697b ldr r3, [r7, #20]
}
8004492: 4618 mov r0, r3
8004494: 3718 adds r7, #24
8004496: 46bd mov sp, r7
8004498: bd80 pop {r7, pc}
800449a: bf00 nop
800449c: 200008c0 .word 0x200008c0
80044a0: 20000d9c .word 0x20000d9c
80044a4: 200008c4 .word 0x200008c4
080044a8 <prvAddCurrentTaskToDelayedList>:
#endif
/*-----------------------------------------------------------*/
static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
80044a8: b580 push {r7, lr}
80044aa: b084 sub sp, #16
80044ac: af00 add r7, sp, #0
80044ae: 6078 str r0, [r7, #4]
80044b0: 6039 str r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
80044b2: 4b21 ldr r3, [pc, #132] ; (8004538 <prvAddCurrentTaskToDelayedList+0x90>)
80044b4: 681b ldr r3, [r3, #0]
80044b6: 60fb str r3, [r7, #12]
}
#endif
/* Remove the task from the ready list before adding it to the blocked list
as the same list item is used for both lists. */
if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
80044b8: 4b20 ldr r3, [pc, #128] ; (800453c <prvAddCurrentTaskToDelayedList+0x94>)
80044ba: 681b ldr r3, [r3, #0]
80044bc: 3304 adds r3, #4
80044be: 4618 mov r0, r3
80044c0: f7fe fc08 bl 8002cd4 <uxListRemove>
mtCOVERAGE_TEST_MARKER();
}
#if ( INCLUDE_vTaskSuspend == 1 )
{
if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
80044c4: 687b ldr r3, [r7, #4]
80044c6: f1b3 3fff cmp.w r3, #4294967295
80044ca: d10a bne.n 80044e2 <prvAddCurrentTaskToDelayedList+0x3a>
80044cc: 683b ldr r3, [r7, #0]
80044ce: 2b00 cmp r3, #0
80044d0: d007 beq.n 80044e2 <prvAddCurrentTaskToDelayedList+0x3a>
{
/* Add the task to the suspended task list instead of a delayed task
list to ensure it is not woken by a timing event. It will block
indefinitely. */
vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
80044d2: 4b1a ldr r3, [pc, #104] ; (800453c <prvAddCurrentTaskToDelayedList+0x94>)
80044d4: 681b ldr r3, [r3, #0]
80044d6: 3304 adds r3, #4
80044d8: 4619 mov r1, r3
80044da: 4819 ldr r0, [pc, #100] ; (8004540 <prvAddCurrentTaskToDelayedList+0x98>)
80044dc: f7fe fb9d bl 8002c1a <vListInsertEnd>
/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
( void ) xCanBlockIndefinitely;
}
#endif /* INCLUDE_vTaskSuspend */
}
80044e0: e026 b.n 8004530 <prvAddCurrentTaskToDelayedList+0x88>
xTimeToWake = xConstTickCount + xTicksToWait;
80044e2: 68fa ldr r2, [r7, #12]
80044e4: 687b ldr r3, [r7, #4]
80044e6: 4413 add r3, r2
80044e8: 60bb str r3, [r7, #8]
listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
80044ea: 4b14 ldr r3, [pc, #80] ; (800453c <prvAddCurrentTaskToDelayedList+0x94>)
80044ec: 681b ldr r3, [r3, #0]
80044ee: 68ba ldr r2, [r7, #8]
80044f0: 605a str r2, [r3, #4]
if( xTimeToWake < xConstTickCount )
80044f2: 68ba ldr r2, [r7, #8]
80044f4: 68fb ldr r3, [r7, #12]
80044f6: 429a cmp r2, r3
80044f8: d209 bcs.n 800450e <prvAddCurrentTaskToDelayedList+0x66>
vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
80044fa: 4b12 ldr r3, [pc, #72] ; (8004544 <prvAddCurrentTaskToDelayedList+0x9c>)
80044fc: 681a ldr r2, [r3, #0]
80044fe: 4b0f ldr r3, [pc, #60] ; (800453c <prvAddCurrentTaskToDelayedList+0x94>)
8004500: 681b ldr r3, [r3, #0]
8004502: 3304 adds r3, #4
8004504: 4619 mov r1, r3
8004506: 4610 mov r0, r2
8004508: f7fe fbab bl 8002c62 <vListInsert>
}
800450c: e010 b.n 8004530 <prvAddCurrentTaskToDelayedList+0x88>
vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
800450e: 4b0e ldr r3, [pc, #56] ; (8004548 <prvAddCurrentTaskToDelayedList+0xa0>)
8004510: 681a ldr r2, [r3, #0]
8004512: 4b0a ldr r3, [pc, #40] ; (800453c <prvAddCurrentTaskToDelayedList+0x94>)
8004514: 681b ldr r3, [r3, #0]
8004516: 3304 adds r3, #4
8004518: 4619 mov r1, r3
800451a: 4610 mov r0, r2
800451c: f7fe fba1 bl 8002c62 <vListInsert>
if( xTimeToWake < xNextTaskUnblockTime )
8004520: 4b0a ldr r3, [pc, #40] ; (800454c <prvAddCurrentTaskToDelayedList+0xa4>)
8004522: 681b ldr r3, [r3, #0]
8004524: 68ba ldr r2, [r7, #8]
8004526: 429a cmp r2, r3
8004528: d202 bcs.n 8004530 <prvAddCurrentTaskToDelayedList+0x88>
xNextTaskUnblockTime = xTimeToWake;
800452a: 4a08 ldr r2, [pc, #32] ; (800454c <prvAddCurrentTaskToDelayedList+0xa4>)
800452c: 68bb ldr r3, [r7, #8]
800452e: 6013 str r3, [r2, #0]
}
8004530: bf00 nop
8004532: 3710 adds r7, #16
8004534: 46bd mov sp, r7
8004536: bd80 pop {r7, pc}
8004538: 20000d98 .word 0x20000d98
800453c: 200008c0 .word 0x200008c0
8004540: 20000d80 .word 0x20000d80
8004544: 20000d50 .word 0x20000d50
8004548: 20000d4c .word 0x20000d4c
800454c: 20000db4 .word 0x20000db4
08004550 <xTimerCreateTimerTask>:
TimerCallbackFunction_t pxCallbackFunction,
Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/
BaseType_t xTimerCreateTimerTask( void )
{
8004550: b580 push {r7, lr}
8004552: b08a sub sp, #40 ; 0x28
8004554: af04 add r7, sp, #16
BaseType_t xReturn = pdFAIL;
8004556: 2300 movs r3, #0
8004558: 617b str r3, [r7, #20]
/* This function is called when the scheduler is started if
configUSE_TIMERS is set to 1. Check that the infrastructure used by the
timer service task has been created/initialised. If timers have already
been created then the initialisation will already have been performed. */
prvCheckForValidListAndQueue();
800455a: f000 fb07 bl 8004b6c <prvCheckForValidListAndQueue>
if( xTimerQueue != NULL )
800455e: 4b1c ldr r3, [pc, #112] ; (80045d0 <xTimerCreateTimerTask+0x80>)
8004560: 681b ldr r3, [r3, #0]
8004562: 2b00 cmp r3, #0
8004564: d021 beq.n 80045aa <xTimerCreateTimerTask+0x5a>
{
#if( configSUPPORT_STATIC_ALLOCATION == 1 )
{
StaticTask_t *pxTimerTaskTCBBuffer = NULL;
8004566: 2300 movs r3, #0
8004568: 60fb str r3, [r7, #12]
StackType_t *pxTimerTaskStackBuffer = NULL;
800456a: 2300 movs r3, #0
800456c: 60bb str r3, [r7, #8]
uint32_t ulTimerTaskStackSize;
vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
800456e: 1d3a adds r2, r7, #4
8004570: f107 0108 add.w r1, r7, #8
8004574: f107 030c add.w r3, r7, #12
8004578: 4618 mov r0, r3
800457a: f7fe fb07 bl 8002b8c <vApplicationGetTimerTaskMemory>
xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
800457e: 6879 ldr r1, [r7, #4]
8004580: 68bb ldr r3, [r7, #8]
8004582: 68fa ldr r2, [r7, #12]
8004584: 9202 str r2, [sp, #8]
8004586: 9301 str r3, [sp, #4]
8004588: 2302 movs r3, #2
800458a: 9300 str r3, [sp, #0]
800458c: 2300 movs r3, #0
800458e: 460a mov r2, r1
8004590: 4910 ldr r1, [pc, #64] ; (80045d4 <xTimerCreateTimerTask+0x84>)
8004592: 4811 ldr r0, [pc, #68] ; (80045d8 <xTimerCreateTimerTask+0x88>)
8004594: f7ff f8b4 bl 8003700 <xTaskCreateStatic>
8004598: 4603 mov r3, r0
800459a: 4a10 ldr r2, [pc, #64] ; (80045dc <xTimerCreateTimerTask+0x8c>)
800459c: 6013 str r3, [r2, #0]
NULL,
( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
pxTimerTaskStackBuffer,
pxTimerTaskTCBBuffer );
if( xTimerTaskHandle != NULL )
800459e: 4b0f ldr r3, [pc, #60] ; (80045dc <xTimerCreateTimerTask+0x8c>)
80045a0: 681b ldr r3, [r3, #0]
80045a2: 2b00 cmp r3, #0
80045a4: d001 beq.n 80045aa <xTimerCreateTimerTask+0x5a>
{
xReturn = pdPASS;
80045a6: 2301 movs r3, #1
80045a8: 617b str r3, [r7, #20]
else
{
mtCOVERAGE_TEST_MARKER();
}
configASSERT( xReturn );
80045aa: 697b ldr r3, [r7, #20]
80045ac: 2b00 cmp r3, #0
80045ae: d10a bne.n 80045c6 <xTimerCreateTimerTask+0x76>
__asm volatile
80045b0: f04f 0350 mov.w r3, #80 ; 0x50
80045b4: f383 8811 msr BASEPRI, r3
80045b8: f3bf 8f6f isb sy
80045bc: f3bf 8f4f dsb sy
80045c0: 613b str r3, [r7, #16]
}
80045c2: bf00 nop
80045c4: e7fe b.n 80045c4 <xTimerCreateTimerTask+0x74>
return xReturn;
80045c6: 697b ldr r3, [r7, #20]
}
80045c8: 4618 mov r0, r3
80045ca: 3718 adds r7, #24
80045cc: 46bd mov sp, r7
80045ce: bd80 pop {r7, pc}
80045d0: 20000df0 .word 0x20000df0
80045d4: 08005668 .word 0x08005668
80045d8: 08004715 .word 0x08004715
80045dc: 20000df4 .word 0x20000df4
080045e0 <xTimerGenericCommand>:
}
}
/*-----------------------------------------------------------*/
BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
{
80045e0: b580 push {r7, lr}
80045e2: b08a sub sp, #40 ; 0x28
80045e4: af00 add r7, sp, #0
80045e6: 60f8 str r0, [r7, #12]
80045e8: 60b9 str r1, [r7, #8]
80045ea: 607a str r2, [r7, #4]
80045ec: 603b str r3, [r7, #0]
BaseType_t xReturn = pdFAIL;
80045ee: 2300 movs r3, #0
80045f0: 627b str r3, [r7, #36] ; 0x24
DaemonTaskMessage_t xMessage;
configASSERT( xTimer );
80045f2: 68fb ldr r3, [r7, #12]
80045f4: 2b00 cmp r3, #0
80045f6: d10a bne.n 800460e <xTimerGenericCommand+0x2e>
__asm volatile
80045f8: f04f 0350 mov.w r3, #80 ; 0x50
80045fc: f383 8811 msr BASEPRI, r3
8004600: f3bf 8f6f isb sy
8004604: f3bf 8f4f dsb sy
8004608: 623b str r3, [r7, #32]
}
800460a: bf00 nop
800460c: e7fe b.n 800460c <xTimerGenericCommand+0x2c>
/* Send a message to the timer service task to perform a particular action
on a particular timer definition. */
if( xTimerQueue != NULL )
800460e: 4b1a ldr r3, [pc, #104] ; (8004678 <xTimerGenericCommand+0x98>)
8004610: 681b ldr r3, [r3, #0]
8004612: 2b00 cmp r3, #0
8004614: d02a beq.n 800466c <xTimerGenericCommand+0x8c>
{
/* Send a command to the timer service task to start the xTimer timer. */
xMessage.xMessageID = xCommandID;
8004616: 68bb ldr r3, [r7, #8]
8004618: 613b str r3, [r7, #16]
xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
800461a: 687b ldr r3, [r7, #4]
800461c: 617b str r3, [r7, #20]
xMessage.u.xTimerParameters.pxTimer = xTimer;
800461e: 68fb ldr r3, [r7, #12]
8004620: 61bb str r3, [r7, #24]
if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
8004622: 68bb ldr r3, [r7, #8]
8004624: 2b05 cmp r3, #5
8004626: dc18 bgt.n 800465a <xTimerGenericCommand+0x7a>
{
if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
8004628: f7ff feb2 bl 8004390 <xTaskGetSchedulerState>
800462c: 4603 mov r3, r0
800462e: 2b02 cmp r3, #2
8004630: d109 bne.n 8004646 <xTimerGenericCommand+0x66>
{
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
8004632: 4b11 ldr r3, [pc, #68] ; (8004678 <xTimerGenericCommand+0x98>)
8004634: 6818 ldr r0, [r3, #0]
8004636: f107 0110 add.w r1, r7, #16
800463a: 2300 movs r3, #0
800463c: 6b3a ldr r2, [r7, #48] ; 0x30
800463e: f7fe fc77 bl 8002f30 <xQueueGenericSend>
8004642: 6278 str r0, [r7, #36] ; 0x24
8004644: e012 b.n 800466c <xTimerGenericCommand+0x8c>
}
else
{
xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
8004646: 4b0c ldr r3, [pc, #48] ; (8004678 <xTimerGenericCommand+0x98>)
8004648: 6818 ldr r0, [r3, #0]
800464a: f107 0110 add.w r1, r7, #16
800464e: 2300 movs r3, #0
8004650: 2200 movs r2, #0
8004652: f7fe fc6d bl 8002f30 <xQueueGenericSend>
8004656: 6278 str r0, [r7, #36] ; 0x24
8004658: e008 b.n 800466c <xTimerGenericCommand+0x8c>
}
}
else
{
xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
800465a: 4b07 ldr r3, [pc, #28] ; (8004678 <xTimerGenericCommand+0x98>)
800465c: 6818 ldr r0, [r3, #0]
800465e: f107 0110 add.w r1, r7, #16
8004662: 2300 movs r3, #0
8004664: 683a ldr r2, [r7, #0]
8004666: f7fe fd61 bl 800312c <xQueueGenericSendFromISR>
800466a: 6278 str r0, [r7, #36] ; 0x24
else
{
mtCOVERAGE_TEST_MARKER();
}
return xReturn;
800466c: 6a7b ldr r3, [r7, #36] ; 0x24
}
800466e: 4618 mov r0, r3
8004670: 3728 adds r7, #40 ; 0x28
8004672: 46bd mov sp, r7
8004674: bd80 pop {r7, pc}
8004676: bf00 nop
8004678: 20000df0 .word 0x20000df0
0800467c <prvProcessExpiredTimer>:
return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/
static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
800467c: b580 push {r7, lr}
800467e: b088 sub sp, #32
8004680: af02 add r7, sp, #8
8004682: 6078 str r0, [r7, #4]
8004684: 6039 str r1, [r7, #0]
BaseType_t xResult;
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8004686: 4b22 ldr r3, [pc, #136] ; (8004710 <prvProcessExpiredTimer+0x94>)
8004688: 681b ldr r3, [r3, #0]
800468a: 68db ldr r3, [r3, #12]
800468c: 68db ldr r3, [r3, #12]
800468e: 617b str r3, [r7, #20]
/* Remove the timer from the list of active timers. A check has already
been performed to ensure the list is not empty. */
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8004690: 697b ldr r3, [r7, #20]
8004692: 3304 adds r3, #4
8004694: 4618 mov r0, r3
8004696: f7fe fb1d bl 8002cd4 <uxListRemove>
traceTIMER_EXPIRED( pxTimer );
/* If the timer is an auto-reload timer then calculate the next
expiry time and re-insert the timer in the list of active timers. */
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
800469a: 697b ldr r3, [r7, #20]
800469c: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
80046a0: f003 0304 and.w r3, r3, #4
80046a4: 2b00 cmp r3, #0
80046a6: d022 beq.n 80046ee <prvProcessExpiredTimer+0x72>
{
/* The timer is inserted into a list using a time relative to anything
other than the current time. It will therefore be inserted into the
correct list relative to the time this task thinks it is now. */
if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
80046a8: 697b ldr r3, [r7, #20]
80046aa: 699a ldr r2, [r3, #24]
80046ac: 687b ldr r3, [r7, #4]
80046ae: 18d1 adds r1, r2, r3
80046b0: 687b ldr r3, [r7, #4]
80046b2: 683a ldr r2, [r7, #0]
80046b4: 6978 ldr r0, [r7, #20]
80046b6: f000 f8d1 bl 800485c <prvInsertTimerInActiveList>
80046ba: 4603 mov r3, r0
80046bc: 2b00 cmp r3, #0
80046be: d01f beq.n 8004700 <prvProcessExpiredTimer+0x84>
{
/* The timer expired before it was added to the active timer
list. Reload it now. */
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
80046c0: 2300 movs r3, #0
80046c2: 9300 str r3, [sp, #0]
80046c4: 2300 movs r3, #0
80046c6: 687a ldr r2, [r7, #4]
80046c8: 2100 movs r1, #0
80046ca: 6978 ldr r0, [r7, #20]
80046cc: f7ff ff88 bl 80045e0 <xTimerGenericCommand>
80046d0: 6138 str r0, [r7, #16]
configASSERT( xResult );
80046d2: 693b ldr r3, [r7, #16]
80046d4: 2b00 cmp r3, #0
80046d6: d113 bne.n 8004700 <prvProcessExpiredTimer+0x84>
__asm volatile
80046d8: f04f 0350 mov.w r3, #80 ; 0x50
80046dc: f383 8811 msr BASEPRI, r3
80046e0: f3bf 8f6f isb sy
80046e4: f3bf 8f4f dsb sy
80046e8: 60fb str r3, [r7, #12]
}
80046ea: bf00 nop
80046ec: e7fe b.n 80046ec <prvProcessExpiredTimer+0x70>
mtCOVERAGE_TEST_MARKER();
}
}
else
{
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
80046ee: 697b ldr r3, [r7, #20]
80046f0: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
80046f4: f023 0301 bic.w r3, r3, #1
80046f8: b2da uxtb r2, r3
80046fa: 697b ldr r3, [r7, #20]
80046fc: f883 2028 strb.w r2, [r3, #40] ; 0x28
mtCOVERAGE_TEST_MARKER();
}
/* Call the timer callback. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
8004700: 697b ldr r3, [r7, #20]
8004702: 6a1b ldr r3, [r3, #32]
8004704: 6978 ldr r0, [r7, #20]
8004706: 4798 blx r3
}
8004708: bf00 nop
800470a: 3718 adds r7, #24
800470c: 46bd mov sp, r7
800470e: bd80 pop {r7, pc}
8004710: 20000de8 .word 0x20000de8
08004714 <prvTimerTask>:
/*-----------------------------------------------------------*/
static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
8004714: b580 push {r7, lr}
8004716: b084 sub sp, #16
8004718: af00 add r7, sp, #0
800471a: 6078 str r0, [r7, #4]
for( ;; )
{
/* Query the timers list to see if it contains any timers, and if so,
obtain the time at which the next timer will expire. */
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
800471c: f107 0308 add.w r3, r7, #8
8004720: 4618 mov r0, r3
8004722: f000 f857 bl 80047d4 <prvGetNextExpireTime>
8004726: 60f8 str r0, [r7, #12]
/* If a timer has expired, process it. Otherwise, block this task
until either a timer does expire, or a command is received. */
prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
8004728: 68bb ldr r3, [r7, #8]
800472a: 4619 mov r1, r3
800472c: 68f8 ldr r0, [r7, #12]
800472e: f000 f803 bl 8004738 <prvProcessTimerOrBlockTask>
/* Empty the command queue. */
prvProcessReceivedCommands();
8004732: f000 f8d5 bl 80048e0 <prvProcessReceivedCommands>
xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
8004736: e7f1 b.n 800471c <prvTimerTask+0x8>
08004738 <prvProcessTimerOrBlockTask>:
}
}
/*-----------------------------------------------------------*/
static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
8004738: b580 push {r7, lr}
800473a: b084 sub sp, #16
800473c: af00 add r7, sp, #0
800473e: 6078 str r0, [r7, #4]
8004740: 6039 str r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;
vTaskSuspendAll();
8004742: f7ff fa39 bl 8003bb8 <vTaskSuspendAll>
/* Obtain the time now to make an assessment as to whether the timer
has expired or not. If obtaining the time causes the lists to switch
then don't process this timer as any timers that remained in the list
when the lists were switched will have been processed within the
prvSampleTimeNow() function. */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
8004746: f107 0308 add.w r3, r7, #8
800474a: 4618 mov r0, r3
800474c: f000 f866 bl 800481c <prvSampleTimeNow>
8004750: 60f8 str r0, [r7, #12]
if( xTimerListsWereSwitched == pdFALSE )
8004752: 68bb ldr r3, [r7, #8]
8004754: 2b00 cmp r3, #0
8004756: d130 bne.n 80047ba <prvProcessTimerOrBlockTask+0x82>
{
/* The tick count has not overflowed, has the timer expired? */
if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
8004758: 683b ldr r3, [r7, #0]
800475a: 2b00 cmp r3, #0
800475c: d10a bne.n 8004774 <prvProcessTimerOrBlockTask+0x3c>
800475e: 687a ldr r2, [r7, #4]
8004760: 68fb ldr r3, [r7, #12]
8004762: 429a cmp r2, r3
8004764: d806 bhi.n 8004774 <prvProcessTimerOrBlockTask+0x3c>
{
( void ) xTaskResumeAll();
8004766: f7ff fa35 bl 8003bd4 <xTaskResumeAll>
prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
800476a: 68f9 ldr r1, [r7, #12]
800476c: 6878 ldr r0, [r7, #4]
800476e: f7ff ff85 bl 800467c <prvProcessExpiredTimer>
else
{
( void ) xTaskResumeAll();
}
}
}
8004772: e024 b.n 80047be <prvProcessTimerOrBlockTask+0x86>
if( xListWasEmpty != pdFALSE )
8004774: 683b ldr r3, [r7, #0]
8004776: 2b00 cmp r3, #0
8004778: d008 beq.n 800478c <prvProcessTimerOrBlockTask+0x54>
xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
800477a: 4b13 ldr r3, [pc, #76] ; (80047c8 <prvProcessTimerOrBlockTask+0x90>)
800477c: 681b ldr r3, [r3, #0]
800477e: 681b ldr r3, [r3, #0]
8004780: 2b00 cmp r3, #0
8004782: d101 bne.n 8004788 <prvProcessTimerOrBlockTask+0x50>
8004784: 2301 movs r3, #1
8004786: e000 b.n 800478a <prvProcessTimerOrBlockTask+0x52>
8004788: 2300 movs r3, #0
800478a: 603b str r3, [r7, #0]
vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
800478c: 4b0f ldr r3, [pc, #60] ; (80047cc <prvProcessTimerOrBlockTask+0x94>)
800478e: 6818 ldr r0, [r3, #0]
8004790: 687a ldr r2, [r7, #4]
8004792: 68fb ldr r3, [r7, #12]
8004794: 1ad3 subs r3, r2, r3
8004796: 683a ldr r2, [r7, #0]
8004798: 4619 mov r1, r3
800479a: f7fe ff7d bl 8003698 <vQueueWaitForMessageRestricted>
if( xTaskResumeAll() == pdFALSE )
800479e: f7ff fa19 bl 8003bd4 <xTaskResumeAll>
80047a2: 4603 mov r3, r0
80047a4: 2b00 cmp r3, #0
80047a6: d10a bne.n 80047be <prvProcessTimerOrBlockTask+0x86>
portYIELD_WITHIN_API();
80047a8: 4b09 ldr r3, [pc, #36] ; (80047d0 <prvProcessTimerOrBlockTask+0x98>)
80047aa: f04f 5280 mov.w r2, #268435456 ; 0x10000000
80047ae: 601a str r2, [r3, #0]
80047b0: f3bf 8f4f dsb sy
80047b4: f3bf 8f6f isb sy
}
80047b8: e001 b.n 80047be <prvProcessTimerOrBlockTask+0x86>
( void ) xTaskResumeAll();
80047ba: f7ff fa0b bl 8003bd4 <xTaskResumeAll>
}
80047be: bf00 nop
80047c0: 3710 adds r7, #16
80047c2: 46bd mov sp, r7
80047c4: bd80 pop {r7, pc}
80047c6: bf00 nop
80047c8: 20000dec .word 0x20000dec
80047cc: 20000df0 .word 0x20000df0
80047d0: e000ed04 .word 0xe000ed04
080047d4 <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/
static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
80047d4: b480 push {r7}
80047d6: b085 sub sp, #20
80047d8: af00 add r7, sp, #0
80047da: 6078 str r0, [r7, #4]
the timer with the nearest expiry time will expire. If there are no
active timers then just set the next expire time to 0. That will cause
this task to unblock when the tick count overflows, at which point the
timer lists will be switched and the next expiry time can be
re-assessed. */
*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
80047dc: 4b0e ldr r3, [pc, #56] ; (8004818 <prvGetNextExpireTime+0x44>)
80047de: 681b ldr r3, [r3, #0]
80047e0: 681b ldr r3, [r3, #0]
80047e2: 2b00 cmp r3, #0
80047e4: d101 bne.n 80047ea <prvGetNextExpireTime+0x16>
80047e6: 2201 movs r2, #1
80047e8: e000 b.n 80047ec <prvGetNextExpireTime+0x18>
80047ea: 2200 movs r2, #0
80047ec: 687b ldr r3, [r7, #4]
80047ee: 601a str r2, [r3, #0]
if( *pxListWasEmpty == pdFALSE )
80047f0: 687b ldr r3, [r7, #4]
80047f2: 681b ldr r3, [r3, #0]
80047f4: 2b00 cmp r3, #0
80047f6: d105 bne.n 8004804 <prvGetNextExpireTime+0x30>
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
80047f8: 4b07 ldr r3, [pc, #28] ; (8004818 <prvGetNextExpireTime+0x44>)
80047fa: 681b ldr r3, [r3, #0]
80047fc: 68db ldr r3, [r3, #12]
80047fe: 681b ldr r3, [r3, #0]
8004800: 60fb str r3, [r7, #12]
8004802: e001 b.n 8004808 <prvGetNextExpireTime+0x34>
}
else
{
/* Ensure the task unblocks when the tick count rolls over. */
xNextExpireTime = ( TickType_t ) 0U;
8004804: 2300 movs r3, #0
8004806: 60fb str r3, [r7, #12]
}
return xNextExpireTime;
8004808: 68fb ldr r3, [r7, #12]
}
800480a: 4618 mov r0, r3
800480c: 3714 adds r7, #20
800480e: 46bd mov sp, r7
8004810: f85d 7b04 ldr.w r7, [sp], #4
8004814: 4770 bx lr
8004816: bf00 nop
8004818: 20000de8 .word 0x20000de8
0800481c <prvSampleTimeNow>:
/*-----------------------------------------------------------*/
static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
800481c: b580 push {r7, lr}
800481e: b084 sub sp, #16
8004820: af00 add r7, sp, #0
8004822: 6078 str r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
xTimeNow = xTaskGetTickCount();
8004824: f7ff fa74 bl 8003d10 <xTaskGetTickCount>
8004828: 60f8 str r0, [r7, #12]
if( xTimeNow < xLastTime )
800482a: 4b0b ldr r3, [pc, #44] ; (8004858 <prvSampleTimeNow+0x3c>)
800482c: 681b ldr r3, [r3, #0]
800482e: 68fa ldr r2, [r7, #12]
8004830: 429a cmp r2, r3
8004832: d205 bcs.n 8004840 <prvSampleTimeNow+0x24>
{
prvSwitchTimerLists();
8004834: f000 f936 bl 8004aa4 <prvSwitchTimerLists>
*pxTimerListsWereSwitched = pdTRUE;
8004838: 687b ldr r3, [r7, #4]
800483a: 2201 movs r2, #1
800483c: 601a str r2, [r3, #0]
800483e: e002 b.n 8004846 <prvSampleTimeNow+0x2a>
}
else
{
*pxTimerListsWereSwitched = pdFALSE;
8004840: 687b ldr r3, [r7, #4]
8004842: 2200 movs r2, #0
8004844: 601a str r2, [r3, #0]
}
xLastTime = xTimeNow;
8004846: 4a04 ldr r2, [pc, #16] ; (8004858 <prvSampleTimeNow+0x3c>)
8004848: 68fb ldr r3, [r7, #12]
800484a: 6013 str r3, [r2, #0]
return xTimeNow;
800484c: 68fb ldr r3, [r7, #12]
}
800484e: 4618 mov r0, r3
8004850: 3710 adds r7, #16
8004852: 46bd mov sp, r7
8004854: bd80 pop {r7, pc}
8004856: bf00 nop
8004858: 20000df8 .word 0x20000df8
0800485c <prvInsertTimerInActiveList>:
/*-----------------------------------------------------------*/
static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
{
800485c: b580 push {r7, lr}
800485e: b086 sub sp, #24
8004860: af00 add r7, sp, #0
8004862: 60f8 str r0, [r7, #12]
8004864: 60b9 str r1, [r7, #8]
8004866: 607a str r2, [r7, #4]
8004868: 603b str r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
800486a: 2300 movs r3, #0
800486c: 617b str r3, [r7, #20]
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
800486e: 68fb ldr r3, [r7, #12]
8004870: 68ba ldr r2, [r7, #8]
8004872: 605a str r2, [r3, #4]
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
8004874: 68fb ldr r3, [r7, #12]
8004876: 68fa ldr r2, [r7, #12]
8004878: 611a str r2, [r3, #16]
if( xNextExpiryTime <= xTimeNow )
800487a: 68ba ldr r2, [r7, #8]
800487c: 687b ldr r3, [r7, #4]
800487e: 429a cmp r2, r3
8004880: d812 bhi.n 80048a8 <prvInsertTimerInActiveList+0x4c>
{
/* Has the expiry time elapsed between the command to start/reset a
timer was issued, and the time the command was processed? */
if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
8004882: 687a ldr r2, [r7, #4]
8004884: 683b ldr r3, [r7, #0]
8004886: 1ad2 subs r2, r2, r3
8004888: 68fb ldr r3, [r7, #12]
800488a: 699b ldr r3, [r3, #24]
800488c: 429a cmp r2, r3
800488e: d302 bcc.n 8004896 <prvInsertTimerInActiveList+0x3a>
{
/* The time between a command being issued and the command being
processed actually exceeds the timers period. */
xProcessTimerNow = pdTRUE;
8004890: 2301 movs r3, #1
8004892: 617b str r3, [r7, #20]
8004894: e01b b.n 80048ce <prvInsertTimerInActiveList+0x72>
}
else
{
vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
8004896: 4b10 ldr r3, [pc, #64] ; (80048d8 <prvInsertTimerInActiveList+0x7c>)
8004898: 681a ldr r2, [r3, #0]
800489a: 68fb ldr r3, [r7, #12]
800489c: 3304 adds r3, #4
800489e: 4619 mov r1, r3
80048a0: 4610 mov r0, r2
80048a2: f7fe f9de bl 8002c62 <vListInsert>
80048a6: e012 b.n 80048ce <prvInsertTimerInActiveList+0x72>
}
}
else
{
if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
80048a8: 687a ldr r2, [r7, #4]
80048aa: 683b ldr r3, [r7, #0]
80048ac: 429a cmp r2, r3
80048ae: d206 bcs.n 80048be <prvInsertTimerInActiveList+0x62>
80048b0: 68ba ldr r2, [r7, #8]
80048b2: 683b ldr r3, [r7, #0]
80048b4: 429a cmp r2, r3
80048b6: d302 bcc.n 80048be <prvInsertTimerInActiveList+0x62>
{
/* If, since the command was issued, the tick count has overflowed
but the expiry time has not, then the timer must have already passed
its expiry time and should be processed immediately. */
xProcessTimerNow = pdTRUE;
80048b8: 2301 movs r3, #1
80048ba: 617b str r3, [r7, #20]
80048bc: e007 b.n 80048ce <prvInsertTimerInActiveList+0x72>
}
else
{
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
80048be: 4b07 ldr r3, [pc, #28] ; (80048dc <prvInsertTimerInActiveList+0x80>)
80048c0: 681a ldr r2, [r3, #0]
80048c2: 68fb ldr r3, [r7, #12]
80048c4: 3304 adds r3, #4
80048c6: 4619 mov r1, r3
80048c8: 4610 mov r0, r2
80048ca: f7fe f9ca bl 8002c62 <vListInsert>
}
}
return xProcessTimerNow;
80048ce: 697b ldr r3, [r7, #20]
}
80048d0: 4618 mov r0, r3
80048d2: 3718 adds r7, #24
80048d4: 46bd mov sp, r7
80048d6: bd80 pop {r7, pc}
80048d8: 20000dec .word 0x20000dec
80048dc: 20000de8 .word 0x20000de8
080048e0 <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/
static void prvProcessReceivedCommands( void )
{
80048e0: b580 push {r7, lr}
80048e2: b08e sub sp, #56 ; 0x38
80048e4: af02 add r7, sp, #8
DaemonTaskMessage_t xMessage;
Timer_t *pxTimer;
BaseType_t xTimerListsWereSwitched, xResult;
TickType_t xTimeNow;
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
80048e6: e0ca b.n 8004a7e <prvProcessReceivedCommands+0x19e>
{
#if ( INCLUDE_xTimerPendFunctionCall == 1 )
{
/* Negative commands are pended function calls rather than timer
commands. */
if( xMessage.xMessageID < ( BaseType_t ) 0 )
80048e8: 687b ldr r3, [r7, #4]
80048ea: 2b00 cmp r3, #0
80048ec: da18 bge.n 8004920 <prvProcessReceivedCommands+0x40>
{
const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
80048ee: 1d3b adds r3, r7, #4
80048f0: 3304 adds r3, #4
80048f2: 62fb str r3, [r7, #44] ; 0x2c
/* The timer uses the xCallbackParameters member to request a
callback be executed. Check the callback is not NULL. */
configASSERT( pxCallback );
80048f4: 6afb ldr r3, [r7, #44] ; 0x2c
80048f6: 2b00 cmp r3, #0
80048f8: d10a bne.n 8004910 <prvProcessReceivedCommands+0x30>
__asm volatile
80048fa: f04f 0350 mov.w r3, #80 ; 0x50
80048fe: f383 8811 msr BASEPRI, r3
8004902: f3bf 8f6f isb sy
8004906: f3bf 8f4f dsb sy
800490a: 61fb str r3, [r7, #28]
}
800490c: bf00 nop
800490e: e7fe b.n 800490e <prvProcessReceivedCommands+0x2e>
/* Call the function. */
pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
8004910: 6afb ldr r3, [r7, #44] ; 0x2c
8004912: 681b ldr r3, [r3, #0]
8004914: 6afa ldr r2, [r7, #44] ; 0x2c
8004916: 6850 ldr r0, [r2, #4]
8004918: 6afa ldr r2, [r7, #44] ; 0x2c
800491a: 6892 ldr r2, [r2, #8]
800491c: 4611 mov r1, r2
800491e: 4798 blx r3
}
#endif /* INCLUDE_xTimerPendFunctionCall */
/* Commands that are positive are timer commands rather than pended
function calls. */
if( xMessage.xMessageID >= ( BaseType_t ) 0 )
8004920: 687b ldr r3, [r7, #4]
8004922: 2b00 cmp r3, #0
8004924: f2c0 80ab blt.w 8004a7e <prvProcessReceivedCommands+0x19e>
{
/* The messages uses the xTimerParameters member to work on a
software timer. */
pxTimer = xMessage.u.xTimerParameters.pxTimer;
8004928: 68fb ldr r3, [r7, #12]
800492a: 62bb str r3, [r7, #40] ; 0x28
if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
800492c: 6abb ldr r3, [r7, #40] ; 0x28
800492e: 695b ldr r3, [r3, #20]
8004930: 2b00 cmp r3, #0
8004932: d004 beq.n 800493e <prvProcessReceivedCommands+0x5e>
{
/* The timer is in a list, remove it. */
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8004934: 6abb ldr r3, [r7, #40] ; 0x28
8004936: 3304 adds r3, #4
8004938: 4618 mov r0, r3
800493a: f7fe f9cb bl 8002cd4 <uxListRemove>
it must be present in the function call. prvSampleTimeNow() must be
called after the message is received from xTimerQueue so there is no
possibility of a higher priority task adding a message to the message
queue with a time that is ahead of the timer daemon task (because it
pre-empted the timer daemon task after the xTimeNow value was set). */
xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
800493e: 463b mov r3, r7
8004940: 4618 mov r0, r3
8004942: f7ff ff6b bl 800481c <prvSampleTimeNow>
8004946: 6278 str r0, [r7, #36] ; 0x24
switch( xMessage.xMessageID )
8004948: 687b ldr r3, [r7, #4]
800494a: 2b09 cmp r3, #9
800494c: f200 8096 bhi.w 8004a7c <prvProcessReceivedCommands+0x19c>
8004950: a201 add r2, pc, #4 ; (adr r2, 8004958 <prvProcessReceivedCommands+0x78>)
8004952: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004956: bf00 nop
8004958: 08004981 .word 0x08004981
800495c: 08004981 .word 0x08004981
8004960: 08004981 .word 0x08004981
8004964: 080049f5 .word 0x080049f5
8004968: 08004a09 .word 0x08004a09
800496c: 08004a53 .word 0x08004a53
8004970: 08004981 .word 0x08004981
8004974: 08004981 .word 0x08004981
8004978: 080049f5 .word 0x080049f5
800497c: 08004a09 .word 0x08004a09
case tmrCOMMAND_START_FROM_ISR :
case tmrCOMMAND_RESET :
case tmrCOMMAND_RESET_FROM_ISR :
case tmrCOMMAND_START_DONT_TRACE :
/* Start or restart a timer. */
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
8004980: 6abb ldr r3, [r7, #40] ; 0x28
8004982: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
8004986: f043 0301 orr.w r3, r3, #1
800498a: b2da uxtb r2, r3
800498c: 6abb ldr r3, [r7, #40] ; 0x28
800498e: f883 2028 strb.w r2, [r3, #40] ; 0x28
if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
8004992: 68ba ldr r2, [r7, #8]
8004994: 6abb ldr r3, [r7, #40] ; 0x28
8004996: 699b ldr r3, [r3, #24]
8004998: 18d1 adds r1, r2, r3
800499a: 68bb ldr r3, [r7, #8]
800499c: 6a7a ldr r2, [r7, #36] ; 0x24
800499e: 6ab8 ldr r0, [r7, #40] ; 0x28
80049a0: f7ff ff5c bl 800485c <prvInsertTimerInActiveList>
80049a4: 4603 mov r3, r0
80049a6: 2b00 cmp r3, #0
80049a8: d069 beq.n 8004a7e <prvProcessReceivedCommands+0x19e>
{
/* The timer expired before it was added to the active
timer list. Process it now. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
80049aa: 6abb ldr r3, [r7, #40] ; 0x28
80049ac: 6a1b ldr r3, [r3, #32]
80049ae: 6ab8 ldr r0, [r7, #40] ; 0x28
80049b0: 4798 blx r3
traceTIMER_EXPIRED( pxTimer );
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
80049b2: 6abb ldr r3, [r7, #40] ; 0x28
80049b4: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
80049b8: f003 0304 and.w r3, r3, #4
80049bc: 2b00 cmp r3, #0
80049be: d05e beq.n 8004a7e <prvProcessReceivedCommands+0x19e>
{
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
80049c0: 68ba ldr r2, [r7, #8]
80049c2: 6abb ldr r3, [r7, #40] ; 0x28
80049c4: 699b ldr r3, [r3, #24]
80049c6: 441a add r2, r3
80049c8: 2300 movs r3, #0
80049ca: 9300 str r3, [sp, #0]
80049cc: 2300 movs r3, #0
80049ce: 2100 movs r1, #0
80049d0: 6ab8 ldr r0, [r7, #40] ; 0x28
80049d2: f7ff fe05 bl 80045e0 <xTimerGenericCommand>
80049d6: 6238 str r0, [r7, #32]
configASSERT( xResult );
80049d8: 6a3b ldr r3, [r7, #32]
80049da: 2b00 cmp r3, #0
80049dc: d14f bne.n 8004a7e <prvProcessReceivedCommands+0x19e>
__asm volatile
80049de: f04f 0350 mov.w r3, #80 ; 0x50
80049e2: f383 8811 msr BASEPRI, r3
80049e6: f3bf 8f6f isb sy
80049ea: f3bf 8f4f dsb sy
80049ee: 61bb str r3, [r7, #24]
}
80049f0: bf00 nop
80049f2: e7fe b.n 80049f2 <prvProcessReceivedCommands+0x112>
break;
case tmrCOMMAND_STOP :
case tmrCOMMAND_STOP_FROM_ISR :
/* The timer has already been removed from the active list. */
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
80049f4: 6abb ldr r3, [r7, #40] ; 0x28
80049f6: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
80049fa: f023 0301 bic.w r3, r3, #1
80049fe: b2da uxtb r2, r3
8004a00: 6abb ldr r3, [r7, #40] ; 0x28
8004a02: f883 2028 strb.w r2, [r3, #40] ; 0x28
break;
8004a06: e03a b.n 8004a7e <prvProcessReceivedCommands+0x19e>
case tmrCOMMAND_CHANGE_PERIOD :
case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
8004a08: 6abb ldr r3, [r7, #40] ; 0x28
8004a0a: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
8004a0e: f043 0301 orr.w r3, r3, #1
8004a12: b2da uxtb r2, r3
8004a14: 6abb ldr r3, [r7, #40] ; 0x28
8004a16: f883 2028 strb.w r2, [r3, #40] ; 0x28
pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
8004a1a: 68ba ldr r2, [r7, #8]
8004a1c: 6abb ldr r3, [r7, #40] ; 0x28
8004a1e: 619a str r2, [r3, #24]
configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
8004a20: 6abb ldr r3, [r7, #40] ; 0x28
8004a22: 699b ldr r3, [r3, #24]
8004a24: 2b00 cmp r3, #0
8004a26: d10a bne.n 8004a3e <prvProcessReceivedCommands+0x15e>
__asm volatile
8004a28: f04f 0350 mov.w r3, #80 ; 0x50
8004a2c: f383 8811 msr BASEPRI, r3
8004a30: f3bf 8f6f isb sy
8004a34: f3bf 8f4f dsb sy
8004a38: 617b str r3, [r7, #20]
}
8004a3a: bf00 nop
8004a3c: e7fe b.n 8004a3c <prvProcessReceivedCommands+0x15c>
be longer or shorter than the old one. The command time is
therefore set to the current time, and as the period cannot
be zero the next expiry time can only be in the future,
meaning (unlike for the xTimerStart() case above) there is
no fail case that needs to be handled here. */
( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
8004a3e: 6abb ldr r3, [r7, #40] ; 0x28
8004a40: 699a ldr r2, [r3, #24]
8004a42: 6a7b ldr r3, [r7, #36] ; 0x24
8004a44: 18d1 adds r1, r2, r3
8004a46: 6a7b ldr r3, [r7, #36] ; 0x24
8004a48: 6a7a ldr r2, [r7, #36] ; 0x24
8004a4a: 6ab8 ldr r0, [r7, #40] ; 0x28
8004a4c: f7ff ff06 bl 800485c <prvInsertTimerInActiveList>
break;
8004a50: e015 b.n 8004a7e <prvProcessReceivedCommands+0x19e>
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
{
/* The timer has already been removed from the active list,
just free up the memory if the memory was dynamically
allocated. */
if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
8004a52: 6abb ldr r3, [r7, #40] ; 0x28
8004a54: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
8004a58: f003 0302 and.w r3, r3, #2
8004a5c: 2b00 cmp r3, #0
8004a5e: d103 bne.n 8004a68 <prvProcessReceivedCommands+0x188>
{
vPortFree( pxTimer );
8004a60: 6ab8 ldr r0, [r7, #40] ; 0x28
8004a62: f000 fbdd bl 8005220 <vPortFree>
8004a66: e00a b.n 8004a7e <prvProcessReceivedCommands+0x19e>
}
else
{
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
8004a68: 6abb ldr r3, [r7, #40] ; 0x28
8004a6a: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
8004a6e: f023 0301 bic.w r3, r3, #1
8004a72: b2da uxtb r2, r3
8004a74: 6abb ldr r3, [r7, #40] ; 0x28
8004a76: f883 2028 strb.w r2, [r3, #40] ; 0x28
no need to free the memory - just mark the timer as
"not active". */
pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
}
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
break;
8004a7a: e000 b.n 8004a7e <prvProcessReceivedCommands+0x19e>
default :
/* Don't expect to get here. */
break;
8004a7c: bf00 nop
while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
8004a7e: 4b08 ldr r3, [pc, #32] ; (8004aa0 <prvProcessReceivedCommands+0x1c0>)
8004a80: 681b ldr r3, [r3, #0]
8004a82: 1d39 adds r1, r7, #4
8004a84: 2200 movs r2, #0
8004a86: 4618 mov r0, r3
8004a88: f7fe fbec bl 8003264 <xQueueReceive>
8004a8c: 4603 mov r3, r0
8004a8e: 2b00 cmp r3, #0
8004a90: f47f af2a bne.w 80048e8 <prvProcessReceivedCommands+0x8>
}
}
}
}
8004a94: bf00 nop
8004a96: bf00 nop
8004a98: 3730 adds r7, #48 ; 0x30
8004a9a: 46bd mov sp, r7
8004a9c: bd80 pop {r7, pc}
8004a9e: bf00 nop
8004aa0: 20000df0 .word 0x20000df0
08004aa4 <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/
static void prvSwitchTimerLists( void )
{
8004aa4: b580 push {r7, lr}
8004aa6: b088 sub sp, #32
8004aa8: af02 add r7, sp, #8
/* The tick count has overflowed. The timer lists must be switched.
If there are any timers still referenced from the current timer list
then they must have expired and should be processed before the lists
are switched. */
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
8004aaa: e048 b.n 8004b3e <prvSwitchTimerLists+0x9a>
{
xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
8004aac: 4b2d ldr r3, [pc, #180] ; (8004b64 <prvSwitchTimerLists+0xc0>)
8004aae: 681b ldr r3, [r3, #0]
8004ab0: 68db ldr r3, [r3, #12]
8004ab2: 681b ldr r3, [r3, #0]
8004ab4: 613b str r3, [r7, #16]
/* Remove the timer from the list. */
pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
8004ab6: 4b2b ldr r3, [pc, #172] ; (8004b64 <prvSwitchTimerLists+0xc0>)
8004ab8: 681b ldr r3, [r3, #0]
8004aba: 68db ldr r3, [r3, #12]
8004abc: 68db ldr r3, [r3, #12]
8004abe: 60fb str r3, [r7, #12]
( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
8004ac0: 68fb ldr r3, [r7, #12]
8004ac2: 3304 adds r3, #4
8004ac4: 4618 mov r0, r3
8004ac6: f7fe f905 bl 8002cd4 <uxListRemove>
traceTIMER_EXPIRED( pxTimer );
/* Execute its callback, then send a command to restart the timer if
it is an auto-reload timer. It cannot be restarted here as the lists
have not yet been switched. */
pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
8004aca: 68fb ldr r3, [r7, #12]
8004acc: 6a1b ldr r3, [r3, #32]
8004ace: 68f8 ldr r0, [r7, #12]
8004ad0: 4798 blx r3
if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
8004ad2: 68fb ldr r3, [r7, #12]
8004ad4: f893 3028 ldrb.w r3, [r3, #40] ; 0x28
8004ad8: f003 0304 and.w r3, r3, #4
8004adc: 2b00 cmp r3, #0
8004ade: d02e beq.n 8004b3e <prvSwitchTimerLists+0x9a>
the timer going into the same timer list then it has already expired
and the timer should be re-inserted into the current list so it is
processed again within this loop. Otherwise a command should be sent
to restart the timer to ensure it is only inserted into a list after
the lists have been swapped. */
xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
8004ae0: 68fb ldr r3, [r7, #12]
8004ae2: 699b ldr r3, [r3, #24]
8004ae4: 693a ldr r2, [r7, #16]
8004ae6: 4413 add r3, r2
8004ae8: 60bb str r3, [r7, #8]
if( xReloadTime > xNextExpireTime )
8004aea: 68ba ldr r2, [r7, #8]
8004aec: 693b ldr r3, [r7, #16]
8004aee: 429a cmp r2, r3
8004af0: d90e bls.n 8004b10 <prvSwitchTimerLists+0x6c>
{
listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
8004af2: 68fb ldr r3, [r7, #12]
8004af4: 68ba ldr r2, [r7, #8]
8004af6: 605a str r2, [r3, #4]
listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
8004af8: 68fb ldr r3, [r7, #12]
8004afa: 68fa ldr r2, [r7, #12]
8004afc: 611a str r2, [r3, #16]
vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
8004afe: 4b19 ldr r3, [pc, #100] ; (8004b64 <prvSwitchTimerLists+0xc0>)
8004b00: 681a ldr r2, [r3, #0]
8004b02: 68fb ldr r3, [r7, #12]
8004b04: 3304 adds r3, #4
8004b06: 4619 mov r1, r3
8004b08: 4610 mov r0, r2
8004b0a: f7fe f8aa bl 8002c62 <vListInsert>
8004b0e: e016 b.n 8004b3e <prvSwitchTimerLists+0x9a>
}
else
{
xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
8004b10: 2300 movs r3, #0
8004b12: 9300 str r3, [sp, #0]
8004b14: 2300 movs r3, #0
8004b16: 693a ldr r2, [r7, #16]
8004b18: 2100 movs r1, #0
8004b1a: 68f8 ldr r0, [r7, #12]
8004b1c: f7ff fd60 bl 80045e0 <xTimerGenericCommand>
8004b20: 6078 str r0, [r7, #4]
configASSERT( xResult );
8004b22: 687b ldr r3, [r7, #4]
8004b24: 2b00 cmp r3, #0
8004b26: d10a bne.n 8004b3e <prvSwitchTimerLists+0x9a>
__asm volatile
8004b28: f04f 0350 mov.w r3, #80 ; 0x50
8004b2c: f383 8811 msr BASEPRI, r3
8004b30: f3bf 8f6f isb sy
8004b34: f3bf 8f4f dsb sy
8004b38: 603b str r3, [r7, #0]
}
8004b3a: bf00 nop
8004b3c: e7fe b.n 8004b3c <prvSwitchTimerLists+0x98>
while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
8004b3e: 4b09 ldr r3, [pc, #36] ; (8004b64 <prvSwitchTimerLists+0xc0>)
8004b40: 681b ldr r3, [r3, #0]
8004b42: 681b ldr r3, [r3, #0]
8004b44: 2b00 cmp r3, #0
8004b46: d1b1 bne.n 8004aac <prvSwitchTimerLists+0x8>
{
mtCOVERAGE_TEST_MARKER();
}
}
pxTemp = pxCurrentTimerList;
8004b48: 4b06 ldr r3, [pc, #24] ; (8004b64 <prvSwitchTimerLists+0xc0>)
8004b4a: 681b ldr r3, [r3, #0]
8004b4c: 617b str r3, [r7, #20]
pxCurrentTimerList = pxOverflowTimerList;
8004b4e: 4b06 ldr r3, [pc, #24] ; (8004b68 <prvSwitchTimerLists+0xc4>)
8004b50: 681b ldr r3, [r3, #0]
8004b52: 4a04 ldr r2, [pc, #16] ; (8004b64 <prvSwitchTimerLists+0xc0>)
8004b54: 6013 str r3, [r2, #0]
pxOverflowTimerList = pxTemp;
8004b56: 4a04 ldr r2, [pc, #16] ; (8004b68 <prvSwitchTimerLists+0xc4>)
8004b58: 697b ldr r3, [r7, #20]
8004b5a: 6013 str r3, [r2, #0]
}
8004b5c: bf00 nop
8004b5e: 3718 adds r7, #24
8004b60: 46bd mov sp, r7
8004b62: bd80 pop {r7, pc}
8004b64: 20000de8 .word 0x20000de8
8004b68: 20000dec .word 0x20000dec
08004b6c <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/
static void prvCheckForValidListAndQueue( void )
{
8004b6c: b580 push {r7, lr}
8004b6e: b082 sub sp, #8
8004b70: af02 add r7, sp, #8
/* Check that the list from which active timers are referenced, and the
queue used to communicate with the timer service, have been
initialised. */
taskENTER_CRITICAL();
8004b72: f000 f967 bl 8004e44 <vPortEnterCritical>
{
if( xTimerQueue == NULL )
8004b76: 4b15 ldr r3, [pc, #84] ; (8004bcc <prvCheckForValidListAndQueue+0x60>)
8004b78: 681b ldr r3, [r3, #0]
8004b7a: 2b00 cmp r3, #0
8004b7c: d120 bne.n 8004bc0 <prvCheckForValidListAndQueue+0x54>
{
vListInitialise( &xActiveTimerList1 );
8004b7e: 4814 ldr r0, [pc, #80] ; (8004bd0 <prvCheckForValidListAndQueue+0x64>)
8004b80: f7fe f81e bl 8002bc0 <vListInitialise>
vListInitialise( &xActiveTimerList2 );
8004b84: 4813 ldr r0, [pc, #76] ; (8004bd4 <prvCheckForValidListAndQueue+0x68>)
8004b86: f7fe f81b bl 8002bc0 <vListInitialise>
pxCurrentTimerList = &xActiveTimerList1;
8004b8a: 4b13 ldr r3, [pc, #76] ; (8004bd8 <prvCheckForValidListAndQueue+0x6c>)
8004b8c: 4a10 ldr r2, [pc, #64] ; (8004bd0 <prvCheckForValidListAndQueue+0x64>)
8004b8e: 601a str r2, [r3, #0]
pxOverflowTimerList = &xActiveTimerList2;
8004b90: 4b12 ldr r3, [pc, #72] ; (8004bdc <prvCheckForValidListAndQueue+0x70>)
8004b92: 4a10 ldr r2, [pc, #64] ; (8004bd4 <prvCheckForValidListAndQueue+0x68>)
8004b94: 601a str r2, [r3, #0]
/* The timer queue is allocated statically in case
configSUPPORT_DYNAMIC_ALLOCATION is 0. */
static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
8004b96: 2300 movs r3, #0
8004b98: 9300 str r3, [sp, #0]
8004b9a: 4b11 ldr r3, [pc, #68] ; (8004be0 <prvCheckForValidListAndQueue+0x74>)
8004b9c: 4a11 ldr r2, [pc, #68] ; (8004be4 <prvCheckForValidListAndQueue+0x78>)
8004b9e: 2110 movs r1, #16
8004ba0: 200a movs r0, #10
8004ba2: f7fe f929 bl 8002df8 <xQueueGenericCreateStatic>
8004ba6: 4603 mov r3, r0
8004ba8: 4a08 ldr r2, [pc, #32] ; (8004bcc <prvCheckForValidListAndQueue+0x60>)
8004baa: 6013 str r3, [r2, #0]
}
#endif
#if ( configQUEUE_REGISTRY_SIZE > 0 )
{
if( xTimerQueue != NULL )
8004bac: 4b07 ldr r3, [pc, #28] ; (8004bcc <prvCheckForValidListAndQueue+0x60>)
8004bae: 681b ldr r3, [r3, #0]
8004bb0: 2b00 cmp r3, #0
8004bb2: d005 beq.n 8004bc0 <prvCheckForValidListAndQueue+0x54>
{
vQueueAddToRegistry( xTimerQueue, "TmrQ" );
8004bb4: 4b05 ldr r3, [pc, #20] ; (8004bcc <prvCheckForValidListAndQueue+0x60>)
8004bb6: 681b ldr r3, [r3, #0]
8004bb8: 490b ldr r1, [pc, #44] ; (8004be8 <prvCheckForValidListAndQueue+0x7c>)
8004bba: 4618 mov r0, r3
8004bbc: f7fe fd42 bl 8003644 <vQueueAddToRegistry>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
taskEXIT_CRITICAL();
8004bc0: f000 f970 bl 8004ea4 <vPortExitCritical>
}
8004bc4: bf00 nop
8004bc6: 46bd mov sp, r7
8004bc8: bd80 pop {r7, pc}
8004bca: bf00 nop
8004bcc: 20000df0 .word 0x20000df0
8004bd0: 20000dc0 .word 0x20000dc0
8004bd4: 20000dd4 .word 0x20000dd4
8004bd8: 20000de8 .word 0x20000de8
8004bdc: 20000dec .word 0x20000dec
8004be0: 20000e9c .word 0x20000e9c
8004be4: 20000dfc .word 0x20000dfc
8004be8: 08005670 .word 0x08005670
08004bec <pxPortInitialiseStack>:
/*
* See header file for description.
*/
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
8004bec: b480 push {r7}
8004bee: b085 sub sp, #20
8004bf0: af00 add r7, sp, #0
8004bf2: 60f8 str r0, [r7, #12]
8004bf4: 60b9 str r1, [r7, #8]
8004bf6: 607a str r2, [r7, #4]
/* Simulate the stack frame as it would be created by a context switch
interrupt. */
/* Offset added to account for the way the MCU uses the stack on entry/exit
of interrupts, and to ensure alignment. */
pxTopOfStack--;
8004bf8: 68fb ldr r3, [r7, #12]
8004bfa: 3b04 subs r3, #4
8004bfc: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_XPSR; /* xPSR */
8004bfe: 68fb ldr r3, [r7, #12]
8004c00: f04f 7280 mov.w r2, #16777216 ; 0x1000000
8004c04: 601a str r2, [r3, #0]
pxTopOfStack--;
8004c06: 68fb ldr r3, [r7, #12]
8004c08: 3b04 subs r3, #4
8004c0a: 60fb str r3, [r7, #12]
*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
8004c0c: 68bb ldr r3, [r7, #8]
8004c0e: f023 0201 bic.w r2, r3, #1
8004c12: 68fb ldr r3, [r7, #12]
8004c14: 601a str r2, [r3, #0]
pxTopOfStack--;
8004c16: 68fb ldr r3, [r7, #12]
8004c18: 3b04 subs r3, #4
8004c1a: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
8004c1c: 4a0c ldr r2, [pc, #48] ; (8004c50 <pxPortInitialiseStack+0x64>)
8004c1e: 68fb ldr r3, [r7, #12]
8004c20: 601a str r2, [r3, #0]
/* Save code space by skipping register initialisation. */
pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
8004c22: 68fb ldr r3, [r7, #12]
8004c24: 3b14 subs r3, #20
8004c26: 60fb str r3, [r7, #12]
*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
8004c28: 687a ldr r2, [r7, #4]
8004c2a: 68fb ldr r3, [r7, #12]
8004c2c: 601a str r2, [r3, #0]
/* A save method is being used that requires each task to maintain its
own exec return value. */
pxTopOfStack--;
8004c2e: 68fb ldr r3, [r7, #12]
8004c30: 3b04 subs r3, #4
8004c32: 60fb str r3, [r7, #12]
*pxTopOfStack = portINITIAL_EXC_RETURN;
8004c34: 68fb ldr r3, [r7, #12]
8004c36: f06f 0202 mvn.w r2, #2
8004c3a: 601a str r2, [r3, #0]
pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
8004c3c: 68fb ldr r3, [r7, #12]
8004c3e: 3b20 subs r3, #32
8004c40: 60fb str r3, [r7, #12]
return pxTopOfStack;
8004c42: 68fb ldr r3, [r7, #12]
}
8004c44: 4618 mov r0, r3
8004c46: 3714 adds r7, #20
8004c48: 46bd mov sp, r7
8004c4a: f85d 7b04 ldr.w r7, [sp], #4
8004c4e: 4770 bx lr
8004c50: 08004c55 .word 0x08004c55
08004c54 <prvTaskExitError>:
/*-----------------------------------------------------------*/
static void prvTaskExitError( void )
{
8004c54: b480 push {r7}
8004c56: b085 sub sp, #20
8004c58: af00 add r7, sp, #0
volatile uint32_t ulDummy = 0;
8004c5a: 2300 movs r3, #0
8004c5c: 607b str r3, [r7, #4]
its caller as there is nothing to return to. If a task wants to exit it
should instead call vTaskDelete( NULL ).
Artificially force an assert() to be triggered if configASSERT() is
defined, then stop here so application writers can catch the error. */
configASSERT( uxCriticalNesting == ~0UL );
8004c5e: 4b12 ldr r3, [pc, #72] ; (8004ca8 <prvTaskExitError+0x54>)
8004c60: 681b ldr r3, [r3, #0]
8004c62: f1b3 3fff cmp.w r3, #4294967295
8004c66: d00a beq.n 8004c7e <prvTaskExitError+0x2a>
__asm volatile
8004c68: f04f 0350 mov.w r3, #80 ; 0x50
8004c6c: f383 8811 msr BASEPRI, r3
8004c70: f3bf 8f6f isb sy
8004c74: f3bf 8f4f dsb sy
8004c78: 60fb str r3, [r7, #12]
}
8004c7a: bf00 nop
8004c7c: e7fe b.n 8004c7c <prvTaskExitError+0x28>
__asm volatile
8004c7e: f04f 0350 mov.w r3, #80 ; 0x50
8004c82: f383 8811 msr BASEPRI, r3
8004c86: f3bf 8f6f isb sy
8004c8a: f3bf 8f4f dsb sy
8004c8e: 60bb str r3, [r7, #8]
}
8004c90: bf00 nop
portDISABLE_INTERRUPTS();
while( ulDummy == 0 )
8004c92: bf00 nop
8004c94: 687b ldr r3, [r7, #4]
8004c96: 2b00 cmp r3, #0
8004c98: d0fc beq.n 8004c94 <prvTaskExitError+0x40>
about code appearing after this function is called - making ulDummy
volatile makes the compiler think the function could return and
therefore not output an 'unreachable code' warning for code that appears
after it. */
}
}
8004c9a: bf00 nop
8004c9c: bf00 nop
8004c9e: 3714 adds r7, #20
8004ca0: 46bd mov sp, r7
8004ca2: f85d 7b04 ldr.w r7, [sp], #4
8004ca6: 4770 bx lr
8004ca8: 2000000c .word 0x2000000c
8004cac: 00000000 .word 0x00000000
08004cb0 <SVC_Handler>:
/*-----------------------------------------------------------*/
void vPortSVCHandler( void )
{
__asm volatile (
8004cb0: 4b07 ldr r3, [pc, #28] ; (8004cd0 <pxCurrentTCBConst2>)
8004cb2: 6819 ldr r1, [r3, #0]
8004cb4: 6808 ldr r0, [r1, #0]
8004cb6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004cba: f380 8809 msr PSP, r0
8004cbe: f3bf 8f6f isb sy
8004cc2: f04f 0000 mov.w r0, #0
8004cc6: f380 8811 msr BASEPRI, r0
8004cca: 4770 bx lr
8004ccc: f3af 8000 nop.w
08004cd0 <pxCurrentTCBConst2>:
8004cd0: 200008c0 .word 0x200008c0
" bx r14 \n"
" \n"
" .align 4 \n"
"pxCurrentTCBConst2: .word pxCurrentTCB \n"
);
}
8004cd4: bf00 nop
8004cd6: bf00 nop
08004cd8 <prvPortStartFirstTask>:
{
/* Start the first task. This also clears the bit that indicates the FPU is
in use in case the FPU was used before the scheduler was started - which
would otherwise result in the unnecessary leaving of space in the SVC stack
for lazy saving of FPU registers. */
__asm volatile(
8004cd8: 4808 ldr r0, [pc, #32] ; (8004cfc <prvPortStartFirstTask+0x24>)
8004cda: 6800 ldr r0, [r0, #0]
8004cdc: 6800 ldr r0, [r0, #0]
8004cde: f380 8808 msr MSP, r0
8004ce2: f04f 0000 mov.w r0, #0
8004ce6: f380 8814 msr CONTROL, r0
8004cea: b662 cpsie i
8004cec: b661 cpsie f
8004cee: f3bf 8f4f dsb sy
8004cf2: f3bf 8f6f isb sy
8004cf6: df00 svc 0
8004cf8: bf00 nop
" dsb \n"
" isb \n"
" svc 0 \n" /* System call to start first task. */
" nop \n"
);
}
8004cfa: bf00 nop
8004cfc: e000ed08 .word 0xe000ed08
08004d00 <xPortStartScheduler>:
/*
* See header file for description.
*/
BaseType_t xPortStartScheduler( void )
{
8004d00: b580 push {r7, lr}
8004d02: b086 sub sp, #24
8004d04: af00 add r7, sp, #0
configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
/* This port can be used on all revisions of the Cortex-M7 core other than
the r0p1 parts. r0p1 parts should use the port from the
/source/portable/GCC/ARM_CM7/r0p1 directory. */
configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
8004d06: 4b46 ldr r3, [pc, #280] ; (8004e20 <xPortStartScheduler+0x120>)
8004d08: 681b ldr r3, [r3, #0]
8004d0a: 4a46 ldr r2, [pc, #280] ; (8004e24 <xPortStartScheduler+0x124>)
8004d0c: 4293 cmp r3, r2
8004d0e: d10a bne.n 8004d26 <xPortStartScheduler+0x26>
__asm volatile
8004d10: f04f 0350 mov.w r3, #80 ; 0x50
8004d14: f383 8811 msr BASEPRI, r3
8004d18: f3bf 8f6f isb sy
8004d1c: f3bf 8f4f dsb sy
8004d20: 613b str r3, [r7, #16]
}
8004d22: bf00 nop
8004d24: e7fe b.n 8004d24 <xPortStartScheduler+0x24>
configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
8004d26: 4b3e ldr r3, [pc, #248] ; (8004e20 <xPortStartScheduler+0x120>)
8004d28: 681b ldr r3, [r3, #0]
8004d2a: 4a3f ldr r2, [pc, #252] ; (8004e28 <xPortStartScheduler+0x128>)
8004d2c: 4293 cmp r3, r2
8004d2e: d10a bne.n 8004d46 <xPortStartScheduler+0x46>
__asm volatile
8004d30: f04f 0350 mov.w r3, #80 ; 0x50
8004d34: f383 8811 msr BASEPRI, r3
8004d38: f3bf 8f6f isb sy
8004d3c: f3bf 8f4f dsb sy
8004d40: 60fb str r3, [r7, #12]
}
8004d42: bf00 nop
8004d44: e7fe b.n 8004d44 <xPortStartScheduler+0x44>
#if( configASSERT_DEFINED == 1 )
{
volatile uint32_t ulOriginalPriority;
volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
8004d46: 4b39 ldr r3, [pc, #228] ; (8004e2c <xPortStartScheduler+0x12c>)
8004d48: 617b str r3, [r7, #20]
functions can be called. ISR safe functions are those that end in
"FromISR". FreeRTOS maintains separate thread and ISR API functions to
ensure interrupt entry is as fast and simple as possible.
Save the interrupt priority value that is about to be clobbered. */
ulOriginalPriority = *pucFirstUserPriorityRegister;
8004d4a: 697b ldr r3, [r7, #20]
8004d4c: 781b ldrb r3, [r3, #0]
8004d4e: b2db uxtb r3, r3
8004d50: 607b str r3, [r7, #4]
/* Determine the number of priority bits available. First write to all
possible bits. */
*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
8004d52: 697b ldr r3, [r7, #20]
8004d54: 22ff movs r2, #255 ; 0xff
8004d56: 701a strb r2, [r3, #0]
/* Read the value back to see how many bits stuck. */
ucMaxPriorityValue = *pucFirstUserPriorityRegister;
8004d58: 697b ldr r3, [r7, #20]
8004d5a: 781b ldrb r3, [r3, #0]
8004d5c: b2db uxtb r3, r3
8004d5e: 70fb strb r3, [r7, #3]
/* Use the same mask on the maximum system call priority. */
ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
8004d60: 78fb ldrb r3, [r7, #3]
8004d62: b2db uxtb r3, r3
8004d64: f003 0350 and.w r3, r3, #80 ; 0x50
8004d68: b2da uxtb r2, r3
8004d6a: 4b31 ldr r3, [pc, #196] ; (8004e30 <xPortStartScheduler+0x130>)
8004d6c: 701a strb r2, [r3, #0]
/* Calculate the maximum acceptable priority group value for the number
of bits read back. */
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
8004d6e: 4b31 ldr r3, [pc, #196] ; (8004e34 <xPortStartScheduler+0x134>)
8004d70: 2207 movs r2, #7
8004d72: 601a str r2, [r3, #0]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
8004d74: e009 b.n 8004d8a <xPortStartScheduler+0x8a>
{
ulMaxPRIGROUPValue--;
8004d76: 4b2f ldr r3, [pc, #188] ; (8004e34 <xPortStartScheduler+0x134>)
8004d78: 681b ldr r3, [r3, #0]
8004d7a: 3b01 subs r3, #1
8004d7c: 4a2d ldr r2, [pc, #180] ; (8004e34 <xPortStartScheduler+0x134>)
8004d7e: 6013 str r3, [r2, #0]
ucMaxPriorityValue <<= ( uint8_t ) 0x01;
8004d80: 78fb ldrb r3, [r7, #3]
8004d82: b2db uxtb r3, r3
8004d84: 005b lsls r3, r3, #1
8004d86: b2db uxtb r3, r3
8004d88: 70fb strb r3, [r7, #3]
while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
8004d8a: 78fb ldrb r3, [r7, #3]
8004d8c: b2db uxtb r3, r3
8004d8e: f003 0380 and.w r3, r3, #128 ; 0x80
8004d92: 2b80 cmp r3, #128 ; 0x80
8004d94: d0ef beq.n 8004d76 <xPortStartScheduler+0x76>
#ifdef configPRIO_BITS
{
/* Check the FreeRTOS configuration that defines the number of
priority bits matches the number of priority bits actually queried
from the hardware. */
configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
8004d96: 4b27 ldr r3, [pc, #156] ; (8004e34 <xPortStartScheduler+0x134>)
8004d98: 681b ldr r3, [r3, #0]
8004d9a: f1c3 0307 rsb r3, r3, #7
8004d9e: 2b04 cmp r3, #4
8004da0: d00a beq.n 8004db8 <xPortStartScheduler+0xb8>
__asm volatile
8004da2: f04f 0350 mov.w r3, #80 ; 0x50
8004da6: f383 8811 msr BASEPRI, r3
8004daa: f3bf 8f6f isb sy
8004dae: f3bf 8f4f dsb sy
8004db2: 60bb str r3, [r7, #8]
}
8004db4: bf00 nop
8004db6: e7fe b.n 8004db6 <xPortStartScheduler+0xb6>
}
#endif
/* Shift the priority group value back to its position within the AIRCR
register. */
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
8004db8: 4b1e ldr r3, [pc, #120] ; (8004e34 <xPortStartScheduler+0x134>)
8004dba: 681b ldr r3, [r3, #0]
8004dbc: 021b lsls r3, r3, #8
8004dbe: 4a1d ldr r2, [pc, #116] ; (8004e34 <xPortStartScheduler+0x134>)
8004dc0: 6013 str r3, [r2, #0]
ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
8004dc2: 4b1c ldr r3, [pc, #112] ; (8004e34 <xPortStartScheduler+0x134>)
8004dc4: 681b ldr r3, [r3, #0]
8004dc6: f403 63e0 and.w r3, r3, #1792 ; 0x700
8004dca: 4a1a ldr r2, [pc, #104] ; (8004e34 <xPortStartScheduler+0x134>)
8004dcc: 6013 str r3, [r2, #0]
/* Restore the clobbered interrupt priority register to its original
value. */
*pucFirstUserPriorityRegister = ulOriginalPriority;
8004dce: 687b ldr r3, [r7, #4]
8004dd0: b2da uxtb r2, r3
8004dd2: 697b ldr r3, [r7, #20]
8004dd4: 701a strb r2, [r3, #0]
}
#endif /* conifgASSERT_DEFINED */
/* Make PendSV and SysTick the lowest priority interrupts. */
portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
8004dd6: 4b18 ldr r3, [pc, #96] ; (8004e38 <xPortStartScheduler+0x138>)
8004dd8: 681b ldr r3, [r3, #0]
8004dda: 4a17 ldr r2, [pc, #92] ; (8004e38 <xPortStartScheduler+0x138>)
8004ddc: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8004de0: 6013 str r3, [r2, #0]
portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
8004de2: 4b15 ldr r3, [pc, #84] ; (8004e38 <xPortStartScheduler+0x138>)
8004de4: 681b ldr r3, [r3, #0]
8004de6: 4a14 ldr r2, [pc, #80] ; (8004e38 <xPortStartScheduler+0x138>)
8004de8: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000
8004dec: 6013 str r3, [r2, #0]
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
vPortSetupTimerInterrupt();
8004dee: f000 f8dd bl 8004fac <vPortSetupTimerInterrupt>
/* Initialise the critical nesting count ready for the first task. */
uxCriticalNesting = 0;
8004df2: 4b12 ldr r3, [pc, #72] ; (8004e3c <xPortStartScheduler+0x13c>)
8004df4: 2200 movs r2, #0
8004df6: 601a str r2, [r3, #0]
/* Ensure the VFP is enabled - it should be anyway. */
vPortEnableVFP();
8004df8: f000 f8fc bl 8004ff4 <vPortEnableVFP>
/* Lazy save always. */
*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
8004dfc: 4b10 ldr r3, [pc, #64] ; (8004e40 <xPortStartScheduler+0x140>)
8004dfe: 681b ldr r3, [r3, #0]
8004e00: 4a0f ldr r2, [pc, #60] ; (8004e40 <xPortStartScheduler+0x140>)
8004e02: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000
8004e06: 6013 str r3, [r2, #0]
/* Start the first task. */
prvPortStartFirstTask();
8004e08: f7ff ff66 bl 8004cd8 <prvPortStartFirstTask>
exit error function to prevent compiler warnings about a static function
not being called in the case that the application writer overrides this
functionality by defining configTASK_RETURN_ADDRESS. Call
vTaskSwitchContext() so link time optimisation does not remove the
symbol. */
vTaskSwitchContext();
8004e0c: f7ff f84a bl 8003ea4 <vTaskSwitchContext>
prvTaskExitError();
8004e10: f7ff ff20 bl 8004c54 <prvTaskExitError>
/* Should not get here! */
return 0;
8004e14: 2300 movs r3, #0
}
8004e16: 4618 mov r0, r3
8004e18: 3718 adds r7, #24
8004e1a: 46bd mov sp, r7
8004e1c: bd80 pop {r7, pc}
8004e1e: bf00 nop
8004e20: e000ed00 .word 0xe000ed00
8004e24: 410fc271 .word 0x410fc271
8004e28: 410fc270 .word 0x410fc270
8004e2c: e000e400 .word 0xe000e400
8004e30: 20000eec .word 0x20000eec
8004e34: 20000ef0 .word 0x20000ef0
8004e38: e000ed20 .word 0xe000ed20
8004e3c: 2000000c .word 0x2000000c
8004e40: e000ef34 .word 0xe000ef34
08004e44 <vPortEnterCritical>:
configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/
void vPortEnterCritical( void )
{
8004e44: b480 push {r7}
8004e46: b083 sub sp, #12
8004e48: af00 add r7, sp, #0
__asm volatile
8004e4a: f04f 0350 mov.w r3, #80 ; 0x50
8004e4e: f383 8811 msr BASEPRI, r3
8004e52: f3bf 8f6f isb sy
8004e56: f3bf 8f4f dsb sy
8004e5a: 607b str r3, [r7, #4]
}
8004e5c: bf00 nop
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
8004e5e: 4b0f ldr r3, [pc, #60] ; (8004e9c <vPortEnterCritical+0x58>)
8004e60: 681b ldr r3, [r3, #0]
8004e62: 3301 adds r3, #1
8004e64: 4a0d ldr r2, [pc, #52] ; (8004e9c <vPortEnterCritical+0x58>)
8004e66: 6013 str r3, [r2, #0]
/* This is not the interrupt safe version of the enter critical function so
assert() if it is being called from an interrupt context. Only API
functions that end in "FromISR" can be used in an interrupt. Only assert if
the critical nesting count is 1 to protect against recursive calls if the
assert function also uses a critical section. */
if( uxCriticalNesting == 1 )
8004e68: 4b0c ldr r3, [pc, #48] ; (8004e9c <vPortEnterCritical+0x58>)
8004e6a: 681b ldr r3, [r3, #0]
8004e6c: 2b01 cmp r3, #1
8004e6e: d10f bne.n 8004e90 <vPortEnterCritical+0x4c>
{
configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
8004e70: 4b0b ldr r3, [pc, #44] ; (8004ea0 <vPortEnterCritical+0x5c>)
8004e72: 681b ldr r3, [r3, #0]
8004e74: b2db uxtb r3, r3
8004e76: 2b00 cmp r3, #0
8004e78: d00a beq.n 8004e90 <vPortEnterCritical+0x4c>
__asm volatile
8004e7a: f04f 0350 mov.w r3, #80 ; 0x50
8004e7e: f383 8811 msr BASEPRI, r3
8004e82: f3bf 8f6f isb sy
8004e86: f3bf 8f4f dsb sy
8004e8a: 603b str r3, [r7, #0]
}
8004e8c: bf00 nop
8004e8e: e7fe b.n 8004e8e <vPortEnterCritical+0x4a>
}
}
8004e90: bf00 nop
8004e92: 370c adds r7, #12
8004e94: 46bd mov sp, r7
8004e96: f85d 7b04 ldr.w r7, [sp], #4
8004e9a: 4770 bx lr
8004e9c: 2000000c .word 0x2000000c
8004ea0: e000ed04 .word 0xe000ed04
08004ea4 <vPortExitCritical>:
/*-----------------------------------------------------------*/
void vPortExitCritical( void )
{
8004ea4: b480 push {r7}
8004ea6: b083 sub sp, #12
8004ea8: af00 add r7, sp, #0
configASSERT( uxCriticalNesting );
8004eaa: 4b12 ldr r3, [pc, #72] ; (8004ef4 <vPortExitCritical+0x50>)
8004eac: 681b ldr r3, [r3, #0]
8004eae: 2b00 cmp r3, #0
8004eb0: d10a bne.n 8004ec8 <vPortExitCritical+0x24>
__asm volatile
8004eb2: f04f 0350 mov.w r3, #80 ; 0x50
8004eb6: f383 8811 msr BASEPRI, r3
8004eba: f3bf 8f6f isb sy
8004ebe: f3bf 8f4f dsb sy
8004ec2: 607b str r3, [r7, #4]
}
8004ec4: bf00 nop
8004ec6: e7fe b.n 8004ec6 <vPortExitCritical+0x22>
uxCriticalNesting--;
8004ec8: 4b0a ldr r3, [pc, #40] ; (8004ef4 <vPortExitCritical+0x50>)
8004eca: 681b ldr r3, [r3, #0]
8004ecc: 3b01 subs r3, #1
8004ece: 4a09 ldr r2, [pc, #36] ; (8004ef4 <vPortExitCritical+0x50>)
8004ed0: 6013 str r3, [r2, #0]
if( uxCriticalNesting == 0 )
8004ed2: 4b08 ldr r3, [pc, #32] ; (8004ef4 <vPortExitCritical+0x50>)
8004ed4: 681b ldr r3, [r3, #0]
8004ed6: 2b00 cmp r3, #0
8004ed8: d105 bne.n 8004ee6 <vPortExitCritical+0x42>
8004eda: 2300 movs r3, #0
8004edc: 603b str r3, [r7, #0]
__asm volatile
8004ede: 683b ldr r3, [r7, #0]
8004ee0: f383 8811 msr BASEPRI, r3
}
8004ee4: bf00 nop
{
portENABLE_INTERRUPTS();
}
}
8004ee6: bf00 nop
8004ee8: 370c adds r7, #12
8004eea: 46bd mov sp, r7
8004eec: f85d 7b04 ldr.w r7, [sp], #4
8004ef0: 4770 bx lr
8004ef2: bf00 nop
8004ef4: 2000000c .word 0x2000000c
...
08004f00 <PendSV_Handler>:
void xPortPendSVHandler( void )
{
/* This is a naked function. */
__asm volatile
8004f00: f3ef 8009 mrs r0, PSP
8004f04: f3bf 8f6f isb sy
8004f08: 4b15 ldr r3, [pc, #84] ; (8004f60 <pxCurrentTCBConst>)
8004f0a: 681a ldr r2, [r3, #0]
8004f0c: f01e 0f10 tst.w lr, #16
8004f10: bf08 it eq
8004f12: ed20 8a10 vstmdbeq r0!, {s16-s31}
8004f16: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004f1a: 6010 str r0, [r2, #0]
8004f1c: e92d 0009 stmdb sp!, {r0, r3}
8004f20: f04f 0050 mov.w r0, #80 ; 0x50
8004f24: f380 8811 msr BASEPRI, r0
8004f28: f3bf 8f4f dsb sy
8004f2c: f3bf 8f6f isb sy
8004f30: f7fe ffb8 bl 8003ea4 <vTaskSwitchContext>
8004f34: f04f 0000 mov.w r0, #0
8004f38: f380 8811 msr BASEPRI, r0
8004f3c: bc09 pop {r0, r3}
8004f3e: 6819 ldr r1, [r3, #0]
8004f40: 6808 ldr r0, [r1, #0]
8004f42: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
8004f46: f01e 0f10 tst.w lr, #16
8004f4a: bf08 it eq
8004f4c: ecb0 8a10 vldmiaeq r0!, {s16-s31}
8004f50: f380 8809 msr PSP, r0
8004f54: f3bf 8f6f isb sy
8004f58: 4770 bx lr
8004f5a: bf00 nop
8004f5c: f3af 8000 nop.w
08004f60 <pxCurrentTCBConst>:
8004f60: 200008c0 .word 0x200008c0
" \n"
" .align 4 \n"
"pxCurrentTCBConst: .word pxCurrentTCB \n"
::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
);
}
8004f64: bf00 nop
8004f66: bf00 nop
08004f68 <xPortSysTickHandler>:
/*-----------------------------------------------------------*/
void xPortSysTickHandler( void )
{
8004f68: b580 push {r7, lr}
8004f6a: b082 sub sp, #8
8004f6c: af00 add r7, sp, #0
__asm volatile
8004f6e: f04f 0350 mov.w r3, #80 ; 0x50
8004f72: f383 8811 msr BASEPRI, r3
8004f76: f3bf 8f6f isb sy
8004f7a: f3bf 8f4f dsb sy
8004f7e: 607b str r3, [r7, #4]
}
8004f80: bf00 nop
save and then restore the interrupt mask value as its value is already
known. */
portDISABLE_INTERRUPTS();
{
/* Increment the RTOS tick. */
if( xTaskIncrementTick() != pdFALSE )
8004f82: f7fe fed5 bl 8003d30 <xTaskIncrementTick>
8004f86: 4603 mov r3, r0
8004f88: 2b00 cmp r3, #0
8004f8a: d003 beq.n 8004f94 <xPortSysTickHandler+0x2c>
{
/* A context switch is required. Context switching is performed in
the PendSV interrupt. Pend the PendSV interrupt. */
portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
8004f8c: 4b06 ldr r3, [pc, #24] ; (8004fa8 <xPortSysTickHandler+0x40>)
8004f8e: f04f 5280 mov.w r2, #268435456 ; 0x10000000
8004f92: 601a str r2, [r3, #0]
8004f94: 2300 movs r3, #0
8004f96: 603b str r3, [r7, #0]
__asm volatile
8004f98: 683b ldr r3, [r7, #0]
8004f9a: f383 8811 msr BASEPRI, r3
}
8004f9e: bf00 nop
}
}
portENABLE_INTERRUPTS();
}
8004fa0: bf00 nop
8004fa2: 3708 adds r7, #8
8004fa4: 46bd mov sp, r7
8004fa6: bd80 pop {r7, pc}
8004fa8: e000ed04 .word 0xe000ed04
08004fac <vPortSetupTimerInterrupt>:
/*
* Setup the systick timer to generate the tick interrupts at the required
* frequency.
*/
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
8004fac: b480 push {r7}
8004fae: af00 add r7, sp, #0
ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
}
#endif /* configUSE_TICKLESS_IDLE */
/* Stop and clear the SysTick. */
portNVIC_SYSTICK_CTRL_REG = 0UL;
8004fb0: 4b0b ldr r3, [pc, #44] ; (8004fe0 <vPortSetupTimerInterrupt+0x34>)
8004fb2: 2200 movs r2, #0
8004fb4: 601a str r2, [r3, #0]
portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
8004fb6: 4b0b ldr r3, [pc, #44] ; (8004fe4 <vPortSetupTimerInterrupt+0x38>)
8004fb8: 2200 movs r2, #0
8004fba: 601a str r2, [r3, #0]
/* Configure SysTick to interrupt at the requested rate. */
portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
8004fbc: 4b0a ldr r3, [pc, #40] ; (8004fe8 <vPortSetupTimerInterrupt+0x3c>)
8004fbe: 681b ldr r3, [r3, #0]
8004fc0: 4a0a ldr r2, [pc, #40] ; (8004fec <vPortSetupTimerInterrupt+0x40>)
8004fc2: fba2 2303 umull r2, r3, r2, r3
8004fc6: 099b lsrs r3, r3, #6
8004fc8: 4a09 ldr r2, [pc, #36] ; (8004ff0 <vPortSetupTimerInterrupt+0x44>)
8004fca: 3b01 subs r3, #1
8004fcc: 6013 str r3, [r2, #0]
portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
8004fce: 4b04 ldr r3, [pc, #16] ; (8004fe0 <vPortSetupTimerInterrupt+0x34>)
8004fd0: 2207 movs r2, #7
8004fd2: 601a str r2, [r3, #0]
}
8004fd4: bf00 nop
8004fd6: 46bd mov sp, r7
8004fd8: f85d 7b04 ldr.w r7, [sp], #4
8004fdc: 4770 bx lr
8004fde: bf00 nop
8004fe0: e000e010 .word 0xe000e010
8004fe4: e000e018 .word 0xe000e018
8004fe8: 20000000 .word 0x20000000
8004fec: 10624dd3 .word 0x10624dd3
8004ff0: e000e014 .word 0xe000e014
08004ff4 <vPortEnableVFP>:
/*-----------------------------------------------------------*/
/* This is a naked function. */
static void vPortEnableVFP( void )
{
__asm volatile
8004ff4: f8df 000c ldr.w r0, [pc, #12] ; 8005004 <vPortEnableVFP+0x10>
8004ff8: 6801 ldr r1, [r0, #0]
8004ffa: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000
8004ffe: 6001 str r1, [r0, #0]
8005000: 4770 bx lr
" \n"
" orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
" str r1, [r0] \n"
" bx r14 "
);
}
8005002: bf00 nop
8005004: e000ed88 .word 0xe000ed88
08005008 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/
#if( configASSERT_DEFINED == 1 )
void vPortValidateInterruptPriority( void )
{
8005008: b480 push {r7}
800500a: b085 sub sp, #20
800500c: af00 add r7, sp, #0
uint32_t ulCurrentInterrupt;
uint8_t ucCurrentPriority;
/* Obtain the number of the currently executing interrupt. */
__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
800500e: f3ef 8305 mrs r3, IPSR
8005012: 60fb str r3, [r7, #12]
/* Is the interrupt number a user defined interrupt? */
if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
8005014: 68fb ldr r3, [r7, #12]
8005016: 2b0f cmp r3, #15
8005018: d914 bls.n 8005044 <vPortValidateInterruptPriority+0x3c>
{
/* Look up the interrupt's priority. */
ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
800501a: 4a17 ldr r2, [pc, #92] ; (8005078 <vPortValidateInterruptPriority+0x70>)
800501c: 68fb ldr r3, [r7, #12]
800501e: 4413 add r3, r2
8005020: 781b ldrb r3, [r3, #0]
8005022: 72fb strb r3, [r7, #11]
interrupt entry is as fast and simple as possible.
The following links provide detailed information:
http://www.freertos.org/RTOS-Cortex-M3-M4.html
http://www.freertos.org/FAQHelp.html */
configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
8005024: 4b15 ldr r3, [pc, #84] ; (800507c <vPortValidateInterruptPriority+0x74>)
8005026: 781b ldrb r3, [r3, #0]
8005028: 7afa ldrb r2, [r7, #11]
800502a: 429a cmp r2, r3
800502c: d20a bcs.n 8005044 <vPortValidateInterruptPriority+0x3c>
__asm volatile
800502e: f04f 0350 mov.w r3, #80 ; 0x50
8005032: f383 8811 msr BASEPRI, r3
8005036: f3bf 8f6f isb sy
800503a: f3bf 8f4f dsb sy
800503e: 607b str r3, [r7, #4]
}
8005040: bf00 nop
8005042: e7fe b.n 8005042 <vPortValidateInterruptPriority+0x3a>
configuration then the correct setting can be achieved on all Cortex-M
devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
scheduler. Note however that some vendor specific peripheral libraries
assume a non-zero priority group setting, in which cases using a value
of zero will result in unpredictable behaviour. */
configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
8005044: 4b0e ldr r3, [pc, #56] ; (8005080 <vPortValidateInterruptPriority+0x78>)
8005046: 681b ldr r3, [r3, #0]
8005048: f403 62e0 and.w r2, r3, #1792 ; 0x700
800504c: 4b0d ldr r3, [pc, #52] ; (8005084 <vPortValidateInterruptPriority+0x7c>)
800504e: 681b ldr r3, [r3, #0]
8005050: 429a cmp r2, r3
8005052: d90a bls.n 800506a <vPortValidateInterruptPriority+0x62>
__asm volatile
8005054: f04f 0350 mov.w r3, #80 ; 0x50
8005058: f383 8811 msr BASEPRI, r3
800505c: f3bf 8f6f isb sy
8005060: f3bf 8f4f dsb sy
8005064: 603b str r3, [r7, #0]
}
8005066: bf00 nop
8005068: e7fe b.n 8005068 <vPortValidateInterruptPriority+0x60>
}
800506a: bf00 nop
800506c: 3714 adds r7, #20
800506e: 46bd mov sp, r7
8005070: f85d 7b04 ldr.w r7, [sp], #4
8005074: 4770 bx lr
8005076: bf00 nop
8005078: e000e3f0 .word 0xe000e3f0
800507c: 20000eec .word 0x20000eec
8005080: e000ed0c .word 0xe000ed0c
8005084: 20000ef0 .word 0x20000ef0
08005088 <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;
/*-----------------------------------------------------------*/
void *pvPortMalloc( size_t xWantedSize )
{
8005088: b580 push {r7, lr}
800508a: b08a sub sp, #40 ; 0x28
800508c: af00 add r7, sp, #0
800508e: 6078 str r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
8005090: 2300 movs r3, #0
8005092: 61fb str r3, [r7, #28]
vTaskSuspendAll();
8005094: f7fe fd90 bl 8003bb8 <vTaskSuspendAll>
{
/* If this is the first call to malloc then the heap will require
initialisation to setup the list of free blocks. */
if( pxEnd == NULL )
8005098: 4b5b ldr r3, [pc, #364] ; (8005208 <pvPortMalloc+0x180>)
800509a: 681b ldr r3, [r3, #0]
800509c: 2b00 cmp r3, #0
800509e: d101 bne.n 80050a4 <pvPortMalloc+0x1c>
{
prvHeapInit();
80050a0: f000 f920 bl 80052e4 <prvHeapInit>
/* Check the requested block size is not so large that the top bit is
set. The top bit of the block size member of the BlockLink_t structure
is used to determine who owns the block - the application or the
kernel, so it must be free. */
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
80050a4: 4b59 ldr r3, [pc, #356] ; (800520c <pvPortMalloc+0x184>)
80050a6: 681a ldr r2, [r3, #0]
80050a8: 687b ldr r3, [r7, #4]
80050aa: 4013 ands r3, r2
80050ac: 2b00 cmp r3, #0
80050ae: f040 8093 bne.w 80051d8 <pvPortMalloc+0x150>
{
/* The wanted size is increased so it can contain a BlockLink_t
structure in addition to the requested amount of bytes. */
if( xWantedSize > 0 )
80050b2: 687b ldr r3, [r7, #4]
80050b4: 2b00 cmp r3, #0
80050b6: d01d beq.n 80050f4 <pvPortMalloc+0x6c>
{
xWantedSize += xHeapStructSize;
80050b8: 2208 movs r2, #8
80050ba: 687b ldr r3, [r7, #4]
80050bc: 4413 add r3, r2
80050be: 607b str r3, [r7, #4]
/* Ensure that blocks are always aligned to the required number
of bytes. */
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
80050c0: 687b ldr r3, [r7, #4]
80050c2: f003 0307 and.w r3, r3, #7
80050c6: 2b00 cmp r3, #0
80050c8: d014 beq.n 80050f4 <pvPortMalloc+0x6c>
{
/* Byte alignment required. */
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
80050ca: 687b ldr r3, [r7, #4]
80050cc: f023 0307 bic.w r3, r3, #7
80050d0: 3308 adds r3, #8
80050d2: 607b str r3, [r7, #4]
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
80050d4: 687b ldr r3, [r7, #4]
80050d6: f003 0307 and.w r3, r3, #7
80050da: 2b00 cmp r3, #0
80050dc: d00a beq.n 80050f4 <pvPortMalloc+0x6c>
__asm volatile
80050de: f04f 0350 mov.w r3, #80 ; 0x50
80050e2: f383 8811 msr BASEPRI, r3
80050e6: f3bf 8f6f isb sy
80050ea: f3bf 8f4f dsb sy
80050ee: 617b str r3, [r7, #20]
}
80050f0: bf00 nop
80050f2: e7fe b.n 80050f2 <pvPortMalloc+0x6a>
else
{
mtCOVERAGE_TEST_MARKER();
}
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
80050f4: 687b ldr r3, [r7, #4]
80050f6: 2b00 cmp r3, #0
80050f8: d06e beq.n 80051d8 <pvPortMalloc+0x150>
80050fa: 4b45 ldr r3, [pc, #276] ; (8005210 <pvPortMalloc+0x188>)
80050fc: 681b ldr r3, [r3, #0]
80050fe: 687a ldr r2, [r7, #4]
8005100: 429a cmp r2, r3
8005102: d869 bhi.n 80051d8 <pvPortMalloc+0x150>
{
/* Traverse the list from the start (lowest address) block until
one of adequate size is found. */
pxPreviousBlock = &xStart;
8005104: 4b43 ldr r3, [pc, #268] ; (8005214 <pvPortMalloc+0x18c>)
8005106: 623b str r3, [r7, #32]
pxBlock = xStart.pxNextFreeBlock;
8005108: 4b42 ldr r3, [pc, #264] ; (8005214 <pvPortMalloc+0x18c>)
800510a: 681b ldr r3, [r3, #0]
800510c: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800510e: e004 b.n 800511a <pvPortMalloc+0x92>
{
pxPreviousBlock = pxBlock;
8005110: 6a7b ldr r3, [r7, #36] ; 0x24
8005112: 623b str r3, [r7, #32]
pxBlock = pxBlock->pxNextFreeBlock;
8005114: 6a7b ldr r3, [r7, #36] ; 0x24
8005116: 681b ldr r3, [r3, #0]
8005118: 627b str r3, [r7, #36] ; 0x24
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
800511a: 6a7b ldr r3, [r7, #36] ; 0x24
800511c: 685b ldr r3, [r3, #4]
800511e: 687a ldr r2, [r7, #4]
8005120: 429a cmp r2, r3
8005122: d903 bls.n 800512c <pvPortMalloc+0xa4>
8005124: 6a7b ldr r3, [r7, #36] ; 0x24
8005126: 681b ldr r3, [r3, #0]
8005128: 2b00 cmp r3, #0
800512a: d1f1 bne.n 8005110 <pvPortMalloc+0x88>
}
/* If the end marker was reached then a block of adequate size
was not found. */
if( pxBlock != pxEnd )
800512c: 4b36 ldr r3, [pc, #216] ; (8005208 <pvPortMalloc+0x180>)
800512e: 681b ldr r3, [r3, #0]
8005130: 6a7a ldr r2, [r7, #36] ; 0x24
8005132: 429a cmp r2, r3
8005134: d050 beq.n 80051d8 <pvPortMalloc+0x150>
{
/* Return the memory space pointed to - jumping over the
BlockLink_t structure at its start. */
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
8005136: 6a3b ldr r3, [r7, #32]
8005138: 681b ldr r3, [r3, #0]
800513a: 2208 movs r2, #8
800513c: 4413 add r3, r2
800513e: 61fb str r3, [r7, #28]
/* This block is being returned for use so must be taken out
of the list of free blocks. */
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
8005140: 6a7b ldr r3, [r7, #36] ; 0x24
8005142: 681a ldr r2, [r3, #0]
8005144: 6a3b ldr r3, [r7, #32]
8005146: 601a str r2, [r3, #0]
/* If the block is larger than required it can be split into
two. */
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
8005148: 6a7b ldr r3, [r7, #36] ; 0x24
800514a: 685a ldr r2, [r3, #4]
800514c: 687b ldr r3, [r7, #4]
800514e: 1ad2 subs r2, r2, r3
8005150: 2308 movs r3, #8
8005152: 005b lsls r3, r3, #1
8005154: 429a cmp r2, r3
8005156: d91f bls.n 8005198 <pvPortMalloc+0x110>
{
/* This block is to be split into two. Create a new
block following the number of bytes requested. The void
cast is used to prevent byte alignment warnings from the
compiler. */
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
8005158: 6a7a ldr r2, [r7, #36] ; 0x24
800515a: 687b ldr r3, [r7, #4]
800515c: 4413 add r3, r2
800515e: 61bb str r3, [r7, #24]
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
8005160: 69bb ldr r3, [r7, #24]
8005162: f003 0307 and.w r3, r3, #7
8005166: 2b00 cmp r3, #0
8005168: d00a beq.n 8005180 <pvPortMalloc+0xf8>
__asm volatile
800516a: f04f 0350 mov.w r3, #80 ; 0x50
800516e: f383 8811 msr BASEPRI, r3
8005172: f3bf 8f6f isb sy
8005176: f3bf 8f4f dsb sy
800517a: 613b str r3, [r7, #16]
}
800517c: bf00 nop
800517e: e7fe b.n 800517e <pvPortMalloc+0xf6>
/* Calculate the sizes of two blocks split from the
single block. */
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
8005180: 6a7b ldr r3, [r7, #36] ; 0x24
8005182: 685a ldr r2, [r3, #4]
8005184: 687b ldr r3, [r7, #4]
8005186: 1ad2 subs r2, r2, r3
8005188: 69bb ldr r3, [r7, #24]
800518a: 605a str r2, [r3, #4]
pxBlock->xBlockSize = xWantedSize;
800518c: 6a7b ldr r3, [r7, #36] ; 0x24
800518e: 687a ldr r2, [r7, #4]
8005190: 605a str r2, [r3, #4]
/* Insert the new block into the list of free blocks. */
prvInsertBlockIntoFreeList( pxNewBlockLink );
8005192: 69b8 ldr r0, [r7, #24]
8005194: f000 f908 bl 80053a8 <prvInsertBlockIntoFreeList>
else
{
mtCOVERAGE_TEST_MARKER();
}
xFreeBytesRemaining -= pxBlock->xBlockSize;
8005198: 4b1d ldr r3, [pc, #116] ; (8005210 <pvPortMalloc+0x188>)
800519a: 681a ldr r2, [r3, #0]
800519c: 6a7b ldr r3, [r7, #36] ; 0x24
800519e: 685b ldr r3, [r3, #4]
80051a0: 1ad3 subs r3, r2, r3
80051a2: 4a1b ldr r2, [pc, #108] ; (8005210 <pvPortMalloc+0x188>)
80051a4: 6013 str r3, [r2, #0]
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
80051a6: 4b1a ldr r3, [pc, #104] ; (8005210 <pvPortMalloc+0x188>)
80051a8: 681a ldr r2, [r3, #0]
80051aa: 4b1b ldr r3, [pc, #108] ; (8005218 <pvPortMalloc+0x190>)
80051ac: 681b ldr r3, [r3, #0]
80051ae: 429a cmp r2, r3
80051b0: d203 bcs.n 80051ba <pvPortMalloc+0x132>
{
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
80051b2: 4b17 ldr r3, [pc, #92] ; (8005210 <pvPortMalloc+0x188>)
80051b4: 681b ldr r3, [r3, #0]
80051b6: 4a18 ldr r2, [pc, #96] ; (8005218 <pvPortMalloc+0x190>)
80051b8: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
/* The block is being returned - it is allocated and owned
by the application and has no "next" block. */
pxBlock->xBlockSize |= xBlockAllocatedBit;
80051ba: 6a7b ldr r3, [r7, #36] ; 0x24
80051bc: 685a ldr r2, [r3, #4]
80051be: 4b13 ldr r3, [pc, #76] ; (800520c <pvPortMalloc+0x184>)
80051c0: 681b ldr r3, [r3, #0]
80051c2: 431a orrs r2, r3
80051c4: 6a7b ldr r3, [r7, #36] ; 0x24
80051c6: 605a str r2, [r3, #4]
pxBlock->pxNextFreeBlock = NULL;
80051c8: 6a7b ldr r3, [r7, #36] ; 0x24
80051ca: 2200 movs r2, #0
80051cc: 601a str r2, [r3, #0]
xNumberOfSuccessfulAllocations++;
80051ce: 4b13 ldr r3, [pc, #76] ; (800521c <pvPortMalloc+0x194>)
80051d0: 681b ldr r3, [r3, #0]
80051d2: 3301 adds r3, #1
80051d4: 4a11 ldr r2, [pc, #68] ; (800521c <pvPortMalloc+0x194>)
80051d6: 6013 str r3, [r2, #0]
mtCOVERAGE_TEST_MARKER();
}
traceMALLOC( pvReturn, xWantedSize );
}
( void ) xTaskResumeAll();
80051d8: f7fe fcfc bl 8003bd4 <xTaskResumeAll>
mtCOVERAGE_TEST_MARKER();
}
}
#endif
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
80051dc: 69fb ldr r3, [r7, #28]
80051de: f003 0307 and.w r3, r3, #7
80051e2: 2b00 cmp r3, #0
80051e4: d00a beq.n 80051fc <pvPortMalloc+0x174>
__asm volatile
80051e6: f04f 0350 mov.w r3, #80 ; 0x50
80051ea: f383 8811 msr BASEPRI, r3
80051ee: f3bf 8f6f isb sy
80051f2: f3bf 8f4f dsb sy
80051f6: 60fb str r3, [r7, #12]
}
80051f8: bf00 nop
80051fa: e7fe b.n 80051fa <pvPortMalloc+0x172>
return pvReturn;
80051fc: 69fb ldr r3, [r7, #28]
}
80051fe: 4618 mov r0, r3
8005200: 3728 adds r7, #40 ; 0x28
8005202: 46bd mov sp, r7
8005204: bd80 pop {r7, pc}
8005206: bf00 nop
8005208: 20004afc .word 0x20004afc
800520c: 20004b10 .word 0x20004b10
8005210: 20004b00 .word 0x20004b00
8005214: 20004af4 .word 0x20004af4
8005218: 20004b04 .word 0x20004b04
800521c: 20004b08 .word 0x20004b08
08005220 <vPortFree>:
/*-----------------------------------------------------------*/
void vPortFree( void *pv )
{
8005220: b580 push {r7, lr}
8005222: b086 sub sp, #24
8005224: af00 add r7, sp, #0
8005226: 6078 str r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
8005228: 687b ldr r3, [r7, #4]
800522a: 617b str r3, [r7, #20]
BlockLink_t *pxLink;
if( pv != NULL )
800522c: 687b ldr r3, [r7, #4]
800522e: 2b00 cmp r3, #0
8005230: d04d beq.n 80052ce <vPortFree+0xae>
{
/* The memory being freed will have an BlockLink_t structure immediately
before it. */
puc -= xHeapStructSize;
8005232: 2308 movs r3, #8
8005234: 425b negs r3, r3
8005236: 697a ldr r2, [r7, #20]
8005238: 4413 add r3, r2
800523a: 617b str r3, [r7, #20]
/* This casting is to keep the compiler from issuing warnings. */
pxLink = ( void * ) puc;
800523c: 697b ldr r3, [r7, #20]
800523e: 613b str r3, [r7, #16]
/* Check the block is actually allocated. */
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
8005240: 693b ldr r3, [r7, #16]
8005242: 685a ldr r2, [r3, #4]
8005244: 4b24 ldr r3, [pc, #144] ; (80052d8 <vPortFree+0xb8>)
8005246: 681b ldr r3, [r3, #0]
8005248: 4013 ands r3, r2
800524a: 2b00 cmp r3, #0
800524c: d10a bne.n 8005264 <vPortFree+0x44>
__asm volatile
800524e: f04f 0350 mov.w r3, #80 ; 0x50
8005252: f383 8811 msr BASEPRI, r3
8005256: f3bf 8f6f isb sy
800525a: f3bf 8f4f dsb sy
800525e: 60fb str r3, [r7, #12]
}
8005260: bf00 nop
8005262: e7fe b.n 8005262 <vPortFree+0x42>
configASSERT( pxLink->pxNextFreeBlock == NULL );
8005264: 693b ldr r3, [r7, #16]
8005266: 681b ldr r3, [r3, #0]
8005268: 2b00 cmp r3, #0
800526a: d00a beq.n 8005282 <vPortFree+0x62>
__asm volatile
800526c: f04f 0350 mov.w r3, #80 ; 0x50
8005270: f383 8811 msr BASEPRI, r3
8005274: f3bf 8f6f isb sy
8005278: f3bf 8f4f dsb sy
800527c: 60bb str r3, [r7, #8]
}
800527e: bf00 nop
8005280: e7fe b.n 8005280 <vPortFree+0x60>
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
8005282: 693b ldr r3, [r7, #16]
8005284: 685a ldr r2, [r3, #4]
8005286: 4b14 ldr r3, [pc, #80] ; (80052d8 <vPortFree+0xb8>)
8005288: 681b ldr r3, [r3, #0]
800528a: 4013 ands r3, r2
800528c: 2b00 cmp r3, #0
800528e: d01e beq.n 80052ce <vPortFree+0xae>
{
if( pxLink->pxNextFreeBlock == NULL )
8005290: 693b ldr r3, [r7, #16]
8005292: 681b ldr r3, [r3, #0]
8005294: 2b00 cmp r3, #0
8005296: d11a bne.n 80052ce <vPortFree+0xae>
{
/* The block is being returned to the heap - it is no longer
allocated. */
pxLink->xBlockSize &= ~xBlockAllocatedBit;
8005298: 693b ldr r3, [r7, #16]
800529a: 685a ldr r2, [r3, #4]
800529c: 4b0e ldr r3, [pc, #56] ; (80052d8 <vPortFree+0xb8>)
800529e: 681b ldr r3, [r3, #0]
80052a0: 43db mvns r3, r3
80052a2: 401a ands r2, r3
80052a4: 693b ldr r3, [r7, #16]
80052a6: 605a str r2, [r3, #4]
vTaskSuspendAll();
80052a8: f7fe fc86 bl 8003bb8 <vTaskSuspendAll>
{
/* Add this block to the list of free blocks. */
xFreeBytesRemaining += pxLink->xBlockSize;
80052ac: 693b ldr r3, [r7, #16]
80052ae: 685a ldr r2, [r3, #4]
80052b0: 4b0a ldr r3, [pc, #40] ; (80052dc <vPortFree+0xbc>)
80052b2: 681b ldr r3, [r3, #0]
80052b4: 4413 add r3, r2
80052b6: 4a09 ldr r2, [pc, #36] ; (80052dc <vPortFree+0xbc>)
80052b8: 6013 str r3, [r2, #0]
traceFREE( pv, pxLink->xBlockSize );
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
80052ba: 6938 ldr r0, [r7, #16]
80052bc: f000 f874 bl 80053a8 <prvInsertBlockIntoFreeList>
xNumberOfSuccessfulFrees++;
80052c0: 4b07 ldr r3, [pc, #28] ; (80052e0 <vPortFree+0xc0>)
80052c2: 681b ldr r3, [r3, #0]
80052c4: 3301 adds r3, #1
80052c6: 4a06 ldr r2, [pc, #24] ; (80052e0 <vPortFree+0xc0>)
80052c8: 6013 str r3, [r2, #0]
}
( void ) xTaskResumeAll();
80052ca: f7fe fc83 bl 8003bd4 <xTaskResumeAll>
else
{
mtCOVERAGE_TEST_MARKER();
}
}
}
80052ce: bf00 nop
80052d0: 3718 adds r7, #24
80052d2: 46bd mov sp, r7
80052d4: bd80 pop {r7, pc}
80052d6: bf00 nop
80052d8: 20004b10 .word 0x20004b10
80052dc: 20004b00 .word 0x20004b00
80052e0: 20004b0c .word 0x20004b0c
080052e4 <prvHeapInit>:
/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/
static void prvHeapInit( void )
{
80052e4: b480 push {r7}
80052e6: b085 sub sp, #20
80052e8: af00 add r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
80052ea: f44f 5370 mov.w r3, #15360 ; 0x3c00
80052ee: 60bb str r3, [r7, #8]
/* Ensure the heap starts on a correctly aligned boundary. */
uxAddress = ( size_t ) ucHeap;
80052f0: 4b27 ldr r3, [pc, #156] ; (8005390 <prvHeapInit+0xac>)
80052f2: 60fb str r3, [r7, #12]
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
80052f4: 68fb ldr r3, [r7, #12]
80052f6: f003 0307 and.w r3, r3, #7
80052fa: 2b00 cmp r3, #0
80052fc: d00c beq.n 8005318 <prvHeapInit+0x34>
{
uxAddress += ( portBYTE_ALIGNMENT - 1 );
80052fe: 68fb ldr r3, [r7, #12]
8005300: 3307 adds r3, #7
8005302: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
8005304: 68fb ldr r3, [r7, #12]
8005306: f023 0307 bic.w r3, r3, #7
800530a: 60fb str r3, [r7, #12]
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
800530c: 68ba ldr r2, [r7, #8]
800530e: 68fb ldr r3, [r7, #12]
8005310: 1ad3 subs r3, r2, r3
8005312: 4a1f ldr r2, [pc, #124] ; (8005390 <prvHeapInit+0xac>)
8005314: 4413 add r3, r2
8005316: 60bb str r3, [r7, #8]
}
pucAlignedHeap = ( uint8_t * ) uxAddress;
8005318: 68fb ldr r3, [r7, #12]
800531a: 607b str r3, [r7, #4]
/* xStart is used to hold a pointer to the first item in the list of free
blocks. The void cast is used to prevent compiler warnings. */
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
800531c: 4a1d ldr r2, [pc, #116] ; (8005394 <prvHeapInit+0xb0>)
800531e: 687b ldr r3, [r7, #4]
8005320: 6013 str r3, [r2, #0]
xStart.xBlockSize = ( size_t ) 0;
8005322: 4b1c ldr r3, [pc, #112] ; (8005394 <prvHeapInit+0xb0>)
8005324: 2200 movs r2, #0
8005326: 605a str r2, [r3, #4]
/* pxEnd is used to mark the end of the list of free blocks and is inserted
at the end of the heap space. */
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
8005328: 687b ldr r3, [r7, #4]
800532a: 68ba ldr r2, [r7, #8]
800532c: 4413 add r3, r2
800532e: 60fb str r3, [r7, #12]
uxAddress -= xHeapStructSize;
8005330: 2208 movs r2, #8
8005332: 68fb ldr r3, [r7, #12]
8005334: 1a9b subs r3, r3, r2
8005336: 60fb str r3, [r7, #12]
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
8005338: 68fb ldr r3, [r7, #12]
800533a: f023 0307 bic.w r3, r3, #7
800533e: 60fb str r3, [r7, #12]
pxEnd = ( void * ) uxAddress;
8005340: 68fb ldr r3, [r7, #12]
8005342: 4a15 ldr r2, [pc, #84] ; (8005398 <prvHeapInit+0xb4>)
8005344: 6013 str r3, [r2, #0]
pxEnd->xBlockSize = 0;
8005346: 4b14 ldr r3, [pc, #80] ; (8005398 <prvHeapInit+0xb4>)
8005348: 681b ldr r3, [r3, #0]
800534a: 2200 movs r2, #0
800534c: 605a str r2, [r3, #4]
pxEnd->pxNextFreeBlock = NULL;
800534e: 4b12 ldr r3, [pc, #72] ; (8005398 <prvHeapInit+0xb4>)
8005350: 681b ldr r3, [r3, #0]
8005352: 2200 movs r2, #0
8005354: 601a str r2, [r3, #0]
/* To start with there is a single free block that is sized to take up the
entire heap space, minus the space taken by pxEnd. */
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
8005356: 687b ldr r3, [r7, #4]
8005358: 603b str r3, [r7, #0]
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
800535a: 683b ldr r3, [r7, #0]
800535c: 68fa ldr r2, [r7, #12]
800535e: 1ad2 subs r2, r2, r3
8005360: 683b ldr r3, [r7, #0]
8005362: 605a str r2, [r3, #4]
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
8005364: 4b0c ldr r3, [pc, #48] ; (8005398 <prvHeapInit+0xb4>)
8005366: 681a ldr r2, [r3, #0]
8005368: 683b ldr r3, [r7, #0]
800536a: 601a str r2, [r3, #0]
/* Only one block exists - and it covers the entire usable heap space. */
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
800536c: 683b ldr r3, [r7, #0]
800536e: 685b ldr r3, [r3, #4]
8005370: 4a0a ldr r2, [pc, #40] ; (800539c <prvHeapInit+0xb8>)
8005372: 6013 str r3, [r2, #0]
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
8005374: 683b ldr r3, [r7, #0]
8005376: 685b ldr r3, [r3, #4]
8005378: 4a09 ldr r2, [pc, #36] ; (80053a0 <prvHeapInit+0xbc>)
800537a: 6013 str r3, [r2, #0]
/* Work out the position of the top bit in a size_t variable. */
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
800537c: 4b09 ldr r3, [pc, #36] ; (80053a4 <prvHeapInit+0xc0>)
800537e: f04f 4200 mov.w r2, #2147483648 ; 0x80000000
8005382: 601a str r2, [r3, #0]
}
8005384: bf00 nop
8005386: 3714 adds r7, #20
8005388: 46bd mov sp, r7
800538a: f85d 7b04 ldr.w r7, [sp], #4
800538e: 4770 bx lr
8005390: 20000ef4 .word 0x20000ef4
8005394: 20004af4 .word 0x20004af4
8005398: 20004afc .word 0x20004afc
800539c: 20004b04 .word 0x20004b04
80053a0: 20004b00 .word 0x20004b00
80053a4: 20004b10 .word 0x20004b10
080053a8 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/
static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
80053a8: b480 push {r7}
80053aa: b085 sub sp, #20
80053ac: af00 add r7, sp, #0
80053ae: 6078 str r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;
/* Iterate through the list until a block is found that has a higher address
than the block being inserted. */
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
80053b0: 4b28 ldr r3, [pc, #160] ; (8005454 <prvInsertBlockIntoFreeList+0xac>)
80053b2: 60fb str r3, [r7, #12]
80053b4: e002 b.n 80053bc <prvInsertBlockIntoFreeList+0x14>
80053b6: 68fb ldr r3, [r7, #12]
80053b8: 681b ldr r3, [r3, #0]
80053ba: 60fb str r3, [r7, #12]
80053bc: 68fb ldr r3, [r7, #12]
80053be: 681b ldr r3, [r3, #0]
80053c0: 687a ldr r2, [r7, #4]
80053c2: 429a cmp r2, r3
80053c4: d8f7 bhi.n 80053b6 <prvInsertBlockIntoFreeList+0xe>
/* Nothing to do here, just iterate to the right position. */
}
/* Do the block being inserted, and the block it is being inserted after
make a contiguous block of memory? */
puc = ( uint8_t * ) pxIterator;
80053c6: 68fb ldr r3, [r7, #12]
80053c8: 60bb str r3, [r7, #8]
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
80053ca: 68fb ldr r3, [r7, #12]
80053cc: 685b ldr r3, [r3, #4]
80053ce: 68ba ldr r2, [r7, #8]
80053d0: 4413 add r3, r2
80053d2: 687a ldr r2, [r7, #4]
80053d4: 429a cmp r2, r3
80053d6: d108 bne.n 80053ea <prvInsertBlockIntoFreeList+0x42>
{
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
80053d8: 68fb ldr r3, [r7, #12]
80053da: 685a ldr r2, [r3, #4]
80053dc: 687b ldr r3, [r7, #4]
80053de: 685b ldr r3, [r3, #4]
80053e0: 441a add r2, r3
80053e2: 68fb ldr r3, [r7, #12]
80053e4: 605a str r2, [r3, #4]
pxBlockToInsert = pxIterator;
80053e6: 68fb ldr r3, [r7, #12]
80053e8: 607b str r3, [r7, #4]
mtCOVERAGE_TEST_MARKER();
}
/* Do the block being inserted, and the block it is being inserted before
make a contiguous block of memory? */
puc = ( uint8_t * ) pxBlockToInsert;
80053ea: 687b ldr r3, [r7, #4]
80053ec: 60bb str r3, [r7, #8]
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
80053ee: 687b ldr r3, [r7, #4]
80053f0: 685b ldr r3, [r3, #4]
80053f2: 68ba ldr r2, [r7, #8]
80053f4: 441a add r2, r3
80053f6: 68fb ldr r3, [r7, #12]
80053f8: 681b ldr r3, [r3, #0]
80053fa: 429a cmp r2, r3
80053fc: d118 bne.n 8005430 <prvInsertBlockIntoFreeList+0x88>
{
if( pxIterator->pxNextFreeBlock != pxEnd )
80053fe: 68fb ldr r3, [r7, #12]
8005400: 681a ldr r2, [r3, #0]
8005402: 4b15 ldr r3, [pc, #84] ; (8005458 <prvInsertBlockIntoFreeList+0xb0>)
8005404: 681b ldr r3, [r3, #0]
8005406: 429a cmp r2, r3
8005408: d00d beq.n 8005426 <prvInsertBlockIntoFreeList+0x7e>
{
/* Form one big block from the two blocks. */
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
800540a: 687b ldr r3, [r7, #4]
800540c: 685a ldr r2, [r3, #4]
800540e: 68fb ldr r3, [r7, #12]
8005410: 681b ldr r3, [r3, #0]
8005412: 685b ldr r3, [r3, #4]
8005414: 441a add r2, r3
8005416: 687b ldr r3, [r7, #4]
8005418: 605a str r2, [r3, #4]
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
800541a: 68fb ldr r3, [r7, #12]
800541c: 681b ldr r3, [r3, #0]
800541e: 681a ldr r2, [r3, #0]
8005420: 687b ldr r3, [r7, #4]
8005422: 601a str r2, [r3, #0]
8005424: e008 b.n 8005438 <prvInsertBlockIntoFreeList+0x90>
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxEnd;
8005426: 4b0c ldr r3, [pc, #48] ; (8005458 <prvInsertBlockIntoFreeList+0xb0>)
8005428: 681a ldr r2, [r3, #0]
800542a: 687b ldr r3, [r7, #4]
800542c: 601a str r2, [r3, #0]
800542e: e003 b.n 8005438 <prvInsertBlockIntoFreeList+0x90>
}
}
else
{
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
8005430: 68fb ldr r3, [r7, #12]
8005432: 681a ldr r2, [r3, #0]
8005434: 687b ldr r3, [r7, #4]
8005436: 601a str r2, [r3, #0]
/* If the block being inserted plugged a gab, so was merged with the block
before and the block after, then it's pxNextFreeBlock pointer will have
already been set, and should not be set here as that would make it point
to itself. */
if( pxIterator != pxBlockToInsert )
8005438: 68fa ldr r2, [r7, #12]
800543a: 687b ldr r3, [r7, #4]
800543c: 429a cmp r2, r3
800543e: d002 beq.n 8005446 <prvInsertBlockIntoFreeList+0x9e>
{
pxIterator->pxNextFreeBlock = pxBlockToInsert;
8005440: 68fb ldr r3, [r7, #12]
8005442: 687a ldr r2, [r7, #4]
8005444: 601a str r2, [r3, #0]
}
else
{
mtCOVERAGE_TEST_MARKER();
}
}
8005446: bf00 nop
8005448: 3714 adds r7, #20
800544a: 46bd mov sp, r7
800544c: f85d 7b04 ldr.w r7, [sp], #4
8005450: 4770 bx lr
8005452: bf00 nop
8005454: 20004af4 .word 0x20004af4
8005458: 20004afc .word 0x20004afc
0800545c <memset>:
800545c: 4402 add r2, r0
800545e: 4603 mov r3, r0
8005460: 4293 cmp r3, r2
8005462: d100 bne.n 8005466 <memset+0xa>
8005464: 4770 bx lr
8005466: f803 1b01 strb.w r1, [r3], #1
800546a: e7f9 b.n 8005460 <memset+0x4>
0800546c <_reclaim_reent>:
800546c: 4b29 ldr r3, [pc, #164] ; (8005514 <_reclaim_reent+0xa8>)
800546e: 681b ldr r3, [r3, #0]
8005470: 4283 cmp r3, r0
8005472: b570 push {r4, r5, r6, lr}
8005474: 4604 mov r4, r0
8005476: d04b beq.n 8005510 <_reclaim_reent+0xa4>
8005478: 69c3 ldr r3, [r0, #28]
800547a: b143 cbz r3, 800548e <_reclaim_reent+0x22>
800547c: 68db ldr r3, [r3, #12]
800547e: 2b00 cmp r3, #0
8005480: d144 bne.n 800550c <_reclaim_reent+0xa0>
8005482: 69e3 ldr r3, [r4, #28]
8005484: 6819 ldr r1, [r3, #0]
8005486: b111 cbz r1, 800548e <_reclaim_reent+0x22>
8005488: 4620 mov r0, r4
800548a: f000 f879 bl 8005580 <_free_r>
800548e: 6961 ldr r1, [r4, #20]
8005490: b111 cbz r1, 8005498 <_reclaim_reent+0x2c>
8005492: 4620 mov r0, r4
8005494: f000 f874 bl 8005580 <_free_r>
8005498: 69e1 ldr r1, [r4, #28]
800549a: b111 cbz r1, 80054a2 <_reclaim_reent+0x36>
800549c: 4620 mov r0, r4
800549e: f000 f86f bl 8005580 <_free_r>
80054a2: 6b21 ldr r1, [r4, #48] ; 0x30
80054a4: b111 cbz r1, 80054ac <_reclaim_reent+0x40>
80054a6: 4620 mov r0, r4
80054a8: f000 f86a bl 8005580 <_free_r>
80054ac: 6b61 ldr r1, [r4, #52] ; 0x34
80054ae: b111 cbz r1, 80054b6 <_reclaim_reent+0x4a>
80054b0: 4620 mov r0, r4
80054b2: f000 f865 bl 8005580 <_free_r>
80054b6: 6ba1 ldr r1, [r4, #56] ; 0x38
80054b8: b111 cbz r1, 80054c0 <_reclaim_reent+0x54>
80054ba: 4620 mov r0, r4
80054bc: f000 f860 bl 8005580 <_free_r>
80054c0: 6ca1 ldr r1, [r4, #72] ; 0x48
80054c2: b111 cbz r1, 80054ca <_reclaim_reent+0x5e>
80054c4: 4620 mov r0, r4
80054c6: f000 f85b bl 8005580 <_free_r>
80054ca: 6c61 ldr r1, [r4, #68] ; 0x44
80054cc: b111 cbz r1, 80054d4 <_reclaim_reent+0x68>
80054ce: 4620 mov r0, r4
80054d0: f000 f856 bl 8005580 <_free_r>
80054d4: 6ae1 ldr r1, [r4, #44] ; 0x2c
80054d6: b111 cbz r1, 80054de <_reclaim_reent+0x72>
80054d8: 4620 mov r0, r4
80054da: f000 f851 bl 8005580 <_free_r>
80054de: 6a23 ldr r3, [r4, #32]
80054e0: b1b3 cbz r3, 8005510 <_reclaim_reent+0xa4>
80054e2: 4620 mov r0, r4
80054e4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr}
80054e8: 4718 bx r3
80054ea: 5949 ldr r1, [r1, r5]
80054ec: b941 cbnz r1, 8005500 <_reclaim_reent+0x94>
80054ee: 3504 adds r5, #4
80054f0: 69e3 ldr r3, [r4, #28]
80054f2: 2d80 cmp r5, #128 ; 0x80
80054f4: 68d9 ldr r1, [r3, #12]
80054f6: d1f8 bne.n 80054ea <_reclaim_reent+0x7e>
80054f8: 4620 mov r0, r4
80054fa: f000 f841 bl 8005580 <_free_r>
80054fe: e7c0 b.n 8005482 <_reclaim_reent+0x16>
8005500: 680e ldr r6, [r1, #0]
8005502: 4620 mov r0, r4
8005504: f000 f83c bl 8005580 <_free_r>
8005508: 4631 mov r1, r6
800550a: e7ef b.n 80054ec <_reclaim_reent+0x80>
800550c: 2500 movs r5, #0
800550e: e7ef b.n 80054f0 <_reclaim_reent+0x84>
8005510: bd70 pop {r4, r5, r6, pc}
8005512: bf00 nop
8005514: 2000005c .word 0x2000005c
08005518 <__libc_init_array>:
8005518: b570 push {r4, r5, r6, lr}
800551a: 4d0d ldr r5, [pc, #52] ; (8005550 <__libc_init_array+0x38>)
800551c: 4c0d ldr r4, [pc, #52] ; (8005554 <__libc_init_array+0x3c>)
800551e: 1b64 subs r4, r4, r5
8005520: 10a4 asrs r4, r4, #2
8005522: 2600 movs r6, #0
8005524: 42a6 cmp r6, r4
8005526: d109 bne.n 800553c <__libc_init_array+0x24>
8005528: 4d0b ldr r5, [pc, #44] ; (8005558 <__libc_init_array+0x40>)
800552a: 4c0c ldr r4, [pc, #48] ; (800555c <__libc_init_array+0x44>)
800552c: f000 f880 bl 8005630 <_init>
8005530: 1b64 subs r4, r4, r5
8005532: 10a4 asrs r4, r4, #2
8005534: 2600 movs r6, #0
8005536: 42a6 cmp r6, r4
8005538: d105 bne.n 8005546 <__libc_init_array+0x2e>
800553a: bd70 pop {r4, r5, r6, pc}
800553c: f855 3b04 ldr.w r3, [r5], #4
8005540: 4798 blx r3
8005542: 3601 adds r6, #1
8005544: e7ee b.n 8005524 <__libc_init_array+0xc>
8005546: f855 3b04 ldr.w r3, [r5], #4
800554a: 4798 blx r3
800554c: 3601 adds r6, #1
800554e: e7f2 b.n 8005536 <__libc_init_array+0x1e>
8005550: 080056e0 .word 0x080056e0
8005554: 080056e0 .word 0x080056e0
8005558: 080056e0 .word 0x080056e0
800555c: 080056e4 .word 0x080056e4
08005560 <__retarget_lock_acquire_recursive>:
8005560: 4770 bx lr
08005562 <__retarget_lock_release_recursive>:
8005562: 4770 bx lr
08005564 <memcpy>:
8005564: 440a add r2, r1
8005566: 4291 cmp r1, r2
8005568: f100 33ff add.w r3, r0, #4294967295
800556c: d100 bne.n 8005570 <memcpy+0xc>
800556e: 4770 bx lr
8005570: b510 push {r4, lr}
8005572: f811 4b01 ldrb.w r4, [r1], #1
8005576: f803 4f01 strb.w r4, [r3, #1]!
800557a: 4291 cmp r1, r2
800557c: d1f9 bne.n 8005572 <memcpy+0xe>
800557e: bd10 pop {r4, pc}
08005580 <_free_r>:
8005580: b537 push {r0, r1, r2, r4, r5, lr}
8005582: 2900 cmp r1, #0
8005584: d044 beq.n 8005610 <_free_r+0x90>
8005586: f851 3c04 ldr.w r3, [r1, #-4]
800558a: 9001 str r0, [sp, #4]
800558c: 2b00 cmp r3, #0
800558e: f1a1 0404 sub.w r4, r1, #4
8005592: bfb8 it lt
8005594: 18e4 addlt r4, r4, r3
8005596: f000 f83f bl 8005618 <__malloc_lock>
800559a: 4a1e ldr r2, [pc, #120] ; (8005614 <_free_r+0x94>)
800559c: 9801 ldr r0, [sp, #4]
800559e: 6813 ldr r3, [r2, #0]
80055a0: b933 cbnz r3, 80055b0 <_free_r+0x30>
80055a2: 6063 str r3, [r4, #4]
80055a4: 6014 str r4, [r2, #0]
80055a6: b003 add sp, #12
80055a8: e8bd 4030 ldmia.w sp!, {r4, r5, lr}
80055ac: f000 b83a b.w 8005624 <__malloc_unlock>
80055b0: 42a3 cmp r3, r4
80055b2: d908 bls.n 80055c6 <_free_r+0x46>
80055b4: 6825 ldr r5, [r4, #0]
80055b6: 1961 adds r1, r4, r5
80055b8: 428b cmp r3, r1
80055ba: bf01 itttt eq
80055bc: 6819 ldreq r1, [r3, #0]
80055be: 685b ldreq r3, [r3, #4]
80055c0: 1949 addeq r1, r1, r5
80055c2: 6021 streq r1, [r4, #0]
80055c4: e7ed b.n 80055a2 <_free_r+0x22>
80055c6: 461a mov r2, r3
80055c8: 685b ldr r3, [r3, #4]
80055ca: b10b cbz r3, 80055d0 <_free_r+0x50>
80055cc: 42a3 cmp r3, r4
80055ce: d9fa bls.n 80055c6 <_free_r+0x46>
80055d0: 6811 ldr r1, [r2, #0]
80055d2: 1855 adds r5, r2, r1
80055d4: 42a5 cmp r5, r4
80055d6: d10b bne.n 80055f0 <_free_r+0x70>
80055d8: 6824 ldr r4, [r4, #0]
80055da: 4421 add r1, r4
80055dc: 1854 adds r4, r2, r1
80055de: 42a3 cmp r3, r4
80055e0: 6011 str r1, [r2, #0]
80055e2: d1e0 bne.n 80055a6 <_free_r+0x26>
80055e4: 681c ldr r4, [r3, #0]
80055e6: 685b ldr r3, [r3, #4]
80055e8: 6053 str r3, [r2, #4]
80055ea: 440c add r4, r1
80055ec: 6014 str r4, [r2, #0]
80055ee: e7da b.n 80055a6 <_free_r+0x26>
80055f0: d902 bls.n 80055f8 <_free_r+0x78>
80055f2: 230c movs r3, #12
80055f4: 6003 str r3, [r0, #0]
80055f6: e7d6 b.n 80055a6 <_free_r+0x26>
80055f8: 6825 ldr r5, [r4, #0]
80055fa: 1961 adds r1, r4, r5
80055fc: 428b cmp r3, r1
80055fe: bf04 itt eq
8005600: 6819 ldreq r1, [r3, #0]
8005602: 685b ldreq r3, [r3, #4]
8005604: 6063 str r3, [r4, #4]
8005606: bf04 itt eq
8005608: 1949 addeq r1, r1, r5
800560a: 6021 streq r1, [r4, #0]
800560c: 6054 str r4, [r2, #4]
800560e: e7ca b.n 80055a6 <_free_r+0x26>
8005610: b003 add sp, #12
8005612: bd30 pop {r4, r5, pc}
8005614: 20004c50 .word 0x20004c50
08005618 <__malloc_lock>:
8005618: 4801 ldr r0, [pc, #4] ; (8005620 <__malloc_lock+0x8>)
800561a: f7ff bfa1 b.w 8005560 <__retarget_lock_acquire_recursive>
800561e: bf00 nop
8005620: 20004c4c .word 0x20004c4c
08005624 <__malloc_unlock>:
8005624: 4801 ldr r0, [pc, #4] ; (800562c <__malloc_unlock+0x8>)
8005626: f7ff bf9c b.w 8005562 <__retarget_lock_release_recursive>
800562a: bf00 nop
800562c: 20004c4c .word 0x20004c4c
08005630 <_init>:
8005630: b5f8 push {r3, r4, r5, r6, r7, lr}
8005632: bf00 nop
8005634: bcf8 pop {r3, r4, r5, r6, r7}
8005636: bc08 pop {r3}
8005638: 469e mov lr, r3
800563a: 4770 bx lr
0800563c <_fini>:
800563c: b5f8 push {r3, r4, r5, r6, r7, lr}
800563e: bf00 nop
8005640: bcf8 pop {r3, r4, r5, r6, r7}
8005642: bc08 pop {r3}
8005644: 469e mov lr, r3
8005646: 4770 bx lr
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