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stm32-fmt-code/access_control_stm32/Debug/access_control_stm32.list

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access_control_stm32.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 00000198 08000000 08000000 00010000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00002054 08000198 08000198 00010198 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000018 080021ec 080021ec 000121ec 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08002204 08002204 0002000c 2**0
CONTENTS
4 .ARM 00000008 08002204 08002204 00012204 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 0800220c 0800220c 0002000c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 0800220c 0800220c 0001220c 2**2
CONTENTS, ALLOC, LOAD, DATA
7 .fini_array 00000004 08002210 08002210 00012210 2**2
CONTENTS, ALLOC, LOAD, DATA
8 .data 0000000c 20000000 08002214 00020000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00000070 2000000c 08002220 0002000c 2**2
ALLOC
10 ._user_heap_stack 00000604 2000007c 08002220 0002007c 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0002000c 2**0
CONTENTS, READONLY
12 .comment 00000043 00000000 00000000 0002003c 2**0
CONTENTS, READONLY
13 .debug_info 00007126 00000000 00000000 0002007f 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_abbrev 000012ea 00000000 00000000 000271a5 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00000608 00000000 00000000 00028490 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_rnglists 0000049d 00000000 00000000 00028a98 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_macro 0001483d 00000000 00000000 00028f35 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_line 0000798a 00000000 00000000 0003d772 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_str 000818db 00000000 00000000 000450fc 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .debug_frame 000017a8 00000000 00000000 000c69d8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000059 00000000 00000000 000c8180 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
08000198 <__do_global_dtors_aux>:
8000198: b510 push {r4, lr}
800019a: 4c05 ldr r4, [pc, #20] ; (80001b0 <__do_global_dtors_aux+0x18>)
800019c: 7823 ldrb r3, [r4, #0]
800019e: b933 cbnz r3, 80001ae <__do_global_dtors_aux+0x16>
80001a0: 4b04 ldr r3, [pc, #16] ; (80001b4 <__do_global_dtors_aux+0x1c>)
80001a2: b113 cbz r3, 80001aa <__do_global_dtors_aux+0x12>
80001a4: 4804 ldr r0, [pc, #16] ; (80001b8 <__do_global_dtors_aux+0x20>)
80001a6: f3af 8000 nop.w
80001aa: 2301 movs r3, #1
80001ac: 7023 strb r3, [r4, #0]
80001ae: bd10 pop {r4, pc}
80001b0: 2000000c .word 0x2000000c
80001b4: 00000000 .word 0x00000000
80001b8: 080021d4 .word 0x080021d4
080001bc <frame_dummy>:
80001bc: b508 push {r3, lr}
80001be: 4b03 ldr r3, [pc, #12] ; (80001cc <frame_dummy+0x10>)
80001c0: b11b cbz r3, 80001ca <frame_dummy+0xe>
80001c2: 4903 ldr r1, [pc, #12] ; (80001d0 <frame_dummy+0x14>)
80001c4: 4803 ldr r0, [pc, #12] ; (80001d4 <frame_dummy+0x18>)
80001c6: f3af 8000 nop.w
80001ca: bd08 pop {r3, pc}
80001cc: 00000000 .word 0x00000000
80001d0: 20000010 .word 0x20000010
80001d4: 080021d4 .word 0x080021d4
080001d8 <__aeabi_uldivmod>:
80001d8: b953 cbnz r3, 80001f0 <__aeabi_uldivmod+0x18>
80001da: b94a cbnz r2, 80001f0 <__aeabi_uldivmod+0x18>
80001dc: 2900 cmp r1, #0
80001de: bf08 it eq
80001e0: 2800 cmpeq r0, #0
80001e2: bf1c itt ne
80001e4: f04f 31ff movne.w r1, #4294967295
80001e8: f04f 30ff movne.w r0, #4294967295
80001ec: f000 b970 b.w 80004d0 <__aeabi_idiv0>
80001f0: f1ad 0c08 sub.w ip, sp, #8
80001f4: e96d ce04 strd ip, lr, [sp, #-16]!
80001f8: f000 f806 bl 8000208 <__udivmoddi4>
80001fc: f8dd e004 ldr.w lr, [sp, #4]
8000200: e9dd 2302 ldrd r2, r3, [sp, #8]
8000204: b004 add sp, #16
8000206: 4770 bx lr
08000208 <__udivmoddi4>:
8000208: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800020c: 9e08 ldr r6, [sp, #32]
800020e: 460d mov r5, r1
8000210: 4604 mov r4, r0
8000212: 460f mov r7, r1
8000214: 2b00 cmp r3, #0
8000216: d14a bne.n 80002ae <__udivmoddi4+0xa6>
8000218: 428a cmp r2, r1
800021a: 4694 mov ip, r2
800021c: d965 bls.n 80002ea <__udivmoddi4+0xe2>
800021e: fab2 f382 clz r3, r2
8000222: b143 cbz r3, 8000236 <__udivmoddi4+0x2e>
8000224: fa02 fc03 lsl.w ip, r2, r3
8000228: f1c3 0220 rsb r2, r3, #32
800022c: 409f lsls r7, r3
800022e: fa20 f202 lsr.w r2, r0, r2
8000232: 4317 orrs r7, r2
8000234: 409c lsls r4, r3
8000236: ea4f 4e1c mov.w lr, ip, lsr #16
800023a: fa1f f58c uxth.w r5, ip
800023e: fbb7 f1fe udiv r1, r7, lr
8000242: 0c22 lsrs r2, r4, #16
8000244: fb0e 7711 mls r7, lr, r1, r7
8000248: ea42 4207 orr.w r2, r2, r7, lsl #16
800024c: fb01 f005 mul.w r0, r1, r5
8000250: 4290 cmp r0, r2
8000252: d90a bls.n 800026a <__udivmoddi4+0x62>
8000254: eb1c 0202 adds.w r2, ip, r2
8000258: f101 37ff add.w r7, r1, #4294967295
800025c: f080 811c bcs.w 8000498 <__udivmoddi4+0x290>
8000260: 4290 cmp r0, r2
8000262: f240 8119 bls.w 8000498 <__udivmoddi4+0x290>
8000266: 3902 subs r1, #2
8000268: 4462 add r2, ip
800026a: 1a12 subs r2, r2, r0
800026c: b2a4 uxth r4, r4
800026e: fbb2 f0fe udiv r0, r2, lr
8000272: fb0e 2210 mls r2, lr, r0, r2
8000276: ea44 4402 orr.w r4, r4, r2, lsl #16
800027a: fb00 f505 mul.w r5, r0, r5
800027e: 42a5 cmp r5, r4
8000280: d90a bls.n 8000298 <__udivmoddi4+0x90>
8000282: eb1c 0404 adds.w r4, ip, r4
8000286: f100 32ff add.w r2, r0, #4294967295
800028a: f080 8107 bcs.w 800049c <__udivmoddi4+0x294>
800028e: 42a5 cmp r5, r4
8000290: f240 8104 bls.w 800049c <__udivmoddi4+0x294>
8000294: 4464 add r4, ip
8000296: 3802 subs r0, #2
8000298: ea40 4001 orr.w r0, r0, r1, lsl #16
800029c: 1b64 subs r4, r4, r5
800029e: 2100 movs r1, #0
80002a0: b11e cbz r6, 80002aa <__udivmoddi4+0xa2>
80002a2: 40dc lsrs r4, r3
80002a4: 2300 movs r3, #0
80002a6: e9c6 4300 strd r4, r3, [r6]
80002aa: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002ae: 428b cmp r3, r1
80002b0: d908 bls.n 80002c4 <__udivmoddi4+0xbc>
80002b2: 2e00 cmp r6, #0
80002b4: f000 80ed beq.w 8000492 <__udivmoddi4+0x28a>
80002b8: 2100 movs r1, #0
80002ba: e9c6 0500 strd r0, r5, [r6]
80002be: 4608 mov r0, r1
80002c0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002c4: fab3 f183 clz r1, r3
80002c8: 2900 cmp r1, #0
80002ca: d149 bne.n 8000360 <__udivmoddi4+0x158>
80002cc: 42ab cmp r3, r5
80002ce: d302 bcc.n 80002d6 <__udivmoddi4+0xce>
80002d0: 4282 cmp r2, r0
80002d2: f200 80f8 bhi.w 80004c6 <__udivmoddi4+0x2be>
80002d6: 1a84 subs r4, r0, r2
80002d8: eb65 0203 sbc.w r2, r5, r3
80002dc: 2001 movs r0, #1
80002de: 4617 mov r7, r2
80002e0: 2e00 cmp r6, #0
80002e2: d0e2 beq.n 80002aa <__udivmoddi4+0xa2>
80002e4: e9c6 4700 strd r4, r7, [r6]
80002e8: e7df b.n 80002aa <__udivmoddi4+0xa2>
80002ea: b902 cbnz r2, 80002ee <__udivmoddi4+0xe6>
80002ec: deff udf #255 ; 0xff
80002ee: fab2 f382 clz r3, r2
80002f2: 2b00 cmp r3, #0
80002f4: f040 8090 bne.w 8000418 <__udivmoddi4+0x210>
80002f8: 1a8a subs r2, r1, r2
80002fa: ea4f 471c mov.w r7, ip, lsr #16
80002fe: fa1f fe8c uxth.w lr, ip
8000302: 2101 movs r1, #1
8000304: fbb2 f5f7 udiv r5, r2, r7
8000308: fb07 2015 mls r0, r7, r5, r2
800030c: 0c22 lsrs r2, r4, #16
800030e: ea42 4200 orr.w r2, r2, r0, lsl #16
8000312: fb0e f005 mul.w r0, lr, r5
8000316: 4290 cmp r0, r2
8000318: d908 bls.n 800032c <__udivmoddi4+0x124>
800031a: eb1c 0202 adds.w r2, ip, r2
800031e: f105 38ff add.w r8, r5, #4294967295
8000322: d202 bcs.n 800032a <__udivmoddi4+0x122>
8000324: 4290 cmp r0, r2
8000326: f200 80cb bhi.w 80004c0 <__udivmoddi4+0x2b8>
800032a: 4645 mov r5, r8
800032c: 1a12 subs r2, r2, r0
800032e: b2a4 uxth r4, r4
8000330: fbb2 f0f7 udiv r0, r2, r7
8000334: fb07 2210 mls r2, r7, r0, r2
8000338: ea44 4402 orr.w r4, r4, r2, lsl #16
800033c: fb0e fe00 mul.w lr, lr, r0
8000340: 45a6 cmp lr, r4
8000342: d908 bls.n 8000356 <__udivmoddi4+0x14e>
8000344: eb1c 0404 adds.w r4, ip, r4
8000348: f100 32ff add.w r2, r0, #4294967295
800034c: d202 bcs.n 8000354 <__udivmoddi4+0x14c>
800034e: 45a6 cmp lr, r4
8000350: f200 80bb bhi.w 80004ca <__udivmoddi4+0x2c2>
8000354: 4610 mov r0, r2
8000356: eba4 040e sub.w r4, r4, lr
800035a: ea40 4005 orr.w r0, r0, r5, lsl #16
800035e: e79f b.n 80002a0 <__udivmoddi4+0x98>
8000360: f1c1 0720 rsb r7, r1, #32
8000364: 408b lsls r3, r1
8000366: fa22 fc07 lsr.w ip, r2, r7
800036a: ea4c 0c03 orr.w ip, ip, r3
800036e: fa05 f401 lsl.w r4, r5, r1
8000372: fa20 f307 lsr.w r3, r0, r7
8000376: 40fd lsrs r5, r7
8000378: ea4f 491c mov.w r9, ip, lsr #16
800037c: 4323 orrs r3, r4
800037e: fbb5 f8f9 udiv r8, r5, r9
8000382: fa1f fe8c uxth.w lr, ip
8000386: fb09 5518 mls r5, r9, r8, r5
800038a: 0c1c lsrs r4, r3, #16
800038c: ea44 4405 orr.w r4, r4, r5, lsl #16
8000390: fb08 f50e mul.w r5, r8, lr
8000394: 42a5 cmp r5, r4
8000396: fa02 f201 lsl.w r2, r2, r1
800039a: fa00 f001 lsl.w r0, r0, r1
800039e: d90b bls.n 80003b8 <__udivmoddi4+0x1b0>
80003a0: eb1c 0404 adds.w r4, ip, r4
80003a4: f108 3aff add.w sl, r8, #4294967295
80003a8: f080 8088 bcs.w 80004bc <__udivmoddi4+0x2b4>
80003ac: 42a5 cmp r5, r4
80003ae: f240 8085 bls.w 80004bc <__udivmoddi4+0x2b4>
80003b2: f1a8 0802 sub.w r8, r8, #2
80003b6: 4464 add r4, ip
80003b8: 1b64 subs r4, r4, r5
80003ba: b29d uxth r5, r3
80003bc: fbb4 f3f9 udiv r3, r4, r9
80003c0: fb09 4413 mls r4, r9, r3, r4
80003c4: ea45 4404 orr.w r4, r5, r4, lsl #16
80003c8: fb03 fe0e mul.w lr, r3, lr
80003cc: 45a6 cmp lr, r4
80003ce: d908 bls.n 80003e2 <__udivmoddi4+0x1da>
80003d0: eb1c 0404 adds.w r4, ip, r4
80003d4: f103 35ff add.w r5, r3, #4294967295
80003d8: d26c bcs.n 80004b4 <__udivmoddi4+0x2ac>
80003da: 45a6 cmp lr, r4
80003dc: d96a bls.n 80004b4 <__udivmoddi4+0x2ac>
80003de: 3b02 subs r3, #2
80003e0: 4464 add r4, ip
80003e2: ea43 4308 orr.w r3, r3, r8, lsl #16
80003e6: fba3 9502 umull r9, r5, r3, r2
80003ea: eba4 040e sub.w r4, r4, lr
80003ee: 42ac cmp r4, r5
80003f0: 46c8 mov r8, r9
80003f2: 46ae mov lr, r5
80003f4: d356 bcc.n 80004a4 <__udivmoddi4+0x29c>
80003f6: d053 beq.n 80004a0 <__udivmoddi4+0x298>
80003f8: b156 cbz r6, 8000410 <__udivmoddi4+0x208>
80003fa: ebb0 0208 subs.w r2, r0, r8
80003fe: eb64 040e sbc.w r4, r4, lr
8000402: fa04 f707 lsl.w r7, r4, r7
8000406: 40ca lsrs r2, r1
8000408: 40cc lsrs r4, r1
800040a: 4317 orrs r7, r2
800040c: e9c6 7400 strd r7, r4, [r6]
8000410: 4618 mov r0, r3
8000412: 2100 movs r1, #0
8000414: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
8000418: f1c3 0120 rsb r1, r3, #32
800041c: fa02 fc03 lsl.w ip, r2, r3
8000420: fa20 f201 lsr.w r2, r0, r1
8000424: fa25 f101 lsr.w r1, r5, r1
8000428: 409d lsls r5, r3
800042a: 432a orrs r2, r5
800042c: ea4f 471c mov.w r7, ip, lsr #16
8000430: fa1f fe8c uxth.w lr, ip
8000434: fbb1 f0f7 udiv r0, r1, r7
8000438: fb07 1510 mls r5, r7, r0, r1
800043c: 0c11 lsrs r1, r2, #16
800043e: ea41 4105 orr.w r1, r1, r5, lsl #16
8000442: fb00 f50e mul.w r5, r0, lr
8000446: 428d cmp r5, r1
8000448: fa04 f403 lsl.w r4, r4, r3
800044c: d908 bls.n 8000460 <__udivmoddi4+0x258>
800044e: eb1c 0101 adds.w r1, ip, r1
8000452: f100 38ff add.w r8, r0, #4294967295
8000456: d22f bcs.n 80004b8 <__udivmoddi4+0x2b0>
8000458: 428d cmp r5, r1
800045a: d92d bls.n 80004b8 <__udivmoddi4+0x2b0>
800045c: 3802 subs r0, #2
800045e: 4461 add r1, ip
8000460: 1b49 subs r1, r1, r5
8000462: b292 uxth r2, r2
8000464: fbb1 f5f7 udiv r5, r1, r7
8000468: fb07 1115 mls r1, r7, r5, r1
800046c: ea42 4201 orr.w r2, r2, r1, lsl #16
8000470: fb05 f10e mul.w r1, r5, lr
8000474: 4291 cmp r1, r2
8000476: d908 bls.n 800048a <__udivmoddi4+0x282>
8000478: eb1c 0202 adds.w r2, ip, r2
800047c: f105 38ff add.w r8, r5, #4294967295
8000480: d216 bcs.n 80004b0 <__udivmoddi4+0x2a8>
8000482: 4291 cmp r1, r2
8000484: d914 bls.n 80004b0 <__udivmoddi4+0x2a8>
8000486: 3d02 subs r5, #2
8000488: 4462 add r2, ip
800048a: 1a52 subs r2, r2, r1
800048c: ea45 4100 orr.w r1, r5, r0, lsl #16
8000490: e738 b.n 8000304 <__udivmoddi4+0xfc>
8000492: 4631 mov r1, r6
8000494: 4630 mov r0, r6
8000496: e708 b.n 80002aa <__udivmoddi4+0xa2>
8000498: 4639 mov r1, r7
800049a: e6e6 b.n 800026a <__udivmoddi4+0x62>
800049c: 4610 mov r0, r2
800049e: e6fb b.n 8000298 <__udivmoddi4+0x90>
80004a0: 4548 cmp r0, r9
80004a2: d2a9 bcs.n 80003f8 <__udivmoddi4+0x1f0>
80004a4: ebb9 0802 subs.w r8, r9, r2
80004a8: eb65 0e0c sbc.w lr, r5, ip
80004ac: 3b01 subs r3, #1
80004ae: e7a3 b.n 80003f8 <__udivmoddi4+0x1f0>
80004b0: 4645 mov r5, r8
80004b2: e7ea b.n 800048a <__udivmoddi4+0x282>
80004b4: 462b mov r3, r5
80004b6: e794 b.n 80003e2 <__udivmoddi4+0x1da>
80004b8: 4640 mov r0, r8
80004ba: e7d1 b.n 8000460 <__udivmoddi4+0x258>
80004bc: 46d0 mov r8, sl
80004be: e77b b.n 80003b8 <__udivmoddi4+0x1b0>
80004c0: 3d02 subs r5, #2
80004c2: 4462 add r2, ip
80004c4: e732 b.n 800032c <__udivmoddi4+0x124>
80004c6: 4608 mov r0, r1
80004c8: e70a b.n 80002e0 <__udivmoddi4+0xd8>
80004ca: 4464 add r4, ip
80004cc: 3802 subs r0, #2
80004ce: e742 b.n 8000356 <__udivmoddi4+0x14e>
080004d0 <__aeabi_idiv0>:
80004d0: 4770 bx lr
80004d2: bf00 nop
080004d4 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void) {
80004d4: b580 push {r7, lr}
80004d6: b082 sub sp, #8
80004d8: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80004da: f000 fa45 bl 8000968 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80004de: f000 f859 bl 8000594 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80004e2: f000 f8eb bl 80006bc <MX_GPIO_Init>
MX_USART2_UART_Init();
80004e6: f000 f8bf bl 8000668 <MX_USART2_UART_Init>
/* USER CODE BEGIN 2 */
memset(uart_buffer, 0, 10);
80004ea: 220a movs r2, #10
80004ec: 2100 movs r1, #0
80004ee: 4825 ldr r0, [pc, #148] ; (8000584 <main+0xb0>)
80004f0: f001 fe44 bl 800217c <memset>
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 250)
80004f4: 4b24 ldr r3, [pc, #144] ; (8000588 <main+0xb4>)
80004f6: 781b ldrb r3, [r3, #0]
80004f8: 461a mov r2, r3
80004fa: 4b22 ldr r3, [pc, #136] ; (8000584 <main+0xb0>)
80004fc: 18d1 adds r1, r2, r3
80004fe: 23fa movs r3, #250 ; 0xfa
8000500: 2201 movs r2, #1
8000502: 4822 ldr r0, [pc, #136] ; (800058c <main+0xb8>)
8000504: f001 fab5 bl 8001a72 <HAL_UART_Receive>
8000508: 4603 mov r3, r0
800050a: 2b00 cmp r3, #0
800050c: d1f2 bne.n 80004f4 <main+0x20>
== HAL_OK) {
uart_index++;
800050e: 4b1e ldr r3, [pc, #120] ; (8000588 <main+0xb4>)
8000510: 781b ldrb r3, [r3, #0]
8000512: 3301 adds r3, #1
8000514: b2da uxtb r2, r3
8000516: 4b1c ldr r3, [pc, #112] ; (8000588 <main+0xb4>)
8000518: 701a strb r2, [r3, #0]
if (uart_buffer[uart_index - 1] == 0xFF) {
800051a: 4b1b ldr r3, [pc, #108] ; (8000588 <main+0xb4>)
800051c: 781b ldrb r3, [r3, #0]
800051e: 3b01 subs r3, #1
8000520: 4a18 ldr r2, [pc, #96] ; (8000584 <main+0xb0>)
8000522: 5cd3 ldrb r3, [r2, r3]
8000524: 2bff cmp r3, #255 ; 0xff
8000526: d1e5 bne.n 80004f4 <main+0x20>
if (uart_index > 1) {
8000528: 4b17 ldr r3, [pc, #92] ; (8000588 <main+0xb4>)
800052a: 781b ldrb r3, [r3, #0]
800052c: 2b01 cmp r3, #1
800052e: d920 bls.n 8000572 <main+0x9e>
if (uart_buffer[0] == 0x00) {
8000530: 4b14 ldr r3, [pc, #80] ; (8000584 <main+0xb0>)
8000532: 781b ldrb r3, [r3, #0]
8000534: 2b00 cmp r3, #0
8000536: d107 bne.n 8000548 <main+0x74>
HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, uart_buffer[1]);
8000538: 4b12 ldr r3, [pc, #72] ; (8000584 <main+0xb0>)
800053a: 785b ldrb r3, [r3, #1]
800053c: 461a mov r2, r3
800053e: 2120 movs r1, #32
8000540: 4813 ldr r0, [pc, #76] ; (8000590 <main+0xbc>)
8000542: f000 fd05 bl 8000f50 <HAL_GPIO_WritePin>
8000546: e014 b.n 8000572 <main+0x9e>
} else if (uart_buffer[0] == 0x01) {
8000548: 4b0e ldr r3, [pc, #56] ; (8000584 <main+0xb0>)
800054a: 781b ldrb r3, [r3, #0]
800054c: 2b01 cmp r3, #1
800054e: d110 bne.n 8000572 <main+0x9e>
uint8_t payload[3] = { 0x01, HAL_GPIO_ReadPin(GPIOA,
8000550: 2301 movs r3, #1
8000552: 713b strb r3, [r7, #4]
8000554: 2180 movs r1, #128 ; 0x80
8000556: 480e ldr r0, [pc, #56] ; (8000590 <main+0xbc>)
8000558: f000 fce2 bl 8000f20 <HAL_GPIO_ReadPin>
800055c: 4603 mov r3, r0
800055e: 717b strb r3, [r7, #5]
8000560: 23ff movs r3, #255 ; 0xff
8000562: 71bb strb r3, [r7, #6]
GPIO_PIN_7), 0xFF };
HAL_UART_Transmit(&huart2, payload, 3, 1500);
8000564: 1d39 adds r1, r7, #4
8000566: f240 53dc movw r3, #1500 ; 0x5dc
800056a: 2203 movs r2, #3
800056c: 4807 ldr r0, [pc, #28] ; (800058c <main+0xb8>)
800056e: f001 f9ee bl 800194e <HAL_UART_Transmit>
}
}
uart_index = 0;
8000572: 4b05 ldr r3, [pc, #20] ; (8000588 <main+0xb4>)
8000574: 2200 movs r2, #0
8000576: 701a strb r2, [r3, #0]
memset(uart_buffer, 0, 10);
8000578: 220a movs r2, #10
800057a: 2100 movs r1, #0
800057c: 4801 ldr r0, [pc, #4] ; (8000584 <main+0xb0>)
800057e: f001 fdfd bl 800217c <memset>
if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 250)
8000582: e7b7 b.n 80004f4 <main+0x20>
8000584: 2000006c .word 0x2000006c
8000588: 20000076 .word 0x20000076
800058c: 20000028 .word 0x20000028
8000590: 40020000 .word 0x40020000
08000594 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void) {
8000594: b580 push {r7, lr}
8000596: b094 sub sp, #80 ; 0x50
8000598: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = { 0 };
800059a: f107 0320 add.w r3, r7, #32
800059e: 2230 movs r2, #48 ; 0x30
80005a0: 2100 movs r1, #0
80005a2: 4618 mov r0, r3
80005a4: f001 fdea bl 800217c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 };
80005a8: f107 030c add.w r3, r7, #12
80005ac: 2200 movs r2, #0
80005ae: 601a str r2, [r3, #0]
80005b0: 605a str r2, [r3, #4]
80005b2: 609a str r2, [r3, #8]
80005b4: 60da str r2, [r3, #12]
80005b6: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
80005b8: 2300 movs r3, #0
80005ba: 60bb str r3, [r7, #8]
80005bc: 4b28 ldr r3, [pc, #160] ; (8000660 <SystemClock_Config+0xcc>)
80005be: 6c1b ldr r3, [r3, #64] ; 0x40
80005c0: 4a27 ldr r2, [pc, #156] ; (8000660 <SystemClock_Config+0xcc>)
80005c2: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80005c6: 6413 str r3, [r2, #64] ; 0x40
80005c8: 4b25 ldr r3, [pc, #148] ; (8000660 <SystemClock_Config+0xcc>)
80005ca: 6c1b ldr r3, [r3, #64] ; 0x40
80005cc: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80005d0: 60bb str r3, [r7, #8]
80005d2: 68bb ldr r3, [r7, #8]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
80005d4: 2300 movs r3, #0
80005d6: 607b str r3, [r7, #4]
80005d8: 4b22 ldr r3, [pc, #136] ; (8000664 <SystemClock_Config+0xd0>)
80005da: 681b ldr r3, [r3, #0]
80005dc: 4a21 ldr r2, [pc, #132] ; (8000664 <SystemClock_Config+0xd0>)
80005de: f443 4340 orr.w r3, r3, #49152 ; 0xc000
80005e2: 6013 str r3, [r2, #0]
80005e4: 4b1f ldr r3, [pc, #124] ; (8000664 <SystemClock_Config+0xd0>)
80005e6: 681b ldr r3, [r3, #0]
80005e8: f403 4340 and.w r3, r3, #49152 ; 0xc000
80005ec: 607b str r3, [r7, #4]
80005ee: 687b ldr r3, [r7, #4]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
80005f0: 2302 movs r3, #2
80005f2: 623b str r3, [r7, #32]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80005f4: 2301 movs r3, #1
80005f6: 62fb str r3, [r7, #44] ; 0x2c
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80005f8: 2310 movs r3, #16
80005fa: 633b str r3, [r7, #48] ; 0x30
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80005fc: 2302 movs r3, #2
80005fe: 63bb str r3, [r7, #56] ; 0x38
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
8000600: 2300 movs r3, #0
8000602: 63fb str r3, [r7, #60] ; 0x3c
RCC_OscInitStruct.PLL.PLLM = 16;
8000604: 2310 movs r3, #16
8000606: 643b str r3, [r7, #64] ; 0x40
RCC_OscInitStruct.PLL.PLLN = 336;
8000608: f44f 73a8 mov.w r3, #336 ; 0x150
800060c: 647b str r3, [r7, #68] ; 0x44
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
800060e: 2304 movs r3, #4
8000610: 64bb str r3, [r7, #72] ; 0x48
RCC_OscInitStruct.PLL.PLLQ = 4;
8000612: 2304 movs r3, #4
8000614: 64fb str r3, [r7, #76] ; 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
8000616: f107 0320 add.w r3, r7, #32
800061a: 4618 mov r0, r3
800061c: f000 fcb2 bl 8000f84 <HAL_RCC_OscConfig>
8000620: 4603 mov r3, r0
8000622: 2b00 cmp r3, #0
8000624: d001 beq.n 800062a <SystemClock_Config+0x96>
Error_Handler();
8000626: f000 f8c3 bl 80007b0 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
800062a: 230f movs r3, #15
800062c: 60fb str r3, [r7, #12]
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
800062e: 2302 movs r3, #2
8000630: 613b str r3, [r7, #16]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8000632: 2300 movs r3, #0
8000634: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
8000636: f44f 5380 mov.w r3, #4096 ; 0x1000
800063a: 61bb str r3, [r7, #24]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
800063c: 2300 movs r3, #0
800063e: 61fb str r3, [r7, #28]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
8000640: f107 030c add.w r3, r7, #12
8000644: 2102 movs r1, #2
8000646: 4618 mov r0, r3
8000648: f000 ff14 bl 8001474 <HAL_RCC_ClockConfig>
800064c: 4603 mov r3, r0
800064e: 2b00 cmp r3, #0
8000650: d001 beq.n 8000656 <SystemClock_Config+0xc2>
Error_Handler();
8000652: f000 f8ad bl 80007b0 <Error_Handler>
}
}
8000656: bf00 nop
8000658: 3750 adds r7, #80 ; 0x50
800065a: 46bd mov sp, r7
800065c: bd80 pop {r7, pc}
800065e: bf00 nop
8000660: 40023800 .word 0x40023800
8000664: 40007000 .word 0x40007000
08000668 <MX_USART2_UART_Init>:
/**
* @brief USART2 Initialization Function
* @param None
* @retval None
*/
static void MX_USART2_UART_Init(void) {
8000668: b580 push {r7, lr}
800066a: af00 add r7, sp, #0
/* USER CODE END USART2_Init 0 */
/* USER CODE BEGIN USART2_Init 1 */
/* USER CODE END USART2_Init 1 */
huart2.Instance = USART2;
800066c: 4b11 ldr r3, [pc, #68] ; (80006b4 <MX_USART2_UART_Init+0x4c>)
800066e: 4a12 ldr r2, [pc, #72] ; (80006b8 <MX_USART2_UART_Init+0x50>)
8000670: 601a str r2, [r3, #0]
huart2.Init.BaudRate = 115200;
8000672: 4b10 ldr r3, [pc, #64] ; (80006b4 <MX_USART2_UART_Init+0x4c>)
8000674: f44f 32e1 mov.w r2, #115200 ; 0x1c200
8000678: 605a str r2, [r3, #4]
huart2.Init.WordLength = UART_WORDLENGTH_8B;
800067a: 4b0e ldr r3, [pc, #56] ; (80006b4 <MX_USART2_UART_Init+0x4c>)
800067c: 2200 movs r2, #0
800067e: 609a str r2, [r3, #8]
huart2.Init.StopBits = UART_STOPBITS_1;
8000680: 4b0c ldr r3, [pc, #48] ; (80006b4 <MX_USART2_UART_Init+0x4c>)
8000682: 2200 movs r2, #0
8000684: 60da str r2, [r3, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8000686: 4b0b ldr r3, [pc, #44] ; (80006b4 <MX_USART2_UART_Init+0x4c>)
8000688: 2200 movs r2, #0
800068a: 611a str r2, [r3, #16]
huart2.Init.Mode = UART_MODE_TX_RX;
800068c: 4b09 ldr r3, [pc, #36] ; (80006b4 <MX_USART2_UART_Init+0x4c>)
800068e: 220c movs r2, #12
8000690: 615a str r2, [r3, #20]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000692: 4b08 ldr r3, [pc, #32] ; (80006b4 <MX_USART2_UART_Init+0x4c>)
8000694: 2200 movs r2, #0
8000696: 619a str r2, [r3, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
8000698: 4b06 ldr r3, [pc, #24] ; (80006b4 <MX_USART2_UART_Init+0x4c>)
800069a: 2200 movs r2, #0
800069c: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart2) != HAL_OK) {
800069e: 4805 ldr r0, [pc, #20] ; (80006b4 <MX_USART2_UART_Init+0x4c>)
80006a0: f001 f908 bl 80018b4 <HAL_UART_Init>
80006a4: 4603 mov r3, r0
80006a6: 2b00 cmp r3, #0
80006a8: d001 beq.n 80006ae <MX_USART2_UART_Init+0x46>
Error_Handler();
80006aa: f000 f881 bl 80007b0 <Error_Handler>
}
/* USER CODE BEGIN USART2_Init 2 */
/* USER CODE END USART2_Init 2 */
}
80006ae: bf00 nop
80006b0: bd80 pop {r7, pc}
80006b2: bf00 nop
80006b4: 20000028 .word 0x20000028
80006b8: 40004400 .word 0x40004400
080006bc <MX_GPIO_Init>:
/**
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void) {
80006bc: b580 push {r7, lr}
80006be: b08a sub sp, #40 ; 0x28
80006c0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = { 0 };
80006c2: f107 0314 add.w r3, r7, #20
80006c6: 2200 movs r2, #0
80006c8: 601a str r2, [r3, #0]
80006ca: 605a str r2, [r3, #4]
80006cc: 609a str r2, [r3, #8]
80006ce: 60da str r2, [r3, #12]
80006d0: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
80006d2: 2300 movs r3, #0
80006d4: 613b str r3, [r7, #16]
80006d6: 4b33 ldr r3, [pc, #204] ; (80007a4 <MX_GPIO_Init+0xe8>)
80006d8: 6b1b ldr r3, [r3, #48] ; 0x30
80006da: 4a32 ldr r2, [pc, #200] ; (80007a4 <MX_GPIO_Init+0xe8>)
80006dc: f043 0304 orr.w r3, r3, #4
80006e0: 6313 str r3, [r2, #48] ; 0x30
80006e2: 4b30 ldr r3, [pc, #192] ; (80007a4 <MX_GPIO_Init+0xe8>)
80006e4: 6b1b ldr r3, [r3, #48] ; 0x30
80006e6: f003 0304 and.w r3, r3, #4
80006ea: 613b str r3, [r7, #16]
80006ec: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOH_CLK_ENABLE();
80006ee: 2300 movs r3, #0
80006f0: 60fb str r3, [r7, #12]
80006f2: 4b2c ldr r3, [pc, #176] ; (80007a4 <MX_GPIO_Init+0xe8>)
80006f4: 6b1b ldr r3, [r3, #48] ; 0x30
80006f6: 4a2b ldr r2, [pc, #172] ; (80007a4 <MX_GPIO_Init+0xe8>)
80006f8: f043 0380 orr.w r3, r3, #128 ; 0x80
80006fc: 6313 str r3, [r2, #48] ; 0x30
80006fe: 4b29 ldr r3, [pc, #164] ; (80007a4 <MX_GPIO_Init+0xe8>)
8000700: 6b1b ldr r3, [r3, #48] ; 0x30
8000702: f003 0380 and.w r3, r3, #128 ; 0x80
8000706: 60fb str r3, [r7, #12]
8000708: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
800070a: 2300 movs r3, #0
800070c: 60bb str r3, [r7, #8]
800070e: 4b25 ldr r3, [pc, #148] ; (80007a4 <MX_GPIO_Init+0xe8>)
8000710: 6b1b ldr r3, [r3, #48] ; 0x30
8000712: 4a24 ldr r2, [pc, #144] ; (80007a4 <MX_GPIO_Init+0xe8>)
8000714: f043 0301 orr.w r3, r3, #1
8000718: 6313 str r3, [r2, #48] ; 0x30
800071a: 4b22 ldr r3, [pc, #136] ; (80007a4 <MX_GPIO_Init+0xe8>)
800071c: 6b1b ldr r3, [r3, #48] ; 0x30
800071e: f003 0301 and.w r3, r3, #1
8000722: 60bb str r3, [r7, #8]
8000724: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000726: 2300 movs r3, #0
8000728: 607b str r3, [r7, #4]
800072a: 4b1e ldr r3, [pc, #120] ; (80007a4 <MX_GPIO_Init+0xe8>)
800072c: 6b1b ldr r3, [r3, #48] ; 0x30
800072e: 4a1d ldr r2, [pc, #116] ; (80007a4 <MX_GPIO_Init+0xe8>)
8000730: f043 0302 orr.w r3, r3, #2
8000734: 6313 str r3, [r2, #48] ; 0x30
8000736: 4b1b ldr r3, [pc, #108] ; (80007a4 <MX_GPIO_Init+0xe8>)
8000738: 6b1b ldr r3, [r3, #48] ; 0x30
800073a: f003 0302 and.w r3, r3, #2
800073e: 607b str r3, [r7, #4]
8000740: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET);
8000742: 2200 movs r2, #0
8000744: 2120 movs r1, #32
8000746: 4818 ldr r0, [pc, #96] ; (80007a8 <MX_GPIO_Init+0xec>)
8000748: f000 fc02 bl 8000f50 <HAL_GPIO_WritePin>
/*Configure GPIO pin : B1_Pin */
GPIO_InitStruct.Pin = B1_Pin;
800074c: f44f 5300 mov.w r3, #8192 ; 0x2000
8000750: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
8000752: f44f 1304 mov.w r3, #2162688 ; 0x210000
8000756: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000758: 2300 movs r3, #0
800075a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
800075c: f107 0314 add.w r3, r7, #20
8000760: 4619 mov r1, r3
8000762: 4812 ldr r0, [pc, #72] ; (80007ac <MX_GPIO_Init+0xf0>)
8000764: f000 fa58 bl 8000c18 <HAL_GPIO_Init>
/*Configure GPIO pin : LD2_Pin */
GPIO_InitStruct.Pin = LD2_Pin;
8000768: 2320 movs r3, #32
800076a: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800076c: 2301 movs r3, #1
800076e: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000770: 2300 movs r3, #0
8000772: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000774: 2300 movs r3, #0
8000776: 623b str r3, [r7, #32]
HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct);
8000778: f107 0314 add.w r3, r7, #20
800077c: 4619 mov r1, r3
800077e: 480a ldr r0, [pc, #40] ; (80007a8 <MX_GPIO_Init+0xec>)
8000780: f000 fa4a bl 8000c18 <HAL_GPIO_Init>
/*Configure GPIO pin : Door_Sensor_Pin */
GPIO_InitStruct.Pin = Door_Sensor_Pin;
8000784: 2380 movs r3, #128 ; 0x80
8000786: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000788: 2300 movs r3, #0
800078a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
800078c: 2301 movs r3, #1
800078e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(Door_Sensor_GPIO_Port, &GPIO_InitStruct);
8000790: f107 0314 add.w r3, r7, #20
8000794: 4619 mov r1, r3
8000796: 4804 ldr r0, [pc, #16] ; (80007a8 <MX_GPIO_Init+0xec>)
8000798: f000 fa3e bl 8000c18 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
800079c: bf00 nop
800079e: 3728 adds r7, #40 ; 0x28
80007a0: 46bd mov sp, r7
80007a2: bd80 pop {r7, pc}
80007a4: 40023800 .word 0x40023800
80007a8: 40020000 .word 0x40020000
80007ac: 40020800 .word 0x40020800
080007b0 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void) {
80007b0: b480 push {r7}
80007b2: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80007b4: b672 cpsid i
}
80007b6: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1) {
80007b8: e7fe b.n 80007b8 <Error_Handler+0x8>
...
080007bc <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80007bc: b580 push {r7, lr}
80007be: b082 sub sp, #8
80007c0: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80007c2: 2300 movs r3, #0
80007c4: 607b str r3, [r7, #4]
80007c6: 4b10 ldr r3, [pc, #64] ; (8000808 <HAL_MspInit+0x4c>)
80007c8: 6c5b ldr r3, [r3, #68] ; 0x44
80007ca: 4a0f ldr r2, [pc, #60] ; (8000808 <HAL_MspInit+0x4c>)
80007cc: f443 4380 orr.w r3, r3, #16384 ; 0x4000
80007d0: 6453 str r3, [r2, #68] ; 0x44
80007d2: 4b0d ldr r3, [pc, #52] ; (8000808 <HAL_MspInit+0x4c>)
80007d4: 6c5b ldr r3, [r3, #68] ; 0x44
80007d6: f403 4380 and.w r3, r3, #16384 ; 0x4000
80007da: 607b str r3, [r7, #4]
80007dc: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80007de: 2300 movs r3, #0
80007e0: 603b str r3, [r7, #0]
80007e2: 4b09 ldr r3, [pc, #36] ; (8000808 <HAL_MspInit+0x4c>)
80007e4: 6c1b ldr r3, [r3, #64] ; 0x40
80007e6: 4a08 ldr r2, [pc, #32] ; (8000808 <HAL_MspInit+0x4c>)
80007e8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
80007ec: 6413 str r3, [r2, #64] ; 0x40
80007ee: 4b06 ldr r3, [pc, #24] ; (8000808 <HAL_MspInit+0x4c>)
80007f0: 6c1b ldr r3, [r3, #64] ; 0x40
80007f2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80007f6: 603b str r3, [r7, #0]
80007f8: 683b ldr r3, [r7, #0]
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_0);
80007fa: 2007 movs r0, #7
80007fc: f000 f9d8 bl 8000bb0 <HAL_NVIC_SetPriorityGrouping>
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
8000800: bf00 nop
8000802: 3708 adds r7, #8
8000804: 46bd mov sp, r7
8000806: bd80 pop {r7, pc}
8000808: 40023800 .word 0x40023800
0800080c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
800080c: b580 push {r7, lr}
800080e: b08a sub sp, #40 ; 0x28
8000810: af00 add r7, sp, #0
8000812: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000814: f107 0314 add.w r3, r7, #20
8000818: 2200 movs r2, #0
800081a: 601a str r2, [r3, #0]
800081c: 605a str r2, [r3, #4]
800081e: 609a str r2, [r3, #8]
8000820: 60da str r2, [r3, #12]
8000822: 611a str r2, [r3, #16]
if(huart->Instance==USART2)
8000824: 687b ldr r3, [r7, #4]
8000826: 681b ldr r3, [r3, #0]
8000828: 4a19 ldr r2, [pc, #100] ; (8000890 <HAL_UART_MspInit+0x84>)
800082a: 4293 cmp r3, r2
800082c: d12b bne.n 8000886 <HAL_UART_MspInit+0x7a>
{
/* USER CODE BEGIN USART2_MspInit 0 */
/* USER CODE END USART2_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_USART2_CLK_ENABLE();
800082e: 2300 movs r3, #0
8000830: 613b str r3, [r7, #16]
8000832: 4b18 ldr r3, [pc, #96] ; (8000894 <HAL_UART_MspInit+0x88>)
8000834: 6c1b ldr r3, [r3, #64] ; 0x40
8000836: 4a17 ldr r2, [pc, #92] ; (8000894 <HAL_UART_MspInit+0x88>)
8000838: f443 3300 orr.w r3, r3, #131072 ; 0x20000
800083c: 6413 str r3, [r2, #64] ; 0x40
800083e: 4b15 ldr r3, [pc, #84] ; (8000894 <HAL_UART_MspInit+0x88>)
8000840: 6c1b ldr r3, [r3, #64] ; 0x40
8000842: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000846: 613b str r3, [r7, #16]
8000848: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOA_CLK_ENABLE();
800084a: 2300 movs r3, #0
800084c: 60fb str r3, [r7, #12]
800084e: 4b11 ldr r3, [pc, #68] ; (8000894 <HAL_UART_MspInit+0x88>)
8000850: 6b1b ldr r3, [r3, #48] ; 0x30
8000852: 4a10 ldr r2, [pc, #64] ; (8000894 <HAL_UART_MspInit+0x88>)
8000854: f043 0301 orr.w r3, r3, #1
8000858: 6313 str r3, [r2, #48] ; 0x30
800085a: 4b0e ldr r3, [pc, #56] ; (8000894 <HAL_UART_MspInit+0x88>)
800085c: 6b1b ldr r3, [r3, #48] ; 0x30
800085e: f003 0301 and.w r3, r3, #1
8000862: 60fb str r3, [r7, #12]
8000864: 68fb ldr r3, [r7, #12]
/**USART2 GPIO Configuration
PA2 ------> USART2_TX
PA3 ------> USART2_RX
*/
GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
8000866: 230c movs r3, #12
8000868: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800086a: 2302 movs r3, #2
800086c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800086e: 2300 movs r3, #0
8000870: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000872: 2303 movs r3, #3
8000874: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
8000876: 2307 movs r3, #7
8000878: 627b str r3, [r7, #36] ; 0x24
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800087a: f107 0314 add.w r3, r7, #20
800087e: 4619 mov r1, r3
8000880: 4805 ldr r0, [pc, #20] ; (8000898 <HAL_UART_MspInit+0x8c>)
8000882: f000 f9c9 bl 8000c18 <HAL_GPIO_Init>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
8000886: bf00 nop
8000888: 3728 adds r7, #40 ; 0x28
800088a: 46bd mov sp, r7
800088c: bd80 pop {r7, pc}
800088e: bf00 nop
8000890: 40004400 .word 0x40004400
8000894: 40023800 .word 0x40023800
8000898: 40020000 .word 0x40020000
0800089c <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
800089c: b480 push {r7}
800089e: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80008a0: e7fe b.n 80008a0 <NMI_Handler+0x4>
080008a2 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80008a2: b480 push {r7}
80008a4: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80008a6: e7fe b.n 80008a6 <HardFault_Handler+0x4>
080008a8 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80008a8: b480 push {r7}
80008aa: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80008ac: e7fe b.n 80008ac <MemManage_Handler+0x4>
080008ae <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80008ae: b480 push {r7}
80008b0: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80008b2: e7fe b.n 80008b2 <BusFault_Handler+0x4>
080008b4 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80008b4: b480 push {r7}
80008b6: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80008b8: e7fe b.n 80008b8 <UsageFault_Handler+0x4>
080008ba <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80008ba: b480 push {r7}
80008bc: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80008be: bf00 nop
80008c0: 46bd mov sp, r7
80008c2: f85d 7b04 ldr.w r7, [sp], #4
80008c6: 4770 bx lr
080008c8 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80008c8: b480 push {r7}
80008ca: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80008cc: bf00 nop
80008ce: 46bd mov sp, r7
80008d0: f85d 7b04 ldr.w r7, [sp], #4
80008d4: 4770 bx lr
080008d6 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
80008d6: b480 push {r7}
80008d8: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
80008da: bf00 nop
80008dc: 46bd mov sp, r7
80008de: f85d 7b04 ldr.w r7, [sp], #4
80008e2: 4770 bx lr
080008e4 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
80008e4: b580 push {r7, lr}
80008e6: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
80008e8: f000 f890 bl 8000a0c <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
80008ec: bf00 nop
80008ee: bd80 pop {r7, pc}
080008f0 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
80008f0: b480 push {r7}
80008f2: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
80008f4: 4b06 ldr r3, [pc, #24] ; (8000910 <SystemInit+0x20>)
80008f6: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88
80008fa: 4a05 ldr r2, [pc, #20] ; (8000910 <SystemInit+0x20>)
80008fc: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000
8000900: f8c2 3088 str.w r3, [r2, #136] ; 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
8000904: bf00 nop
8000906: 46bd mov sp, r7
8000908: f85d 7b04 ldr.w r7, [sp], #4
800090c: 4770 bx lr
800090e: bf00 nop
8000910: e000ed00 .word 0xe000ed00
08000914 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8000914: f8df d034 ldr.w sp, [pc, #52] ; 800094c <LoopFillZerobss+0x12>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8000918: 480d ldr r0, [pc, #52] ; (8000950 <LoopFillZerobss+0x16>)
ldr r1, =_edata
800091a: 490e ldr r1, [pc, #56] ; (8000954 <LoopFillZerobss+0x1a>)
ldr r2, =_sidata
800091c: 4a0e ldr r2, [pc, #56] ; (8000958 <LoopFillZerobss+0x1e>)
movs r3, #0
800091e: 2300 movs r3, #0
b LoopCopyDataInit
8000920: e002 b.n 8000928 <LoopCopyDataInit>
08000922 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8000922: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8000924: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8000926: 3304 adds r3, #4
08000928 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8000928: 18c4 adds r4, r0, r3
cmp r4, r1
800092a: 428c cmp r4, r1
bcc CopyDataInit
800092c: d3f9 bcc.n 8000922 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
800092e: 4a0b ldr r2, [pc, #44] ; (800095c <LoopFillZerobss+0x22>)
ldr r4, =_ebss
8000930: 4c0b ldr r4, [pc, #44] ; (8000960 <LoopFillZerobss+0x26>)
movs r3, #0
8000932: 2300 movs r3, #0
b LoopFillZerobss
8000934: e001 b.n 800093a <LoopFillZerobss>
08000936 <FillZerobss>:
FillZerobss:
str r3, [r2]
8000936: 6013 str r3, [r2, #0]
adds r2, r2, #4
8000938: 3204 adds r2, #4
0800093a <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
800093a: 42a2 cmp r2, r4
bcc FillZerobss
800093c: d3fb bcc.n 8000936 <FillZerobss>
/* Call the clock system initialization function.*/
bl SystemInit
800093e: f7ff ffd7 bl 80008f0 <SystemInit>
/* Call static constructors */
bl __libc_init_array
8000942: f001 fc23 bl 800218c <__libc_init_array>
/* Call the application's entry point.*/
bl main
8000946: f7ff fdc5 bl 80004d4 <main>
bx lr
800094a: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
800094c: 20020000 .word 0x20020000
ldr r0, =_sdata
8000950: 20000000 .word 0x20000000
ldr r1, =_edata
8000954: 2000000c .word 0x2000000c
ldr r2, =_sidata
8000958: 08002214 .word 0x08002214
ldr r2, =_sbss
800095c: 2000000c .word 0x2000000c
ldr r4, =_ebss
8000960: 2000007c .word 0x2000007c
08000964 <ADC_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8000964: e7fe b.n 8000964 <ADC_IRQHandler>
...
08000968 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8000968: b580 push {r7, lr}
800096a: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
800096c: 4b0e ldr r3, [pc, #56] ; (80009a8 <HAL_Init+0x40>)
800096e: 681b ldr r3, [r3, #0]
8000970: 4a0d ldr r2, [pc, #52] ; (80009a8 <HAL_Init+0x40>)
8000972: f443 7300 orr.w r3, r3, #512 ; 0x200
8000976: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8000978: 4b0b ldr r3, [pc, #44] ; (80009a8 <HAL_Init+0x40>)
800097a: 681b ldr r3, [r3, #0]
800097c: 4a0a ldr r2, [pc, #40] ; (80009a8 <HAL_Init+0x40>)
800097e: f443 6380 orr.w r3, r3, #1024 ; 0x400
8000982: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8000984: 4b08 ldr r3, [pc, #32] ; (80009a8 <HAL_Init+0x40>)
8000986: 681b ldr r3, [r3, #0]
8000988: 4a07 ldr r2, [pc, #28] ; (80009a8 <HAL_Init+0x40>)
800098a: f443 7380 orr.w r3, r3, #256 ; 0x100
800098e: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8000990: 2003 movs r0, #3
8000992: f000 f90d bl 8000bb0 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8000996: 2000 movs r0, #0
8000998: f000 f808 bl 80009ac <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
800099c: f7ff ff0e bl 80007bc <HAL_MspInit>
/* Return function status */
return HAL_OK;
80009a0: 2300 movs r3, #0
}
80009a2: 4618 mov r0, r3
80009a4: bd80 pop {r7, pc}
80009a6: bf00 nop
80009a8: 40023c00 .word 0x40023c00
080009ac <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
80009ac: b580 push {r7, lr}
80009ae: b082 sub sp, #8
80009b0: af00 add r7, sp, #0
80009b2: 6078 str r0, [r7, #4]
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
80009b4: 4b12 ldr r3, [pc, #72] ; (8000a00 <HAL_InitTick+0x54>)
80009b6: 681a ldr r2, [r3, #0]
80009b8: 4b12 ldr r3, [pc, #72] ; (8000a04 <HAL_InitTick+0x58>)
80009ba: 781b ldrb r3, [r3, #0]
80009bc: 4619 mov r1, r3
80009be: f44f 737a mov.w r3, #1000 ; 0x3e8
80009c2: fbb3 f3f1 udiv r3, r3, r1
80009c6: fbb2 f3f3 udiv r3, r2, r3
80009ca: 4618 mov r0, r3
80009cc: f000 f917 bl 8000bfe <HAL_SYSTICK_Config>
80009d0: 4603 mov r3, r0
80009d2: 2b00 cmp r3, #0
80009d4: d001 beq.n 80009da <HAL_InitTick+0x2e>
{
return HAL_ERROR;
80009d6: 2301 movs r3, #1
80009d8: e00e b.n 80009f8 <HAL_InitTick+0x4c>
}
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80009da: 687b ldr r3, [r7, #4]
80009dc: 2b0f cmp r3, #15
80009de: d80a bhi.n 80009f6 <HAL_InitTick+0x4a>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
80009e0: 2200 movs r2, #0
80009e2: 6879 ldr r1, [r7, #4]
80009e4: f04f 30ff mov.w r0, #4294967295
80009e8: f000 f8ed bl 8000bc6 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80009ec: 4a06 ldr r2, [pc, #24] ; (8000a08 <HAL_InitTick+0x5c>)
80009ee: 687b ldr r3, [r7, #4]
80009f0: 6013 str r3, [r2, #0]
{
return HAL_ERROR;
}
/* Return function status */
return HAL_OK;
80009f2: 2300 movs r3, #0
80009f4: e000 b.n 80009f8 <HAL_InitTick+0x4c>
return HAL_ERROR;
80009f6: 2301 movs r3, #1
}
80009f8: 4618 mov r0, r3
80009fa: 3708 adds r7, #8
80009fc: 46bd mov sp, r7
80009fe: bd80 pop {r7, pc}
8000a00: 20000000 .word 0x20000000
8000a04: 20000008 .word 0x20000008
8000a08: 20000004 .word 0x20000004
08000a0c <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8000a0c: b480 push {r7}
8000a0e: af00 add r7, sp, #0
uwTick += uwTickFreq;
8000a10: 4b06 ldr r3, [pc, #24] ; (8000a2c <HAL_IncTick+0x20>)
8000a12: 781b ldrb r3, [r3, #0]
8000a14: 461a mov r2, r3
8000a16: 4b06 ldr r3, [pc, #24] ; (8000a30 <HAL_IncTick+0x24>)
8000a18: 681b ldr r3, [r3, #0]
8000a1a: 4413 add r3, r2
8000a1c: 4a04 ldr r2, [pc, #16] ; (8000a30 <HAL_IncTick+0x24>)
8000a1e: 6013 str r3, [r2, #0]
}
8000a20: bf00 nop
8000a22: 46bd mov sp, r7
8000a24: f85d 7b04 ldr.w r7, [sp], #4
8000a28: 4770 bx lr
8000a2a: bf00 nop
8000a2c: 20000008 .word 0x20000008
8000a30: 20000078 .word 0x20000078
08000a34 <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8000a34: b480 push {r7}
8000a36: af00 add r7, sp, #0
return uwTick;
8000a38: 4b03 ldr r3, [pc, #12] ; (8000a48 <HAL_GetTick+0x14>)
8000a3a: 681b ldr r3, [r3, #0]
}
8000a3c: 4618 mov r0, r3
8000a3e: 46bd mov sp, r7
8000a40: f85d 7b04 ldr.w r7, [sp], #4
8000a44: 4770 bx lr
8000a46: bf00 nop
8000a48: 20000078 .word 0x20000078
08000a4c <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000a4c: b480 push {r7}
8000a4e: b085 sub sp, #20
8000a50: af00 add r7, sp, #0
8000a52: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000a54: 687b ldr r3, [r7, #4]
8000a56: f003 0307 and.w r3, r3, #7
8000a5a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8000a5c: 4b0c ldr r3, [pc, #48] ; (8000a90 <__NVIC_SetPriorityGrouping+0x44>)
8000a5e: 68db ldr r3, [r3, #12]
8000a60: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8000a62: 68ba ldr r2, [r7, #8]
8000a64: f64f 03ff movw r3, #63743 ; 0xf8ff
8000a68: 4013 ands r3, r2
8000a6a: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8000a6c: 68fb ldr r3, [r7, #12]
8000a6e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000a70: 68bb ldr r3, [r7, #8]
8000a72: 4313 orrs r3, r2
reg_value = (reg_value |
8000a74: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000
8000a78: f443 3300 orr.w r3, r3, #131072 ; 0x20000
8000a7c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8000a7e: 4a04 ldr r2, [pc, #16] ; (8000a90 <__NVIC_SetPriorityGrouping+0x44>)
8000a80: 68bb ldr r3, [r7, #8]
8000a82: 60d3 str r3, [r2, #12]
}
8000a84: bf00 nop
8000a86: 3714 adds r7, #20
8000a88: 46bd mov sp, r7
8000a8a: f85d 7b04 ldr.w r7, [sp], #4
8000a8e: 4770 bx lr
8000a90: e000ed00 .word 0xe000ed00
08000a94 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8000a94: b480 push {r7}
8000a96: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8000a98: 4b04 ldr r3, [pc, #16] ; (8000aac <__NVIC_GetPriorityGrouping+0x18>)
8000a9a: 68db ldr r3, [r3, #12]
8000a9c: 0a1b lsrs r3, r3, #8
8000a9e: f003 0307 and.w r3, r3, #7
}
8000aa2: 4618 mov r0, r3
8000aa4: 46bd mov sp, r7
8000aa6: f85d 7b04 ldr.w r7, [sp], #4
8000aaa: 4770 bx lr
8000aac: e000ed00 .word 0xe000ed00
08000ab0 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8000ab0: b480 push {r7}
8000ab2: b083 sub sp, #12
8000ab4: af00 add r7, sp, #0
8000ab6: 4603 mov r3, r0
8000ab8: 6039 str r1, [r7, #0]
8000aba: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8000abc: f997 3007 ldrsb.w r3, [r7, #7]
8000ac0: 2b00 cmp r3, #0
8000ac2: db0a blt.n 8000ada <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000ac4: 683b ldr r3, [r7, #0]
8000ac6: b2da uxtb r2, r3
8000ac8: 490c ldr r1, [pc, #48] ; (8000afc <__NVIC_SetPriority+0x4c>)
8000aca: f997 3007 ldrsb.w r3, [r7, #7]
8000ace: 0112 lsls r2, r2, #4
8000ad0: b2d2 uxtb r2, r2
8000ad2: 440b add r3, r1
8000ad4: f883 2300 strb.w r2, [r3, #768] ; 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8000ad8: e00a b.n 8000af0 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8000ada: 683b ldr r3, [r7, #0]
8000adc: b2da uxtb r2, r3
8000ade: 4908 ldr r1, [pc, #32] ; (8000b00 <__NVIC_SetPriority+0x50>)
8000ae0: 79fb ldrb r3, [r7, #7]
8000ae2: f003 030f and.w r3, r3, #15
8000ae6: 3b04 subs r3, #4
8000ae8: 0112 lsls r2, r2, #4
8000aea: b2d2 uxtb r2, r2
8000aec: 440b add r3, r1
8000aee: 761a strb r2, [r3, #24]
}
8000af0: bf00 nop
8000af2: 370c adds r7, #12
8000af4: 46bd mov sp, r7
8000af6: f85d 7b04 ldr.w r7, [sp], #4
8000afa: 4770 bx lr
8000afc: e000e100 .word 0xe000e100
8000b00: e000ed00 .word 0xe000ed00
08000b04 <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000b04: b480 push {r7}
8000b06: b089 sub sp, #36 ; 0x24
8000b08: af00 add r7, sp, #0
8000b0a: 60f8 str r0, [r7, #12]
8000b0c: 60b9 str r1, [r7, #8]
8000b0e: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8000b10: 68fb ldr r3, [r7, #12]
8000b12: f003 0307 and.w r3, r3, #7
8000b16: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8000b18: 69fb ldr r3, [r7, #28]
8000b1a: f1c3 0307 rsb r3, r3, #7
8000b1e: 2b04 cmp r3, #4
8000b20: bf28 it cs
8000b22: 2304 movcs r3, #4
8000b24: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8000b26: 69fb ldr r3, [r7, #28]
8000b28: 3304 adds r3, #4
8000b2a: 2b06 cmp r3, #6
8000b2c: d902 bls.n 8000b34 <NVIC_EncodePriority+0x30>
8000b2e: 69fb ldr r3, [r7, #28]
8000b30: 3b03 subs r3, #3
8000b32: e000 b.n 8000b36 <NVIC_EncodePriority+0x32>
8000b34: 2300 movs r3, #0
8000b36: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000b38: f04f 32ff mov.w r2, #4294967295
8000b3c: 69bb ldr r3, [r7, #24]
8000b3e: fa02 f303 lsl.w r3, r2, r3
8000b42: 43da mvns r2, r3
8000b44: 68bb ldr r3, [r7, #8]
8000b46: 401a ands r2, r3
8000b48: 697b ldr r3, [r7, #20]
8000b4a: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8000b4c: f04f 31ff mov.w r1, #4294967295
8000b50: 697b ldr r3, [r7, #20]
8000b52: fa01 f303 lsl.w r3, r1, r3
8000b56: 43d9 mvns r1, r3
8000b58: 687b ldr r3, [r7, #4]
8000b5a: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8000b5c: 4313 orrs r3, r2
);
}
8000b5e: 4618 mov r0, r3
8000b60: 3724 adds r7, #36 ; 0x24
8000b62: 46bd mov sp, r7
8000b64: f85d 7b04 ldr.w r7, [sp], #4
8000b68: 4770 bx lr
...
08000b6c <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8000b6c: b580 push {r7, lr}
8000b6e: b082 sub sp, #8
8000b70: af00 add r7, sp, #0
8000b72: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8000b74: 687b ldr r3, [r7, #4]
8000b76: 3b01 subs r3, #1
8000b78: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000
8000b7c: d301 bcc.n 8000b82 <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8000b7e: 2301 movs r3, #1
8000b80: e00f b.n 8000ba2 <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8000b82: 4a0a ldr r2, [pc, #40] ; (8000bac <SysTick_Config+0x40>)
8000b84: 687b ldr r3, [r7, #4]
8000b86: 3b01 subs r3, #1
8000b88: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8000b8a: 210f movs r1, #15
8000b8c: f04f 30ff mov.w r0, #4294967295
8000b90: f7ff ff8e bl 8000ab0 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8000b94: 4b05 ldr r3, [pc, #20] ; (8000bac <SysTick_Config+0x40>)
8000b96: 2200 movs r2, #0
8000b98: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8000b9a: 4b04 ldr r3, [pc, #16] ; (8000bac <SysTick_Config+0x40>)
8000b9c: 2207 movs r2, #7
8000b9e: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8000ba0: 2300 movs r3, #0
}
8000ba2: 4618 mov r0, r3
8000ba4: 3708 adds r7, #8
8000ba6: 46bd mov sp, r7
8000ba8: bd80 pop {r7, pc}
8000baa: bf00 nop
8000bac: e000e010 .word 0xe000e010
08000bb0 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8000bb0: b580 push {r7, lr}
8000bb2: b082 sub sp, #8
8000bb4: af00 add r7, sp, #0
8000bb6: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8000bb8: 6878 ldr r0, [r7, #4]
8000bba: f7ff ff47 bl 8000a4c <__NVIC_SetPriorityGrouping>
}
8000bbe: bf00 nop
8000bc0: 3708 adds r7, #8
8000bc2: 46bd mov sp, r7
8000bc4: bd80 pop {r7, pc}
08000bc6 <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8000bc6: b580 push {r7, lr}
8000bc8: b086 sub sp, #24
8000bca: af00 add r7, sp, #0
8000bcc: 4603 mov r3, r0
8000bce: 60b9 str r1, [r7, #8]
8000bd0: 607a str r2, [r7, #4]
8000bd2: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8000bd4: 2300 movs r3, #0
8000bd6: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8000bd8: f7ff ff5c bl 8000a94 <__NVIC_GetPriorityGrouping>
8000bdc: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8000bde: 687a ldr r2, [r7, #4]
8000be0: 68b9 ldr r1, [r7, #8]
8000be2: 6978 ldr r0, [r7, #20]
8000be4: f7ff ff8e bl 8000b04 <NVIC_EncodePriority>
8000be8: 4602 mov r2, r0
8000bea: f997 300f ldrsb.w r3, [r7, #15]
8000bee: 4611 mov r1, r2
8000bf0: 4618 mov r0, r3
8000bf2: f7ff ff5d bl 8000ab0 <__NVIC_SetPriority>
}
8000bf6: bf00 nop
8000bf8: 3718 adds r7, #24
8000bfa: 46bd mov sp, r7
8000bfc: bd80 pop {r7, pc}
08000bfe <HAL_SYSTICK_Config>:
* @param TicksNumb Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8000bfe: b580 push {r7, lr}
8000c00: b082 sub sp, #8
8000c02: af00 add r7, sp, #0
8000c04: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8000c06: 6878 ldr r0, [r7, #4]
8000c08: f7ff ffb0 bl 8000b6c <SysTick_Config>
8000c0c: 4603 mov r3, r0
}
8000c0e: 4618 mov r0, r3
8000c10: 3708 adds r7, #8
8000c12: 46bd mov sp, r7
8000c14: bd80 pop {r7, pc}
...
08000c18 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
8000c18: b480 push {r7}
8000c1a: b089 sub sp, #36 ; 0x24
8000c1c: af00 add r7, sp, #0
8000c1e: 6078 str r0, [r7, #4]
8000c20: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
8000c22: 2300 movs r3, #0
8000c24: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
8000c26: 2300 movs r3, #0
8000c28: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
8000c2a: 2300 movs r3, #0
8000c2c: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
8000c2e: 2300 movs r3, #0
8000c30: 61fb str r3, [r7, #28]
8000c32: e159 b.n 8000ee8 <HAL_GPIO_Init+0x2d0>
{
/* Get the IO position */
ioposition = 0x01U << position;
8000c34: 2201 movs r2, #1
8000c36: 69fb ldr r3, [r7, #28]
8000c38: fa02 f303 lsl.w r3, r2, r3
8000c3c: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
8000c3e: 683b ldr r3, [r7, #0]
8000c40: 681b ldr r3, [r3, #0]
8000c42: 697a ldr r2, [r7, #20]
8000c44: 4013 ands r3, r2
8000c46: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
8000c48: 693a ldr r2, [r7, #16]
8000c4a: 697b ldr r3, [r7, #20]
8000c4c: 429a cmp r2, r3
8000c4e: f040 8148 bne.w 8000ee2 <HAL_GPIO_Init+0x2ca>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8000c52: 683b ldr r3, [r7, #0]
8000c54: 685b ldr r3, [r3, #4]
8000c56: f003 0303 and.w r3, r3, #3
8000c5a: 2b01 cmp r3, #1
8000c5c: d005 beq.n 8000c6a <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000c5e: 683b ldr r3, [r7, #0]
8000c60: 685b ldr r3, [r3, #4]
8000c62: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
8000c66: 2b02 cmp r3, #2
8000c68: d130 bne.n 8000ccc <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8000c6a: 687b ldr r3, [r7, #4]
8000c6c: 689b ldr r3, [r3, #8]
8000c6e: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
8000c70: 69fb ldr r3, [r7, #28]
8000c72: 005b lsls r3, r3, #1
8000c74: 2203 movs r2, #3
8000c76: fa02 f303 lsl.w r3, r2, r3
8000c7a: 43db mvns r3, r3
8000c7c: 69ba ldr r2, [r7, #24]
8000c7e: 4013 ands r3, r2
8000c80: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
8000c82: 683b ldr r3, [r7, #0]
8000c84: 68da ldr r2, [r3, #12]
8000c86: 69fb ldr r3, [r7, #28]
8000c88: 005b lsls r3, r3, #1
8000c8a: fa02 f303 lsl.w r3, r2, r3
8000c8e: 69ba ldr r2, [r7, #24]
8000c90: 4313 orrs r3, r2
8000c92: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
8000c94: 687b ldr r3, [r7, #4]
8000c96: 69ba ldr r2, [r7, #24]
8000c98: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8000c9a: 687b ldr r3, [r7, #4]
8000c9c: 685b ldr r3, [r3, #4]
8000c9e: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8000ca0: 2201 movs r2, #1
8000ca2: 69fb ldr r3, [r7, #28]
8000ca4: fa02 f303 lsl.w r3, r2, r3
8000ca8: 43db mvns r3, r3
8000caa: 69ba ldr r2, [r7, #24]
8000cac: 4013 ands r3, r2
8000cae: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8000cb0: 683b ldr r3, [r7, #0]
8000cb2: 685b ldr r3, [r3, #4]
8000cb4: 091b lsrs r3, r3, #4
8000cb6: f003 0201 and.w r2, r3, #1
8000cba: 69fb ldr r3, [r7, #28]
8000cbc: fa02 f303 lsl.w r3, r2, r3
8000cc0: 69ba ldr r2, [r7, #24]
8000cc2: 4313 orrs r3, r2
8000cc4: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
8000cc6: 687b ldr r3, [r7, #4]
8000cc8: 69ba ldr r2, [r7, #24]
8000cca: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8000ccc: 683b ldr r3, [r7, #0]
8000cce: 685b ldr r3, [r3, #4]
8000cd0: f003 0303 and.w r3, r3, #3
8000cd4: 2b03 cmp r3, #3
8000cd6: d017 beq.n 8000d08 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8000cd8: 687b ldr r3, [r7, #4]
8000cda: 68db ldr r3, [r3, #12]
8000cdc: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8000cde: 69fb ldr r3, [r7, #28]
8000ce0: 005b lsls r3, r3, #1
8000ce2: 2203 movs r2, #3
8000ce4: fa02 f303 lsl.w r3, r2, r3
8000ce8: 43db mvns r3, r3
8000cea: 69ba ldr r2, [r7, #24]
8000cec: 4013 ands r3, r2
8000cee: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8000cf0: 683b ldr r3, [r7, #0]
8000cf2: 689a ldr r2, [r3, #8]
8000cf4: 69fb ldr r3, [r7, #28]
8000cf6: 005b lsls r3, r3, #1
8000cf8: fa02 f303 lsl.w r3, r2, r3
8000cfc: 69ba ldr r2, [r7, #24]
8000cfe: 4313 orrs r3, r2
8000d00: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
8000d02: 687b ldr r3, [r7, #4]
8000d04: 69ba ldr r2, [r7, #24]
8000d06: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8000d08: 683b ldr r3, [r7, #0]
8000d0a: 685b ldr r3, [r3, #4]
8000d0c: f003 0303 and.w r3, r3, #3
8000d10: 2b02 cmp r3, #2
8000d12: d123 bne.n 8000d5c <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
8000d14: 69fb ldr r3, [r7, #28]
8000d16: 08da lsrs r2, r3, #3
8000d18: 687b ldr r3, [r7, #4]
8000d1a: 3208 adds r2, #8
8000d1c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
8000d20: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
8000d22: 69fb ldr r3, [r7, #28]
8000d24: f003 0307 and.w r3, r3, #7
8000d28: 009b lsls r3, r3, #2
8000d2a: 220f movs r2, #15
8000d2c: fa02 f303 lsl.w r3, r2, r3
8000d30: 43db mvns r3, r3
8000d32: 69ba ldr r2, [r7, #24]
8000d34: 4013 ands r3, r2
8000d36: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
8000d38: 683b ldr r3, [r7, #0]
8000d3a: 691a ldr r2, [r3, #16]
8000d3c: 69fb ldr r3, [r7, #28]
8000d3e: f003 0307 and.w r3, r3, #7
8000d42: 009b lsls r3, r3, #2
8000d44: fa02 f303 lsl.w r3, r2, r3
8000d48: 69ba ldr r2, [r7, #24]
8000d4a: 4313 orrs r3, r2
8000d4c: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
8000d4e: 69fb ldr r3, [r7, #28]
8000d50: 08da lsrs r2, r3, #3
8000d52: 687b ldr r3, [r7, #4]
8000d54: 3208 adds r2, #8
8000d56: 69b9 ldr r1, [r7, #24]
8000d58: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
8000d5c: 687b ldr r3, [r7, #4]
8000d5e: 681b ldr r3, [r3, #0]
8000d60: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
8000d62: 69fb ldr r3, [r7, #28]
8000d64: 005b lsls r3, r3, #1
8000d66: 2203 movs r2, #3
8000d68: fa02 f303 lsl.w r3, r2, r3
8000d6c: 43db mvns r3, r3
8000d6e: 69ba ldr r2, [r7, #24]
8000d70: 4013 ands r3, r2
8000d72: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8000d74: 683b ldr r3, [r7, #0]
8000d76: 685b ldr r3, [r3, #4]
8000d78: f003 0203 and.w r2, r3, #3
8000d7c: 69fb ldr r3, [r7, #28]
8000d7e: 005b lsls r3, r3, #1
8000d80: fa02 f303 lsl.w r3, r2, r3
8000d84: 69ba ldr r2, [r7, #24]
8000d86: 4313 orrs r3, r2
8000d88: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8000d8a: 687b ldr r3, [r7, #4]
8000d8c: 69ba ldr r2, [r7, #24]
8000d8e: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8000d90: 683b ldr r3, [r7, #0]
8000d92: 685b ldr r3, [r3, #4]
8000d94: f403 3340 and.w r3, r3, #196608 ; 0x30000
8000d98: 2b00 cmp r3, #0
8000d9a: f000 80a2 beq.w 8000ee2 <HAL_GPIO_Init+0x2ca>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8000d9e: 2300 movs r3, #0
8000da0: 60fb str r3, [r7, #12]
8000da2: 4b57 ldr r3, [pc, #348] ; (8000f00 <HAL_GPIO_Init+0x2e8>)
8000da4: 6c5b ldr r3, [r3, #68] ; 0x44
8000da6: 4a56 ldr r2, [pc, #344] ; (8000f00 <HAL_GPIO_Init+0x2e8>)
8000da8: f443 4380 orr.w r3, r3, #16384 ; 0x4000
8000dac: 6453 str r3, [r2, #68] ; 0x44
8000dae: 4b54 ldr r3, [pc, #336] ; (8000f00 <HAL_GPIO_Init+0x2e8>)
8000db0: 6c5b ldr r3, [r3, #68] ; 0x44
8000db2: f403 4380 and.w r3, r3, #16384 ; 0x4000
8000db6: 60fb str r3, [r7, #12]
8000db8: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8000dba: 4a52 ldr r2, [pc, #328] ; (8000f04 <HAL_GPIO_Init+0x2ec>)
8000dbc: 69fb ldr r3, [r7, #28]
8000dbe: 089b lsrs r3, r3, #2
8000dc0: 3302 adds r3, #2
8000dc2: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8000dc6: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8000dc8: 69fb ldr r3, [r7, #28]
8000dca: f003 0303 and.w r3, r3, #3
8000dce: 009b lsls r3, r3, #2
8000dd0: 220f movs r2, #15
8000dd2: fa02 f303 lsl.w r3, r2, r3
8000dd6: 43db mvns r3, r3
8000dd8: 69ba ldr r2, [r7, #24]
8000dda: 4013 ands r3, r2
8000ddc: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8000dde: 687b ldr r3, [r7, #4]
8000de0: 4a49 ldr r2, [pc, #292] ; (8000f08 <HAL_GPIO_Init+0x2f0>)
8000de2: 4293 cmp r3, r2
8000de4: d019 beq.n 8000e1a <HAL_GPIO_Init+0x202>
8000de6: 687b ldr r3, [r7, #4]
8000de8: 4a48 ldr r2, [pc, #288] ; (8000f0c <HAL_GPIO_Init+0x2f4>)
8000dea: 4293 cmp r3, r2
8000dec: d013 beq.n 8000e16 <HAL_GPIO_Init+0x1fe>
8000dee: 687b ldr r3, [r7, #4]
8000df0: 4a47 ldr r2, [pc, #284] ; (8000f10 <HAL_GPIO_Init+0x2f8>)
8000df2: 4293 cmp r3, r2
8000df4: d00d beq.n 8000e12 <HAL_GPIO_Init+0x1fa>
8000df6: 687b ldr r3, [r7, #4]
8000df8: 4a46 ldr r2, [pc, #280] ; (8000f14 <HAL_GPIO_Init+0x2fc>)
8000dfa: 4293 cmp r3, r2
8000dfc: d007 beq.n 8000e0e <HAL_GPIO_Init+0x1f6>
8000dfe: 687b ldr r3, [r7, #4]
8000e00: 4a45 ldr r2, [pc, #276] ; (8000f18 <HAL_GPIO_Init+0x300>)
8000e02: 4293 cmp r3, r2
8000e04: d101 bne.n 8000e0a <HAL_GPIO_Init+0x1f2>
8000e06: 2304 movs r3, #4
8000e08: e008 b.n 8000e1c <HAL_GPIO_Init+0x204>
8000e0a: 2307 movs r3, #7
8000e0c: e006 b.n 8000e1c <HAL_GPIO_Init+0x204>
8000e0e: 2303 movs r3, #3
8000e10: e004 b.n 8000e1c <HAL_GPIO_Init+0x204>
8000e12: 2302 movs r3, #2
8000e14: e002 b.n 8000e1c <HAL_GPIO_Init+0x204>
8000e16: 2301 movs r3, #1
8000e18: e000 b.n 8000e1c <HAL_GPIO_Init+0x204>
8000e1a: 2300 movs r3, #0
8000e1c: 69fa ldr r2, [r7, #28]
8000e1e: f002 0203 and.w r2, r2, #3
8000e22: 0092 lsls r2, r2, #2
8000e24: 4093 lsls r3, r2
8000e26: 69ba ldr r2, [r7, #24]
8000e28: 4313 orrs r3, r2
8000e2a: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
8000e2c: 4935 ldr r1, [pc, #212] ; (8000f04 <HAL_GPIO_Init+0x2ec>)
8000e2e: 69fb ldr r3, [r7, #28]
8000e30: 089b lsrs r3, r3, #2
8000e32: 3302 adds r3, #2
8000e34: 69ba ldr r2, [r7, #24]
8000e36: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
8000e3a: 4b38 ldr r3, [pc, #224] ; (8000f1c <HAL_GPIO_Init+0x304>)
8000e3c: 689b ldr r3, [r3, #8]
8000e3e: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8000e40: 693b ldr r3, [r7, #16]
8000e42: 43db mvns r3, r3
8000e44: 69ba ldr r2, [r7, #24]
8000e46: 4013 ands r3, r2
8000e48: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8000e4a: 683b ldr r3, [r7, #0]
8000e4c: 685b ldr r3, [r3, #4]
8000e4e: f403 1380 and.w r3, r3, #1048576 ; 0x100000
8000e52: 2b00 cmp r3, #0
8000e54: d003 beq.n 8000e5e <HAL_GPIO_Init+0x246>
{
temp |= iocurrent;
8000e56: 69ba ldr r2, [r7, #24]
8000e58: 693b ldr r3, [r7, #16]
8000e5a: 4313 orrs r3, r2
8000e5c: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
8000e5e: 4a2f ldr r2, [pc, #188] ; (8000f1c <HAL_GPIO_Init+0x304>)
8000e60: 69bb ldr r3, [r7, #24]
8000e62: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8000e64: 4b2d ldr r3, [pc, #180] ; (8000f1c <HAL_GPIO_Init+0x304>)
8000e66: 68db ldr r3, [r3, #12]
8000e68: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8000e6a: 693b ldr r3, [r7, #16]
8000e6c: 43db mvns r3, r3
8000e6e: 69ba ldr r2, [r7, #24]
8000e70: 4013 ands r3, r2
8000e72: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8000e74: 683b ldr r3, [r7, #0]
8000e76: 685b ldr r3, [r3, #4]
8000e78: f403 1300 and.w r3, r3, #2097152 ; 0x200000
8000e7c: 2b00 cmp r3, #0
8000e7e: d003 beq.n 8000e88 <HAL_GPIO_Init+0x270>
{
temp |= iocurrent;
8000e80: 69ba ldr r2, [r7, #24]
8000e82: 693b ldr r3, [r7, #16]
8000e84: 4313 orrs r3, r2
8000e86: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8000e88: 4a24 ldr r2, [pc, #144] ; (8000f1c <HAL_GPIO_Init+0x304>)
8000e8a: 69bb ldr r3, [r7, #24]
8000e8c: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
8000e8e: 4b23 ldr r3, [pc, #140] ; (8000f1c <HAL_GPIO_Init+0x304>)
8000e90: 685b ldr r3, [r3, #4]
8000e92: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8000e94: 693b ldr r3, [r7, #16]
8000e96: 43db mvns r3, r3
8000e98: 69ba ldr r2, [r7, #24]
8000e9a: 4013 ands r3, r2
8000e9c: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8000e9e: 683b ldr r3, [r7, #0]
8000ea0: 685b ldr r3, [r3, #4]
8000ea2: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000ea6: 2b00 cmp r3, #0
8000ea8: d003 beq.n 8000eb2 <HAL_GPIO_Init+0x29a>
{
temp |= iocurrent;
8000eaa: 69ba ldr r2, [r7, #24]
8000eac: 693b ldr r3, [r7, #16]
8000eae: 4313 orrs r3, r2
8000eb0: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8000eb2: 4a1a ldr r2, [pc, #104] ; (8000f1c <HAL_GPIO_Init+0x304>)
8000eb4: 69bb ldr r3, [r7, #24]
8000eb6: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8000eb8: 4b18 ldr r3, [pc, #96] ; (8000f1c <HAL_GPIO_Init+0x304>)
8000eba: 681b ldr r3, [r3, #0]
8000ebc: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8000ebe: 693b ldr r3, [r7, #16]
8000ec0: 43db mvns r3, r3
8000ec2: 69ba ldr r2, [r7, #24]
8000ec4: 4013 ands r3, r2
8000ec6: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8000ec8: 683b ldr r3, [r7, #0]
8000eca: 685b ldr r3, [r3, #4]
8000ecc: f403 3380 and.w r3, r3, #65536 ; 0x10000
8000ed0: 2b00 cmp r3, #0
8000ed2: d003 beq.n 8000edc <HAL_GPIO_Init+0x2c4>
{
temp |= iocurrent;
8000ed4: 69ba ldr r2, [r7, #24]
8000ed6: 693b ldr r3, [r7, #16]
8000ed8: 4313 orrs r3, r2
8000eda: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
8000edc: 4a0f ldr r2, [pc, #60] ; (8000f1c <HAL_GPIO_Init+0x304>)
8000ede: 69bb ldr r3, [r7, #24]
8000ee0: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
8000ee2: 69fb ldr r3, [r7, #28]
8000ee4: 3301 adds r3, #1
8000ee6: 61fb str r3, [r7, #28]
8000ee8: 69fb ldr r3, [r7, #28]
8000eea: 2b0f cmp r3, #15
8000eec: f67f aea2 bls.w 8000c34 <HAL_GPIO_Init+0x1c>
}
}
}
}
8000ef0: bf00 nop
8000ef2: bf00 nop
8000ef4: 3724 adds r7, #36 ; 0x24
8000ef6: 46bd mov sp, r7
8000ef8: f85d 7b04 ldr.w r7, [sp], #4
8000efc: 4770 bx lr
8000efe: bf00 nop
8000f00: 40023800 .word 0x40023800
8000f04: 40013800 .word 0x40013800
8000f08: 40020000 .word 0x40020000
8000f0c: 40020400 .word 0x40020400
8000f10: 40020800 .word 0x40020800
8000f14: 40020c00 .word 0x40020c00
8000f18: 40021000 .word 0x40021000
8000f1c: 40013c00 .word 0x40013c00
08000f20 <HAL_GPIO_ReadPin>:
* @param GPIO_Pin specifies the port bit to read.
* This parameter can be GPIO_PIN_x where x can be (0..15).
* @retval The input port pin value.
*/
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
8000f20: b480 push {r7}
8000f22: b085 sub sp, #20
8000f24: af00 add r7, sp, #0
8000f26: 6078 str r0, [r7, #4]
8000f28: 460b mov r3, r1
8000f2a: 807b strh r3, [r7, #2]
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
8000f2c: 687b ldr r3, [r7, #4]
8000f2e: 691a ldr r2, [r3, #16]
8000f30: 887b ldrh r3, [r7, #2]
8000f32: 4013 ands r3, r2
8000f34: 2b00 cmp r3, #0
8000f36: d002 beq.n 8000f3e <HAL_GPIO_ReadPin+0x1e>
{
bitstatus = GPIO_PIN_SET;
8000f38: 2301 movs r3, #1
8000f3a: 73fb strb r3, [r7, #15]
8000f3c: e001 b.n 8000f42 <HAL_GPIO_ReadPin+0x22>
}
else
{
bitstatus = GPIO_PIN_RESET;
8000f3e: 2300 movs r3, #0
8000f40: 73fb strb r3, [r7, #15]
}
return bitstatus;
8000f42: 7bfb ldrb r3, [r7, #15]
}
8000f44: 4618 mov r0, r3
8000f46: 3714 adds r7, #20
8000f48: 46bd mov sp, r7
8000f4a: f85d 7b04 ldr.w r7, [sp], #4
8000f4e: 4770 bx lr
08000f50 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8000f50: b480 push {r7}
8000f52: b083 sub sp, #12
8000f54: af00 add r7, sp, #0
8000f56: 6078 str r0, [r7, #4]
8000f58: 460b mov r3, r1
8000f5a: 807b strh r3, [r7, #2]
8000f5c: 4613 mov r3, r2
8000f5e: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
8000f60: 787b ldrb r3, [r7, #1]
8000f62: 2b00 cmp r3, #0
8000f64: d003 beq.n 8000f6e <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
8000f66: 887a ldrh r2, [r7, #2]
8000f68: 687b ldr r3, [r7, #4]
8000f6a: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
8000f6c: e003 b.n 8000f76 <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
8000f6e: 887b ldrh r3, [r7, #2]
8000f70: 041a lsls r2, r3, #16
8000f72: 687b ldr r3, [r7, #4]
8000f74: 619a str r2, [r3, #24]
}
8000f76: bf00 nop
8000f78: 370c adds r7, #12
8000f7a: 46bd mov sp, r7
8000f7c: f85d 7b04 ldr.w r7, [sp], #4
8000f80: 4770 bx lr
...
08000f84 <HAL_RCC_OscConfig>:
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8000f84: b580 push {r7, lr}
8000f86: b086 sub sp, #24
8000f88: af00 add r7, sp, #0
8000f8a: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8000f8c: 687b ldr r3, [r7, #4]
8000f8e: 2b00 cmp r3, #0
8000f90: d101 bne.n 8000f96 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8000f92: 2301 movs r3, #1
8000f94: e267 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8000f96: 687b ldr r3, [r7, #4]
8000f98: 681b ldr r3, [r3, #0]
8000f9a: f003 0301 and.w r3, r3, #1
8000f9e: 2b00 cmp r3, #0
8000fa0: d075 beq.n 800108e <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8000fa2: 4b88 ldr r3, [pc, #544] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8000fa4: 689b ldr r3, [r3, #8]
8000fa6: f003 030c and.w r3, r3, #12
8000faa: 2b04 cmp r3, #4
8000fac: d00c beq.n 8000fc8 <HAL_RCC_OscConfig+0x44>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8000fae: 4b85 ldr r3, [pc, #532] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8000fb0: 689b ldr r3, [r3, #8]
8000fb2: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8000fb6: 2b08 cmp r3, #8
8000fb8: d112 bne.n 8000fe0 <HAL_RCC_OscConfig+0x5c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8000fba: 4b82 ldr r3, [pc, #520] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8000fbc: 685b ldr r3, [r3, #4]
8000fbe: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8000fc2: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000
8000fc6: d10b bne.n 8000fe0 <HAL_RCC_OscConfig+0x5c>
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8000fc8: 4b7e ldr r3, [pc, #504] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8000fca: 681b ldr r3, [r3, #0]
8000fcc: f403 3300 and.w r3, r3, #131072 ; 0x20000
8000fd0: 2b00 cmp r3, #0
8000fd2: d05b beq.n 800108c <HAL_RCC_OscConfig+0x108>
8000fd4: 687b ldr r3, [r7, #4]
8000fd6: 685b ldr r3, [r3, #4]
8000fd8: 2b00 cmp r3, #0
8000fda: d157 bne.n 800108c <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8000fdc: 2301 movs r3, #1
8000fde: e242 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8000fe0: 687b ldr r3, [r7, #4]
8000fe2: 685b ldr r3, [r3, #4]
8000fe4: f5b3 3f80 cmp.w r3, #65536 ; 0x10000
8000fe8: d106 bne.n 8000ff8 <HAL_RCC_OscConfig+0x74>
8000fea: 4b76 ldr r3, [pc, #472] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8000fec: 681b ldr r3, [r3, #0]
8000fee: 4a75 ldr r2, [pc, #468] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8000ff0: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8000ff4: 6013 str r3, [r2, #0]
8000ff6: e01d b.n 8001034 <HAL_RCC_OscConfig+0xb0>
8000ff8: 687b ldr r3, [r7, #4]
8000ffa: 685b ldr r3, [r3, #4]
8000ffc: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000
8001000: d10c bne.n 800101c <HAL_RCC_OscConfig+0x98>
8001002: 4b70 ldr r3, [pc, #448] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001004: 681b ldr r3, [r3, #0]
8001006: 4a6f ldr r2, [pc, #444] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001008: f443 2380 orr.w r3, r3, #262144 ; 0x40000
800100c: 6013 str r3, [r2, #0]
800100e: 4b6d ldr r3, [pc, #436] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001010: 681b ldr r3, [r3, #0]
8001012: 4a6c ldr r2, [pc, #432] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001014: f443 3380 orr.w r3, r3, #65536 ; 0x10000
8001018: 6013 str r3, [r2, #0]
800101a: e00b b.n 8001034 <HAL_RCC_OscConfig+0xb0>
800101c: 4b69 ldr r3, [pc, #420] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
800101e: 681b ldr r3, [r3, #0]
8001020: 4a68 ldr r2, [pc, #416] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001022: f423 3380 bic.w r3, r3, #65536 ; 0x10000
8001026: 6013 str r3, [r2, #0]
8001028: 4b66 ldr r3, [pc, #408] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
800102a: 681b ldr r3, [r3, #0]
800102c: 4a65 ldr r2, [pc, #404] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
800102e: f423 2380 bic.w r3, r3, #262144 ; 0x40000
8001032: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
8001034: 687b ldr r3, [r7, #4]
8001036: 685b ldr r3, [r3, #4]
8001038: 2b00 cmp r3, #0
800103a: d013 beq.n 8001064 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick */
tickstart = HAL_GetTick();
800103c: f7ff fcfa bl 8000a34 <HAL_GetTick>
8001040: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001042: e008 b.n 8001056 <HAL_RCC_OscConfig+0xd2>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8001044: f7ff fcf6 bl 8000a34 <HAL_GetTick>
8001048: 4602 mov r2, r0
800104a: 693b ldr r3, [r7, #16]
800104c: 1ad3 subs r3, r2, r3
800104e: 2b64 cmp r3, #100 ; 0x64
8001050: d901 bls.n 8001056 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
8001052: 2303 movs r3, #3
8001054: e207 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001056: 4b5b ldr r3, [pc, #364] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001058: 681b ldr r3, [r3, #0]
800105a: f403 3300 and.w r3, r3, #131072 ; 0x20000
800105e: 2b00 cmp r3, #0
8001060: d0f0 beq.n 8001044 <HAL_RCC_OscConfig+0xc0>
8001062: e014 b.n 800108e <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
8001064: f7ff fce6 bl 8000a34 <HAL_GetTick>
8001068: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800106a: e008 b.n 800107e <HAL_RCC_OscConfig+0xfa>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
800106c: f7ff fce2 bl 8000a34 <HAL_GetTick>
8001070: 4602 mov r2, r0
8001072: 693b ldr r3, [r7, #16]
8001074: 1ad3 subs r3, r2, r3
8001076: 2b64 cmp r3, #100 ; 0x64
8001078: d901 bls.n 800107e <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
800107a: 2303 movs r3, #3
800107c: e1f3 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
800107e: 4b51 ldr r3, [pc, #324] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001080: 681b ldr r3, [r3, #0]
8001082: f403 3300 and.w r3, r3, #131072 ; 0x20000
8001086: 2b00 cmp r3, #0
8001088: d1f0 bne.n 800106c <HAL_RCC_OscConfig+0xe8>
800108a: e000 b.n 800108e <HAL_RCC_OscConfig+0x10a>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
800108c: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800108e: 687b ldr r3, [r7, #4]
8001090: 681b ldr r3, [r3, #0]
8001092: f003 0302 and.w r3, r3, #2
8001096: 2b00 cmp r3, #0
8001098: d063 beq.n 8001162 <HAL_RCC_OscConfig+0x1de>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
800109a: 4b4a ldr r3, [pc, #296] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
800109c: 689b ldr r3, [r3, #8]
800109e: f003 030c and.w r3, r3, #12
80010a2: 2b00 cmp r3, #0
80010a4: d00b beq.n 80010be <HAL_RCC_OscConfig+0x13a>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80010a6: 4b47 ldr r3, [pc, #284] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
80010a8: 689b ldr r3, [r3, #8]
80010aa: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
80010ae: 2b08 cmp r3, #8
80010b0: d11c bne.n 80010ec <HAL_RCC_OscConfig+0x168>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
80010b2: 4b44 ldr r3, [pc, #272] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
80010b4: 685b ldr r3, [r3, #4]
80010b6: f403 0380 and.w r3, r3, #4194304 ; 0x400000
80010ba: 2b00 cmp r3, #0
80010bc: d116 bne.n 80010ec <HAL_RCC_OscConfig+0x168>
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80010be: 4b41 ldr r3, [pc, #260] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
80010c0: 681b ldr r3, [r3, #0]
80010c2: f003 0302 and.w r3, r3, #2
80010c6: 2b00 cmp r3, #0
80010c8: d005 beq.n 80010d6 <HAL_RCC_OscConfig+0x152>
80010ca: 687b ldr r3, [r7, #4]
80010cc: 68db ldr r3, [r3, #12]
80010ce: 2b01 cmp r3, #1
80010d0: d001 beq.n 80010d6 <HAL_RCC_OscConfig+0x152>
{
return HAL_ERROR;
80010d2: 2301 movs r3, #1
80010d4: e1c7 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
80010d6: 4b3b ldr r3, [pc, #236] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
80010d8: 681b ldr r3, [r3, #0]
80010da: f023 02f8 bic.w r2, r3, #248 ; 0xf8
80010de: 687b ldr r3, [r7, #4]
80010e0: 691b ldr r3, [r3, #16]
80010e2: 00db lsls r3, r3, #3
80010e4: 4937 ldr r1, [pc, #220] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
80010e6: 4313 orrs r3, r2
80010e8: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
80010ea: e03a b.n 8001162 <HAL_RCC_OscConfig+0x1de>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
80010ec: 687b ldr r3, [r7, #4]
80010ee: 68db ldr r3, [r3, #12]
80010f0: 2b00 cmp r3, #0
80010f2: d020 beq.n 8001136 <HAL_RCC_OscConfig+0x1b2>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
80010f4: 4b34 ldr r3, [pc, #208] ; (80011c8 <HAL_RCC_OscConfig+0x244>)
80010f6: 2201 movs r2, #1
80010f8: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80010fa: f7ff fc9b bl 8000a34 <HAL_GetTick>
80010fe: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001100: e008 b.n 8001114 <HAL_RCC_OscConfig+0x190>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001102: f7ff fc97 bl 8000a34 <HAL_GetTick>
8001106: 4602 mov r2, r0
8001108: 693b ldr r3, [r7, #16]
800110a: 1ad3 subs r3, r2, r3
800110c: 2b02 cmp r3, #2
800110e: d901 bls.n 8001114 <HAL_RCC_OscConfig+0x190>
{
return HAL_TIMEOUT;
8001110: 2303 movs r3, #3
8001112: e1a8 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001114: 4b2b ldr r3, [pc, #172] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001116: 681b ldr r3, [r3, #0]
8001118: f003 0302 and.w r3, r3, #2
800111c: 2b00 cmp r3, #0
800111e: d0f0 beq.n 8001102 <HAL_RCC_OscConfig+0x17e>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8001120: 4b28 ldr r3, [pc, #160] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001122: 681b ldr r3, [r3, #0]
8001124: f023 02f8 bic.w r2, r3, #248 ; 0xf8
8001128: 687b ldr r3, [r7, #4]
800112a: 691b ldr r3, [r3, #16]
800112c: 00db lsls r3, r3, #3
800112e: 4925 ldr r1, [pc, #148] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001130: 4313 orrs r3, r2
8001132: 600b str r3, [r1, #0]
8001134: e015 b.n 8001162 <HAL_RCC_OscConfig+0x1de>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8001136: 4b24 ldr r3, [pc, #144] ; (80011c8 <HAL_RCC_OscConfig+0x244>)
8001138: 2200 movs r2, #0
800113a: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800113c: f7ff fc7a bl 8000a34 <HAL_GetTick>
8001140: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001142: e008 b.n 8001156 <HAL_RCC_OscConfig+0x1d2>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8001144: f7ff fc76 bl 8000a34 <HAL_GetTick>
8001148: 4602 mov r2, r0
800114a: 693b ldr r3, [r7, #16]
800114c: 1ad3 subs r3, r2, r3
800114e: 2b02 cmp r3, #2
8001150: d901 bls.n 8001156 <HAL_RCC_OscConfig+0x1d2>
{
return HAL_TIMEOUT;
8001152: 2303 movs r3, #3
8001154: e187 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8001156: 4b1b ldr r3, [pc, #108] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001158: 681b ldr r3, [r3, #0]
800115a: f003 0302 and.w r3, r3, #2
800115e: 2b00 cmp r3, #0
8001160: d1f0 bne.n 8001144 <HAL_RCC_OscConfig+0x1c0>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8001162: 687b ldr r3, [r7, #4]
8001164: 681b ldr r3, [r3, #0]
8001166: f003 0308 and.w r3, r3, #8
800116a: 2b00 cmp r3, #0
800116c: d036 beq.n 80011dc <HAL_RCC_OscConfig+0x258>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
800116e: 687b ldr r3, [r7, #4]
8001170: 695b ldr r3, [r3, #20]
8001172: 2b00 cmp r3, #0
8001174: d016 beq.n 80011a4 <HAL_RCC_OscConfig+0x220>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8001176: 4b15 ldr r3, [pc, #84] ; (80011cc <HAL_RCC_OscConfig+0x248>)
8001178: 2201 movs r2, #1
800117a: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800117c: f7ff fc5a bl 8000a34 <HAL_GetTick>
8001180: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001182: e008 b.n 8001196 <HAL_RCC_OscConfig+0x212>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8001184: f7ff fc56 bl 8000a34 <HAL_GetTick>
8001188: 4602 mov r2, r0
800118a: 693b ldr r3, [r7, #16]
800118c: 1ad3 subs r3, r2, r3
800118e: 2b02 cmp r3, #2
8001190: d901 bls.n 8001196 <HAL_RCC_OscConfig+0x212>
{
return HAL_TIMEOUT;
8001192: 2303 movs r3, #3
8001194: e167 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8001196: 4b0b ldr r3, [pc, #44] ; (80011c4 <HAL_RCC_OscConfig+0x240>)
8001198: 6f5b ldr r3, [r3, #116] ; 0x74
800119a: f003 0302 and.w r3, r3, #2
800119e: 2b00 cmp r3, #0
80011a0: d0f0 beq.n 8001184 <HAL_RCC_OscConfig+0x200>
80011a2: e01b b.n 80011dc <HAL_RCC_OscConfig+0x258>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
80011a4: 4b09 ldr r3, [pc, #36] ; (80011cc <HAL_RCC_OscConfig+0x248>)
80011a6: 2200 movs r2, #0
80011a8: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80011aa: f7ff fc43 bl 8000a34 <HAL_GetTick>
80011ae: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80011b0: e00e b.n 80011d0 <HAL_RCC_OscConfig+0x24c>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
80011b2: f7ff fc3f bl 8000a34 <HAL_GetTick>
80011b6: 4602 mov r2, r0
80011b8: 693b ldr r3, [r7, #16]
80011ba: 1ad3 subs r3, r2, r3
80011bc: 2b02 cmp r3, #2
80011be: d907 bls.n 80011d0 <HAL_RCC_OscConfig+0x24c>
{
return HAL_TIMEOUT;
80011c0: 2303 movs r3, #3
80011c2: e150 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
80011c4: 40023800 .word 0x40023800
80011c8: 42470000 .word 0x42470000
80011cc: 42470e80 .word 0x42470e80
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
80011d0: 4b88 ldr r3, [pc, #544] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
80011d2: 6f5b ldr r3, [r3, #116] ; 0x74
80011d4: f003 0302 and.w r3, r3, #2
80011d8: 2b00 cmp r3, #0
80011da: d1ea bne.n 80011b2 <HAL_RCC_OscConfig+0x22e>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
80011dc: 687b ldr r3, [r7, #4]
80011de: 681b ldr r3, [r3, #0]
80011e0: f003 0304 and.w r3, r3, #4
80011e4: 2b00 cmp r3, #0
80011e6: f000 8097 beq.w 8001318 <HAL_RCC_OscConfig+0x394>
{
FlagStatus pwrclkchanged = RESET;
80011ea: 2300 movs r3, #0
80011ec: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
80011ee: 4b81 ldr r3, [pc, #516] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
80011f0: 6c1b ldr r3, [r3, #64] ; 0x40
80011f2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
80011f6: 2b00 cmp r3, #0
80011f8: d10f bne.n 800121a <HAL_RCC_OscConfig+0x296>
{
__HAL_RCC_PWR_CLK_ENABLE();
80011fa: 2300 movs r3, #0
80011fc: 60bb str r3, [r7, #8]
80011fe: 4b7d ldr r3, [pc, #500] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001200: 6c1b ldr r3, [r3, #64] ; 0x40
8001202: 4a7c ldr r2, [pc, #496] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001204: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000
8001208: 6413 str r3, [r2, #64] ; 0x40
800120a: 4b7a ldr r3, [pc, #488] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
800120c: 6c1b ldr r3, [r3, #64] ; 0x40
800120e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000
8001212: 60bb str r3, [r7, #8]
8001214: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8001216: 2301 movs r3, #1
8001218: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800121a: 4b77 ldr r3, [pc, #476] ; (80013f8 <HAL_RCC_OscConfig+0x474>)
800121c: 681b ldr r3, [r3, #0]
800121e: f403 7380 and.w r3, r3, #256 ; 0x100
8001222: 2b00 cmp r3, #0
8001224: d118 bne.n 8001258 <HAL_RCC_OscConfig+0x2d4>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8001226: 4b74 ldr r3, [pc, #464] ; (80013f8 <HAL_RCC_OscConfig+0x474>)
8001228: 681b ldr r3, [r3, #0]
800122a: 4a73 ldr r2, [pc, #460] ; (80013f8 <HAL_RCC_OscConfig+0x474>)
800122c: f443 7380 orr.w r3, r3, #256 ; 0x100
8001230: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8001232: f7ff fbff bl 8000a34 <HAL_GetTick>
8001236: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8001238: e008 b.n 800124c <HAL_RCC_OscConfig+0x2c8>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
800123a: f7ff fbfb bl 8000a34 <HAL_GetTick>
800123e: 4602 mov r2, r0
8001240: 693b ldr r3, [r7, #16]
8001242: 1ad3 subs r3, r2, r3
8001244: 2b02 cmp r3, #2
8001246: d901 bls.n 800124c <HAL_RCC_OscConfig+0x2c8>
{
return HAL_TIMEOUT;
8001248: 2303 movs r3, #3
800124a: e10c b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
800124c: 4b6a ldr r3, [pc, #424] ; (80013f8 <HAL_RCC_OscConfig+0x474>)
800124e: 681b ldr r3, [r3, #0]
8001250: f403 7380 and.w r3, r3, #256 ; 0x100
8001254: 2b00 cmp r3, #0
8001256: d0f0 beq.n 800123a <HAL_RCC_OscConfig+0x2b6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8001258: 687b ldr r3, [r7, #4]
800125a: 689b ldr r3, [r3, #8]
800125c: 2b01 cmp r3, #1
800125e: d106 bne.n 800126e <HAL_RCC_OscConfig+0x2ea>
8001260: 4b64 ldr r3, [pc, #400] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001262: 6f1b ldr r3, [r3, #112] ; 0x70
8001264: 4a63 ldr r2, [pc, #396] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001266: f043 0301 orr.w r3, r3, #1
800126a: 6713 str r3, [r2, #112] ; 0x70
800126c: e01c b.n 80012a8 <HAL_RCC_OscConfig+0x324>
800126e: 687b ldr r3, [r7, #4]
8001270: 689b ldr r3, [r3, #8]
8001272: 2b05 cmp r3, #5
8001274: d10c bne.n 8001290 <HAL_RCC_OscConfig+0x30c>
8001276: 4b5f ldr r3, [pc, #380] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001278: 6f1b ldr r3, [r3, #112] ; 0x70
800127a: 4a5e ldr r2, [pc, #376] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
800127c: f043 0304 orr.w r3, r3, #4
8001280: 6713 str r3, [r2, #112] ; 0x70
8001282: 4b5c ldr r3, [pc, #368] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001284: 6f1b ldr r3, [r3, #112] ; 0x70
8001286: 4a5b ldr r2, [pc, #364] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001288: f043 0301 orr.w r3, r3, #1
800128c: 6713 str r3, [r2, #112] ; 0x70
800128e: e00b b.n 80012a8 <HAL_RCC_OscConfig+0x324>
8001290: 4b58 ldr r3, [pc, #352] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001292: 6f1b ldr r3, [r3, #112] ; 0x70
8001294: 4a57 ldr r2, [pc, #348] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001296: f023 0301 bic.w r3, r3, #1
800129a: 6713 str r3, [r2, #112] ; 0x70
800129c: 4b55 ldr r3, [pc, #340] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
800129e: 6f1b ldr r3, [r3, #112] ; 0x70
80012a0: 4a54 ldr r2, [pc, #336] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
80012a2: f023 0304 bic.w r3, r3, #4
80012a6: 6713 str r3, [r2, #112] ; 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
80012a8: 687b ldr r3, [r7, #4]
80012aa: 689b ldr r3, [r3, #8]
80012ac: 2b00 cmp r3, #0
80012ae: d015 beq.n 80012dc <HAL_RCC_OscConfig+0x358>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80012b0: f7ff fbc0 bl 8000a34 <HAL_GetTick>
80012b4: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80012b6: e00a b.n 80012ce <HAL_RCC_OscConfig+0x34a>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80012b8: f7ff fbbc bl 8000a34 <HAL_GetTick>
80012bc: 4602 mov r2, r0
80012be: 693b ldr r3, [r7, #16]
80012c0: 1ad3 subs r3, r2, r3
80012c2: f241 3288 movw r2, #5000 ; 0x1388
80012c6: 4293 cmp r3, r2
80012c8: d901 bls.n 80012ce <HAL_RCC_OscConfig+0x34a>
{
return HAL_TIMEOUT;
80012ca: 2303 movs r3, #3
80012cc: e0cb b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
80012ce: 4b49 ldr r3, [pc, #292] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
80012d0: 6f1b ldr r3, [r3, #112] ; 0x70
80012d2: f003 0302 and.w r3, r3, #2
80012d6: 2b00 cmp r3, #0
80012d8: d0ee beq.n 80012b8 <HAL_RCC_OscConfig+0x334>
80012da: e014 b.n 8001306 <HAL_RCC_OscConfig+0x382>
}
}
else
{
/* Get Start Tick */
tickstart = HAL_GetTick();
80012dc: f7ff fbaa bl 8000a34 <HAL_GetTick>
80012e0: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80012e2: e00a b.n 80012fa <HAL_RCC_OscConfig+0x376>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
80012e4: f7ff fba6 bl 8000a34 <HAL_GetTick>
80012e8: 4602 mov r2, r0
80012ea: 693b ldr r3, [r7, #16]
80012ec: 1ad3 subs r3, r2, r3
80012ee: f241 3288 movw r2, #5000 ; 0x1388
80012f2: 4293 cmp r3, r2
80012f4: d901 bls.n 80012fa <HAL_RCC_OscConfig+0x376>
{
return HAL_TIMEOUT;
80012f6: 2303 movs r3, #3
80012f8: e0b5 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
80012fa: 4b3e ldr r3, [pc, #248] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
80012fc: 6f1b ldr r3, [r3, #112] ; 0x70
80012fe: f003 0302 and.w r3, r3, #2
8001302: 2b00 cmp r3, #0
8001304: d1ee bne.n 80012e4 <HAL_RCC_OscConfig+0x360>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8001306: 7dfb ldrb r3, [r7, #23]
8001308: 2b01 cmp r3, #1
800130a: d105 bne.n 8001318 <HAL_RCC_OscConfig+0x394>
{
__HAL_RCC_PWR_CLK_DISABLE();
800130c: 4b39 ldr r3, [pc, #228] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
800130e: 6c1b ldr r3, [r3, #64] ; 0x40
8001310: 4a38 ldr r2, [pc, #224] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001312: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000
8001316: 6413 str r3, [r2, #64] ; 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
8001318: 687b ldr r3, [r7, #4]
800131a: 699b ldr r3, [r3, #24]
800131c: 2b00 cmp r3, #0
800131e: f000 80a1 beq.w 8001464 <HAL_RCC_OscConfig+0x4e0>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
8001322: 4b34 ldr r3, [pc, #208] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001324: 689b ldr r3, [r3, #8]
8001326: f003 030c and.w r3, r3, #12
800132a: 2b08 cmp r3, #8
800132c: d05c beq.n 80013e8 <HAL_RCC_OscConfig+0x464>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
800132e: 687b ldr r3, [r7, #4]
8001330: 699b ldr r3, [r3, #24]
8001332: 2b02 cmp r3, #2
8001334: d141 bne.n 80013ba <HAL_RCC_OscConfig+0x436>
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8001336: 4b31 ldr r3, [pc, #196] ; (80013fc <HAL_RCC_OscConfig+0x478>)
8001338: 2200 movs r2, #0
800133a: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
800133c: f7ff fb7a bl 8000a34 <HAL_GetTick>
8001340: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001342: e008 b.n 8001356 <HAL_RCC_OscConfig+0x3d2>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8001344: f7ff fb76 bl 8000a34 <HAL_GetTick>
8001348: 4602 mov r2, r0
800134a: 693b ldr r3, [r7, #16]
800134c: 1ad3 subs r3, r2, r3
800134e: 2b02 cmp r3, #2
8001350: d901 bls.n 8001356 <HAL_RCC_OscConfig+0x3d2>
{
return HAL_TIMEOUT;
8001352: 2303 movs r3, #3
8001354: e087 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8001356: 4b27 ldr r3, [pc, #156] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001358: 681b ldr r3, [r3, #0]
800135a: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800135e: 2b00 cmp r3, #0
8001360: d1f0 bne.n 8001344 <HAL_RCC_OscConfig+0x3c0>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
8001362: 687b ldr r3, [r7, #4]
8001364: 69da ldr r2, [r3, #28]
8001366: 687b ldr r3, [r7, #4]
8001368: 6a1b ldr r3, [r3, #32]
800136a: 431a orrs r2, r3
800136c: 687b ldr r3, [r7, #4]
800136e: 6a5b ldr r3, [r3, #36] ; 0x24
8001370: 019b lsls r3, r3, #6
8001372: 431a orrs r2, r3
8001374: 687b ldr r3, [r7, #4]
8001376: 6a9b ldr r3, [r3, #40] ; 0x28
8001378: 085b lsrs r3, r3, #1
800137a: 3b01 subs r3, #1
800137c: 041b lsls r3, r3, #16
800137e: 431a orrs r2, r3
8001380: 687b ldr r3, [r7, #4]
8001382: 6adb ldr r3, [r3, #44] ; 0x2c
8001384: 061b lsls r3, r3, #24
8001386: 491b ldr r1, [pc, #108] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
8001388: 4313 orrs r3, r2
800138a: 604b str r3, [r1, #4]
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
800138c: 4b1b ldr r3, [pc, #108] ; (80013fc <HAL_RCC_OscConfig+0x478>)
800138e: 2201 movs r2, #1
8001390: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001392: f7ff fb4f bl 8000a34 <HAL_GetTick>
8001396: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001398: e008 b.n 80013ac <HAL_RCC_OscConfig+0x428>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
800139a: f7ff fb4b bl 8000a34 <HAL_GetTick>
800139e: 4602 mov r2, r0
80013a0: 693b ldr r3, [r7, #16]
80013a2: 1ad3 subs r3, r2, r3
80013a4: 2b02 cmp r3, #2
80013a6: d901 bls.n 80013ac <HAL_RCC_OscConfig+0x428>
{
return HAL_TIMEOUT;
80013a8: 2303 movs r3, #3
80013aa: e05c b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80013ac: 4b11 ldr r3, [pc, #68] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
80013ae: 681b ldr r3, [r3, #0]
80013b0: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80013b4: 2b00 cmp r3, #0
80013b6: d0f0 beq.n 800139a <HAL_RCC_OscConfig+0x416>
80013b8: e054 b.n 8001464 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
80013ba: 4b10 ldr r3, [pc, #64] ; (80013fc <HAL_RCC_OscConfig+0x478>)
80013bc: 2200 movs r2, #0
80013be: 601a str r2, [r3, #0]
/* Get Start Tick */
tickstart = HAL_GetTick();
80013c0: f7ff fb38 bl 8000a34 <HAL_GetTick>
80013c4: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80013c6: e008 b.n 80013da <HAL_RCC_OscConfig+0x456>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80013c8: f7ff fb34 bl 8000a34 <HAL_GetTick>
80013cc: 4602 mov r2, r0
80013ce: 693b ldr r3, [r7, #16]
80013d0: 1ad3 subs r3, r2, r3
80013d2: 2b02 cmp r3, #2
80013d4: d901 bls.n 80013da <HAL_RCC_OscConfig+0x456>
{
return HAL_TIMEOUT;
80013d6: 2303 movs r3, #3
80013d8: e045 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
80013da: 4b06 ldr r3, [pc, #24] ; (80013f4 <HAL_RCC_OscConfig+0x470>)
80013dc: 681b ldr r3, [r3, #0]
80013de: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
80013e2: 2b00 cmp r3, #0
80013e4: d1f0 bne.n 80013c8 <HAL_RCC_OscConfig+0x444>
80013e6: e03d b.n 8001464 <HAL_RCC_OscConfig+0x4e0>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
80013e8: 687b ldr r3, [r7, #4]
80013ea: 699b ldr r3, [r3, #24]
80013ec: 2b01 cmp r3, #1
80013ee: d107 bne.n 8001400 <HAL_RCC_OscConfig+0x47c>
{
return HAL_ERROR;
80013f0: 2301 movs r3, #1
80013f2: e038 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
80013f4: 40023800 .word 0x40023800
80013f8: 40007000 .word 0x40007000
80013fc: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
8001400: 4b1b ldr r3, [pc, #108] ; (8001470 <HAL_RCC_OscConfig+0x4ec>)
8001402: 685b ldr r3, [r3, #4]
8001404: 60fb str r3, [r7, #12]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001406: 687b ldr r3, [r7, #4]
8001408: 699b ldr r3, [r3, #24]
800140a: 2b01 cmp r3, #1
800140c: d028 beq.n 8001460 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800140e: 68fb ldr r3, [r7, #12]
8001410: f403 0280 and.w r2, r3, #4194304 ; 0x400000
8001414: 687b ldr r3, [r7, #4]
8001416: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8001418: 429a cmp r2, r3
800141a: d121 bne.n 8001460 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
800141c: 68fb ldr r3, [r7, #12]
800141e: f003 023f and.w r2, r3, #63 ; 0x3f
8001422: 687b ldr r3, [r7, #4]
8001424: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8001426: 429a cmp r2, r3
8001428: d11a bne.n 8001460 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
800142a: 68fa ldr r2, [r7, #12]
800142c: f647 73c0 movw r3, #32704 ; 0x7fc0
8001430: 4013 ands r3, r2
8001432: 687a ldr r2, [r7, #4]
8001434: 6a52 ldr r2, [r2, #36] ; 0x24
8001436: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8001438: 4293 cmp r3, r2
800143a: d111 bne.n 8001460 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
800143c: 68fb ldr r3, [r7, #12]
800143e: f403 3240 and.w r2, r3, #196608 ; 0x30000
8001442: 687b ldr r3, [r7, #4]
8001444: 6a9b ldr r3, [r3, #40] ; 0x28
8001446: 085b lsrs r3, r3, #1
8001448: 3b01 subs r3, #1
800144a: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
800144c: 429a cmp r2, r3
800144e: d107 bne.n 8001460 <HAL_RCC_OscConfig+0x4dc>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
8001450: 68fb ldr r3, [r7, #12]
8001452: f003 6270 and.w r2, r3, #251658240 ; 0xf000000
8001456: 687b ldr r3, [r7, #4]
8001458: 6adb ldr r3, [r3, #44] ; 0x2c
800145a: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
800145c: 429a cmp r2, r3
800145e: d001 beq.n 8001464 <HAL_RCC_OscConfig+0x4e0>
#endif
{
return HAL_ERROR;
8001460: 2301 movs r3, #1
8001462: e000 b.n 8001466 <HAL_RCC_OscConfig+0x4e2>
}
}
}
}
return HAL_OK;
8001464: 2300 movs r3, #0
}
8001466: 4618 mov r0, r3
8001468: 3718 adds r7, #24
800146a: 46bd mov sp, r7
800146c: bd80 pop {r7, pc}
800146e: bf00 nop
8001470: 40023800 .word 0x40023800
08001474 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8001474: b580 push {r7, lr}
8001476: b084 sub sp, #16
8001478: af00 add r7, sp, #0
800147a: 6078 str r0, [r7, #4]
800147c: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
800147e: 687b ldr r3, [r7, #4]
8001480: 2b00 cmp r3, #0
8001482: d101 bne.n 8001488 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
8001484: 2301 movs r3, #1
8001486: e0cc b.n 8001622 <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
8001488: 4b68 ldr r3, [pc, #416] ; (800162c <HAL_RCC_ClockConfig+0x1b8>)
800148a: 681b ldr r3, [r3, #0]
800148c: f003 0307 and.w r3, r3, #7
8001490: 683a ldr r2, [r7, #0]
8001492: 429a cmp r2, r3
8001494: d90c bls.n 80014b0 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8001496: 4b65 ldr r3, [pc, #404] ; (800162c <HAL_RCC_ClockConfig+0x1b8>)
8001498: 683a ldr r2, [r7, #0]
800149a: b2d2 uxtb r2, r2
800149c: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
800149e: 4b63 ldr r3, [pc, #396] ; (800162c <HAL_RCC_ClockConfig+0x1b8>)
80014a0: 681b ldr r3, [r3, #0]
80014a2: f003 0307 and.w r3, r3, #7
80014a6: 683a ldr r2, [r7, #0]
80014a8: 429a cmp r2, r3
80014aa: d001 beq.n 80014b0 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
80014ac: 2301 movs r3, #1
80014ae: e0b8 b.n 8001622 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80014b0: 687b ldr r3, [r7, #4]
80014b2: 681b ldr r3, [r3, #0]
80014b4: f003 0302 and.w r3, r3, #2
80014b8: 2b00 cmp r3, #0
80014ba: d020 beq.n 80014fe <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80014bc: 687b ldr r3, [r7, #4]
80014be: 681b ldr r3, [r3, #0]
80014c0: f003 0304 and.w r3, r3, #4
80014c4: 2b00 cmp r3, #0
80014c6: d005 beq.n 80014d4 <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80014c8: 4b59 ldr r3, [pc, #356] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80014ca: 689b ldr r3, [r3, #8]
80014cc: 4a58 ldr r2, [pc, #352] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80014ce: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00
80014d2: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80014d4: 687b ldr r3, [r7, #4]
80014d6: 681b ldr r3, [r3, #0]
80014d8: f003 0308 and.w r3, r3, #8
80014dc: 2b00 cmp r3, #0
80014de: d005 beq.n 80014ec <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
80014e0: 4b53 ldr r3, [pc, #332] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80014e2: 689b ldr r3, [r3, #8]
80014e4: 4a52 ldr r2, [pc, #328] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80014e6: f443 4360 orr.w r3, r3, #57344 ; 0xe000
80014ea: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80014ec: 4b50 ldr r3, [pc, #320] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80014ee: 689b ldr r3, [r3, #8]
80014f0: f023 02f0 bic.w r2, r3, #240 ; 0xf0
80014f4: 687b ldr r3, [r7, #4]
80014f6: 689b ldr r3, [r3, #8]
80014f8: 494d ldr r1, [pc, #308] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80014fa: 4313 orrs r3, r2
80014fc: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
80014fe: 687b ldr r3, [r7, #4]
8001500: 681b ldr r3, [r3, #0]
8001502: f003 0301 and.w r3, r3, #1
8001506: 2b00 cmp r3, #0
8001508: d044 beq.n 8001594 <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
800150a: 687b ldr r3, [r7, #4]
800150c: 685b ldr r3, [r3, #4]
800150e: 2b01 cmp r3, #1
8001510: d107 bne.n 8001522 <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8001512: 4b47 ldr r3, [pc, #284] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
8001514: 681b ldr r3, [r3, #0]
8001516: f403 3300 and.w r3, r3, #131072 ; 0x20000
800151a: 2b00 cmp r3, #0
800151c: d119 bne.n 8001552 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800151e: 2301 movs r3, #1
8001520: e07f b.n 8001622 <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8001522: 687b ldr r3, [r7, #4]
8001524: 685b ldr r3, [r3, #4]
8001526: 2b02 cmp r3, #2
8001528: d003 beq.n 8001532 <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
800152a: 687b ldr r3, [r7, #4]
800152c: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
800152e: 2b03 cmp r3, #3
8001530: d107 bne.n 8001542 <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
8001532: 4b3f ldr r3, [pc, #252] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
8001534: 681b ldr r3, [r3, #0]
8001536: f003 7300 and.w r3, r3, #33554432 ; 0x2000000
800153a: 2b00 cmp r3, #0
800153c: d109 bne.n 8001552 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800153e: 2301 movs r3, #1
8001540: e06f b.n 8001622 <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8001542: 4b3b ldr r3, [pc, #236] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
8001544: 681b ldr r3, [r3, #0]
8001546: f003 0302 and.w r3, r3, #2
800154a: 2b00 cmp r3, #0
800154c: d101 bne.n 8001552 <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
800154e: 2301 movs r3, #1
8001550: e067 b.n 8001622 <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
8001552: 4b37 ldr r3, [pc, #220] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
8001554: 689b ldr r3, [r3, #8]
8001556: f023 0203 bic.w r2, r3, #3
800155a: 687b ldr r3, [r7, #4]
800155c: 685b ldr r3, [r3, #4]
800155e: 4934 ldr r1, [pc, #208] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
8001560: 4313 orrs r3, r2
8001562: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
8001564: f7ff fa66 bl 8000a34 <HAL_GetTick>
8001568: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
800156a: e00a b.n 8001582 <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
800156c: f7ff fa62 bl 8000a34 <HAL_GetTick>
8001570: 4602 mov r2, r0
8001572: 68fb ldr r3, [r7, #12]
8001574: 1ad3 subs r3, r2, r3
8001576: f241 3288 movw r2, #5000 ; 0x1388
800157a: 4293 cmp r3, r2
800157c: d901 bls.n 8001582 <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
800157e: 2303 movs r3, #3
8001580: e04f b.n 8001622 <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8001582: 4b2b ldr r3, [pc, #172] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
8001584: 689b ldr r3, [r3, #8]
8001586: f003 020c and.w r2, r3, #12
800158a: 687b ldr r3, [r7, #4]
800158c: 685b ldr r3, [r3, #4]
800158e: 009b lsls r3, r3, #2
8001590: 429a cmp r2, r3
8001592: d1eb bne.n 800156c <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
8001594: 4b25 ldr r3, [pc, #148] ; (800162c <HAL_RCC_ClockConfig+0x1b8>)
8001596: 681b ldr r3, [r3, #0]
8001598: f003 0307 and.w r3, r3, #7
800159c: 683a ldr r2, [r7, #0]
800159e: 429a cmp r2, r3
80015a0: d20c bcs.n 80015bc <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80015a2: 4b22 ldr r3, [pc, #136] ; (800162c <HAL_RCC_ClockConfig+0x1b8>)
80015a4: 683a ldr r2, [r7, #0]
80015a6: b2d2 uxtb r2, r2
80015a8: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80015aa: 4b20 ldr r3, [pc, #128] ; (800162c <HAL_RCC_ClockConfig+0x1b8>)
80015ac: 681b ldr r3, [r3, #0]
80015ae: f003 0307 and.w r3, r3, #7
80015b2: 683a ldr r2, [r7, #0]
80015b4: 429a cmp r2, r3
80015b6: d001 beq.n 80015bc <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
80015b8: 2301 movs r3, #1
80015ba: e032 b.n 8001622 <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80015bc: 687b ldr r3, [r7, #4]
80015be: 681b ldr r3, [r3, #0]
80015c0: f003 0304 and.w r3, r3, #4
80015c4: 2b00 cmp r3, #0
80015c6: d008 beq.n 80015da <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80015c8: 4b19 ldr r3, [pc, #100] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80015ca: 689b ldr r3, [r3, #8]
80015cc: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00
80015d0: 687b ldr r3, [r7, #4]
80015d2: 68db ldr r3, [r3, #12]
80015d4: 4916 ldr r1, [pc, #88] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80015d6: 4313 orrs r3, r2
80015d8: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80015da: 687b ldr r3, [r7, #4]
80015dc: 681b ldr r3, [r3, #0]
80015de: f003 0308 and.w r3, r3, #8
80015e2: 2b00 cmp r3, #0
80015e4: d009 beq.n 80015fa <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
80015e6: 4b12 ldr r3, [pc, #72] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80015e8: 689b ldr r3, [r3, #8]
80015ea: f423 4260 bic.w r2, r3, #57344 ; 0xe000
80015ee: 687b ldr r3, [r7, #4]
80015f0: 691b ldr r3, [r3, #16]
80015f2: 00db lsls r3, r3, #3
80015f4: 490e ldr r1, [pc, #56] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
80015f6: 4313 orrs r3, r2
80015f8: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
80015fa: f000 f821 bl 8001640 <HAL_RCC_GetSysClockFreq>
80015fe: 4602 mov r2, r0
8001600: 4b0b ldr r3, [pc, #44] ; (8001630 <HAL_RCC_ClockConfig+0x1bc>)
8001602: 689b ldr r3, [r3, #8]
8001604: 091b lsrs r3, r3, #4
8001606: f003 030f and.w r3, r3, #15
800160a: 490a ldr r1, [pc, #40] ; (8001634 <HAL_RCC_ClockConfig+0x1c0>)
800160c: 5ccb ldrb r3, [r1, r3]
800160e: fa22 f303 lsr.w r3, r2, r3
8001612: 4a09 ldr r2, [pc, #36] ; (8001638 <HAL_RCC_ClockConfig+0x1c4>)
8001614: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
8001616: 4b09 ldr r3, [pc, #36] ; (800163c <HAL_RCC_ClockConfig+0x1c8>)
8001618: 681b ldr r3, [r3, #0]
800161a: 4618 mov r0, r3
800161c: f7ff f9c6 bl 80009ac <HAL_InitTick>
return HAL_OK;
8001620: 2300 movs r3, #0
}
8001622: 4618 mov r0, r3
8001624: 3710 adds r7, #16
8001626: 46bd mov sp, r7
8001628: bd80 pop {r7, pc}
800162a: bf00 nop
800162c: 40023c00 .word 0x40023c00
8001630: 40023800 .word 0x40023800
8001634: 080021ec .word 0x080021ec
8001638: 20000000 .word 0x20000000
800163c: 20000004 .word 0x20000004
08001640 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
8001640: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001644: b094 sub sp, #80 ; 0x50
8001646: af00 add r7, sp, #0
uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
8001648: 2300 movs r3, #0
800164a: 647b str r3, [r7, #68] ; 0x44
800164c: 2300 movs r3, #0
800164e: 64fb str r3, [r7, #76] ; 0x4c
8001650: 2300 movs r3, #0
8001652: 643b str r3, [r7, #64] ; 0x40
uint32_t sysclockfreq = 0U;
8001654: 2300 movs r3, #0
8001656: 64bb str r3, [r7, #72] ; 0x48
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
8001658: 4b79 ldr r3, [pc, #484] ; (8001840 <HAL_RCC_GetSysClockFreq+0x200>)
800165a: 689b ldr r3, [r3, #8]
800165c: f003 030c and.w r3, r3, #12
8001660: 2b08 cmp r3, #8
8001662: d00d beq.n 8001680 <HAL_RCC_GetSysClockFreq+0x40>
8001664: 2b08 cmp r3, #8
8001666: f200 80e1 bhi.w 800182c <HAL_RCC_GetSysClockFreq+0x1ec>
800166a: 2b00 cmp r3, #0
800166c: d002 beq.n 8001674 <HAL_RCC_GetSysClockFreq+0x34>
800166e: 2b04 cmp r3, #4
8001670: d003 beq.n 800167a <HAL_RCC_GetSysClockFreq+0x3a>
8001672: e0db b.n 800182c <HAL_RCC_GetSysClockFreq+0x1ec>
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
8001674: 4b73 ldr r3, [pc, #460] ; (8001844 <HAL_RCC_GetSysClockFreq+0x204>)
8001676: 64bb str r3, [r7, #72] ; 0x48
break;
8001678: e0db b.n 8001832 <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
800167a: 4b73 ldr r3, [pc, #460] ; (8001848 <HAL_RCC_GetSysClockFreq+0x208>)
800167c: 64bb str r3, [r7, #72] ; 0x48
break;
800167e: e0d8 b.n 8001832 <HAL_RCC_GetSysClockFreq+0x1f2>
}
case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8001680: 4b6f ldr r3, [pc, #444] ; (8001840 <HAL_RCC_GetSysClockFreq+0x200>)
8001682: 685b ldr r3, [r3, #4]
8001684: f003 033f and.w r3, r3, #63 ; 0x3f
8001688: 647b str r3, [r7, #68] ; 0x44
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
800168a: 4b6d ldr r3, [pc, #436] ; (8001840 <HAL_RCC_GetSysClockFreq+0x200>)
800168c: 685b ldr r3, [r3, #4]
800168e: f403 0380 and.w r3, r3, #4194304 ; 0x400000
8001692: 2b00 cmp r3, #0
8001694: d063 beq.n 800175e <HAL_RCC_GetSysClockFreq+0x11e>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8001696: 4b6a ldr r3, [pc, #424] ; (8001840 <HAL_RCC_GetSysClockFreq+0x200>)
8001698: 685b ldr r3, [r3, #4]
800169a: 099b lsrs r3, r3, #6
800169c: 2200 movs r2, #0
800169e: 63bb str r3, [r7, #56] ; 0x38
80016a0: 63fa str r2, [r7, #60] ; 0x3c
80016a2: 6bbb ldr r3, [r7, #56] ; 0x38
80016a4: f3c3 0308 ubfx r3, r3, #0, #9
80016a8: 633b str r3, [r7, #48] ; 0x30
80016aa: 2300 movs r3, #0
80016ac: 637b str r3, [r7, #52] ; 0x34
80016ae: e9d7 450c ldrd r4, r5, [r7, #48] ; 0x30
80016b2: 4622 mov r2, r4
80016b4: 462b mov r3, r5
80016b6: f04f 0000 mov.w r0, #0
80016ba: f04f 0100 mov.w r1, #0
80016be: 0159 lsls r1, r3, #5
80016c0: ea41 61d2 orr.w r1, r1, r2, lsr #27
80016c4: 0150 lsls r0, r2, #5
80016c6: 4602 mov r2, r0
80016c8: 460b mov r3, r1
80016ca: 4621 mov r1, r4
80016cc: 1a51 subs r1, r2, r1
80016ce: 6139 str r1, [r7, #16]
80016d0: 4629 mov r1, r5
80016d2: eb63 0301 sbc.w r3, r3, r1
80016d6: 617b str r3, [r7, #20]
80016d8: f04f 0200 mov.w r2, #0
80016dc: f04f 0300 mov.w r3, #0
80016e0: e9d7 ab04 ldrd sl, fp, [r7, #16]
80016e4: 4659 mov r1, fp
80016e6: 018b lsls r3, r1, #6
80016e8: 4651 mov r1, sl
80016ea: ea43 6391 orr.w r3, r3, r1, lsr #26
80016ee: 4651 mov r1, sl
80016f0: 018a lsls r2, r1, #6
80016f2: 4651 mov r1, sl
80016f4: ebb2 0801 subs.w r8, r2, r1
80016f8: 4659 mov r1, fp
80016fa: eb63 0901 sbc.w r9, r3, r1
80016fe: f04f 0200 mov.w r2, #0
8001702: f04f 0300 mov.w r3, #0
8001706: ea4f 03c9 mov.w r3, r9, lsl #3
800170a: ea43 7358 orr.w r3, r3, r8, lsr #29
800170e: ea4f 02c8 mov.w r2, r8, lsl #3
8001712: 4690 mov r8, r2
8001714: 4699 mov r9, r3
8001716: 4623 mov r3, r4
8001718: eb18 0303 adds.w r3, r8, r3
800171c: 60bb str r3, [r7, #8]
800171e: 462b mov r3, r5
8001720: eb49 0303 adc.w r3, r9, r3
8001724: 60fb str r3, [r7, #12]
8001726: f04f 0200 mov.w r2, #0
800172a: f04f 0300 mov.w r3, #0
800172e: e9d7 4502 ldrd r4, r5, [r7, #8]
8001732: 4629 mov r1, r5
8001734: 024b lsls r3, r1, #9
8001736: 4621 mov r1, r4
8001738: ea43 53d1 orr.w r3, r3, r1, lsr #23
800173c: 4621 mov r1, r4
800173e: 024a lsls r2, r1, #9
8001740: 4610 mov r0, r2
8001742: 4619 mov r1, r3
8001744: 6c7b ldr r3, [r7, #68] ; 0x44
8001746: 2200 movs r2, #0
8001748: 62bb str r3, [r7, #40] ; 0x28
800174a: 62fa str r2, [r7, #44] ; 0x2c
800174c: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
8001750: f7fe fd42 bl 80001d8 <__aeabi_uldivmod>
8001754: 4602 mov r2, r0
8001756: 460b mov r3, r1
8001758: 4613 mov r3, r2
800175a: 64fb str r3, [r7, #76] ; 0x4c
800175c: e058 b.n 8001810 <HAL_RCC_GetSysClockFreq+0x1d0>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
800175e: 4b38 ldr r3, [pc, #224] ; (8001840 <HAL_RCC_GetSysClockFreq+0x200>)
8001760: 685b ldr r3, [r3, #4]
8001762: 099b lsrs r3, r3, #6
8001764: 2200 movs r2, #0
8001766: 4618 mov r0, r3
8001768: 4611 mov r1, r2
800176a: f3c0 0308 ubfx r3, r0, #0, #9
800176e: 623b str r3, [r7, #32]
8001770: 2300 movs r3, #0
8001772: 627b str r3, [r7, #36] ; 0x24
8001774: e9d7 8908 ldrd r8, r9, [r7, #32]
8001778: 4642 mov r2, r8
800177a: 464b mov r3, r9
800177c: f04f 0000 mov.w r0, #0
8001780: f04f 0100 mov.w r1, #0
8001784: 0159 lsls r1, r3, #5
8001786: ea41 61d2 orr.w r1, r1, r2, lsr #27
800178a: 0150 lsls r0, r2, #5
800178c: 4602 mov r2, r0
800178e: 460b mov r3, r1
8001790: 4641 mov r1, r8
8001792: ebb2 0a01 subs.w sl, r2, r1
8001796: 4649 mov r1, r9
8001798: eb63 0b01 sbc.w fp, r3, r1
800179c: f04f 0200 mov.w r2, #0
80017a0: f04f 0300 mov.w r3, #0
80017a4: ea4f 138b mov.w r3, fp, lsl #6
80017a8: ea43 639a orr.w r3, r3, sl, lsr #26
80017ac: ea4f 128a mov.w r2, sl, lsl #6
80017b0: ebb2 040a subs.w r4, r2, sl
80017b4: eb63 050b sbc.w r5, r3, fp
80017b8: f04f 0200 mov.w r2, #0
80017bc: f04f 0300 mov.w r3, #0
80017c0: 00eb lsls r3, r5, #3
80017c2: ea43 7354 orr.w r3, r3, r4, lsr #29
80017c6: 00e2 lsls r2, r4, #3
80017c8: 4614 mov r4, r2
80017ca: 461d mov r5, r3
80017cc: 4643 mov r3, r8
80017ce: 18e3 adds r3, r4, r3
80017d0: 603b str r3, [r7, #0]
80017d2: 464b mov r3, r9
80017d4: eb45 0303 adc.w r3, r5, r3
80017d8: 607b str r3, [r7, #4]
80017da: f04f 0200 mov.w r2, #0
80017de: f04f 0300 mov.w r3, #0
80017e2: e9d7 4500 ldrd r4, r5, [r7]
80017e6: 4629 mov r1, r5
80017e8: 028b lsls r3, r1, #10
80017ea: 4621 mov r1, r4
80017ec: ea43 5391 orr.w r3, r3, r1, lsr #22
80017f0: 4621 mov r1, r4
80017f2: 028a lsls r2, r1, #10
80017f4: 4610 mov r0, r2
80017f6: 4619 mov r1, r3
80017f8: 6c7b ldr r3, [r7, #68] ; 0x44
80017fa: 2200 movs r2, #0
80017fc: 61bb str r3, [r7, #24]
80017fe: 61fa str r2, [r7, #28]
8001800: e9d7 2306 ldrd r2, r3, [r7, #24]
8001804: f7fe fce8 bl 80001d8 <__aeabi_uldivmod>
8001808: 4602 mov r2, r0
800180a: 460b mov r3, r1
800180c: 4613 mov r3, r2
800180e: 64fb str r3, [r7, #76] ; 0x4c
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
8001810: 4b0b ldr r3, [pc, #44] ; (8001840 <HAL_RCC_GetSysClockFreq+0x200>)
8001812: 685b ldr r3, [r3, #4]
8001814: 0c1b lsrs r3, r3, #16
8001816: f003 0303 and.w r3, r3, #3
800181a: 3301 adds r3, #1
800181c: 005b lsls r3, r3, #1
800181e: 643b str r3, [r7, #64] ; 0x40
sysclockfreq = pllvco/pllp;
8001820: 6cfa ldr r2, [r7, #76] ; 0x4c
8001822: 6c3b ldr r3, [r7, #64] ; 0x40
8001824: fbb2 f3f3 udiv r3, r2, r3
8001828: 64bb str r3, [r7, #72] ; 0x48
break;
800182a: e002 b.n 8001832 <HAL_RCC_GetSysClockFreq+0x1f2>
}
default:
{
sysclockfreq = HSI_VALUE;
800182c: 4b05 ldr r3, [pc, #20] ; (8001844 <HAL_RCC_GetSysClockFreq+0x204>)
800182e: 64bb str r3, [r7, #72] ; 0x48
break;
8001830: bf00 nop
}
}
return sysclockfreq;
8001832: 6cbb ldr r3, [r7, #72] ; 0x48
}
8001834: 4618 mov r0, r3
8001836: 3750 adds r7, #80 ; 0x50
8001838: 46bd mov sp, r7
800183a: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
800183e: bf00 nop
8001840: 40023800 .word 0x40023800
8001844: 00f42400 .word 0x00f42400
8001848: 007a1200 .word 0x007a1200
0800184c <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
800184c: b480 push {r7}
800184e: af00 add r7, sp, #0
return SystemCoreClock;
8001850: 4b03 ldr r3, [pc, #12] ; (8001860 <HAL_RCC_GetHCLKFreq+0x14>)
8001852: 681b ldr r3, [r3, #0]
}
8001854: 4618 mov r0, r3
8001856: 46bd mov sp, r7
8001858: f85d 7b04 ldr.w r7, [sp], #4
800185c: 4770 bx lr
800185e: bf00 nop
8001860: 20000000 .word 0x20000000
08001864 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8001864: b580 push {r7, lr}
8001866: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
8001868: f7ff fff0 bl 800184c <HAL_RCC_GetHCLKFreq>
800186c: 4602 mov r2, r0
800186e: 4b05 ldr r3, [pc, #20] ; (8001884 <HAL_RCC_GetPCLK1Freq+0x20>)
8001870: 689b ldr r3, [r3, #8]
8001872: 0a9b lsrs r3, r3, #10
8001874: f003 0307 and.w r3, r3, #7
8001878: 4903 ldr r1, [pc, #12] ; (8001888 <HAL_RCC_GetPCLK1Freq+0x24>)
800187a: 5ccb ldrb r3, [r1, r3]
800187c: fa22 f303 lsr.w r3, r2, r3
}
8001880: 4618 mov r0, r3
8001882: bd80 pop {r7, pc}
8001884: 40023800 .word 0x40023800
8001888: 080021fc .word 0x080021fc
0800188c <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
800188c: b580 push {r7, lr}
800188e: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
8001890: f7ff ffdc bl 800184c <HAL_RCC_GetHCLKFreq>
8001894: 4602 mov r2, r0
8001896: 4b05 ldr r3, [pc, #20] ; (80018ac <HAL_RCC_GetPCLK2Freq+0x20>)
8001898: 689b ldr r3, [r3, #8]
800189a: 0b5b lsrs r3, r3, #13
800189c: f003 0307 and.w r3, r3, #7
80018a0: 4903 ldr r1, [pc, #12] ; (80018b0 <HAL_RCC_GetPCLK2Freq+0x24>)
80018a2: 5ccb ldrb r3, [r1, r3]
80018a4: fa22 f303 lsr.w r3, r2, r3
}
80018a8: 4618 mov r0, r3
80018aa: bd80 pop {r7, pc}
80018ac: 40023800 .word 0x40023800
80018b0: 080021fc .word 0x080021fc
080018b4 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
80018b4: b580 push {r7, lr}
80018b6: b082 sub sp, #8
80018b8: af00 add r7, sp, #0
80018ba: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
80018bc: 687b ldr r3, [r7, #4]
80018be: 2b00 cmp r3, #0
80018c0: d101 bne.n 80018c6 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
80018c2: 2301 movs r3, #1
80018c4: e03f b.n 8001946 <HAL_UART_Init+0x92>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
80018c6: 687b ldr r3, [r7, #4]
80018c8: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
80018cc: b2db uxtb r3, r3
80018ce: 2b00 cmp r3, #0
80018d0: d106 bne.n 80018e0 <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
80018d2: 687b ldr r3, [r7, #4]
80018d4: 2200 movs r2, #0
80018d6: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
80018da: 6878 ldr r0, [r7, #4]
80018dc: f7fe ff96 bl 800080c <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
80018e0: 687b ldr r3, [r7, #4]
80018e2: 2224 movs r2, #36 ; 0x24
80018e4: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
80018e8: 687b ldr r3, [r7, #4]
80018ea: 681b ldr r3, [r3, #0]
80018ec: 68da ldr r2, [r3, #12]
80018ee: 687b ldr r3, [r7, #4]
80018f0: 681b ldr r3, [r3, #0]
80018f2: f422 5200 bic.w r2, r2, #8192 ; 0x2000
80018f6: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
80018f8: 6878 ldr r0, [r7, #4]
80018fa: f000 f9cb bl 8001c94 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80018fe: 687b ldr r3, [r7, #4]
8001900: 681b ldr r3, [r3, #0]
8001902: 691a ldr r2, [r3, #16]
8001904: 687b ldr r3, [r7, #4]
8001906: 681b ldr r3, [r3, #0]
8001908: f422 4290 bic.w r2, r2, #18432 ; 0x4800
800190c: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800190e: 687b ldr r3, [r7, #4]
8001910: 681b ldr r3, [r3, #0]
8001912: 695a ldr r2, [r3, #20]
8001914: 687b ldr r3, [r7, #4]
8001916: 681b ldr r3, [r3, #0]
8001918: f022 022a bic.w r2, r2, #42 ; 0x2a
800191c: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
800191e: 687b ldr r3, [r7, #4]
8001920: 681b ldr r3, [r3, #0]
8001922: 68da ldr r2, [r3, #12]
8001924: 687b ldr r3, [r7, #4]
8001926: 681b ldr r3, [r3, #0]
8001928: f442 5200 orr.w r2, r2, #8192 ; 0x2000
800192c: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800192e: 687b ldr r3, [r7, #4]
8001930: 2200 movs r2, #0
8001932: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_READY;
8001934: 687b ldr r3, [r7, #4]
8001936: 2220 movs r2, #32
8001938: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
800193c: 687b ldr r3, [r7, #4]
800193e: 2220 movs r2, #32
8001940: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8001944: 2300 movs r3, #0
}
8001946: 4618 mov r0, r3
8001948: 3708 adds r7, #8
800194a: 46bd mov sp, r7
800194c: bd80 pop {r7, pc}
0800194e <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
800194e: b580 push {r7, lr}
8001950: b08a sub sp, #40 ; 0x28
8001952: af02 add r7, sp, #8
8001954: 60f8 str r0, [r7, #12]
8001956: 60b9 str r1, [r7, #8]
8001958: 603b str r3, [r7, #0]
800195a: 4613 mov r3, r2
800195c: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart = 0U;
800195e: 2300 movs r3, #0
8001960: 617b str r3, [r7, #20]
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8001962: 68fb ldr r3, [r7, #12]
8001964: f893 303d ldrb.w r3, [r3, #61] ; 0x3d
8001968: b2db uxtb r3, r3
800196a: 2b20 cmp r3, #32
800196c: d17c bne.n 8001a68 <HAL_UART_Transmit+0x11a>
{
if ((pData == NULL) || (Size == 0U))
800196e: 68bb ldr r3, [r7, #8]
8001970: 2b00 cmp r3, #0
8001972: d002 beq.n 800197a <HAL_UART_Transmit+0x2c>
8001974: 88fb ldrh r3, [r7, #6]
8001976: 2b00 cmp r3, #0
8001978: d101 bne.n 800197e <HAL_UART_Transmit+0x30>
{
return HAL_ERROR;
800197a: 2301 movs r3, #1
800197c: e075 b.n 8001a6a <HAL_UART_Transmit+0x11c>
}
/* Process Locked */
__HAL_LOCK(huart);
800197e: 68fb ldr r3, [r7, #12]
8001980: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8001984: 2b01 cmp r3, #1
8001986: d101 bne.n 800198c <HAL_UART_Transmit+0x3e>
8001988: 2302 movs r3, #2
800198a: e06e b.n 8001a6a <HAL_UART_Transmit+0x11c>
800198c: 68fb ldr r3, [r7, #12]
800198e: 2201 movs r2, #1
8001990: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8001994: 68fb ldr r3, [r7, #12]
8001996: 2200 movs r2, #0
8001998: 641a str r2, [r3, #64] ; 0x40
huart->gState = HAL_UART_STATE_BUSY_TX;
800199a: 68fb ldr r3, [r7, #12]
800199c: 2221 movs r2, #33 ; 0x21
800199e: f883 203d strb.w r2, [r3, #61] ; 0x3d
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
80019a2: f7ff f847 bl 8000a34 <HAL_GetTick>
80019a6: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
80019a8: 68fb ldr r3, [r7, #12]
80019aa: 88fa ldrh r2, [r7, #6]
80019ac: 849a strh r2, [r3, #36] ; 0x24
huart->TxXferCount = Size;
80019ae: 68fb ldr r3, [r7, #12]
80019b0: 88fa ldrh r2, [r7, #6]
80019b2: 84da strh r2, [r3, #38] ; 0x26
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
80019b4: 68fb ldr r3, [r7, #12]
80019b6: 689b ldr r3, [r3, #8]
80019b8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
80019bc: d108 bne.n 80019d0 <HAL_UART_Transmit+0x82>
80019be: 68fb ldr r3, [r7, #12]
80019c0: 691b ldr r3, [r3, #16]
80019c2: 2b00 cmp r3, #0
80019c4: d104 bne.n 80019d0 <HAL_UART_Transmit+0x82>
{
pdata8bits = NULL;
80019c6: 2300 movs r3, #0
80019c8: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
80019ca: 68bb ldr r3, [r7, #8]
80019cc: 61bb str r3, [r7, #24]
80019ce: e003 b.n 80019d8 <HAL_UART_Transmit+0x8a>
}
else
{
pdata8bits = pData;
80019d0: 68bb ldr r3, [r7, #8]
80019d2: 61fb str r3, [r7, #28]
pdata16bits = NULL;
80019d4: 2300 movs r3, #0
80019d6: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
80019d8: 68fb ldr r3, [r7, #12]
80019da: 2200 movs r2, #0
80019dc: f883 203c strb.w r2, [r3, #60] ; 0x3c
while (huart->TxXferCount > 0U)
80019e0: e02a b.n 8001a38 <HAL_UART_Transmit+0xea>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
80019e2: 683b ldr r3, [r7, #0]
80019e4: 9300 str r3, [sp, #0]
80019e6: 697b ldr r3, [r7, #20]
80019e8: 2200 movs r2, #0
80019ea: 2180 movs r1, #128 ; 0x80
80019ec: 68f8 ldr r0, [r7, #12]
80019ee: f000 f8e2 bl 8001bb6 <UART_WaitOnFlagUntilTimeout>
80019f2: 4603 mov r3, r0
80019f4: 2b00 cmp r3, #0
80019f6: d001 beq.n 80019fc <HAL_UART_Transmit+0xae>
{
return HAL_TIMEOUT;
80019f8: 2303 movs r3, #3
80019fa: e036 b.n 8001a6a <HAL_UART_Transmit+0x11c>
}
if (pdata8bits == NULL)
80019fc: 69fb ldr r3, [r7, #28]
80019fe: 2b00 cmp r3, #0
8001a00: d10b bne.n 8001a1a <HAL_UART_Transmit+0xcc>
{
huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
8001a02: 69bb ldr r3, [r7, #24]
8001a04: 881b ldrh r3, [r3, #0]
8001a06: 461a mov r2, r3
8001a08: 68fb ldr r3, [r7, #12]
8001a0a: 681b ldr r3, [r3, #0]
8001a0c: f3c2 0208 ubfx r2, r2, #0, #9
8001a10: 605a str r2, [r3, #4]
pdata16bits++;
8001a12: 69bb ldr r3, [r7, #24]
8001a14: 3302 adds r3, #2
8001a16: 61bb str r3, [r7, #24]
8001a18: e007 b.n 8001a2a <HAL_UART_Transmit+0xdc>
}
else
{
huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
8001a1a: 69fb ldr r3, [r7, #28]
8001a1c: 781a ldrb r2, [r3, #0]
8001a1e: 68fb ldr r3, [r7, #12]
8001a20: 681b ldr r3, [r3, #0]
8001a22: 605a str r2, [r3, #4]
pdata8bits++;
8001a24: 69fb ldr r3, [r7, #28]
8001a26: 3301 adds r3, #1
8001a28: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8001a2a: 68fb ldr r3, [r7, #12]
8001a2c: 8cdb ldrh r3, [r3, #38] ; 0x26
8001a2e: b29b uxth r3, r3
8001a30: 3b01 subs r3, #1
8001a32: b29a uxth r2, r3
8001a34: 68fb ldr r3, [r7, #12]
8001a36: 84da strh r2, [r3, #38] ; 0x26
while (huart->TxXferCount > 0U)
8001a38: 68fb ldr r3, [r7, #12]
8001a3a: 8cdb ldrh r3, [r3, #38] ; 0x26
8001a3c: b29b uxth r3, r3
8001a3e: 2b00 cmp r3, #0
8001a40: d1cf bne.n 80019e2 <HAL_UART_Transmit+0x94>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8001a42: 683b ldr r3, [r7, #0]
8001a44: 9300 str r3, [sp, #0]
8001a46: 697b ldr r3, [r7, #20]
8001a48: 2200 movs r2, #0
8001a4a: 2140 movs r1, #64 ; 0x40
8001a4c: 68f8 ldr r0, [r7, #12]
8001a4e: f000 f8b2 bl 8001bb6 <UART_WaitOnFlagUntilTimeout>
8001a52: 4603 mov r3, r0
8001a54: 2b00 cmp r3, #0
8001a56: d001 beq.n 8001a5c <HAL_UART_Transmit+0x10e>
{
return HAL_TIMEOUT;
8001a58: 2303 movs r3, #3
8001a5a: e006 b.n 8001a6a <HAL_UART_Transmit+0x11c>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8001a5c: 68fb ldr r3, [r7, #12]
8001a5e: 2220 movs r2, #32
8001a60: f883 203d strb.w r2, [r3, #61] ; 0x3d
return HAL_OK;
8001a64: 2300 movs r3, #0
8001a66: e000 b.n 8001a6a <HAL_UART_Transmit+0x11c>
}
else
{
return HAL_BUSY;
8001a68: 2302 movs r3, #2
}
}
8001a6a: 4618 mov r0, r3
8001a6c: 3720 adds r7, #32
8001a6e: 46bd mov sp, r7
8001a70: bd80 pop {r7, pc}
08001a72 <HAL_UART_Receive>:
* @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
8001a72: b580 push {r7, lr}
8001a74: b08a sub sp, #40 ; 0x28
8001a76: af02 add r7, sp, #8
8001a78: 60f8 str r0, [r7, #12]
8001a7a: 60b9 str r1, [r7, #8]
8001a7c: 603b str r3, [r7, #0]
8001a7e: 4613 mov r3, r2
8001a80: 80fb strh r3, [r7, #6]
uint8_t *pdata8bits;
uint16_t *pdata16bits;
uint32_t tickstart = 0U;
8001a82: 2300 movs r3, #0
8001a84: 617b str r3, [r7, #20]
/* Check that a Rx process is not already ongoing */
if (huart->RxState == HAL_UART_STATE_READY)
8001a86: 68fb ldr r3, [r7, #12]
8001a88: f893 303e ldrb.w r3, [r3, #62] ; 0x3e
8001a8c: b2db uxtb r3, r3
8001a8e: 2b20 cmp r3, #32
8001a90: f040 808c bne.w 8001bac <HAL_UART_Receive+0x13a>
{
if ((pData == NULL) || (Size == 0U))
8001a94: 68bb ldr r3, [r7, #8]
8001a96: 2b00 cmp r3, #0
8001a98: d002 beq.n 8001aa0 <HAL_UART_Receive+0x2e>
8001a9a: 88fb ldrh r3, [r7, #6]
8001a9c: 2b00 cmp r3, #0
8001a9e: d101 bne.n 8001aa4 <HAL_UART_Receive+0x32>
{
return HAL_ERROR;
8001aa0: 2301 movs r3, #1
8001aa2: e084 b.n 8001bae <HAL_UART_Receive+0x13c>
}
/* Process Locked */
__HAL_LOCK(huart);
8001aa4: 68fb ldr r3, [r7, #12]
8001aa6: f893 303c ldrb.w r3, [r3, #60] ; 0x3c
8001aaa: 2b01 cmp r3, #1
8001aac: d101 bne.n 8001ab2 <HAL_UART_Receive+0x40>
8001aae: 2302 movs r3, #2
8001ab0: e07d b.n 8001bae <HAL_UART_Receive+0x13c>
8001ab2: 68fb ldr r3, [r7, #12]
8001ab4: 2201 movs r2, #1
8001ab6: f883 203c strb.w r2, [r3, #60] ; 0x3c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8001aba: 68fb ldr r3, [r7, #12]
8001abc: 2200 movs r2, #0
8001abe: 641a str r2, [r3, #64] ; 0x40
huart->RxState = HAL_UART_STATE_BUSY_RX;
8001ac0: 68fb ldr r3, [r7, #12]
8001ac2: 2222 movs r2, #34 ; 0x22
8001ac4: f883 203e strb.w r2, [r3, #62] ; 0x3e
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8001ac8: 68fb ldr r3, [r7, #12]
8001aca: 2200 movs r2, #0
8001acc: 631a str r2, [r3, #48] ; 0x30
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8001ace: f7fe ffb1 bl 8000a34 <HAL_GetTick>
8001ad2: 6178 str r0, [r7, #20]
huart->RxXferSize = Size;
8001ad4: 68fb ldr r3, [r7, #12]
8001ad6: 88fa ldrh r2, [r7, #6]
8001ad8: 859a strh r2, [r3, #44] ; 0x2c
huart->RxXferCount = Size;
8001ada: 68fb ldr r3, [r7, #12]
8001adc: 88fa ldrh r2, [r7, #6]
8001ade: 85da strh r2, [r3, #46] ; 0x2e
/* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8001ae0: 68fb ldr r3, [r7, #12]
8001ae2: 689b ldr r3, [r3, #8]
8001ae4: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8001ae8: d108 bne.n 8001afc <HAL_UART_Receive+0x8a>
8001aea: 68fb ldr r3, [r7, #12]
8001aec: 691b ldr r3, [r3, #16]
8001aee: 2b00 cmp r3, #0
8001af0: d104 bne.n 8001afc <HAL_UART_Receive+0x8a>
{
pdata8bits = NULL;
8001af2: 2300 movs r3, #0
8001af4: 61fb str r3, [r7, #28]
pdata16bits = (uint16_t *) pData;
8001af6: 68bb ldr r3, [r7, #8]
8001af8: 61bb str r3, [r7, #24]
8001afa: e003 b.n 8001b04 <HAL_UART_Receive+0x92>
}
else
{
pdata8bits = pData;
8001afc: 68bb ldr r3, [r7, #8]
8001afe: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8001b00: 2300 movs r3, #0
8001b02: 61bb str r3, [r7, #24]
}
/* Process Unlocked */
__HAL_UNLOCK(huart);
8001b04: 68fb ldr r3, [r7, #12]
8001b06: 2200 movs r2, #0
8001b08: f883 203c strb.w r2, [r3, #60] ; 0x3c
/* Check the remain data to be received */
while (huart->RxXferCount > 0U)
8001b0c: e043 b.n 8001b96 <HAL_UART_Receive+0x124>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
8001b0e: 683b ldr r3, [r7, #0]
8001b10: 9300 str r3, [sp, #0]
8001b12: 697b ldr r3, [r7, #20]
8001b14: 2200 movs r2, #0
8001b16: 2120 movs r1, #32
8001b18: 68f8 ldr r0, [r7, #12]
8001b1a: f000 f84c bl 8001bb6 <UART_WaitOnFlagUntilTimeout>
8001b1e: 4603 mov r3, r0
8001b20: 2b00 cmp r3, #0
8001b22: d001 beq.n 8001b28 <HAL_UART_Receive+0xb6>
{
return HAL_TIMEOUT;
8001b24: 2303 movs r3, #3
8001b26: e042 b.n 8001bae <HAL_UART_Receive+0x13c>
}
if (pdata8bits == NULL)
8001b28: 69fb ldr r3, [r7, #28]
8001b2a: 2b00 cmp r3, #0
8001b2c: d10c bne.n 8001b48 <HAL_UART_Receive+0xd6>
{
*pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
8001b2e: 68fb ldr r3, [r7, #12]
8001b30: 681b ldr r3, [r3, #0]
8001b32: 685b ldr r3, [r3, #4]
8001b34: b29b uxth r3, r3
8001b36: f3c3 0308 ubfx r3, r3, #0, #9
8001b3a: b29a uxth r2, r3
8001b3c: 69bb ldr r3, [r7, #24]
8001b3e: 801a strh r2, [r3, #0]
pdata16bits++;
8001b40: 69bb ldr r3, [r7, #24]
8001b42: 3302 adds r3, #2
8001b44: 61bb str r3, [r7, #24]
8001b46: e01f b.n 8001b88 <HAL_UART_Receive+0x116>
}
else
{
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
8001b48: 68fb ldr r3, [r7, #12]
8001b4a: 689b ldr r3, [r3, #8]
8001b4c: f5b3 5f80 cmp.w r3, #4096 ; 0x1000
8001b50: d007 beq.n 8001b62 <HAL_UART_Receive+0xf0>
8001b52: 68fb ldr r3, [r7, #12]
8001b54: 689b ldr r3, [r3, #8]
8001b56: 2b00 cmp r3, #0
8001b58: d10a bne.n 8001b70 <HAL_UART_Receive+0xfe>
8001b5a: 68fb ldr r3, [r7, #12]
8001b5c: 691b ldr r3, [r3, #16]
8001b5e: 2b00 cmp r3, #0
8001b60: d106 bne.n 8001b70 <HAL_UART_Receive+0xfe>
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
8001b62: 68fb ldr r3, [r7, #12]
8001b64: 681b ldr r3, [r3, #0]
8001b66: 685b ldr r3, [r3, #4]
8001b68: b2da uxtb r2, r3
8001b6a: 69fb ldr r3, [r7, #28]
8001b6c: 701a strb r2, [r3, #0]
8001b6e: e008 b.n 8001b82 <HAL_UART_Receive+0x110>
}
else
{
*pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
8001b70: 68fb ldr r3, [r7, #12]
8001b72: 681b ldr r3, [r3, #0]
8001b74: 685b ldr r3, [r3, #4]
8001b76: b2db uxtb r3, r3
8001b78: f003 037f and.w r3, r3, #127 ; 0x7f
8001b7c: b2da uxtb r2, r3
8001b7e: 69fb ldr r3, [r7, #28]
8001b80: 701a strb r2, [r3, #0]
}
pdata8bits++;
8001b82: 69fb ldr r3, [r7, #28]
8001b84: 3301 adds r3, #1
8001b86: 61fb str r3, [r7, #28]
}
huart->RxXferCount--;
8001b88: 68fb ldr r3, [r7, #12]
8001b8a: 8ddb ldrh r3, [r3, #46] ; 0x2e
8001b8c: b29b uxth r3, r3
8001b8e: 3b01 subs r3, #1
8001b90: b29a uxth r2, r3
8001b92: 68fb ldr r3, [r7, #12]
8001b94: 85da strh r2, [r3, #46] ; 0x2e
while (huart->RxXferCount > 0U)
8001b96: 68fb ldr r3, [r7, #12]
8001b98: 8ddb ldrh r3, [r3, #46] ; 0x2e
8001b9a: b29b uxth r3, r3
8001b9c: 2b00 cmp r3, #0
8001b9e: d1b6 bne.n 8001b0e <HAL_UART_Receive+0x9c>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8001ba0: 68fb ldr r3, [r7, #12]
8001ba2: 2220 movs r2, #32
8001ba4: f883 203e strb.w r2, [r3, #62] ; 0x3e
return HAL_OK;
8001ba8: 2300 movs r3, #0
8001baa: e000 b.n 8001bae <HAL_UART_Receive+0x13c>
}
else
{
return HAL_BUSY;
8001bac: 2302 movs r3, #2
}
}
8001bae: 4618 mov r0, r3
8001bb0: 3720 adds r7, #32
8001bb2: 46bd mov sp, r7
8001bb4: bd80 pop {r7, pc}
08001bb6 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
8001bb6: b580 push {r7, lr}
8001bb8: b090 sub sp, #64 ; 0x40
8001bba: af00 add r7, sp, #0
8001bbc: 60f8 str r0, [r7, #12]
8001bbe: 60b9 str r1, [r7, #8]
8001bc0: 603b str r3, [r7, #0]
8001bc2: 4613 mov r3, r2
8001bc4: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8001bc6: e050 b.n 8001c6a <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
8001bc8: 6cbb ldr r3, [r7, #72] ; 0x48
8001bca: f1b3 3fff cmp.w r3, #4294967295
8001bce: d04c beq.n 8001c6a <UART_WaitOnFlagUntilTimeout+0xb4>
{
if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
8001bd0: 6cbb ldr r3, [r7, #72] ; 0x48
8001bd2: 2b00 cmp r3, #0
8001bd4: d007 beq.n 8001be6 <UART_WaitOnFlagUntilTimeout+0x30>
8001bd6: f7fe ff2d bl 8000a34 <HAL_GetTick>
8001bda: 4602 mov r2, r0
8001bdc: 683b ldr r3, [r7, #0]
8001bde: 1ad3 subs r3, r2, r3
8001be0: 6cba ldr r2, [r7, #72] ; 0x48
8001be2: 429a cmp r2, r3
8001be4: d241 bcs.n 8001c6a <UART_WaitOnFlagUntilTimeout+0xb4>
{
/* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
8001be6: 68fb ldr r3, [r7, #12]
8001be8: 681b ldr r3, [r3, #0]
8001bea: 330c adds r3, #12
8001bec: 62bb str r3, [r7, #40] ; 0x28
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8001bee: 6abb ldr r3, [r7, #40] ; 0x28
8001bf0: e853 3f00 ldrex r3, [r3]
8001bf4: 627b str r3, [r7, #36] ; 0x24
return(result);
8001bf6: 6a7b ldr r3, [r7, #36] ; 0x24
8001bf8: f423 73d0 bic.w r3, r3, #416 ; 0x1a0
8001bfc: 63fb str r3, [r7, #60] ; 0x3c
8001bfe: 68fb ldr r3, [r7, #12]
8001c00: 681b ldr r3, [r3, #0]
8001c02: 330c adds r3, #12
8001c04: 6bfa ldr r2, [r7, #60] ; 0x3c
8001c06: 637a str r2, [r7, #52] ; 0x34
8001c08: 633b str r3, [r7, #48] ; 0x30
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8001c0a: 6b39 ldr r1, [r7, #48] ; 0x30
8001c0c: 6b7a ldr r2, [r7, #52] ; 0x34
8001c0e: e841 2300 strex r3, r2, [r1]
8001c12: 62fb str r3, [r7, #44] ; 0x2c
return(result);
8001c14: 6afb ldr r3, [r7, #44] ; 0x2c
8001c16: 2b00 cmp r3, #0
8001c18: d1e5 bne.n 8001be6 <UART_WaitOnFlagUntilTimeout+0x30>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8001c1a: 68fb ldr r3, [r7, #12]
8001c1c: 681b ldr r3, [r3, #0]
8001c1e: 3314 adds r3, #20
8001c20: 617b str r3, [r7, #20]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8001c22: 697b ldr r3, [r7, #20]
8001c24: e853 3f00 ldrex r3, [r3]
8001c28: 613b str r3, [r7, #16]
return(result);
8001c2a: 693b ldr r3, [r7, #16]
8001c2c: f023 0301 bic.w r3, r3, #1
8001c30: 63bb str r3, [r7, #56] ; 0x38
8001c32: 68fb ldr r3, [r7, #12]
8001c34: 681b ldr r3, [r3, #0]
8001c36: 3314 adds r3, #20
8001c38: 6bba ldr r2, [r7, #56] ; 0x38
8001c3a: 623a str r2, [r7, #32]
8001c3c: 61fb str r3, [r7, #28]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8001c3e: 69f9 ldr r1, [r7, #28]
8001c40: 6a3a ldr r2, [r7, #32]
8001c42: e841 2300 strex r3, r2, [r1]
8001c46: 61bb str r3, [r7, #24]
return(result);
8001c48: 69bb ldr r3, [r7, #24]
8001c4a: 2b00 cmp r3, #0
8001c4c: d1e5 bne.n 8001c1a <UART_WaitOnFlagUntilTimeout+0x64>
huart->gState = HAL_UART_STATE_READY;
8001c4e: 68fb ldr r3, [r7, #12]
8001c50: 2220 movs r2, #32
8001c52: f883 203d strb.w r2, [r3, #61] ; 0x3d
huart->RxState = HAL_UART_STATE_READY;
8001c56: 68fb ldr r3, [r7, #12]
8001c58: 2220 movs r2, #32
8001c5a: f883 203e strb.w r2, [r3, #62] ; 0x3e
/* Process Unlocked */
__HAL_UNLOCK(huart);
8001c5e: 68fb ldr r3, [r7, #12]
8001c60: 2200 movs r2, #0
8001c62: f883 203c strb.w r2, [r3, #60] ; 0x3c
return HAL_TIMEOUT;
8001c66: 2303 movs r3, #3
8001c68: e00f b.n 8001c8a <UART_WaitOnFlagUntilTimeout+0xd4>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8001c6a: 68fb ldr r3, [r7, #12]
8001c6c: 681b ldr r3, [r3, #0]
8001c6e: 681a ldr r2, [r3, #0]
8001c70: 68bb ldr r3, [r7, #8]
8001c72: 4013 ands r3, r2
8001c74: 68ba ldr r2, [r7, #8]
8001c76: 429a cmp r2, r3
8001c78: bf0c ite eq
8001c7a: 2301 moveq r3, #1
8001c7c: 2300 movne r3, #0
8001c7e: b2db uxtb r3, r3
8001c80: 461a mov r2, r3
8001c82: 79fb ldrb r3, [r7, #7]
8001c84: 429a cmp r2, r3
8001c86: d09f beq.n 8001bc8 <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
return HAL_OK;
8001c88: 2300 movs r3, #0
}
8001c8a: 4618 mov r0, r3
8001c8c: 3740 adds r7, #64 ; 0x40
8001c8e: 46bd mov sp, r7
8001c90: bd80 pop {r7, pc}
...
08001c94 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
8001c94: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8001c98: b0c0 sub sp, #256 ; 0x100
8001c9a: af00 add r7, sp, #0
8001c9c: f8c7 00f4 str.w r0, [r7, #244] ; 0xf4
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8001ca0: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001ca4: 681b ldr r3, [r3, #0]
8001ca6: 691b ldr r3, [r3, #16]
8001ca8: f423 5040 bic.w r0, r3, #12288 ; 0x3000
8001cac: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001cb0: 68d9 ldr r1, [r3, #12]
8001cb2: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001cb6: 681a ldr r2, [r3, #0]
8001cb8: ea40 0301 orr.w r3, r0, r1
8001cbc: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
8001cbe: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001cc2: 689a ldr r2, [r3, #8]
8001cc4: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001cc8: 691b ldr r3, [r3, #16]
8001cca: 431a orrs r2, r3
8001ccc: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001cd0: 695b ldr r3, [r3, #20]
8001cd2: 431a orrs r2, r3
8001cd4: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001cd8: 69db ldr r3, [r3, #28]
8001cda: 4313 orrs r3, r2
8001cdc: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8
MODIFY_REG(huart->Instance->CR1,
8001ce0: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001ce4: 681b ldr r3, [r3, #0]
8001ce6: 68db ldr r3, [r3, #12]
8001ce8: f423 4116 bic.w r1, r3, #38400 ; 0x9600
8001cec: f021 010c bic.w r1, r1, #12
8001cf0: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001cf4: 681a ldr r2, [r3, #0]
8001cf6: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8
8001cfa: 430b orrs r3, r1
8001cfc: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
8001cfe: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001d02: 681b ldr r3, [r3, #0]
8001d04: 695b ldr r3, [r3, #20]
8001d06: f423 7040 bic.w r0, r3, #768 ; 0x300
8001d0a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001d0e: 6999 ldr r1, [r3, #24]
8001d10: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001d14: 681a ldr r2, [r3, #0]
8001d16: ea40 0301 orr.w r3, r0, r1
8001d1a: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
8001d1c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001d20: 681a ldr r2, [r3, #0]
8001d22: 4b8f ldr r3, [pc, #572] ; (8001f60 <UART_SetConfig+0x2cc>)
8001d24: 429a cmp r2, r3
8001d26: d005 beq.n 8001d34 <UART_SetConfig+0xa0>
8001d28: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001d2c: 681a ldr r2, [r3, #0]
8001d2e: 4b8d ldr r3, [pc, #564] ; (8001f64 <UART_SetConfig+0x2d0>)
8001d30: 429a cmp r2, r3
8001d32: d104 bne.n 8001d3e <UART_SetConfig+0xaa>
{
pclk = HAL_RCC_GetPCLK2Freq();
8001d34: f7ff fdaa bl 800188c <HAL_RCC_GetPCLK2Freq>
8001d38: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
8001d3c: e003 b.n 8001d46 <UART_SetConfig+0xb2>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
8001d3e: f7ff fd91 bl 8001864 <HAL_RCC_GetPCLK1Freq>
8001d42: f8c7 00fc str.w r0, [r7, #252] ; 0xfc
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8001d46: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001d4a: 69db ldr r3, [r3, #28]
8001d4c: f5b3 4f00 cmp.w r3, #32768 ; 0x8000
8001d50: f040 810c bne.w 8001f6c <UART_SetConfig+0x2d8>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
8001d54: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001d58: 2200 movs r2, #0
8001d5a: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8
8001d5e: f8c7 20ec str.w r2, [r7, #236] ; 0xec
8001d62: e9d7 453a ldrd r4, r5, [r7, #232] ; 0xe8
8001d66: 4622 mov r2, r4
8001d68: 462b mov r3, r5
8001d6a: 1891 adds r1, r2, r2
8001d6c: 65b9 str r1, [r7, #88] ; 0x58
8001d6e: 415b adcs r3, r3
8001d70: 65fb str r3, [r7, #92] ; 0x5c
8001d72: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58
8001d76: 4621 mov r1, r4
8001d78: eb12 0801 adds.w r8, r2, r1
8001d7c: 4629 mov r1, r5
8001d7e: eb43 0901 adc.w r9, r3, r1
8001d82: f04f 0200 mov.w r2, #0
8001d86: f04f 0300 mov.w r3, #0
8001d8a: ea4f 03c9 mov.w r3, r9, lsl #3
8001d8e: ea43 7358 orr.w r3, r3, r8, lsr #29
8001d92: ea4f 02c8 mov.w r2, r8, lsl #3
8001d96: 4690 mov r8, r2
8001d98: 4699 mov r9, r3
8001d9a: 4623 mov r3, r4
8001d9c: eb18 0303 adds.w r3, r8, r3
8001da0: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0
8001da4: 462b mov r3, r5
8001da6: eb49 0303 adc.w r3, r9, r3
8001daa: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4
8001dae: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001db2: 685b ldr r3, [r3, #4]
8001db4: 2200 movs r2, #0
8001db6: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8
8001dba: f8c7 20dc str.w r2, [r7, #220] ; 0xdc
8001dbe: e9d7 1236 ldrd r1, r2, [r7, #216] ; 0xd8
8001dc2: 460b mov r3, r1
8001dc4: 18db adds r3, r3, r3
8001dc6: 653b str r3, [r7, #80] ; 0x50
8001dc8: 4613 mov r3, r2
8001dca: eb42 0303 adc.w r3, r2, r3
8001dce: 657b str r3, [r7, #84] ; 0x54
8001dd0: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50
8001dd4: e9d7 0138 ldrd r0, r1, [r7, #224] ; 0xe0
8001dd8: f7fe f9fe bl 80001d8 <__aeabi_uldivmod>
8001ddc: 4602 mov r2, r0
8001dde: 460b mov r3, r1
8001de0: 4b61 ldr r3, [pc, #388] ; (8001f68 <UART_SetConfig+0x2d4>)
8001de2: fba3 2302 umull r2, r3, r3, r2
8001de6: 095b lsrs r3, r3, #5
8001de8: 011c lsls r4, r3, #4
8001dea: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001dee: 2200 movs r2, #0
8001df0: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0
8001df4: f8c7 20d4 str.w r2, [r7, #212] ; 0xd4
8001df8: e9d7 8934 ldrd r8, r9, [r7, #208] ; 0xd0
8001dfc: 4642 mov r2, r8
8001dfe: 464b mov r3, r9
8001e00: 1891 adds r1, r2, r2
8001e02: 64b9 str r1, [r7, #72] ; 0x48
8001e04: 415b adcs r3, r3
8001e06: 64fb str r3, [r7, #76] ; 0x4c
8001e08: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48
8001e0c: 4641 mov r1, r8
8001e0e: eb12 0a01 adds.w sl, r2, r1
8001e12: 4649 mov r1, r9
8001e14: eb43 0b01 adc.w fp, r3, r1
8001e18: f04f 0200 mov.w r2, #0
8001e1c: f04f 0300 mov.w r3, #0
8001e20: ea4f 03cb mov.w r3, fp, lsl #3
8001e24: ea43 735a orr.w r3, r3, sl, lsr #29
8001e28: ea4f 02ca mov.w r2, sl, lsl #3
8001e2c: 4692 mov sl, r2
8001e2e: 469b mov fp, r3
8001e30: 4643 mov r3, r8
8001e32: eb1a 0303 adds.w r3, sl, r3
8001e36: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8
8001e3a: 464b mov r3, r9
8001e3c: eb4b 0303 adc.w r3, fp, r3
8001e40: f8c7 30cc str.w r3, [r7, #204] ; 0xcc
8001e44: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001e48: 685b ldr r3, [r3, #4]
8001e4a: 2200 movs r2, #0
8001e4c: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0
8001e50: f8c7 20c4 str.w r2, [r7, #196] ; 0xc4
8001e54: e9d7 1230 ldrd r1, r2, [r7, #192] ; 0xc0
8001e58: 460b mov r3, r1
8001e5a: 18db adds r3, r3, r3
8001e5c: 643b str r3, [r7, #64] ; 0x40
8001e5e: 4613 mov r3, r2
8001e60: eb42 0303 adc.w r3, r2, r3
8001e64: 647b str r3, [r7, #68] ; 0x44
8001e66: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40
8001e6a: e9d7 0132 ldrd r0, r1, [r7, #200] ; 0xc8
8001e6e: f7fe f9b3 bl 80001d8 <__aeabi_uldivmod>
8001e72: 4602 mov r2, r0
8001e74: 460b mov r3, r1
8001e76: 4611 mov r1, r2
8001e78: 4b3b ldr r3, [pc, #236] ; (8001f68 <UART_SetConfig+0x2d4>)
8001e7a: fba3 2301 umull r2, r3, r3, r1
8001e7e: 095b lsrs r3, r3, #5
8001e80: 2264 movs r2, #100 ; 0x64
8001e82: fb02 f303 mul.w r3, r2, r3
8001e86: 1acb subs r3, r1, r3
8001e88: 00db lsls r3, r3, #3
8001e8a: f103 0232 add.w r2, r3, #50 ; 0x32
8001e8e: 4b36 ldr r3, [pc, #216] ; (8001f68 <UART_SetConfig+0x2d4>)
8001e90: fba3 2302 umull r2, r3, r3, r2
8001e94: 095b lsrs r3, r3, #5
8001e96: 005b lsls r3, r3, #1
8001e98: f403 73f8 and.w r3, r3, #496 ; 0x1f0
8001e9c: 441c add r4, r3
8001e9e: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001ea2: 2200 movs r2, #0
8001ea4: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8
8001ea8: f8c7 20bc str.w r2, [r7, #188] ; 0xbc
8001eac: e9d7 892e ldrd r8, r9, [r7, #184] ; 0xb8
8001eb0: 4642 mov r2, r8
8001eb2: 464b mov r3, r9
8001eb4: 1891 adds r1, r2, r2
8001eb6: 63b9 str r1, [r7, #56] ; 0x38
8001eb8: 415b adcs r3, r3
8001eba: 63fb str r3, [r7, #60] ; 0x3c
8001ebc: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38
8001ec0: 4641 mov r1, r8
8001ec2: 1851 adds r1, r2, r1
8001ec4: 6339 str r1, [r7, #48] ; 0x30
8001ec6: 4649 mov r1, r9
8001ec8: 414b adcs r3, r1
8001eca: 637b str r3, [r7, #52] ; 0x34
8001ecc: f04f 0200 mov.w r2, #0
8001ed0: f04f 0300 mov.w r3, #0
8001ed4: e9d7 ab0c ldrd sl, fp, [r7, #48] ; 0x30
8001ed8: 4659 mov r1, fp
8001eda: 00cb lsls r3, r1, #3
8001edc: 4651 mov r1, sl
8001ede: ea43 7351 orr.w r3, r3, r1, lsr #29
8001ee2: 4651 mov r1, sl
8001ee4: 00ca lsls r2, r1, #3
8001ee6: 4610 mov r0, r2
8001ee8: 4619 mov r1, r3
8001eea: 4603 mov r3, r0
8001eec: 4642 mov r2, r8
8001eee: 189b adds r3, r3, r2
8001ef0: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0
8001ef4: 464b mov r3, r9
8001ef6: 460a mov r2, r1
8001ef8: eb42 0303 adc.w r3, r2, r3
8001efc: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4
8001f00: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001f04: 685b ldr r3, [r3, #4]
8001f06: 2200 movs r2, #0
8001f08: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8
8001f0c: f8c7 20ac str.w r2, [r7, #172] ; 0xac
8001f10: e9d7 122a ldrd r1, r2, [r7, #168] ; 0xa8
8001f14: 460b mov r3, r1
8001f16: 18db adds r3, r3, r3
8001f18: 62bb str r3, [r7, #40] ; 0x28
8001f1a: 4613 mov r3, r2
8001f1c: eb42 0303 adc.w r3, r2, r3
8001f20: 62fb str r3, [r7, #44] ; 0x2c
8001f22: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28
8001f26: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0
8001f2a: f7fe f955 bl 80001d8 <__aeabi_uldivmod>
8001f2e: 4602 mov r2, r0
8001f30: 460b mov r3, r1
8001f32: 4b0d ldr r3, [pc, #52] ; (8001f68 <UART_SetConfig+0x2d4>)
8001f34: fba3 1302 umull r1, r3, r3, r2
8001f38: 095b lsrs r3, r3, #5
8001f3a: 2164 movs r1, #100 ; 0x64
8001f3c: fb01 f303 mul.w r3, r1, r3
8001f40: 1ad3 subs r3, r2, r3
8001f42: 00db lsls r3, r3, #3
8001f44: 3332 adds r3, #50 ; 0x32
8001f46: 4a08 ldr r2, [pc, #32] ; (8001f68 <UART_SetConfig+0x2d4>)
8001f48: fba2 2303 umull r2, r3, r2, r3
8001f4c: 095b lsrs r3, r3, #5
8001f4e: f003 0207 and.w r2, r3, #7
8001f52: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001f56: 681b ldr r3, [r3, #0]
8001f58: 4422 add r2, r4
8001f5a: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
8001f5c: e106 b.n 800216c <UART_SetConfig+0x4d8>
8001f5e: bf00 nop
8001f60: 40011000 .word 0x40011000
8001f64: 40011400 .word 0x40011400
8001f68: 51eb851f .word 0x51eb851f
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
8001f6c: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8001f70: 2200 movs r2, #0
8001f72: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0
8001f76: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4
8001f7a: e9d7 8928 ldrd r8, r9, [r7, #160] ; 0xa0
8001f7e: 4642 mov r2, r8
8001f80: 464b mov r3, r9
8001f82: 1891 adds r1, r2, r2
8001f84: 6239 str r1, [r7, #32]
8001f86: 415b adcs r3, r3
8001f88: 627b str r3, [r7, #36] ; 0x24
8001f8a: e9d7 2308 ldrd r2, r3, [r7, #32]
8001f8e: 4641 mov r1, r8
8001f90: 1854 adds r4, r2, r1
8001f92: 4649 mov r1, r9
8001f94: eb43 0501 adc.w r5, r3, r1
8001f98: f04f 0200 mov.w r2, #0
8001f9c: f04f 0300 mov.w r3, #0
8001fa0: 00eb lsls r3, r5, #3
8001fa2: ea43 7354 orr.w r3, r3, r4, lsr #29
8001fa6: 00e2 lsls r2, r4, #3
8001fa8: 4614 mov r4, r2
8001faa: 461d mov r5, r3
8001fac: 4643 mov r3, r8
8001fae: 18e3 adds r3, r4, r3
8001fb0: f8c7 3098 str.w r3, [r7, #152] ; 0x98
8001fb4: 464b mov r3, r9
8001fb6: eb45 0303 adc.w r3, r5, r3
8001fba: f8c7 309c str.w r3, [r7, #156] ; 0x9c
8001fbe: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8001fc2: 685b ldr r3, [r3, #4]
8001fc4: 2200 movs r2, #0
8001fc6: f8c7 3090 str.w r3, [r7, #144] ; 0x90
8001fca: f8c7 2094 str.w r2, [r7, #148] ; 0x94
8001fce: f04f 0200 mov.w r2, #0
8001fd2: f04f 0300 mov.w r3, #0
8001fd6: e9d7 4524 ldrd r4, r5, [r7, #144] ; 0x90
8001fda: 4629 mov r1, r5
8001fdc: 008b lsls r3, r1, #2
8001fde: 4621 mov r1, r4
8001fe0: ea43 7391 orr.w r3, r3, r1, lsr #30
8001fe4: 4621 mov r1, r4
8001fe6: 008a lsls r2, r1, #2
8001fe8: e9d7 0126 ldrd r0, r1, [r7, #152] ; 0x98
8001fec: f7fe f8f4 bl 80001d8 <__aeabi_uldivmod>
8001ff0: 4602 mov r2, r0
8001ff2: 460b mov r3, r1
8001ff4: 4b60 ldr r3, [pc, #384] ; (8002178 <UART_SetConfig+0x4e4>)
8001ff6: fba3 2302 umull r2, r3, r3, r2
8001ffa: 095b lsrs r3, r3, #5
8001ffc: 011c lsls r4, r3, #4
8001ffe: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
8002002: 2200 movs r2, #0
8002004: f8c7 3088 str.w r3, [r7, #136] ; 0x88
8002008: f8c7 208c str.w r2, [r7, #140] ; 0x8c
800200c: e9d7 8922 ldrd r8, r9, [r7, #136] ; 0x88
8002010: 4642 mov r2, r8
8002012: 464b mov r3, r9
8002014: 1891 adds r1, r2, r2
8002016: 61b9 str r1, [r7, #24]
8002018: 415b adcs r3, r3
800201a: 61fb str r3, [r7, #28]
800201c: e9d7 2306 ldrd r2, r3, [r7, #24]
8002020: 4641 mov r1, r8
8002022: 1851 adds r1, r2, r1
8002024: 6139 str r1, [r7, #16]
8002026: 4649 mov r1, r9
8002028: 414b adcs r3, r1
800202a: 617b str r3, [r7, #20]
800202c: f04f 0200 mov.w r2, #0
8002030: f04f 0300 mov.w r3, #0
8002034: e9d7 ab04 ldrd sl, fp, [r7, #16]
8002038: 4659 mov r1, fp
800203a: 00cb lsls r3, r1, #3
800203c: 4651 mov r1, sl
800203e: ea43 7351 orr.w r3, r3, r1, lsr #29
8002042: 4651 mov r1, sl
8002044: 00ca lsls r2, r1, #3
8002046: 4610 mov r0, r2
8002048: 4619 mov r1, r3
800204a: 4603 mov r3, r0
800204c: 4642 mov r2, r8
800204e: 189b adds r3, r3, r2
8002050: f8c7 3080 str.w r3, [r7, #128] ; 0x80
8002054: 464b mov r3, r9
8002056: 460a mov r2, r1
8002058: eb42 0303 adc.w r3, r2, r3
800205c: f8c7 3084 str.w r3, [r7, #132] ; 0x84
8002060: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002064: 685b ldr r3, [r3, #4]
8002066: 2200 movs r2, #0
8002068: 67bb str r3, [r7, #120] ; 0x78
800206a: 67fa str r2, [r7, #124] ; 0x7c
800206c: f04f 0200 mov.w r2, #0
8002070: f04f 0300 mov.w r3, #0
8002074: e9d7 891e ldrd r8, r9, [r7, #120] ; 0x78
8002078: 4649 mov r1, r9
800207a: 008b lsls r3, r1, #2
800207c: 4641 mov r1, r8
800207e: ea43 7391 orr.w r3, r3, r1, lsr #30
8002082: 4641 mov r1, r8
8002084: 008a lsls r2, r1, #2
8002086: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80
800208a: f7fe f8a5 bl 80001d8 <__aeabi_uldivmod>
800208e: 4602 mov r2, r0
8002090: 460b mov r3, r1
8002092: 4611 mov r1, r2
8002094: 4b38 ldr r3, [pc, #224] ; (8002178 <UART_SetConfig+0x4e4>)
8002096: fba3 2301 umull r2, r3, r3, r1
800209a: 095b lsrs r3, r3, #5
800209c: 2264 movs r2, #100 ; 0x64
800209e: fb02 f303 mul.w r3, r2, r3
80020a2: 1acb subs r3, r1, r3
80020a4: 011b lsls r3, r3, #4
80020a6: 3332 adds r3, #50 ; 0x32
80020a8: 4a33 ldr r2, [pc, #204] ; (8002178 <UART_SetConfig+0x4e4>)
80020aa: fba2 2303 umull r2, r3, r2, r3
80020ae: 095b lsrs r3, r3, #5
80020b0: f003 03f0 and.w r3, r3, #240 ; 0xf0
80020b4: 441c add r4, r3
80020b6: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc
80020ba: 2200 movs r2, #0
80020bc: 673b str r3, [r7, #112] ; 0x70
80020be: 677a str r2, [r7, #116] ; 0x74
80020c0: e9d7 891c ldrd r8, r9, [r7, #112] ; 0x70
80020c4: 4642 mov r2, r8
80020c6: 464b mov r3, r9
80020c8: 1891 adds r1, r2, r2
80020ca: 60b9 str r1, [r7, #8]
80020cc: 415b adcs r3, r3
80020ce: 60fb str r3, [r7, #12]
80020d0: e9d7 2302 ldrd r2, r3, [r7, #8]
80020d4: 4641 mov r1, r8
80020d6: 1851 adds r1, r2, r1
80020d8: 6039 str r1, [r7, #0]
80020da: 4649 mov r1, r9
80020dc: 414b adcs r3, r1
80020de: 607b str r3, [r7, #4]
80020e0: f04f 0200 mov.w r2, #0
80020e4: f04f 0300 mov.w r3, #0
80020e8: e9d7 ab00 ldrd sl, fp, [r7]
80020ec: 4659 mov r1, fp
80020ee: 00cb lsls r3, r1, #3
80020f0: 4651 mov r1, sl
80020f2: ea43 7351 orr.w r3, r3, r1, lsr #29
80020f6: 4651 mov r1, sl
80020f8: 00ca lsls r2, r1, #3
80020fa: 4610 mov r0, r2
80020fc: 4619 mov r1, r3
80020fe: 4603 mov r3, r0
8002100: 4642 mov r2, r8
8002102: 189b adds r3, r3, r2
8002104: 66bb str r3, [r7, #104] ; 0x68
8002106: 464b mov r3, r9
8002108: 460a mov r2, r1
800210a: eb42 0303 adc.w r3, r2, r3
800210e: 66fb str r3, [r7, #108] ; 0x6c
8002110: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002114: 685b ldr r3, [r3, #4]
8002116: 2200 movs r2, #0
8002118: 663b str r3, [r7, #96] ; 0x60
800211a: 667a str r2, [r7, #100] ; 0x64
800211c: f04f 0200 mov.w r2, #0
8002120: f04f 0300 mov.w r3, #0
8002124: e9d7 8918 ldrd r8, r9, [r7, #96] ; 0x60
8002128: 4649 mov r1, r9
800212a: 008b lsls r3, r1, #2
800212c: 4641 mov r1, r8
800212e: ea43 7391 orr.w r3, r3, r1, lsr #30
8002132: 4641 mov r1, r8
8002134: 008a lsls r2, r1, #2
8002136: e9d7 011a ldrd r0, r1, [r7, #104] ; 0x68
800213a: f7fe f84d bl 80001d8 <__aeabi_uldivmod>
800213e: 4602 mov r2, r0
8002140: 460b mov r3, r1
8002142: 4b0d ldr r3, [pc, #52] ; (8002178 <UART_SetConfig+0x4e4>)
8002144: fba3 1302 umull r1, r3, r3, r2
8002148: 095b lsrs r3, r3, #5
800214a: 2164 movs r1, #100 ; 0x64
800214c: fb01 f303 mul.w r3, r1, r3
8002150: 1ad3 subs r3, r2, r3
8002152: 011b lsls r3, r3, #4
8002154: 3332 adds r3, #50 ; 0x32
8002156: 4a08 ldr r2, [pc, #32] ; (8002178 <UART_SetConfig+0x4e4>)
8002158: fba2 2303 umull r2, r3, r2, r3
800215c: 095b lsrs r3, r3, #5
800215e: f003 020f and.w r2, r3, #15
8002162: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4
8002166: 681b ldr r3, [r3, #0]
8002168: 4422 add r2, r4
800216a: 609a str r2, [r3, #8]
}
800216c: bf00 nop
800216e: f507 7780 add.w r7, r7, #256 ; 0x100
8002172: 46bd mov sp, r7
8002174: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8002178: 51eb851f .word 0x51eb851f
0800217c <memset>:
800217c: 4402 add r2, r0
800217e: 4603 mov r3, r0
8002180: 4293 cmp r3, r2
8002182: d100 bne.n 8002186 <memset+0xa>
8002184: 4770 bx lr
8002186: f803 1b01 strb.w r1, [r3], #1
800218a: e7f9 b.n 8002180 <memset+0x4>
0800218c <__libc_init_array>:
800218c: b570 push {r4, r5, r6, lr}
800218e: 4d0d ldr r5, [pc, #52] ; (80021c4 <__libc_init_array+0x38>)
8002190: 4c0d ldr r4, [pc, #52] ; (80021c8 <__libc_init_array+0x3c>)
8002192: 1b64 subs r4, r4, r5
8002194: 10a4 asrs r4, r4, #2
8002196: 2600 movs r6, #0
8002198: 42a6 cmp r6, r4
800219a: d109 bne.n 80021b0 <__libc_init_array+0x24>
800219c: 4d0b ldr r5, [pc, #44] ; (80021cc <__libc_init_array+0x40>)
800219e: 4c0c ldr r4, [pc, #48] ; (80021d0 <__libc_init_array+0x44>)
80021a0: f000 f818 bl 80021d4 <_init>
80021a4: 1b64 subs r4, r4, r5
80021a6: 10a4 asrs r4, r4, #2
80021a8: 2600 movs r6, #0
80021aa: 42a6 cmp r6, r4
80021ac: d105 bne.n 80021ba <__libc_init_array+0x2e>
80021ae: bd70 pop {r4, r5, r6, pc}
80021b0: f855 3b04 ldr.w r3, [r5], #4
80021b4: 4798 blx r3
80021b6: 3601 adds r6, #1
80021b8: e7ee b.n 8002198 <__libc_init_array+0xc>
80021ba: f855 3b04 ldr.w r3, [r5], #4
80021be: 4798 blx r3
80021c0: 3601 adds r6, #1
80021c2: e7f2 b.n 80021aa <__libc_init_array+0x1e>
80021c4: 0800220c .word 0x0800220c
80021c8: 0800220c .word 0x0800220c
80021cc: 0800220c .word 0x0800220c
80021d0: 08002210 .word 0x08002210
080021d4 <_init>:
80021d4: b5f8 push {r3, r4, r5, r6, r7, lr}
80021d6: bf00 nop
80021d8: bcf8 pop {r3, r4, r5, r6, r7}
80021da: bc08 pop {r3}
80021dc: 469e mov lr, r3
80021de: 4770 bx lr
080021e0 <_fini>:
80021e0: b5f8 push {r3, r4, r5, r6, r7, lr}
80021e2: bf00 nop
80021e4: bcf8 pop {r3, r4, r5, r6, r7}
80021e6: bc08 pop {r3}
80021e8: 469e mov lr, r3
80021ea: 4770 bx lr
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