diff --git a/access_control_python/__pycache__/access_control.cpython-311.pyc b/access_control_python/__pycache__/access_control.cpython-311.pyc index cf8aadf..023b18b 100644 Binary files a/access_control_python/__pycache__/access_control.cpython-311.pyc and b/access_control_python/__pycache__/access_control.cpython-311.pyc differ diff --git a/access_control_python/__pycache__/face_processing.cpython-311.pyc b/access_control_python/__pycache__/face_processing.cpython-311.pyc index 9945fe6..b99e133 100644 Binary files a/access_control_python/__pycache__/face_processing.cpython-311.pyc and b/access_control_python/__pycache__/face_processing.cpython-311.pyc differ diff --git a/access_control_python/access_control.py b/access_control_python/access_control.py index 5ad8d53..55a4863 100644 --- a/access_control_python/access_control.py +++ b/access_control_python/access_control.py @@ -5,22 +5,33 @@ from threading import Thread class access_control: _in_payloads = [] _read_buffer = [] - _door_state: bool = 0 + _door_state: bool = False serial_adapter: serial.Serial + _scan_active: bool = False + _read_active = True def __init__(self, serial_port: str): self.serial_adapter = serial.Serial(serial_port,baudrate=9600) - #Thread(target=self.read_serial).start() - #Thread(target=self._process_payload).start() - def read_serial(self): + Thread(target=self.read_serial).start() + Thread(target=self._process_payload).start() + #Thread(target=self._state_requester).start() + + def _state_requester(self): while True: - if self.serial_adapter.in_waiting: - in_byte = self.serial_adapter.read(1) - if(in_byte==b'\xFF'): - self._in_payloads.append(self._read_buffer) - self._read_buffer = [] - else: - self._read_buffer.append(in_byte) - time.sleep(0.01) + if self._read_active: + self._request_door_state() + self._request_scan_state() + time.sleep(1) + + def read_serial(self): + while True: + if self.serial_adapter.in_waiting>0: + in_byte = self.serial_adapter.read(1) + if(in_byte==b'\xFF'): + self._in_payloads.append(self._read_buffer) + self._read_buffer = [] + else: + self._read_buffer.append(in_byte) + time.sleep(0.01) def _process_payload(self): while True: self._process_payload_once() @@ -30,11 +41,18 @@ class access_control: def _process_payload_once(self): if(len(self._in_payloads)>0): payload = self._in_payloads.pop(0) - if(payload[0]==b'\x01'): - if(payload[1]==b'\x00'): - self._door_state = True - elif(payload[1]==b'\01'): - self._door_state = False + if len(payload)>0: + if(payload[0]==b'\x01'): + if(payload[1]==b'\x00'): + self._door_state = True + elif(payload[1]==b'\01'): + self._door_state = False + elif(payload[0]==b'\x02'): + if(payload[1]==b'\x00'): + self._scan_active = False + elif(payload[1]==b'\01'): + self._scan_active = True + def light_on(self): packet = bytearray() @@ -53,11 +71,18 @@ class access_control: packet.append(0x01) packet.append(0xFF) self.serial_adapter.write(packet) + + def _request_scan_state(self): + packet = bytearray() + packet.append(0x03) + packet.append(0xFF) + self.serial_adapter.write(packet) def get_door_state(self) -> bool: - self._request_door_state() - time.sleep(0.05) return self._door_state + def get_scan_state(self) -> bool: + return self._scan_active + def lock_door(self): packet = bytearray() packet.append(0x02) diff --git a/access_control_python/face_processing.py b/access_control_python/face_processing.py index fbaa624..030e032 100644 --- a/access_control_python/face_processing.py +++ b/access_control_python/face_processing.py @@ -5,8 +5,8 @@ import requests import json #api_server = "http://localhost:5000" -#api_server = "http://192.168.0.239:5000" -api_server = "https://racist.siwatsystem.com" +api_server = "http://192.168.0.239" +#api_server = "https://racist.siwatsystem.com" def analyze_face(img): endpoint = api_server +"/process_image" diff --git a/access_control_python/main.py b/access_control_python/main.py index 8b4406a..407475f 100644 --- a/access_control_python/main.py +++ b/access_control_python/main.py @@ -28,10 +28,13 @@ while True: time.sleep(1) #Try to identify face - faces = fp.identify_face(img, target_condidence=0.6) - if(len(faces)>0): - print("Door Unlocked!, Locking in 5 seconds") - stm32.unlock_door() - time.sleep(5) - stm32.lock_door() - print("Door Locked!") + if stm32.get_scan_state(): + print("SCAN ACTIVE!") + faces = fp.identify_face(img, target_condidence=0.6) + if(len(faces)>0): + print("Door Unlocked!, Locking in 5 seconds") + stm32.unlock_door() + time.sleep(5) + stm32.lock_door() + print("Door Locked!") + print("DONE") diff --git a/access_control_python/mcu_test.py b/access_control_python/mcu_test.py index dbd13e9..49def66 100644 --- a/access_control_python/mcu_test.py +++ b/access_control_python/mcu_test.py @@ -10,6 +10,10 @@ while True: stm32.lock_door() if(cmd == 'unlock'): stm32.unlock_door() + if(cmd == 'scan_state'): + print(stm32.get_scan_state()) + if(cmd == 'door_state'): + print(stm32.get_door_state()) #stm32.unlock_door() time.sleep(1) #door_state = False diff --git a/access_control_stm32/.mxproject b/access_control_stm32/.mxproject index 0ec63c1..57f8abe 100644 --- a/access_control_stm32/.mxproject +++ b/access_control_stm32/.mxproject @@ -1,8 +1,8 @@ [PreviousLibFiles] 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[PreviousUsedCubeIDEFiles] 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+SourceFiles=Core\Src\main.c;Core\Src\freertos.c;Core\Src\stm32f4xx_it.c;Core\Src\stm32f4xx_hal_msp.c;Core\Src\stm32f4xx_hal_timebase_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_adc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_ll_adc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_rcc_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_flash_ramfunc.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_gpio.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_dma.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_pwr_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_cortex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_exti.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_tim_ex.c;Drivers\STM32F4xx_HAL_Driver\Src\stm32f4xx_hal_uart.c;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c;Drivers\CMSIS\Device\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c;Core\Src\system_stm32f4xx.c;;;Middlewares\Third_Party\FreeRTOS\Source\croutine.c;Middlewares\Third_Party\FreeRTOS\Source\event_groups.c;Middlewares\Third_Party\FreeRTOS\Source\list.c;Middlewares\Third_Party\FreeRTOS\Source\queue.c;Middlewares\Third_Party\FreeRTOS\Source\stream_buffer.c;Middlewares\Third_Party\FreeRTOS\Source\tasks.c;Middlewares\Third_Party\FreeRTOS\Source\timers.c;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2\cmsis_os2.c;Middlewares\Third_Party\FreeRTOS\Source\portable\MemMang\heap_4.c;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F\port.c; HeaderPath=Drivers\STM32F4xx_HAL_Driver\Inc;Drivers\STM32F4xx_HAL_Driver\Inc\Legacy;Middlewares\Third_Party\FreeRTOS\Source\include;Middlewares\Third_Party\FreeRTOS\Source\CMSIS_RTOS_V2;Middlewares\Third_Party\FreeRTOS\Source\portable\GCC\ARM_CM4F;Drivers\CMSIS\Device\ST\STM32F4xx\Include;Drivers\CMSIS\Include;Core\Inc; CDefines=USE_HAL_DRIVER;STM32F411xE;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/access_control_stm32/.settings/language.settings.xml b/access_control_stm32/.settings/language.settings.xml index 20511cb..4038738 100644 --- a/access_control_stm32/.settings/language.settings.xml +++ b/access_control_stm32/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/access_control_stm32/Core/Inc/stm32f4xx_hal_conf.h b/access_control_stm32/Core/Inc/stm32f4xx_hal_conf.h index 0514b7b..0cc01db 100644 --- a/access_control_stm32/Core/Inc/stm32f4xx_hal_conf.h +++ b/access_control_stm32/Core/Inc/stm32f4xx_hal_conf.h @@ -38,7 +38,7 @@ #define HAL_MODULE_ENABLED /* #define HAL_CRYP_MODULE_ENABLED */ -/* #define HAL_ADC_MODULE_ENABLED */ +#define HAL_ADC_MODULE_ENABLED /* #define HAL_CAN_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ /* #define HAL_CAN_LEGACY_MODULE_ENABLED */ diff --git a/access_control_stm32/Core/Inc/stm32f4xx_it.h b/access_control_stm32/Core/Inc/stm32f4xx_it.h index 5d8679e..cea38c9 100644 --- a/access_control_stm32/Core/Inc/stm32f4xx_it.h +++ b/access_control_stm32/Core/Inc/stm32f4xx_it.h @@ -52,6 +52,7 @@ void MemManage_Handler(void); void BusFault_Handler(void); void UsageFault_Handler(void); void DebugMon_Handler(void); +void ADC_IRQHandler(void); void TIM1_UP_TIM10_IRQHandler(void); /* USER CODE BEGIN EFP */ diff --git a/access_control_stm32/Core/Src/main.c b/access_control_stm32/Core/Src/main.c index 498d90b..250bb05 100644 --- a/access_control_stm32/Core/Src/main.c +++ b/access_control_stm32/Core/Src/main.c @@ -55,16 +55,38 @@ /* USER CODE END PM */ /* Private variables ---------------------------------------------------------*/ +ADC_HandleTypeDef hadc1; + UART_HandleTypeDef huart2; /* Definitions for mainTask */ osThreadId_t mainTaskHandle; -const osThreadAttr_t mainTask_attributes = { .name = "mainTask", .stack_size = - 128 * 4, .priority = (osPriority_t) osPriorityNormal, }; +const osThreadAttr_t mainTask_attributes = { + .name = "mainTask", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityNormal, +}; /* Definitions for doorHandler */ osThreadId_t doorHandlerHandle; -const osThreadAttr_t doorHandler_attributes = { .name = "doorHandler", - .stack_size = 128 * 4, .priority = (osPriority_t) osPriorityLow, }; +const osThreadAttr_t doorHandler_attributes = { + .name = "doorHandler", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityHigh, +}; +/* Definitions for StateSendTask */ +osThreadId_t StateSendTaskHandle; +const osThreadAttr_t StateSendTask_attributes = { + .name = "StateSendTask", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityLow, +}; +/* Definitions for ADCReqTask */ +osThreadId_t ADCReqTaskHandle; +const osThreadAttr_t ADCReqTask_attributes = { + .name = "ADCReqTask", + .stack_size = 128 * 4, + .priority = (osPriority_t) osPriorityLow, +}; /* USER CODE BEGIN PV */ uint8_t uart_buffer[10]; uint8_t uart_index = 0; @@ -76,14 +98,20 @@ bool door_lock_state_command = false; bool door_lock_waiting = false; bool alarm_active = false; +bool scan_active = false; +uint16_t adc_val = 0; +int flag_uart_cmd = 99; /* USER CODE END PV */ /* Private function prototypes -----------------------------------------------*/ void SystemClock_Config(void); static void MX_GPIO_Init(void); static void MX_USART2_UART_Init(void); +static void MX_ADC1_Init(void); void StartMainTask(void *argument); void startDoorHandleTask(void *argument); +void StartStateSendTask(void *argument); +void StartADCReqTask(void *argument); /* USER CODE BEGIN PFP */ @@ -91,205 +119,273 @@ void startDoorHandleTask(void *argument); /* Private user code ---------------------------------------------------------*/ /* USER CODE BEGIN 0 */ - +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { + adc_val = HAL_ADC_GetValue(&hadc1); + scan_active = adc_val < 1000; +} /* USER CODE END 0 */ /** - * @brief The application entry point. - * @retval int - */ -int main(void) { - /* USER CODE BEGIN 1 */ + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ - /* USER CODE END 1 */ + /* USER CODE END 1 */ - /* MCU Configuration--------------------------------------------------------*/ + /* MCU Configuration--------------------------------------------------------*/ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); - /* USER CODE BEGIN Init */ + /* USER CODE BEGIN Init */ - /* USER CODE END Init */ + /* USER CODE END Init */ - /* Configure the system clock */ - SystemClock_Config(); + /* Configure the system clock */ + SystemClock_Config(); - /* USER CODE BEGIN SysInit */ + /* USER CODE BEGIN SysInit */ - /* USER CODE END SysInit */ + /* USER CODE END SysInit */ - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_USART2_UART_Init(); - /* USER CODE BEGIN 2 */ + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART2_UART_Init(); + MX_ADC1_Init(); + /* USER CODE BEGIN 2 */ memset(uart_buffer, 0, 10); - /* USER CODE END 2 */ + /* USER CODE END 2 */ - /* Init scheduler */ - osKernelInitialize(); + /* Init scheduler */ + osKernelInitialize(); - /* USER CODE BEGIN RTOS_MUTEX */ + /* USER CODE BEGIN RTOS_MUTEX */ /* add mutexes, ... */ - /* USER CODE END RTOS_MUTEX */ + /* USER CODE END RTOS_MUTEX */ - /* USER CODE BEGIN RTOS_SEMAPHORES */ + /* USER CODE BEGIN RTOS_SEMAPHORES */ /* add semaphores, ... */ - /* USER CODE END RTOS_SEMAPHORES */ + /* USER CODE END RTOS_SEMAPHORES */ - /* USER CODE BEGIN RTOS_TIMERS */ + /* USER CODE BEGIN RTOS_TIMERS */ /* start timers, add new ones, ... */ - /* USER CODE END RTOS_TIMERS */ + /* USER CODE END RTOS_TIMERS */ - /* USER CODE BEGIN RTOS_QUEUES */ + /* USER CODE BEGIN RTOS_QUEUES */ /* add queues, ... */ - /* USER CODE END RTOS_QUEUES */ + /* USER CODE END RTOS_QUEUES */ - /* Create the thread(s) */ - /* creation of mainTask */ - mainTaskHandle = osThreadNew(StartMainTask, NULL, &mainTask_attributes); + /* Create the thread(s) */ + /* creation of mainTask */ + mainTaskHandle = osThreadNew(StartMainTask, NULL, &mainTask_attributes); - /* creation of doorHandler */ - doorHandlerHandle = osThreadNew(startDoorHandleTask, NULL, - &doorHandler_attributes); + /* creation of doorHandler */ + doorHandlerHandle = osThreadNew(startDoorHandleTask, NULL, &doorHandler_attributes); - /* USER CODE BEGIN RTOS_THREADS */ + /* creation of StateSendTask */ + StateSendTaskHandle = osThreadNew(StartStateSendTask, NULL, &StateSendTask_attributes); + + /* creation of ADCReqTask */ + ADCReqTaskHandle = osThreadNew(StartADCReqTask, NULL, &ADCReqTask_attributes); + + /* USER CODE BEGIN RTOS_THREADS */ /* add threads, ... */ - /* USER CODE END RTOS_THREADS */ + /* USER CODE END RTOS_THREADS */ - /* USER CODE BEGIN RTOS_EVENTS */ + /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ - /* USER CODE END RTOS_EVENTS */ + /* USER CODE END RTOS_EVENTS */ - /* Start scheduler */ - osKernelStart(); + /* Start scheduler */ + osKernelStart(); - /* We should never get here as control is now taken by the scheduler */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ + /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ while (1) { } - /* USER CODE END WHILE */ + /* USER CODE END WHILE */ - /* USER CODE BEGIN 3 */ + /* USER CODE BEGIN 3 */ - /* USER CODE END 3 */ + /* USER CODE END 3 */ } /** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) { - RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; - RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - /** Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 16; - RCC_OscInitStruct.PLL.PLLN = 336; - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; - RCC_OscInitStruct.PLL.PLLQ = 4; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { - Error_Handler(); - } + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 16; + RCC_OscInitStruct.PLL.PLLN = 336; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; + RCC_OscInitStruct.PLL.PLLQ = 4; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - Error_Handler(); - } + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } } /** - * @brief USART2 Initialization Function - * @param None - * @retval None - */ -static void MX_USART2_UART_Init(void) { + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ - /* USER CODE BEGIN USART2_Init 0 */ + /* USER CODE BEGIN ADC1_Init 0 */ - /* USER CODE END USART2_Init 0 */ + /* USER CODE END ADC1_Init 0 */ - /* USER CODE BEGIN USART2_Init 1 */ + ADC_ChannelConfTypeDef sConfig = {0}; - /* USER CODE END USART2_Init 1 */ - huart2.Instance = USART2; - huart2.Init.BaudRate = 9600; - huart2.Init.WordLength = UART_WORDLENGTH_8B; - huart2.Init.StopBits = UART_STOPBITS_1; - huart2.Init.Parity = UART_PARITY_NONE; - huart2.Init.Mode = UART_MODE_TX_RX; - huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart2.Init.OverSampling = UART_OVERSAMPLING_16; - if (HAL_UART_Init(&huart2) != HAL_OK) { - Error_Handler(); - } - /* USER CODE BEGIN USART2_Init 2 */ + /* USER CODE BEGIN ADC1_Init 1 */ - /* USER CODE END USART2_Init 2 */ + /* USER CODE END ADC1_Init 1 */ + + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + hadc1.Init.ScanConvMode = DISABLE; + hadc1.Init.ContinuousConvMode = DISABLE; + hadc1.Init.DiscontinuousConvMode = DISABLE; + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + hadc1.Init.NbrOfConversion = 1; + hadc1.Init.DMAContinuousRequests = DISABLE; + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + if (HAL_ADC_Init(&hadc1) != HAL_OK) + { + Error_Handler(); + } + + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_1; + sConfig.Rank = 1; + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN ADC1_Init 2 */ + + /* USER CODE END ADC1_Init 2 */ } /** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) { - GPIO_InitTypeDef GPIO_InitStruct = { 0 }; - /* USER CODE BEGIN MX_GPIO_Init_1 */ - /* USER CODE END MX_GPIO_Init_1 */ + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); + /* USER CODE BEGIN USART2_Init 0 */ - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOA, LD2_Pin | Door_Lock_Pin, GPIO_PIN_RESET); + /* USER CODE END USART2_Init 0 */ - /*Configure GPIO pin : B1_Pin */ - GPIO_InitStruct.Pin = B1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); + /* USER CODE BEGIN USART2_Init 1 */ - /*Configure GPIO pins : LD2_Pin Door_Lock_Pin */ - GPIO_InitStruct.Pin = LD2_Pin | Door_Lock_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + huart2.Init.BaudRate = 9600; + huart2.Init.WordLength = UART_WORDLENGTH_8B; + huart2.Init.StopBits = UART_STOPBITS_1; + huart2.Init.Parity = UART_PARITY_NONE; + huart2.Init.Mode = UART_MODE_TX_RX; + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart2) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART2_Init 2 */ - /*Configure GPIO pin : Door_Sensor_Pin */ - GPIO_InitStruct.Pin = Door_Sensor_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_PULLUP; - HAL_GPIO_Init(Door_Sensor_GPIO_Port, &GPIO_InitStruct); + /* USER CODE END USART2_Init 2 */ - /* USER CODE BEGIN MX_GPIO_Init_2 */ - /* USER CODE END MX_GPIO_Init_2 */ +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOH_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, LD2_Pin|Door_Lock_Pin, GPIO_PIN_RESET); + + /*Configure GPIO pin : B1_Pin */ + GPIO_InitStruct.Pin = B1_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); + + /*Configure GPIO pins : LD2_Pin Door_Lock_Pin */ + GPIO_InitStruct.Pin = LD2_Pin|Door_Lock_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /*Configure GPIO pin : Door_Sensor_Pin */ + GPIO_InitStruct.Pin = Door_Sensor_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLUP; + HAL_GPIO_Init(Door_Sensor_GPIO_Port, &GPIO_InitStruct); + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ } /* USER CODE BEGIN 4 */ @@ -303,8 +399,9 @@ static void MX_GPIO_Init(void) { * @retval None */ /* USER CODE END Header_StartMainTask */ -void StartMainTask(void *argument) { - /* USER CODE BEGIN 5 */ +void StartMainTask(void *argument) +{ + /* USER CODE BEGIN 5 */ memset(uart_buffer, 0, 10); /* USER CODE END 2 */ @@ -312,12 +409,12 @@ void StartMainTask(void *argument) { /* USER CODE BEGIN WHILE */ while (1) { - if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 1000) + if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 100) == HAL_OK) { uart_index++; if (uart_buffer[uart_index - 1] == 0xFF) { if (uart_index > 1) { - //Command Internal LED + // Command Internal LED if (uart_buffer[0] == 0x00) { HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, uart_buffer[1]); } @@ -326,9 +423,13 @@ void StartMainTask(void *argument) { uint8_t payload[3] = { 0x01, door_state, 0xFF }; HAL_UART_Transmit(&huart2, payload, 3, 1500); } - // + // Set Door Lock State else if (uart_buffer[0] == 0x02) { door_lock_state_command = uart_buffer[1]; + // Get Current Scan Active State + } else if (uart_buffer[0] == 0x03) { + uint8_t payload[3] = { 0x02, scan_active, 0xFF }; + HAL_UART_Transmit(&huart2, payload, 3, 1500); } } uart_index = 0; @@ -340,7 +441,7 @@ void StartMainTask(void *argument) { } vTaskDelay(1); } - /* USER CODE END 5 */ + /* USER CODE END 5 */ } /* USER CODE BEGIN Header_startDoorHandleTask */ @@ -350,8 +451,9 @@ void StartMainTask(void *argument) { * @retval None */ /* USER CODE END Header_startDoorHandleTask */ -void startDoorHandleTask(void *argument) { - /* USER CODE BEGIN startDoorHandleTask */ +void startDoorHandleTask(void *argument) +{ + /* USER CODE BEGIN startDoorHandleTask */ /* Infinite loop */ for (;;) { door_state = HAL_GPIO_ReadPin(DOOR_SENSOR_BANK, DOOR_SENSOR_PIN); @@ -385,7 +487,7 @@ void startDoorHandleTask(void *argument) { door_lock_waiting = false; } } - if(!door_lock_state_command && door_lock_waiting) { + if (!door_lock_state_command && door_lock_waiting) { door_lock_waiting = false; } if (alarm_active && !door_lock_state_command) { @@ -396,44 +498,85 @@ void startDoorHandleTask(void *argument) { HAL_GPIO_WritePin(ALARM_BANK, ALARM_PIN, 1); alarm_active = true; } - //HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, uart_buffer[1]); vTaskDelay(50); } - /* USER CODE END startDoorHandleTask */ + /* USER CODE END startDoorHandleTask */ } +/* USER CODE BEGIN Header_StartStateSendTask */ /** - * @brief Period elapsed callback in non blocking mode - * @note This function is called when TIM1 interrupt took place, inside - * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param htim : TIM handle + * @brief Function implementing the StateSendTask thread. + * @param argument: Not used * @retval None */ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { - /* USER CODE BEGIN Callback 0 */ - - /* USER CODE END Callback 0 */ - if (htim->Instance == TIM1) { - HAL_IncTick(); +/* USER CODE END Header_StartStateSendTask */ +void StartStateSendTask(void *argument) +{ + /* USER CODE BEGIN StartStateSendTask */ + /* Infinite loop */ + for (;;) { + uint8_t payload1[3] = { 0x01, door_state, 0xFF }; + HAL_UART_Transmit(&huart2, payload1, 3, 1000); + uint8_t payload2[3] = { 0x02, scan_active, 0xFF }; + HAL_UART_Transmit(&huart2, payload2, 3, 1000); + osDelay(200); } - /* USER CODE BEGIN Callback 1 */ + /* USER CODE END StartStateSendTask */ +} - /* USER CODE END Callback 1 */ +/* USER CODE BEGIN Header_StartADCReqTask */ +/** +* @brief Function implementing the ADCReqTask thread. +* @param argument: Not used +* @retval None +*/ +/* USER CODE END Header_StartADCReqTask */ +void StartADCReqTask(void *argument) +{ + /* USER CODE BEGIN StartADCReqTask */ + /* Infinite loop */ + for(;;) + { + HAL_ADC_Start_IT(&hadc1); + osDelay(500); + } + /* USER CODE END StartADCReqTask */ } /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) { - /* USER CODE BEGIN Error_Handler_Debug */ + * @brief Period elapsed callback in non blocking mode + * @note This function is called when TIM1 interrupt took place, inside + * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM1) { + HAL_IncTick(); + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ +} + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { } - /* USER CODE END Error_Handler_Debug */ + /* USER CODE END Error_Handler_Debug */ } #ifdef USE_FULL_ASSERT diff --git a/access_control_stm32/Core/Src/stm32f4xx_hal_msp.c b/access_control_stm32/Core/Src/stm32f4xx_hal_msp.c index c5167b8..d3f7e55 100644 --- a/access_control_stm32/Core/Src/stm32f4xx_hal_msp.c +++ b/access_control_stm32/Core/Src/stm32f4xx_hal_msp.c @@ -79,6 +79,72 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } +/** +* @brief ADC MSP Initialization +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + GPIO_InitTypeDef GPIO_InitStruct = {0}; + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + + __HAL_RCC_GPIOA_CLK_ENABLE(); + /**ADC1 GPIO Configuration + PA1 ------> ADC1_IN1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + GPIO_InitStruct.Pull = GPIO_NOPULL; + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + /* ADC1 interrupt Init */ + HAL_NVIC_SetPriority(ADC_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(ADC_IRQn); + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + +/** +* @brief ADC MSP De-Initialization +* This function freeze the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + if(hadc->Instance==ADC1) + { + /* USER CODE BEGIN ADC1_MspDeInit 0 */ + + /* USER CODE END ADC1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_ADC1_CLK_DISABLE(); + + /**ADC1 GPIO Configuration + PA1 ------> ADC1_IN1 + */ + HAL_GPIO_DeInit(GPIOA, GPIO_PIN_1); + + /* ADC1 interrupt DeInit */ + HAL_NVIC_DisableIRQ(ADC_IRQn); + /* USER CODE BEGIN ADC1_MspDeInit 1 */ + + /* USER CODE END ADC1_MspDeInit 1 */ + } + +} + /** * @brief UART MSP Initialization * This function configures the hardware resources used in this example diff --git a/access_control_stm32/Core/Src/stm32f4xx_it.c b/access_control_stm32/Core/Src/stm32f4xx_it.c index a32378e..b79d33e 100644 --- a/access_control_stm32/Core/Src/stm32f4xx_it.c +++ b/access_control_stm32/Core/Src/stm32f4xx_it.c @@ -55,6 +55,7 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ +extern ADC_HandleTypeDef hadc1; extern TIM_HandleTypeDef htim1; /* USER CODE BEGIN EV */ @@ -159,6 +160,20 @@ void DebugMon_Handler(void) /* please refer to the startup file (startup_stm32f4xx.s). */ /******************************************************************************/ +/** + * @brief This function handles ADC1 global interrupt. + */ +void ADC_IRQHandler(void) +{ + /* USER CODE BEGIN ADC_IRQn 0 */ + + /* USER CODE END ADC_IRQn 0 */ + HAL_ADC_IRQHandler(&hadc1); + /* USER CODE BEGIN ADC_IRQn 1 */ + + /* USER CODE END ADC_IRQn 1 */ +} + /** * @brief This function handles TIM1 update interrupt and TIM10 global interrupt. */ diff --git a/access_control_stm32/Debug/Core/Src/freertos.d b/access_control_stm32/Debug/Core/Src/freertos.d index 5df50d3..0ee2062 100644 --- a/access_control_stm32/Debug/Core/Src/freertos.d +++ b/access_control_stm32/Debug/Core/Src/freertos.d @@ -28,6 +28,9 @@ Core/Src/freertos.o: ../Core/Src/freertos.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -66,6 +69,9 @@ Core/Src/freertos.o: ../Core/Src/freertos.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Core/Src/freertos.o b/access_control_stm32/Debug/Core/Src/freertos.o index 4bbca30..01c6870 100644 Binary files a/access_control_stm32/Debug/Core/Src/freertos.o and b/access_control_stm32/Debug/Core/Src/freertos.o differ diff --git a/access_control_stm32/Debug/Core/Src/main.cyclo b/access_control_stm32/Debug/Core/Src/main.cyclo index 81a251f..d901855 100644 --- a/access_control_stm32/Debug/Core/Src/main.cyclo +++ b/access_control_stm32/Debug/Core/Src/main.cyclo @@ -1,8 +1,12 @@ -../Core/Src/main.c:101:5:main 1 -../Core/Src/main.c:183:6:SystemClock_Config 3 -../Core/Src/main.c:227:13:MX_USART2_UART_Init 2 -../Core/Src/main.c:258:13:MX_GPIO_Init 1 -../Core/Src/main.c:306:6:StartMainTask 8 -../Core/Src/main.c:353:6:startDoorHandleTask 14 -../Core/Src/main.c:414:6:HAL_TIM_PeriodElapsedCallback 2 -../Core/Src/main.c:430:6:Error_Handler 1 +../Core/Src/main.c:122:6:HAL_ADC_ConvCpltCallback 1 +../Core/Src/main.c:132:5:main 1 +../Core/Src/main.c:221:6:SystemClock_Config 3 +../Core/Src/main.c:268:13:MX_ADC1_Init 3 +../Core/Src/main.c:320:13:MX_USART2_UART_Init 2 +../Core/Src/main.c:353:13:MX_GPIO_Init 1 +../Core/Src/main.c:402:6:StartMainTask 9 +../Core/Src/main.c:454:6:startDoorHandleTask 14 +../Core/Src/main.c:514:6:StartStateSendTask 1 +../Core/Src/main.c:535:6:StartADCReqTask 1 +../Core/Src/main.c:555:6:HAL_TIM_PeriodElapsedCallback 2 +../Core/Src/main.c:572:6:Error_Handler 1 diff --git a/access_control_stm32/Debug/Core/Src/main.d b/access_control_stm32/Debug/Core/Src/main.d index a94f2d8..7e8cac0 100644 --- a/access_control_stm32/Debug/Core/Src/main.d +++ b/access_control_stm32/Debug/Core/Src/main.d @@ -19,6 +19,9 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -59,6 +62,9 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Core/Src/main.o b/access_control_stm32/Debug/Core/Src/main.o index cff9ca3..d6d6242 100644 Binary files a/access_control_stm32/Debug/Core/Src/main.o and b/access_control_stm32/Debug/Core/Src/main.o differ diff --git a/access_control_stm32/Debug/Core/Src/main.su b/access_control_stm32/Debug/Core/Src/main.su index 159789e..ae04708 100644 --- a/access_control_stm32/Debug/Core/Src/main.su +++ b/access_control_stm32/Debug/Core/Src/main.su @@ -1,8 +1,12 @@ -../Core/Src/main.c:101:5:main 8 static -../Core/Src/main.c:183:6:SystemClock_Config 88 static -../Core/Src/main.c:227:13:MX_USART2_UART_Init 8 static -../Core/Src/main.c:258:13:MX_GPIO_Init 48 static -../Core/Src/main.c:306:6:StartMainTask 24 static -../Core/Src/main.c:353:6:startDoorHandleTask 16 static -../Core/Src/main.c:414:6:HAL_TIM_PeriodElapsedCallback 16 static -../Core/Src/main.c:430:6:Error_Handler 4 static,ignoring_inline_asm +../Core/Src/main.c:122:6:HAL_ADC_ConvCpltCallback 16 static +../Core/Src/main.c:132:5:main 8 static +../Core/Src/main.c:221:6:SystemClock_Config 88 static +../Core/Src/main.c:268:13:MX_ADC1_Init 24 static +../Core/Src/main.c:320:13:MX_USART2_UART_Init 8 static +../Core/Src/main.c:353:13:MX_GPIO_Init 48 static +../Core/Src/main.c:402:6:StartMainTask 24 static +../Core/Src/main.c:454:6:startDoorHandleTask 16 static +../Core/Src/main.c:514:6:StartStateSendTask 24 static +../Core/Src/main.c:535:6:StartADCReqTask 16 static +../Core/Src/main.c:555:6:HAL_TIM_PeriodElapsedCallback 16 static +../Core/Src/main.c:572:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.cyclo b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.cyclo index f785e20..a27ff23 100644 --- a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.cyclo +++ b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.cyclo @@ -1,3 +1,5 @@ ../Core/Src/stm32f4xx_hal_msp.c:64:6:HAL_MspInit 1 -../Core/Src/stm32f4xx_hal_msp.c:88:6:HAL_UART_MspInit 2 -../Core/Src/stm32f4xx_hal_msp.c:124:6:HAL_UART_MspDeInit 2 +../Core/Src/stm32f4xx_hal_msp.c:88:6:HAL_ADC_MspInit 2 +../Core/Src/stm32f4xx_hal_msp.c:124:6:HAL_ADC_MspDeInit 2 +../Core/Src/stm32f4xx_hal_msp.c:154:6:HAL_UART_MspInit 2 +../Core/Src/stm32f4xx_hal_msp.c:190:6:HAL_UART_MspDeInit 2 diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.d b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.d index 6d675bc..e95519d 100644 --- a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.d +++ b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.d @@ -19,6 +19,9 @@ Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Core/Src/stm32f4xx_hal_msp.o: ../Core/Src/stm32f4xx_hal_msp.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.o b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.o index 69ec17d..3e852fc 100644 Binary files a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.o and b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.o differ diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.su b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.su index 79f4ef7..6a40c6e 100644 --- a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.su +++ b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_msp.su @@ -1,3 +1,5 @@ ../Core/Src/stm32f4xx_hal_msp.c:64:6:HAL_MspInit 16 static -../Core/Src/stm32f4xx_hal_msp.c:88:6:HAL_UART_MspInit 48 static -../Core/Src/stm32f4xx_hal_msp.c:124:6:HAL_UART_MspDeInit 16 static +../Core/Src/stm32f4xx_hal_msp.c:88:6:HAL_ADC_MspInit 48 static +../Core/Src/stm32f4xx_hal_msp.c:124:6:HAL_ADC_MspDeInit 16 static +../Core/Src/stm32f4xx_hal_msp.c:154:6:HAL_UART_MspInit 48 static +../Core/Src/stm32f4xx_hal_msp.c:190:6:HAL_UART_MspDeInit 16 static diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d index f9a6044..4412c07 100644 --- a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d +++ b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_timebase_tim.d @@ -20,6 +20,9 @@ Core/Src/stm32f4xx_hal_timebase_tim.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Core/Src/stm32f4xx_hal_timebase_tim.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o index 31ef9e9..c84e571 100644 Binary files a/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o and b/access_control_stm32/Debug/Core/Src/stm32f4xx_hal_timebase_tim.o differ diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_it.cyclo b/access_control_stm32/Debug/Core/Src/stm32f4xx_it.cyclo index 8080909..d4da44e 100644 --- a/access_control_stm32/Debug/Core/Src/stm32f4xx_it.cyclo +++ b/access_control_stm32/Debug/Core/Src/stm32f4xx_it.cyclo @@ -1,7 +1,8 @@ -../Core/Src/stm32f4xx_it.c:70:6:NMI_Handler 1 -../Core/Src/stm32f4xx_it.c:85:6:HardFault_Handler 1 -../Core/Src/stm32f4xx_it.c:100:6:MemManage_Handler 1 -../Core/Src/stm32f4xx_it.c:115:6:BusFault_Handler 1 -../Core/Src/stm32f4xx_it.c:130:6:UsageFault_Handler 1 -../Core/Src/stm32f4xx_it.c:145:6:DebugMon_Handler 1 -../Core/Src/stm32f4xx_it.c:165:6:TIM1_UP_TIM10_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:71:6:NMI_Handler 1 +../Core/Src/stm32f4xx_it.c:86:6:HardFault_Handler 1 +../Core/Src/stm32f4xx_it.c:101:6:MemManage_Handler 1 +../Core/Src/stm32f4xx_it.c:116:6:BusFault_Handler 1 +../Core/Src/stm32f4xx_it.c:131:6:UsageFault_Handler 1 +../Core/Src/stm32f4xx_it.c:146:6:DebugMon_Handler 1 +../Core/Src/stm32f4xx_it.c:166:6:ADC_IRQHandler 1 +../Core/Src/stm32f4xx_it.c:180:6:TIM1_UP_TIM10_IRQHandler 1 diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_it.d b/access_control_stm32/Debug/Core/Src/stm32f4xx_it.d index c7516f9..0095f3c 100644 --- a/access_control_stm32/Debug/Core/Src/stm32f4xx_it.d +++ b/access_control_stm32/Debug/Core/Src/stm32f4xx_it.d @@ -19,6 +19,9 @@ Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -49,6 +52,9 @@ Core/Src/stm32f4xx_it.o: ../Core/Src/stm32f4xx_it.c ../Core/Inc/main.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_it.o b/access_control_stm32/Debug/Core/Src/stm32f4xx_it.o index 307bc0f..b7ba8b3 100644 Binary files a/access_control_stm32/Debug/Core/Src/stm32f4xx_it.o and b/access_control_stm32/Debug/Core/Src/stm32f4xx_it.o differ diff --git a/access_control_stm32/Debug/Core/Src/stm32f4xx_it.su b/access_control_stm32/Debug/Core/Src/stm32f4xx_it.su index 6c2f09c..05bcfda 100644 --- a/access_control_stm32/Debug/Core/Src/stm32f4xx_it.su +++ b/access_control_stm32/Debug/Core/Src/stm32f4xx_it.su @@ -1,7 +1,8 @@ -../Core/Src/stm32f4xx_it.c:70:6:NMI_Handler 4 static -../Core/Src/stm32f4xx_it.c:85:6:HardFault_Handler 4 static -../Core/Src/stm32f4xx_it.c:100:6:MemManage_Handler 4 static -../Core/Src/stm32f4xx_it.c:115:6:BusFault_Handler 4 static -../Core/Src/stm32f4xx_it.c:130:6:UsageFault_Handler 4 static -../Core/Src/stm32f4xx_it.c:145:6:DebugMon_Handler 4 static -../Core/Src/stm32f4xx_it.c:165:6:TIM1_UP_TIM10_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:71:6:NMI_Handler 4 static +../Core/Src/stm32f4xx_it.c:86:6:HardFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:101:6:MemManage_Handler 4 static +../Core/Src/stm32f4xx_it.c:116:6:BusFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:131:6:UsageFault_Handler 4 static +../Core/Src/stm32f4xx_it.c:146:6:DebugMon_Handler 4 static +../Core/Src/stm32f4xx_it.c:166:6:ADC_IRQHandler 8 static +../Core/Src/stm32f4xx_it.c:180:6:TIM1_UP_TIM10_IRQHandler 8 static diff --git a/access_control_stm32/Debug/Core/Src/system_stm32f4xx.d b/access_control_stm32/Debug/Core/Src/system_stm32f4xx.d index f9fb14e..a82fd30 100644 --- a/access_control_stm32/Debug/Core/Src/system_stm32f4xx.d +++ b/access_control_stm32/Debug/Core/Src/system_stm32f4xx.d @@ -19,6 +19,9 @@ Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -47,6 +50,9 @@ Core/Src/system_stm32f4xx.o: ../Core/Src/system_stm32f4xx.c \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Core/Src/system_stm32f4xx.o b/access_control_stm32/Debug/Core/Src/system_stm32f4xx.o index 9822b46..5c65172 100644 Binary files a/access_control_stm32/Debug/Core/Src/system_stm32f4xx.o and b/access_control_stm32/Debug/Core/Src/system_stm32f4xx.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d index ab0d97d..7da50ad 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o index 0c4bc23..7eea546 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.cyclo b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.cyclo new file mode 100644 index 0000000..5e421af --- /dev/null +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.cyclo @@ -0,0 +1,26 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:311:19:HAL_ADC_Init 4 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:405:19:HAL_ADC_DeInit 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:662:13:HAL_ADC_MspInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:677:13:HAL_ADC_MspDeInit 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:716:19:HAL_ADC_Start 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:839:19:HAL_ADC_Stop 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:882:19:HAL_ADC_PollForConversion 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:971:19:HAL_ADC_PollForEvent 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1037:19:HAL_ADC_Start_IT 11 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1162:19:HAL_ADC_Stop_IT 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1199:6:HAL_ADC_IRQHandler 24 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1364:19:HAL_ADC_Start_DMA 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1512:19:HAL_ADC_Stop_DMA 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1568:10:HAL_ADC_GetValue 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1580:13:HAL_ADC_ConvCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1595:13:HAL_ADC_ConvHalfCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1610:13:HAL_ADC_LevelOutOfWindowCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1631:13:HAL_ADC_ErrorCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1669:19:HAL_ADC_ConfigChannel 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1792:19:HAL_ADC_AnalogWDGConfig 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1874:10:HAL_ADC_GetState 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1886:10:HAL_ADC_GetError 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1906:13:ADC_Init 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1994:13:ADC_DMAConvCplt 8 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:2063:13:ADC_DMAHalfConvCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:2080:13:ADC_DMAError 1 diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.d new file mode 100644 index 0000000..ce94231 --- /dev/null +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.d @@ -0,0 +1,64 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o new file mode 100644 index 0000000..9d74579 Binary files /dev/null and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.su b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.su new file mode 100644 index 0000000..92b54b5 --- /dev/null +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.su @@ -0,0 +1,26 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:311:19:HAL_ADC_Init 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:405:19:HAL_ADC_DeInit 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:662:13:HAL_ADC_MspInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:677:13:HAL_ADC_MspDeInit 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:716:19:HAL_ADC_Start 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:839:19:HAL_ADC_Stop 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:882:19:HAL_ADC_PollForConversion 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:971:19:HAL_ADC_PollForEvent 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1037:19:HAL_ADC_Start_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1162:19:HAL_ADC_Stop_IT 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1199:6:HAL_ADC_IRQHandler 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1364:19:HAL_ADC_Start_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1512:19:HAL_ADC_Stop_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1568:10:HAL_ADC_GetValue 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1580:13:HAL_ADC_ConvCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1595:13:HAL_ADC_ConvHalfCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1610:13:HAL_ADC_LevelOutOfWindowCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1631:13:HAL_ADC_ErrorCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1669:19:HAL_ADC_ConfigChannel 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1792:19:HAL_ADC_AnalogWDGConfig 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1874:10:HAL_ADC_GetState 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1886:10:HAL_ADC_GetError 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1906:13:ADC_Init 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:1994:13:ADC_DMAConvCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:2063:13:ADC_DMAHalfConvCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c:2080:13:ADC_DMAError 24 static diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.cyclo b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.cyclo new file mode 100644 index 0000000..7896c2a --- /dev/null +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.cyclo @@ -0,0 +1,15 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:146:19:HAL_ADCEx_InjectedStart 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:249:19:HAL_ADCEx_InjectedStart_IT 12 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:360:19:HAL_ADCEx_InjectedStop 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:414:19:HAL_ADCEx_InjectedPollForConversion 13 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:485:19:HAL_ADCEx_InjectedStop_IT 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:547:10:HAL_ADCEx_InjectedGetValue 5 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:598:19:HAL_ADCEx_MultiModeStart_DMA 9 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:725:19:HAL_ADCEx_MultiModeStop_DMA 3 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:778:10:HAL_ADCEx_MultiModeGetValue 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:797:13:HAL_ADCEx_InjectedConvCpltCallback 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:814:19:HAL_ADCEx_InjectedConfigChannel 15 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:978:19:HAL_ADCEx_MultiModeConfigChannel 2 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:1025:13:ADC_MultiModeDMAConvCplt 7 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:1078:13:ADC_MultiModeDMAHalfConvCplt 1 +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:1091:13:ADC_MultiModeDMAError 1 diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.d new file mode 100644 index 0000000..c131f88 --- /dev/null +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.d @@ -0,0 +1,64 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h \ + ../Core/Inc/stm32f4xx_hal_conf.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h: +../Core/Inc/stm32f4xx_hal_conf.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f411xe.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_exti.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_tim_ex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o new file mode 100644 index 0000000..66e3a3d Binary files /dev/null and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.su b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.su new file mode 100644 index 0000000..e39f7c7 --- /dev/null +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.su @@ -0,0 +1,15 @@ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:146:19:HAL_ADCEx_InjectedStart 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:249:19:HAL_ADCEx_InjectedStart_IT 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:360:19:HAL_ADCEx_InjectedStop 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:414:19:HAL_ADCEx_InjectedPollForConversion 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:485:19:HAL_ADCEx_InjectedStop_IT 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:547:10:HAL_ADCEx_InjectedGetValue 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:598:19:HAL_ADCEx_MultiModeStart_DMA 32 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:725:19:HAL_ADCEx_MultiModeStop_DMA 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:778:10:HAL_ADCEx_MultiModeGetValue 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:797:13:HAL_ADCEx_InjectedConvCpltCallback 16 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:814:19:HAL_ADCEx_InjectedConfigChannel 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:978:19:HAL_ADCEx_MultiModeConfigChannel 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:1025:13:ADC_MultiModeDMAConvCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:1078:13:ADC_MultiModeDMAHalfConvCplt 24 static +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c:1091:13:ADC_MultiModeDMAError 24 static diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d index c7c005a..50d8940 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o index ddececa..d7f7174 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d index ec0585d..3b9cb58 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o index 22d690c..3266d5f 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d index baf7e9e..099e9c9 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o index a2a4fd7..46ae57c 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d index add2ca7..b509a7a 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o index 2428fed..0495b67 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d index c5ec984..f66d295 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o index bb215cc..63e1dc5 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d index cc47320..88bd165 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o index 19be877..42b35b6 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d index 0143496..06791c2 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o index 991201e..3fa7fdb 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d index 5030a1d..d641a60 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o index 14bab4b..349fcc0 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d index 99b54e9..6d37d04 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o index 6080c65..94b9306 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d index 14135eb..5d1419f 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o index 9fc3f6b..2bb778e 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d index 6c34a82..e98dccb 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o index e12a376..03b32cb 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d index 8517dd6..4415804 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o index 544c494..00e00fe 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d index 92fc295..54c3b26 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o index 9f37dbb..04f60c1 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d index 254b2e1..e7a578f 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o index 31c3888..32a6e87 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d index f4d5e10..d3cf6b3 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d @@ -20,6 +20,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -48,6 +51,9 @@ Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o index caed59d..181d292 100644 Binary files a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.cyclo b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.d b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.d new file mode 100644 index 0000000..b7bd6f6 --- /dev/null +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.d @@ -0,0 +1,2 @@ +Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o: \ + ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o new file mode 100644 index 0000000..24ac672 Binary files /dev/null and b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o differ diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.su b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.su new file mode 100644 index 0000000..e69de29 diff --git a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk index 989dd9c..4d122b1 100644 --- a/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk +++ b/access_control_stm32/Debug/Drivers/STM32F4xx_HAL_Driver/Src/subdir.mk @@ -6,6 +6,8 @@ # Add inputs and outputs from these tool invocations to the build variables C_SRCS += \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.c \ @@ -20,10 +22,13 @@ C_SRCS += \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.c \ ../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.c \ -../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.c \ +../Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c OBJS += \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o \ @@ -38,10 +43,13 @@ OBJS += \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o C_DEPS += \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d \ @@ -56,7 +64,8 @@ C_DEPS += \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d \ ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d \ -./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d \ +./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.d # Each subdirectory must supply rules for building sources it contributes @@ -66,7 +75,7 @@ Drivers/STM32F4xx_HAL_Driver/Src/%.o Drivers/STM32F4xx_HAL_Driver/Src/%.su Drive clean: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src: - -$(RM) ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su + -$(RM) ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.su ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.cyclo ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.su .PHONY: clean-Drivers-2f-STM32F4xx_HAL_Driver-2f-Src diff --git a/access_control_stm32/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d b/access_control_stm32/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d index bf00f14..570dc17 100644 --- a/access_control_stm32/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d +++ b/access_control_stm32/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.d @@ -38,6 +38,9 @@ Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h \ + ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h \ @@ -84,6 +87,9 @@ Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o: \ ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_cortex.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h: +../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ex.h: ../Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_flash_ramfunc.h: diff --git a/access_control_stm32/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o b/access_control_stm32/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o index f53b24a..f79c82e 100644 Binary files a/access_control_stm32/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o and b/access_control_stm32/Debug/Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o differ diff --git a/access_control_stm32/Debug/access_control_stm32.elf b/access_control_stm32/Debug/access_control_stm32.elf index ef6d609..cdba186 100644 Binary files a/access_control_stm32/Debug/access_control_stm32.elf and b/access_control_stm32/Debug/access_control_stm32.elf differ diff --git a/access_control_stm32/Debug/access_control_stm32.list b/access_control_stm32/Debug/access_control_stm32.list index 8afde39..d074e91 100644 --- a/access_control_stm32/Debug/access_control_stm32.list +++ b/access_control_stm32/Debug/access_control_stm32.list @@ -5,47 +5,47 @@ Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000198 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA - 1 .text 00005528 080001a0 080001a0 000101a0 2**4 + 1 .text 000060a8 080001a0 080001a0 000101a0 2**4 CONTENTS, ALLOC, LOAD, READONLY, CODE - 2 .rodata 00000090 080056c8 080056c8 000156c8 2**2 + 2 .rodata 000000f4 08006248 08006248 00016248 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 3 .ARM.extab 00000000 08005758 08005758 00020060 2**0 + 3 .ARM.extab 00000000 0800633c 0800633c 00020060 2**0 CONTENTS - 4 .ARM 00000008 08005758 08005758 00015758 2**2 + 4 .ARM 00000008 0800633c 0800633c 0001633c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA - 5 .preinit_array 00000000 08005760 08005760 00020060 2**0 + 5 .preinit_array 00000000 08006344 08006344 00020060 2**0 CONTENTS, ALLOC, LOAD, DATA - 6 .init_array 00000004 08005760 08005760 00015760 2**2 + 6 .init_array 00000004 08006344 08006344 00016344 2**2 CONTENTS, ALLOC, LOAD, DATA - 7 .fini_array 00000004 08005764 08005764 00015764 2**2 + 7 .fini_array 00000004 08006348 08006348 00016348 2**2 CONTENTS, ALLOC, LOAD, DATA - 8 .data 00000060 20000000 08005768 00020000 2**2 + 8 .data 00000060 20000000 0800634c 00020000 2**2 CONTENTS, ALLOC, LOAD, DATA - 9 .bss 00004bf4 20000060 080057c8 00020060 2**2 + 9 .bss 00004c44 20000060 080063ac 00020060 2**2 ALLOC - 10 ._user_heap_stack 00003004 20004c54 080057c8 00024c54 2**0 + 10 ._user_heap_stack 00003004 20004ca4 080063ac 00024ca4 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 00020060 2**0 CONTENTS, READONLY 12 .comment 00000043 00000000 00000000 00020090 2**0 CONTENTS, READONLY - 13 .debug_info 000175bc 00000000 00000000 000200d3 2**0 + 13 .debug_info 000197ff 00000000 00000000 000200d3 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 14 .debug_abbrev 0000318b 00000000 00000000 0003768f 2**0 + 14 .debug_abbrev 000035e1 00000000 00000000 000398d2 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 15 .debug_aranges 00001390 00000000 00000000 0003a820 2**3 + 15 .debug_aranges 00001540 00000000 00000000 0003ceb8 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS - 16 .debug_rnglists 00000f3f 00000000 00000000 0003bbb0 2**0 + 16 .debug_rnglists 00001092 00000000 00000000 0003e3f8 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 17 .debug_macro 00003557 00000000 00000000 0003caef 2**0 + 17 .debug_macro 00003b4c 00000000 00000000 0003f48a 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 18 .debug_line 00015830 00000000 00000000 00040046 2**0 + 18 .debug_line 00017e68 00000000 00000000 00042fd6 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 19 .debug_str 0009856e 00000000 00000000 00055876 2**0 + 19 .debug_str 000a457b 00000000 00000000 0005ae3e 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS - 20 .debug_frame 000055a0 00000000 00000000 000edde4 2**2 + 20 .debug_frame 00005cd8 00000000 00000000 000ff3bc 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS - 21 .debug_line_str 00000059 00000000 00000000 000f3384 2**0 + 21 .debug_line_str 00000059 00000000 00000000 00105094 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: @@ -64,7 +64,7 @@ Disassembly of section .text: 80001b6: bd10 pop {r4, pc} 80001b8: 20000060 .word 0x20000060 80001bc: 00000000 .word 0x00000000 - 80001c0: 080056b0 .word 0x080056b0 + 80001c0: 08006230 .word 0x08006230 080001c4 : 80001c4: b508 push {r3, lr} @@ -76,7 +76,7 @@ Disassembly of section .text: 80001d2: bd08 pop {r3, pc} 80001d4: 00000000 .word 0x00000000 80001d8: 20000064 .word 0x20000064 - 80001dc: 080056b0 .word 0x080056b0 + 80001dc: 08006230 .word 0x08006230 080001e0 <__aeabi_uldivmod>: 80001e0: b953 cbnz r3, 80001f8 <__aeabi_uldivmod+0x18> @@ -351,14570 +351,16624 @@ Disassembly of section .text: 80004d8: 4770 bx lr 80004da: bf00 nop -080004dc
: +080004dc : -/** - * @brief The application entry point. - * @retval int - */ -int main(void) { +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { 80004dc: b580 push {r7, lr} - 80004de: af00 add r7, sp, #0 - /* USER CODE END 1 */ + 80004de: b082 sub sp, #8 + 80004e0: af00 add r7, sp, #0 + 80004e2: 6078 str r0, [r7, #4] + adc_val = HAL_ADC_GetValue(&hadc1); + 80004e4: 480a ldr r0, [pc, #40] ; (8000510 ) + 80004e6: f000 ff57 bl 8001398 + 80004ea: 4603 mov r3, r0 + 80004ec: b29a uxth r2, r3 + 80004ee: 4b09 ldr r3, [pc, #36] ; (8000514 ) + 80004f0: 801a strh r2, [r3, #0] + scan_active = adc_val < 1000; + 80004f2: 4b08 ldr r3, [pc, #32] ; (8000514 ) + 80004f4: 881b ldrh r3, [r3, #0] + 80004f6: f240 32e7 movw r2, #999 ; 0x3e7 + 80004fa: 4293 cmp r3, r2 + 80004fc: bf94 ite ls + 80004fe: 2301 movls r3, #1 + 8000500: 2300 movhi r3, #0 + 8000502: b2da uxtb r2, r3 + 8000504: 4b04 ldr r3, [pc, #16] ; (8000518 ) + 8000506: 701a strb r2, [r3, #0] +} + 8000508: bf00 nop + 800050a: 3708 adds r7, #8 + 800050c: 46bd mov sp, r7 + 800050e: bd80 pop {r7, pc} + 8000510: 2000007c .word 0x2000007c + 8000514: 2000012e .word 0x2000012e + 8000518: 2000012d .word 0x2000012d - /* MCU Configuration--------------------------------------------------------*/ +0800051c
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 800051c: b580 push {r7, lr} + 800051e: af00 add r7, sp, #0 + /* USER CODE END 1 */ - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - 80004e0: f000 fbd0 bl 8000c84 - /* USER CODE BEGIN Init */ + /* MCU Configuration--------------------------------------------------------*/ - /* USER CODE END Init */ + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000520: f000 fce6 bl 8000ef0 + /* USER CODE BEGIN Init */ - /* Configure the system clock */ - SystemClock_Config(); - 80004e4: f000 f82c bl 8000540 - /* USER CODE BEGIN SysInit */ + /* USER CODE END Init */ - /* USER CODE END SysInit */ + /* Configure the system clock */ + SystemClock_Config(); + 8000524: f000 f84a bl 80005bc + /* USER CODE BEGIN SysInit */ - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - 80004e8: f000 f8be bl 8000668 - MX_USART2_UART_Init(); - 80004ec: f000 f892 bl 8000614 - /* USER CODE BEGIN 2 */ + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000528: f000 f92e bl 8000788 + MX_USART2_UART_Init(); + 800052c: f000 f902 bl 8000734 + MX_ADC1_Init(); + 8000530: f000 f8ae bl 8000690 + /* USER CODE BEGIN 2 */ memset(uart_buffer, 0, 10); - 80004f0: 220a movs r2, #10 - 80004f2: 2100 movs r1, #0 - 80004f4: 480b ldr r0, [pc, #44] ; (8000524 ) - 80004f6: f004 fff1 bl 80054dc - /* USER CODE END 2 */ + 8000534: 220a movs r2, #10 + 8000536: 2100 movs r1, #0 + 8000538: 4813 ldr r0, [pc, #76] ; (8000588 ) + 800053a: f005 fd8f bl 800605c + /* USER CODE END 2 */ - /* Init scheduler */ - osKernelInitialize(); - 80004fa: f002 fa8f bl 8002a1c + /* Init scheduler */ + osKernelInitialize(); + 800053e: f003 f80f bl 8003560 /* add queues, ... */ - /* USER CODE END RTOS_QUEUES */ + /* USER CODE END RTOS_QUEUES */ - /* Create the thread(s) */ - /* creation of mainTask */ - mainTaskHandle = osThreadNew(StartMainTask, NULL, &mainTask_attributes); - 80004fe: 4a0a ldr r2, [pc, #40] ; (8000528 ) - 8000500: 2100 movs r1, #0 - 8000502: 480a ldr r0, [pc, #40] ; (800052c ) - 8000504: f002 fad4 bl 8002ab0 - 8000508: 4603 mov r3, r0 - 800050a: 4a09 ldr r2, [pc, #36] ; (8000530 ) - 800050c: 6013 str r3, [r2, #0] + /* Create the thread(s) */ + /* creation of mainTask */ + mainTaskHandle = osThreadNew(StartMainTask, NULL, &mainTask_attributes); + 8000542: 4a12 ldr r2, [pc, #72] ; (800058c ) + 8000544: 2100 movs r1, #0 + 8000546: 4812 ldr r0, [pc, #72] ; (8000590 ) + 8000548: f003 f854 bl 80035f4 + 800054c: 4603 mov r3, r0 + 800054e: 4a11 ldr r2, [pc, #68] ; (8000594 ) + 8000550: 6013 str r3, [r2, #0] - /* creation of doorHandler */ - doorHandlerHandle = osThreadNew(startDoorHandleTask, NULL, - 800050e: 4a09 ldr r2, [pc, #36] ; (8000534 ) - 8000510: 2100 movs r1, #0 - 8000512: 4809 ldr r0, [pc, #36] ; (8000538 ) - 8000514: f002 facc bl 8002ab0 - 8000518: 4603 mov r3, r0 - 800051a: 4a08 ldr r2, [pc, #32] ; (800053c ) - 800051c: 6013 str r3, [r2, #0] - /* USER CODE BEGIN RTOS_EVENTS */ + /* creation of doorHandler */ + doorHandlerHandle = osThreadNew(startDoorHandleTask, NULL, &doorHandler_attributes); + 8000552: 4a11 ldr r2, [pc, #68] ; (8000598 ) + 8000554: 2100 movs r1, #0 + 8000556: 4811 ldr r0, [pc, #68] ; (800059c ) + 8000558: f003 f84c bl 80035f4 + 800055c: 4603 mov r3, r0 + 800055e: 4a10 ldr r2, [pc, #64] ; (80005a0 ) + 8000560: 6013 str r3, [r2, #0] + + /* creation of StateSendTask */ + StateSendTaskHandle = osThreadNew(StartStateSendTask, NULL, &StateSendTask_attributes); + 8000562: 4a10 ldr r2, [pc, #64] ; (80005a4 ) + 8000564: 2100 movs r1, #0 + 8000566: 4810 ldr r0, [pc, #64] ; (80005a8 ) + 8000568: f003 f844 bl 80035f4 + 800056c: 4603 mov r3, r0 + 800056e: 4a0f ldr r2, [pc, #60] ; (80005ac ) + 8000570: 6013 str r3, [r2, #0] + + /* creation of ADCReqTask */ + ADCReqTaskHandle = osThreadNew(StartADCReqTask, NULL, &ADCReqTask_attributes); + 8000572: 4a0f ldr r2, [pc, #60] ; (80005b0 ) + 8000574: 2100 movs r1, #0 + 8000576: 480f ldr r0, [pc, #60] ; (80005b4 ) + 8000578: f003 f83c bl 80035f4 + 800057c: 4603 mov r3, r0 + 800057e: 4a0e ldr r2, [pc, #56] ; (80005b8 ) + 8000580: 6013 str r3, [r2, #0] + /* USER CODE BEGIN RTOS_EVENTS */ /* add events, ... */ - /* USER CODE END RTOS_EVENTS */ + /* USER CODE END RTOS_EVENTS */ - /* Start scheduler */ - osKernelStart(); - 800051e: f002 faa1 bl 8002a64 + /* Start scheduler */ + osKernelStart(); + 8000582: f003 f811 bl 80035a8 - /* We should never get here as control is now taken by the scheduler */ - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ + /* We should never get here as control is now taken by the scheduler */ + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ while (1) { - 8000522: e7fe b.n 8000522 - 8000524: 200000c8 .word 0x200000c8 - 8000528: 080056f8 .word 0x080056f8 - 800052c: 08000761 .word 0x08000761 - 8000530: 200000c0 .word 0x200000c0 - 8000534: 0800571c .word 0x0800571c - 8000538: 08000855 .word 0x08000855 - 800053c: 200000c4 .word 0x200000c4 - -08000540 : + 8000586: e7fe b.n 8000586 + 8000588: 20000118 .word 0x20000118 + 800058c: 08006294 .word 0x08006294 + 8000590: 08000881 .word 0x08000881 + 8000594: 20000108 .word 0x20000108 + 8000598: 080062b8 .word 0x080062b8 + 800059c: 080009a1 .word 0x080009a1 + 80005a0: 2000010c .word 0x2000010c + 80005a4: 080062dc .word 0x080062dc + 80005a8: 08000b1d .word 0x08000b1d + 80005ac: 20000110 .word 0x20000110 + 80005b0: 08006300 .word 0x08006300 + 80005b4: 08000b75 .word 0x08000b75 + 80005b8: 20000114 .word 0x20000114 +080005bc : /** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) { - 8000540: b580 push {r7, lr} - 8000542: b094 sub sp, #80 ; 0x50 - 8000544: af00 add r7, sp, #0 - RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; - 8000546: f107 0320 add.w r3, r7, #32 - 800054a: 2230 movs r2, #48 ; 0x30 - 800054c: 2100 movs r1, #0 - 800054e: 4618 mov r0, r3 - 8000550: f004 ffc4 bl 80054dc - RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; - 8000554: f107 030c add.w r3, r7, #12 - 8000558: 2200 movs r2, #0 - 800055a: 601a str r2, [r3, #0] - 800055c: 605a str r2, [r3, #4] - 800055e: 609a str r2, [r3, #8] - 8000560: 60da str r2, [r3, #12] - 8000562: 611a str r2, [r3, #16] - - /** Configure the main internal regulator output voltage - */ - __HAL_RCC_PWR_CLK_ENABLE(); - 8000564: 2300 movs r3, #0 - 8000566: 60bb str r3, [r7, #8] - 8000568: 4b28 ldr r3, [pc, #160] ; (800060c ) - 800056a: 6c1b ldr r3, [r3, #64] ; 0x40 - 800056c: 4a27 ldr r2, [pc, #156] ; (800060c ) - 800056e: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8000572: 6413 str r3, [r2, #64] ; 0x40 - 8000574: 4b25 ldr r3, [pc, #148] ; (800060c ) - 8000576: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000578: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 800057c: 60bb str r3, [r7, #8] - 800057e: 68bb ldr r3, [r7, #8] - __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - 8000580: 2300 movs r3, #0 - 8000582: 607b str r3, [r7, #4] - 8000584: 4b22 ldr r3, [pc, #136] ; (8000610 ) - 8000586: 681b ldr r3, [r3, #0] - 8000588: 4a21 ldr r2, [pc, #132] ; (8000610 ) - 800058a: f443 4340 orr.w r3, r3, #49152 ; 0xc000 - 800058e: 6013 str r3, [r2, #0] - 8000590: 4b1f ldr r3, [pc, #124] ; (8000610 ) - 8000592: 681b ldr r3, [r3, #0] - 8000594: f403 4340 and.w r3, r3, #49152 ; 0xc000 - 8000598: 607b str r3, [r7, #4] - 800059a: 687b ldr r3, [r7, #4] - - /** Initializes the RCC Oscillators according to the specified parameters - * in the RCC_OscInitTypeDef structure. - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - 800059c: 2302 movs r3, #2 - 800059e: 623b str r3, [r7, #32] - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - 80005a0: 2301 movs r3, #1 - 80005a2: 62fb str r3, [r7, #44] ; 0x2c - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - 80005a4: 2310 movs r3, #16 - 80005a6: 633b str r3, [r7, #48] ; 0x30 - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - 80005a8: 2302 movs r3, #2 - 80005aa: 63bb str r3, [r7, #56] ; 0x38 - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - 80005ac: 2300 movs r3, #0 - 80005ae: 63fb str r3, [r7, #60] ; 0x3c - RCC_OscInitStruct.PLL.PLLM = 16; - 80005b0: 2310 movs r3, #16 - 80005b2: 643b str r3, [r7, #64] ; 0x40 - RCC_OscInitStruct.PLL.PLLN = 336; - 80005b4: f44f 73a8 mov.w r3, #336 ; 0x150 - 80005b8: 647b str r3, [r7, #68] ; 0x44 - RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; - 80005ba: 2304 movs r3, #4 - 80005bc: 64bb str r3, [r7, #72] ; 0x48 - RCC_OscInitStruct.PLL.PLLQ = 4; - 80005be: 2304 movs r3, #4 - 80005c0: 64fb str r3, [r7, #76] ; 0x4c - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 80005bc: b580 push {r7, lr} + 80005be: b094 sub sp, #80 ; 0x50 + 80005c0: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 80005c2: f107 0320 add.w r3, r7, #32 - 80005c6: 4618 mov r0, r3 - 80005c8: f000 fe36 bl 8001238 - 80005cc: 4603 mov r3, r0 - 80005ce: 2b00 cmp r3, #0 - 80005d0: d001 beq.n 80005d6 - Error_Handler(); - 80005d2: f000 fa0f bl 80009f4 - } + 80005c6: 2230 movs r2, #48 ; 0x30 + 80005c8: 2100 movs r1, #0 + 80005ca: 4618 mov r0, r3 + 80005cc: f005 fd46 bl 800605c + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 80005d0: f107 030c add.w r3, r7, #12 + 80005d4: 2200 movs r2, #0 + 80005d6: 601a str r2, [r3, #0] + 80005d8: 605a str r2, [r3, #4] + 80005da: 609a str r2, [r3, #8] + 80005dc: 60da str r2, [r3, #12] + 80005de: 611a str r2, [r3, #16] - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK - 80005d6: 230f movs r3, #15 - 80005d8: 60fb str r3, [r7, #12] - | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - 80005da: 2302 movs r3, #2 - 80005dc: 613b str r3, [r7, #16] - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - 80005de: 2300 movs r3, #0 - 80005e0: 617b str r3, [r7, #20] - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; - 80005e2: f44f 5380 mov.w r3, #4096 ; 0x1000 - 80005e6: 61bb str r3, [r7, #24] - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - 80005e8: 2300 movs r3, #0 - 80005ea: 61fb str r3, [r7, #28] + /** Configure the main internal regulator output voltage + */ + __HAL_RCC_PWR_CLK_ENABLE(); + 80005e0: 2300 movs r3, #0 + 80005e2: 60bb str r3, [r7, #8] + 80005e4: 4b28 ldr r3, [pc, #160] ; (8000688 ) + 80005e6: 6c1b ldr r3, [r3, #64] ; 0x40 + 80005e8: 4a27 ldr r2, [pc, #156] ; (8000688 ) + 80005ea: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 80005ee: 6413 str r3, [r2, #64] ; 0x40 + 80005f0: 4b25 ldr r3, [pc, #148] ; (8000688 ) + 80005f2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80005f4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 80005f8: 60bb str r3, [r7, #8] + 80005fa: 68bb ldr r3, [r7, #8] + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 80005fc: 2300 movs r3, #0 + 80005fe: 607b str r3, [r7, #4] + 8000600: 4b22 ldr r3, [pc, #136] ; (800068c ) + 8000602: 681b ldr r3, [r3, #0] + 8000604: 4a21 ldr r2, [pc, #132] ; (800068c ) + 8000606: f443 4340 orr.w r3, r3, #49152 ; 0xc000 + 800060a: 6013 str r3, [r2, #0] + 800060c: 4b1f ldr r3, [pc, #124] ; (800068c ) + 800060e: 681b ldr r3, [r3, #0] + 8000610: f403 4340 and.w r3, r3, #49152 ; 0xc000 + 8000614: 607b str r3, [r7, #4] + 8000616: 687b ldr r3, [r7, #4] - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { - 80005ec: f107 030c add.w r3, r7, #12 - 80005f0: 2102 movs r1, #2 - 80005f2: 4618 mov r0, r3 - 80005f4: f001 f898 bl 8001728 - 80005f8: 4603 mov r3, r0 - 80005fa: 2b00 cmp r3, #0 - 80005fc: d001 beq.n 8000602 - Error_Handler(); - 80005fe: f000 f9f9 bl 80009f4 - } + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + 8000618: 2302 movs r3, #2 + 800061a: 623b str r3, [r7, #32] + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + 800061c: 2301 movs r3, #1 + 800061e: 62fb str r3, [r7, #44] ; 0x2c + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + 8000620: 2310 movs r3, #16 + 8000622: 633b str r3, [r7, #48] ; 0x30 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + 8000624: 2302 movs r3, #2 + 8000626: 63bb str r3, [r7, #56] ; 0x38 + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + 8000628: 2300 movs r3, #0 + 800062a: 63fb str r3, [r7, #60] ; 0x3c + RCC_OscInitStruct.PLL.PLLM = 16; + 800062c: 2310 movs r3, #16 + 800062e: 643b str r3, [r7, #64] ; 0x40 + RCC_OscInitStruct.PLL.PLLN = 336; + 8000630: f44f 73a8 mov.w r3, #336 ; 0x150 + 8000634: 647b str r3, [r7, #68] ; 0x44 + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; + 8000636: 2304 movs r3, #4 + 8000638: 64bb str r3, [r7, #72] ; 0x48 + RCC_OscInitStruct.PLL.PLLQ = 4; + 800063a: 2304 movs r3, #4 + 800063c: 64fb str r3, [r7, #76] ; 0x4c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 800063e: f107 0320 add.w r3, r7, #32 + 8000642: 4618 mov r0, r3 + 8000644: f001 fb9a bl 8001d7c + 8000648: 4603 mov r3, r0 + 800064a: 2b00 cmp r3, #0 + 800064c: d001 beq.n 8000652 + { + Error_Handler(); + 800064e: f000 fab1 bl 8000bb4 + } + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + 8000652: 230f movs r3, #15 + 8000654: 60fb str r3, [r7, #12] + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + 8000656: 2302 movs r3, #2 + 8000658: 613b str r3, [r7, #16] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 800065a: 2300 movs r3, #0 + 800065c: 617b str r3, [r7, #20] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + 800065e: f44f 5380 mov.w r3, #4096 ; 0x1000 + 8000662: 61bb str r3, [r7, #24] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 8000664: 2300 movs r3, #0 + 8000666: 61fb str r3, [r7, #28] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 8000668: f107 030c add.w r3, r7, #12 + 800066c: 2102 movs r1, #2 + 800066e: 4618 mov r0, r3 + 8000670: f001 fdfc bl 800226c + 8000674: 4603 mov r3, r0 + 8000676: 2b00 cmp r3, #0 + 8000678: d001 beq.n 800067e + { + Error_Handler(); + 800067a: f000 fa9b bl 8000bb4 + } } - 8000602: bf00 nop - 8000604: 3750 adds r7, #80 ; 0x50 - 8000606: 46bd mov sp, r7 - 8000608: bd80 pop {r7, pc} - 800060a: bf00 nop - 800060c: 40023800 .word 0x40023800 - 8000610: 40007000 .word 0x40007000 + 800067e: bf00 nop + 8000680: 3750 adds r7, #80 ; 0x50 + 8000682: 46bd mov sp, r7 + 8000684: bd80 pop {r7, pc} + 8000686: bf00 nop + 8000688: 40023800 .word 0x40023800 + 800068c: 40007000 .word 0x40007000 -08000614 : -/** - * @brief USART2 Initialization Function - * @param None - * @retval None - */ -static void MX_USART2_UART_Init(void) { - 8000614: b580 push {r7, lr} - 8000616: af00 add r7, sp, #0 - /* USER CODE END USART2_Init 0 */ +08000690 : + * @brief ADC1 Initialization Function + * @param None + * @retval None + */ +static void MX_ADC1_Init(void) +{ + 8000690: b580 push {r7, lr} + 8000692: b084 sub sp, #16 + 8000694: af00 add r7, sp, #0 - /* USER CODE BEGIN USART2_Init 1 */ + /* USER CODE BEGIN ADC1_Init 0 */ - /* USER CODE END USART2_Init 1 */ - huart2.Instance = USART2; - 8000618: 4b11 ldr r3, [pc, #68] ; (8000660 ) - 800061a: 4a12 ldr r2, [pc, #72] ; (8000664 ) - 800061c: 601a str r2, [r3, #0] - huart2.Init.BaudRate = 9600; - 800061e: 4b10 ldr r3, [pc, #64] ; (8000660 ) - 8000620: f44f 5216 mov.w r2, #9600 ; 0x2580 - 8000624: 605a str r2, [r3, #4] - huart2.Init.WordLength = UART_WORDLENGTH_8B; - 8000626: 4b0e ldr r3, [pc, #56] ; (8000660 ) - 8000628: 2200 movs r2, #0 - 800062a: 609a str r2, [r3, #8] - huart2.Init.StopBits = UART_STOPBITS_1; - 800062c: 4b0c ldr r3, [pc, #48] ; (8000660 ) - 800062e: 2200 movs r2, #0 - 8000630: 60da str r2, [r3, #12] - huart2.Init.Parity = UART_PARITY_NONE; - 8000632: 4b0b ldr r3, [pc, #44] ; (8000660 ) - 8000634: 2200 movs r2, #0 - 8000636: 611a str r2, [r3, #16] - huart2.Init.Mode = UART_MODE_TX_RX; - 8000638: 4b09 ldr r3, [pc, #36] ; (8000660 ) - 800063a: 220c movs r2, #12 - 800063c: 615a str r2, [r3, #20] - huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; - 800063e: 4b08 ldr r3, [pc, #32] ; (8000660 ) - 8000640: 2200 movs r2, #0 - 8000642: 619a str r2, [r3, #24] - huart2.Init.OverSampling = UART_OVERSAMPLING_16; - 8000644: 4b06 ldr r3, [pc, #24] ; (8000660 ) - 8000646: 2200 movs r2, #0 - 8000648: 61da str r2, [r3, #28] - if (HAL_UART_Init(&huart2) != HAL_OK) { - 800064a: 4805 ldr r0, [pc, #20] ; (8000660 ) - 800064c: f001 fd3e bl 80020cc - 8000650: 4603 mov r3, r0 - 8000652: 2b00 cmp r3, #0 - 8000654: d001 beq.n 800065a - Error_Handler(); - 8000656: f000 f9cd bl 80009f4 - } - /* USER CODE BEGIN USART2_Init 2 */ + /* USER CODE END ADC1_Init 0 */ - /* USER CODE END USART2_Init 2 */ + ADC_ChannelConfTypeDef sConfig = {0}; + 8000696: 463b mov r3, r7 + 8000698: 2200 movs r2, #0 + 800069a: 601a str r2, [r3, #0] + 800069c: 605a str r2, [r3, #4] + 800069e: 609a str r2, [r3, #8] + 80006a0: 60da str r2, [r3, #12] -} - 800065a: bf00 nop - 800065c: bd80 pop {r7, pc} - 800065e: bf00 nop - 8000660: 2000007c .word 0x2000007c - 8000664: 40004400 .word 0x40004400 + /* USER CODE END ADC1_Init 1 */ -08000668 : -/** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) { - 8000668: b580 push {r7, lr} - 800066a: b08a sub sp, #40 ; 0x28 - 800066c: af00 add r7, sp, #0 - GPIO_InitTypeDef GPIO_InitStruct = { 0 }; - 800066e: f107 0314 add.w r3, r7, #20 - 8000672: 2200 movs r2, #0 - 8000674: 601a str r2, [r3, #0] - 8000676: 605a str r2, [r3, #4] - 8000678: 609a str r2, [r3, #8] - 800067a: 60da str r2, [r3, #12] - 800067c: 611a str r2, [r3, #16] - /* USER CODE BEGIN MX_GPIO_Init_1 */ - /* USER CODE END MX_GPIO_Init_1 */ + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc1.Instance = ADC1; + 80006a2: 4b21 ldr r3, [pc, #132] ; (8000728 ) + 80006a4: 4a21 ldr r2, [pc, #132] ; (800072c ) + 80006a6: 601a str r2, [r3, #0] + hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4; + 80006a8: 4b1f ldr r3, [pc, #124] ; (8000728 ) + 80006aa: f44f 3280 mov.w r2, #65536 ; 0x10000 + 80006ae: 605a str r2, [r3, #4] + hadc1.Init.Resolution = ADC_RESOLUTION_12B; + 80006b0: 4b1d ldr r3, [pc, #116] ; (8000728 ) + 80006b2: 2200 movs r2, #0 + 80006b4: 609a str r2, [r3, #8] + hadc1.Init.ScanConvMode = DISABLE; + 80006b6: 4b1c ldr r3, [pc, #112] ; (8000728 ) + 80006b8: 2200 movs r2, #0 + 80006ba: 611a str r2, [r3, #16] + hadc1.Init.ContinuousConvMode = DISABLE; + 80006bc: 4b1a ldr r3, [pc, #104] ; (8000728 ) + 80006be: 2200 movs r2, #0 + 80006c0: 761a strb r2, [r3, #24] + hadc1.Init.DiscontinuousConvMode = DISABLE; + 80006c2: 4b19 ldr r3, [pc, #100] ; (8000728 ) + 80006c4: 2200 movs r2, #0 + 80006c6: f883 2020 strb.w r2, [r3, #32] + hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 80006ca: 4b17 ldr r3, [pc, #92] ; (8000728 ) + 80006cc: 2200 movs r2, #0 + 80006ce: 62da str r2, [r3, #44] ; 0x2c + hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 80006d0: 4b15 ldr r3, [pc, #84] ; (8000728 ) + 80006d2: 4a17 ldr r2, [pc, #92] ; (8000730 ) + 80006d4: 629a str r2, [r3, #40] ; 0x28 + hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 80006d6: 4b14 ldr r3, [pc, #80] ; (8000728 ) + 80006d8: 2200 movs r2, #0 + 80006da: 60da str r2, [r3, #12] + hadc1.Init.NbrOfConversion = 1; + 80006dc: 4b12 ldr r3, [pc, #72] ; (8000728 ) + 80006de: 2201 movs r2, #1 + 80006e0: 61da str r2, [r3, #28] + hadc1.Init.DMAContinuousRequests = DISABLE; + 80006e2: 4b11 ldr r3, [pc, #68] ; (8000728 ) + 80006e4: 2200 movs r2, #0 + 80006e6: f883 2030 strb.w r2, [r3, #48] ; 0x30 + hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 80006ea: 4b0f ldr r3, [pc, #60] ; (8000728 ) + 80006ec: 2201 movs r2, #1 + 80006ee: 615a str r2, [r3, #20] + if (HAL_ADC_Init(&hadc1) != HAL_OK) + 80006f0: 480d ldr r0, [pc, #52] ; (8000728 ) + 80006f2: f000 fc3f bl 8000f74 + 80006f6: 4603 mov r3, r0 + 80006f8: 2b00 cmp r3, #0 + 80006fa: d001 beq.n 8000700 + { + Error_Handler(); + 80006fc: f000 fa5a bl 8000bb4 + } - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOC_CLK_ENABLE(); - 800067e: 2300 movs r3, #0 - 8000680: 613b str r3, [r7, #16] - 8000682: 4b34 ldr r3, [pc, #208] ; (8000754 ) - 8000684: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000686: 4a33 ldr r2, [pc, #204] ; (8000754 ) - 8000688: f043 0304 orr.w r3, r3, #4 - 800068c: 6313 str r3, [r2, #48] ; 0x30 - 800068e: 4b31 ldr r3, [pc, #196] ; (8000754 ) - 8000690: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000692: f003 0304 and.w r3, r3, #4 - 8000696: 613b str r3, [r7, #16] - 8000698: 693b ldr r3, [r7, #16] - __HAL_RCC_GPIOH_CLK_ENABLE(); - 800069a: 2300 movs r3, #0 - 800069c: 60fb str r3, [r7, #12] - 800069e: 4b2d ldr r3, [pc, #180] ; (8000754 ) - 80006a0: 6b1b ldr r3, [r3, #48] ; 0x30 - 80006a2: 4a2c ldr r2, [pc, #176] ; (8000754 ) - 80006a4: f043 0380 orr.w r3, r3, #128 ; 0x80 - 80006a8: 6313 str r3, [r2, #48] ; 0x30 - 80006aa: 4b2a ldr r3, [pc, #168] ; (8000754 ) - 80006ac: 6b1b ldr r3, [r3, #48] ; 0x30 - 80006ae: f003 0380 and.w r3, r3, #128 ; 0x80 - 80006b2: 60fb str r3, [r7, #12] - 80006b4: 68fb ldr r3, [r7, #12] - __HAL_RCC_GPIOA_CLK_ENABLE(); - 80006b6: 2300 movs r3, #0 - 80006b8: 60bb str r3, [r7, #8] - 80006ba: 4b26 ldr r3, [pc, #152] ; (8000754 ) - 80006bc: 6b1b ldr r3, [r3, #48] ; 0x30 - 80006be: 4a25 ldr r2, [pc, #148] ; (8000754 ) - 80006c0: f043 0301 orr.w r3, r3, #1 - 80006c4: 6313 str r3, [r2, #48] ; 0x30 - 80006c6: 4b23 ldr r3, [pc, #140] ; (8000754 ) - 80006c8: 6b1b ldr r3, [r3, #48] ; 0x30 - 80006ca: f003 0301 and.w r3, r3, #1 - 80006ce: 60bb str r3, [r7, #8] - 80006d0: 68bb ldr r3, [r7, #8] - __HAL_RCC_GPIOB_CLK_ENABLE(); - 80006d2: 2300 movs r3, #0 - 80006d4: 607b str r3, [r7, #4] - 80006d6: 4b1f ldr r3, [pc, #124] ; (8000754 ) - 80006d8: 6b1b ldr r3, [r3, #48] ; 0x30 - 80006da: 4a1e ldr r2, [pc, #120] ; (8000754 ) - 80006dc: f043 0302 orr.w r3, r3, #2 - 80006e0: 6313 str r3, [r2, #48] ; 0x30 - 80006e2: 4b1c ldr r3, [pc, #112] ; (8000754 ) - 80006e4: 6b1b ldr r3, [r3, #48] ; 0x30 - 80006e6: f003 0302 and.w r3, r3, #2 - 80006ea: 607b str r3, [r7, #4] - 80006ec: 687b ldr r3, [r7, #4] - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOA, LD2_Pin | Door_Lock_Pin, GPIO_PIN_RESET); - 80006ee: 2200 movs r2, #0 - 80006f0: f44f 7108 mov.w r1, #544 ; 0x220 - 80006f4: 4818 ldr r0, [pc, #96] ; (8000758 ) - 80006f6: f000 fd85 bl 8001204 - - /*Configure GPIO pin : B1_Pin */ - GPIO_InitStruct.Pin = B1_Pin; - 80006fa: f44f 5300 mov.w r3, #8192 ; 0x2000 - 80006fe: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; - 8000700: f44f 1304 mov.w r3, #2162688 ; 0x210000 - 8000704: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000706: 2300 movs r3, #0 - 8000708: 61fb str r3, [r7, #28] - HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); - 800070a: f107 0314 add.w r3, r7, #20 + /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time. + */ + sConfig.Channel = ADC_CHANNEL_1; + 8000700: 2301 movs r3, #1 + 8000702: 603b str r3, [r7, #0] + sConfig.Rank = 1; + 8000704: 2301 movs r3, #1 + 8000706: 607b str r3, [r7, #4] + sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES; + 8000708: 2300 movs r3, #0 + 800070a: 60bb str r3, [r7, #8] + if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK) + 800070c: 463b mov r3, r7 800070e: 4619 mov r1, r3 - 8000710: 4812 ldr r0, [pc, #72] ; (800075c ) - 8000712: f000 fbdb bl 8000ecc + 8000710: 4805 ldr r0, [pc, #20] ; (8000728 ) + 8000712: f000 fe63 bl 80013dc + 8000716: 4603 mov r3, r0 + 8000718: 2b00 cmp r3, #0 + 800071a: d001 beq.n 8000720 + { + Error_Handler(); + 800071c: f000 fa4a bl 8000bb4 + } + /* USER CODE BEGIN ADC1_Init 2 */ - /*Configure GPIO pins : LD2_Pin Door_Lock_Pin */ - GPIO_InitStruct.Pin = LD2_Pin | Door_Lock_Pin; - 8000716: f44f 7308 mov.w r3, #544 ; 0x220 - 800071a: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - 800071c: 2301 movs r3, #1 - 800071e: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000720: 2300 movs r3, #0 - 8000722: 61fb str r3, [r7, #28] - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - 8000724: 2300 movs r3, #0 - 8000726: 623b str r3, [r7, #32] - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000728: f107 0314 add.w r3, r7, #20 - 800072c: 4619 mov r1, r3 - 800072e: 480a ldr r0, [pc, #40] ; (8000758 ) - 8000730: f000 fbcc bl 8000ecc + /* USER CODE END ADC1_Init 2 */ - /*Configure GPIO pin : Door_Sensor_Pin */ - GPIO_InitStruct.Pin = Door_Sensor_Pin; - 8000734: 2380 movs r3, #128 ; 0x80 - 8000736: 617b str r3, [r7, #20] - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - 8000738: 2300 movs r3, #0 - 800073a: 61bb str r3, [r7, #24] - GPIO_InitStruct.Pull = GPIO_PULLUP; - 800073c: 2301 movs r3, #1 - 800073e: 61fb str r3, [r7, #28] - HAL_GPIO_Init(Door_Sensor_GPIO_Port, &GPIO_InitStruct); - 8000740: f107 0314 add.w r3, r7, #20 - 8000744: 4619 mov r1, r3 - 8000746: 4804 ldr r0, [pc, #16] ; (8000758 ) - 8000748: f000 fbc0 bl 8000ecc - - /* USER CODE BEGIN MX_GPIO_Init_2 */ - /* USER CODE END MX_GPIO_Init_2 */ } - 800074c: bf00 nop - 800074e: 3728 adds r7, #40 ; 0x28 - 8000750: 46bd mov sp, r7 - 8000752: bd80 pop {r7, pc} - 8000754: 40023800 .word 0x40023800 - 8000758: 40020000 .word 0x40020000 - 800075c: 40020800 .word 0x40020800 + 8000720: bf00 nop + 8000722: 3710 adds r7, #16 + 8000724: 46bd mov sp, r7 + 8000726: bd80 pop {r7, pc} + 8000728: 2000007c .word 0x2000007c + 800072c: 40012000 .word 0x40012000 + 8000730: 0f000001 .word 0x0f000001 -08000760 : - * @brief Function implementing the mainTask thread. +08000734 : + * @brief USART2 Initialization Function + * @param None + * @retval None + */ +static void MX_USART2_UART_Init(void) +{ + 8000734: b580 push {r7, lr} + 8000736: af00 add r7, sp, #0 + /* USER CODE END USART2_Init 0 */ + + /* USER CODE BEGIN USART2_Init 1 */ + + /* USER CODE END USART2_Init 1 */ + huart2.Instance = USART2; + 8000738: 4b11 ldr r3, [pc, #68] ; (8000780 ) + 800073a: 4a12 ldr r2, [pc, #72] ; (8000784 ) + 800073c: 601a str r2, [r3, #0] + huart2.Init.BaudRate = 9600; + 800073e: 4b10 ldr r3, [pc, #64] ; (8000780 ) + 8000740: f44f 5216 mov.w r2, #9600 ; 0x2580 + 8000744: 605a str r2, [r3, #4] + huart2.Init.WordLength = UART_WORDLENGTH_8B; + 8000746: 4b0e ldr r3, [pc, #56] ; (8000780 ) + 8000748: 2200 movs r2, #0 + 800074a: 609a str r2, [r3, #8] + huart2.Init.StopBits = UART_STOPBITS_1; + 800074c: 4b0c ldr r3, [pc, #48] ; (8000780 ) + 800074e: 2200 movs r2, #0 + 8000750: 60da str r2, [r3, #12] + huart2.Init.Parity = UART_PARITY_NONE; + 8000752: 4b0b ldr r3, [pc, #44] ; (8000780 ) + 8000754: 2200 movs r2, #0 + 8000756: 611a str r2, [r3, #16] + huart2.Init.Mode = UART_MODE_TX_RX; + 8000758: 4b09 ldr r3, [pc, #36] ; (8000780 ) + 800075a: 220c movs r2, #12 + 800075c: 615a str r2, [r3, #20] + huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800075e: 4b08 ldr r3, [pc, #32] ; (8000780 ) + 8000760: 2200 movs r2, #0 + 8000762: 619a str r2, [r3, #24] + huart2.Init.OverSampling = UART_OVERSAMPLING_16; + 8000764: 4b06 ldr r3, [pc, #24] ; (8000780 ) + 8000766: 2200 movs r2, #0 + 8000768: 61da str r2, [r3, #28] + if (HAL_UART_Init(&huart2) != HAL_OK) + 800076a: 4805 ldr r0, [pc, #20] ; (8000780 ) + 800076c: f002 fa50 bl 8002c10 + 8000770: 4603 mov r3, r0 + 8000772: 2b00 cmp r3, #0 + 8000774: d001 beq.n 800077a + { + Error_Handler(); + 8000776: f000 fa1d bl 8000bb4 + } + /* USER CODE BEGIN USART2_Init 2 */ + + /* USER CODE END USART2_Init 2 */ + +} + 800077a: bf00 nop + 800077c: bd80 pop {r7, pc} + 800077e: bf00 nop + 8000780: 200000c4 .word 0x200000c4 + 8000784: 40004400 .word 0x40004400 + +08000788 : + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + 8000788: b580 push {r7, lr} + 800078a: b08a sub sp, #40 ; 0x28 + 800078c: af00 add r7, sp, #0 + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800078e: f107 0314 add.w r3, r7, #20 + 8000792: 2200 movs r2, #0 + 8000794: 601a str r2, [r3, #0] + 8000796: 605a str r2, [r3, #4] + 8000798: 609a str r2, [r3, #8] + 800079a: 60da str r2, [r3, #12] + 800079c: 611a str r2, [r3, #16] +/* USER CODE BEGIN MX_GPIO_Init_1 */ +/* USER CODE END MX_GPIO_Init_1 */ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800079e: 2300 movs r3, #0 + 80007a0: 613b str r3, [r7, #16] + 80007a2: 4b34 ldr r3, [pc, #208] ; (8000874 ) + 80007a4: 6b1b ldr r3, [r3, #48] ; 0x30 + 80007a6: 4a33 ldr r2, [pc, #204] ; (8000874 ) + 80007a8: f043 0304 orr.w r3, r3, #4 + 80007ac: 6313 str r3, [r2, #48] ; 0x30 + 80007ae: 4b31 ldr r3, [pc, #196] ; (8000874 ) + 80007b0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80007b2: f003 0304 and.w r3, r3, #4 + 80007b6: 613b str r3, [r7, #16] + 80007b8: 693b ldr r3, [r7, #16] + __HAL_RCC_GPIOH_CLK_ENABLE(); + 80007ba: 2300 movs r3, #0 + 80007bc: 60fb str r3, [r7, #12] + 80007be: 4b2d ldr r3, [pc, #180] ; (8000874 ) + 80007c0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80007c2: 4a2c ldr r2, [pc, #176] ; (8000874 ) + 80007c4: f043 0380 orr.w r3, r3, #128 ; 0x80 + 80007c8: 6313 str r3, [r2, #48] ; 0x30 + 80007ca: 4b2a ldr r3, [pc, #168] ; (8000874 ) + 80007cc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80007ce: f003 0380 and.w r3, r3, #128 ; 0x80 + 80007d2: 60fb str r3, [r7, #12] + 80007d4: 68fb ldr r3, [r7, #12] + __HAL_RCC_GPIOA_CLK_ENABLE(); + 80007d6: 2300 movs r3, #0 + 80007d8: 60bb str r3, [r7, #8] + 80007da: 4b26 ldr r3, [pc, #152] ; (8000874 ) + 80007dc: 6b1b ldr r3, [r3, #48] ; 0x30 + 80007de: 4a25 ldr r2, [pc, #148] ; (8000874 ) + 80007e0: f043 0301 orr.w r3, r3, #1 + 80007e4: 6313 str r3, [r2, #48] ; 0x30 + 80007e6: 4b23 ldr r3, [pc, #140] ; (8000874 ) + 80007e8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80007ea: f003 0301 and.w r3, r3, #1 + 80007ee: 60bb str r3, [r7, #8] + 80007f0: 68bb ldr r3, [r7, #8] + __HAL_RCC_GPIOB_CLK_ENABLE(); + 80007f2: 2300 movs r3, #0 + 80007f4: 607b str r3, [r7, #4] + 80007f6: 4b1f ldr r3, [pc, #124] ; (8000874 ) + 80007f8: 6b1b ldr r3, [r3, #48] ; 0x30 + 80007fa: 4a1e ldr r2, [pc, #120] ; (8000874 ) + 80007fc: f043 0302 orr.w r3, r3, #2 + 8000800: 6313 str r3, [r2, #48] ; 0x30 + 8000802: 4b1c ldr r3, [pc, #112] ; (8000874 ) + 8000804: 6b1b ldr r3, [r3, #48] ; 0x30 + 8000806: f003 0302 and.w r3, r3, #2 + 800080a: 607b str r3, [r7, #4] + 800080c: 687b ldr r3, [r7, #4] + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOA, LD2_Pin|Door_Lock_Pin, GPIO_PIN_RESET); + 800080e: 2200 movs r2, #0 + 8000810: f44f 7108 mov.w r1, #544 ; 0x220 + 8000814: 4818 ldr r0, [pc, #96] ; (8000878 ) + 8000816: f001 fa97 bl 8001d48 + + /*Configure GPIO pin : B1_Pin */ + GPIO_InitStruct.Pin = B1_Pin; + 800081a: f44f 5300 mov.w r3, #8192 ; 0x2000 + 800081e: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; + 8000820: f44f 1304 mov.w r3, #2162688 ; 0x210000 + 8000824: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000826: 2300 movs r3, #0 + 8000828: 61fb str r3, [r7, #28] + HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); + 800082a: f107 0314 add.w r3, r7, #20 + 800082e: 4619 mov r1, r3 + 8000830: 4812 ldr r0, [pc, #72] ; (800087c ) + 8000832: f001 f8ed bl 8001a10 + + /*Configure GPIO pins : LD2_Pin Door_Lock_Pin */ + GPIO_InitStruct.Pin = LD2_Pin|Door_Lock_Pin; + 8000836: f44f 7308 mov.w r3, #544 ; 0x220 + 800083a: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 800083c: 2301 movs r3, #1 + 800083e: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000840: 2300 movs r3, #0 + 8000842: 61fb str r3, [r7, #28] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000844: 2300 movs r3, #0 + 8000846: 623b str r3, [r7, #32] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000848: f107 0314 add.w r3, r7, #20 + 800084c: 4619 mov r1, r3 + 800084e: 480a ldr r0, [pc, #40] ; (8000878 ) + 8000850: f001 f8de bl 8001a10 + + /*Configure GPIO pin : Door_Sensor_Pin */ + GPIO_InitStruct.Pin = Door_Sensor_Pin; + 8000854: 2380 movs r3, #128 ; 0x80 + 8000856: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + 8000858: 2300 movs r3, #0 + 800085a: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_PULLUP; + 800085c: 2301 movs r3, #1 + 800085e: 61fb str r3, [r7, #28] + HAL_GPIO_Init(Door_Sensor_GPIO_Port, &GPIO_InitStruct); + 8000860: f107 0314 add.w r3, r7, #20 + 8000864: 4619 mov r1, r3 + 8000866: 4804 ldr r0, [pc, #16] ; (8000878 ) + 8000868: f001 f8d2 bl 8001a10 + +/* USER CODE BEGIN MX_GPIO_Init_2 */ +/* USER CODE END MX_GPIO_Init_2 */ +} + 800086c: bf00 nop + 800086e: 3728 adds r7, #40 ; 0x28 + 8000870: 46bd mov sp, r7 + 8000872: bd80 pop {r7, pc} + 8000874: 40023800 .word 0x40023800 + 8000878: 40020000 .word 0x40020000 + 800087c: 40020800 .word 0x40020800 + +08000880 : * @param argument: Not used * @retval None */ /* USER CODE END Header_StartMainTask */ -void StartMainTask(void *argument) { - 8000760: b580 push {r7, lr} - 8000762: b084 sub sp, #16 - 8000764: af00 add r7, sp, #0 - 8000766: 6078 str r0, [r7, #4] - /* USER CODE BEGIN 5 */ +void StartMainTask(void *argument) +{ + 8000880: b580 push {r7, lr} + 8000882: b084 sub sp, #16 + 8000884: af00 add r7, sp, #0 + 8000886: 6078 str r0, [r7, #4] + /* USER CODE BEGIN 5 */ memset(uart_buffer, 0, 10); - 8000768: 220a movs r2, #10 - 800076a: 2100 movs r1, #0 - 800076c: 4833 ldr r0, [pc, #204] ; (800083c ) - 800076e: f004 feb5 bl 80054dc + 8000888: 220a movs r2, #10 + 800088a: 2100 movs r1, #0 + 800088c: 483d ldr r0, [pc, #244] ; (8000984 ) + 800088e: f005 fbe5 bl 800605c /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { - if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 1000) - 8000772: 4b33 ldr r3, [pc, #204] ; (8000840 ) - 8000774: 781b ldrb r3, [r3, #0] - 8000776: 461a mov r2, r3 - 8000778: 4b30 ldr r3, [pc, #192] ; (800083c ) - 800077a: 18d1 adds r1, r2, r3 - 800077c: f44f 737a mov.w r3, #1000 ; 0x3e8 - 8000780: 2201 movs r2, #1 - 8000782: 4830 ldr r0, [pc, #192] ; (8000844 ) - 8000784: f001 fd81 bl 800228a - 8000788: 4603 mov r3, r0 - 800078a: 2b00 cmp r3, #0 - 800078c: d152 bne.n 8000834 + if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 100) + 8000892: 4b3d ldr r3, [pc, #244] ; (8000988 ) + 8000894: 781b ldrb r3, [r3, #0] + 8000896: 461a mov r2, r3 + 8000898: 4b3a ldr r3, [pc, #232] ; (8000984 ) + 800089a: 18d1 adds r1, r2, r3 + 800089c: 2364 movs r3, #100 ; 0x64 + 800089e: 2201 movs r2, #1 + 80008a0: 483a ldr r0, [pc, #232] ; (800098c ) + 80008a2: f002 fa94 bl 8002dce + 80008a6: 4603 mov r3, r0 + 80008a8: 2b00 cmp r3, #0 + 80008aa: d166 bne.n 800097a == HAL_OK) { uart_index++; - 800078e: 4b2c ldr r3, [pc, #176] ; (8000840 ) - 8000790: 781b ldrb r3, [r3, #0] - 8000792: 3301 adds r3, #1 - 8000794: b2da uxtb r2, r3 - 8000796: 4b2a ldr r3, [pc, #168] ; (8000840 ) - 8000798: 701a strb r2, [r3, #0] + 80008ac: 4b36 ldr r3, [pc, #216] ; (8000988 ) + 80008ae: 781b ldrb r3, [r3, #0] + 80008b0: 3301 adds r3, #1 + 80008b2: b2da uxtb r2, r3 + 80008b4: 4b34 ldr r3, [pc, #208] ; (8000988 ) + 80008b6: 701a strb r2, [r3, #0] if (uart_buffer[uart_index - 1] == 0xFF) { - 800079a: 4b29 ldr r3, [pc, #164] ; (8000840 ) - 800079c: 781b ldrb r3, [r3, #0] - 800079e: 3b01 subs r3, #1 - 80007a0: 4a26 ldr r2, [pc, #152] ; (800083c ) - 80007a2: 5cd3 ldrb r3, [r2, r3] - 80007a4: 2bff cmp r3, #255 ; 0xff - 80007a6: d139 bne.n 800081c + 80008b8: 4b33 ldr r3, [pc, #204] ; (8000988 ) + 80008ba: 781b ldrb r3, [r3, #0] + 80008bc: 3b01 subs r3, #1 + 80008be: 4a31 ldr r2, [pc, #196] ; (8000984 ) + 80008c0: 5cd3 ldrb r3, [r2, r3] + 80008c2: 2bff cmp r3, #255 ; 0xff + 80008c4: d14d bne.n 8000962 if (uart_index > 1) { - 80007a8: 4b25 ldr r3, [pc, #148] ; (8000840 ) - 80007aa: 781b ldrb r3, [r3, #0] - 80007ac: 2b01 cmp r3, #1 - 80007ae: d92c bls.n 800080a - //Command Internal LED + 80008c6: 4b30 ldr r3, [pc, #192] ; (8000988 ) + 80008c8: 781b ldrb r3, [r3, #0] + 80008ca: 2b01 cmp r3, #1 + 80008cc: d940 bls.n 8000950 + // Command Internal LED if (uart_buffer[0] == 0x00) { - 80007b0: 4b22 ldr r3, [pc, #136] ; (800083c ) - 80007b2: 781b ldrb r3, [r3, #0] - 80007b4: 2b00 cmp r3, #0 - 80007b6: d107 bne.n 80007c8 + 80008ce: 4b2d ldr r3, [pc, #180] ; (8000984 ) + 80008d0: 781b ldrb r3, [r3, #0] + 80008d2: 2b00 cmp r3, #0 + 80008d4: d107 bne.n 80008e6 HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, uart_buffer[1]); - 80007b8: 4b20 ldr r3, [pc, #128] ; (800083c ) - 80007ba: 785b ldrb r3, [r3, #1] - 80007bc: 461a mov r2, r3 - 80007be: 2120 movs r1, #32 - 80007c0: 4821 ldr r0, [pc, #132] ; (8000848 ) - 80007c2: f000 fd1f bl 8001204 - 80007c6: e020 b.n 800080a + 80008d6: 4b2b ldr r3, [pc, #172] ; (8000984 ) + 80008d8: 785b ldrb r3, [r3, #1] + 80008da: 461a mov r2, r3 + 80008dc: 2120 movs r1, #32 + 80008de: 482c ldr r0, [pc, #176] ; (8000990 ) + 80008e0: f001 fa32 bl 8001d48 + 80008e4: e034 b.n 8000950 } // Get Current Door State else if (uart_buffer[0] == 0x01) { - 80007c8: 4b1c ldr r3, [pc, #112] ; (800083c ) - 80007ca: 781b ldrb r3, [r3, #0] - 80007cc: 2b01 cmp r3, #1 - 80007ce: d10f bne.n 80007f0 + 80008e6: 4b27 ldr r3, [pc, #156] ; (8000984 ) + 80008e8: 781b ldrb r3, [r3, #0] + 80008ea: 2b01 cmp r3, #1 + 80008ec: d10f bne.n 800090e uint8_t payload[3] = { 0x01, door_state, 0xFF }; - 80007d0: 2301 movs r3, #1 - 80007d2: 733b strb r3, [r7, #12] - 80007d4: 4b1d ldr r3, [pc, #116] ; (800084c ) - 80007d6: 781b ldrb r3, [r3, #0] - 80007d8: 737b strb r3, [r7, #13] - 80007da: 23ff movs r3, #255 ; 0xff - 80007dc: 73bb strb r3, [r7, #14] + 80008ee: 2301 movs r3, #1 + 80008f0: 733b strb r3, [r7, #12] + 80008f2: 4b28 ldr r3, [pc, #160] ; (8000994 ) + 80008f4: 781b ldrb r3, [r3, #0] + 80008f6: 737b strb r3, [r7, #13] + 80008f8: 23ff movs r3, #255 ; 0xff + 80008fa: 73bb strb r3, [r7, #14] HAL_UART_Transmit(&huart2, payload, 3, 1500); - 80007de: f107 010c add.w r1, r7, #12 - 80007e2: f240 53dc movw r3, #1500 ; 0x5dc - 80007e6: 2203 movs r2, #3 - 80007e8: 4816 ldr r0, [pc, #88] ; (8000844 ) - 80007ea: f001 fcbc bl 8002166 - 80007ee: e00c b.n 800080a + 80008fc: f107 010c add.w r1, r7, #12 + 8000900: f240 53dc movw r3, #1500 ; 0x5dc + 8000904: 2203 movs r2, #3 + 8000906: 4821 ldr r0, [pc, #132] ; (800098c ) + 8000908: f002 f9cf bl 8002caa + 800090c: e020 b.n 8000950 } - // + // Set Door Lock State else if (uart_buffer[0] == 0x02) { - 80007f0: 4b12 ldr r3, [pc, #72] ; (800083c ) - 80007f2: 781b ldrb r3, [r3, #0] - 80007f4: 2b02 cmp r3, #2 - 80007f6: d108 bne.n 800080a + 800090e: 4b1d ldr r3, [pc, #116] ; (8000984 ) + 8000910: 781b ldrb r3, [r3, #0] + 8000912: 2b02 cmp r3, #2 + 8000914: d109 bne.n 800092a door_lock_state_command = uart_buffer[1]; - 80007f8: 4b10 ldr r3, [pc, #64] ; (800083c ) - 80007fa: 785b ldrb r3, [r3, #1] - 80007fc: 2b00 cmp r3, #0 - 80007fe: bf14 ite ne - 8000800: 2301 movne r3, #1 - 8000802: 2300 moveq r3, #0 - 8000804: b2da uxtb r2, r3 - 8000806: 4b12 ldr r3, [pc, #72] ; (8000850 ) - 8000808: 701a strb r2, [r3, #0] + 8000916: 4b1b ldr r3, [pc, #108] ; (8000984 ) + 8000918: 785b ldrb r3, [r3, #1] + 800091a: 2b00 cmp r3, #0 + 800091c: bf14 ite ne + 800091e: 2301 movne r3, #1 + 8000920: 2300 moveq r3, #0 + 8000922: b2da uxtb r2, r3 + 8000924: 4b1c ldr r3, [pc, #112] ; (8000998 ) + 8000926: 701a strb r2, [r3, #0] + 8000928: e012 b.n 8000950 + // Get Current Scan Active State + } else if (uart_buffer[0] == 0x03) { + 800092a: 4b16 ldr r3, [pc, #88] ; (8000984 ) + 800092c: 781b ldrb r3, [r3, #0] + 800092e: 2b03 cmp r3, #3 + 8000930: d10e bne.n 8000950 + uint8_t payload[3] = { 0x02, scan_active, 0xFF }; + 8000932: 2302 movs r3, #2 + 8000934: 723b strb r3, [r7, #8] + 8000936: 4b19 ldr r3, [pc, #100] ; (800099c ) + 8000938: 781b ldrb r3, [r3, #0] + 800093a: 727b strb r3, [r7, #9] + 800093c: 23ff movs r3, #255 ; 0xff + 800093e: 72bb strb r3, [r7, #10] + HAL_UART_Transmit(&huart2, payload, 3, 1500); + 8000940: f107 0108 add.w r1, r7, #8 + 8000944: f240 53dc movw r3, #1500 ; 0x5dc + 8000948: 2203 movs r2, #3 + 800094a: 4810 ldr r0, [pc, #64] ; (800098c ) + 800094c: f002 f9ad bl 8002caa } } uart_index = 0; - 800080a: 4b0d ldr r3, [pc, #52] ; (8000840 ) - 800080c: 2200 movs r2, #0 - 800080e: 701a strb r2, [r3, #0] + 8000950: 4b0d ldr r3, [pc, #52] ; (8000988 ) + 8000952: 2200 movs r2, #0 + 8000954: 701a strb r2, [r3, #0] memset(uart_buffer, 0, 10); - 8000810: 220a movs r2, #10 - 8000812: 2100 movs r1, #0 - 8000814: 4809 ldr r0, [pc, #36] ; (800083c ) - 8000816: f004 fe61 bl 80054dc - 800081a: e00b b.n 8000834 + 8000956: 220a movs r2, #10 + 8000958: 2100 movs r1, #0 + 800095a: 480a ldr r0, [pc, #40] ; (8000984 ) + 800095c: f005 fb7e bl 800605c + 8000960: e00b b.n 800097a } else if (uart_index > sizeof(uart_buffer) - 1) { - 800081c: 4b08 ldr r3, [pc, #32] ; (8000840 ) - 800081e: 781b ldrb r3, [r3, #0] - 8000820: 2b09 cmp r3, #9 - 8000822: d907 bls.n 8000834 + 8000962: 4b09 ldr r3, [pc, #36] ; (8000988 ) + 8000964: 781b ldrb r3, [r3, #0] + 8000966: 2b09 cmp r3, #9 + 8000968: d907 bls.n 800097a memset(uart_buffer, 0, 10); - 8000824: 220a movs r2, #10 - 8000826: 2100 movs r1, #0 - 8000828: 4804 ldr r0, [pc, #16] ; (800083c ) - 800082a: f004 fe57 bl 80054dc + 800096a: 220a movs r2, #10 + 800096c: 2100 movs r1, #0 + 800096e: 4805 ldr r0, [pc, #20] ; (8000984 ) + 8000970: f005 fb74 bl 800605c uart_index = 0; - 800082e: 4b04 ldr r3, [pc, #16] ; (8000840 ) - 8000830: 2200 movs r2, #0 - 8000832: 701a strb r2, [r3, #0] + 8000974: 4b04 ldr r3, [pc, #16] ; (8000988 ) + 8000976: 2200 movs r2, #0 + 8000978: 701a strb r2, [r3, #0] } } vTaskDelay(1); - 8000834: 2001 movs r0, #1 - 8000836: f003 f959 bl 8003aec - if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 1000) - 800083a: e79a b.n 8000772 - 800083c: 200000c8 .word 0x200000c8 - 8000840: 200000d2 .word 0x200000d2 - 8000844: 2000007c .word 0x2000007c - 8000848: 40020000 .word 0x40020000 - 800084c: 200000d8 .word 0x200000d8 - 8000850: 200000da .word 0x200000da + 800097a: 2001 movs r0, #1 + 800097c: f003 fe74 bl 8004668 + if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 100) + 8000980: e787 b.n 8000892 + 8000982: bf00 nop + 8000984: 20000118 .word 0x20000118 + 8000988: 20000122 .word 0x20000122 + 800098c: 200000c4 .word 0x200000c4 + 8000990: 40020000 .word 0x40020000 + 8000994: 20000128 .word 0x20000128 + 8000998: 2000012a .word 0x2000012a + 800099c: 2000012d .word 0x2000012d -08000854 : - * @brief Function implementing the doorHandler thread. +080009a0 : * @param argument: Not used * @retval None */ /* USER CODE END Header_startDoorHandleTask */ -void startDoorHandleTask(void *argument) { - 8000854: b580 push {r7, lr} - 8000856: b082 sub sp, #8 - 8000858: af00 add r7, sp, #0 - 800085a: 6078 str r0, [r7, #4] - /* USER CODE BEGIN startDoorHandleTask */ +void startDoorHandleTask(void *argument) +{ + 80009a0: b580 push {r7, lr} + 80009a2: b082 sub sp, #8 + 80009a4: af00 add r7, sp, #0 + 80009a6: 6078 str r0, [r7, #4] + /* USER CODE BEGIN startDoorHandleTask */ /* Infinite loop */ for (;;) { door_state = HAL_GPIO_ReadPin(DOOR_SENSOR_BANK, DOOR_SENSOR_PIN); - 800085c: 2180 movs r1, #128 ; 0x80 - 800085e: 4854 ldr r0, [pc, #336] ; (80009b0 ) - 8000860: f000 fcb8 bl 80011d4 - 8000864: 4603 mov r3, r0 - 8000866: 2b00 cmp r3, #0 - 8000868: bf14 ite ne - 800086a: 2301 movne r3, #1 - 800086c: 2300 moveq r3, #0 - 800086e: b2da uxtb r2, r3 - 8000870: 4b50 ldr r3, [pc, #320] ; (80009b4 ) - 8000872: 701a strb r2, [r3, #0] + 80009a8: 2180 movs r1, #128 ; 0x80 + 80009aa: 4854 ldr r0, [pc, #336] ; (8000afc ) + 80009ac: f001 f9b4 bl 8001d18 + 80009b0: 4603 mov r3, r0 + 80009b2: 2b00 cmp r3, #0 + 80009b4: bf14 ite ne + 80009b6: 2301 movne r3, #1 + 80009b8: 2300 moveq r3, #0 + 80009ba: b2da uxtb r2, r3 + 80009bc: 4b50 ldr r3, [pc, #320] ; (8000b00 ) + 80009be: 701a strb r2, [r3, #0] if (door_lock_state != door_lock_state_command) { - 8000874: 4b50 ldr r3, [pc, #320] ; (80009b8 ) - 8000876: 781a ldrb r2, [r3, #0] - 8000878: 4b50 ldr r3, [pc, #320] ; (80009bc ) - 800087a: 781b ldrb r3, [r3, #0] - 800087c: 429a cmp r2, r3 - 800087e: d05e beq.n 800093e + 80009c0: 4b50 ldr r3, [pc, #320] ; (8000b04 ) + 80009c2: 781a ldrb r2, [r3, #0] + 80009c4: 4b50 ldr r3, [pc, #320] ; (8000b08 ) + 80009c6: 781b ldrb r3, [r3, #0] + 80009c8: 429a cmp r2, r3 + 80009ca: d05e beq.n 8000a8a if (door_lock_state_command == DOOR_LOCK_LOCKED) { - 8000880: 4b4e ldr r3, [pc, #312] ; (80009bc ) - 8000882: 781b ldrb r3, [r3, #0] - 8000884: 2b00 cmp r3, #0 - 8000886: d047 beq.n 8000918 + 80009cc: 4b4e ldr r3, [pc, #312] ; (8000b08 ) + 80009ce: 781b ldrb r3, [r3, #0] + 80009d0: 2b00 cmp r3, #0 + 80009d2: d047 beq.n 8000a64 if (door_state == DOOR_STATE_CLOSED) { - 8000888: 4b4a ldr r3, [pc, #296] ; (80009b4 ) - 800088a: 781b ldrb r3, [r3, #0] - 800088c: 2b00 cmp r3, #0 - 800088e: d00c beq.n 80008aa + 80009d4: 4b4a ldr r3, [pc, #296] ; (8000b00 ) + 80009d6: 781b ldrb r3, [r3, #0] + 80009d8: 2b00 cmp r3, #0 + 80009da: d00c beq.n 80009f6 HAL_GPIO_WritePin(DOOR_LOCK_BANK, DOOR_LOCK_PIN, 1); - 8000890: 2201 movs r2, #1 - 8000892: f44f 7100 mov.w r1, #512 ; 0x200 - 8000896: 4846 ldr r0, [pc, #280] ; (80009b0 ) - 8000898: f000 fcb4 bl 8001204 + 80009dc: 2201 movs r2, #1 + 80009de: f44f 7100 mov.w r1, #512 ; 0x200 + 80009e2: 4846 ldr r0, [pc, #280] ; (8000afc ) + 80009e4: f001 f9b0 bl 8001d48 door_lock_state = DOOR_LOCK_LOCKED; - 800089c: 4b46 ldr r3, [pc, #280] ; (80009b8 ) - 800089e: 2201 movs r2, #1 - 80008a0: 701a strb r2, [r3, #0] + 80009e8: 4b46 ldr r3, [pc, #280] ; (8000b04 ) + 80009ea: 2201 movs r2, #1 + 80009ec: 701a strb r2, [r3, #0] door_lock_waiting = false; - 80008a2: 4b47 ldr r3, [pc, #284] ; (80009c0 ) - 80008a4: 2200 movs r2, #0 - 80008a6: 701a strb r2, [r3, #0] - 80008a8: e049 b.n 800093e + 80009ee: 4b47 ldr r3, [pc, #284] ; (8000b0c ) + 80009f0: 2200 movs r2, #0 + 80009f2: 701a strb r2, [r3, #0] + 80009f4: e049 b.n 8000a8a } else { if (!door_lock_waiting) { - 80008aa: 4b45 ldr r3, [pc, #276] ; (80009c0 ) - 80008ac: 781b ldrb r3, [r3, #0] - 80008ae: f083 0301 eor.w r3, r3, #1 - 80008b2: b2db uxtb r3, r3 - 80008b4: 2b00 cmp r3, #0 - 80008b6: d008 beq.n 80008ca + 80009f6: 4b45 ldr r3, [pc, #276] ; (8000b0c ) + 80009f8: 781b ldrb r3, [r3, #0] + 80009fa: f083 0301 eor.w r3, r3, #1 + 80009fe: b2db uxtb r3, r3 + 8000a00: 2b00 cmp r3, #0 + 8000a02: d008 beq.n 8000a16 door_lock_command_time = HAL_GetTick(); - 80008b8: f000 fa1a bl 8000cf0 - 80008bc: 4603 mov r3, r0 - 80008be: 4a41 ldr r2, [pc, #260] ; (80009c4 ) - 80008c0: 6013 str r3, [r2, #0] + 8000a04: f000 faaa bl 8000f5c + 8000a08: 4603 mov r3, r0 + 8000a0a: 4a41 ldr r2, [pc, #260] ; (8000b10 ) + 8000a0c: 6013 str r3, [r2, #0] door_lock_waiting = true; - 80008c2: 4b3f ldr r3, [pc, #252] ; (80009c0 ) - 80008c4: 2201 movs r2, #1 - 80008c6: 701a strb r2, [r3, #0] - 80008c8: e039 b.n 800093e + 8000a0e: 4b3f ldr r3, [pc, #252] ; (8000b0c ) + 8000a10: 2201 movs r2, #1 + 8000a12: 701a strb r2, [r3, #0] + 8000a14: e039 b.n 8000a8a } else { if (door_state == DOOR_STATE_OPEN) { - 80008ca: 4b3a ldr r3, [pc, #232] ; (80009b4 ) - 80008cc: 781b ldrb r3, [r3, #0] - 80008ce: f083 0301 eor.w r3, r3, #1 - 80008d2: b2db uxtb r3, r3 - 80008d4: 2b00 cmp r3, #0 - 80008d6: d012 beq.n 80008fe + 8000a16: 4b3a ldr r3, [pc, #232] ; (8000b00 ) + 8000a18: 781b ldrb r3, [r3, #0] + 8000a1a: f083 0301 eor.w r3, r3, #1 + 8000a1e: b2db uxtb r3, r3 + 8000a20: 2b00 cmp r3, #0 + 8000a22: d012 beq.n 8000a4a if (HAL_GetTick() - 80008d8: f000 fa0a bl 8000cf0 - 80008dc: 4602 mov r2, r0 + 8000a24: f000 fa9a bl 8000f5c + 8000a28: 4602 mov r2, r0 - door_lock_command_time>DOOR_ERROR_ALARM_DELAY) { - 80008de: 4b39 ldr r3, [pc, #228] ; (80009c4 ) - 80008e0: 681b ldr r3, [r3, #0] - 80008e2: 1ad3 subs r3, r2, r3 + 8000a2a: 4b39 ldr r3, [pc, #228] ; (8000b10 ) + 8000a2c: 681b ldr r3, [r3, #0] + 8000a2e: 1ad3 subs r3, r2, r3 if (HAL_GetTick() - 80008e4: f242 7210 movw r2, #10000 ; 0x2710 - 80008e8: 4293 cmp r3, r2 - 80008ea: d928 bls.n 800093e + 8000a30: f242 7210 movw r2, #10000 ; 0x2710 + 8000a34: 4293 cmp r3, r2 + 8000a36: d928 bls.n 8000a8a alarm_active = true; - 80008ec: 4b36 ldr r3, [pc, #216] ; (80009c8 ) - 80008ee: 2201 movs r2, #1 - 80008f0: 701a strb r2, [r3, #0] + 8000a38: 4b36 ldr r3, [pc, #216] ; (8000b14 ) + 8000a3a: 2201 movs r2, #1 + 8000a3c: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(ALARM_BANK, ALARM_PIN, 1); - 80008f2: 2201 movs r2, #1 - 80008f4: 2101 movs r1, #1 - 80008f6: 4835 ldr r0, [pc, #212] ; (80009cc ) - 80008f8: f000 fc84 bl 8001204 - 80008fc: e01f b.n 800093e + 8000a3e: 2201 movs r2, #1 + 8000a40: 2101 movs r1, #1 + 8000a42: 4835 ldr r0, [pc, #212] ; (8000b18 ) + 8000a44: f001 f980 bl 8001d48 + 8000a48: e01f b.n 8000a8a } } else { HAL_GPIO_WritePin(DOOR_LOCK_BANK, DOOR_LOCK_PIN, 1); - 80008fe: 2201 movs r2, #1 - 8000900: f44f 7100 mov.w r1, #512 ; 0x200 - 8000904: 482a ldr r0, [pc, #168] ; (80009b0 ) - 8000906: f000 fc7d bl 8001204 + 8000a4a: 2201 movs r2, #1 + 8000a4c: f44f 7100 mov.w r1, #512 ; 0x200 + 8000a50: 482a ldr r0, [pc, #168] ; (8000afc ) + 8000a52: f001 f979 bl 8001d48 door_lock_waiting = false; - 800090a: 4b2d ldr r3, [pc, #180] ; (80009c0 ) - 800090c: 2200 movs r2, #0 - 800090e: 701a strb r2, [r3, #0] + 8000a56: 4b2d ldr r3, [pc, #180] ; (8000b0c ) + 8000a58: 2200 movs r2, #0 + 8000a5a: 701a strb r2, [r3, #0] door_lock_state = DOOR_LOCK_LOCKED; - 8000910: 4b29 ldr r3, [pc, #164] ; (80009b8 ) - 8000912: 2201 movs r2, #1 - 8000914: 701a strb r2, [r3, #0] - 8000916: e012 b.n 800093e + 8000a5c: 4b29 ldr r3, [pc, #164] ; (8000b04 ) + 8000a5e: 2201 movs r2, #1 + 8000a60: 701a strb r2, [r3, #0] + 8000a62: e012 b.n 8000a8a } } } } else if (door_lock_state_command == DOOR_LOCK_UNLOCKED) { - 8000918: 4b28 ldr r3, [pc, #160] ; (80009bc ) - 800091a: 781b ldrb r3, [r3, #0] - 800091c: f083 0301 eor.w r3, r3, #1 - 8000920: b2db uxtb r3, r3 - 8000922: 2b00 cmp r3, #0 - 8000924: d00b beq.n 800093e + 8000a64: 4b28 ldr r3, [pc, #160] ; (8000b08 ) + 8000a66: 781b ldrb r3, [r3, #0] + 8000a68: f083 0301 eor.w r3, r3, #1 + 8000a6c: b2db uxtb r3, r3 + 8000a6e: 2b00 cmp r3, #0 + 8000a70: d00b beq.n 8000a8a HAL_GPIO_WritePin(DOOR_LOCK_BANK, DOOR_LOCK_PIN, 0); - 8000926: 2200 movs r2, #0 - 8000928: f44f 7100 mov.w r1, #512 ; 0x200 - 800092c: 4820 ldr r0, [pc, #128] ; (80009b0 ) - 800092e: f000 fc69 bl 8001204 + 8000a72: 2200 movs r2, #0 + 8000a74: f44f 7100 mov.w r1, #512 ; 0x200 + 8000a78: 4820 ldr r0, [pc, #128] ; (8000afc ) + 8000a7a: f001 f965 bl 8001d48 door_lock_state = DOOR_LOCK_UNLOCKED; - 8000932: 4b21 ldr r3, [pc, #132] ; (80009b8 ) - 8000934: 2200 movs r2, #0 - 8000936: 701a strb r2, [r3, #0] + 8000a7e: 4b21 ldr r3, [pc, #132] ; (8000b04 ) + 8000a80: 2200 movs r2, #0 + 8000a82: 701a strb r2, [r3, #0] door_lock_waiting = false; - 8000938: 4b21 ldr r3, [pc, #132] ; (80009c0 ) - 800093a: 2200 movs r2, #0 - 800093c: 701a strb r2, [r3, #0] + 8000a84: 4b21 ldr r3, [pc, #132] ; (8000b0c ) + 8000a86: 2200 movs r2, #0 + 8000a88: 701a strb r2, [r3, #0] } } - if(!door_lock_state_command && door_lock_waiting) { - 800093e: 4b1f ldr r3, [pc, #124] ; (80009bc ) - 8000940: 781b ldrb r3, [r3, #0] - 8000942: f083 0301 eor.w r3, r3, #1 - 8000946: b2db uxtb r3, r3 - 8000948: 2b00 cmp r3, #0 - 800094a: d006 beq.n 800095a - 800094c: 4b1c ldr r3, [pc, #112] ; (80009c0 ) - 800094e: 781b ldrb r3, [r3, #0] - 8000950: 2b00 cmp r3, #0 - 8000952: d002 beq.n 800095a + if (!door_lock_state_command && door_lock_waiting) { + 8000a8a: 4b1f ldr r3, [pc, #124] ; (8000b08 ) + 8000a8c: 781b ldrb r3, [r3, #0] + 8000a8e: f083 0301 eor.w r3, r3, #1 + 8000a92: b2db uxtb r3, r3 + 8000a94: 2b00 cmp r3, #0 + 8000a96: d006 beq.n 8000aa6 + 8000a98: 4b1c ldr r3, [pc, #112] ; (8000b0c ) + 8000a9a: 781b ldrb r3, [r3, #0] + 8000a9c: 2b00 cmp r3, #0 + 8000a9e: d002 beq.n 8000aa6 door_lock_waiting = false; - 8000954: 4b1a ldr r3, [pc, #104] ; (80009c0 ) - 8000956: 2200 movs r2, #0 - 8000958: 701a strb r2, [r3, #0] + 8000aa0: 4b1a ldr r3, [pc, #104] ; (8000b0c ) + 8000aa2: 2200 movs r2, #0 + 8000aa4: 701a strb r2, [r3, #0] } if (alarm_active && !door_lock_state_command) { - 800095a: 4b1b ldr r3, [pc, #108] ; (80009c8 ) - 800095c: 781b ldrb r3, [r3, #0] - 800095e: 2b00 cmp r3, #0 - 8000960: d00e beq.n 8000980 - 8000962: 4b16 ldr r3, [pc, #88] ; (80009bc ) - 8000964: 781b ldrb r3, [r3, #0] - 8000966: f083 0301 eor.w r3, r3, #1 - 800096a: b2db uxtb r3, r3 - 800096c: 2b00 cmp r3, #0 - 800096e: d007 beq.n 8000980 + 8000aa6: 4b1b ldr r3, [pc, #108] ; (8000b14 ) + 8000aa8: 781b ldrb r3, [r3, #0] + 8000aaa: 2b00 cmp r3, #0 + 8000aac: d00e beq.n 8000acc + 8000aae: 4b16 ldr r3, [pc, #88] ; (8000b08 ) + 8000ab0: 781b ldrb r3, [r3, #0] + 8000ab2: f083 0301 eor.w r3, r3, #1 + 8000ab6: b2db uxtb r3, r3 + 8000ab8: 2b00 cmp r3, #0 + 8000aba: d007 beq.n 8000acc HAL_GPIO_WritePin(ALARM_BANK, ALARM_PIN, 0); - 8000970: 2200 movs r2, #0 - 8000972: 2101 movs r1, #1 - 8000974: 4815 ldr r0, [pc, #84] ; (80009cc ) - 8000976: f000 fc45 bl 8001204 + 8000abc: 2200 movs r2, #0 + 8000abe: 2101 movs r1, #1 + 8000ac0: 4815 ldr r0, [pc, #84] ; (8000b18 ) + 8000ac2: f001 f941 bl 8001d48 alarm_active = false; - 800097a: 4b13 ldr r3, [pc, #76] ; (80009c8 ) - 800097c: 2200 movs r2, #0 - 800097e: 701a strb r2, [r3, #0] + 8000ac6: 4b13 ldr r3, [pc, #76] ; (8000b14 ) + 8000ac8: 2200 movs r2, #0 + 8000aca: 701a strb r2, [r3, #0] } if (!door_state && door_lock_state) { - 8000980: 4b0c ldr r3, [pc, #48] ; (80009b4 ) - 8000982: 781b ldrb r3, [r3, #0] - 8000984: f083 0301 eor.w r3, r3, #1 - 8000988: b2db uxtb r3, r3 - 800098a: 2b00 cmp r3, #0 - 800098c: d00b beq.n 80009a6 - 800098e: 4b0a ldr r3, [pc, #40] ; (80009b8 ) - 8000990: 781b ldrb r3, [r3, #0] - 8000992: 2b00 cmp r3, #0 - 8000994: d007 beq.n 80009a6 + 8000acc: 4b0c ldr r3, [pc, #48] ; (8000b00 ) + 8000ace: 781b ldrb r3, [r3, #0] + 8000ad0: f083 0301 eor.w r3, r3, #1 + 8000ad4: b2db uxtb r3, r3 + 8000ad6: 2b00 cmp r3, #0 + 8000ad8: d00b beq.n 8000af2 + 8000ada: 4b0a ldr r3, [pc, #40] ; (8000b04 ) + 8000adc: 781b ldrb r3, [r3, #0] + 8000ade: 2b00 cmp r3, #0 + 8000ae0: d007 beq.n 8000af2 HAL_GPIO_WritePin(ALARM_BANK, ALARM_PIN, 1); - 8000996: 2201 movs r2, #1 - 8000998: 2101 movs r1, #1 - 800099a: 480c ldr r0, [pc, #48] ; (80009cc ) - 800099c: f000 fc32 bl 8001204 + 8000ae2: 2201 movs r2, #1 + 8000ae4: 2101 movs r1, #1 + 8000ae6: 480c ldr r0, [pc, #48] ; (8000b18 ) + 8000ae8: f001 f92e bl 8001d48 alarm_active = true; - 80009a0: 4b09 ldr r3, [pc, #36] ; (80009c8 ) - 80009a2: 2201 movs r2, #1 - 80009a4: 701a strb r2, [r3, #0] + 8000aec: 4b09 ldr r3, [pc, #36] ; (8000b14 ) + 8000aee: 2201 movs r2, #1 + 8000af0: 701a strb r2, [r3, #0] } - //HAL_GPIO_WritePin(DOOR_LOCK_PIN, DOOR_LOCK_BANK, uart_buffer[1]); vTaskDelay(50); - 80009a6: 2032 movs r0, #50 ; 0x32 - 80009a8: f003 f8a0 bl 8003aec + 8000af2: 2032 movs r0, #50 ; 0x32 + 8000af4: f003 fdb8 bl 8004668 door_state = HAL_GPIO_ReadPin(DOOR_SENSOR_BANK, DOOR_SENSOR_PIN); - 80009ac: e756 b.n 800085c - 80009ae: bf00 nop - 80009b0: 40020000 .word 0x40020000 - 80009b4: 200000d8 .word 0x200000d8 - 80009b8: 200000d9 .word 0x200000d9 - 80009bc: 200000da .word 0x200000da - 80009c0: 200000db .word 0x200000db - 80009c4: 200000d4 .word 0x200000d4 - 80009c8: 200000dc .word 0x200000dc - 80009cc: 40020800 .word 0x40020800 + 8000af8: e756 b.n 80009a8 + 8000afa: bf00 nop + 8000afc: 40020000 .word 0x40020000 + 8000b00: 20000128 .word 0x20000128 + 8000b04: 20000129 .word 0x20000129 + 8000b08: 2000012a .word 0x2000012a + 8000b0c: 2000012b .word 0x2000012b + 8000b10: 20000124 .word 0x20000124 + 8000b14: 2000012c .word 0x2000012c + 8000b18: 40020800 .word 0x40020800 -080009d0 : - * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param htim : TIM handle +08000b1c : + * @param argument: Not used * @retval None */ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { - 80009d0: b580 push {r7, lr} - 80009d2: b082 sub sp, #8 - 80009d4: af00 add r7, sp, #0 - 80009d6: 6078 str r0, [r7, #4] - /* USER CODE BEGIN Callback 0 */ +/* USER CODE END Header_StartStateSendTask */ +void StartStateSendTask(void *argument) +{ + 8000b1c: b580 push {r7, lr} + 8000b1e: b084 sub sp, #16 + 8000b20: af00 add r7, sp, #0 + 8000b22: 6078 str r0, [r7, #4] + /* USER CODE BEGIN StartStateSendTask */ + /* Infinite loop */ + for (;;) { + uint8_t payload1[3] = { 0x01, door_state, 0xFF }; + 8000b24: 2301 movs r3, #1 + 8000b26: 733b strb r3, [r7, #12] + 8000b28: 4b0f ldr r3, [pc, #60] ; (8000b68 ) + 8000b2a: 781b ldrb r3, [r3, #0] + 8000b2c: 737b strb r3, [r7, #13] + 8000b2e: 23ff movs r3, #255 ; 0xff + 8000b30: 73bb strb r3, [r7, #14] + HAL_UART_Transmit(&huart2, payload1, 3, 1000); + 8000b32: f107 010c add.w r1, r7, #12 + 8000b36: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8000b3a: 2203 movs r2, #3 + 8000b3c: 480b ldr r0, [pc, #44] ; (8000b6c ) + 8000b3e: f002 f8b4 bl 8002caa + uint8_t payload2[3] = { 0x02, scan_active, 0xFF }; + 8000b42: 2302 movs r3, #2 + 8000b44: 723b strb r3, [r7, #8] + 8000b46: 4b0a ldr r3, [pc, #40] ; (8000b70 ) + 8000b48: 781b ldrb r3, [r3, #0] + 8000b4a: 727b strb r3, [r7, #9] + 8000b4c: 23ff movs r3, #255 ; 0xff + 8000b4e: 72bb strb r3, [r7, #10] + HAL_UART_Transmit(&huart2, payload2, 3, 1000); + 8000b50: f107 0108 add.w r1, r7, #8 + 8000b54: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8000b58: 2203 movs r2, #3 + 8000b5a: 4804 ldr r0, [pc, #16] ; (8000b6c ) + 8000b5c: f002 f8a5 bl 8002caa + osDelay(200); + 8000b60: 20c8 movs r0, #200 ; 0xc8 + 8000b62: f002 fdd9 bl 8003718 + for (;;) { + 8000b66: e7dd b.n 8000b24 + 8000b68: 20000128 .word 0x20000128 + 8000b6c: 200000c4 .word 0x200000c4 + 8000b70: 2000012d .word 0x2000012d - /* USER CODE END Callback 0 */ - if (htim->Instance == TIM1) { - 80009d8: 687b ldr r3, [r7, #4] - 80009da: 681b ldr r3, [r3, #0] - 80009dc: 4a04 ldr r2, [pc, #16] ; (80009f0 ) - 80009de: 4293 cmp r3, r2 - 80009e0: d101 bne.n 80009e6 - HAL_IncTick(); - 80009e2: f000 f971 bl 8000cc8 - } - /* USER CODE BEGIN Callback 1 */ +08000b74 : +* @param argument: Not used +* @retval None +*/ +/* USER CODE END Header_StartADCReqTask */ +void StartADCReqTask(void *argument) +{ + 8000b74: b580 push {r7, lr} + 8000b76: b082 sub sp, #8 + 8000b78: af00 add r7, sp, #0 + 8000b7a: 6078 str r0, [r7, #4] + /* USER CODE BEGIN StartADCReqTask */ + /* Infinite loop */ + for(;;) + { + HAL_ADC_Start_IT(&hadc1); + 8000b7c: 4803 ldr r0, [pc, #12] ; (8000b8c ) + 8000b7e: f000 fa3d bl 8000ffc + osDelay(500); + 8000b82: f44f 70fa mov.w r0, #500 ; 0x1f4 + 8000b86: f002 fdc7 bl 8003718 + HAL_ADC_Start_IT(&hadc1); + 8000b8a: e7f7 b.n 8000b7c + 8000b8c: 2000007c .word 0x2000007c - /* USER CODE END Callback 1 */ +08000b90 : + * a global variable "uwTick" used as application time base. + * @param htim : TIM handle + * @retval None + */ +void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) +{ + 8000b90: b580 push {r7, lr} + 8000b92: b082 sub sp, #8 + 8000b94: af00 add r7, sp, #0 + 8000b96: 6078 str r0, [r7, #4] + /* USER CODE BEGIN Callback 0 */ + + /* USER CODE END Callback 0 */ + if (htim->Instance == TIM1) { + 8000b98: 687b ldr r3, [r7, #4] + 8000b9a: 681b ldr r3, [r3, #0] + 8000b9c: 4a04 ldr r2, [pc, #16] ; (8000bb0 ) + 8000b9e: 4293 cmp r3, r2 + 8000ba0: d101 bne.n 8000ba6 + HAL_IncTick(); + 8000ba2: f000 f9c7 bl 8000f34 + } + /* USER CODE BEGIN Callback 1 */ + + /* USER CODE END Callback 1 */ } - 80009e6: bf00 nop - 80009e8: 3708 adds r7, #8 - 80009ea: 46bd mov sp, r7 - 80009ec: bd80 pop {r7, pc} - 80009ee: bf00 nop - 80009f0: 40010000 .word 0x40010000 - -080009f4 : + 8000ba6: bf00 nop + 8000ba8: 3708 adds r7, #8 + 8000baa: 46bd mov sp, r7 + 8000bac: bd80 pop {r7, pc} + 8000bae: bf00 nop + 8000bb0: 40010000 .word 0x40010000 +08000bb4 : /** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) { - 80009f4: b480 push {r7} - 80009f6: af00 add r7, sp, #0 + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8000bb4: b480 push {r7} + 8000bb6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); - 80009f8: b672 cpsid i + 8000bb8: b672 cpsid i } - 80009fa: bf00 nop - /* USER CODE BEGIN Error_Handler_Debug */ + 8000bba: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) { - 80009fc: e7fe b.n 80009fc + 8000bbc: e7fe b.n 8000bbc ... -08000a00 : +08000bc0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { - 8000a00: b580 push {r7, lr} - 8000a02: b082 sub sp, #8 - 8000a04: af00 add r7, sp, #0 + 8000bc0: b580 push {r7, lr} + 8000bc2: b082 sub sp, #8 + 8000bc4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8000a06: 2300 movs r3, #0 - 8000a08: 607b str r3, [r7, #4] - 8000a0a: 4b12 ldr r3, [pc, #72] ; (8000a54 ) - 8000a0c: 6c5b ldr r3, [r3, #68] ; 0x44 - 8000a0e: 4a11 ldr r2, [pc, #68] ; (8000a54 ) - 8000a10: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8000a14: 6453 str r3, [r2, #68] ; 0x44 - 8000a16: 4b0f ldr r3, [pc, #60] ; (8000a54 ) - 8000a18: 6c5b ldr r3, [r3, #68] ; 0x44 - 8000a1a: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 8000a1e: 607b str r3, [r7, #4] - 8000a20: 687b ldr r3, [r7, #4] + 8000bc6: 2300 movs r3, #0 + 8000bc8: 607b str r3, [r7, #4] + 8000bca: 4b12 ldr r3, [pc, #72] ; (8000c14 ) + 8000bcc: 6c5b ldr r3, [r3, #68] ; 0x44 + 8000bce: 4a11 ldr r2, [pc, #68] ; (8000c14 ) + 8000bd0: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8000bd4: 6453 str r3, [r2, #68] ; 0x44 + 8000bd6: 4b0f ldr r3, [pc, #60] ; (8000c14 ) + 8000bd8: 6c5b ldr r3, [r3, #68] ; 0x44 + 8000bda: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8000bde: 607b str r3, [r7, #4] + 8000be0: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); - 8000a22: 2300 movs r3, #0 - 8000a24: 603b str r3, [r7, #0] - 8000a26: 4b0b ldr r3, [pc, #44] ; (8000a54 ) - 8000a28: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000a2a: 4a0a ldr r2, [pc, #40] ; (8000a54 ) - 8000a2c: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 8000a30: 6413 str r3, [r2, #64] ; 0x40 - 8000a32: 4b08 ldr r3, [pc, #32] ; (8000a54 ) - 8000a34: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000a36: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 8000a3a: 603b str r3, [r7, #0] - 8000a3c: 683b ldr r3, [r7, #0] + 8000be2: 2300 movs r3, #0 + 8000be4: 603b str r3, [r7, #0] + 8000be6: 4b0b ldr r3, [pc, #44] ; (8000c14 ) + 8000be8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000bea: 4a0a ldr r2, [pc, #40] ; (8000c14 ) + 8000bec: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8000bf0: 6413 str r3, [r2, #64] ; 0x40 + 8000bf2: 4b08 ldr r3, [pc, #32] ; (8000c14 ) + 8000bf4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000bf6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8000bfa: 603b str r3, [r7, #0] + 8000bfc: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0); - 8000a3e: 2200 movs r2, #0 - 8000a40: 210f movs r1, #15 - 8000a42: f06f 0001 mvn.w r0, #1 - 8000a46: f000 fa17 bl 8000e78 + 8000bfe: 2200 movs r2, #0 + 8000c00: 210f movs r1, #15 + 8000c02: f06f 0001 mvn.w r0, #1 + 8000c06: f000 fed9 bl 80019bc /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } - 8000a4a: bf00 nop - 8000a4c: 3708 adds r7, #8 - 8000a4e: 46bd mov sp, r7 - 8000a50: bd80 pop {r7, pc} - 8000a52: bf00 nop - 8000a54: 40023800 .word 0x40023800 + 8000c0a: bf00 nop + 8000c0c: 3708 adds r7, #8 + 8000c0e: 46bd mov sp, r7 + 8000c10: bd80 pop {r7, pc} + 8000c12: bf00 nop + 8000c14: 40023800 .word 0x40023800 -08000a58 : +08000c18 : +* This function configures the hardware resources used in this example +* @param hadc: ADC handle pointer +* @retval None +*/ +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + 8000c18: b580 push {r7, lr} + 8000c1a: b08a sub sp, #40 ; 0x28 + 8000c1c: af00 add r7, sp, #0 + 8000c1e: 6078 str r0, [r7, #4] + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000c20: f107 0314 add.w r3, r7, #20 + 8000c24: 2200 movs r2, #0 + 8000c26: 601a str r2, [r3, #0] + 8000c28: 605a str r2, [r3, #4] + 8000c2a: 609a str r2, [r3, #8] + 8000c2c: 60da str r2, [r3, #12] + 8000c2e: 611a str r2, [r3, #16] + if(hadc->Instance==ADC1) + 8000c30: 687b ldr r3, [r7, #4] + 8000c32: 681b ldr r3, [r3, #0] + 8000c34: 4a1b ldr r2, [pc, #108] ; (8000ca4 ) + 8000c36: 4293 cmp r3, r2 + 8000c38: d12f bne.n 8000c9a + { + /* USER CODE BEGIN ADC1_MspInit 0 */ + + /* USER CODE END ADC1_MspInit 0 */ + /* Peripheral clock enable */ + __HAL_RCC_ADC1_CLK_ENABLE(); + 8000c3a: 2300 movs r3, #0 + 8000c3c: 613b str r3, [r7, #16] + 8000c3e: 4b1a ldr r3, [pc, #104] ; (8000ca8 ) + 8000c40: 6c5b ldr r3, [r3, #68] ; 0x44 + 8000c42: 4a19 ldr r2, [pc, #100] ; (8000ca8 ) + 8000c44: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8000c48: 6453 str r3, [r2, #68] ; 0x44 + 8000c4a: 4b17 ldr r3, [pc, #92] ; (8000ca8 ) + 8000c4c: 6c5b ldr r3, [r3, #68] ; 0x44 + 8000c4e: f403 7380 and.w r3, r3, #256 ; 0x100 + 8000c52: 613b str r3, [r7, #16] + 8000c54: 693b ldr r3, [r7, #16] + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8000c56: 2300 movs r3, #0 + 8000c58: 60fb str r3, [r7, #12] + 8000c5a: 4b13 ldr r3, [pc, #76] ; (8000ca8 ) + 8000c5c: 6b1b ldr r3, [r3, #48] ; 0x30 + 8000c5e: 4a12 ldr r2, [pc, #72] ; (8000ca8 ) + 8000c60: f043 0301 orr.w r3, r3, #1 + 8000c64: 6313 str r3, [r2, #48] ; 0x30 + 8000c66: 4b10 ldr r3, [pc, #64] ; (8000ca8 ) + 8000c68: 6b1b ldr r3, [r3, #48] ; 0x30 + 8000c6a: f003 0301 and.w r3, r3, #1 + 8000c6e: 60fb str r3, [r7, #12] + 8000c70: 68fb ldr r3, [r7, #12] + /**ADC1 GPIO Configuration + PA1 ------> ADC1_IN1 + */ + GPIO_InitStruct.Pin = GPIO_PIN_1; + 8000c72: 2302 movs r3, #2 + 8000c74: 617b str r3, [r7, #20] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8000c76: 2303 movs r3, #3 + 8000c78: 61bb str r3, [r7, #24] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000c7a: 2300 movs r3, #0 + 8000c7c: 61fb str r3, [r7, #28] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 8000c7e: f107 0314 add.w r3, r7, #20 + 8000c82: 4619 mov r1, r3 + 8000c84: 4809 ldr r0, [pc, #36] ; (8000cac ) + 8000c86: f000 fec3 bl 8001a10 + + /* ADC1 interrupt Init */ + HAL_NVIC_SetPriority(ADC_IRQn, 5, 0); + 8000c8a: 2200 movs r2, #0 + 8000c8c: 2105 movs r1, #5 + 8000c8e: 2012 movs r0, #18 + 8000c90: f000 fe94 bl 80019bc + HAL_NVIC_EnableIRQ(ADC_IRQn); + 8000c94: 2012 movs r0, #18 + 8000c96: f000 fead bl 80019f4 + /* USER CODE BEGIN ADC1_MspInit 1 */ + + /* USER CODE END ADC1_MspInit 1 */ + } + +} + 8000c9a: bf00 nop + 8000c9c: 3728 adds r7, #40 ; 0x28 + 8000c9e: 46bd mov sp, r7 + 8000ca0: bd80 pop {r7, pc} + 8000ca2: bf00 nop + 8000ca4: 40012000 .word 0x40012000 + 8000ca8: 40023800 .word 0x40023800 + 8000cac: 40020000 .word 0x40020000 + +08000cb0 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { - 8000a58: b580 push {r7, lr} - 8000a5a: b08a sub sp, #40 ; 0x28 - 8000a5c: af00 add r7, sp, #0 - 8000a5e: 6078 str r0, [r7, #4] + 8000cb0: b580 push {r7, lr} + 8000cb2: b08a sub sp, #40 ; 0x28 + 8000cb4: af00 add r7, sp, #0 + 8000cb6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; - 8000a60: f107 0314 add.w r3, r7, #20 - 8000a64: 2200 movs r2, #0 - 8000a66: 601a str r2, [r3, #0] - 8000a68: 605a str r2, [r3, #4] - 8000a6a: 609a str r2, [r3, #8] - 8000a6c: 60da str r2, [r3, #12] - 8000a6e: 611a str r2, [r3, #16] + 8000cb8: f107 0314 add.w r3, r7, #20 + 8000cbc: 2200 movs r2, #0 + 8000cbe: 601a str r2, [r3, #0] + 8000cc0: 605a str r2, [r3, #4] + 8000cc2: 609a str r2, [r3, #8] + 8000cc4: 60da str r2, [r3, #12] + 8000cc6: 611a str r2, [r3, #16] if(huart->Instance==USART2) - 8000a70: 687b ldr r3, [r7, #4] - 8000a72: 681b ldr r3, [r3, #0] - 8000a74: 4a19 ldr r2, [pc, #100] ; (8000adc ) - 8000a76: 4293 cmp r3, r2 - 8000a78: d12b bne.n 8000ad2 + 8000cc8: 687b ldr r3, [r7, #4] + 8000cca: 681b ldr r3, [r3, #0] + 8000ccc: 4a19 ldr r2, [pc, #100] ; (8000d34 ) + 8000cce: 4293 cmp r3, r2 + 8000cd0: d12b bne.n 8000d2a { /* USER CODE BEGIN USART2_MspInit 0 */ /* USER CODE END USART2_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_USART2_CLK_ENABLE(); - 8000a7a: 2300 movs r3, #0 - 8000a7c: 613b str r3, [r7, #16] - 8000a7e: 4b18 ldr r3, [pc, #96] ; (8000ae0 ) - 8000a80: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000a82: 4a17 ldr r2, [pc, #92] ; (8000ae0 ) - 8000a84: f443 3300 orr.w r3, r3, #131072 ; 0x20000 - 8000a88: 6413 str r3, [r2, #64] ; 0x40 - 8000a8a: 4b15 ldr r3, [pc, #84] ; (8000ae0 ) - 8000a8c: 6c1b ldr r3, [r3, #64] ; 0x40 - 8000a8e: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8000a92: 613b str r3, [r7, #16] - 8000a94: 693b ldr r3, [r7, #16] + 8000cd2: 2300 movs r3, #0 + 8000cd4: 613b str r3, [r7, #16] + 8000cd6: 4b18 ldr r3, [pc, #96] ; (8000d38 ) + 8000cd8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000cda: 4a17 ldr r2, [pc, #92] ; (8000d38 ) + 8000cdc: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8000ce0: 6413 str r3, [r2, #64] ; 0x40 + 8000ce2: 4b15 ldr r3, [pc, #84] ; (8000d38 ) + 8000ce4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000ce6: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8000cea: 613b str r3, [r7, #16] + 8000cec: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); - 8000a96: 2300 movs r3, #0 - 8000a98: 60fb str r3, [r7, #12] - 8000a9a: 4b11 ldr r3, [pc, #68] ; (8000ae0 ) - 8000a9c: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000a9e: 4a10 ldr r2, [pc, #64] ; (8000ae0 ) - 8000aa0: f043 0301 orr.w r3, r3, #1 - 8000aa4: 6313 str r3, [r2, #48] ; 0x30 - 8000aa6: 4b0e ldr r3, [pc, #56] ; (8000ae0 ) - 8000aa8: 6b1b ldr r3, [r3, #48] ; 0x30 - 8000aaa: f003 0301 and.w r3, r3, #1 - 8000aae: 60fb str r3, [r7, #12] - 8000ab0: 68fb ldr r3, [r7, #12] + 8000cee: 2300 movs r3, #0 + 8000cf0: 60fb str r3, [r7, #12] + 8000cf2: 4b11 ldr r3, [pc, #68] ; (8000d38 ) + 8000cf4: 6b1b ldr r3, [r3, #48] ; 0x30 + 8000cf6: 4a10 ldr r2, [pc, #64] ; (8000d38 ) + 8000cf8: f043 0301 orr.w r3, r3, #1 + 8000cfc: 6313 str r3, [r2, #48] ; 0x30 + 8000cfe: 4b0e ldr r3, [pc, #56] ; (8000d38 ) + 8000d00: 6b1b ldr r3, [r3, #48] ; 0x30 + 8000d02: f003 0301 and.w r3, r3, #1 + 8000d06: 60fb str r3, [r7, #12] + 8000d08: 68fb ldr r3, [r7, #12] /**USART2 GPIO Configuration PA2 ------> USART2_TX PA3 ------> USART2_RX */ GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin; - 8000ab2: 230c movs r3, #12 - 8000ab4: 617b str r3, [r7, #20] + 8000d0a: 230c movs r3, #12 + 8000d0c: 617b str r3, [r7, #20] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - 8000ab6: 2302 movs r3, #2 - 8000ab8: 61bb str r3, [r7, #24] + 8000d0e: 2302 movs r3, #2 + 8000d10: 61bb str r3, [r7, #24] GPIO_InitStruct.Pull = GPIO_NOPULL; - 8000aba: 2300 movs r3, #0 - 8000abc: 61fb str r3, [r7, #28] + 8000d12: 2300 movs r3, #0 + 8000d14: 61fb str r3, [r7, #28] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - 8000abe: 2303 movs r3, #3 - 8000ac0: 623b str r3, [r7, #32] + 8000d16: 2303 movs r3, #3 + 8000d18: 623b str r3, [r7, #32] GPIO_InitStruct.Alternate = GPIO_AF7_USART2; - 8000ac2: 2307 movs r3, #7 - 8000ac4: 627b str r3, [r7, #36] ; 0x24 + 8000d1a: 2307 movs r3, #7 + 8000d1c: 627b str r3, [r7, #36] ; 0x24 HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - 8000ac6: f107 0314 add.w r3, r7, #20 - 8000aca: 4619 mov r1, r3 - 8000acc: 4805 ldr r0, [pc, #20] ; (8000ae4 ) - 8000ace: f000 f9fd bl 8000ecc + 8000d1e: f107 0314 add.w r3, r7, #20 + 8000d22: 4619 mov r1, r3 + 8000d24: 4805 ldr r0, [pc, #20] ; (8000d3c ) + 8000d26: f000 fe73 bl 8001a10 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } - 8000ad2: bf00 nop - 8000ad4: 3728 adds r7, #40 ; 0x28 - 8000ad6: 46bd mov sp, r7 - 8000ad8: bd80 pop {r7, pc} - 8000ada: bf00 nop - 8000adc: 40004400 .word 0x40004400 - 8000ae0: 40023800 .word 0x40023800 - 8000ae4: 40020000 .word 0x40020000 + 8000d2a: bf00 nop + 8000d2c: 3728 adds r7, #40 ; 0x28 + 8000d2e: 46bd mov sp, r7 + 8000d30: bd80 pop {r7, pc} + 8000d32: bf00 nop + 8000d34: 40004400 .word 0x40004400 + 8000d38: 40023800 .word 0x40023800 + 8000d3c: 40020000 .word 0x40020000 -08000ae8 : +08000d40 : * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). * @param TickPriority: Tick interrupt priority. * @retval HAL status */ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { - 8000ae8: b580 push {r7, lr} - 8000aea: b08c sub sp, #48 ; 0x30 - 8000aec: af00 add r7, sp, #0 - 8000aee: 6078 str r0, [r7, #4] + 8000d40: b580 push {r7, lr} + 8000d42: b08c sub sp, #48 ; 0x30 + 8000d44: af00 add r7, sp, #0 + 8000d46: 6078 str r0, [r7, #4] RCC_ClkInitTypeDef clkconfig; uint32_t uwTimclock = 0U; - 8000af0: 2300 movs r3, #0 - 8000af2: 62bb str r3, [r7, #40] ; 0x28 + 8000d48: 2300 movs r3, #0 + 8000d4a: 62bb str r3, [r7, #40] ; 0x28 uint32_t uwPrescalerValue = 0U; - 8000af4: 2300 movs r3, #0 - 8000af6: 627b str r3, [r7, #36] ; 0x24 + 8000d4c: 2300 movs r3, #0 + 8000d4e: 627b str r3, [r7, #36] ; 0x24 uint32_t pFLatency; HAL_StatusTypeDef status; /* Enable TIM1 clock */ __HAL_RCC_TIM1_CLK_ENABLE(); - 8000af8: 2300 movs r3, #0 - 8000afa: 60bb str r3, [r7, #8] - 8000afc: 4b2e ldr r3, [pc, #184] ; (8000bb8 ) - 8000afe: 6c5b ldr r3, [r3, #68] ; 0x44 - 8000b00: 4a2d ldr r2, [pc, #180] ; (8000bb8 ) - 8000b02: f043 0301 orr.w r3, r3, #1 - 8000b06: 6453 str r3, [r2, #68] ; 0x44 - 8000b08: 4b2b ldr r3, [pc, #172] ; (8000bb8 ) - 8000b0a: 6c5b ldr r3, [r3, #68] ; 0x44 - 8000b0c: f003 0301 and.w r3, r3, #1 - 8000b10: 60bb str r3, [r7, #8] - 8000b12: 68bb ldr r3, [r7, #8] + 8000d50: 2300 movs r3, #0 + 8000d52: 60bb str r3, [r7, #8] + 8000d54: 4b2e ldr r3, [pc, #184] ; (8000e10 ) + 8000d56: 6c5b ldr r3, [r3, #68] ; 0x44 + 8000d58: 4a2d ldr r2, [pc, #180] ; (8000e10 ) + 8000d5a: f043 0301 orr.w r3, r3, #1 + 8000d5e: 6453 str r3, [r2, #68] ; 0x44 + 8000d60: 4b2b ldr r3, [pc, #172] ; (8000e10 ) + 8000d62: 6c5b ldr r3, [r3, #68] ; 0x44 + 8000d64: f003 0301 and.w r3, r3, #1 + 8000d68: 60bb str r3, [r7, #8] + 8000d6a: 68bb ldr r3, [r7, #8] /* Get clock configuration */ HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); - 8000b14: f107 020c add.w r2, r7, #12 - 8000b18: f107 0310 add.w r3, r7, #16 - 8000b1c: 4611 mov r1, r2 - 8000b1e: 4618 mov r0, r3 - 8000b20: f001 f822 bl 8001b68 + 8000d6c: f107 020c add.w r2, r7, #12 + 8000d70: f107 0310 add.w r3, r7, #16 + 8000d74: 4611 mov r1, r2 + 8000d76: 4618 mov r0, r3 + 8000d78: f001 fc98 bl 80026ac /* Compute TIM1 clock */ uwTimclock = HAL_RCC_GetPCLK2Freq(); - 8000b24: f001 f80c bl 8001b40 - 8000b28: 62b8 str r0, [r7, #40] ; 0x28 + 8000d7c: f001 fc82 bl 8002684 + 8000d80: 62b8 str r0, [r7, #40] ; 0x28 /* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */ uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); - 8000b2a: 6abb ldr r3, [r7, #40] ; 0x28 - 8000b2c: 4a23 ldr r2, [pc, #140] ; (8000bbc ) - 8000b2e: fba2 2303 umull r2, r3, r2, r3 - 8000b32: 0c9b lsrs r3, r3, #18 - 8000b34: 3b01 subs r3, #1 - 8000b36: 627b str r3, [r7, #36] ; 0x24 + 8000d82: 6abb ldr r3, [r7, #40] ; 0x28 + 8000d84: 4a23 ldr r2, [pc, #140] ; (8000e14 ) + 8000d86: fba2 2303 umull r2, r3, r2, r3 + 8000d8a: 0c9b lsrs r3, r3, #18 + 8000d8c: 3b01 subs r3, #1 + 8000d8e: 627b str r3, [r7, #36] ; 0x24 /* Initialize TIM1 */ htim1.Instance = TIM1; - 8000b38: 4b21 ldr r3, [pc, #132] ; (8000bc0 ) - 8000b3a: 4a22 ldr r2, [pc, #136] ; (8000bc4 ) - 8000b3c: 601a str r2, [r3, #0] + 8000d90: 4b21 ldr r3, [pc, #132] ; (8000e18 ) + 8000d92: 4a22 ldr r2, [pc, #136] ; (8000e1c ) + 8000d94: 601a str r2, [r3, #0] + Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base. + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. + ClockDivision = 0 + Counter direction = Up */ htim1.Init.Period = (1000000U / 1000U) - 1U; - 8000b3e: 4b20 ldr r3, [pc, #128] ; (8000bc0 ) - 8000b40: f240 32e7 movw r2, #999 ; 0x3e7 - 8000b44: 60da str r2, [r3, #12] + 8000d96: 4b20 ldr r3, [pc, #128] ; (8000e18 ) + 8000d98: f240 32e7 movw r2, #999 ; 0x3e7 + 8000d9c: 60da str r2, [r3, #12] htim1.Init.Prescaler = uwPrescalerValue; - 8000b46: 4a1e ldr r2, [pc, #120] ; (8000bc0 ) - 8000b48: 6a7b ldr r3, [r7, #36] ; 0x24 - 8000b4a: 6053 str r3, [r2, #4] + 8000d9e: 4a1e ldr r2, [pc, #120] ; (8000e18 ) + 8000da0: 6a7b ldr r3, [r7, #36] ; 0x24 + 8000da2: 6053 str r3, [r2, #4] htim1.Init.ClockDivision = 0; - 8000b4c: 4b1c ldr r3, [pc, #112] ; (8000bc0 ) - 8000b4e: 2200 movs r2, #0 - 8000b50: 611a str r2, [r3, #16] + 8000da4: 4b1c ldr r3, [pc, #112] ; (8000e18 ) + 8000da6: 2200 movs r2, #0 + 8000da8: 611a str r2, [r3, #16] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; - 8000b52: 4b1b ldr r3, [pc, #108] ; (8000bc0 ) - 8000b54: 2200 movs r2, #0 - 8000b56: 609a str r2, [r3, #8] + 8000daa: 4b1b ldr r3, [pc, #108] ; (8000e18 ) + 8000dac: 2200 movs r2, #0 + 8000dae: 609a str r2, [r3, #8] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; - 8000b58: 4b19 ldr r3, [pc, #100] ; (8000bc0 ) - 8000b5a: 2200 movs r2, #0 - 8000b5c: 619a str r2, [r3, #24] + 8000db0: 4b19 ldr r3, [pc, #100] ; (8000e18 ) + 8000db2: 2200 movs r2, #0 + 8000db4: 619a str r2, [r3, #24] status = HAL_TIM_Base_Init(&htim1); - 8000b5e: 4818 ldr r0, [pc, #96] ; (8000bc0 ) - 8000b60: f001 f834 bl 8001bcc - 8000b64: 4603 mov r3, r0 - 8000b66: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8000db6: 4818 ldr r0, [pc, #96] ; (8000e18 ) + 8000db8: f001 fcaa bl 8002710 + 8000dbc: 4603 mov r3, r0 + 8000dbe: f887 302f strb.w r3, [r7, #47] ; 0x2f if (status == HAL_OK) - 8000b6a: f897 302f ldrb.w r3, [r7, #47] ; 0x2f - 8000b6e: 2b00 cmp r3, #0 - 8000b70: d11b bne.n 8000baa + 8000dc2: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8000dc6: 2b00 cmp r3, #0 + 8000dc8: d11b bne.n 8000e02 { /* Start the TIM time Base generation in interrupt mode */ status = HAL_TIM_Base_Start_IT(&htim1); - 8000b72: 4813 ldr r0, [pc, #76] ; (8000bc0 ) - 8000b74: f001 f884 bl 8001c80 - 8000b78: 4603 mov r3, r0 - 8000b7a: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8000dca: 4813 ldr r0, [pc, #76] ; (8000e18 ) + 8000dcc: f001 fcfa bl 80027c4 + 8000dd0: 4603 mov r3, r0 + 8000dd2: f887 302f strb.w r3, [r7, #47] ; 0x2f if (status == HAL_OK) - 8000b7e: f897 302f ldrb.w r3, [r7, #47] ; 0x2f - 8000b82: 2b00 cmp r3, #0 - 8000b84: d111 bne.n 8000baa + 8000dd6: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8000dda: 2b00 cmp r3, #0 + 8000ddc: d111 bne.n 8000e02 { /* Enable the TIM1 global Interrupt */ HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn); - 8000b86: 2019 movs r0, #25 - 8000b88: f000 f992 bl 8000eb0 + 8000dde: 2019 movs r0, #25 + 8000de0: f000 fe08 bl 80019f4 /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - 8000b8c: 687b ldr r3, [r7, #4] - 8000b8e: 2b0f cmp r3, #15 - 8000b90: d808 bhi.n 8000ba4 + 8000de4: 687b ldr r3, [r7, #4] + 8000de6: 2b0f cmp r3, #15 + 8000de8: d808 bhi.n 8000dfc { /* Configure the TIM IRQ priority */ HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, TickPriority, 0U); - 8000b92: 2200 movs r2, #0 - 8000b94: 6879 ldr r1, [r7, #4] - 8000b96: 2019 movs r0, #25 - 8000b98: f000 f96e bl 8000e78 + 8000dea: 2200 movs r2, #0 + 8000dec: 6879 ldr r1, [r7, #4] + 8000dee: 2019 movs r0, #25 + 8000df0: f000 fde4 bl 80019bc uwTickPrio = TickPriority; - 8000b9c: 4a0a ldr r2, [pc, #40] ; (8000bc8 ) - 8000b9e: 687b ldr r3, [r7, #4] - 8000ba0: 6013 str r3, [r2, #0] - 8000ba2: e002 b.n 8000baa + 8000df4: 4a0a ldr r2, [pc, #40] ; (8000e20 ) + 8000df6: 687b ldr r3, [r7, #4] + 8000df8: 6013 str r3, [r2, #0] + 8000dfa: e002 b.n 8000e02 } else { status = HAL_ERROR; - 8000ba4: 2301 movs r3, #1 - 8000ba6: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8000dfc: 2301 movs r3, #1 + 8000dfe: f887 302f strb.w r3, [r7, #47] ; 0x2f } } } /* Return function status */ return status; - 8000baa: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8000e02: f897 302f ldrb.w r3, [r7, #47] ; 0x2f } - 8000bae: 4618 mov r0, r3 - 8000bb0: 3730 adds r7, #48 ; 0x30 - 8000bb2: 46bd mov sp, r7 - 8000bb4: bd80 pop {r7, pc} - 8000bb6: bf00 nop - 8000bb8: 40023800 .word 0x40023800 - 8000bbc: 431bde83 .word 0x431bde83 - 8000bc0: 200000e0 .word 0x200000e0 - 8000bc4: 40010000 .word 0x40010000 - 8000bc8: 20000004 .word 0x20000004 + 8000e06: 4618 mov r0, r3 + 8000e08: 3730 adds r7, #48 ; 0x30 + 8000e0a: 46bd mov sp, r7 + 8000e0c: bd80 pop {r7, pc} + 8000e0e: bf00 nop + 8000e10: 40023800 .word 0x40023800 + 8000e14: 431bde83 .word 0x431bde83 + 8000e18: 20000130 .word 0x20000130 + 8000e1c: 40010000 .word 0x40010000 + 8000e20: 20000004 .word 0x20000004 -08000bcc : +08000e24 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { - 8000bcc: b480 push {r7} - 8000bce: af00 add r7, sp, #0 + 8000e24: b480 push {r7} + 8000e26: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) - 8000bd0: e7fe b.n 8000bd0 + 8000e28: e7fe b.n 8000e28 -08000bd2 : +08000e2a : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { - 8000bd2: b480 push {r7} - 8000bd4: af00 add r7, sp, #0 + 8000e2a: b480 push {r7} + 8000e2c: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) - 8000bd6: e7fe b.n 8000bd6 + 8000e2e: e7fe b.n 8000e2e -08000bd8 : +08000e30 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { - 8000bd8: b480 push {r7} - 8000bda: af00 add r7, sp, #0 + 8000e30: b480 push {r7} + 8000e32: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) - 8000bdc: e7fe b.n 8000bdc + 8000e34: e7fe b.n 8000e34 -08000bde : +08000e36 : /** * @brief This function handles Pre-fetch fault, memory access fault. */ void BusFault_Handler(void) { - 8000bde: b480 push {r7} - 8000be0: af00 add r7, sp, #0 + 8000e36: b480 push {r7} + 8000e38: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) - 8000be2: e7fe b.n 8000be2 + 8000e3a: e7fe b.n 8000e3a -08000be4 : +08000e3c : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { - 8000be4: b480 push {r7} - 8000be6: af00 add r7, sp, #0 + 8000e3c: b480 push {r7} + 8000e3e: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) - 8000be8: e7fe b.n 8000be8 + 8000e40: e7fe b.n 8000e40 -08000bea : +08000e42 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { - 8000bea: b480 push {r7} - 8000bec: af00 add r7, sp, #0 + 8000e42: b480 push {r7} + 8000e44: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } - 8000bee: bf00 nop - 8000bf0: 46bd mov sp, r7 - 8000bf2: f85d 7b04 ldr.w r7, [sp], #4 - 8000bf6: 4770 bx lr + 8000e46: bf00 nop + 8000e48: 46bd mov sp, r7 + 8000e4a: f85d 7b04 ldr.w r7, [sp], #4 + 8000e4e: 4770 bx lr -08000bf8 : +08000e50 : + +/** + * @brief This function handles ADC1 global interrupt. + */ +void ADC_IRQHandler(void) +{ + 8000e50: b580 push {r7, lr} + 8000e52: af00 add r7, sp, #0 + /* USER CODE BEGIN ADC_IRQn 0 */ + + /* USER CODE END ADC_IRQn 0 */ + HAL_ADC_IRQHandler(&hadc1); + 8000e54: 4802 ldr r0, [pc, #8] ; (8000e60 ) + 8000e56: f000 f98f bl 8001178 + /* USER CODE BEGIN ADC_IRQn 1 */ + + /* USER CODE END ADC_IRQn 1 */ +} + 8000e5a: bf00 nop + 8000e5c: bd80 pop {r7, pc} + 8000e5e: bf00 nop + 8000e60: 2000007c .word 0x2000007c + +08000e64 : /** * @brief This function handles TIM1 update interrupt and TIM10 global interrupt. */ void TIM1_UP_TIM10_IRQHandler(void) { - 8000bf8: b580 push {r7, lr} - 8000bfa: af00 add r7, sp, #0 + 8000e64: b580 push {r7, lr} + 8000e66: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */ /* USER CODE END TIM1_UP_TIM10_IRQn 0 */ HAL_TIM_IRQHandler(&htim1); - 8000bfc: 4802 ldr r0, [pc, #8] ; (8000c08 ) - 8000bfe: f001 f8a1 bl 8001d44 + 8000e68: 4802 ldr r0, [pc, #8] ; (8000e74 ) + 8000e6a: f001 fd0d bl 8002888 /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */ /* USER CODE END TIM1_UP_TIM10_IRQn 1 */ } - 8000c02: bf00 nop - 8000c04: bd80 pop {r7, pc} - 8000c06: bf00 nop - 8000c08: 200000e0 .word 0x200000e0 + 8000e6e: bf00 nop + 8000e70: bd80 pop {r7, pc} + 8000e72: bf00 nop + 8000e74: 20000130 .word 0x20000130 -08000c0c : +08000e78 : * configuration. * @param None * @retval None */ void SystemInit(void) { - 8000c0c: b480 push {r7} - 8000c0e: af00 add r7, sp, #0 + 8000e78: b480 push {r7} + 8000e7a: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - 8000c10: 4b06 ldr r3, [pc, #24] ; (8000c2c ) - 8000c12: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 - 8000c16: 4a05 ldr r2, [pc, #20] ; (8000c2c ) - 8000c18: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 - 8000c1c: f8c2 3088 str.w r3, [r2, #136] ; 0x88 + 8000e7c: 4b06 ldr r3, [pc, #24] ; (8000e98 ) + 8000e7e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8000e82: 4a05 ldr r2, [pc, #20] ; (8000e98 ) + 8000e84: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 8000e88: f8c2 3088 str.w r3, [r2, #136] ; 0x88 /* Configure the Vector Table location -------------------------------------*/ #if defined(USER_VECT_TAB_ADDRESS) SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ } - 8000c20: bf00 nop - 8000c22: 46bd mov sp, r7 - 8000c24: f85d 7b04 ldr.w r7, [sp], #4 - 8000c28: 4770 bx lr - 8000c2a: bf00 nop - 8000c2c: e000ed00 .word 0xe000ed00 + 8000e8c: bf00 nop + 8000e8e: 46bd mov sp, r7 + 8000e90: f85d 7b04 ldr.w r7, [sp], #4 + 8000e94: 4770 bx lr + 8000e96: bf00 nop + 8000e98: e000ed00 .word 0xe000ed00 -08000c30 : +08000e9c : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* set stack pointer */ - 8000c30: f8df d034 ldr.w sp, [pc, #52] ; 8000c68 + 8000e9c: f8df d034 ldr.w sp, [pc, #52] ; 8000ed4 /* Copy the data segment initializers from flash to SRAM */ ldr r0, =_sdata - 8000c34: 480d ldr r0, [pc, #52] ; (8000c6c ) + 8000ea0: 480d ldr r0, [pc, #52] ; (8000ed8 ) ldr r1, =_edata - 8000c36: 490e ldr r1, [pc, #56] ; (8000c70 ) + 8000ea2: 490e ldr r1, [pc, #56] ; (8000edc ) ldr r2, =_sidata - 8000c38: 4a0e ldr r2, [pc, #56] ; (8000c74 ) + 8000ea4: 4a0e ldr r2, [pc, #56] ; (8000ee0 ) movs r3, #0 - 8000c3a: 2300 movs r3, #0 + 8000ea6: 2300 movs r3, #0 b LoopCopyDataInit - 8000c3c: e002 b.n 8000c44 + 8000ea8: e002 b.n 8000eb0 -08000c3e : +08000eaa : CopyDataInit: ldr r4, [r2, r3] - 8000c3e: 58d4 ldr r4, [r2, r3] + 8000eaa: 58d4 ldr r4, [r2, r3] str r4, [r0, r3] - 8000c40: 50c4 str r4, [r0, r3] + 8000eac: 50c4 str r4, [r0, r3] adds r3, r3, #4 - 8000c42: 3304 adds r3, #4 + 8000eae: 3304 adds r3, #4 -08000c44 : +08000eb0 : LoopCopyDataInit: adds r4, r0, r3 - 8000c44: 18c4 adds r4, r0, r3 + 8000eb0: 18c4 adds r4, r0, r3 cmp r4, r1 - 8000c46: 428c cmp r4, r1 + 8000eb2: 428c cmp r4, r1 bcc CopyDataInit - 8000c48: d3f9 bcc.n 8000c3e + 8000eb4: d3f9 bcc.n 8000eaa /* Zero fill the bss segment. */ ldr r2, =_sbss - 8000c4a: 4a0b ldr r2, [pc, #44] ; (8000c78 ) + 8000eb6: 4a0b ldr r2, [pc, #44] ; (8000ee4 ) ldr r4, =_ebss - 8000c4c: 4c0b ldr r4, [pc, #44] ; (8000c7c ) + 8000eb8: 4c0b ldr r4, [pc, #44] ; (8000ee8 ) movs r3, #0 - 8000c4e: 2300 movs r3, #0 + 8000eba: 2300 movs r3, #0 b LoopFillZerobss - 8000c50: e001 b.n 8000c56 + 8000ebc: e001 b.n 8000ec2 -08000c52 : +08000ebe : FillZerobss: str r3, [r2] - 8000c52: 6013 str r3, [r2, #0] + 8000ebe: 6013 str r3, [r2, #0] adds r2, r2, #4 - 8000c54: 3204 adds r2, #4 + 8000ec0: 3204 adds r2, #4 -08000c56 : +08000ec2 : LoopFillZerobss: cmp r2, r4 - 8000c56: 42a2 cmp r2, r4 + 8000ec2: 42a2 cmp r2, r4 bcc FillZerobss - 8000c58: d3fb bcc.n 8000c52 + 8000ec4: d3fb bcc.n 8000ebe /* Call the clock system initialization function.*/ bl SystemInit - 8000c5a: f7ff ffd7 bl 8000c0c + 8000ec6: f7ff ffd7 bl 8000e78 /* Call static constructors */ bl __libc_init_array - 8000c5e: f004 fc9b bl 8005598 <__libc_init_array> + 8000eca: f005 f925 bl 8006118 <__libc_init_array> /* Call the application's entry point.*/ bl main - 8000c62: f7ff fc3b bl 80004dc
+ 8000ece: f7ff fb25 bl 800051c
bx lr - 8000c66: 4770 bx lr + 8000ed2: 4770 bx lr ldr sp, =_estack /* set stack pointer */ - 8000c68: 20020000 .word 0x20020000 + 8000ed4: 20020000 .word 0x20020000 ldr r0, =_sdata - 8000c6c: 20000000 .word 0x20000000 + 8000ed8: 20000000 .word 0x20000000 ldr r1, =_edata - 8000c70: 20000060 .word 0x20000060 + 8000edc: 20000060 .word 0x20000060 ldr r2, =_sidata - 8000c74: 08005768 .word 0x08005768 + 8000ee0: 0800634c .word 0x0800634c ldr r2, =_sbss - 8000c78: 20000060 .word 0x20000060 + 8000ee4: 20000060 .word 0x20000060 ldr r4, =_ebss - 8000c7c: 20004c54 .word 0x20004c54 + 8000ee8: 20004ca4 .word 0x20004ca4 -08000c80 : +08000eec : * @retval None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop - 8000c80: e7fe b.n 8000c80 + 8000eec: e7fe b.n 8000eec ... -08000c84 : +08000ef0 : * need to ensure that the SysTick time base is always set to 1 millisecond * to have correct HAL operation. * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { - 8000c84: b580 push {r7, lr} - 8000c86: af00 add r7, sp, #0 + 8000ef0: b580 push {r7, lr} + 8000ef2: af00 add r7, sp, #0 /* Configure Flash prefetch, Instruction cache, Data cache */ #if (INSTRUCTION_CACHE_ENABLE != 0U) __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); - 8000c88: 4b0e ldr r3, [pc, #56] ; (8000cc4 ) - 8000c8a: 681b ldr r3, [r3, #0] - 8000c8c: 4a0d ldr r2, [pc, #52] ; (8000cc4 ) - 8000c8e: f443 7300 orr.w r3, r3, #512 ; 0x200 - 8000c92: 6013 str r3, [r2, #0] + 8000ef4: 4b0e ldr r3, [pc, #56] ; (8000f30 ) + 8000ef6: 681b ldr r3, [r3, #0] + 8000ef8: 4a0d ldr r2, [pc, #52] ; (8000f30 ) + 8000efa: f443 7300 orr.w r3, r3, #512 ; 0x200 + 8000efe: 6013 str r3, [r2, #0] #endif /* INSTRUCTION_CACHE_ENABLE */ #if (DATA_CACHE_ENABLE != 0U) __HAL_FLASH_DATA_CACHE_ENABLE(); - 8000c94: 4b0b ldr r3, [pc, #44] ; (8000cc4 ) - 8000c96: 681b ldr r3, [r3, #0] - 8000c98: 4a0a ldr r2, [pc, #40] ; (8000cc4 ) - 8000c9a: f443 6380 orr.w r3, r3, #1024 ; 0x400 - 8000c9e: 6013 str r3, [r2, #0] + 8000f00: 4b0b ldr r3, [pc, #44] ; (8000f30 ) + 8000f02: 681b ldr r3, [r3, #0] + 8000f04: 4a0a ldr r2, [pc, #40] ; (8000f30 ) + 8000f06: f443 6380 orr.w r3, r3, #1024 ; 0x400 + 8000f0a: 6013 str r3, [r2, #0] #endif /* DATA_CACHE_ENABLE */ #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); - 8000ca0: 4b08 ldr r3, [pc, #32] ; (8000cc4 ) - 8000ca2: 681b ldr r3, [r3, #0] - 8000ca4: 4a07 ldr r2, [pc, #28] ; (8000cc4 ) - 8000ca6: f443 7380 orr.w r3, r3, #256 ; 0x100 - 8000caa: 6013 str r3, [r2, #0] + 8000f0c: 4b08 ldr r3, [pc, #32] ; (8000f30 ) + 8000f0e: 681b ldr r3, [r3, #0] + 8000f10: 4a07 ldr r2, [pc, #28] ; (8000f30 ) + 8000f12: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8000f16: 6013 str r3, [r2, #0] #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - 8000cac: 2003 movs r0, #3 - 8000cae: f000 f8d8 bl 8000e62 + 8000f18: 2003 movs r0, #3 + 8000f1a: f000 fd44 bl 80019a6 /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ HAL_InitTick(TICK_INT_PRIORITY); - 8000cb2: 200f movs r0, #15 - 8000cb4: f7ff ff18 bl 8000ae8 + 8000f1e: 200f movs r0, #15 + 8000f20: f7ff ff0e bl 8000d40 /* Init the low level hardware */ HAL_MspInit(); - 8000cb8: f7ff fea2 bl 8000a00 + 8000f24: f7ff fe4c bl 8000bc0 /* Return function status */ return HAL_OK; - 8000cbc: 2300 movs r3, #0 + 8000f28: 2300 movs r3, #0 } - 8000cbe: 4618 mov r0, r3 - 8000cc0: bd80 pop {r7, pc} - 8000cc2: bf00 nop - 8000cc4: 40023c00 .word 0x40023c00 + 8000f2a: 4618 mov r0, r3 + 8000f2c: bd80 pop {r7, pc} + 8000f2e: bf00 nop + 8000f30: 40023c00 .word 0x40023c00 -08000cc8 : +08000f34 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { - 8000cc8: b480 push {r7} - 8000cca: af00 add r7, sp, #0 + 8000f34: b480 push {r7} + 8000f36: af00 add r7, sp, #0 uwTick += uwTickFreq; - 8000ccc: 4b06 ldr r3, [pc, #24] ; (8000ce8 ) - 8000cce: 781b ldrb r3, [r3, #0] - 8000cd0: 461a mov r2, r3 - 8000cd2: 4b06 ldr r3, [pc, #24] ; (8000cec ) - 8000cd4: 681b ldr r3, [r3, #0] - 8000cd6: 4413 add r3, r2 - 8000cd8: 4a04 ldr r2, [pc, #16] ; (8000cec ) - 8000cda: 6013 str r3, [r2, #0] + 8000f38: 4b06 ldr r3, [pc, #24] ; (8000f54 ) + 8000f3a: 781b ldrb r3, [r3, #0] + 8000f3c: 461a mov r2, r3 + 8000f3e: 4b06 ldr r3, [pc, #24] ; (8000f58 ) + 8000f40: 681b ldr r3, [r3, #0] + 8000f42: 4413 add r3, r2 + 8000f44: 4a04 ldr r2, [pc, #16] ; (8000f58 ) + 8000f46: 6013 str r3, [r2, #0] } - 8000cdc: bf00 nop - 8000cde: 46bd mov sp, r7 - 8000ce0: f85d 7b04 ldr.w r7, [sp], #4 - 8000ce4: 4770 bx lr - 8000ce6: bf00 nop - 8000ce8: 20000008 .word 0x20000008 - 8000cec: 20000128 .word 0x20000128 + 8000f48: bf00 nop + 8000f4a: 46bd mov sp, r7 + 8000f4c: f85d 7b04 ldr.w r7, [sp], #4 + 8000f50: 4770 bx lr + 8000f52: bf00 nop + 8000f54: 20000008 .word 0x20000008 + 8000f58: 20000178 .word 0x20000178 -08000cf0 : +08000f5c : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { - 8000cf0: b480 push {r7} - 8000cf2: af00 add r7, sp, #0 + 8000f5c: b480 push {r7} + 8000f5e: af00 add r7, sp, #0 return uwTick; - 8000cf4: 4b03 ldr r3, [pc, #12] ; (8000d04 ) - 8000cf6: 681b ldr r3, [r3, #0] + 8000f60: 4b03 ldr r3, [pc, #12] ; (8000f70 ) + 8000f62: 681b ldr r3, [r3, #0] } - 8000cf8: 4618 mov r0, r3 - 8000cfa: 46bd mov sp, r7 - 8000cfc: f85d 7b04 ldr.w r7, [sp], #4 - 8000d00: 4770 bx lr - 8000d02: bf00 nop - 8000d04: 20000128 .word 0x20000128 + 8000f64: 4618 mov r0, r3 + 8000f66: 46bd mov sp, r7 + 8000f68: f85d 7b04 ldr.w r7, [sp], #4 + 8000f6c: 4770 bx lr + 8000f6e: bf00 nop + 8000f70: 20000178 .word 0x20000178 -08000d08 <__NVIC_SetPriorityGrouping>: +08000f74 : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + 8000f74: b580 push {r7, lr} + 8000f76: b084 sub sp, #16 + 8000f78: af00 add r7, sp, #0 + 8000f7a: 6078 str r0, [r7, #4] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 8000f7c: 2300 movs r3, #0 + 8000f7e: 73fb strb r3, [r7, #15] + + /* Check ADC handle */ + if(hadc == NULL) + 8000f80: 687b ldr r3, [r7, #4] + 8000f82: 2b00 cmp r3, #0 + 8000f84: d101 bne.n 8000f8a + { + return HAL_ERROR; + 8000f86: 2301 movs r3, #1 + 8000f88: e033 b.n 8000ff2 + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + } + + if(hadc->State == HAL_ADC_STATE_RESET) + 8000f8a: 687b ldr r3, [r7, #4] + 8000f8c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000f8e: 2b00 cmp r3, #0 + 8000f90: d109 bne.n 8000fa6 + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); + 8000f92: 6878 ldr r0, [r7, #4] + 8000f94: f7ff fe40 bl 8000c18 +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + 8000f98: 687b ldr r3, [r7, #4] + 8000f9a: 2200 movs r2, #0 + 8000f9c: 645a str r2, [r3, #68] ; 0x44 + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + 8000f9e: 687b ldr r3, [r7, #4] + 8000fa0: 2200 movs r2, #0 + 8000fa2: f883 203c strb.w r2, [r3, #60] ; 0x3c + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + 8000fa6: 687b ldr r3, [r7, #4] + 8000fa8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000faa: f003 0310 and.w r3, r3, #16 + 8000fae: 2b00 cmp r3, #0 + 8000fb0: d118 bne.n 8000fe4 + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 8000fb2: 687b ldr r3, [r7, #4] + 8000fb4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000fb6: f423 5388 bic.w r3, r3, #4352 ; 0x1100 + 8000fba: f023 0302 bic.w r3, r3, #2 + 8000fbe: f043 0202 orr.w r2, r3, #2 + 8000fc2: 687b ldr r3, [r7, #4] + 8000fc4: 641a str r2, [r3, #64] ; 0x40 + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Set ADC parameters */ + ADC_Init(hadc); + 8000fc6: 6878 ldr r0, [r7, #4] + 8000fc8: f000 fb3a bl 8001640 + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + 8000fcc: 687b ldr r3, [r7, #4] + 8000fce: 2200 movs r2, #0 + 8000fd0: 645a str r2, [r3, #68] ; 0x44 + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 8000fd2: 687b ldr r3, [r7, #4] + 8000fd4: 6c1b ldr r3, [r3, #64] ; 0x40 + 8000fd6: f023 0303 bic.w r3, r3, #3 + 8000fda: f043 0201 orr.w r2, r3, #1 + 8000fde: 687b ldr r3, [r7, #4] + 8000fe0: 641a str r2, [r3, #64] ; 0x40 + 8000fe2: e001 b.n 8000fe8 + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + tmp_hal_status = HAL_ERROR; + 8000fe4: 2301 movs r3, #1 + 8000fe6: 73fb strb r3, [r7, #15] + } + + /* Release Lock */ + __HAL_UNLOCK(hadc); + 8000fe8: 687b ldr r3, [r7, #4] + 8000fea: 2200 movs r2, #0 + 8000fec: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Return function status */ + return tmp_hal_status; + 8000ff0: 7bfb ldrb r3, [r7, #15] +} + 8000ff2: 4618 mov r0, r3 + 8000ff4: 3710 adds r7, #16 + 8000ff6: 46bd mov sp, r7 + 8000ff8: bd80 pop {r7, pc} + ... + +08000ffc : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + 8000ffc: b480 push {r7} + 8000ffe: b085 sub sp, #20 + 8001000: af00 add r7, sp, #0 + 8001002: 6078 str r0, [r7, #4] + __IO uint32_t counter = 0U; + 8001004: 2300 movs r3, #0 + 8001006: 60bb str r3, [r7, #8] + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + 8001008: 687b ldr r3, [r7, #4] + 800100a: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 800100e: 2b01 cmp r3, #1 + 8001010: d101 bne.n 8001016 + 8001012: 2302 movs r3, #2 + 8001014: e0a1 b.n 800115a + 8001016: 687b ldr r3, [r7, #4] + 8001018: 2201 movs r2, #1 + 800101a: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + 800101e: 687b ldr r3, [r7, #4] + 8001020: 681b ldr r3, [r3, #0] + 8001022: 689b ldr r3, [r3, #8] + 8001024: f003 0301 and.w r3, r3, #1 + 8001028: 2b01 cmp r3, #1 + 800102a: d018 beq.n 800105e + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + 800102c: 687b ldr r3, [r7, #4] + 800102e: 681b ldr r3, [r3, #0] + 8001030: 689a ldr r2, [r3, #8] + 8001032: 687b ldr r3, [r7, #4] + 8001034: 681b ldr r3, [r3, #0] + 8001036: f042 0201 orr.w r2, r2, #1 + 800103a: 609a str r2, [r3, #8] + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + 800103c: 4b4a ldr r3, [pc, #296] ; (8001168 ) + 800103e: 681b ldr r3, [r3, #0] + 8001040: 4a4a ldr r2, [pc, #296] ; (800116c ) + 8001042: fba2 2303 umull r2, r3, r2, r3 + 8001046: 0c9a lsrs r2, r3, #18 + 8001048: 4613 mov r3, r2 + 800104a: 005b lsls r3, r3, #1 + 800104c: 4413 add r3, r2 + 800104e: 60bb str r3, [r7, #8] + while(counter != 0U) + 8001050: e002 b.n 8001058 + { + counter--; + 8001052: 68bb ldr r3, [r7, #8] + 8001054: 3b01 subs r3, #1 + 8001056: 60bb str r3, [r7, #8] + while(counter != 0U) + 8001058: 68bb ldr r3, [r7, #8] + 800105a: 2b00 cmp r3, #0 + 800105c: d1f9 bne.n 8001052 + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + 800105e: 687b ldr r3, [r7, #4] + 8001060: 681b ldr r3, [r3, #0] + 8001062: 689b ldr r3, [r3, #8] + 8001064: f003 0301 and.w r3, r3, #1 + 8001068: 2b01 cmp r3, #1 + 800106a: d169 bne.n 8001140 + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + 800106c: 687b ldr r3, [r7, #4] + 800106e: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001070: f423 63e0 bic.w r3, r3, #1792 ; 0x700 + 8001074: f023 0301 bic.w r3, r3, #1 + 8001078: f443 7280 orr.w r2, r3, #256 ; 0x100 + 800107c: 687b ldr r3, [r7, #4] + 800107e: 641a str r2, [r3, #64] ; 0x40 + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + 8001080: 687b ldr r3, [r7, #4] + 8001082: 681b ldr r3, [r3, #0] + 8001084: 685b ldr r3, [r3, #4] + 8001086: f403 6380 and.w r3, r3, #1024 ; 0x400 + 800108a: 2b00 cmp r3, #0 + 800108c: d007 beq.n 800109e + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + 800108e: 687b ldr r3, [r7, #4] + 8001090: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001092: f423 5340 bic.w r3, r3, #12288 ; 0x3000 + 8001096: f443 5280 orr.w r2, r3, #4096 ; 0x1000 + 800109a: 687b ldr r3, [r7, #4] + 800109c: 641a str r2, [r3, #64] ; 0x40 + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + 800109e: 687b ldr r3, [r7, #4] + 80010a0: 6c1b ldr r3, [r3, #64] ; 0x40 + 80010a2: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 80010a6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 80010aa: d106 bne.n 80010ba + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + 80010ac: 687b ldr r3, [r7, #4] + 80010ae: 6c5b ldr r3, [r3, #68] ; 0x44 + 80010b0: f023 0206 bic.w r2, r3, #6 + 80010b4: 687b ldr r3, [r7, #4] + 80010b6: 645a str r2, [r3, #68] ; 0x44 + 80010b8: e002 b.n 80010c0 + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + 80010ba: 687b ldr r3, [r7, #4] + 80010bc: 2200 movs r2, #0 + 80010be: 645a str r2, [r3, #68] ; 0x44 + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + 80010c0: 687b ldr r3, [r7, #4] + 80010c2: 2200 movs r2, #0 + 80010c4: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + 80010c8: 4b29 ldr r3, [pc, #164] ; (8001170 ) + 80010ca: 60fb str r3, [r7, #12] + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + 80010cc: 687b ldr r3, [r7, #4] + 80010ce: 681b ldr r3, [r3, #0] + 80010d0: f06f 0222 mvn.w r2, #34 ; 0x22 + 80010d4: 601a str r2, [r3, #0] + + /* Enable end of conversion interrupt for regular group */ + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + 80010d6: 687b ldr r3, [r7, #4] + 80010d8: 681b ldr r3, [r3, #0] + 80010da: 685b ldr r3, [r3, #4] + 80010dc: 687a ldr r2, [r7, #4] + 80010de: 6812 ldr r2, [r2, #0] + 80010e0: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 80010e4: f043 0320 orr.w r3, r3, #32 + 80010e8: 6053 str r3, [r2, #4] + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + 80010ea: 68fb ldr r3, [r7, #12] + 80010ec: 685b ldr r3, [r3, #4] + 80010ee: f003 031f and.w r3, r3, #31 + 80010f2: 2b00 cmp r3, #0 + 80010f4: d10f bne.n 8001116 + if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + { +#endif /* ADC2 || ADC3 */ + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + 80010f6: 687b ldr r3, [r7, #4] + 80010f8: 681b ldr r3, [r3, #0] + 80010fa: 689b ldr r3, [r3, #8] + 80010fc: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 + 8001100: 2b00 cmp r3, #0 + 8001102: d129 bne.n 8001158 + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + 8001104: 687b ldr r3, [r7, #4] + 8001106: 681b ldr r3, [r3, #0] + 8001108: 689a ldr r2, [r3, #8] + 800110a: 687b ldr r3, [r7, #4] + 800110c: 681b ldr r3, [r3, #0] + 800110e: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000 + 8001112: 609a str r2, [r3, #8] + 8001114: e020 b.n 8001158 +#endif /* ADC2 || ADC3 */ + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + 8001116: 687b ldr r3, [r7, #4] + 8001118: 681b ldr r3, [r3, #0] + 800111a: 4a16 ldr r2, [pc, #88] ; (8001174 ) + 800111c: 4293 cmp r3, r2 + 800111e: d11b bne.n 8001158 + 8001120: 687b ldr r3, [r7, #4] + 8001122: 681b ldr r3, [r3, #0] + 8001124: 689b ldr r3, [r3, #8] + 8001126: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 + 800112a: 2b00 cmp r3, #0 + 800112c: d114 bne.n 8001158 + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + 800112e: 687b ldr r3, [r7, #4] + 8001130: 681b ldr r3, [r3, #0] + 8001132: 689a ldr r2, [r3, #8] + 8001134: 687b ldr r3, [r7, #4] + 8001136: 681b ldr r3, [r3, #0] + 8001138: f042 4280 orr.w r2, r2, #1073741824 ; 0x40000000 + 800113c: 609a str r2, [r3, #8] + 800113e: e00b b.n 8001158 + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 8001140: 687b ldr r3, [r7, #4] + 8001142: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001144: f043 0210 orr.w r2, r3, #16 + 8001148: 687b ldr r3, [r7, #4] + 800114a: 641a str r2, [r3, #64] ; 0x40 + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 800114c: 687b ldr r3, [r7, #4] + 800114e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001150: f043 0201 orr.w r2, r3, #1 + 8001154: 687b ldr r3, [r7, #4] + 8001156: 645a str r2, [r3, #68] ; 0x44 + } + + /* Return function status */ + return HAL_OK; + 8001158: 2300 movs r3, #0 +} + 800115a: 4618 mov r0, r3 + 800115c: 3714 adds r7, #20 + 800115e: 46bd mov sp, r7 + 8001160: f85d 7b04 ldr.w r7, [sp], #4 + 8001164: 4770 bx lr + 8001166: bf00 nop + 8001168: 20000000 .word 0x20000000 + 800116c: 431bde83 .word 0x431bde83 + 8001170: 40012300 .word 0x40012300 + 8001174: 40012000 .word 0x40012000 + +08001178 : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + 8001178: b580 push {r7, lr} + 800117a: b086 sub sp, #24 + 800117c: af00 add r7, sp, #0 + 800117e: 6078 str r0, [r7, #4] + uint32_t tmp1 = 0U, tmp2 = 0U; + 8001180: 2300 movs r3, #0 + 8001182: 617b str r3, [r7, #20] + 8001184: 2300 movs r3, #0 + 8001186: 613b str r3, [r7, #16] + + uint32_t tmp_sr = hadc->Instance->SR; + 8001188: 687b ldr r3, [r7, #4] + 800118a: 681b ldr r3, [r3, #0] + 800118c: 681b ldr r3, [r3, #0] + 800118e: 60fb str r3, [r7, #12] + uint32_t tmp_cr1 = hadc->Instance->CR1; + 8001190: 687b ldr r3, [r7, #4] + 8001192: 681b ldr r3, [r3, #0] + 8001194: 685b ldr r3, [r3, #4] + 8001196: 60bb str r3, [r7, #8] + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + + tmp1 = tmp_sr & ADC_FLAG_EOC; + 8001198: 68fb ldr r3, [r7, #12] + 800119a: f003 0302 and.w r3, r3, #2 + 800119e: 617b str r3, [r7, #20] + tmp2 = tmp_cr1 & ADC_IT_EOC; + 80011a0: 68bb ldr r3, [r7, #8] + 80011a2: f003 0320 and.w r3, r3, #32 + 80011a6: 613b str r3, [r7, #16] + /* Check End of conversion flag for regular channels */ + if(tmp1 && tmp2) + 80011a8: 697b ldr r3, [r7, #20] + 80011aa: 2b00 cmp r3, #0 + 80011ac: d049 beq.n 8001242 + 80011ae: 693b ldr r3, [r7, #16] + 80011b0: 2b00 cmp r3, #0 + 80011b2: d046 beq.n 8001242 + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + 80011b4: 687b ldr r3, [r7, #4] + 80011b6: 6c1b ldr r3, [r3, #64] ; 0x40 + 80011b8: f003 0310 and.w r3, r3, #16 + 80011bc: 2b00 cmp r3, #0 + 80011be: d105 bne.n 80011cc + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + 80011c0: 687b ldr r3, [r7, #4] + 80011c2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80011c4: f443 7200 orr.w r2, r3, #512 ; 0x200 + 80011c8: 687b ldr r3, [r7, #4] + 80011ca: 641a str r2, [r3, #64] ; 0x40 + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F4, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 80011cc: 687b ldr r3, [r7, #4] + 80011ce: 681b ldr r3, [r3, #0] + 80011d0: 689b ldr r3, [r3, #8] + 80011d2: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 + 80011d6: 2b00 cmp r3, #0 + 80011d8: d12b bne.n 8001232 + (hadc->Init.ContinuousConvMode == DISABLE) && + 80011da: 687b ldr r3, [r7, #4] + 80011dc: 7e1b ldrb r3, [r3, #24] + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 80011de: 2b00 cmp r3, #0 + 80011e0: d127 bne.n 8001232 + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 80011e2: 687b ldr r3, [r7, #4] + 80011e4: 681b ldr r3, [r3, #0] + 80011e6: 6adb ldr r3, [r3, #44] ; 0x2c + 80011e8: f403 0370 and.w r3, r3, #15728640 ; 0xf00000 + (hadc->Init.ContinuousConvMode == DISABLE) && + 80011ec: 2b00 cmp r3, #0 + 80011ee: d006 beq.n 80011fe + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + 80011f0: 687b ldr r3, [r7, #4] + 80011f2: 681b ldr r3, [r3, #0] + 80011f4: 689b ldr r3, [r3, #8] + 80011f6: f403 6380 and.w r3, r3, #1024 ; 0x400 + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + 80011fa: 2b00 cmp r3, #0 + 80011fc: d119 bne.n 8001232 + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + 80011fe: 687b ldr r3, [r7, #4] + 8001200: 681b ldr r3, [r3, #0] + 8001202: 685a ldr r2, [r3, #4] + 8001204: 687b ldr r3, [r7, #4] + 8001206: 681b ldr r3, [r3, #0] + 8001208: f022 0220 bic.w r2, r2, #32 + 800120c: 605a str r2, [r3, #4] + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + 800120e: 687b ldr r3, [r7, #4] + 8001210: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001212: f423 7280 bic.w r2, r3, #256 ; 0x100 + 8001216: 687b ldr r3, [r7, #4] + 8001218: 641a str r2, [r3, #64] ; 0x40 + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + 800121a: 687b ldr r3, [r7, #4] + 800121c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800121e: f403 5380 and.w r3, r3, #4096 ; 0x1000 + 8001222: 2b00 cmp r3, #0 + 8001224: d105 bne.n 8001232 + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + 8001226: 687b ldr r3, [r7, #4] + 8001228: 6c1b ldr r3, [r3, #64] ; 0x40 + 800122a: f043 0201 orr.w r2, r3, #1 + 800122e: 687b ldr r3, [r7, #4] + 8001230: 641a str r2, [r3, #64] ; 0x40 + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); + 8001232: 6878 ldr r0, [r7, #4] + 8001234: f7ff f952 bl 80004dc +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + 8001238: 687b ldr r3, [r7, #4] + 800123a: 681b ldr r3, [r3, #0] + 800123c: f06f 0212 mvn.w r2, #18 + 8001240: 601a str r2, [r3, #0] + } + + tmp1 = tmp_sr & ADC_FLAG_JEOC; + 8001242: 68fb ldr r3, [r7, #12] + 8001244: f003 0304 and.w r3, r3, #4 + 8001248: 617b str r3, [r7, #20] + tmp2 = tmp_cr1 & ADC_IT_JEOC; + 800124a: 68bb ldr r3, [r7, #8] + 800124c: f003 0380 and.w r3, r3, #128 ; 0x80 + 8001250: 613b str r3, [r7, #16] + /* Check End of conversion flag for injected channels */ + if(tmp1 && tmp2) + 8001252: 697b ldr r3, [r7, #20] + 8001254: 2b00 cmp r3, #0 + 8001256: d057 beq.n 8001308 + 8001258: 693b ldr r3, [r7, #16] + 800125a: 2b00 cmp r3, #0 + 800125c: d054 beq.n 8001308 + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + 800125e: 687b ldr r3, [r7, #4] + 8001260: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001262: f003 0310 and.w r3, r3, #16 + 8001266: 2b00 cmp r3, #0 + 8001268: d105 bne.n 8001276 + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + 800126a: 687b ldr r3, [r7, #4] + 800126c: 6c1b ldr r3, [r3, #64] ; 0x40 + 800126e: f443 5200 orr.w r2, r3, #8192 ; 0x2000 + 8001272: 687b ldr r3, [r7, #4] + 8001274: 641a str r2, [r3, #64] ; 0x40 + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, scan sequence on going or by automatic injected */ + /* conversion from group regular (same conditions as group regular */ + /* interruption disabling above). */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + 8001276: 687b ldr r3, [r7, #4] + 8001278: 681b ldr r3, [r3, #0] + 800127a: 689b ldr r3, [r3, #8] + 800127c: f403 1340 and.w r3, r3, #3145728 ; 0x300000 + 8001280: 2b00 cmp r3, #0 + 8001282: d139 bne.n 80012f8 + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 8001284: 687b ldr r3, [r7, #4] + 8001286: 681b ldr r3, [r3, #0] + 8001288: 6b9b ldr r3, [r3, #56] ; 0x38 + 800128a: f403 1340 and.w r3, r3, #3145728 ; 0x300000 + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + 800128e: 2b00 cmp r3, #0 + 8001290: d006 beq.n 80012a0 + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + 8001292: 687b ldr r3, [r7, #4] + 8001294: 681b ldr r3, [r3, #0] + 8001296: 689b ldr r3, [r3, #8] + 8001298: f403 6380 and.w r3, r3, #1024 ; 0x400 + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + 800129c: 2b00 cmp r3, #0 + 800129e: d12b bne.n 80012f8 + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + 80012a0: 687b ldr r3, [r7, #4] + 80012a2: 681b ldr r3, [r3, #0] + 80012a4: 685b ldr r3, [r3, #4] + 80012a6: f403 6380 and.w r3, r3, #1024 ; 0x400 + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + 80012aa: 2b00 cmp r3, #0 + 80012ac: d124 bne.n 80012f8 + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 80012ae: 687b ldr r3, [r7, #4] + 80012b0: 681b ldr r3, [r3, #0] + 80012b2: 689b ldr r3, [r3, #8] + 80012b4: f003 5340 and.w r3, r3, #805306368 ; 0x30000000 + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + 80012b8: 2b00 cmp r3, #0 + 80012ba: d11d bne.n 80012f8 + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + 80012bc: 687b ldr r3, [r7, #4] + 80012be: 7e1b ldrb r3, [r3, #24] + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + 80012c0: 2b00 cmp r3, #0 + 80012c2: d119 bne.n 80012f8 + { + /* Disable ADC end of single conversion interrupt on group injected */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + 80012c4: 687b ldr r3, [r7, #4] + 80012c6: 681b ldr r3, [r3, #0] + 80012c8: 685a ldr r2, [r3, #4] + 80012ca: 687b ldr r3, [r7, #4] + 80012cc: 681b ldr r3, [r3, #0] + 80012ce: f022 0280 bic.w r2, r2, #128 ; 0x80 + 80012d2: 605a str r2, [r3, #4] + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + 80012d4: 687b ldr r3, [r7, #4] + 80012d6: 6c1b ldr r3, [r3, #64] ; 0x40 + 80012d8: f423 5280 bic.w r2, r3, #4096 ; 0x1000 + 80012dc: 687b ldr r3, [r7, #4] + 80012de: 641a str r2, [r3, #64] ; 0x40 + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + 80012e0: 687b ldr r3, [r7, #4] + 80012e2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80012e4: f403 7380 and.w r3, r3, #256 ; 0x100 + 80012e8: 2b00 cmp r3, #0 + 80012ea: d105 bne.n 80012f8 + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + 80012ec: 687b ldr r3, [r7, #4] + 80012ee: 6c1b ldr r3, [r3, #64] ; 0x40 + 80012f0: f043 0201 orr.w r2, r3, #1 + 80012f4: 687b ldr r3, [r7, #4] + 80012f6: 641a str r2, [r3, #64] ; 0x40 + /* Conversion complete callback */ + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedConvCpltCallback(hadc); +#else + HAL_ADCEx_InjectedConvCpltCallback(hadc); + 80012f8: 6878 ldr r0, [r7, #4] + 80012fa: f000 fa9d bl 8001838 +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); + 80012fe: 687b ldr r3, [r7, #4] + 8001300: 681b ldr r3, [r3, #0] + 8001302: f06f 020c mvn.w r2, #12 + 8001306: 601a str r2, [r3, #0] + } + + tmp1 = tmp_sr & ADC_FLAG_AWD; + 8001308: 68fb ldr r3, [r7, #12] + 800130a: f003 0301 and.w r3, r3, #1 + 800130e: 617b str r3, [r7, #20] + tmp2 = tmp_cr1 & ADC_IT_AWD; + 8001310: 68bb ldr r3, [r7, #8] + 8001312: f003 0340 and.w r3, r3, #64 ; 0x40 + 8001316: 613b str r3, [r7, #16] + /* Check Analog watchdog flag */ + if(tmp1 && tmp2) + 8001318: 697b ldr r3, [r7, #20] + 800131a: 2b00 cmp r3, #0 + 800131c: d017 beq.n 800134e + 800131e: 693b ldr r3, [r7, #16] + 8001320: 2b00 cmp r3, #0 + 8001322: d014 beq.n 800134e + { + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) + 8001324: 687b ldr r3, [r7, #4] + 8001326: 681b ldr r3, [r3, #0] + 8001328: 681b ldr r3, [r3, #0] + 800132a: f003 0301 and.w r3, r3, #1 + 800132e: 2b01 cmp r3, #1 + 8001330: d10d bne.n 800134e + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + 8001332: 687b ldr r3, [r7, #4] + 8001334: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001336: f443 3280 orr.w r2, r3, #65536 ; 0x10000 + 800133a: 687b ldr r3, [r7, #4] + 800133c: 641a str r2, [r3, #64] ; 0x40 + + /* Level out of window callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); + 800133e: 6878 ldr r0, [r7, #4] + 8001340: f000 f837 bl 80013b2 +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear the ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + 8001344: 687b ldr r3, [r7, #4] + 8001346: 681b ldr r3, [r3, #0] + 8001348: f06f 0201 mvn.w r2, #1 + 800134c: 601a str r2, [r3, #0] + } + } + + tmp1 = tmp_sr & ADC_FLAG_OVR; + 800134e: 68fb ldr r3, [r7, #12] + 8001350: f003 0320 and.w r3, r3, #32 + 8001354: 617b str r3, [r7, #20] + tmp2 = tmp_cr1 & ADC_IT_OVR; + 8001356: 68bb ldr r3, [r7, #8] + 8001358: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 800135c: 613b str r3, [r7, #16] + /* Check Overrun flag */ + if(tmp1 && tmp2) + 800135e: 697b ldr r3, [r7, #20] + 8001360: 2b00 cmp r3, #0 + 8001362: d015 beq.n 8001390 + 8001364: 693b ldr r3, [r7, #16] + 8001366: 2b00 cmp r3, #0 + 8001368: d012 beq.n 8001390 + /* Note: On STM32F4, ADC overrun can be set through other parameters */ + /* refer to description of parameter "EOCSelection" for more */ + /* details. */ + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + 800136a: 687b ldr r3, [r7, #4] + 800136c: 6c5b ldr r3, [r3, #68] ; 0x44 + 800136e: f043 0202 orr.w r2, r3, #2 + 8001372: 687b ldr r3, [r7, #4] + 8001374: 645a str r2, [r3, #68] ; 0x44 + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + 8001376: 687b ldr r3, [r7, #4] + 8001378: 681b ldr r3, [r3, #0] + 800137a: f06f 0220 mvn.w r2, #32 + 800137e: 601a str r2, [r3, #0] + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); + 8001380: 6878 ldr r0, [r7, #4] + 8001382: f000 f820 bl 80013c6 +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear the Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + 8001386: 687b ldr r3, [r7, #4] + 8001388: 681b ldr r3, [r3, #0] + 800138a: f06f 0220 mvn.w r2, #32 + 800138e: 601a str r2, [r3, #0] + } +} + 8001390: bf00 nop + 8001392: 3718 adds r7, #24 + 8001394: 46bd mov sp, r7 + 8001396: bd80 pop {r7, pc} + +08001398 : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval Converted value + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + 8001398: b480 push {r7} + 800139a: b083 sub sp, #12 + 800139c: af00 add r7, sp, #0 + 800139e: 6078 str r0, [r7, #4] + /* Return the selected ADC converted value */ + return hadc->Instance->DR; + 80013a0: 687b ldr r3, [r7, #4] + 80013a2: 681b ldr r3, [r3, #0] + 80013a4: 6cdb ldr r3, [r3, #76] ; 0x4c +} + 80013a6: 4618 mov r0, r3 + 80013a8: 370c adds r7, #12 + 80013aa: 46bd mov sp, r7 + 80013ac: f85d 7b04 ldr.w r7, [sp], #4 + 80013b0: 4770 bx lr + +080013b2 : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +{ + 80013b2: b480 push {r7} + 80013b4: b083 sub sp, #12 + 80013b6: af00 add r7, sp, #0 + 80013b8: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file + */ +} + 80013ba: bf00 nop + 80013bc: 370c adds r7, #12 + 80013be: 46bd mov sp, r7 + 80013c0: f85d 7b04 ldr.w r7, [sp], #4 + 80013c4: 4770 bx lr + +080013c6 : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + 80013c6: b480 push {r7} + 80013c8: b083 sub sp, #12 + 80013ca: af00 add r7, sp, #0 + 80013cc: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ErrorCallback could be implemented in the user file + */ +} + 80013ce: bf00 nop + 80013d0: 370c adds r7, #12 + 80013d2: 46bd mov sp, r7 + 80013d4: f85d 7b04 ldr.w r7, [sp], #4 + 80013d8: 4770 bx lr + ... + +080013dc : + * the configuration information for the specified ADC. + * @param sConfig ADC configuration structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + 80013dc: b480 push {r7} + 80013de: b085 sub sp, #20 + 80013e0: af00 add r7, sp, #0 + 80013e2: 6078 str r0, [r7, #4] + 80013e4: 6039 str r1, [r7, #0] + __IO uint32_t counter = 0U; + 80013e6: 2300 movs r3, #0 + 80013e8: 60bb str r3, [r7, #8] + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + + /* Process locked */ + __HAL_LOCK(hadc); + 80013ea: 687b ldr r3, [r7, #4] + 80013ec: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 80013f0: 2b01 cmp r3, #1 + 80013f2: d101 bne.n 80013f8 + 80013f4: 2302 movs r3, #2 + 80013f6: e113 b.n 8001620 + 80013f8: 687b ldr r3, [r7, #4] + 80013fa: 2201 movs r2, #1 + 80013fc: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (sConfig->Channel > ADC_CHANNEL_9) + 8001400: 683b ldr r3, [r7, #0] + 8001402: 681b ldr r3, [r3, #0] + 8001404: 2b09 cmp r3, #9 + 8001406: d925 bls.n 8001454 + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); + 8001408: 687b ldr r3, [r7, #4] + 800140a: 681b ldr r3, [r3, #0] + 800140c: 68d9 ldr r1, [r3, #12] + 800140e: 683b ldr r3, [r7, #0] + 8001410: 681b ldr r3, [r3, #0] + 8001412: b29b uxth r3, r3 + 8001414: 461a mov r2, r3 + 8001416: 4613 mov r3, r2 + 8001418: 005b lsls r3, r3, #1 + 800141a: 4413 add r3, r2 + 800141c: 3b1e subs r3, #30 + 800141e: 2207 movs r2, #7 + 8001420: fa02 f303 lsl.w r3, r2, r3 + 8001424: 43da mvns r2, r3 + 8001426: 687b ldr r3, [r7, #4] + 8001428: 681b ldr r3, [r3, #0] + 800142a: 400a ands r2, r1 + 800142c: 60da str r2, [r3, #12] + + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); + 800142e: 687b ldr r3, [r7, #4] + 8001430: 681b ldr r3, [r3, #0] + 8001432: 68d9 ldr r1, [r3, #12] + 8001434: 683b ldr r3, [r7, #0] + 8001436: 689a ldr r2, [r3, #8] + 8001438: 683b ldr r3, [r7, #0] + 800143a: 681b ldr r3, [r3, #0] + 800143c: b29b uxth r3, r3 + 800143e: 4618 mov r0, r3 + 8001440: 4603 mov r3, r0 + 8001442: 005b lsls r3, r3, #1 + 8001444: 4403 add r3, r0 + 8001446: 3b1e subs r3, #30 + 8001448: 409a lsls r2, r3 + 800144a: 687b ldr r3, [r7, #4] + 800144c: 681b ldr r3, [r3, #0] + 800144e: 430a orrs r2, r1 + 8001450: 60da str r2, [r3, #12] + 8001452: e022 b.n 800149a + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Clear the old sample time */ + hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); + 8001454: 687b ldr r3, [r7, #4] + 8001456: 681b ldr r3, [r3, #0] + 8001458: 6919 ldr r1, [r3, #16] + 800145a: 683b ldr r3, [r7, #0] + 800145c: 681b ldr r3, [r3, #0] + 800145e: b29b uxth r3, r3 + 8001460: 461a mov r2, r3 + 8001462: 4613 mov r3, r2 + 8001464: 005b lsls r3, r3, #1 + 8001466: 4413 add r3, r2 + 8001468: 2207 movs r2, #7 + 800146a: fa02 f303 lsl.w r3, r2, r3 + 800146e: 43da mvns r2, r3 + 8001470: 687b ldr r3, [r7, #4] + 8001472: 681b ldr r3, [r3, #0] + 8001474: 400a ands r2, r1 + 8001476: 611a str r2, [r3, #16] + + /* Set the new sample time */ + hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); + 8001478: 687b ldr r3, [r7, #4] + 800147a: 681b ldr r3, [r3, #0] + 800147c: 6919 ldr r1, [r3, #16] + 800147e: 683b ldr r3, [r7, #0] + 8001480: 689a ldr r2, [r3, #8] + 8001482: 683b ldr r3, [r7, #0] + 8001484: 681b ldr r3, [r3, #0] + 8001486: b29b uxth r3, r3 + 8001488: 4618 mov r0, r3 + 800148a: 4603 mov r3, r0 + 800148c: 005b lsls r3, r3, #1 + 800148e: 4403 add r3, r0 + 8001490: 409a lsls r2, r3 + 8001492: 687b ldr r3, [r7, #4] + 8001494: 681b ldr r3, [r3, #0] + 8001496: 430a orrs r2, r1 + 8001498: 611a str r2, [r3, #16] + } + + /* For Rank 1 to 6 */ + if (sConfig->Rank < 7U) + 800149a: 683b ldr r3, [r7, #0] + 800149c: 685b ldr r3, [r3, #4] + 800149e: 2b06 cmp r3, #6 + 80014a0: d824 bhi.n 80014ec + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); + 80014a2: 687b ldr r3, [r7, #4] + 80014a4: 681b ldr r3, [r3, #0] + 80014a6: 6b59 ldr r1, [r3, #52] ; 0x34 + 80014a8: 683b ldr r3, [r7, #0] + 80014aa: 685a ldr r2, [r3, #4] + 80014ac: 4613 mov r3, r2 + 80014ae: 009b lsls r3, r3, #2 + 80014b0: 4413 add r3, r2 + 80014b2: 3b05 subs r3, #5 + 80014b4: 221f movs r2, #31 + 80014b6: fa02 f303 lsl.w r3, r2, r3 + 80014ba: 43da mvns r2, r3 + 80014bc: 687b ldr r3, [r7, #4] + 80014be: 681b ldr r3, [r3, #0] + 80014c0: 400a ands r2, r1 + 80014c2: 635a str r2, [r3, #52] ; 0x34 + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); + 80014c4: 687b ldr r3, [r7, #4] + 80014c6: 681b ldr r3, [r3, #0] + 80014c8: 6b59 ldr r1, [r3, #52] ; 0x34 + 80014ca: 683b ldr r3, [r7, #0] + 80014cc: 681b ldr r3, [r3, #0] + 80014ce: b29b uxth r3, r3 + 80014d0: 4618 mov r0, r3 + 80014d2: 683b ldr r3, [r7, #0] + 80014d4: 685a ldr r2, [r3, #4] + 80014d6: 4613 mov r3, r2 + 80014d8: 009b lsls r3, r3, #2 + 80014da: 4413 add r3, r2 + 80014dc: 3b05 subs r3, #5 + 80014de: fa00 f203 lsl.w r2, r0, r3 + 80014e2: 687b ldr r3, [r7, #4] + 80014e4: 681b ldr r3, [r3, #0] + 80014e6: 430a orrs r2, r1 + 80014e8: 635a str r2, [r3, #52] ; 0x34 + 80014ea: e04c b.n 8001586 + } + /* For Rank 7 to 12 */ + else if (sConfig->Rank < 13U) + 80014ec: 683b ldr r3, [r7, #0] + 80014ee: 685b ldr r3, [r3, #4] + 80014f0: 2b0c cmp r3, #12 + 80014f2: d824 bhi.n 800153e + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); + 80014f4: 687b ldr r3, [r7, #4] + 80014f6: 681b ldr r3, [r3, #0] + 80014f8: 6b19 ldr r1, [r3, #48] ; 0x30 + 80014fa: 683b ldr r3, [r7, #0] + 80014fc: 685a ldr r2, [r3, #4] + 80014fe: 4613 mov r3, r2 + 8001500: 009b lsls r3, r3, #2 + 8001502: 4413 add r3, r2 + 8001504: 3b23 subs r3, #35 ; 0x23 + 8001506: 221f movs r2, #31 + 8001508: fa02 f303 lsl.w r3, r2, r3 + 800150c: 43da mvns r2, r3 + 800150e: 687b ldr r3, [r7, #4] + 8001510: 681b ldr r3, [r3, #0] + 8001512: 400a ands r2, r1 + 8001514: 631a str r2, [r3, #48] ; 0x30 + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); + 8001516: 687b ldr r3, [r7, #4] + 8001518: 681b ldr r3, [r3, #0] + 800151a: 6b19 ldr r1, [r3, #48] ; 0x30 + 800151c: 683b ldr r3, [r7, #0] + 800151e: 681b ldr r3, [r3, #0] + 8001520: b29b uxth r3, r3 + 8001522: 4618 mov r0, r3 + 8001524: 683b ldr r3, [r7, #0] + 8001526: 685a ldr r2, [r3, #4] + 8001528: 4613 mov r3, r2 + 800152a: 009b lsls r3, r3, #2 + 800152c: 4413 add r3, r2 + 800152e: 3b23 subs r3, #35 ; 0x23 + 8001530: fa00 f203 lsl.w r2, r0, r3 + 8001534: 687b ldr r3, [r7, #4] + 8001536: 681b ldr r3, [r3, #0] + 8001538: 430a orrs r2, r1 + 800153a: 631a str r2, [r3, #48] ; 0x30 + 800153c: e023 b.n 8001586 + } + /* For Rank 13 to 16 */ + else + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); + 800153e: 687b ldr r3, [r7, #4] + 8001540: 681b ldr r3, [r3, #0] + 8001542: 6ad9 ldr r1, [r3, #44] ; 0x2c + 8001544: 683b ldr r3, [r7, #0] + 8001546: 685a ldr r2, [r3, #4] + 8001548: 4613 mov r3, r2 + 800154a: 009b lsls r3, r3, #2 + 800154c: 4413 add r3, r2 + 800154e: 3b41 subs r3, #65 ; 0x41 + 8001550: 221f movs r2, #31 + 8001552: fa02 f303 lsl.w r3, r2, r3 + 8001556: 43da mvns r2, r3 + 8001558: 687b ldr r3, [r7, #4] + 800155a: 681b ldr r3, [r3, #0] + 800155c: 400a ands r2, r1 + 800155e: 62da str r2, [r3, #44] ; 0x2c + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); + 8001560: 687b ldr r3, [r7, #4] + 8001562: 681b ldr r3, [r3, #0] + 8001564: 6ad9 ldr r1, [r3, #44] ; 0x2c + 8001566: 683b ldr r3, [r7, #0] + 8001568: 681b ldr r3, [r3, #0] + 800156a: b29b uxth r3, r3 + 800156c: 4618 mov r0, r3 + 800156e: 683b ldr r3, [r7, #0] + 8001570: 685a ldr r2, [r3, #4] + 8001572: 4613 mov r3, r2 + 8001574: 009b lsls r3, r3, #2 + 8001576: 4413 add r3, r2 + 8001578: 3b41 subs r3, #65 ; 0x41 + 800157a: fa00 f203 lsl.w r2, r0, r3 + 800157e: 687b ldr r3, [r7, #4] + 8001580: 681b ldr r3, [r3, #0] + 8001582: 430a orrs r2, r1 + 8001584: 62da str r2, [r3, #44] ; 0x2c + } + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + 8001586: 4b29 ldr r3, [pc, #164] ; (800162c ) + 8001588: 60fb str r3, [r7, #12] + + /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */ + if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) + 800158a: 687b ldr r3, [r7, #4] + 800158c: 681b ldr r3, [r3, #0] + 800158e: 4a28 ldr r2, [pc, #160] ; (8001630 ) + 8001590: 4293 cmp r3, r2 + 8001592: d10f bne.n 80015b4 + 8001594: 683b ldr r3, [r7, #0] + 8001596: 681b ldr r3, [r3, #0] + 8001598: 2b12 cmp r3, #18 + 800159a: d10b bne.n 80015b4 + { + /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/ + if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT) + { + tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE; + 800159c: 68fb ldr r3, [r7, #12] + 800159e: 685b ldr r3, [r3, #4] + 80015a0: f423 0200 bic.w r2, r3, #8388608 ; 0x800000 + 80015a4: 68fb ldr r3, [r7, #12] + 80015a6: 605a str r2, [r3, #4] + } + /* Enable the VBAT channel*/ + tmpADC_Common->CCR |= ADC_CCR_VBATE; + 80015a8: 68fb ldr r3, [r7, #12] + 80015aa: 685b ldr r3, [r3, #4] + 80015ac: f443 0280 orr.w r2, r3, #4194304 ; 0x400000 + 80015b0: 68fb ldr r3, [r7, #12] + 80015b2: 605a str r2, [r3, #4] + } + + /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or + Channel_17 is selected for VREFINT enable TSVREFE */ + if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) + 80015b4: 687b ldr r3, [r7, #4] + 80015b6: 681b ldr r3, [r3, #0] + 80015b8: 4a1d ldr r2, [pc, #116] ; (8001630 ) + 80015ba: 4293 cmp r3, r2 + 80015bc: d12b bne.n 8001616 + 80015be: 683b ldr r3, [r7, #0] + 80015c0: 681b ldr r3, [r3, #0] + 80015c2: 4a1c ldr r2, [pc, #112] ; (8001634 ) + 80015c4: 4293 cmp r3, r2 + 80015c6: d003 beq.n 80015d0 + 80015c8: 683b ldr r3, [r7, #0] + 80015ca: 681b ldr r3, [r3, #0] + 80015cc: 2b11 cmp r3, #17 + 80015ce: d122 bne.n 8001616 + { + /* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/ + if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT) + { + tmpADC_Common->CCR &= ~ADC_CCR_VBATE; + 80015d0: 68fb ldr r3, [r7, #12] + 80015d2: 685b ldr r3, [r3, #4] + 80015d4: f423 0280 bic.w r2, r3, #4194304 ; 0x400000 + 80015d8: 68fb ldr r3, [r7, #12] + 80015da: 605a str r2, [r3, #4] + } + /* Enable the Temperature sensor and VREFINT channel*/ + tmpADC_Common->CCR |= ADC_CCR_TSVREFE; + 80015dc: 68fb ldr r3, [r7, #12] + 80015de: 685b ldr r3, [r3, #4] + 80015e0: f443 0200 orr.w r2, r3, #8388608 ; 0x800000 + 80015e4: 68fb ldr r3, [r7, #12] + 80015e6: 605a str r2, [r3, #4] + + if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + 80015e8: 683b ldr r3, [r7, #0] + 80015ea: 681b ldr r3, [r3, #0] + 80015ec: 4a11 ldr r2, [pc, #68] ; (8001634 ) + 80015ee: 4293 cmp r3, r2 + 80015f0: d111 bne.n 8001616 + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + 80015f2: 4b11 ldr r3, [pc, #68] ; (8001638 ) + 80015f4: 681b ldr r3, [r3, #0] + 80015f6: 4a11 ldr r2, [pc, #68] ; (800163c ) + 80015f8: fba2 2303 umull r2, r3, r2, r3 + 80015fc: 0c9a lsrs r2, r3, #18 + 80015fe: 4613 mov r3, r2 + 8001600: 009b lsls r3, r3, #2 + 8001602: 4413 add r3, r2 + 8001604: 005b lsls r3, r3, #1 + 8001606: 60bb str r3, [r7, #8] + while(counter != 0U) + 8001608: e002 b.n 8001610 + { + counter--; + 800160a: 68bb ldr r3, [r7, #8] + 800160c: 3b01 subs r3, #1 + 800160e: 60bb str r3, [r7, #8] + while(counter != 0U) + 8001610: 68bb ldr r3, [r7, #8] + 8001612: 2b00 cmp r3, #0 + 8001614: d1f9 bne.n 800160a + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + 8001616: 687b ldr r3, [r7, #4] + 8001618: 2200 movs r2, #0 + 800161a: f883 203c strb.w r2, [r3, #60] ; 0x3c + + /* Return function status */ + return HAL_OK; + 800161e: 2300 movs r3, #0 +} + 8001620: 4618 mov r0, r3 + 8001622: 3714 adds r7, #20 + 8001624: 46bd mov sp, r7 + 8001626: f85d 7b04 ldr.w r7, [sp], #4 + 800162a: 4770 bx lr + 800162c: 40012300 .word 0x40012300 + 8001630: 40012000 .word 0x40012000 + 8001634: 10000012 .word 0x10000012 + 8001638: 20000000 .word 0x20000000 + 800163c: 431bde83 .word 0x431bde83 + +08001640 : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +static void ADC_Init(ADC_HandleTypeDef* hadc) +{ + 8001640: b480 push {r7} + 8001642: b085 sub sp, #20 + 8001644: af00 add r7, sp, #0 + 8001646: 6078 str r0, [r7, #4] + + /* Set ADC parameters */ + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + 8001648: 4b79 ldr r3, [pc, #484] ; (8001830 ) + 800164a: 60fb str r3, [r7, #12] + + /* Set the ADC clock prescaler */ + tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE); + 800164c: 68fb ldr r3, [r7, #12] + 800164e: 685b ldr r3, [r3, #4] + 8001650: f423 3240 bic.w r2, r3, #196608 ; 0x30000 + 8001654: 68fb ldr r3, [r7, #12] + 8001656: 605a str r2, [r3, #4] + tmpADC_Common->CCR |= hadc->Init.ClockPrescaler; + 8001658: 68fb ldr r3, [r7, #12] + 800165a: 685a ldr r2, [r3, #4] + 800165c: 687b ldr r3, [r7, #4] + 800165e: 685b ldr r3, [r3, #4] + 8001660: 431a orrs r2, r3 + 8001662: 68fb ldr r3, [r7, #12] + 8001664: 605a str r2, [r3, #4] + + /* Set ADC scan mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); + 8001666: 687b ldr r3, [r7, #4] + 8001668: 681b ldr r3, [r3, #0] + 800166a: 685a ldr r2, [r3, #4] + 800166c: 687b ldr r3, [r7, #4] + 800166e: 681b ldr r3, [r3, #0] + 8001670: f422 7280 bic.w r2, r2, #256 ; 0x100 + 8001674: 605a str r2, [r3, #4] + hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); + 8001676: 687b ldr r3, [r7, #4] + 8001678: 681b ldr r3, [r3, #0] + 800167a: 6859 ldr r1, [r3, #4] + 800167c: 687b ldr r3, [r7, #4] + 800167e: 691b ldr r3, [r3, #16] + 8001680: 021a lsls r2, r3, #8 + 8001682: 687b ldr r3, [r7, #4] + 8001684: 681b ldr r3, [r3, #0] + 8001686: 430a orrs r2, r1 + 8001688: 605a str r2, [r3, #4] + + /* Set ADC resolution */ + hadc->Instance->CR1 &= ~(ADC_CR1_RES); + 800168a: 687b ldr r3, [r7, #4] + 800168c: 681b ldr r3, [r3, #0] + 800168e: 685a ldr r2, [r3, #4] + 8001690: 687b ldr r3, [r7, #4] + 8001692: 681b ldr r3, [r3, #0] + 8001694: f022 7240 bic.w r2, r2, #50331648 ; 0x3000000 + 8001698: 605a str r2, [r3, #4] + hadc->Instance->CR1 |= hadc->Init.Resolution; + 800169a: 687b ldr r3, [r7, #4] + 800169c: 681b ldr r3, [r3, #0] + 800169e: 6859 ldr r1, [r3, #4] + 80016a0: 687b ldr r3, [r7, #4] + 80016a2: 689a ldr r2, [r3, #8] + 80016a4: 687b ldr r3, [r7, #4] + 80016a6: 681b ldr r3, [r3, #0] + 80016a8: 430a orrs r2, r1 + 80016aa: 605a str r2, [r3, #4] + + /* Set ADC data alignment */ + hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); + 80016ac: 687b ldr r3, [r7, #4] + 80016ae: 681b ldr r3, [r3, #0] + 80016b0: 689a ldr r2, [r3, #8] + 80016b2: 687b ldr r3, [r7, #4] + 80016b4: 681b ldr r3, [r3, #0] + 80016b6: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 80016ba: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= hadc->Init.DataAlign; + 80016bc: 687b ldr r3, [r7, #4] + 80016be: 681b ldr r3, [r3, #0] + 80016c0: 6899 ldr r1, [r3, #8] + 80016c2: 687b ldr r3, [r7, #4] + 80016c4: 68da ldr r2, [r3, #12] + 80016c6: 687b ldr r3, [r7, #4] + 80016c8: 681b ldr r3, [r3, #0] + 80016ca: 430a orrs r2, r1 + 80016cc: 609a str r2, [r3, #8] + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + 80016ce: 687b ldr r3, [r7, #4] + 80016d0: 6a9b ldr r3, [r3, #40] ; 0x28 + 80016d2: 4a58 ldr r2, [pc, #352] ; (8001834 ) + 80016d4: 4293 cmp r3, r2 + 80016d6: d022 beq.n 800171e + { + /* Select external trigger to start conversion */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + 80016d8: 687b ldr r3, [r7, #4] + 80016da: 681b ldr r3, [r3, #0] + 80016dc: 689a ldr r2, [r3, #8] + 80016de: 687b ldr r3, [r7, #4] + 80016e0: 681b ldr r3, [r3, #0] + 80016e2: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 + 80016e6: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; + 80016e8: 687b ldr r3, [r7, #4] + 80016ea: 681b ldr r3, [r3, #0] + 80016ec: 6899 ldr r1, [r3, #8] + 80016ee: 687b ldr r3, [r7, #4] + 80016f0: 6a9a ldr r2, [r3, #40] ; 0x28 + 80016f2: 687b ldr r3, [r7, #4] + 80016f4: 681b ldr r3, [r3, #0] + 80016f6: 430a orrs r2, r1 + 80016f8: 609a str r2, [r3, #8] + + /* Select external trigger polarity */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + 80016fa: 687b ldr r3, [r7, #4] + 80016fc: 681b ldr r3, [r3, #0] + 80016fe: 689a ldr r2, [r3, #8] + 8001700: 687b ldr r3, [r7, #4] + 8001702: 681b ldr r3, [r3, #0] + 8001704: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000 + 8001708: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; + 800170a: 687b ldr r3, [r7, #4] + 800170c: 681b ldr r3, [r3, #0] + 800170e: 6899 ldr r1, [r3, #8] + 8001710: 687b ldr r3, [r7, #4] + 8001712: 6ada ldr r2, [r3, #44] ; 0x2c + 8001714: 687b ldr r3, [r7, #4] + 8001716: 681b ldr r3, [r3, #0] + 8001718: 430a orrs r2, r1 + 800171a: 609a str r2, [r3, #8] + 800171c: e00f b.n 800173e + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + 800171e: 687b ldr r3, [r7, #4] + 8001720: 681b ldr r3, [r3, #0] + 8001722: 689a ldr r2, [r3, #8] + 8001724: 687b ldr r3, [r7, #4] + 8001726: 681b ldr r3, [r3, #0] + 8001728: f022 6270 bic.w r2, r2, #251658240 ; 0xf000000 + 800172c: 609a str r2, [r3, #8] + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + 800172e: 687b ldr r3, [r7, #4] + 8001730: 681b ldr r3, [r3, #0] + 8001732: 689a ldr r2, [r3, #8] + 8001734: 687b ldr r3, [r7, #4] + 8001736: 681b ldr r3, [r3, #0] + 8001738: f022 5240 bic.w r2, r2, #805306368 ; 0x30000000 + 800173c: 609a str r2, [r3, #8] + } + + /* Enable or disable ADC continuous conversion mode */ + hadc->Instance->CR2 &= ~(ADC_CR2_CONT); + 800173e: 687b ldr r3, [r7, #4] + 8001740: 681b ldr r3, [r3, #0] + 8001742: 689a ldr r2, [r3, #8] + 8001744: 687b ldr r3, [r7, #4] + 8001746: 681b ldr r3, [r3, #0] + 8001748: f022 0202 bic.w r2, r2, #2 + 800174c: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); + 800174e: 687b ldr r3, [r7, #4] + 8001750: 681b ldr r3, [r3, #0] + 8001752: 6899 ldr r1, [r3, #8] + 8001754: 687b ldr r3, [r7, #4] + 8001756: 7e1b ldrb r3, [r3, #24] + 8001758: 005a lsls r2, r3, #1 + 800175a: 687b ldr r3, [r7, #4] + 800175c: 681b ldr r3, [r3, #0] + 800175e: 430a orrs r2, r1 + 8001760: 609a str r2, [r3, #8] + + if(hadc->Init.DiscontinuousConvMode != DISABLE) + 8001762: 687b ldr r3, [r7, #4] + 8001764: f893 3020 ldrb.w r3, [r3, #32] + 8001768: 2b00 cmp r3, #0 + 800176a: d01b beq.n 80017a4 + { + assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); + + /* Enable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; + 800176c: 687b ldr r3, [r7, #4] + 800176e: 681b ldr r3, [r3, #0] + 8001770: 685a ldr r2, [r3, #4] + 8001772: 687b ldr r3, [r7, #4] + 8001774: 681b ldr r3, [r3, #0] + 8001776: f442 6200 orr.w r2, r2, #2048 ; 0x800 + 800177a: 605a str r2, [r3, #4] + + /* Set the number of channels to be converted in discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); + 800177c: 687b ldr r3, [r7, #4] + 800177e: 681b ldr r3, [r3, #0] + 8001780: 685a ldr r2, [r3, #4] + 8001782: 687b ldr r3, [r7, #4] + 8001784: 681b ldr r3, [r3, #0] + 8001786: f422 4260 bic.w r2, r2, #57344 ; 0xe000 + 800178a: 605a str r2, [r3, #4] + hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); + 800178c: 687b ldr r3, [r7, #4] + 800178e: 681b ldr r3, [r3, #0] + 8001790: 6859 ldr r1, [r3, #4] + 8001792: 687b ldr r3, [r7, #4] + 8001794: 6a5b ldr r3, [r3, #36] ; 0x24 + 8001796: 3b01 subs r3, #1 + 8001798: 035a lsls r2, r3, #13 + 800179a: 687b ldr r3, [r7, #4] + 800179c: 681b ldr r3, [r3, #0] + 800179e: 430a orrs r2, r1 + 80017a0: 605a str r2, [r3, #4] + 80017a2: e007 b.n 80017b4 + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); + 80017a4: 687b ldr r3, [r7, #4] + 80017a6: 681b ldr r3, [r3, #0] + 80017a8: 685a ldr r2, [r3, #4] + 80017aa: 687b ldr r3, [r7, #4] + 80017ac: 681b ldr r3, [r3, #0] + 80017ae: f422 6200 bic.w r2, r2, #2048 ; 0x800 + 80017b2: 605a str r2, [r3, #4] + } + + /* Set ADC number of conversion */ + hadc->Instance->SQR1 &= ~(ADC_SQR1_L); + 80017b4: 687b ldr r3, [r7, #4] + 80017b6: 681b ldr r3, [r3, #0] + 80017b8: 6ada ldr r2, [r3, #44] ; 0x2c + 80017ba: 687b ldr r3, [r7, #4] + 80017bc: 681b ldr r3, [r3, #0] + 80017be: f422 0270 bic.w r2, r2, #15728640 ; 0xf00000 + 80017c2: 62da str r2, [r3, #44] ; 0x2c + hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); + 80017c4: 687b ldr r3, [r7, #4] + 80017c6: 681b ldr r3, [r3, #0] + 80017c8: 6ad9 ldr r1, [r3, #44] ; 0x2c + 80017ca: 687b ldr r3, [r7, #4] + 80017cc: 69db ldr r3, [r3, #28] + 80017ce: 3b01 subs r3, #1 + 80017d0: 051a lsls r2, r3, #20 + 80017d2: 687b ldr r3, [r7, #4] + 80017d4: 681b ldr r3, [r3, #0] + 80017d6: 430a orrs r2, r1 + 80017d8: 62da str r2, [r3, #44] ; 0x2c + + /* Enable or disable ADC DMA continuous request */ + hadc->Instance->CR2 &= ~(ADC_CR2_DDS); + 80017da: 687b ldr r3, [r7, #4] + 80017dc: 681b ldr r3, [r3, #0] + 80017de: 689a ldr r2, [r3, #8] + 80017e0: 687b ldr r3, [r7, #4] + 80017e2: 681b ldr r3, [r3, #0] + 80017e4: f422 7200 bic.w r2, r2, #512 ; 0x200 + 80017e8: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests); + 80017ea: 687b ldr r3, [r7, #4] + 80017ec: 681b ldr r3, [r3, #0] + 80017ee: 6899 ldr r1, [r3, #8] + 80017f0: 687b ldr r3, [r7, #4] + 80017f2: f893 3030 ldrb.w r3, [r3, #48] ; 0x30 + 80017f6: 025a lsls r2, r3, #9 + 80017f8: 687b ldr r3, [r7, #4] + 80017fa: 681b ldr r3, [r3, #0] + 80017fc: 430a orrs r2, r1 + 80017fe: 609a str r2, [r3, #8] + + /* Enable or disable ADC end of conversion selection */ + hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); + 8001800: 687b ldr r3, [r7, #4] + 8001802: 681b ldr r3, [r3, #0] + 8001804: 689a ldr r2, [r3, #8] + 8001806: 687b ldr r3, [r7, #4] + 8001808: 681b ldr r3, [r3, #0] + 800180a: f422 6280 bic.w r2, r2, #1024 ; 0x400 + 800180e: 609a str r2, [r3, #8] + hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); + 8001810: 687b ldr r3, [r7, #4] + 8001812: 681b ldr r3, [r3, #0] + 8001814: 6899 ldr r1, [r3, #8] + 8001816: 687b ldr r3, [r7, #4] + 8001818: 695b ldr r3, [r3, #20] + 800181a: 029a lsls r2, r3, #10 + 800181c: 687b ldr r3, [r7, #4] + 800181e: 681b ldr r3, [r3, #0] + 8001820: 430a orrs r2, r1 + 8001822: 609a str r2, [r3, #8] +} + 8001824: bf00 nop + 8001826: 3714 adds r7, #20 + 8001828: 46bd mov sp, r7 + 800182a: f85d 7b04 ldr.w r7, [sp], #4 + 800182e: 4770 bx lr + 8001830: 40012300 .word 0x40012300 + 8001834: 0f000001 .word 0x0f000001 + +08001838 : + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + 8001838: b480 push {r7} + 800183a: b083 sub sp, #12 + 800183c: af00 add r7, sp, #0 + 800183e: 6078 str r0, [r7, #4] + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file + */ +} + 8001840: bf00 nop + 8001842: 370c adds r7, #12 + 8001844: 46bd mov sp, r7 + 8001846: f85d 7b04 ldr.w r7, [sp], #4 + 800184a: 4770 bx lr + +0800184c <__NVIC_SetPriorityGrouping>: In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8000d08: b480 push {r7} - 8000d0a: b085 sub sp, #20 - 8000d0c: af00 add r7, sp, #0 - 8000d0e: 6078 str r0, [r7, #4] + 800184c: b480 push {r7} + 800184e: b085 sub sp, #20 + 8001850: af00 add r7, sp, #0 + 8001852: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8000d10: 687b ldr r3, [r7, #4] - 8000d12: f003 0307 and.w r3, r3, #7 - 8000d16: 60fb str r3, [r7, #12] + 8001854: 687b ldr r3, [r7, #4] + 8001856: f003 0307 and.w r3, r3, #7 + 800185a: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ - 8000d18: 4b0c ldr r3, [pc, #48] ; (8000d4c <__NVIC_SetPriorityGrouping+0x44>) - 8000d1a: 68db ldr r3, [r3, #12] - 8000d1c: 60bb str r3, [r7, #8] + 800185c: 4b0c ldr r3, [pc, #48] ; (8001890 <__NVIC_SetPriorityGrouping+0x44>) + 800185e: 68db ldr r3, [r3, #12] + 8001860: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - 8000d1e: 68ba ldr r2, [r7, #8] - 8000d20: f64f 03ff movw r3, #63743 ; 0xf8ff - 8000d24: 4013 ands r3, r2 - 8000d26: 60bb str r3, [r7, #8] + 8001862: 68ba ldr r2, [r7, #8] + 8001864: f64f 03ff movw r3, #63743 ; 0xf8ff + 8001868: 4013 ands r3, r2 + 800186a: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - 8000d28: 68fb ldr r3, [r7, #12] - 8000d2a: 021a lsls r2, r3, #8 + 800186c: 68fb ldr r3, [r7, #12] + 800186e: 021a lsls r2, r3, #8 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - 8000d2c: 68bb ldr r3, [r7, #8] - 8000d2e: 4313 orrs r3, r2 + 8001870: 68bb ldr r3, [r7, #8] + 8001872: 4313 orrs r3, r2 reg_value = (reg_value | - 8000d30: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 - 8000d34: f443 3300 orr.w r3, r3, #131072 ; 0x20000 - 8000d38: 60bb str r3, [r7, #8] + 8001874: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 8001878: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 800187c: 60bb str r3, [r7, #8] SCB->AIRCR = reg_value; - 8000d3a: 4a04 ldr r2, [pc, #16] ; (8000d4c <__NVIC_SetPriorityGrouping+0x44>) - 8000d3c: 68bb ldr r3, [r7, #8] - 8000d3e: 60d3 str r3, [r2, #12] + 800187e: 4a04 ldr r2, [pc, #16] ; (8001890 <__NVIC_SetPriorityGrouping+0x44>) + 8001880: 68bb ldr r3, [r7, #8] + 8001882: 60d3 str r3, [r2, #12] } - 8000d40: bf00 nop - 8000d42: 3714 adds r7, #20 - 8000d44: 46bd mov sp, r7 - 8000d46: f85d 7b04 ldr.w r7, [sp], #4 - 8000d4a: 4770 bx lr - 8000d4c: e000ed00 .word 0xe000ed00 + 8001884: bf00 nop + 8001886: 3714 adds r7, #20 + 8001888: 46bd mov sp, r7 + 800188a: f85d 7b04 ldr.w r7, [sp], #4 + 800188e: 4770 bx lr + 8001890: e000ed00 .word 0xe000ed00 -08000d50 <__NVIC_GetPriorityGrouping>: +08001894 <__NVIC_GetPriorityGrouping>: \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) { - 8000d50: b480 push {r7} - 8000d52: af00 add r7, sp, #0 + 8001894: b480 push {r7} + 8001896: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); - 8000d54: 4b04 ldr r3, [pc, #16] ; (8000d68 <__NVIC_GetPriorityGrouping+0x18>) - 8000d56: 68db ldr r3, [r3, #12] - 8000d58: 0a1b lsrs r3, r3, #8 - 8000d5a: f003 0307 and.w r3, r3, #7 + 8001898: 4b04 ldr r3, [pc, #16] ; (80018ac <__NVIC_GetPriorityGrouping+0x18>) + 800189a: 68db ldr r3, [r3, #12] + 800189c: 0a1b lsrs r3, r3, #8 + 800189e: f003 0307 and.w r3, r3, #7 } - 8000d5e: 4618 mov r0, r3 - 8000d60: 46bd mov sp, r7 - 8000d62: f85d 7b04 ldr.w r7, [sp], #4 - 8000d66: 4770 bx lr - 8000d68: e000ed00 .word 0xe000ed00 + 80018a2: 4618 mov r0, r3 + 80018a4: 46bd mov sp, r7 + 80018a6: f85d 7b04 ldr.w r7, [sp], #4 + 80018aa: 4770 bx lr + 80018ac: e000ed00 .word 0xe000ed00 -08000d6c <__NVIC_EnableIRQ>: +080018b0 <__NVIC_EnableIRQ>: \details Enables a device specific interrupt in the NVIC interrupt controller. \param [in] IRQn Device specific interrupt number. \note IRQn must not be negative. */ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) { - 8000d6c: b480 push {r7} - 8000d6e: b083 sub sp, #12 - 8000d70: af00 add r7, sp, #0 - 8000d72: 4603 mov r3, r0 - 8000d74: 71fb strb r3, [r7, #7] + 80018b0: b480 push {r7} + 80018b2: b083 sub sp, #12 + 80018b4: af00 add r7, sp, #0 + 80018b6: 4603 mov r3, r0 + 80018b8: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 8000d76: f997 3007 ldrsb.w r3, [r7, #7] - 8000d7a: 2b00 cmp r3, #0 - 8000d7c: db0b blt.n 8000d96 <__NVIC_EnableIRQ+0x2a> + 80018ba: f997 3007 ldrsb.w r3, [r7, #7] + 80018be: 2b00 cmp r3, #0 + 80018c0: db0b blt.n 80018da <__NVIC_EnableIRQ+0x2a> { NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - 8000d7e: 79fb ldrb r3, [r7, #7] - 8000d80: f003 021f and.w r2, r3, #31 - 8000d84: 4907 ldr r1, [pc, #28] ; (8000da4 <__NVIC_EnableIRQ+0x38>) - 8000d86: f997 3007 ldrsb.w r3, [r7, #7] - 8000d8a: 095b lsrs r3, r3, #5 - 8000d8c: 2001 movs r0, #1 - 8000d8e: fa00 f202 lsl.w r2, r0, r2 - 8000d92: f841 2023 str.w r2, [r1, r3, lsl #2] + 80018c2: 79fb ldrb r3, [r7, #7] + 80018c4: f003 021f and.w r2, r3, #31 + 80018c8: 4907 ldr r1, [pc, #28] ; (80018e8 <__NVIC_EnableIRQ+0x38>) + 80018ca: f997 3007 ldrsb.w r3, [r7, #7] + 80018ce: 095b lsrs r3, r3, #5 + 80018d0: 2001 movs r0, #1 + 80018d2: fa00 f202 lsl.w r2, r0, r2 + 80018d6: f841 2023 str.w r2, [r1, r3, lsl #2] } } - 8000d96: bf00 nop - 8000d98: 370c adds r7, #12 - 8000d9a: 46bd mov sp, r7 - 8000d9c: f85d 7b04 ldr.w r7, [sp], #4 - 8000da0: 4770 bx lr - 8000da2: bf00 nop - 8000da4: e000e100 .word 0xe000e100 + 80018da: bf00 nop + 80018dc: 370c adds r7, #12 + 80018de: 46bd mov sp, r7 + 80018e0: f85d 7b04 ldr.w r7, [sp], #4 + 80018e4: 4770 bx lr + 80018e6: bf00 nop + 80018e8: e000e100 .word 0xe000e100 -08000da8 <__NVIC_SetPriority>: +080018ec <__NVIC_SetPriority>: \param [in] IRQn Interrupt number. \param [in] priority Priority to set. \note The priority cannot be set for every processor exception. */ __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - 8000da8: b480 push {r7} - 8000daa: b083 sub sp, #12 - 8000dac: af00 add r7, sp, #0 - 8000dae: 4603 mov r3, r0 - 8000db0: 6039 str r1, [r7, #0] - 8000db2: 71fb strb r3, [r7, #7] + 80018ec: b480 push {r7} + 80018ee: b083 sub sp, #12 + 80018f0: af00 add r7, sp, #0 + 80018f2: 4603 mov r3, r0 + 80018f4: 6039 str r1, [r7, #0] + 80018f6: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 8000db4: f997 3007 ldrsb.w r3, [r7, #7] - 8000db8: 2b00 cmp r3, #0 - 8000dba: db0a blt.n 8000dd2 <__NVIC_SetPriority+0x2a> + 80018f8: f997 3007 ldrsb.w r3, [r7, #7] + 80018fc: 2b00 cmp r3, #0 + 80018fe: db0a blt.n 8001916 <__NVIC_SetPriority+0x2a> { NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8000dbc: 683b ldr r3, [r7, #0] - 8000dbe: b2da uxtb r2, r3 - 8000dc0: 490c ldr r1, [pc, #48] ; (8000df4 <__NVIC_SetPriority+0x4c>) - 8000dc2: f997 3007 ldrsb.w r3, [r7, #7] - 8000dc6: 0112 lsls r2, r2, #4 - 8000dc8: b2d2 uxtb r2, r2 - 8000dca: 440b add r3, r1 - 8000dcc: f883 2300 strb.w r2, [r3, #768] ; 0x300 + 8001900: 683b ldr r3, [r7, #0] + 8001902: b2da uxtb r2, r3 + 8001904: 490c ldr r1, [pc, #48] ; (8001938 <__NVIC_SetPriority+0x4c>) + 8001906: f997 3007 ldrsb.w r3, [r7, #7] + 800190a: 0112 lsls r2, r2, #4 + 800190c: b2d2 uxtb r2, r2 + 800190e: 440b add r3, r1 + 8001910: f883 2300 strb.w r2, [r3, #768] ; 0x300 } else { SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); } } - 8000dd0: e00a b.n 8000de8 <__NVIC_SetPriority+0x40> + 8001914: e00a b.n 800192c <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 8000dd2: 683b ldr r3, [r7, #0] - 8000dd4: b2da uxtb r2, r3 - 8000dd6: 4908 ldr r1, [pc, #32] ; (8000df8 <__NVIC_SetPriority+0x50>) - 8000dd8: 79fb ldrb r3, [r7, #7] - 8000dda: f003 030f and.w r3, r3, #15 - 8000dde: 3b04 subs r3, #4 - 8000de0: 0112 lsls r2, r2, #4 - 8000de2: b2d2 uxtb r2, r2 - 8000de4: 440b add r3, r1 - 8000de6: 761a strb r2, [r3, #24] + 8001916: 683b ldr r3, [r7, #0] + 8001918: b2da uxtb r2, r3 + 800191a: 4908 ldr r1, [pc, #32] ; (800193c <__NVIC_SetPriority+0x50>) + 800191c: 79fb ldrb r3, [r7, #7] + 800191e: f003 030f and.w r3, r3, #15 + 8001922: 3b04 subs r3, #4 + 8001924: 0112 lsls r2, r2, #4 + 8001926: b2d2 uxtb r2, r2 + 8001928: 440b add r3, r1 + 800192a: 761a strb r2, [r3, #24] } - 8000de8: bf00 nop - 8000dea: 370c adds r7, #12 - 8000dec: 46bd mov sp, r7 - 8000dee: f85d 7b04 ldr.w r7, [sp], #4 - 8000df2: 4770 bx lr - 8000df4: e000e100 .word 0xe000e100 - 8000df8: e000ed00 .word 0xe000ed00 + 800192c: bf00 nop + 800192e: 370c adds r7, #12 + 8001930: 46bd mov sp, r7 + 8001932: f85d 7b04 ldr.w r7, [sp], #4 + 8001936: 4770 bx lr + 8001938: e000e100 .word 0xe000e100 + 800193c: e000ed00 .word 0xe000ed00 -08000dfc : +08001940 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - 8000dfc: b480 push {r7} - 8000dfe: b089 sub sp, #36 ; 0x24 - 8000e00: af00 add r7, sp, #0 - 8000e02: 60f8 str r0, [r7, #12] - 8000e04: 60b9 str r1, [r7, #8] - 8000e06: 607a str r2, [r7, #4] + 8001940: b480 push {r7} + 8001942: b089 sub sp, #36 ; 0x24 + 8001944: af00 add r7, sp, #0 + 8001946: 60f8 str r0, [r7, #12] + 8001948: 60b9 str r1, [r7, #8] + 800194a: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - 8000e08: 68fb ldr r3, [r7, #12] - 8000e0a: f003 0307 and.w r3, r3, #7 - 8000e0e: 61fb str r3, [r7, #28] + 800194c: 68fb ldr r3, [r7, #12] + 800194e: f003 0307 and.w r3, r3, #7 + 8001952: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - 8000e10: 69fb ldr r3, [r7, #28] - 8000e12: f1c3 0307 rsb r3, r3, #7 - 8000e16: 2b04 cmp r3, #4 - 8000e18: bf28 it cs - 8000e1a: 2304 movcs r3, #4 - 8000e1c: 61bb str r3, [r7, #24] + 8001954: 69fb ldr r3, [r7, #28] + 8001956: f1c3 0307 rsb r3, r3, #7 + 800195a: 2b04 cmp r3, #4 + 800195c: bf28 it cs + 800195e: 2304 movcs r3, #4 + 8001960: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - 8000e1e: 69fb ldr r3, [r7, #28] - 8000e20: 3304 adds r3, #4 - 8000e22: 2b06 cmp r3, #6 - 8000e24: d902 bls.n 8000e2c - 8000e26: 69fb ldr r3, [r7, #28] - 8000e28: 3b03 subs r3, #3 - 8000e2a: e000 b.n 8000e2e - 8000e2c: 2300 movs r3, #0 - 8000e2e: 617b str r3, [r7, #20] + 8001962: 69fb ldr r3, [r7, #28] + 8001964: 3304 adds r3, #4 + 8001966: 2b06 cmp r3, #6 + 8001968: d902 bls.n 8001970 + 800196a: 69fb ldr r3, [r7, #28] + 800196c: 3b03 subs r3, #3 + 800196e: e000 b.n 8001972 + 8001970: 2300 movs r3, #0 + 8001972: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8000e30: f04f 32ff mov.w r2, #4294967295 - 8000e34: 69bb ldr r3, [r7, #24] - 8000e36: fa02 f303 lsl.w r3, r2, r3 - 8000e3a: 43da mvns r2, r3 - 8000e3c: 68bb ldr r3, [r7, #8] - 8000e3e: 401a ands r2, r3 - 8000e40: 697b ldr r3, [r7, #20] - 8000e42: 409a lsls r2, r3 + 8001974: f04f 32ff mov.w r2, #4294967295 + 8001978: 69bb ldr r3, [r7, #24] + 800197a: fa02 f303 lsl.w r3, r2, r3 + 800197e: 43da mvns r2, r3 + 8001980: 68bb ldr r3, [r7, #8] + 8001982: 401a ands r2, r3 + 8001984: 697b ldr r3, [r7, #20] + 8001986: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - 8000e44: f04f 31ff mov.w r1, #4294967295 - 8000e48: 697b ldr r3, [r7, #20] - 8000e4a: fa01 f303 lsl.w r3, r1, r3 - 8000e4e: 43d9 mvns r1, r3 - 8000e50: 687b ldr r3, [r7, #4] - 8000e52: 400b ands r3, r1 + 8001988: f04f 31ff mov.w r1, #4294967295 + 800198c: 697b ldr r3, [r7, #20] + 800198e: fa01 f303 lsl.w r3, r1, r3 + 8001992: 43d9 mvns r1, r3 + 8001994: 687b ldr r3, [r7, #4] + 8001996: 400b ands r3, r1 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - 8000e54: 4313 orrs r3, r2 + 8001998: 4313 orrs r3, r2 ); } - 8000e56: 4618 mov r0, r3 - 8000e58: 3724 adds r7, #36 ; 0x24 - 8000e5a: 46bd mov sp, r7 - 8000e5c: f85d 7b04 ldr.w r7, [sp], #4 - 8000e60: 4770 bx lr + 800199a: 4618 mov r0, r3 + 800199c: 3724 adds r7, #36 ; 0x24 + 800199e: 46bd mov sp, r7 + 80019a0: f85d 7b04 ldr.w r7, [sp], #4 + 80019a4: 4770 bx lr -08000e62 : +080019a6 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { - 8000e62: b580 push {r7, lr} - 8000e64: b082 sub sp, #8 - 8000e66: af00 add r7, sp, #0 - 8000e68: 6078 str r0, [r7, #4] + 80019a6: b580 push {r7, lr} + 80019a8: b082 sub sp, #8 + 80019aa: af00 add r7, sp, #0 + 80019ac: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); - 8000e6a: 6878 ldr r0, [r7, #4] - 8000e6c: f7ff ff4c bl 8000d08 <__NVIC_SetPriorityGrouping> + 80019ae: 6878 ldr r0, [r7, #4] + 80019b0: f7ff ff4c bl 800184c <__NVIC_SetPriorityGrouping> } - 8000e70: bf00 nop - 8000e72: 3708 adds r7, #8 - 8000e74: 46bd mov sp, r7 - 8000e76: bd80 pop {r7, pc} + 80019b4: bf00 nop + 80019b6: 3708 adds r7, #8 + 80019b8: 46bd mov sp, r7 + 80019ba: bd80 pop {r7, pc} -08000e78 : +080019bc : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { - 8000e78: b580 push {r7, lr} - 8000e7a: b086 sub sp, #24 - 8000e7c: af00 add r7, sp, #0 - 8000e7e: 4603 mov r3, r0 - 8000e80: 60b9 str r1, [r7, #8] - 8000e82: 607a str r2, [r7, #4] - 8000e84: 73fb strb r3, [r7, #15] + 80019bc: b580 push {r7, lr} + 80019be: b086 sub sp, #24 + 80019c0: af00 add r7, sp, #0 + 80019c2: 4603 mov r3, r0 + 80019c4: 60b9 str r1, [r7, #8] + 80019c6: 607a str r2, [r7, #4] + 80019c8: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00U; - 8000e86: 2300 movs r3, #0 - 8000e88: 617b str r3, [r7, #20] + 80019ca: 2300 movs r3, #0 + 80019cc: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); - 8000e8a: f7ff ff61 bl 8000d50 <__NVIC_GetPriorityGrouping> - 8000e8e: 6178 str r0, [r7, #20] + 80019ce: f7ff ff61 bl 8001894 <__NVIC_GetPriorityGrouping> + 80019d2: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); - 8000e90: 687a ldr r2, [r7, #4] - 8000e92: 68b9 ldr r1, [r7, #8] - 8000e94: 6978 ldr r0, [r7, #20] - 8000e96: f7ff ffb1 bl 8000dfc - 8000e9a: 4602 mov r2, r0 - 8000e9c: f997 300f ldrsb.w r3, [r7, #15] - 8000ea0: 4611 mov r1, r2 - 8000ea2: 4618 mov r0, r3 - 8000ea4: f7ff ff80 bl 8000da8 <__NVIC_SetPriority> + 80019d4: 687a ldr r2, [r7, #4] + 80019d6: 68b9 ldr r1, [r7, #8] + 80019d8: 6978 ldr r0, [r7, #20] + 80019da: f7ff ffb1 bl 8001940 + 80019de: 4602 mov r2, r0 + 80019e0: f997 300f ldrsb.w r3, [r7, #15] + 80019e4: 4611 mov r1, r2 + 80019e6: 4618 mov r0, r3 + 80019e8: f7ff ff80 bl 80018ec <__NVIC_SetPriority> } - 8000ea8: bf00 nop - 8000eaa: 3718 adds r7, #24 - 8000eac: 46bd mov sp, r7 - 8000eae: bd80 pop {r7, pc} + 80019ec: bf00 nop + 80019ee: 3718 adds r7, #24 + 80019f0: 46bd mov sp, r7 + 80019f2: bd80 pop {r7, pc} -08000eb0 : +080019f4 : * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { - 8000eb0: b580 push {r7, lr} - 8000eb2: b082 sub sp, #8 - 8000eb4: af00 add r7, sp, #0 - 8000eb6: 4603 mov r3, r0 - 8000eb8: 71fb strb r3, [r7, #7] + 80019f4: b580 push {r7, lr} + 80019f6: b082 sub sp, #8 + 80019f8: af00 add r7, sp, #0 + 80019fa: 4603 mov r3, r0 + 80019fc: 71fb strb r3, [r7, #7] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); - 8000eba: f997 3007 ldrsb.w r3, [r7, #7] - 8000ebe: 4618 mov r0, r3 - 8000ec0: f7ff ff54 bl 8000d6c <__NVIC_EnableIRQ> + 80019fe: f997 3007 ldrsb.w r3, [r7, #7] + 8001a02: 4618 mov r0, r3 + 8001a04: f7ff ff54 bl 80018b0 <__NVIC_EnableIRQ> } - 8000ec4: bf00 nop - 8000ec6: 3708 adds r7, #8 - 8000ec8: 46bd mov sp, r7 - 8000eca: bd80 pop {r7, pc} + 8001a08: bf00 nop + 8001a0a: 3708 adds r7, #8 + 8001a0c: 46bd mov sp, r7 + 8001a0e: bd80 pop {r7, pc} -08000ecc : +08001a10 : * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - 8000ecc: b480 push {r7} - 8000ece: b089 sub sp, #36 ; 0x24 - 8000ed0: af00 add r7, sp, #0 - 8000ed2: 6078 str r0, [r7, #4] - 8000ed4: 6039 str r1, [r7, #0] + 8001a10: b480 push {r7} + 8001a12: b089 sub sp, #36 ; 0x24 + 8001a14: af00 add r7, sp, #0 + 8001a16: 6078 str r0, [r7, #4] + 8001a18: 6039 str r1, [r7, #0] uint32_t position; uint32_t ioposition = 0x00U; - 8000ed6: 2300 movs r3, #0 - 8000ed8: 617b str r3, [r7, #20] + 8001a1a: 2300 movs r3, #0 + 8001a1c: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00U; - 8000eda: 2300 movs r3, #0 - 8000edc: 613b str r3, [r7, #16] + 8001a1e: 2300 movs r3, #0 + 8001a20: 613b str r3, [r7, #16] uint32_t temp = 0x00U; - 8000ede: 2300 movs r3, #0 - 8000ee0: 61bb str r3, [r7, #24] + 8001a22: 2300 movs r3, #0 + 8001a24: 61bb str r3, [r7, #24] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) - 8000ee2: 2300 movs r3, #0 - 8000ee4: 61fb str r3, [r7, #28] - 8000ee6: e159 b.n 800119c + 8001a26: 2300 movs r3, #0 + 8001a28: 61fb str r3, [r7, #28] + 8001a2a: e159 b.n 8001ce0 { /* Get the IO position */ ioposition = 0x01U << position; - 8000ee8: 2201 movs r2, #1 - 8000eea: 69fb ldr r3, [r7, #28] - 8000eec: fa02 f303 lsl.w r3, r2, r3 - 8000ef0: 617b str r3, [r7, #20] + 8001a2c: 2201 movs r2, #1 + 8001a2e: 69fb ldr r3, [r7, #28] + 8001a30: fa02 f303 lsl.w r3, r2, r3 + 8001a34: 617b str r3, [r7, #20] /* Get the current IO position */ iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition; - 8000ef2: 683b ldr r3, [r7, #0] - 8000ef4: 681b ldr r3, [r3, #0] - 8000ef6: 697a ldr r2, [r7, #20] - 8000ef8: 4013 ands r3, r2 - 8000efa: 613b str r3, [r7, #16] + 8001a36: 683b ldr r3, [r7, #0] + 8001a38: 681b ldr r3, [r3, #0] + 8001a3a: 697a ldr r2, [r7, #20] + 8001a3c: 4013 ands r3, r2 + 8001a3e: 613b str r3, [r7, #16] if(iocurrent == ioposition) - 8000efc: 693a ldr r2, [r7, #16] - 8000efe: 697b ldr r3, [r7, #20] - 8000f00: 429a cmp r2, r3 - 8000f02: f040 8148 bne.w 8001196 + 8001a40: 693a ldr r2, [r7, #16] + 8001a42: 697b ldr r3, [r7, #20] + 8001a44: 429a cmp r2, r3 + 8001a46: f040 8148 bne.w 8001cda { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Output or Alternate function mode selection */ if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ - 8000f06: 683b ldr r3, [r7, #0] - 8000f08: 685b ldr r3, [r3, #4] - 8000f0a: f003 0303 and.w r3, r3, #3 - 8000f0e: 2b01 cmp r3, #1 - 8000f10: d005 beq.n 8000f1e + 8001a4a: 683b ldr r3, [r7, #0] + 8001a4c: 685b ldr r3, [r3, #4] + 8001a4e: f003 0303 and.w r3, r3, #3 + 8001a52: 2b01 cmp r3, #1 + 8001a54: d005 beq.n 8001a62 (GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 8000f12: 683b ldr r3, [r7, #0] - 8000f14: 685b ldr r3, [r3, #4] - 8000f16: f003 0303 and.w r3, r3, #3 + 8001a56: 683b ldr r3, [r7, #0] + 8001a58: 685b ldr r3, [r3, #4] + 8001a5a: f003 0303 and.w r3, r3, #3 if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \ - 8000f1a: 2b02 cmp r3, #2 - 8000f1c: d130 bne.n 8000f80 + 8001a5e: 2b02 cmp r3, #2 + 8001a60: d130 bne.n 8001ac4 { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; - 8000f1e: 687b ldr r3, [r7, #4] - 8000f20: 689b ldr r3, [r3, #8] - 8000f22: 61bb str r3, [r7, #24] + 8001a62: 687b ldr r3, [r7, #4] + 8001a64: 689b ldr r3, [r3, #8] + 8001a66: 61bb str r3, [r7, #24] temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U)); - 8000f24: 69fb ldr r3, [r7, #28] - 8000f26: 005b lsls r3, r3, #1 - 8000f28: 2203 movs r2, #3 - 8000f2a: fa02 f303 lsl.w r3, r2, r3 - 8000f2e: 43db mvns r3, r3 - 8000f30: 69ba ldr r2, [r7, #24] - 8000f32: 4013 ands r3, r2 - 8000f34: 61bb str r3, [r7, #24] + 8001a68: 69fb ldr r3, [r7, #28] + 8001a6a: 005b lsls r3, r3, #1 + 8001a6c: 2203 movs r2, #3 + 8001a6e: fa02 f303 lsl.w r3, r2, r3 + 8001a72: 43db mvns r3, r3 + 8001a74: 69ba ldr r2, [r7, #24] + 8001a76: 4013 ands r3, r2 + 8001a78: 61bb str r3, [r7, #24] temp |= (GPIO_Init->Speed << (position * 2U)); - 8000f36: 683b ldr r3, [r7, #0] - 8000f38: 68da ldr r2, [r3, #12] - 8000f3a: 69fb ldr r3, [r7, #28] - 8000f3c: 005b lsls r3, r3, #1 - 8000f3e: fa02 f303 lsl.w r3, r2, r3 - 8000f42: 69ba ldr r2, [r7, #24] - 8000f44: 4313 orrs r3, r2 - 8000f46: 61bb str r3, [r7, #24] + 8001a7a: 683b ldr r3, [r7, #0] + 8001a7c: 68da ldr r2, [r3, #12] + 8001a7e: 69fb ldr r3, [r7, #28] + 8001a80: 005b lsls r3, r3, #1 + 8001a82: fa02 f303 lsl.w r3, r2, r3 + 8001a86: 69ba ldr r2, [r7, #24] + 8001a88: 4313 orrs r3, r2 + 8001a8a: 61bb str r3, [r7, #24] GPIOx->OSPEEDR = temp; - 8000f48: 687b ldr r3, [r7, #4] - 8000f4a: 69ba ldr r2, [r7, #24] - 8000f4c: 609a str r2, [r3, #8] + 8001a8c: 687b ldr r3, [r7, #4] + 8001a8e: 69ba ldr r2, [r7, #24] + 8001a90: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; - 8000f4e: 687b ldr r3, [r7, #4] - 8000f50: 685b ldr r3, [r3, #4] - 8000f52: 61bb str r3, [r7, #24] + 8001a92: 687b ldr r3, [r7, #4] + 8001a94: 685b ldr r3, [r3, #4] + 8001a96: 61bb str r3, [r7, #24] temp &= ~(GPIO_OTYPER_OT_0 << position) ; - 8000f54: 2201 movs r2, #1 - 8000f56: 69fb ldr r3, [r7, #28] - 8000f58: fa02 f303 lsl.w r3, r2, r3 - 8000f5c: 43db mvns r3, r3 - 8000f5e: 69ba ldr r2, [r7, #24] - 8000f60: 4013 ands r3, r2 - 8000f62: 61bb str r3, [r7, #24] + 8001a98: 2201 movs r2, #1 + 8001a9a: 69fb ldr r3, [r7, #28] + 8001a9c: fa02 f303 lsl.w r3, r2, r3 + 8001aa0: 43db mvns r3, r3 + 8001aa2: 69ba ldr r2, [r7, #24] + 8001aa4: 4013 ands r3, r2 + 8001aa6: 61bb str r3, [r7, #24] temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); - 8000f64: 683b ldr r3, [r7, #0] - 8000f66: 685b ldr r3, [r3, #4] - 8000f68: 091b lsrs r3, r3, #4 - 8000f6a: f003 0201 and.w r2, r3, #1 - 8000f6e: 69fb ldr r3, [r7, #28] - 8000f70: fa02 f303 lsl.w r3, r2, r3 - 8000f74: 69ba ldr r2, [r7, #24] - 8000f76: 4313 orrs r3, r2 - 8000f78: 61bb str r3, [r7, #24] + 8001aa8: 683b ldr r3, [r7, #0] + 8001aaa: 685b ldr r3, [r3, #4] + 8001aac: 091b lsrs r3, r3, #4 + 8001aae: f003 0201 and.w r2, r3, #1 + 8001ab2: 69fb ldr r3, [r7, #28] + 8001ab4: fa02 f303 lsl.w r3, r2, r3 + 8001ab8: 69ba ldr r2, [r7, #24] + 8001aba: 4313 orrs r3, r2 + 8001abc: 61bb str r3, [r7, #24] GPIOx->OTYPER = temp; - 8000f7a: 687b ldr r3, [r7, #4] - 8000f7c: 69ba ldr r2, [r7, #24] - 8000f7e: 605a str r2, [r3, #4] + 8001abe: 687b ldr r3, [r7, #4] + 8001ac0: 69ba ldr r2, [r7, #24] + 8001ac2: 605a str r2, [r3, #4] } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) - 8000f80: 683b ldr r3, [r7, #0] - 8000f82: 685b ldr r3, [r3, #4] - 8000f84: f003 0303 and.w r3, r3, #3 - 8000f88: 2b03 cmp r3, #3 - 8000f8a: d017 beq.n 8000fbc + 8001ac4: 683b ldr r3, [r7, #0] + 8001ac6: 685b ldr r3, [r3, #4] + 8001ac8: f003 0303 and.w r3, r3, #3 + 8001acc: 2b03 cmp r3, #3 + 8001ace: d017 beq.n 8001b00 { /* Check the parameters */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; - 8000f8c: 687b ldr r3, [r7, #4] - 8000f8e: 68db ldr r3, [r3, #12] - 8000f90: 61bb str r3, [r7, #24] + 8001ad0: 687b ldr r3, [r7, #4] + 8001ad2: 68db ldr r3, [r3, #12] + 8001ad4: 61bb str r3, [r7, #24] temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); - 8000f92: 69fb ldr r3, [r7, #28] - 8000f94: 005b lsls r3, r3, #1 - 8000f96: 2203 movs r2, #3 - 8000f98: fa02 f303 lsl.w r3, r2, r3 - 8000f9c: 43db mvns r3, r3 - 8000f9e: 69ba ldr r2, [r7, #24] - 8000fa0: 4013 ands r3, r2 - 8000fa2: 61bb str r3, [r7, #24] + 8001ad6: 69fb ldr r3, [r7, #28] + 8001ad8: 005b lsls r3, r3, #1 + 8001ada: 2203 movs r2, #3 + 8001adc: fa02 f303 lsl.w r3, r2, r3 + 8001ae0: 43db mvns r3, r3 + 8001ae2: 69ba ldr r2, [r7, #24] + 8001ae4: 4013 ands r3, r2 + 8001ae6: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Pull) << (position * 2U)); - 8000fa4: 683b ldr r3, [r7, #0] - 8000fa6: 689a ldr r2, [r3, #8] - 8000fa8: 69fb ldr r3, [r7, #28] - 8000faa: 005b lsls r3, r3, #1 - 8000fac: fa02 f303 lsl.w r3, r2, r3 - 8000fb0: 69ba ldr r2, [r7, #24] - 8000fb2: 4313 orrs r3, r2 - 8000fb4: 61bb str r3, [r7, #24] + 8001ae8: 683b ldr r3, [r7, #0] + 8001aea: 689a ldr r2, [r3, #8] + 8001aec: 69fb ldr r3, [r7, #28] + 8001aee: 005b lsls r3, r3, #1 + 8001af0: fa02 f303 lsl.w r3, r2, r3 + 8001af4: 69ba ldr r2, [r7, #24] + 8001af6: 4313 orrs r3, r2 + 8001af8: 61bb str r3, [r7, #24] GPIOx->PUPDR = temp; - 8000fb6: 687b ldr r3, [r7, #4] - 8000fb8: 69ba ldr r2, [r7, #24] - 8000fba: 60da str r2, [r3, #12] + 8001afa: 687b ldr r3, [r7, #4] + 8001afc: 69ba ldr r2, [r7, #24] + 8001afe: 60da str r2, [r3, #12] } /* In case of Alternate function mode selection */ if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) - 8000fbc: 683b ldr r3, [r7, #0] - 8000fbe: 685b ldr r3, [r3, #4] - 8000fc0: f003 0303 and.w r3, r3, #3 - 8000fc4: 2b02 cmp r3, #2 - 8000fc6: d123 bne.n 8001010 + 8001b00: 683b ldr r3, [r7, #0] + 8001b02: 685b ldr r3, [r3, #4] + 8001b04: f003 0303 and.w r3, r3, #3 + 8001b08: 2b02 cmp r3, #2 + 8001b0a: d123 bne.n 8001b54 { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3U]; - 8000fc8: 69fb ldr r3, [r7, #28] - 8000fca: 08da lsrs r2, r3, #3 - 8000fcc: 687b ldr r3, [r7, #4] - 8000fce: 3208 adds r2, #8 - 8000fd0: f853 3022 ldr.w r3, [r3, r2, lsl #2] - 8000fd4: 61bb str r3, [r7, #24] + 8001b0c: 69fb ldr r3, [r7, #28] + 8001b0e: 08da lsrs r2, r3, #3 + 8001b10: 687b ldr r3, [r7, #4] + 8001b12: 3208 adds r2, #8 + 8001b14: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8001b18: 61bb str r3, [r7, #24] temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ; - 8000fd6: 69fb ldr r3, [r7, #28] - 8000fd8: f003 0307 and.w r3, r3, #7 - 8000fdc: 009b lsls r3, r3, #2 - 8000fde: 220f movs r2, #15 - 8000fe0: fa02 f303 lsl.w r3, r2, r3 - 8000fe4: 43db mvns r3, r3 - 8000fe6: 69ba ldr r2, [r7, #24] - 8000fe8: 4013 ands r3, r2 - 8000fea: 61bb str r3, [r7, #24] + 8001b1a: 69fb ldr r3, [r7, #28] + 8001b1c: f003 0307 and.w r3, r3, #7 + 8001b20: 009b lsls r3, r3, #2 + 8001b22: 220f movs r2, #15 + 8001b24: fa02 f303 lsl.w r3, r2, r3 + 8001b28: 43db mvns r3, r3 + 8001b2a: 69ba ldr r2, [r7, #24] + 8001b2c: 4013 ands r3, r2 + 8001b2e: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U)); - 8000fec: 683b ldr r3, [r7, #0] - 8000fee: 691a ldr r2, [r3, #16] - 8000ff0: 69fb ldr r3, [r7, #28] - 8000ff2: f003 0307 and.w r3, r3, #7 - 8000ff6: 009b lsls r3, r3, #2 - 8000ff8: fa02 f303 lsl.w r3, r2, r3 - 8000ffc: 69ba ldr r2, [r7, #24] - 8000ffe: 4313 orrs r3, r2 - 8001000: 61bb str r3, [r7, #24] + 8001b30: 683b ldr r3, [r7, #0] + 8001b32: 691a ldr r2, [r3, #16] + 8001b34: 69fb ldr r3, [r7, #28] + 8001b36: f003 0307 and.w r3, r3, #7 + 8001b3a: 009b lsls r3, r3, #2 + 8001b3c: fa02 f303 lsl.w r3, r2, r3 + 8001b40: 69ba ldr r2, [r7, #24] + 8001b42: 4313 orrs r3, r2 + 8001b44: 61bb str r3, [r7, #24] GPIOx->AFR[position >> 3U] = temp; - 8001002: 69fb ldr r3, [r7, #28] - 8001004: 08da lsrs r2, r3, #3 - 8001006: 687b ldr r3, [r7, #4] - 8001008: 3208 adds r2, #8 - 800100a: 69b9 ldr r1, [r7, #24] - 800100c: f843 1022 str.w r1, [r3, r2, lsl #2] + 8001b46: 69fb ldr r3, [r7, #28] + 8001b48: 08da lsrs r2, r3, #3 + 8001b4a: 687b ldr r3, [r7, #4] + 8001b4c: 3208 adds r2, #8 + 8001b4e: 69b9 ldr r1, [r7, #24] + 8001b50: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; - 8001010: 687b ldr r3, [r7, #4] - 8001012: 681b ldr r3, [r3, #0] - 8001014: 61bb str r3, [r7, #24] + 8001b54: 687b ldr r3, [r7, #4] + 8001b56: 681b ldr r3, [r3, #0] + 8001b58: 61bb str r3, [r7, #24] temp &= ~(GPIO_MODER_MODER0 << (position * 2U)); - 8001016: 69fb ldr r3, [r7, #28] - 8001018: 005b lsls r3, r3, #1 - 800101a: 2203 movs r2, #3 - 800101c: fa02 f303 lsl.w r3, r2, r3 - 8001020: 43db mvns r3, r3 - 8001022: 69ba ldr r2, [r7, #24] - 8001024: 4013 ands r3, r2 - 8001026: 61bb str r3, [r7, #24] + 8001b5a: 69fb ldr r3, [r7, #28] + 8001b5c: 005b lsls r3, r3, #1 + 8001b5e: 2203 movs r2, #3 + 8001b60: fa02 f303 lsl.w r3, r2, r3 + 8001b64: 43db mvns r3, r3 + 8001b66: 69ba ldr r2, [r7, #24] + 8001b68: 4013 ands r3, r2 + 8001b6a: 61bb str r3, [r7, #24] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); - 8001028: 683b ldr r3, [r7, #0] - 800102a: 685b ldr r3, [r3, #4] - 800102c: f003 0203 and.w r2, r3, #3 - 8001030: 69fb ldr r3, [r7, #28] - 8001032: 005b lsls r3, r3, #1 - 8001034: fa02 f303 lsl.w r3, r2, r3 - 8001038: 69ba ldr r2, [r7, #24] - 800103a: 4313 orrs r3, r2 - 800103c: 61bb str r3, [r7, #24] + 8001b6c: 683b ldr r3, [r7, #0] + 8001b6e: 685b ldr r3, [r3, #4] + 8001b70: f003 0203 and.w r2, r3, #3 + 8001b74: 69fb ldr r3, [r7, #28] + 8001b76: 005b lsls r3, r3, #1 + 8001b78: fa02 f303 lsl.w r3, r2, r3 + 8001b7c: 69ba ldr r2, [r7, #24] + 8001b7e: 4313 orrs r3, r2 + 8001b80: 61bb str r3, [r7, #24] GPIOx->MODER = temp; - 800103e: 687b ldr r3, [r7, #4] - 8001040: 69ba ldr r2, [r7, #24] - 8001042: 601a str r2, [r3, #0] + 8001b82: 687b ldr r3, [r7, #4] + 8001b84: 69ba ldr r2, [r7, #24] + 8001b86: 601a str r2, [r3, #0] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) - 8001044: 683b ldr r3, [r7, #0] - 8001046: 685b ldr r3, [r3, #4] - 8001048: f403 3340 and.w r3, r3, #196608 ; 0x30000 - 800104c: 2b00 cmp r3, #0 - 800104e: f000 80a2 beq.w 8001196 + 8001b88: 683b ldr r3, [r7, #0] + 8001b8a: 685b ldr r3, [r3, #4] + 8001b8c: f403 3340 and.w r3, r3, #196608 ; 0x30000 + 8001b90: 2b00 cmp r3, #0 + 8001b92: f000 80a2 beq.w 8001cda { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); - 8001052: 2300 movs r3, #0 - 8001054: 60fb str r3, [r7, #12] - 8001056: 4b57 ldr r3, [pc, #348] ; (80011b4 ) - 8001058: 6c5b ldr r3, [r3, #68] ; 0x44 - 800105a: 4a56 ldr r2, [pc, #344] ; (80011b4 ) - 800105c: f443 4380 orr.w r3, r3, #16384 ; 0x4000 - 8001060: 6453 str r3, [r2, #68] ; 0x44 - 8001062: 4b54 ldr r3, [pc, #336] ; (80011b4 ) - 8001064: 6c5b ldr r3, [r3, #68] ; 0x44 - 8001066: f403 4380 and.w r3, r3, #16384 ; 0x4000 - 800106a: 60fb str r3, [r7, #12] - 800106c: 68fb ldr r3, [r7, #12] + 8001b96: 2300 movs r3, #0 + 8001b98: 60fb str r3, [r7, #12] + 8001b9a: 4b57 ldr r3, [pc, #348] ; (8001cf8 ) + 8001b9c: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001b9e: 4a56 ldr r2, [pc, #344] ; (8001cf8 ) + 8001ba0: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 8001ba4: 6453 str r3, [r2, #68] ; 0x44 + 8001ba6: 4b54 ldr r3, [pc, #336] ; (8001cf8 ) + 8001ba8: 6c5b ldr r3, [r3, #68] ; 0x44 + 8001baa: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8001bae: 60fb str r3, [r7, #12] + 8001bb0: 68fb ldr r3, [r7, #12] temp = SYSCFG->EXTICR[position >> 2U]; - 800106e: 4a52 ldr r2, [pc, #328] ; (80011b8 ) - 8001070: 69fb ldr r3, [r7, #28] - 8001072: 089b lsrs r3, r3, #2 - 8001074: 3302 adds r3, #2 - 8001076: f852 3023 ldr.w r3, [r2, r3, lsl #2] - 800107a: 61bb str r3, [r7, #24] + 8001bb2: 4a52 ldr r2, [pc, #328] ; (8001cfc ) + 8001bb4: 69fb ldr r3, [r7, #28] + 8001bb6: 089b lsrs r3, r3, #2 + 8001bb8: 3302 adds r3, #2 + 8001bba: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8001bbe: 61bb str r3, [r7, #24] temp &= ~(0x0FU << (4U * (position & 0x03U))); - 800107c: 69fb ldr r3, [r7, #28] - 800107e: f003 0303 and.w r3, r3, #3 - 8001082: 009b lsls r3, r3, #2 - 8001084: 220f movs r2, #15 - 8001086: fa02 f303 lsl.w r3, r2, r3 - 800108a: 43db mvns r3, r3 - 800108c: 69ba ldr r2, [r7, #24] - 800108e: 4013 ands r3, r2 - 8001090: 61bb str r3, [r7, #24] + 8001bc0: 69fb ldr r3, [r7, #28] + 8001bc2: f003 0303 and.w r3, r3, #3 + 8001bc6: 009b lsls r3, r3, #2 + 8001bc8: 220f movs r2, #15 + 8001bca: fa02 f303 lsl.w r3, r2, r3 + 8001bce: 43db mvns r3, r3 + 8001bd0: 69ba ldr r2, [r7, #24] + 8001bd2: 4013 ands r3, r2 + 8001bd4: 61bb str r3, [r7, #24] temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); - 8001092: 687b ldr r3, [r7, #4] - 8001094: 4a49 ldr r2, [pc, #292] ; (80011bc ) - 8001096: 4293 cmp r3, r2 - 8001098: d019 beq.n 80010ce - 800109a: 687b ldr r3, [r7, #4] - 800109c: 4a48 ldr r2, [pc, #288] ; (80011c0 ) - 800109e: 4293 cmp r3, r2 - 80010a0: d013 beq.n 80010ca - 80010a2: 687b ldr r3, [r7, #4] - 80010a4: 4a47 ldr r2, [pc, #284] ; (80011c4 ) - 80010a6: 4293 cmp r3, r2 - 80010a8: d00d beq.n 80010c6 - 80010aa: 687b ldr r3, [r7, #4] - 80010ac: 4a46 ldr r2, [pc, #280] ; (80011c8 ) - 80010ae: 4293 cmp r3, r2 - 80010b0: d007 beq.n 80010c2 - 80010b2: 687b ldr r3, [r7, #4] - 80010b4: 4a45 ldr r2, [pc, #276] ; (80011cc ) - 80010b6: 4293 cmp r3, r2 - 80010b8: d101 bne.n 80010be - 80010ba: 2304 movs r3, #4 - 80010bc: e008 b.n 80010d0 - 80010be: 2307 movs r3, #7 - 80010c0: e006 b.n 80010d0 - 80010c2: 2303 movs r3, #3 - 80010c4: e004 b.n 80010d0 - 80010c6: 2302 movs r3, #2 - 80010c8: e002 b.n 80010d0 - 80010ca: 2301 movs r3, #1 - 80010cc: e000 b.n 80010d0 - 80010ce: 2300 movs r3, #0 - 80010d0: 69fa ldr r2, [r7, #28] - 80010d2: f002 0203 and.w r2, r2, #3 - 80010d6: 0092 lsls r2, r2, #2 - 80010d8: 4093 lsls r3, r2 - 80010da: 69ba ldr r2, [r7, #24] - 80010dc: 4313 orrs r3, r2 - 80010de: 61bb str r3, [r7, #24] + 8001bd6: 687b ldr r3, [r7, #4] + 8001bd8: 4a49 ldr r2, [pc, #292] ; (8001d00 ) + 8001bda: 4293 cmp r3, r2 + 8001bdc: d019 beq.n 8001c12 + 8001bde: 687b ldr r3, [r7, #4] + 8001be0: 4a48 ldr r2, [pc, #288] ; (8001d04 ) + 8001be2: 4293 cmp r3, r2 + 8001be4: d013 beq.n 8001c0e + 8001be6: 687b ldr r3, [r7, #4] + 8001be8: 4a47 ldr r2, [pc, #284] ; (8001d08 ) + 8001bea: 4293 cmp r3, r2 + 8001bec: d00d beq.n 8001c0a + 8001bee: 687b ldr r3, [r7, #4] + 8001bf0: 4a46 ldr r2, [pc, #280] ; (8001d0c ) + 8001bf2: 4293 cmp r3, r2 + 8001bf4: d007 beq.n 8001c06 + 8001bf6: 687b ldr r3, [r7, #4] + 8001bf8: 4a45 ldr r2, [pc, #276] ; (8001d10 ) + 8001bfa: 4293 cmp r3, r2 + 8001bfc: d101 bne.n 8001c02 + 8001bfe: 2304 movs r3, #4 + 8001c00: e008 b.n 8001c14 + 8001c02: 2307 movs r3, #7 + 8001c04: e006 b.n 8001c14 + 8001c06: 2303 movs r3, #3 + 8001c08: e004 b.n 8001c14 + 8001c0a: 2302 movs r3, #2 + 8001c0c: e002 b.n 8001c14 + 8001c0e: 2301 movs r3, #1 + 8001c10: e000 b.n 8001c14 + 8001c12: 2300 movs r3, #0 + 8001c14: 69fa ldr r2, [r7, #28] + 8001c16: f002 0203 and.w r2, r2, #3 + 8001c1a: 0092 lsls r2, r2, #2 + 8001c1c: 4093 lsls r3, r2 + 8001c1e: 69ba ldr r2, [r7, #24] + 8001c20: 4313 orrs r3, r2 + 8001c22: 61bb str r3, [r7, #24] SYSCFG->EXTICR[position >> 2U] = temp; - 80010e0: 4935 ldr r1, [pc, #212] ; (80011b8 ) - 80010e2: 69fb ldr r3, [r7, #28] - 80010e4: 089b lsrs r3, r3, #2 - 80010e6: 3302 adds r3, #2 - 80010e8: 69ba ldr r2, [r7, #24] - 80010ea: f841 2023 str.w r2, [r1, r3, lsl #2] + 8001c24: 4935 ldr r1, [pc, #212] ; (8001cfc ) + 8001c26: 69fb ldr r3, [r7, #28] + 8001c28: 089b lsrs r3, r3, #2 + 8001c2a: 3302 adds r3, #2 + 8001c2c: 69ba ldr r2, [r7, #24] + 8001c2e: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR; - 80010ee: 4b38 ldr r3, [pc, #224] ; (80011d0 ) - 80010f0: 689b ldr r3, [r3, #8] - 80010f2: 61bb str r3, [r7, #24] + 8001c32: 4b38 ldr r3, [pc, #224] ; (8001d14 ) + 8001c34: 689b ldr r3, [r3, #8] + 8001c36: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 80010f4: 693b ldr r3, [r7, #16] - 80010f6: 43db mvns r3, r3 - 80010f8: 69ba ldr r2, [r7, #24] - 80010fa: 4013 ands r3, r2 - 80010fc: 61bb str r3, [r7, #24] + 8001c38: 693b ldr r3, [r7, #16] + 8001c3a: 43db mvns r3, r3 + 8001c3c: 69ba ldr r2, [r7, #24] + 8001c3e: 4013 ands r3, r2 + 8001c40: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) - 80010fe: 683b ldr r3, [r7, #0] - 8001100: 685b ldr r3, [r3, #4] - 8001102: f403 1380 and.w r3, r3, #1048576 ; 0x100000 - 8001106: 2b00 cmp r3, #0 - 8001108: d003 beq.n 8001112 + 8001c42: 683b ldr r3, [r7, #0] + 8001c44: 685b ldr r3, [r3, #4] + 8001c46: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8001c4a: 2b00 cmp r3, #0 + 8001c4c: d003 beq.n 8001c56 { temp |= iocurrent; - 800110a: 69ba ldr r2, [r7, #24] - 800110c: 693b ldr r3, [r7, #16] - 800110e: 4313 orrs r3, r2 - 8001110: 61bb str r3, [r7, #24] + 8001c4e: 69ba ldr r2, [r7, #24] + 8001c50: 693b ldr r3, [r7, #16] + 8001c52: 4313 orrs r3, r2 + 8001c54: 61bb str r3, [r7, #24] } EXTI->RTSR = temp; - 8001112: 4a2f ldr r2, [pc, #188] ; (80011d0 ) - 8001114: 69bb ldr r3, [r7, #24] - 8001116: 6093 str r3, [r2, #8] + 8001c56: 4a2f ldr r2, [pc, #188] ; (8001d14 ) + 8001c58: 69bb ldr r3, [r7, #24] + 8001c5a: 6093 str r3, [r2, #8] temp = EXTI->FTSR; - 8001118: 4b2d ldr r3, [pc, #180] ; (80011d0 ) - 800111a: 68db ldr r3, [r3, #12] - 800111c: 61bb str r3, [r7, #24] + 8001c5c: 4b2d ldr r3, [pc, #180] ; (8001d14 ) + 8001c5e: 68db ldr r3, [r3, #12] + 8001c60: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 800111e: 693b ldr r3, [r7, #16] - 8001120: 43db mvns r3, r3 - 8001122: 69ba ldr r2, [r7, #24] - 8001124: 4013 ands r3, r2 - 8001126: 61bb str r3, [r7, #24] + 8001c62: 693b ldr r3, [r7, #16] + 8001c64: 43db mvns r3, r3 + 8001c66: 69ba ldr r2, [r7, #24] + 8001c68: 4013 ands r3, r2 + 8001c6a: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) - 8001128: 683b ldr r3, [r7, #0] - 800112a: 685b ldr r3, [r3, #4] - 800112c: f403 1300 and.w r3, r3, #2097152 ; 0x200000 - 8001130: 2b00 cmp r3, #0 - 8001132: d003 beq.n 800113c + 8001c6c: 683b ldr r3, [r7, #0] + 8001c6e: 685b ldr r3, [r3, #4] + 8001c70: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8001c74: 2b00 cmp r3, #0 + 8001c76: d003 beq.n 8001c80 { temp |= iocurrent; - 8001134: 69ba ldr r2, [r7, #24] - 8001136: 693b ldr r3, [r7, #16] - 8001138: 4313 orrs r3, r2 - 800113a: 61bb str r3, [r7, #24] + 8001c78: 69ba ldr r2, [r7, #24] + 8001c7a: 693b ldr r3, [r7, #16] + 8001c7c: 4313 orrs r3, r2 + 8001c7e: 61bb str r3, [r7, #24] } EXTI->FTSR = temp; - 800113c: 4a24 ldr r2, [pc, #144] ; (80011d0 ) - 800113e: 69bb ldr r3, [r7, #24] - 8001140: 60d3 str r3, [r2, #12] + 8001c80: 4a24 ldr r2, [pc, #144] ; (8001d14 ) + 8001c82: 69bb ldr r3, [r7, #24] + 8001c84: 60d3 str r3, [r2, #12] temp = EXTI->EMR; - 8001142: 4b23 ldr r3, [pc, #140] ; (80011d0 ) - 8001144: 685b ldr r3, [r3, #4] - 8001146: 61bb str r3, [r7, #24] + 8001c86: 4b23 ldr r3, [pc, #140] ; (8001d14 ) + 8001c88: 685b ldr r3, [r3, #4] + 8001c8a: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001148: 693b ldr r3, [r7, #16] - 800114a: 43db mvns r3, r3 - 800114c: 69ba ldr r2, [r7, #24] - 800114e: 4013 ands r3, r2 - 8001150: 61bb str r3, [r7, #24] + 8001c8c: 693b ldr r3, [r7, #16] + 8001c8e: 43db mvns r3, r3 + 8001c90: 69ba ldr r2, [r7, #24] + 8001c92: 4013 ands r3, r2 + 8001c94: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) - 8001152: 683b ldr r3, [r7, #0] - 8001154: 685b ldr r3, [r3, #4] - 8001156: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 800115a: 2b00 cmp r3, #0 - 800115c: d003 beq.n 8001166 + 8001c96: 683b ldr r3, [r7, #0] + 8001c98: 685b ldr r3, [r3, #4] + 8001c9a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001c9e: 2b00 cmp r3, #0 + 8001ca0: d003 beq.n 8001caa { temp |= iocurrent; - 800115e: 69ba ldr r2, [r7, #24] - 8001160: 693b ldr r3, [r7, #16] - 8001162: 4313 orrs r3, r2 - 8001164: 61bb str r3, [r7, #24] + 8001ca2: 69ba ldr r2, [r7, #24] + 8001ca4: 693b ldr r3, [r7, #16] + 8001ca6: 4313 orrs r3, r2 + 8001ca8: 61bb str r3, [r7, #24] } EXTI->EMR = temp; - 8001166: 4a1a ldr r2, [pc, #104] ; (80011d0 ) - 8001168: 69bb ldr r3, [r7, #24] - 800116a: 6053 str r3, [r2, #4] + 8001caa: 4a1a ldr r2, [pc, #104] ; (8001d14 ) + 8001cac: 69bb ldr r3, [r7, #24] + 8001cae: 6053 str r3, [r2, #4] /* Clear EXTI line configuration */ temp = EXTI->IMR; - 800116c: 4b18 ldr r3, [pc, #96] ; (80011d0 ) - 800116e: 681b ldr r3, [r3, #0] - 8001170: 61bb str r3, [r7, #24] + 8001cb0: 4b18 ldr r3, [pc, #96] ; (8001d14 ) + 8001cb2: 681b ldr r3, [r3, #0] + 8001cb4: 61bb str r3, [r7, #24] temp &= ~((uint32_t)iocurrent); - 8001172: 693b ldr r3, [r7, #16] - 8001174: 43db mvns r3, r3 - 8001176: 69ba ldr r2, [r7, #24] - 8001178: 4013 ands r3, r2 - 800117a: 61bb str r3, [r7, #24] + 8001cb6: 693b ldr r3, [r7, #16] + 8001cb8: 43db mvns r3, r3 + 8001cba: 69ba ldr r2, [r7, #24] + 8001cbc: 4013 ands r3, r2 + 8001cbe: 61bb str r3, [r7, #24] if((GPIO_Init->Mode & EXTI_IT) != 0x00U) - 800117c: 683b ldr r3, [r7, #0] - 800117e: 685b ldr r3, [r3, #4] - 8001180: f403 3380 and.w r3, r3, #65536 ; 0x10000 - 8001184: 2b00 cmp r3, #0 - 8001186: d003 beq.n 8001190 + 8001cc0: 683b ldr r3, [r7, #0] + 8001cc2: 685b ldr r3, [r3, #4] + 8001cc4: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8001cc8: 2b00 cmp r3, #0 + 8001cca: d003 beq.n 8001cd4 { temp |= iocurrent; - 8001188: 69ba ldr r2, [r7, #24] - 800118a: 693b ldr r3, [r7, #16] - 800118c: 4313 orrs r3, r2 - 800118e: 61bb str r3, [r7, #24] + 8001ccc: 69ba ldr r2, [r7, #24] + 8001cce: 693b ldr r3, [r7, #16] + 8001cd0: 4313 orrs r3, r2 + 8001cd2: 61bb str r3, [r7, #24] } EXTI->IMR = temp; - 8001190: 4a0f ldr r2, [pc, #60] ; (80011d0 ) - 8001192: 69bb ldr r3, [r7, #24] - 8001194: 6013 str r3, [r2, #0] + 8001cd4: 4a0f ldr r2, [pc, #60] ; (8001d14 ) + 8001cd6: 69bb ldr r3, [r7, #24] + 8001cd8: 6013 str r3, [r2, #0] for(position = 0U; position < GPIO_NUMBER; position++) - 8001196: 69fb ldr r3, [r7, #28] - 8001198: 3301 adds r3, #1 - 800119a: 61fb str r3, [r7, #28] - 800119c: 69fb ldr r3, [r7, #28] - 800119e: 2b0f cmp r3, #15 - 80011a0: f67f aea2 bls.w 8000ee8 + 8001cda: 69fb ldr r3, [r7, #28] + 8001cdc: 3301 adds r3, #1 + 8001cde: 61fb str r3, [r7, #28] + 8001ce0: 69fb ldr r3, [r7, #28] + 8001ce2: 2b0f cmp r3, #15 + 8001ce4: f67f aea2 bls.w 8001a2c } } } } - 80011a4: bf00 nop - 80011a6: bf00 nop - 80011a8: 3724 adds r7, #36 ; 0x24 - 80011aa: 46bd mov sp, r7 - 80011ac: f85d 7b04 ldr.w r7, [sp], #4 - 80011b0: 4770 bx lr - 80011b2: bf00 nop - 80011b4: 40023800 .word 0x40023800 - 80011b8: 40013800 .word 0x40013800 - 80011bc: 40020000 .word 0x40020000 - 80011c0: 40020400 .word 0x40020400 - 80011c4: 40020800 .word 0x40020800 - 80011c8: 40020c00 .word 0x40020c00 - 80011cc: 40021000 .word 0x40021000 - 80011d0: 40013c00 .word 0x40013c00 + 8001ce8: bf00 nop + 8001cea: bf00 nop + 8001cec: 3724 adds r7, #36 ; 0x24 + 8001cee: 46bd mov sp, r7 + 8001cf0: f85d 7b04 ldr.w r7, [sp], #4 + 8001cf4: 4770 bx lr + 8001cf6: bf00 nop + 8001cf8: 40023800 .word 0x40023800 + 8001cfc: 40013800 .word 0x40013800 + 8001d00: 40020000 .word 0x40020000 + 8001d04: 40020400 .word 0x40020400 + 8001d08: 40020800 .word 0x40020800 + 8001d0c: 40020c00 .word 0x40020c00 + 8001d10: 40021000 .word 0x40021000 + 8001d14: 40013c00 .word 0x40013c00 -080011d4 : +08001d18 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { - 80011d4: b480 push {r7} - 80011d6: b085 sub sp, #20 - 80011d8: af00 add r7, sp, #0 - 80011da: 6078 str r0, [r7, #4] - 80011dc: 460b mov r3, r1 - 80011de: 807b strh r3, [r7, #2] + 8001d18: b480 push {r7} + 8001d1a: b085 sub sp, #20 + 8001d1c: af00 add r7, sp, #0 + 8001d1e: 6078 str r0, [r7, #4] + 8001d20: 460b mov r3, r1 + 8001d22: 807b strh r3, [r7, #2] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) - 80011e0: 687b ldr r3, [r7, #4] - 80011e2: 691a ldr r2, [r3, #16] - 80011e4: 887b ldrh r3, [r7, #2] - 80011e6: 4013 ands r3, r2 - 80011e8: 2b00 cmp r3, #0 - 80011ea: d002 beq.n 80011f2 + 8001d24: 687b ldr r3, [r7, #4] + 8001d26: 691a ldr r2, [r3, #16] + 8001d28: 887b ldrh r3, [r7, #2] + 8001d2a: 4013 ands r3, r2 + 8001d2c: 2b00 cmp r3, #0 + 8001d2e: d002 beq.n 8001d36 { bitstatus = GPIO_PIN_SET; - 80011ec: 2301 movs r3, #1 - 80011ee: 73fb strb r3, [r7, #15] - 80011f0: e001 b.n 80011f6 + 8001d30: 2301 movs r3, #1 + 8001d32: 73fb strb r3, [r7, #15] + 8001d34: e001 b.n 8001d3a } else { bitstatus = GPIO_PIN_RESET; - 80011f2: 2300 movs r3, #0 - 80011f4: 73fb strb r3, [r7, #15] + 8001d36: 2300 movs r3, #0 + 8001d38: 73fb strb r3, [r7, #15] } return bitstatus; - 80011f6: 7bfb ldrb r3, [r7, #15] + 8001d3a: 7bfb ldrb r3, [r7, #15] } - 80011f8: 4618 mov r0, r3 - 80011fa: 3714 adds r7, #20 - 80011fc: 46bd mov sp, r7 - 80011fe: f85d 7b04 ldr.w r7, [sp], #4 - 8001202: 4770 bx lr + 8001d3c: 4618 mov r0, r3 + 8001d3e: 3714 adds r7, #20 + 8001d40: 46bd mov sp, r7 + 8001d42: f85d 7b04 ldr.w r7, [sp], #4 + 8001d46: 4770 bx lr -08001204 : +08001d48 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { - 8001204: b480 push {r7} - 8001206: b083 sub sp, #12 - 8001208: af00 add r7, sp, #0 - 800120a: 6078 str r0, [r7, #4] - 800120c: 460b mov r3, r1 - 800120e: 807b strh r3, [r7, #2] - 8001210: 4613 mov r3, r2 - 8001212: 707b strb r3, [r7, #1] + 8001d48: b480 push {r7} + 8001d4a: b083 sub sp, #12 + 8001d4c: af00 add r7, sp, #0 + 8001d4e: 6078 str r0, [r7, #4] + 8001d50: 460b mov r3, r1 + 8001d52: 807b strh r3, [r7, #2] + 8001d54: 4613 mov r3, r2 + 8001d56: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) - 8001214: 787b ldrb r3, [r7, #1] - 8001216: 2b00 cmp r3, #0 - 8001218: d003 beq.n 8001222 + 8001d58: 787b ldrb r3, [r7, #1] + 8001d5a: 2b00 cmp r3, #0 + 8001d5c: d003 beq.n 8001d66 { GPIOx->BSRR = GPIO_Pin; - 800121a: 887a ldrh r2, [r7, #2] - 800121c: 687b ldr r3, [r7, #4] - 800121e: 619a str r2, [r3, #24] + 8001d5e: 887a ldrh r2, [r7, #2] + 8001d60: 687b ldr r3, [r7, #4] + 8001d62: 619a str r2, [r3, #24] } else { GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; } } - 8001220: e003 b.n 800122a + 8001d64: e003 b.n 8001d6e GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; - 8001222: 887b ldrh r3, [r7, #2] - 8001224: 041a lsls r2, r3, #16 - 8001226: 687b ldr r3, [r7, #4] - 8001228: 619a str r2, [r3, #24] + 8001d66: 887b ldrh r3, [r7, #2] + 8001d68: 041a lsls r2, r3, #16 + 8001d6a: 687b ldr r3, [r7, #4] + 8001d6c: 619a str r2, [r3, #24] } - 800122a: bf00 nop - 800122c: 370c adds r7, #12 - 800122e: 46bd mov sp, r7 - 8001230: f85d 7b04 ldr.w r7, [sp], #4 - 8001234: 4770 bx lr + 8001d6e: bf00 nop + 8001d70: 370c adds r7, #12 + 8001d72: 46bd mov sp, r7 + 8001d74: f85d 7b04 ldr.w r7, [sp], #4 + 8001d78: 4770 bx lr ... -08001238 : +08001d7c : * supported by this API. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { - 8001238: b580 push {r7, lr} - 800123a: b086 sub sp, #24 - 800123c: af00 add r7, sp, #0 - 800123e: 6078 str r0, [r7, #4] + 8001d7c: b580 push {r7, lr} + 8001d7e: b086 sub sp, #24 + 8001d80: af00 add r7, sp, #0 + 8001d82: 6078 str r0, [r7, #4] uint32_t tickstart, pll_config; /* Check Null pointer */ if(RCC_OscInitStruct == NULL) - 8001240: 687b ldr r3, [r7, #4] - 8001242: 2b00 cmp r3, #0 - 8001244: d101 bne.n 800124a + 8001d84: 687b ldr r3, [r7, #4] + 8001d86: 2b00 cmp r3, #0 + 8001d88: d101 bne.n 8001d8e { return HAL_ERROR; - 8001246: 2301 movs r3, #1 - 8001248: e267 b.n 800171a + 8001d8a: 2301 movs r3, #1 + 8001d8c: e267 b.n 800225e } /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - 800124a: 687b ldr r3, [r7, #4] - 800124c: 681b ldr r3, [r3, #0] - 800124e: f003 0301 and.w r3, r3, #1 - 8001252: 2b00 cmp r3, #0 - 8001254: d075 beq.n 8001342 + 8001d8e: 687b ldr r3, [r7, #4] + 8001d90: 681b ldr r3, [r3, #0] + 8001d92: f003 0301 and.w r3, r3, #1 + 8001d96: 2b00 cmp r3, #0 + 8001d98: d075 beq.n 8001e86 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ - 8001256: 4b88 ldr r3, [pc, #544] ; (8001478 ) - 8001258: 689b ldr r3, [r3, #8] - 800125a: f003 030c and.w r3, r3, #12 - 800125e: 2b04 cmp r3, #4 - 8001260: d00c beq.n 800127c + 8001d9a: 4b88 ldr r3, [pc, #544] ; (8001fbc ) + 8001d9c: 689b ldr r3, [r3, #8] + 8001d9e: f003 030c and.w r3, r3, #12 + 8001da2: 2b04 cmp r3, #4 + 8001da4: d00c beq.n 8001dc0 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - 8001262: 4b85 ldr r3, [pc, #532] ; (8001478 ) - 8001264: 689b ldr r3, [r3, #8] - 8001266: f003 030c and.w r3, r3, #12 + 8001da6: 4b85 ldr r3, [pc, #532] ; (8001fbc ) + 8001da8: 689b ldr r3, [r3, #8] + 8001daa: f003 030c and.w r3, r3, #12 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ - 800126a: 2b08 cmp r3, #8 - 800126c: d112 bne.n 8001294 + 8001dae: 2b08 cmp r3, #8 + 8001db0: d112 bne.n 8001dd8 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) - 800126e: 4b82 ldr r3, [pc, #520] ; (8001478 ) - 8001270: 685b ldr r3, [r3, #4] - 8001272: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 8001276: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 - 800127a: d10b bne.n 8001294 + 8001db2: 4b82 ldr r3, [pc, #520] ; (8001fbc ) + 8001db4: 685b ldr r3, [r3, #4] + 8001db6: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8001dba: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8001dbe: d10b bne.n 8001dd8 { if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 800127c: 4b7e ldr r3, [pc, #504] ; (8001478 ) - 800127e: 681b ldr r3, [r3, #0] - 8001280: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8001284: 2b00 cmp r3, #0 - 8001286: d05b beq.n 8001340 - 8001288: 687b ldr r3, [r7, #4] - 800128a: 685b ldr r3, [r3, #4] - 800128c: 2b00 cmp r3, #0 - 800128e: d157 bne.n 8001340 + 8001dc0: 4b7e ldr r3, [pc, #504] ; (8001fbc ) + 8001dc2: 681b ldr r3, [r3, #0] + 8001dc4: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001dc8: 2b00 cmp r3, #0 + 8001dca: d05b beq.n 8001e84 + 8001dcc: 687b ldr r3, [r7, #4] + 8001dce: 685b ldr r3, [r3, #4] + 8001dd0: 2b00 cmp r3, #0 + 8001dd2: d157 bne.n 8001e84 { return HAL_ERROR; - 8001290: 2301 movs r3, #1 - 8001292: e242 b.n 800171a + 8001dd4: 2301 movs r3, #1 + 8001dd6: e242 b.n 800225e } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); - 8001294: 687b ldr r3, [r7, #4] - 8001296: 685b ldr r3, [r3, #4] - 8001298: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 - 800129c: d106 bne.n 80012ac - 800129e: 4b76 ldr r3, [pc, #472] ; (8001478 ) - 80012a0: 681b ldr r3, [r3, #0] - 80012a2: 4a75 ldr r2, [pc, #468] ; (8001478 ) - 80012a4: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 80012a8: 6013 str r3, [r2, #0] - 80012aa: e01d b.n 80012e8 - 80012ac: 687b ldr r3, [r7, #4] - 80012ae: 685b ldr r3, [r3, #4] - 80012b0: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 - 80012b4: d10c bne.n 80012d0 - 80012b6: 4b70 ldr r3, [pc, #448] ; (8001478 ) - 80012b8: 681b ldr r3, [r3, #0] - 80012ba: 4a6f ldr r2, [pc, #444] ; (8001478 ) - 80012bc: f443 2380 orr.w r3, r3, #262144 ; 0x40000 - 80012c0: 6013 str r3, [r2, #0] - 80012c2: 4b6d ldr r3, [pc, #436] ; (8001478 ) - 80012c4: 681b ldr r3, [r3, #0] - 80012c6: 4a6c ldr r2, [pc, #432] ; (8001478 ) - 80012c8: f443 3380 orr.w r3, r3, #65536 ; 0x10000 - 80012cc: 6013 str r3, [r2, #0] - 80012ce: e00b b.n 80012e8 - 80012d0: 4b69 ldr r3, [pc, #420] ; (8001478 ) - 80012d2: 681b ldr r3, [r3, #0] - 80012d4: 4a68 ldr r2, [pc, #416] ; (8001478 ) - 80012d6: f423 3380 bic.w r3, r3, #65536 ; 0x10000 - 80012da: 6013 str r3, [r2, #0] - 80012dc: 4b66 ldr r3, [pc, #408] ; (8001478 ) - 80012de: 681b ldr r3, [r3, #0] - 80012e0: 4a65 ldr r2, [pc, #404] ; (8001478 ) - 80012e2: f423 2380 bic.w r3, r3, #262144 ; 0x40000 - 80012e6: 6013 str r3, [r2, #0] + 8001dd8: 687b ldr r3, [r7, #4] + 8001dda: 685b ldr r3, [r3, #4] + 8001ddc: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8001de0: d106 bne.n 8001df0 + 8001de2: 4b76 ldr r3, [pc, #472] ; (8001fbc ) + 8001de4: 681b ldr r3, [r3, #0] + 8001de6: 4a75 ldr r2, [pc, #468] ; (8001fbc ) + 8001de8: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8001dec: 6013 str r3, [r2, #0] + 8001dee: e01d b.n 8001e2c + 8001df0: 687b ldr r3, [r7, #4] + 8001df2: 685b ldr r3, [r3, #4] + 8001df4: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 + 8001df8: d10c bne.n 8001e14 + 8001dfa: 4b70 ldr r3, [pc, #448] ; (8001fbc ) + 8001dfc: 681b ldr r3, [r3, #0] + 8001dfe: 4a6f ldr r2, [pc, #444] ; (8001fbc ) + 8001e00: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8001e04: 6013 str r3, [r2, #0] + 8001e06: 4b6d ldr r3, [pc, #436] ; (8001fbc ) + 8001e08: 681b ldr r3, [r3, #0] + 8001e0a: 4a6c ldr r2, [pc, #432] ; (8001fbc ) + 8001e0c: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8001e10: 6013 str r3, [r2, #0] + 8001e12: e00b b.n 8001e2c + 8001e14: 4b69 ldr r3, [pc, #420] ; (8001fbc ) + 8001e16: 681b ldr r3, [r3, #0] + 8001e18: 4a68 ldr r2, [pc, #416] ; (8001fbc ) + 8001e1a: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8001e1e: 6013 str r3, [r2, #0] + 8001e20: 4b66 ldr r3, [pc, #408] ; (8001fbc ) + 8001e22: 681b ldr r3, [r3, #0] + 8001e24: 4a65 ldr r2, [pc, #404] ; (8001fbc ) + 8001e26: f423 2380 bic.w r3, r3, #262144 ; 0x40000 + 8001e2a: 6013 str r3, [r2, #0] /* Check the HSE State */ if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) - 80012e8: 687b ldr r3, [r7, #4] - 80012ea: 685b ldr r3, [r3, #4] - 80012ec: 2b00 cmp r3, #0 - 80012ee: d013 beq.n 8001318 + 8001e2c: 687b ldr r3, [r7, #4] + 8001e2e: 685b ldr r3, [r3, #4] + 8001e30: 2b00 cmp r3, #0 + 8001e32: d013 beq.n 8001e5c { /* Get Start Tick */ tickstart = HAL_GetTick(); - 80012f0: f7ff fcfe bl 8000cf0 - 80012f4: 6138 str r0, [r7, #16] + 8001e34: f7ff f892 bl 8000f5c + 8001e38: 6138 str r0, [r7, #16] /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 80012f6: e008 b.n 800130a + 8001e3a: e008 b.n 8001e4e { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 80012f8: f7ff fcfa bl 8000cf0 - 80012fc: 4602 mov r2, r0 - 80012fe: 693b ldr r3, [r7, #16] - 8001300: 1ad3 subs r3, r2, r3 - 8001302: 2b64 cmp r3, #100 ; 0x64 - 8001304: d901 bls.n 800130a + 8001e3c: f7ff f88e bl 8000f5c + 8001e40: 4602 mov r2, r0 + 8001e42: 693b ldr r3, [r7, #16] + 8001e44: 1ad3 subs r3, r2, r3 + 8001e46: 2b64 cmp r3, #100 ; 0x64 + 8001e48: d901 bls.n 8001e4e { return HAL_TIMEOUT; - 8001306: 2303 movs r3, #3 - 8001308: e207 b.n 800171a + 8001e4a: 2303 movs r3, #3 + 8001e4c: e207 b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 800130a: 4b5b ldr r3, [pc, #364] ; (8001478 ) - 800130c: 681b ldr r3, [r3, #0] - 800130e: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 8001312: 2b00 cmp r3, #0 - 8001314: d0f0 beq.n 80012f8 - 8001316: e014 b.n 8001342 + 8001e4e: 4b5b ldr r3, [pc, #364] ; (8001fbc ) + 8001e50: 681b ldr r3, [r3, #0] + 8001e52: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001e56: 2b00 cmp r3, #0 + 8001e58: d0f0 beq.n 8001e3c + 8001e5a: e014 b.n 8001e86 } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001318: f7ff fcea bl 8000cf0 - 800131c: 6138 str r0, [r7, #16] + 8001e5c: f7ff f87e bl 8000f5c + 8001e60: 6138 str r0, [r7, #16] /* Wait till HSE is bypassed or disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 800131e: e008 b.n 8001332 + 8001e62: e008 b.n 8001e76 { if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) - 8001320: f7ff fce6 bl 8000cf0 - 8001324: 4602 mov r2, r0 - 8001326: 693b ldr r3, [r7, #16] - 8001328: 1ad3 subs r3, r2, r3 - 800132a: 2b64 cmp r3, #100 ; 0x64 - 800132c: d901 bls.n 8001332 + 8001e64: f7ff f87a bl 8000f5c + 8001e68: 4602 mov r2, r0 + 8001e6a: 693b ldr r3, [r7, #16] + 8001e6c: 1ad3 subs r3, r2, r3 + 8001e6e: 2b64 cmp r3, #100 ; 0x64 + 8001e70: d901 bls.n 8001e76 { return HAL_TIMEOUT; - 800132e: 2303 movs r3, #3 - 8001330: e1f3 b.n 800171a + 8001e72: 2303 movs r3, #3 + 8001e74: e1f3 b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) - 8001332: 4b51 ldr r3, [pc, #324] ; (8001478 ) - 8001334: 681b ldr r3, [r3, #0] - 8001336: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 800133a: 2b00 cmp r3, #0 - 800133c: d1f0 bne.n 8001320 - 800133e: e000 b.n 8001342 + 8001e76: 4b51 ldr r3, [pc, #324] ; (8001fbc ) + 8001e78: 681b ldr r3, [r3, #0] + 8001e7a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8001e7e: 2b00 cmp r3, #0 + 8001e80: d1f0 bne.n 8001e64 + 8001e82: e000 b.n 8001e86 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) - 8001340: bf00 nop + 8001e84: bf00 nop } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - 8001342: 687b ldr r3, [r7, #4] - 8001344: 681b ldr r3, [r3, #0] - 8001346: f003 0302 and.w r3, r3, #2 - 800134a: 2b00 cmp r3, #0 - 800134c: d063 beq.n 8001416 + 8001e86: 687b ldr r3, [r7, #4] + 8001e88: 681b ldr r3, [r3, #0] + 8001e8a: f003 0302 and.w r3, r3, #2 + 8001e8e: 2b00 cmp r3, #0 + 8001e90: d063 beq.n 8001f5a /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ - 800134e: 4b4a ldr r3, [pc, #296] ; (8001478 ) - 8001350: 689b ldr r3, [r3, #8] - 8001352: f003 030c and.w r3, r3, #12 - 8001356: 2b00 cmp r3, #0 - 8001358: d00b beq.n 8001372 + 8001e92: 4b4a ldr r3, [pc, #296] ; (8001fbc ) + 8001e94: 689b ldr r3, [r3, #8] + 8001e96: f003 030c and.w r3, r3, #12 + 8001e9a: 2b00 cmp r3, #0 + 8001e9c: d00b beq.n 8001eb6 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - 800135a: 4b47 ldr r3, [pc, #284] ; (8001478 ) - 800135c: 689b ldr r3, [r3, #8] - 800135e: f003 030c and.w r3, r3, #12 + 8001e9e: 4b47 ldr r3, [pc, #284] ; (8001fbc ) + 8001ea0: 689b ldr r3, [r3, #8] + 8001ea2: f003 030c and.w r3, r3, #12 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ - 8001362: 2b08 cmp r3, #8 - 8001364: d11c bne.n 80013a0 + 8001ea6: 2b08 cmp r3, #8 + 8001ea8: d11c bne.n 8001ee4 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) - 8001366: 4b44 ldr r3, [pc, #272] ; (8001478 ) - 8001368: 685b ldr r3, [r3, #4] - 800136a: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 800136e: 2b00 cmp r3, #0 - 8001370: d116 bne.n 80013a0 + 8001eaa: 4b44 ldr r3, [pc, #272] ; (8001fbc ) + 8001eac: 685b ldr r3, [r3, #4] + 8001eae: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8001eb2: 2b00 cmp r3, #0 + 8001eb4: d116 bne.n 8001ee4 { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 8001372: 4b41 ldr r3, [pc, #260] ; (8001478 ) - 8001374: 681b ldr r3, [r3, #0] - 8001376: f003 0302 and.w r3, r3, #2 - 800137a: 2b00 cmp r3, #0 - 800137c: d005 beq.n 800138a - 800137e: 687b ldr r3, [r7, #4] - 8001380: 68db ldr r3, [r3, #12] - 8001382: 2b01 cmp r3, #1 - 8001384: d001 beq.n 800138a + 8001eb6: 4b41 ldr r3, [pc, #260] ; (8001fbc ) + 8001eb8: 681b ldr r3, [r3, #0] + 8001eba: f003 0302 and.w r3, r3, #2 + 8001ebe: 2b00 cmp r3, #0 + 8001ec0: d005 beq.n 8001ece + 8001ec2: 687b ldr r3, [r7, #4] + 8001ec4: 68db ldr r3, [r3, #12] + 8001ec6: 2b01 cmp r3, #1 + 8001ec8: d001 beq.n 8001ece { return HAL_ERROR; - 8001386: 2301 movs r3, #1 - 8001388: e1c7 b.n 800171a + 8001eca: 2301 movs r3, #1 + 8001ecc: e1c7 b.n 800225e } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 800138a: 4b3b ldr r3, [pc, #236] ; (8001478 ) - 800138c: 681b ldr r3, [r3, #0] - 800138e: f023 02f8 bic.w r2, r3, #248 ; 0xf8 - 8001392: 687b ldr r3, [r7, #4] - 8001394: 691b ldr r3, [r3, #16] - 8001396: 00db lsls r3, r3, #3 - 8001398: 4937 ldr r1, [pc, #220] ; (8001478 ) - 800139a: 4313 orrs r3, r2 - 800139c: 600b str r3, [r1, #0] + 8001ece: 4b3b ldr r3, [pc, #236] ; (8001fbc ) + 8001ed0: 681b ldr r3, [r3, #0] + 8001ed2: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8001ed6: 687b ldr r3, [r7, #4] + 8001ed8: 691b ldr r3, [r3, #16] + 8001eda: 00db lsls r3, r3, #3 + 8001edc: 4937 ldr r1, [pc, #220] ; (8001fbc ) + 8001ede: 4313 orrs r3, r2 + 8001ee0: 600b str r3, [r1, #0] if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) - 800139e: e03a b.n 8001416 + 8001ee2: e03a b.n 8001f5a } } else { /* Check the HSI State */ if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) - 80013a0: 687b ldr r3, [r7, #4] - 80013a2: 68db ldr r3, [r3, #12] - 80013a4: 2b00 cmp r3, #0 - 80013a6: d020 beq.n 80013ea + 8001ee4: 687b ldr r3, [r7, #4] + 8001ee6: 68db ldr r3, [r3, #12] + 8001ee8: 2b00 cmp r3, #0 + 8001eea: d020 beq.n 8001f2e { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); - 80013a8: 4b34 ldr r3, [pc, #208] ; (800147c ) - 80013aa: 2201 movs r2, #1 - 80013ac: 601a str r2, [r3, #0] + 8001eec: 4b34 ldr r3, [pc, #208] ; (8001fc0 ) + 8001eee: 2201 movs r2, #1 + 8001ef0: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80013ae: f7ff fc9f bl 8000cf0 - 80013b2: 6138 str r0, [r7, #16] + 8001ef2: f7ff f833 bl 8000f5c + 8001ef6: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 80013b4: e008 b.n 80013c8 + 8001ef8: e008 b.n 8001f0c { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 80013b6: f7ff fc9b bl 8000cf0 - 80013ba: 4602 mov r2, r0 - 80013bc: 693b ldr r3, [r7, #16] - 80013be: 1ad3 subs r3, r2, r3 - 80013c0: 2b02 cmp r3, #2 - 80013c2: d901 bls.n 80013c8 + 8001efa: f7ff f82f bl 8000f5c + 8001efe: 4602 mov r2, r0 + 8001f00: 693b ldr r3, [r7, #16] + 8001f02: 1ad3 subs r3, r2, r3 + 8001f04: 2b02 cmp r3, #2 + 8001f06: d901 bls.n 8001f0c { return HAL_TIMEOUT; - 80013c4: 2303 movs r3, #3 - 80013c6: e1a8 b.n 800171a + 8001f08: 2303 movs r3, #3 + 8001f0a: e1a8 b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 80013c8: 4b2b ldr r3, [pc, #172] ; (8001478 ) - 80013ca: 681b ldr r3, [r3, #0] - 80013cc: f003 0302 and.w r3, r3, #2 - 80013d0: 2b00 cmp r3, #0 - 80013d2: d0f0 beq.n 80013b6 + 8001f0c: 4b2b ldr r3, [pc, #172] ; (8001fbc ) + 8001f0e: 681b ldr r3, [r3, #0] + 8001f10: f003 0302 and.w r3, r3, #2 + 8001f14: 2b00 cmp r3, #0 + 8001f16: d0f0 beq.n 8001efa } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); - 80013d4: 4b28 ldr r3, [pc, #160] ; (8001478 ) - 80013d6: 681b ldr r3, [r3, #0] - 80013d8: f023 02f8 bic.w r2, r3, #248 ; 0xf8 - 80013dc: 687b ldr r3, [r7, #4] - 80013de: 691b ldr r3, [r3, #16] - 80013e0: 00db lsls r3, r3, #3 - 80013e2: 4925 ldr r1, [pc, #148] ; (8001478 ) - 80013e4: 4313 orrs r3, r2 - 80013e6: 600b str r3, [r1, #0] - 80013e8: e015 b.n 8001416 + 8001f18: 4b28 ldr r3, [pc, #160] ; (8001fbc ) + 8001f1a: 681b ldr r3, [r3, #0] + 8001f1c: f023 02f8 bic.w r2, r3, #248 ; 0xf8 + 8001f20: 687b ldr r3, [r7, #4] + 8001f22: 691b ldr r3, [r3, #16] + 8001f24: 00db lsls r3, r3, #3 + 8001f26: 4925 ldr r1, [pc, #148] ; (8001fbc ) + 8001f28: 4313 orrs r3, r2 + 8001f2a: 600b str r3, [r1, #0] + 8001f2c: e015 b.n 8001f5a } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); - 80013ea: 4b24 ldr r3, [pc, #144] ; (800147c ) - 80013ec: 2200 movs r2, #0 - 80013ee: 601a str r2, [r3, #0] + 8001f2e: 4b24 ldr r3, [pc, #144] ; (8001fc0 ) + 8001f30: 2200 movs r2, #0 + 8001f32: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 80013f0: f7ff fc7e bl 8000cf0 - 80013f4: 6138 str r0, [r7, #16] + 8001f34: f7ff f812 bl 8000f5c + 8001f38: 6138 str r0, [r7, #16] /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 80013f6: e008 b.n 800140a + 8001f3a: e008 b.n 8001f4e { if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) - 80013f8: f7ff fc7a bl 8000cf0 - 80013fc: 4602 mov r2, r0 - 80013fe: 693b ldr r3, [r7, #16] - 8001400: 1ad3 subs r3, r2, r3 - 8001402: 2b02 cmp r3, #2 - 8001404: d901 bls.n 800140a + 8001f3c: f7ff f80e bl 8000f5c + 8001f40: 4602 mov r2, r0 + 8001f42: 693b ldr r3, [r7, #16] + 8001f44: 1ad3 subs r3, r2, r3 + 8001f46: 2b02 cmp r3, #2 + 8001f48: d901 bls.n 8001f4e { return HAL_TIMEOUT; - 8001406: 2303 movs r3, #3 - 8001408: e187 b.n 800171a + 8001f4a: 2303 movs r3, #3 + 8001f4c: e187 b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) - 800140a: 4b1b ldr r3, [pc, #108] ; (8001478 ) - 800140c: 681b ldr r3, [r3, #0] - 800140e: f003 0302 and.w r3, r3, #2 - 8001412: 2b00 cmp r3, #0 - 8001414: d1f0 bne.n 80013f8 + 8001f4e: 4b1b ldr r3, [pc, #108] ; (8001fbc ) + 8001f50: 681b ldr r3, [r3, #0] + 8001f52: f003 0302 and.w r3, r3, #2 + 8001f56: 2b00 cmp r3, #0 + 8001f58: d1f0 bne.n 8001f3c } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - 8001416: 687b ldr r3, [r7, #4] - 8001418: 681b ldr r3, [r3, #0] - 800141a: f003 0308 and.w r3, r3, #8 - 800141e: 2b00 cmp r3, #0 - 8001420: d036 beq.n 8001490 + 8001f5a: 687b ldr r3, [r7, #4] + 8001f5c: 681b ldr r3, [r3, #0] + 8001f5e: f003 0308 and.w r3, r3, #8 + 8001f62: 2b00 cmp r3, #0 + 8001f64: d036 beq.n 8001fd4 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) - 8001422: 687b ldr r3, [r7, #4] - 8001424: 695b ldr r3, [r3, #20] - 8001426: 2b00 cmp r3, #0 - 8001428: d016 beq.n 8001458 + 8001f66: 687b ldr r3, [r7, #4] + 8001f68: 695b ldr r3, [r3, #20] + 8001f6a: 2b00 cmp r3, #0 + 8001f6c: d016 beq.n 8001f9c { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); - 800142a: 4b15 ldr r3, [pc, #84] ; (8001480 ) - 800142c: 2201 movs r2, #1 - 800142e: 601a str r2, [r3, #0] + 8001f6e: 4b15 ldr r3, [pc, #84] ; (8001fc4 ) + 8001f70: 2201 movs r2, #1 + 8001f72: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001430: f7ff fc5e bl 8000cf0 - 8001434: 6138 str r0, [r7, #16] + 8001f74: f7fe fff2 bl 8000f5c + 8001f78: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 8001436: e008 b.n 800144a + 8001f7a: e008 b.n 8001f8e { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8001438: f7ff fc5a bl 8000cf0 - 800143c: 4602 mov r2, r0 - 800143e: 693b ldr r3, [r7, #16] - 8001440: 1ad3 subs r3, r2, r3 - 8001442: 2b02 cmp r3, #2 - 8001444: d901 bls.n 800144a + 8001f7c: f7fe ffee bl 8000f5c + 8001f80: 4602 mov r2, r0 + 8001f82: 693b ldr r3, [r7, #16] + 8001f84: 1ad3 subs r3, r2, r3 + 8001f86: 2b02 cmp r3, #2 + 8001f88: d901 bls.n 8001f8e { return HAL_TIMEOUT; - 8001446: 2303 movs r3, #3 - 8001448: e167 b.n 800171a + 8001f8a: 2303 movs r3, #3 + 8001f8c: e167 b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) - 800144a: 4b0b ldr r3, [pc, #44] ; (8001478 ) - 800144c: 6f5b ldr r3, [r3, #116] ; 0x74 - 800144e: f003 0302 and.w r3, r3, #2 - 8001452: 2b00 cmp r3, #0 - 8001454: d0f0 beq.n 8001438 - 8001456: e01b b.n 8001490 + 8001f8e: 4b0b ldr r3, [pc, #44] ; (8001fbc ) + 8001f90: 6f5b ldr r3, [r3, #116] ; 0x74 + 8001f92: f003 0302 and.w r3, r3, #2 + 8001f96: 2b00 cmp r3, #0 + 8001f98: d0f0 beq.n 8001f7c + 8001f9a: e01b b.n 8001fd4 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); - 8001458: 4b09 ldr r3, [pc, #36] ; (8001480 ) - 800145a: 2200 movs r2, #0 - 800145c: 601a str r2, [r3, #0] + 8001f9c: 4b09 ldr r3, [pc, #36] ; (8001fc4 ) + 8001f9e: 2200 movs r2, #0 + 8001fa0: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 800145e: f7ff fc47 bl 8000cf0 - 8001462: 6138 str r0, [r7, #16] + 8001fa2: f7fe ffdb bl 8000f5c + 8001fa6: 6138 str r0, [r7, #16] /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8001464: e00e b.n 8001484 + 8001fa8: e00e b.n 8001fc8 { if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) - 8001466: f7ff fc43 bl 8000cf0 - 800146a: 4602 mov r2, r0 - 800146c: 693b ldr r3, [r7, #16] - 800146e: 1ad3 subs r3, r2, r3 - 8001470: 2b02 cmp r3, #2 - 8001472: d907 bls.n 8001484 + 8001faa: f7fe ffd7 bl 8000f5c + 8001fae: 4602 mov r2, r0 + 8001fb0: 693b ldr r3, [r7, #16] + 8001fb2: 1ad3 subs r3, r2, r3 + 8001fb4: 2b02 cmp r3, #2 + 8001fb6: d907 bls.n 8001fc8 { return HAL_TIMEOUT; - 8001474: 2303 movs r3, #3 - 8001476: e150 b.n 800171a - 8001478: 40023800 .word 0x40023800 - 800147c: 42470000 .word 0x42470000 - 8001480: 42470e80 .word 0x42470e80 + 8001fb8: 2303 movs r3, #3 + 8001fba: e150 b.n 800225e + 8001fbc: 40023800 .word 0x40023800 + 8001fc0: 42470000 .word 0x42470000 + 8001fc4: 42470e80 .word 0x42470e80 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) - 8001484: 4b88 ldr r3, [pc, #544] ; (80016a8 ) - 8001486: 6f5b ldr r3, [r3, #116] ; 0x74 - 8001488: f003 0302 and.w r3, r3, #2 - 800148c: 2b00 cmp r3, #0 - 800148e: d1ea bne.n 8001466 + 8001fc8: 4b88 ldr r3, [pc, #544] ; (80021ec ) + 8001fca: 6f5b ldr r3, [r3, #116] ; 0x74 + 8001fcc: f003 0302 and.w r3, r3, #2 + 8001fd0: 2b00 cmp r3, #0 + 8001fd2: d1ea bne.n 8001faa } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - 8001490: 687b ldr r3, [r7, #4] - 8001492: 681b ldr r3, [r3, #0] - 8001494: f003 0304 and.w r3, r3, #4 - 8001498: 2b00 cmp r3, #0 - 800149a: f000 8097 beq.w 80015cc + 8001fd4: 687b ldr r3, [r7, #4] + 8001fd6: 681b ldr r3, [r3, #0] + 8001fd8: f003 0304 and.w r3, r3, #4 + 8001fdc: 2b00 cmp r3, #0 + 8001fde: f000 8097 beq.w 8002110 { FlagStatus pwrclkchanged = RESET; - 800149e: 2300 movs r3, #0 - 80014a0: 75fb strb r3, [r7, #23] + 8001fe2: 2300 movs r3, #0 + 8001fe4: 75fb strb r3, [r7, #23] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - 80014a2: 4b81 ldr r3, [pc, #516] ; (80016a8 ) - 80014a4: 6c1b ldr r3, [r3, #64] ; 0x40 - 80014a6: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 80014aa: 2b00 cmp r3, #0 - 80014ac: d10f bne.n 80014ce + 8001fe6: 4b81 ldr r3, [pc, #516] ; (80021ec ) + 8001fe8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001fea: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001fee: 2b00 cmp r3, #0 + 8001ff0: d10f bne.n 8002012 { __HAL_RCC_PWR_CLK_ENABLE(); - 80014ae: 2300 movs r3, #0 - 80014b0: 60bb str r3, [r7, #8] - 80014b2: 4b7d ldr r3, [pc, #500] ; (80016a8 ) - 80014b4: 6c1b ldr r3, [r3, #64] ; 0x40 - 80014b6: 4a7c ldr r2, [pc, #496] ; (80016a8 ) - 80014b8: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 - 80014bc: 6413 str r3, [r2, #64] ; 0x40 - 80014be: 4b7a ldr r3, [pc, #488] ; (80016a8 ) - 80014c0: 6c1b ldr r3, [r3, #64] ; 0x40 - 80014c2: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 - 80014c6: 60bb str r3, [r7, #8] - 80014c8: 68bb ldr r3, [r7, #8] + 8001ff2: 2300 movs r3, #0 + 8001ff4: 60bb str r3, [r7, #8] + 8001ff6: 4b7d ldr r3, [pc, #500] ; (80021ec ) + 8001ff8: 6c1b ldr r3, [r3, #64] ; 0x40 + 8001ffa: 4a7c ldr r2, [pc, #496] ; (80021ec ) + 8001ffc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8002000: 6413 str r3, [r2, #64] ; 0x40 + 8002002: 4b7a ldr r3, [pc, #488] ; (80021ec ) + 8002004: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002006: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800200a: 60bb str r3, [r7, #8] + 800200c: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; - 80014ca: 2301 movs r3, #1 - 80014cc: 75fb strb r3, [r7, #23] + 800200e: 2301 movs r3, #1 + 8002010: 75fb strb r3, [r7, #23] } if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80014ce: 4b77 ldr r3, [pc, #476] ; (80016ac ) - 80014d0: 681b ldr r3, [r3, #0] - 80014d2: f403 7380 and.w r3, r3, #256 ; 0x100 - 80014d6: 2b00 cmp r3, #0 - 80014d8: d118 bne.n 800150c + 8002012: 4b77 ldr r3, [pc, #476] ; (80021f0 ) + 8002014: 681b ldr r3, [r3, #0] + 8002016: f403 7380 and.w r3, r3, #256 ; 0x100 + 800201a: 2b00 cmp r3, #0 + 800201c: d118 bne.n 8002050 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR, PWR_CR_DBP); - 80014da: 4b74 ldr r3, [pc, #464] ; (80016ac ) - 80014dc: 681b ldr r3, [r3, #0] - 80014de: 4a73 ldr r2, [pc, #460] ; (80016ac ) - 80014e0: f443 7380 orr.w r3, r3, #256 ; 0x100 - 80014e4: 6013 str r3, [r2, #0] + 800201e: 4b74 ldr r3, [pc, #464] ; (80021f0 ) + 8002020: 681b ldr r3, [r3, #0] + 8002022: 4a73 ldr r2, [pc, #460] ; (80021f0 ) + 8002024: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8002028: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); - 80014e6: f7ff fc03 bl 8000cf0 - 80014ea: 6138 str r0, [r7, #16] + 800202a: f7fe ff97 bl 8000f5c + 800202e: 6138 str r0, [r7, #16] while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 80014ec: e008 b.n 8001500 + 8002030: e008 b.n 8002044 { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - 80014ee: f7ff fbff bl 8000cf0 - 80014f2: 4602 mov r2, r0 - 80014f4: 693b ldr r3, [r7, #16] - 80014f6: 1ad3 subs r3, r2, r3 - 80014f8: 2b02 cmp r3, #2 - 80014fa: d901 bls.n 8001500 + 8002032: f7fe ff93 bl 8000f5c + 8002036: 4602 mov r2, r0 + 8002038: 693b ldr r3, [r7, #16] + 800203a: 1ad3 subs r3, r2, r3 + 800203c: 2b02 cmp r3, #2 + 800203e: d901 bls.n 8002044 { return HAL_TIMEOUT; - 80014fc: 2303 movs r3, #3 - 80014fe: e10c b.n 800171a + 8002040: 2303 movs r3, #3 + 8002042: e10c b.n 800225e while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) - 8001500: 4b6a ldr r3, [pc, #424] ; (80016ac ) - 8001502: 681b ldr r3, [r3, #0] - 8001504: f403 7380 and.w r3, r3, #256 ; 0x100 - 8001508: 2b00 cmp r3, #0 - 800150a: d0f0 beq.n 80014ee + 8002044: 4b6a ldr r3, [pc, #424] ; (80021f0 ) + 8002046: 681b ldr r3, [r3, #0] + 8002048: f403 7380 and.w r3, r3, #256 ; 0x100 + 800204c: 2b00 cmp r3, #0 + 800204e: d0f0 beq.n 8002032 } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); - 800150c: 687b ldr r3, [r7, #4] - 800150e: 689b ldr r3, [r3, #8] - 8001510: 2b01 cmp r3, #1 - 8001512: d106 bne.n 8001522 - 8001514: 4b64 ldr r3, [pc, #400] ; (80016a8 ) - 8001516: 6f1b ldr r3, [r3, #112] ; 0x70 - 8001518: 4a63 ldr r2, [pc, #396] ; (80016a8 ) - 800151a: f043 0301 orr.w r3, r3, #1 - 800151e: 6713 str r3, [r2, #112] ; 0x70 - 8001520: e01c b.n 800155c - 8001522: 687b ldr r3, [r7, #4] - 8001524: 689b ldr r3, [r3, #8] - 8001526: 2b05 cmp r3, #5 - 8001528: d10c bne.n 8001544 - 800152a: 4b5f ldr r3, [pc, #380] ; (80016a8 ) - 800152c: 6f1b ldr r3, [r3, #112] ; 0x70 - 800152e: 4a5e ldr r2, [pc, #376] ; (80016a8 ) - 8001530: f043 0304 orr.w r3, r3, #4 - 8001534: 6713 str r3, [r2, #112] ; 0x70 - 8001536: 4b5c ldr r3, [pc, #368] ; (80016a8 ) - 8001538: 6f1b ldr r3, [r3, #112] ; 0x70 - 800153a: 4a5b ldr r2, [pc, #364] ; (80016a8 ) - 800153c: f043 0301 orr.w r3, r3, #1 - 8001540: 6713 str r3, [r2, #112] ; 0x70 - 8001542: e00b b.n 800155c - 8001544: 4b58 ldr r3, [pc, #352] ; (80016a8 ) - 8001546: 6f1b ldr r3, [r3, #112] ; 0x70 - 8001548: 4a57 ldr r2, [pc, #348] ; (80016a8 ) - 800154a: f023 0301 bic.w r3, r3, #1 - 800154e: 6713 str r3, [r2, #112] ; 0x70 - 8001550: 4b55 ldr r3, [pc, #340] ; (80016a8 ) - 8001552: 6f1b ldr r3, [r3, #112] ; 0x70 - 8001554: 4a54 ldr r2, [pc, #336] ; (80016a8 ) - 8001556: f023 0304 bic.w r3, r3, #4 - 800155a: 6713 str r3, [r2, #112] ; 0x70 + 8002050: 687b ldr r3, [r7, #4] + 8002052: 689b ldr r3, [r3, #8] + 8002054: 2b01 cmp r3, #1 + 8002056: d106 bne.n 8002066 + 8002058: 4b64 ldr r3, [pc, #400] ; (80021ec ) + 800205a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800205c: 4a63 ldr r2, [pc, #396] ; (80021ec ) + 800205e: f043 0301 orr.w r3, r3, #1 + 8002062: 6713 str r3, [r2, #112] ; 0x70 + 8002064: e01c b.n 80020a0 + 8002066: 687b ldr r3, [r7, #4] + 8002068: 689b ldr r3, [r3, #8] + 800206a: 2b05 cmp r3, #5 + 800206c: d10c bne.n 8002088 + 800206e: 4b5f ldr r3, [pc, #380] ; (80021ec ) + 8002070: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002072: 4a5e ldr r2, [pc, #376] ; (80021ec ) + 8002074: f043 0304 orr.w r3, r3, #4 + 8002078: 6713 str r3, [r2, #112] ; 0x70 + 800207a: 4b5c ldr r3, [pc, #368] ; (80021ec ) + 800207c: 6f1b ldr r3, [r3, #112] ; 0x70 + 800207e: 4a5b ldr r2, [pc, #364] ; (80021ec ) + 8002080: f043 0301 orr.w r3, r3, #1 + 8002084: 6713 str r3, [r2, #112] ; 0x70 + 8002086: e00b b.n 80020a0 + 8002088: 4b58 ldr r3, [pc, #352] ; (80021ec ) + 800208a: 6f1b ldr r3, [r3, #112] ; 0x70 + 800208c: 4a57 ldr r2, [pc, #348] ; (80021ec ) + 800208e: f023 0301 bic.w r3, r3, #1 + 8002092: 6713 str r3, [r2, #112] ; 0x70 + 8002094: 4b55 ldr r3, [pc, #340] ; (80021ec ) + 8002096: 6f1b ldr r3, [r3, #112] ; 0x70 + 8002098: 4a54 ldr r2, [pc, #336] ; (80021ec ) + 800209a: f023 0304 bic.w r3, r3, #4 + 800209e: 6713 str r3, [r2, #112] ; 0x70 /* Check the LSE State */ if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) - 800155c: 687b ldr r3, [r7, #4] - 800155e: 689b ldr r3, [r3, #8] - 8001560: 2b00 cmp r3, #0 - 8001562: d015 beq.n 8001590 + 80020a0: 687b ldr r3, [r7, #4] + 80020a2: 689b ldr r3, [r3, #8] + 80020a4: 2b00 cmp r3, #0 + 80020a6: d015 beq.n 80020d4 { /* Get Start Tick*/ tickstart = HAL_GetTick(); - 8001564: f7ff fbc4 bl 8000cf0 - 8001568: 6138 str r0, [r7, #16] + 80020a8: f7fe ff58 bl 8000f5c + 80020ac: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 800156a: e00a b.n 8001582 + 80020ae: e00a b.n 80020c6 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 800156c: f7ff fbc0 bl 8000cf0 - 8001570: 4602 mov r2, r0 - 8001572: 693b ldr r3, [r7, #16] - 8001574: 1ad3 subs r3, r2, r3 - 8001576: f241 3288 movw r2, #5000 ; 0x1388 - 800157a: 4293 cmp r3, r2 - 800157c: d901 bls.n 8001582 + 80020b0: f7fe ff54 bl 8000f5c + 80020b4: 4602 mov r2, r0 + 80020b6: 693b ldr r3, [r7, #16] + 80020b8: 1ad3 subs r3, r2, r3 + 80020ba: f241 3288 movw r2, #5000 ; 0x1388 + 80020be: 4293 cmp r3, r2 + 80020c0: d901 bls.n 80020c6 { return HAL_TIMEOUT; - 800157e: 2303 movs r3, #3 - 8001580: e0cb b.n 800171a + 80020c2: 2303 movs r3, #3 + 80020c4: e0cb b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) - 8001582: 4b49 ldr r3, [pc, #292] ; (80016a8 ) - 8001584: 6f1b ldr r3, [r3, #112] ; 0x70 - 8001586: f003 0302 and.w r3, r3, #2 - 800158a: 2b00 cmp r3, #0 - 800158c: d0ee beq.n 800156c - 800158e: e014 b.n 80015ba + 80020c6: 4b49 ldr r3, [pc, #292] ; (80021ec ) + 80020c8: 6f1b ldr r3, [r3, #112] ; 0x70 + 80020ca: f003 0302 and.w r3, r3, #2 + 80020ce: 2b00 cmp r3, #0 + 80020d0: d0ee beq.n 80020b0 + 80020d2: e014 b.n 80020fe } } else { /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001590: f7ff fbae bl 8000cf0 - 8001594: 6138 str r0, [r7, #16] + 80020d4: f7fe ff42 bl 8000f5c + 80020d8: 6138 str r0, [r7, #16] /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 8001596: e00a b.n 80015ae + 80020da: e00a b.n 80020f2 { if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) - 8001598: f7ff fbaa bl 8000cf0 - 800159c: 4602 mov r2, r0 - 800159e: 693b ldr r3, [r7, #16] - 80015a0: 1ad3 subs r3, r2, r3 - 80015a2: f241 3288 movw r2, #5000 ; 0x1388 - 80015a6: 4293 cmp r3, r2 - 80015a8: d901 bls.n 80015ae + 80020dc: f7fe ff3e bl 8000f5c + 80020e0: 4602 mov r2, r0 + 80020e2: 693b ldr r3, [r7, #16] + 80020e4: 1ad3 subs r3, r2, r3 + 80020e6: f241 3288 movw r2, #5000 ; 0x1388 + 80020ea: 4293 cmp r3, r2 + 80020ec: d901 bls.n 80020f2 { return HAL_TIMEOUT; - 80015aa: 2303 movs r3, #3 - 80015ac: e0b5 b.n 800171a + 80020ee: 2303 movs r3, #3 + 80020f0: e0b5 b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) - 80015ae: 4b3e ldr r3, [pc, #248] ; (80016a8 ) - 80015b0: 6f1b ldr r3, [r3, #112] ; 0x70 - 80015b2: f003 0302 and.w r3, r3, #2 - 80015b6: 2b00 cmp r3, #0 - 80015b8: d1ee bne.n 8001598 + 80020f2: 4b3e ldr r3, [pc, #248] ; (80021ec ) + 80020f4: 6f1b ldr r3, [r3, #112] ; 0x70 + 80020f6: f003 0302 and.w r3, r3, #2 + 80020fa: 2b00 cmp r3, #0 + 80020fc: d1ee bne.n 80020dc } } } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) - 80015ba: 7dfb ldrb r3, [r7, #23] - 80015bc: 2b01 cmp r3, #1 - 80015be: d105 bne.n 80015cc + 80020fe: 7dfb ldrb r3, [r7, #23] + 8002100: 2b01 cmp r3, #1 + 8002102: d105 bne.n 8002110 { __HAL_RCC_PWR_CLK_DISABLE(); - 80015c0: 4b39 ldr r3, [pc, #228] ; (80016a8 ) - 80015c2: 6c1b ldr r3, [r3, #64] ; 0x40 - 80015c4: 4a38 ldr r2, [pc, #224] ; (80016a8 ) - 80015c6: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 - 80015ca: 6413 str r3, [r2, #64] ; 0x40 + 8002104: 4b39 ldr r3, [pc, #228] ; (80021ec ) + 8002106: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002108: 4a38 ldr r2, [pc, #224] ; (80021ec ) + 800210a: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 800210e: 6413 str r3, [r2, #64] ; 0x40 } } /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - 80015cc: 687b ldr r3, [r7, #4] - 80015ce: 699b ldr r3, [r3, #24] - 80015d0: 2b00 cmp r3, #0 - 80015d2: f000 80a1 beq.w 8001718 + 8002110: 687b ldr r3, [r7, #4] + 8002112: 699b ldr r3, [r3, #24] + 8002114: 2b00 cmp r3, #0 + 8002116: f000 80a1 beq.w 800225c { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) - 80015d6: 4b34 ldr r3, [pc, #208] ; (80016a8 ) - 80015d8: 689b ldr r3, [r3, #8] - 80015da: f003 030c and.w r3, r3, #12 - 80015de: 2b08 cmp r3, #8 - 80015e0: d05c beq.n 800169c + 800211a: 4b34 ldr r3, [pc, #208] ; (80021ec ) + 800211c: 689b ldr r3, [r3, #8] + 800211e: f003 030c and.w r3, r3, #12 + 8002122: 2b08 cmp r3, #8 + 8002124: d05c beq.n 80021e0 { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - 80015e2: 687b ldr r3, [r7, #4] - 80015e4: 699b ldr r3, [r3, #24] - 80015e6: 2b02 cmp r3, #2 - 80015e8: d141 bne.n 800166e + 8002126: 687b ldr r3, [r7, #4] + 8002128: 699b ldr r3, [r3, #24] + 800212a: 2b02 cmp r3, #2 + 800212c: d141 bne.n 80021b2 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 80015ea: 4b31 ldr r3, [pc, #196] ; (80016b0 ) - 80015ec: 2200 movs r2, #0 - 80015ee: 601a str r2, [r3, #0] + 800212e: 4b31 ldr r3, [pc, #196] ; (80021f4 ) + 8002130: 2200 movs r2, #0 + 8002132: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 80015f0: f7ff fb7e bl 8000cf0 - 80015f4: 6138 str r0, [r7, #16] + 8002134: f7fe ff12 bl 8000f5c + 8002138: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 80015f6: e008 b.n 800160a + 800213a: e008 b.n 800214e { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 80015f8: f7ff fb7a bl 8000cf0 - 80015fc: 4602 mov r2, r0 - 80015fe: 693b ldr r3, [r7, #16] - 8001600: 1ad3 subs r3, r2, r3 - 8001602: 2b02 cmp r3, #2 - 8001604: d901 bls.n 800160a + 800213c: f7fe ff0e bl 8000f5c + 8002140: 4602 mov r2, r0 + 8002142: 693b ldr r3, [r7, #16] + 8002144: 1ad3 subs r3, r2, r3 + 8002146: 2b02 cmp r3, #2 + 8002148: d901 bls.n 800214e { return HAL_TIMEOUT; - 8001606: 2303 movs r3, #3 - 8001608: e087 b.n 800171a + 800214a: 2303 movs r3, #3 + 800214c: e087 b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 800160a: 4b27 ldr r3, [pc, #156] ; (80016a8 ) - 800160c: 681b ldr r3, [r3, #0] - 800160e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8001612: 2b00 cmp r3, #0 - 8001614: d1f0 bne.n 80015f8 + 800214e: 4b27 ldr r3, [pc, #156] ; (80021ec ) + 8002150: 681b ldr r3, [r3, #0] + 8002152: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002156: 2b00 cmp r3, #0 + 8002158: d1f0 bne.n 800213c } } /* Configure the main PLL clock source, multiplication and division factors. */ WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ - 8001616: 687b ldr r3, [r7, #4] - 8001618: 69da ldr r2, [r3, #28] - 800161a: 687b ldr r3, [r7, #4] - 800161c: 6a1b ldr r3, [r3, #32] - 800161e: 431a orrs r2, r3 - 8001620: 687b ldr r3, [r7, #4] - 8001622: 6a5b ldr r3, [r3, #36] ; 0x24 - 8001624: 019b lsls r3, r3, #6 - 8001626: 431a orrs r2, r3 - 8001628: 687b ldr r3, [r7, #4] - 800162a: 6a9b ldr r3, [r3, #40] ; 0x28 - 800162c: 085b lsrs r3, r3, #1 - 800162e: 3b01 subs r3, #1 - 8001630: 041b lsls r3, r3, #16 - 8001632: 431a orrs r2, r3 - 8001634: 687b ldr r3, [r7, #4] - 8001636: 6adb ldr r3, [r3, #44] ; 0x2c - 8001638: 061b lsls r3, r3, #24 - 800163a: 491b ldr r1, [pc, #108] ; (80016a8 ) - 800163c: 4313 orrs r3, r2 - 800163e: 604b str r3, [r1, #4] + 800215a: 687b ldr r3, [r7, #4] + 800215c: 69da ldr r2, [r3, #28] + 800215e: 687b ldr r3, [r7, #4] + 8002160: 6a1b ldr r3, [r3, #32] + 8002162: 431a orrs r2, r3 + 8002164: 687b ldr r3, [r7, #4] + 8002166: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002168: 019b lsls r3, r3, #6 + 800216a: 431a orrs r2, r3 + 800216c: 687b ldr r3, [r7, #4] + 800216e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8002170: 085b lsrs r3, r3, #1 + 8002172: 3b01 subs r3, #1 + 8002174: 041b lsls r3, r3, #16 + 8002176: 431a orrs r2, r3 + 8002178: 687b ldr r3, [r7, #4] + 800217a: 6adb ldr r3, [r3, #44] ; 0x2c + 800217c: 061b lsls r3, r3, #24 + 800217e: 491b ldr r1, [pc, #108] ; (80021ec ) + 8002180: 4313 orrs r3, r2 + 8002182: 604b str r3, [r1, #4] RCC_OscInitStruct->PLL.PLLM | \ (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); - 8001640: 4b1b ldr r3, [pc, #108] ; (80016b0 ) - 8001642: 2201 movs r2, #1 - 8001644: 601a str r2, [r3, #0] + 8002184: 4b1b ldr r3, [pc, #108] ; (80021f4 ) + 8002186: 2201 movs r2, #1 + 8002188: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001646: f7ff fb53 bl 8000cf0 - 800164a: 6138 str r0, [r7, #16] + 800218a: f7fe fee7 bl 8000f5c + 800218e: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 800164c: e008 b.n 8001660 + 8002190: e008 b.n 80021a4 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 800164e: f7ff fb4f bl 8000cf0 - 8001652: 4602 mov r2, r0 - 8001654: 693b ldr r3, [r7, #16] - 8001656: 1ad3 subs r3, r2, r3 - 8001658: 2b02 cmp r3, #2 - 800165a: d901 bls.n 8001660 + 8002192: f7fe fee3 bl 8000f5c + 8002196: 4602 mov r2, r0 + 8002198: 693b ldr r3, [r7, #16] + 800219a: 1ad3 subs r3, r2, r3 + 800219c: 2b02 cmp r3, #2 + 800219e: d901 bls.n 80021a4 { return HAL_TIMEOUT; - 800165c: 2303 movs r3, #3 - 800165e: e05c b.n 800171a + 80021a0: 2303 movs r3, #3 + 80021a2: e05c b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 8001660: 4b11 ldr r3, [pc, #68] ; (80016a8 ) - 8001662: 681b ldr r3, [r3, #0] - 8001664: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8001668: 2b00 cmp r3, #0 - 800166a: d0f0 beq.n 800164e - 800166c: e054 b.n 8001718 + 80021a4: 4b11 ldr r3, [pc, #68] ; (80021ec ) + 80021a6: 681b ldr r3, [r3, #0] + 80021a8: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80021ac: 2b00 cmp r3, #0 + 80021ae: d0f0 beq.n 8002192 + 80021b0: e054 b.n 800225c } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); - 800166e: 4b10 ldr r3, [pc, #64] ; (80016b0 ) - 8001670: 2200 movs r2, #0 - 8001672: 601a str r2, [r3, #0] + 80021b2: 4b10 ldr r3, [pc, #64] ; (80021f4 ) + 80021b4: 2200 movs r2, #0 + 80021b6: 601a str r2, [r3, #0] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001674: f7ff fb3c bl 8000cf0 - 8001678: 6138 str r0, [r7, #16] + 80021b8: f7fe fed0 bl 8000f5c + 80021bc: 6138 str r0, [r7, #16] /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 800167a: e008 b.n 800168e + 80021be: e008 b.n 80021d2 { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) - 800167c: f7ff fb38 bl 8000cf0 - 8001680: 4602 mov r2, r0 - 8001682: 693b ldr r3, [r7, #16] - 8001684: 1ad3 subs r3, r2, r3 - 8001686: 2b02 cmp r3, #2 - 8001688: d901 bls.n 800168e + 80021c0: f7fe fecc bl 8000f5c + 80021c4: 4602 mov r2, r0 + 80021c6: 693b ldr r3, [r7, #16] + 80021c8: 1ad3 subs r3, r2, r3 + 80021ca: 2b02 cmp r3, #2 + 80021cc: d901 bls.n 80021d2 { return HAL_TIMEOUT; - 800168a: 2303 movs r3, #3 - 800168c: e045 b.n 800171a + 80021ce: 2303 movs r3, #3 + 80021d0: e045 b.n 800225e while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) - 800168e: 4b06 ldr r3, [pc, #24] ; (80016a8 ) - 8001690: 681b ldr r3, [r3, #0] - 8001692: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 8001696: 2b00 cmp r3, #0 - 8001698: d1f0 bne.n 800167c - 800169a: e03d b.n 8001718 + 80021d2: 4b06 ldr r3, [pc, #24] ; (80021ec ) + 80021d4: 681b ldr r3, [r3, #0] + 80021d6: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 80021da: 2b00 cmp r3, #0 + 80021dc: d1f0 bne.n 80021c0 + 80021de: e03d b.n 800225c } } else { /* Check if there is a request to disable the PLL used as System clock source */ if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) - 800169c: 687b ldr r3, [r7, #4] - 800169e: 699b ldr r3, [r3, #24] - 80016a0: 2b01 cmp r3, #1 - 80016a2: d107 bne.n 80016b4 + 80021e0: 687b ldr r3, [r7, #4] + 80021e2: 699b ldr r3, [r3, #24] + 80021e4: 2b01 cmp r3, #1 + 80021e6: d107 bne.n 80021f8 { return HAL_ERROR; - 80016a4: 2301 movs r3, #1 - 80016a6: e038 b.n 800171a - 80016a8: 40023800 .word 0x40023800 - 80016ac: 40007000 .word 0x40007000 - 80016b0: 42470060 .word 0x42470060 + 80021e8: 2301 movs r3, #1 + 80021ea: e038 b.n 800225e + 80021ec: 40023800 .word 0x40023800 + 80021f0: 40007000 .word 0x40007000 + 80021f4: 42470060 .word 0x42470060 } else { /* Do not return HAL_ERROR if request repeats the current configuration */ pll_config = RCC->PLLCFGR; - 80016b4: 4b1b ldr r3, [pc, #108] ; (8001724 ) - 80016b6: 685b ldr r3, [r3, #4] - 80016b8: 60fb str r3, [r7, #12] + 80021f8: 4b1b ldr r3, [pc, #108] ; (8002268 ) + 80021fa: 685b ldr r3, [r3, #4] + 80021fc: 60fb str r3, [r7, #12] (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos))) #else if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 80016ba: 687b ldr r3, [r7, #4] - 80016bc: 699b ldr r3, [r3, #24] - 80016be: 2b01 cmp r3, #1 - 80016c0: d028 beq.n 8001714 + 80021fe: 687b ldr r3, [r7, #4] + 8002200: 699b ldr r3, [r3, #24] + 8002202: 2b01 cmp r3, #1 + 8002204: d028 beq.n 8002258 (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 80016c2: 68fb ldr r3, [r7, #12] - 80016c4: f403 0280 and.w r2, r3, #4194304 ; 0x400000 - 80016c8: 687b ldr r3, [r7, #4] - 80016ca: 69db ldr r3, [r3, #28] + 8002206: 68fb ldr r3, [r7, #12] + 8002208: f403 0280 and.w r2, r3, #4194304 ; 0x400000 + 800220c: 687b ldr r3, [r7, #4] + 800220e: 69db ldr r3, [r3, #28] if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - 80016cc: 429a cmp r2, r3 - 80016ce: d121 bne.n 8001714 + 8002210: 429a cmp r2, r3 + 8002212: d121 bne.n 8002258 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - 80016d0: 68fb ldr r3, [r7, #12] - 80016d2: f003 023f and.w r2, r3, #63 ; 0x3f - 80016d6: 687b ldr r3, [r7, #4] - 80016d8: 6a1b ldr r3, [r3, #32] + 8002214: 68fb ldr r3, [r7, #12] + 8002216: f003 023f and.w r2, r3, #63 ; 0x3f + 800221a: 687b ldr r3, [r7, #4] + 800221c: 6a1b ldr r3, [r3, #32] (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) || - 80016da: 429a cmp r2, r3 - 80016dc: d11a bne.n 8001714 + 800221e: 429a cmp r2, r3 + 8002220: d11a bne.n 8002258 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - 80016de: 68fa ldr r2, [r7, #12] - 80016e0: f647 73c0 movw r3, #32704 ; 0x7fc0 - 80016e4: 4013 ands r3, r2 - 80016e6: 687a ldr r2, [r7, #4] - 80016e8: 6a52 ldr r2, [r2, #36] ; 0x24 - 80016ea: 0192 lsls r2, r2, #6 + 8002222: 68fa ldr r2, [r7, #12] + 8002224: f647 73c0 movw r3, #32704 ; 0x7fc0 + 8002228: 4013 ands r3, r2 + 800222a: 687a ldr r2, [r7, #4] + 800222c: 6a52 ldr r2, [r2, #36] ; 0x24 + 800222e: 0192 lsls r2, r2, #6 (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) || - 80016ec: 4293 cmp r3, r2 - 80016ee: d111 bne.n 8001714 + 8002230: 4293 cmp r3, r2 + 8002232: d111 bne.n 8002258 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - 80016f0: 68fb ldr r3, [r7, #12] - 80016f2: f403 3240 and.w r2, r3, #196608 ; 0x30000 - 80016f6: 687b ldr r3, [r7, #4] - 80016f8: 6a9b ldr r3, [r3, #40] ; 0x28 - 80016fa: 085b lsrs r3, r3, #1 - 80016fc: 3b01 subs r3, #1 - 80016fe: 041b lsls r3, r3, #16 + 8002234: 68fb ldr r3, [r7, #12] + 8002236: f403 3240 and.w r2, r3, #196608 ; 0x30000 + 800223a: 687b ldr r3, [r7, #4] + 800223c: 6a9b ldr r3, [r3, #40] ; 0x28 + 800223e: 085b lsrs r3, r3, #1 + 8002240: 3b01 subs r3, #1 + 8002242: 041b lsls r3, r3, #16 (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) || - 8001700: 429a cmp r2, r3 - 8001702: d107 bne.n 8001714 + 8002244: 429a cmp r2, r3 + 8002246: d107 bne.n 8002258 (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos))) - 8001704: 68fb ldr r3, [r7, #12] - 8001706: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 - 800170a: 687b ldr r3, [r7, #4] - 800170c: 6adb ldr r3, [r3, #44] ; 0x2c - 800170e: 061b lsls r3, r3, #24 + 8002248: 68fb ldr r3, [r7, #12] + 800224a: f003 6270 and.w r2, r3, #251658240 ; 0xf000000 + 800224e: 687b ldr r3, [r7, #4] + 8002250: 6adb ldr r3, [r3, #44] ; 0x2c + 8002252: 061b lsls r3, r3, #24 (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) || - 8001710: 429a cmp r2, r3 - 8001712: d001 beq.n 8001718 + 8002254: 429a cmp r2, r3 + 8002256: d001 beq.n 800225c #endif { return HAL_ERROR; - 8001714: 2301 movs r3, #1 - 8001716: e000 b.n 800171a + 8002258: 2301 movs r3, #1 + 800225a: e000 b.n 800225e } } } } return HAL_OK; - 8001718: 2300 movs r3, #0 + 800225c: 2300 movs r3, #0 } - 800171a: 4618 mov r0, r3 - 800171c: 3718 adds r7, #24 - 800171e: 46bd mov sp, r7 - 8001720: bd80 pop {r7, pc} - 8001722: bf00 nop - 8001724: 40023800 .word 0x40023800 + 800225e: 4618 mov r0, r3 + 8002260: 3718 adds r7, #24 + 8002262: 46bd mov sp, r7 + 8002264: bd80 pop {r7, pc} + 8002266: bf00 nop + 8002268: 40023800 .word 0x40023800 -08001728 : +0800226c : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { - 8001728: b580 push {r7, lr} - 800172a: b084 sub sp, #16 - 800172c: af00 add r7, sp, #0 - 800172e: 6078 str r0, [r7, #4] - 8001730: 6039 str r1, [r7, #0] + 800226c: b580 push {r7, lr} + 800226e: b084 sub sp, #16 + 8002270: af00 add r7, sp, #0 + 8002272: 6078 str r0, [r7, #4] + 8002274: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if(RCC_ClkInitStruct == NULL) - 8001732: 687b ldr r3, [r7, #4] - 8001734: 2b00 cmp r3, #0 - 8001736: d101 bne.n 800173c + 8002276: 687b ldr r3, [r7, #4] + 8002278: 2b00 cmp r3, #0 + 800227a: d101 bne.n 8002280 { return HAL_ERROR; - 8001738: 2301 movs r3, #1 - 800173a: e0cc b.n 80018d6 + 800227c: 2301 movs r3, #1 + 800227e: e0cc b.n 800241a /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > __HAL_FLASH_GET_LATENCY()) - 800173c: 4b68 ldr r3, [pc, #416] ; (80018e0 ) - 800173e: 681b ldr r3, [r3, #0] - 8001740: f003 0307 and.w r3, r3, #7 - 8001744: 683a ldr r2, [r7, #0] - 8001746: 429a cmp r2, r3 - 8001748: d90c bls.n 8001764 + 8002280: 4b68 ldr r3, [pc, #416] ; (8002424 ) + 8002282: 681b ldr r3, [r3, #0] + 8002284: f003 0307 and.w r3, r3, #7 + 8002288: 683a ldr r2, [r7, #0] + 800228a: 429a cmp r2, r3 + 800228c: d90c bls.n 80022a8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 800174a: 4b65 ldr r3, [pc, #404] ; (80018e0 ) - 800174c: 683a ldr r2, [r7, #0] - 800174e: b2d2 uxtb r2, r2 - 8001750: 701a strb r2, [r3, #0] + 800228e: 4b65 ldr r3, [pc, #404] ; (8002424 ) + 8002290: 683a ldr r2, [r7, #0] + 8002292: b2d2 uxtb r2, r2 + 8002294: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 8001752: 4b63 ldr r3, [pc, #396] ; (80018e0 ) - 8001754: 681b ldr r3, [r3, #0] - 8001756: f003 0307 and.w r3, r3, #7 - 800175a: 683a ldr r2, [r7, #0] - 800175c: 429a cmp r2, r3 - 800175e: d001 beq.n 8001764 + 8002296: 4b63 ldr r3, [pc, #396] ; (8002424 ) + 8002298: 681b ldr r3, [r3, #0] + 800229a: f003 0307 and.w r3, r3, #7 + 800229e: 683a ldr r2, [r7, #0] + 80022a0: 429a cmp r2, r3 + 80022a2: d001 beq.n 80022a8 { return HAL_ERROR; - 8001760: 2301 movs r3, #1 - 8001762: e0b8 b.n 80018d6 + 80022a4: 2301 movs r3, #1 + 80022a6: e0b8 b.n 800241a } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - 8001764: 687b ldr r3, [r7, #4] - 8001766: 681b ldr r3, [r3, #0] - 8001768: f003 0302 and.w r3, r3, #2 - 800176c: 2b00 cmp r3, #0 - 800176e: d020 beq.n 80017b2 + 80022a8: 687b ldr r3, [r7, #4] + 80022aa: 681b ldr r3, [r3, #0] + 80022ac: f003 0302 and.w r3, r3, #2 + 80022b0: 2b00 cmp r3, #0 + 80022b2: d020 beq.n 80022f6 { /* Set the highest APBx dividers in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8001770: 687b ldr r3, [r7, #4] - 8001772: 681b ldr r3, [r3, #0] - 8001774: f003 0304 and.w r3, r3, #4 - 8001778: 2b00 cmp r3, #0 - 800177a: d005 beq.n 8001788 + 80022b4: 687b ldr r3, [r7, #4] + 80022b6: 681b ldr r3, [r3, #0] + 80022b8: f003 0304 and.w r3, r3, #4 + 80022bc: 2b00 cmp r3, #0 + 80022be: d005 beq.n 80022cc { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16); - 800177c: 4b59 ldr r3, [pc, #356] ; (80018e4 ) - 800177e: 689b ldr r3, [r3, #8] - 8001780: 4a58 ldr r2, [pc, #352] ; (80018e4 ) - 8001782: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 - 8001786: 6093 str r3, [r2, #8] + 80022c0: 4b59 ldr r3, [pc, #356] ; (8002428 ) + 80022c2: 689b ldr r3, [r3, #8] + 80022c4: 4a58 ldr r2, [pc, #352] ; (8002428 ) + 80022c6: f443 53e0 orr.w r3, r3, #7168 ; 0x1c00 + 80022ca: 6093 str r3, [r2, #8] } if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 8001788: 687b ldr r3, [r7, #4] - 800178a: 681b ldr r3, [r3, #0] - 800178c: f003 0308 and.w r3, r3, #8 - 8001790: 2b00 cmp r3, #0 - 8001792: d005 beq.n 80017a0 + 80022cc: 687b ldr r3, [r7, #4] + 80022ce: 681b ldr r3, [r3, #0] + 80022d0: f003 0308 and.w r3, r3, #8 + 80022d4: 2b00 cmp r3, #0 + 80022d6: d005 beq.n 80022e4 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3)); - 8001794: 4b53 ldr r3, [pc, #332] ; (80018e4 ) - 8001796: 689b ldr r3, [r3, #8] - 8001798: 4a52 ldr r2, [pc, #328] ; (80018e4 ) - 800179a: f443 4360 orr.w r3, r3, #57344 ; 0xe000 - 800179e: 6093 str r3, [r2, #8] + 80022d8: 4b53 ldr r3, [pc, #332] ; (8002428 ) + 80022da: 689b ldr r3, [r3, #8] + 80022dc: 4a52 ldr r2, [pc, #328] ; (8002428 ) + 80022de: f443 4360 orr.w r3, r3, #57344 ; 0xe000 + 80022e2: 6093 str r3, [r2, #8] } assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); - 80017a0: 4b50 ldr r3, [pc, #320] ; (80018e4 ) - 80017a2: 689b ldr r3, [r3, #8] - 80017a4: f023 02f0 bic.w r2, r3, #240 ; 0xf0 - 80017a8: 687b ldr r3, [r7, #4] - 80017aa: 689b ldr r3, [r3, #8] - 80017ac: 494d ldr r1, [pc, #308] ; (80018e4 ) - 80017ae: 4313 orrs r3, r2 - 80017b0: 608b str r3, [r1, #8] + 80022e4: 4b50 ldr r3, [pc, #320] ; (8002428 ) + 80022e6: 689b ldr r3, [r3, #8] + 80022e8: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 80022ec: 687b ldr r3, [r7, #4] + 80022ee: 689b ldr r3, [r3, #8] + 80022f0: 494d ldr r1, [pc, #308] ; (8002428 ) + 80022f2: 4313 orrs r3, r2 + 80022f4: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - 80017b2: 687b ldr r3, [r7, #4] - 80017b4: 681b ldr r3, [r3, #0] - 80017b6: f003 0301 and.w r3, r3, #1 - 80017ba: 2b00 cmp r3, #0 - 80017bc: d044 beq.n 8001848 + 80022f6: 687b ldr r3, [r7, #4] + 80022f8: 681b ldr r3, [r3, #0] + 80022fa: f003 0301 and.w r3, r3, #1 + 80022fe: 2b00 cmp r3, #0 + 8002300: d044 beq.n 800238c { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - 80017be: 687b ldr r3, [r7, #4] - 80017c0: 685b ldr r3, [r3, #4] - 80017c2: 2b01 cmp r3, #1 - 80017c4: d107 bne.n 80017d6 + 8002302: 687b ldr r3, [r7, #4] + 8002304: 685b ldr r3, [r3, #4] + 8002306: 2b01 cmp r3, #1 + 8002308: d107 bne.n 800231a { /* Check the HSE ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) - 80017c6: 4b47 ldr r3, [pc, #284] ; (80018e4 ) - 80017c8: 681b ldr r3, [r3, #0] - 80017ca: f403 3300 and.w r3, r3, #131072 ; 0x20000 - 80017ce: 2b00 cmp r3, #0 - 80017d0: d119 bne.n 8001806 + 800230a: 4b47 ldr r3, [pc, #284] ; (8002428 ) + 800230c: 681b ldr r3, [r3, #0] + 800230e: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002312: 2b00 cmp r3, #0 + 8002314: d119 bne.n 800234a { return HAL_ERROR; - 80017d2: 2301 movs r3, #1 - 80017d4: e07f b.n 80018d6 + 8002316: 2301 movs r3, #1 + 8002318: e07f b.n 800241a } } /* PLL is selected as System Clock Source */ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || - 80017d6: 687b ldr r3, [r7, #4] - 80017d8: 685b ldr r3, [r3, #4] - 80017da: 2b02 cmp r3, #2 - 80017dc: d003 beq.n 80017e6 + 800231a: 687b ldr r3, [r7, #4] + 800231c: 685b ldr r3, [r3, #4] + 800231e: 2b02 cmp r3, #2 + 8002320: d003 beq.n 800232a (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)) - 80017de: 687b ldr r3, [r7, #4] - 80017e0: 685b ldr r3, [r3, #4] + 8002322: 687b ldr r3, [r7, #4] + 8002324: 685b ldr r3, [r3, #4] else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) || - 80017e2: 2b03 cmp r3, #3 - 80017e4: d107 bne.n 80017f6 + 8002326: 2b03 cmp r3, #3 + 8002328: d107 bne.n 800233a { /* Check the PLL ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) - 80017e6: 4b3f ldr r3, [pc, #252] ; (80018e4 ) - 80017e8: 681b ldr r3, [r3, #0] - 80017ea: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 - 80017ee: 2b00 cmp r3, #0 - 80017f0: d109 bne.n 8001806 + 800232a: 4b3f ldr r3, [pc, #252] ; (8002428 ) + 800232c: 681b ldr r3, [r3, #0] + 800232e: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 8002332: 2b00 cmp r3, #0 + 8002334: d109 bne.n 800234a { return HAL_ERROR; - 80017f2: 2301 movs r3, #1 - 80017f4: e06f b.n 80018d6 + 8002336: 2301 movs r3, #1 + 8002338: e06f b.n 800241a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) - 80017f6: 4b3b ldr r3, [pc, #236] ; (80018e4 ) - 80017f8: 681b ldr r3, [r3, #0] - 80017fa: f003 0302 and.w r3, r3, #2 - 80017fe: 2b00 cmp r3, #0 - 8001800: d101 bne.n 8001806 + 800233a: 4b3b ldr r3, [pc, #236] ; (8002428 ) + 800233c: 681b ldr r3, [r3, #0] + 800233e: f003 0302 and.w r3, r3, #2 + 8002342: 2b00 cmp r3, #0 + 8002344: d101 bne.n 800234a { return HAL_ERROR; - 8001802: 2301 movs r3, #1 - 8001804: e067 b.n 80018d6 + 8002346: 2301 movs r3, #1 + 8002348: e067 b.n 800241a } } __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); - 8001806: 4b37 ldr r3, [pc, #220] ; (80018e4 ) - 8001808: 689b ldr r3, [r3, #8] - 800180a: f023 0203 bic.w r2, r3, #3 - 800180e: 687b ldr r3, [r7, #4] - 8001810: 685b ldr r3, [r3, #4] - 8001812: 4934 ldr r1, [pc, #208] ; (80018e4 ) - 8001814: 4313 orrs r3, r2 - 8001816: 608b str r3, [r1, #8] + 800234a: 4b37 ldr r3, [pc, #220] ; (8002428 ) + 800234c: 689b ldr r3, [r3, #8] + 800234e: f023 0203 bic.w r2, r3, #3 + 8002352: 687b ldr r3, [r7, #4] + 8002354: 685b ldr r3, [r3, #4] + 8002356: 4934 ldr r1, [pc, #208] ; (8002428 ) + 8002358: 4313 orrs r3, r2 + 800235a: 608b str r3, [r1, #8] /* Get Start Tick */ tickstart = HAL_GetTick(); - 8001818: f7ff fa6a bl 8000cf0 - 800181c: 60f8 str r0, [r7, #12] + 800235c: f7fe fdfe bl 8000f5c + 8002360: 60f8 str r0, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 800181e: e00a b.n 8001836 + 8002362: e00a b.n 800237a { if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - 8001820: f7ff fa66 bl 8000cf0 - 8001824: 4602 mov r2, r0 - 8001826: 68fb ldr r3, [r7, #12] - 8001828: 1ad3 subs r3, r2, r3 - 800182a: f241 3288 movw r2, #5000 ; 0x1388 - 800182e: 4293 cmp r3, r2 - 8001830: d901 bls.n 8001836 + 8002364: f7fe fdfa bl 8000f5c + 8002368: 4602 mov r2, r0 + 800236a: 68fb ldr r3, [r7, #12] + 800236c: 1ad3 subs r3, r2, r3 + 800236e: f241 3288 movw r2, #5000 ; 0x1388 + 8002372: 4293 cmp r3, r2 + 8002374: d901 bls.n 800237a { return HAL_TIMEOUT; - 8001832: 2303 movs r3, #3 - 8001834: e04f b.n 80018d6 + 8002376: 2303 movs r3, #3 + 8002378: e04f b.n 800241a while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) - 8001836: 4b2b ldr r3, [pc, #172] ; (80018e4 ) - 8001838: 689b ldr r3, [r3, #8] - 800183a: f003 020c and.w r2, r3, #12 - 800183e: 687b ldr r3, [r7, #4] - 8001840: 685b ldr r3, [r3, #4] - 8001842: 009b lsls r3, r3, #2 - 8001844: 429a cmp r2, r3 - 8001846: d1eb bne.n 8001820 + 800237a: 4b2b ldr r3, [pc, #172] ; (8002428 ) + 800237c: 689b ldr r3, [r3, #8] + 800237e: f003 020c and.w r2, r3, #12 + 8002382: 687b ldr r3, [r7, #4] + 8002384: 685b ldr r3, [r3, #4] + 8002386: 009b lsls r3, r3, #2 + 8002388: 429a cmp r2, r3 + 800238a: d1eb bne.n 8002364 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < __HAL_FLASH_GET_LATENCY()) - 8001848: 4b25 ldr r3, [pc, #148] ; (80018e0 ) - 800184a: 681b ldr r3, [r3, #0] - 800184c: f003 0307 and.w r3, r3, #7 - 8001850: 683a ldr r2, [r7, #0] - 8001852: 429a cmp r2, r3 - 8001854: d20c bcs.n 8001870 + 800238c: 4b25 ldr r3, [pc, #148] ; (8002424 ) + 800238e: 681b ldr r3, [r3, #0] + 8002390: f003 0307 and.w r3, r3, #7 + 8002394: 683a ldr r2, [r7, #0] + 8002396: 429a cmp r2, r3 + 8002398: d20c bcs.n 80023b4 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); - 8001856: 4b22 ldr r3, [pc, #136] ; (80018e0 ) - 8001858: 683a ldr r2, [r7, #0] - 800185a: b2d2 uxtb r2, r2 - 800185c: 701a strb r2, [r3, #0] + 800239a: 4b22 ldr r3, [pc, #136] ; (8002424 ) + 800239c: 683a ldr r2, [r7, #0] + 800239e: b2d2 uxtb r2, r2 + 80023a0: 701a strb r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if(__HAL_FLASH_GET_LATENCY() != FLatency) - 800185e: 4b20 ldr r3, [pc, #128] ; (80018e0 ) - 8001860: 681b ldr r3, [r3, #0] - 8001862: f003 0307 and.w r3, r3, #7 - 8001866: 683a ldr r2, [r7, #0] - 8001868: 429a cmp r2, r3 - 800186a: d001 beq.n 8001870 + 80023a2: 4b20 ldr r3, [pc, #128] ; (8002424 ) + 80023a4: 681b ldr r3, [r3, #0] + 80023a6: f003 0307 and.w r3, r3, #7 + 80023aa: 683a ldr r2, [r7, #0] + 80023ac: 429a cmp r2, r3 + 80023ae: d001 beq.n 80023b4 { return HAL_ERROR; - 800186c: 2301 movs r3, #1 - 800186e: e032 b.n 80018d6 + 80023b0: 2301 movs r3, #1 + 80023b2: e032 b.n 800241a } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - 8001870: 687b ldr r3, [r7, #4] - 8001872: 681b ldr r3, [r3, #0] - 8001874: f003 0304 and.w r3, r3, #4 - 8001878: 2b00 cmp r3, #0 - 800187a: d008 beq.n 800188e + 80023b4: 687b ldr r3, [r7, #4] + 80023b6: 681b ldr r3, [r3, #0] + 80023b8: f003 0304 and.w r3, r3, #4 + 80023bc: 2b00 cmp r3, #0 + 80023be: d008 beq.n 80023d2 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); - 800187c: 4b19 ldr r3, [pc, #100] ; (80018e4 ) - 800187e: 689b ldr r3, [r3, #8] - 8001880: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 - 8001884: 687b ldr r3, [r7, #4] - 8001886: 68db ldr r3, [r3, #12] - 8001888: 4916 ldr r1, [pc, #88] ; (80018e4 ) - 800188a: 4313 orrs r3, r2 - 800188c: 608b str r3, [r1, #8] + 80023c0: 4b19 ldr r3, [pc, #100] ; (8002428 ) + 80023c2: 689b ldr r3, [r3, #8] + 80023c4: f423 52e0 bic.w r2, r3, #7168 ; 0x1c00 + 80023c8: 687b ldr r3, [r7, #4] + 80023ca: 68db ldr r3, [r3, #12] + 80023cc: 4916 ldr r1, [pc, #88] ; (8002428 ) + 80023ce: 4313 orrs r3, r2 + 80023d0: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - 800188e: 687b ldr r3, [r7, #4] - 8001890: 681b ldr r3, [r3, #0] - 8001892: f003 0308 and.w r3, r3, #8 - 8001896: 2b00 cmp r3, #0 - 8001898: d009 beq.n 80018ae + 80023d2: 687b ldr r3, [r7, #4] + 80023d4: 681b ldr r3, [r3, #0] + 80023d6: f003 0308 and.w r3, r3, #8 + 80023da: 2b00 cmp r3, #0 + 80023dc: d009 beq.n 80023f2 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); - 800189a: 4b12 ldr r3, [pc, #72] ; (80018e4 ) - 800189c: 689b ldr r3, [r3, #8] - 800189e: f423 4260 bic.w r2, r3, #57344 ; 0xe000 - 80018a2: 687b ldr r3, [r7, #4] - 80018a4: 691b ldr r3, [r3, #16] - 80018a6: 00db lsls r3, r3, #3 - 80018a8: 490e ldr r1, [pc, #56] ; (80018e4 ) - 80018aa: 4313 orrs r3, r2 - 80018ac: 608b str r3, [r1, #8] + 80023de: 4b12 ldr r3, [pc, #72] ; (8002428 ) + 80023e0: 689b ldr r3, [r3, #8] + 80023e2: f423 4260 bic.w r2, r3, #57344 ; 0xe000 + 80023e6: 687b ldr r3, [r7, #4] + 80023e8: 691b ldr r3, [r3, #16] + 80023ea: 00db lsls r3, r3, #3 + 80023ec: 490e ldr r1, [pc, #56] ; (8002428 ) + 80023ee: 4313 orrs r3, r2 + 80023f0: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos]; - 80018ae: f000 f821 bl 80018f4 - 80018b2: 4602 mov r2, r0 - 80018b4: 4b0b ldr r3, [pc, #44] ; (80018e4 ) - 80018b6: 689b ldr r3, [r3, #8] - 80018b8: 091b lsrs r3, r3, #4 - 80018ba: f003 030f and.w r3, r3, #15 - 80018be: 490a ldr r1, [pc, #40] ; (80018e8 ) - 80018c0: 5ccb ldrb r3, [r1, r3] - 80018c2: fa22 f303 lsr.w r3, r2, r3 - 80018c6: 4a09 ldr r2, [pc, #36] ; (80018ec ) - 80018c8: 6013 str r3, [r2, #0] + 80023f2: f000 f821 bl 8002438 + 80023f6: 4602 mov r2, r0 + 80023f8: 4b0b ldr r3, [pc, #44] ; (8002428 ) + 80023fa: 689b ldr r3, [r3, #8] + 80023fc: 091b lsrs r3, r3, #4 + 80023fe: f003 030f and.w r3, r3, #15 + 8002402: 490a ldr r1, [pc, #40] ; (800242c ) + 8002404: 5ccb ldrb r3, [r1, r3] + 8002406: fa22 f303 lsr.w r3, r2, r3 + 800240a: 4a09 ldr r2, [pc, #36] ; (8002430 ) + 800240c: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings */ HAL_InitTick (uwTickPrio); - 80018ca: 4b09 ldr r3, [pc, #36] ; (80018f0 ) - 80018cc: 681b ldr r3, [r3, #0] - 80018ce: 4618 mov r0, r3 - 80018d0: f7ff f90a bl 8000ae8 + 800240e: 4b09 ldr r3, [pc, #36] ; (8002434 ) + 8002410: 681b ldr r3, [r3, #0] + 8002412: 4618 mov r0, r3 + 8002414: f7fe fc94 bl 8000d40 return HAL_OK; - 80018d4: 2300 movs r3, #0 + 8002418: 2300 movs r3, #0 } - 80018d6: 4618 mov r0, r3 - 80018d8: 3710 adds r7, #16 - 80018da: 46bd mov sp, r7 - 80018dc: bd80 pop {r7, pc} - 80018de: bf00 nop - 80018e0: 40023c00 .word 0x40023c00 - 80018e4: 40023800 .word 0x40023800 - 80018e8: 08005740 .word 0x08005740 - 80018ec: 20000000 .word 0x20000000 - 80018f0: 20000004 .word 0x20000004 + 800241a: 4618 mov r0, r3 + 800241c: 3710 adds r7, #16 + 800241e: 46bd mov sp, r7 + 8002420: bd80 pop {r7, pc} + 8002422: bf00 nop + 8002424: 40023c00 .word 0x40023c00 + 8002428: 40023800 .word 0x40023800 + 800242c: 08006324 .word 0x08006324 + 8002430: 20000000 .word 0x20000000 + 8002434: 20000004 .word 0x20000004 -080018f4 : +08002438 : * * * @retval SYSCLK frequency */ __weak uint32_t HAL_RCC_GetSysClockFreq(void) { - 80018f4: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} - 80018f8: b094 sub sp, #80 ; 0x50 - 80018fa: af00 add r7, sp, #0 + 8002438: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 800243c: b094 sub sp, #80 ; 0x50 + 800243e: af00 add r7, sp, #0 uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; - 80018fc: 2300 movs r3, #0 - 80018fe: 647b str r3, [r7, #68] ; 0x44 - 8001900: 2300 movs r3, #0 - 8001902: 64fb str r3, [r7, #76] ; 0x4c - 8001904: 2300 movs r3, #0 - 8001906: 643b str r3, [r7, #64] ; 0x40 + 8002440: 2300 movs r3, #0 + 8002442: 647b str r3, [r7, #68] ; 0x44 + 8002444: 2300 movs r3, #0 + 8002446: 64fb str r3, [r7, #76] ; 0x4c + 8002448: 2300 movs r3, #0 + 800244a: 643b str r3, [r7, #64] ; 0x40 uint32_t sysclockfreq = 0U; - 8001908: 2300 movs r3, #0 - 800190a: 64bb str r3, [r7, #72] ; 0x48 + 800244c: 2300 movs r3, #0 + 800244e: 64bb str r3, [r7, #72] ; 0x48 /* Get SYSCLK source -------------------------------------------------------*/ switch (RCC->CFGR & RCC_CFGR_SWS) - 800190c: 4b79 ldr r3, [pc, #484] ; (8001af4 ) - 800190e: 689b ldr r3, [r3, #8] - 8001910: f003 030c and.w r3, r3, #12 - 8001914: 2b08 cmp r3, #8 - 8001916: d00d beq.n 8001934 - 8001918: 2b08 cmp r3, #8 - 800191a: f200 80e1 bhi.w 8001ae0 - 800191e: 2b00 cmp r3, #0 - 8001920: d002 beq.n 8001928 - 8001922: 2b04 cmp r3, #4 - 8001924: d003 beq.n 800192e - 8001926: e0db b.n 8001ae0 + 8002450: 4b79 ldr r3, [pc, #484] ; (8002638 ) + 8002452: 689b ldr r3, [r3, #8] + 8002454: f003 030c and.w r3, r3, #12 + 8002458: 2b08 cmp r3, #8 + 800245a: d00d beq.n 8002478 + 800245c: 2b08 cmp r3, #8 + 800245e: f200 80e1 bhi.w 8002624 + 8002462: 2b00 cmp r3, #0 + 8002464: d002 beq.n 800246c + 8002466: 2b04 cmp r3, #4 + 8002468: d003 beq.n 8002472 + 800246a: e0db b.n 8002624 { case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ { sysclockfreq = HSI_VALUE; - 8001928: 4b73 ldr r3, [pc, #460] ; (8001af8 ) - 800192a: 64bb str r3, [r7, #72] ; 0x48 + 800246c: 4b73 ldr r3, [pc, #460] ; (800263c ) + 800246e: 64bb str r3, [r7, #72] ; 0x48 break; - 800192c: e0db b.n 8001ae6 + 8002470: e0db b.n 800262a } case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ { sysclockfreq = HSE_VALUE; - 800192e: 4b73 ldr r3, [pc, #460] ; (8001afc ) - 8001930: 64bb str r3, [r7, #72] ; 0x48 + 8002472: 4b73 ldr r3, [pc, #460] ; (8002640 ) + 8002474: 64bb str r3, [r7, #72] ; 0x48 break; - 8001932: e0d8 b.n 8001ae6 + 8002476: e0d8 b.n 800262a } case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ { /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - 8001934: 4b6f ldr r3, [pc, #444] ; (8001af4 ) - 8001936: 685b ldr r3, [r3, #4] - 8001938: f003 033f and.w r3, r3, #63 ; 0x3f - 800193c: 647b str r3, [r7, #68] ; 0x44 + 8002478: 4b6f ldr r3, [pc, #444] ; (8002638 ) + 800247a: 685b ldr r3, [r3, #4] + 800247c: f003 033f and.w r3, r3, #63 ; 0x3f + 8002480: 647b str r3, [r7, #68] ; 0x44 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) - 800193e: 4b6d ldr r3, [pc, #436] ; (8001af4 ) - 8001940: 685b ldr r3, [r3, #4] - 8001942: f403 0380 and.w r3, r3, #4194304 ; 0x400000 - 8001946: 2b00 cmp r3, #0 - 8001948: d063 beq.n 8001a12 + 8002482: 4b6d ldr r3, [pc, #436] ; (8002638 ) + 8002484: 685b ldr r3, [r3, #4] + 8002486: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800248a: 2b00 cmp r3, #0 + 800248c: d063 beq.n 8002556 { /* HSE used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 800194a: 4b6a ldr r3, [pc, #424] ; (8001af4 ) - 800194c: 685b ldr r3, [r3, #4] - 800194e: 099b lsrs r3, r3, #6 - 8001950: 2200 movs r2, #0 - 8001952: 63bb str r3, [r7, #56] ; 0x38 - 8001954: 63fa str r2, [r7, #60] ; 0x3c - 8001956: 6bbb ldr r3, [r7, #56] ; 0x38 - 8001958: f3c3 0308 ubfx r3, r3, #0, #9 - 800195c: 633b str r3, [r7, #48] ; 0x30 - 800195e: 2300 movs r3, #0 - 8001960: 637b str r3, [r7, #52] ; 0x34 - 8001962: e9d7 450c ldrd r4, r5, [r7, #48] ; 0x30 - 8001966: 4622 mov r2, r4 - 8001968: 462b mov r3, r5 - 800196a: f04f 0000 mov.w r0, #0 - 800196e: f04f 0100 mov.w r1, #0 - 8001972: 0159 lsls r1, r3, #5 - 8001974: ea41 61d2 orr.w r1, r1, r2, lsr #27 - 8001978: 0150 lsls r0, r2, #5 - 800197a: 4602 mov r2, r0 - 800197c: 460b mov r3, r1 - 800197e: 4621 mov r1, r4 - 8001980: 1a51 subs r1, r2, r1 - 8001982: 6139 str r1, [r7, #16] - 8001984: 4629 mov r1, r5 - 8001986: eb63 0301 sbc.w r3, r3, r1 - 800198a: 617b str r3, [r7, #20] - 800198c: f04f 0200 mov.w r2, #0 - 8001990: f04f 0300 mov.w r3, #0 - 8001994: e9d7 ab04 ldrd sl, fp, [r7, #16] - 8001998: 4659 mov r1, fp - 800199a: 018b lsls r3, r1, #6 - 800199c: 4651 mov r1, sl - 800199e: ea43 6391 orr.w r3, r3, r1, lsr #26 - 80019a2: 4651 mov r1, sl - 80019a4: 018a lsls r2, r1, #6 - 80019a6: 4651 mov r1, sl - 80019a8: ebb2 0801 subs.w r8, r2, r1 - 80019ac: 4659 mov r1, fp - 80019ae: eb63 0901 sbc.w r9, r3, r1 - 80019b2: f04f 0200 mov.w r2, #0 - 80019b6: f04f 0300 mov.w r3, #0 - 80019ba: ea4f 03c9 mov.w r3, r9, lsl #3 - 80019be: ea43 7358 orr.w r3, r3, r8, lsr #29 - 80019c2: ea4f 02c8 mov.w r2, r8, lsl #3 - 80019c6: 4690 mov r8, r2 - 80019c8: 4699 mov r9, r3 - 80019ca: 4623 mov r3, r4 - 80019cc: eb18 0303 adds.w r3, r8, r3 - 80019d0: 60bb str r3, [r7, #8] - 80019d2: 462b mov r3, r5 - 80019d4: eb49 0303 adc.w r3, r9, r3 - 80019d8: 60fb str r3, [r7, #12] - 80019da: f04f 0200 mov.w r2, #0 - 80019de: f04f 0300 mov.w r3, #0 - 80019e2: e9d7 4502 ldrd r4, r5, [r7, #8] - 80019e6: 4629 mov r1, r5 - 80019e8: 024b lsls r3, r1, #9 - 80019ea: 4621 mov r1, r4 - 80019ec: ea43 53d1 orr.w r3, r3, r1, lsr #23 - 80019f0: 4621 mov r1, r4 - 80019f2: 024a lsls r2, r1, #9 - 80019f4: 4610 mov r0, r2 - 80019f6: 4619 mov r1, r3 - 80019f8: 6c7b ldr r3, [r7, #68] ; 0x44 - 80019fa: 2200 movs r2, #0 - 80019fc: 62bb str r3, [r7, #40] ; 0x28 - 80019fe: 62fa str r2, [r7, #44] ; 0x2c - 8001a00: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 - 8001a04: f7fe fbec bl 80001e0 <__aeabi_uldivmod> - 8001a08: 4602 mov r2, r0 - 8001a0a: 460b mov r3, r1 - 8001a0c: 4613 mov r3, r2 - 8001a0e: 64fb str r3, [r7, #76] ; 0x4c - 8001a10: e058 b.n 8001ac4 + 800248e: 4b6a ldr r3, [pc, #424] ; (8002638 ) + 8002490: 685b ldr r3, [r3, #4] + 8002492: 099b lsrs r3, r3, #6 + 8002494: 2200 movs r2, #0 + 8002496: 63bb str r3, [r7, #56] ; 0x38 + 8002498: 63fa str r2, [r7, #60] ; 0x3c + 800249a: 6bbb ldr r3, [r7, #56] ; 0x38 + 800249c: f3c3 0308 ubfx r3, r3, #0, #9 + 80024a0: 633b str r3, [r7, #48] ; 0x30 + 80024a2: 2300 movs r3, #0 + 80024a4: 637b str r3, [r7, #52] ; 0x34 + 80024a6: e9d7 450c ldrd r4, r5, [r7, #48] ; 0x30 + 80024aa: 4622 mov r2, r4 + 80024ac: 462b mov r3, r5 + 80024ae: f04f 0000 mov.w r0, #0 + 80024b2: f04f 0100 mov.w r1, #0 + 80024b6: 0159 lsls r1, r3, #5 + 80024b8: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 80024bc: 0150 lsls r0, r2, #5 + 80024be: 4602 mov r2, r0 + 80024c0: 460b mov r3, r1 + 80024c2: 4621 mov r1, r4 + 80024c4: 1a51 subs r1, r2, r1 + 80024c6: 6139 str r1, [r7, #16] + 80024c8: 4629 mov r1, r5 + 80024ca: eb63 0301 sbc.w r3, r3, r1 + 80024ce: 617b str r3, [r7, #20] + 80024d0: f04f 0200 mov.w r2, #0 + 80024d4: f04f 0300 mov.w r3, #0 + 80024d8: e9d7 ab04 ldrd sl, fp, [r7, #16] + 80024dc: 4659 mov r1, fp + 80024de: 018b lsls r3, r1, #6 + 80024e0: 4651 mov r1, sl + 80024e2: ea43 6391 orr.w r3, r3, r1, lsr #26 + 80024e6: 4651 mov r1, sl + 80024e8: 018a lsls r2, r1, #6 + 80024ea: 4651 mov r1, sl + 80024ec: ebb2 0801 subs.w r8, r2, r1 + 80024f0: 4659 mov r1, fp + 80024f2: eb63 0901 sbc.w r9, r3, r1 + 80024f6: f04f 0200 mov.w r2, #0 + 80024fa: f04f 0300 mov.w r3, #0 + 80024fe: ea4f 03c9 mov.w r3, r9, lsl #3 + 8002502: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8002506: ea4f 02c8 mov.w r2, r8, lsl #3 + 800250a: 4690 mov r8, r2 + 800250c: 4699 mov r9, r3 + 800250e: 4623 mov r3, r4 + 8002510: eb18 0303 adds.w r3, r8, r3 + 8002514: 60bb str r3, [r7, #8] + 8002516: 462b mov r3, r5 + 8002518: eb49 0303 adc.w r3, r9, r3 + 800251c: 60fb str r3, [r7, #12] + 800251e: f04f 0200 mov.w r2, #0 + 8002522: f04f 0300 mov.w r3, #0 + 8002526: e9d7 4502 ldrd r4, r5, [r7, #8] + 800252a: 4629 mov r1, r5 + 800252c: 024b lsls r3, r1, #9 + 800252e: 4621 mov r1, r4 + 8002530: ea43 53d1 orr.w r3, r3, r1, lsr #23 + 8002534: 4621 mov r1, r4 + 8002536: 024a lsls r2, r1, #9 + 8002538: 4610 mov r0, r2 + 800253a: 4619 mov r1, r3 + 800253c: 6c7b ldr r3, [r7, #68] ; 0x44 + 800253e: 2200 movs r2, #0 + 8002540: 62bb str r3, [r7, #40] ; 0x28 + 8002542: 62fa str r2, [r7, #44] ; 0x2c + 8002544: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 + 8002548: f7fd fe4a bl 80001e0 <__aeabi_uldivmod> + 800254c: 4602 mov r2, r0 + 800254e: 460b mov r3, r1 + 8002550: 4613 mov r3, r2 + 8002552: 64fb str r3, [r7, #76] ; 0x4c + 8002554: e058 b.n 8002608 } else { /* HSI used as PLL clock source */ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm); - 8001a12: 4b38 ldr r3, [pc, #224] ; (8001af4 ) - 8001a14: 685b ldr r3, [r3, #4] - 8001a16: 099b lsrs r3, r3, #6 - 8001a18: 2200 movs r2, #0 - 8001a1a: 4618 mov r0, r3 - 8001a1c: 4611 mov r1, r2 - 8001a1e: f3c0 0308 ubfx r3, r0, #0, #9 - 8001a22: 623b str r3, [r7, #32] - 8001a24: 2300 movs r3, #0 - 8001a26: 627b str r3, [r7, #36] ; 0x24 - 8001a28: e9d7 8908 ldrd r8, r9, [r7, #32] - 8001a2c: 4642 mov r2, r8 - 8001a2e: 464b mov r3, r9 - 8001a30: f04f 0000 mov.w r0, #0 - 8001a34: f04f 0100 mov.w r1, #0 - 8001a38: 0159 lsls r1, r3, #5 - 8001a3a: ea41 61d2 orr.w r1, r1, r2, lsr #27 - 8001a3e: 0150 lsls r0, r2, #5 - 8001a40: 4602 mov r2, r0 - 8001a42: 460b mov r3, r1 - 8001a44: 4641 mov r1, r8 - 8001a46: ebb2 0a01 subs.w sl, r2, r1 - 8001a4a: 4649 mov r1, r9 - 8001a4c: eb63 0b01 sbc.w fp, r3, r1 - 8001a50: f04f 0200 mov.w r2, #0 - 8001a54: f04f 0300 mov.w r3, #0 - 8001a58: ea4f 138b mov.w r3, fp, lsl #6 - 8001a5c: ea43 639a orr.w r3, r3, sl, lsr #26 - 8001a60: ea4f 128a mov.w r2, sl, lsl #6 - 8001a64: ebb2 040a subs.w r4, r2, sl - 8001a68: eb63 050b sbc.w r5, r3, fp - 8001a6c: f04f 0200 mov.w r2, #0 - 8001a70: f04f 0300 mov.w r3, #0 - 8001a74: 00eb lsls r3, r5, #3 - 8001a76: ea43 7354 orr.w r3, r3, r4, lsr #29 - 8001a7a: 00e2 lsls r2, r4, #3 - 8001a7c: 4614 mov r4, r2 - 8001a7e: 461d mov r5, r3 - 8001a80: 4643 mov r3, r8 - 8001a82: 18e3 adds r3, r4, r3 - 8001a84: 603b str r3, [r7, #0] - 8001a86: 464b mov r3, r9 - 8001a88: eb45 0303 adc.w r3, r5, r3 - 8001a8c: 607b str r3, [r7, #4] - 8001a8e: f04f 0200 mov.w r2, #0 - 8001a92: f04f 0300 mov.w r3, #0 - 8001a96: e9d7 4500 ldrd r4, r5, [r7] - 8001a9a: 4629 mov r1, r5 - 8001a9c: 028b lsls r3, r1, #10 - 8001a9e: 4621 mov r1, r4 - 8001aa0: ea43 5391 orr.w r3, r3, r1, lsr #22 - 8001aa4: 4621 mov r1, r4 - 8001aa6: 028a lsls r2, r1, #10 - 8001aa8: 4610 mov r0, r2 - 8001aaa: 4619 mov r1, r3 - 8001aac: 6c7b ldr r3, [r7, #68] ; 0x44 - 8001aae: 2200 movs r2, #0 - 8001ab0: 61bb str r3, [r7, #24] - 8001ab2: 61fa str r2, [r7, #28] - 8001ab4: e9d7 2306 ldrd r2, r3, [r7, #24] - 8001ab8: f7fe fb92 bl 80001e0 <__aeabi_uldivmod> - 8001abc: 4602 mov r2, r0 - 8001abe: 460b mov r3, r1 - 8001ac0: 4613 mov r3, r2 - 8001ac2: 64fb str r3, [r7, #76] ; 0x4c + 8002556: 4b38 ldr r3, [pc, #224] ; (8002638 ) + 8002558: 685b ldr r3, [r3, #4] + 800255a: 099b lsrs r3, r3, #6 + 800255c: 2200 movs r2, #0 + 800255e: 4618 mov r0, r3 + 8002560: 4611 mov r1, r2 + 8002562: f3c0 0308 ubfx r3, r0, #0, #9 + 8002566: 623b str r3, [r7, #32] + 8002568: 2300 movs r3, #0 + 800256a: 627b str r3, [r7, #36] ; 0x24 + 800256c: e9d7 8908 ldrd r8, r9, [r7, #32] + 8002570: 4642 mov r2, r8 + 8002572: 464b mov r3, r9 + 8002574: f04f 0000 mov.w r0, #0 + 8002578: f04f 0100 mov.w r1, #0 + 800257c: 0159 lsls r1, r3, #5 + 800257e: ea41 61d2 orr.w r1, r1, r2, lsr #27 + 8002582: 0150 lsls r0, r2, #5 + 8002584: 4602 mov r2, r0 + 8002586: 460b mov r3, r1 + 8002588: 4641 mov r1, r8 + 800258a: ebb2 0a01 subs.w sl, r2, r1 + 800258e: 4649 mov r1, r9 + 8002590: eb63 0b01 sbc.w fp, r3, r1 + 8002594: f04f 0200 mov.w r2, #0 + 8002598: f04f 0300 mov.w r3, #0 + 800259c: ea4f 138b mov.w r3, fp, lsl #6 + 80025a0: ea43 639a orr.w r3, r3, sl, lsr #26 + 80025a4: ea4f 128a mov.w r2, sl, lsl #6 + 80025a8: ebb2 040a subs.w r4, r2, sl + 80025ac: eb63 050b sbc.w r5, r3, fp + 80025b0: f04f 0200 mov.w r2, #0 + 80025b4: f04f 0300 mov.w r3, #0 + 80025b8: 00eb lsls r3, r5, #3 + 80025ba: ea43 7354 orr.w r3, r3, r4, lsr #29 + 80025be: 00e2 lsls r2, r4, #3 + 80025c0: 4614 mov r4, r2 + 80025c2: 461d mov r5, r3 + 80025c4: 4643 mov r3, r8 + 80025c6: 18e3 adds r3, r4, r3 + 80025c8: 603b str r3, [r7, #0] + 80025ca: 464b mov r3, r9 + 80025cc: eb45 0303 adc.w r3, r5, r3 + 80025d0: 607b str r3, [r7, #4] + 80025d2: f04f 0200 mov.w r2, #0 + 80025d6: f04f 0300 mov.w r3, #0 + 80025da: e9d7 4500 ldrd r4, r5, [r7] + 80025de: 4629 mov r1, r5 + 80025e0: 028b lsls r3, r1, #10 + 80025e2: 4621 mov r1, r4 + 80025e4: ea43 5391 orr.w r3, r3, r1, lsr #22 + 80025e8: 4621 mov r1, r4 + 80025ea: 028a lsls r2, r1, #10 + 80025ec: 4610 mov r0, r2 + 80025ee: 4619 mov r1, r3 + 80025f0: 6c7b ldr r3, [r7, #68] ; 0x44 + 80025f2: 2200 movs r2, #0 + 80025f4: 61bb str r3, [r7, #24] + 80025f6: 61fa str r2, [r7, #28] + 80025f8: e9d7 2306 ldrd r2, r3, [r7, #24] + 80025fc: f7fd fdf0 bl 80001e0 <__aeabi_uldivmod> + 8002600: 4602 mov r2, r0 + 8002602: 460b mov r3, r1 + 8002604: 4613 mov r3, r2 + 8002606: 64fb str r3, [r7, #76] ; 0x4c } pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U); - 8001ac4: 4b0b ldr r3, [pc, #44] ; (8001af4 ) - 8001ac6: 685b ldr r3, [r3, #4] - 8001ac8: 0c1b lsrs r3, r3, #16 - 8001aca: f003 0303 and.w r3, r3, #3 - 8001ace: 3301 adds r3, #1 - 8001ad0: 005b lsls r3, r3, #1 - 8001ad2: 643b str r3, [r7, #64] ; 0x40 + 8002608: 4b0b ldr r3, [pc, #44] ; (8002638 ) + 800260a: 685b ldr r3, [r3, #4] + 800260c: 0c1b lsrs r3, r3, #16 + 800260e: f003 0303 and.w r3, r3, #3 + 8002612: 3301 adds r3, #1 + 8002614: 005b lsls r3, r3, #1 + 8002616: 643b str r3, [r7, #64] ; 0x40 sysclockfreq = pllvco/pllp; - 8001ad4: 6cfa ldr r2, [r7, #76] ; 0x4c - 8001ad6: 6c3b ldr r3, [r7, #64] ; 0x40 - 8001ad8: fbb2 f3f3 udiv r3, r2, r3 - 8001adc: 64bb str r3, [r7, #72] ; 0x48 + 8002618: 6cfa ldr r2, [r7, #76] ; 0x4c + 800261a: 6c3b ldr r3, [r7, #64] ; 0x40 + 800261c: fbb2 f3f3 udiv r3, r2, r3 + 8002620: 64bb str r3, [r7, #72] ; 0x48 break; - 8001ade: e002 b.n 8001ae6 + 8002622: e002 b.n 800262a } default: { sysclockfreq = HSI_VALUE; - 8001ae0: 4b05 ldr r3, [pc, #20] ; (8001af8 ) - 8001ae2: 64bb str r3, [r7, #72] ; 0x48 + 8002624: 4b05 ldr r3, [pc, #20] ; (800263c ) + 8002626: 64bb str r3, [r7, #72] ; 0x48 break; - 8001ae4: bf00 nop + 8002628: bf00 nop } } return sysclockfreq; - 8001ae6: 6cbb ldr r3, [r7, #72] ; 0x48 + 800262a: 6cbb ldr r3, [r7, #72] ; 0x48 } - 8001ae8: 4618 mov r0, r3 - 8001aea: 3750 adds r7, #80 ; 0x50 - 8001aec: 46bd mov sp, r7 - 8001aee: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} - 8001af2: bf00 nop - 8001af4: 40023800 .word 0x40023800 - 8001af8: 00f42400 .word 0x00f42400 - 8001afc: 007a1200 .word 0x007a1200 + 800262c: 4618 mov r0, r3 + 800262e: 3750 adds r7, #80 ; 0x50 + 8002630: 46bd mov sp, r7 + 8002632: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 8002636: bf00 nop + 8002638: 40023800 .word 0x40023800 + 800263c: 00f42400 .word 0x00f42400 + 8002640: 007a1200 .word 0x007a1200 -08001b00 : +08002644 : * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency * and updated within this function * @retval HCLK frequency */ uint32_t HAL_RCC_GetHCLKFreq(void) { - 8001b00: b480 push {r7} - 8001b02: af00 add r7, sp, #0 + 8002644: b480 push {r7} + 8002646: af00 add r7, sp, #0 return SystemCoreClock; - 8001b04: 4b03 ldr r3, [pc, #12] ; (8001b14 ) - 8001b06: 681b ldr r3, [r3, #0] + 8002648: 4b03 ldr r3, [pc, #12] ; (8002658 ) + 800264a: 681b ldr r3, [r3, #0] } - 8001b08: 4618 mov r0, r3 - 8001b0a: 46bd mov sp, r7 - 8001b0c: f85d 7b04 ldr.w r7, [sp], #4 - 8001b10: 4770 bx lr - 8001b12: bf00 nop - 8001b14: 20000000 .word 0x20000000 + 800264c: 4618 mov r0, r3 + 800264e: 46bd mov sp, r7 + 8002650: f85d 7b04 ldr.w r7, [sp], #4 + 8002654: 4770 bx lr + 8002656: bf00 nop + 8002658: 20000000 .word 0x20000000 -08001b18 : +0800265c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency */ uint32_t HAL_RCC_GetPCLK1Freq(void) { - 8001b18: b580 push {r7, lr} - 8001b1a: af00 add r7, sp, #0 + 800265c: b580 push {r7, lr} + 800265e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]); - 8001b1c: f7ff fff0 bl 8001b00 - 8001b20: 4602 mov r2, r0 - 8001b22: 4b05 ldr r3, [pc, #20] ; (8001b38 ) - 8001b24: 689b ldr r3, [r3, #8] - 8001b26: 0a9b lsrs r3, r3, #10 - 8001b28: f003 0307 and.w r3, r3, #7 - 8001b2c: 4903 ldr r1, [pc, #12] ; (8001b3c ) - 8001b2e: 5ccb ldrb r3, [r1, r3] - 8001b30: fa22 f303 lsr.w r3, r2, r3 + 8002660: f7ff fff0 bl 8002644 + 8002664: 4602 mov r2, r0 + 8002666: 4b05 ldr r3, [pc, #20] ; (800267c ) + 8002668: 689b ldr r3, [r3, #8] + 800266a: 0a9b lsrs r3, r3, #10 + 800266c: f003 0307 and.w r3, r3, #7 + 8002670: 4903 ldr r1, [pc, #12] ; (8002680 ) + 8002672: 5ccb ldrb r3, [r1, r3] + 8002674: fa22 f303 lsr.w r3, r2, r3 } - 8001b34: 4618 mov r0, r3 - 8001b36: bd80 pop {r7, pc} - 8001b38: 40023800 .word 0x40023800 - 8001b3c: 08005750 .word 0x08005750 + 8002678: 4618 mov r0, r3 + 800267a: bd80 pop {r7, pc} + 800267c: 40023800 .word 0x40023800 + 8002680: 08006334 .word 0x08006334 -08001b40 : +08002684 : * @note Each time PCLK2 changes, this function must be called to update the * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK2 frequency */ uint32_t HAL_RCC_GetPCLK2Freq(void) { - 8001b40: b580 push {r7, lr} - 8001b42: af00 add r7, sp, #0 + 8002684: b580 push {r7, lr} + 8002686: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]); - 8001b44: f7ff ffdc bl 8001b00 - 8001b48: 4602 mov r2, r0 - 8001b4a: 4b05 ldr r3, [pc, #20] ; (8001b60 ) - 8001b4c: 689b ldr r3, [r3, #8] - 8001b4e: 0b5b lsrs r3, r3, #13 - 8001b50: f003 0307 and.w r3, r3, #7 - 8001b54: 4903 ldr r1, [pc, #12] ; (8001b64 ) - 8001b56: 5ccb ldrb r3, [r1, r3] - 8001b58: fa22 f303 lsr.w r3, r2, r3 + 8002688: f7ff ffdc bl 8002644 + 800268c: 4602 mov r2, r0 + 800268e: 4b05 ldr r3, [pc, #20] ; (80026a4 ) + 8002690: 689b ldr r3, [r3, #8] + 8002692: 0b5b lsrs r3, r3, #13 + 8002694: f003 0307 and.w r3, r3, #7 + 8002698: 4903 ldr r1, [pc, #12] ; (80026a8 ) + 800269a: 5ccb ldrb r3, [r1, r3] + 800269c: fa22 f303 lsr.w r3, r2, r3 } - 8001b5c: 4618 mov r0, r3 - 8001b5e: bd80 pop {r7, pc} - 8001b60: 40023800 .word 0x40023800 - 8001b64: 08005750 .word 0x08005750 + 80026a0: 4618 mov r0, r3 + 80026a2: bd80 pop {r7, pc} + 80026a4: 40023800 .word 0x40023800 + 80026a8: 08006334 .word 0x08006334 -08001b68 : +080026ac : * will be configured. * @param pFLatency Pointer on the Flash Latency. * @retval None */ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) { - 8001b68: b480 push {r7} - 8001b6a: b083 sub sp, #12 - 8001b6c: af00 add r7, sp, #0 - 8001b6e: 6078 str r0, [r7, #4] - 8001b70: 6039 str r1, [r7, #0] + 80026ac: b480 push {r7} + 80026ae: b083 sub sp, #12 + 80026b0: af00 add r7, sp, #0 + 80026b2: 6078 str r0, [r7, #4] + 80026b4: 6039 str r1, [r7, #0] /* Set all possible values for the Clock type parameter --------------------*/ RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; - 8001b72: 687b ldr r3, [r7, #4] - 8001b74: 220f movs r2, #15 - 8001b76: 601a str r2, [r3, #0] + 80026b6: 687b ldr r3, [r7, #4] + 80026b8: 220f movs r2, #15 + 80026ba: 601a str r2, [r3, #0] /* Get the SYSCLK configuration --------------------------------------------*/ RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); - 8001b78: 4b12 ldr r3, [pc, #72] ; (8001bc4 ) - 8001b7a: 689b ldr r3, [r3, #8] - 8001b7c: f003 0203 and.w r2, r3, #3 - 8001b80: 687b ldr r3, [r7, #4] - 8001b82: 605a str r2, [r3, #4] + 80026bc: 4b12 ldr r3, [pc, #72] ; (8002708 ) + 80026be: 689b ldr r3, [r3, #8] + 80026c0: f003 0203 and.w r2, r3, #3 + 80026c4: 687b ldr r3, [r7, #4] + 80026c6: 605a str r2, [r3, #4] /* Get the HCLK configuration ----------------------------------------------*/ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); - 8001b84: 4b0f ldr r3, [pc, #60] ; (8001bc4 ) - 8001b86: 689b ldr r3, [r3, #8] - 8001b88: f003 02f0 and.w r2, r3, #240 ; 0xf0 - 8001b8c: 687b ldr r3, [r7, #4] - 8001b8e: 609a str r2, [r3, #8] + 80026c8: 4b0f ldr r3, [pc, #60] ; (8002708 ) + 80026ca: 689b ldr r3, [r3, #8] + 80026cc: f003 02f0 and.w r2, r3, #240 ; 0xf0 + 80026d0: 687b ldr r3, [r7, #4] + 80026d2: 609a str r2, [r3, #8] /* Get the APB1 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); - 8001b90: 4b0c ldr r3, [pc, #48] ; (8001bc4 ) - 8001b92: 689b ldr r3, [r3, #8] - 8001b94: f403 52e0 and.w r2, r3, #7168 ; 0x1c00 - 8001b98: 687b ldr r3, [r7, #4] - 8001b9a: 60da str r2, [r3, #12] + 80026d4: 4b0c ldr r3, [pc, #48] ; (8002708 ) + 80026d6: 689b ldr r3, [r3, #8] + 80026d8: f403 52e0 and.w r2, r3, #7168 ; 0x1c00 + 80026dc: 687b ldr r3, [r7, #4] + 80026de: 60da str r2, [r3, #12] /* Get the APB2 configuration ----------------------------------------------*/ RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); - 8001b9c: 4b09 ldr r3, [pc, #36] ; (8001bc4 ) - 8001b9e: 689b ldr r3, [r3, #8] - 8001ba0: 08db lsrs r3, r3, #3 - 8001ba2: f403 52e0 and.w r2, r3, #7168 ; 0x1c00 - 8001ba6: 687b ldr r3, [r7, #4] - 8001ba8: 611a str r2, [r3, #16] + 80026e0: 4b09 ldr r3, [pc, #36] ; (8002708 ) + 80026e2: 689b ldr r3, [r3, #8] + 80026e4: 08db lsrs r3, r3, #3 + 80026e6: f403 52e0 and.w r2, r3, #7168 ; 0x1c00 + 80026ea: 687b ldr r3, [r7, #4] + 80026ec: 611a str r2, [r3, #16] /* Get the Flash Wait State (Latency) configuration ------------------------*/ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); - 8001baa: 4b07 ldr r3, [pc, #28] ; (8001bc8 ) - 8001bac: 681b ldr r3, [r3, #0] - 8001bae: f003 0207 and.w r2, r3, #7 - 8001bb2: 683b ldr r3, [r7, #0] - 8001bb4: 601a str r2, [r3, #0] + 80026ee: 4b07 ldr r3, [pc, #28] ; (800270c ) + 80026f0: 681b ldr r3, [r3, #0] + 80026f2: f003 0207 and.w r2, r3, #7 + 80026f6: 683b ldr r3, [r7, #0] + 80026f8: 601a str r2, [r3, #0] } - 8001bb6: bf00 nop - 8001bb8: 370c adds r7, #12 - 8001bba: 46bd mov sp, r7 - 8001bbc: f85d 7b04 ldr.w r7, [sp], #4 - 8001bc0: 4770 bx lr - 8001bc2: bf00 nop - 8001bc4: 40023800 .word 0x40023800 - 8001bc8: 40023c00 .word 0x40023c00 + 80026fa: bf00 nop + 80026fc: 370c adds r7, #12 + 80026fe: 46bd mov sp, r7 + 8002700: f85d 7b04 ldr.w r7, [sp], #4 + 8002704: 4770 bx lr + 8002706: bf00 nop + 8002708: 40023800 .word 0x40023800 + 800270c: 40023c00 .word 0x40023c00 -08001bcc : +08002710 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { - 8001bcc: b580 push {r7, lr} - 8001bce: b082 sub sp, #8 - 8001bd0: af00 add r7, sp, #0 - 8001bd2: 6078 str r0, [r7, #4] + 8002710: b580 push {r7, lr} + 8002712: b082 sub sp, #8 + 8002714: af00 add r7, sp, #0 + 8002716: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) - 8001bd4: 687b ldr r3, [r7, #4] - 8001bd6: 2b00 cmp r3, #0 - 8001bd8: d101 bne.n 8001bde + 8002718: 687b ldr r3, [r7, #4] + 800271a: 2b00 cmp r3, #0 + 800271c: d101 bne.n 8002722 { return HAL_ERROR; - 8001bda: 2301 movs r3, #1 - 8001bdc: e041 b.n 8001c62 + 800271e: 2301 movs r3, #1 + 8002720: e041 b.n 80027a6 assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) - 8001bde: 687b ldr r3, [r7, #4] - 8001be0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d - 8001be4: b2db uxtb r3, r3 - 8001be6: 2b00 cmp r3, #0 - 8001be8: d106 bne.n 8001bf8 + 8002722: 687b ldr r3, [r7, #4] + 8002724: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8002728: b2db uxtb r3, r3 + 800272a: 2b00 cmp r3, #0 + 800272c: d106 bne.n 800273c { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; - 8001bea: 687b ldr r3, [r7, #4] - 8001bec: 2200 movs r2, #0 - 8001bee: f883 203c strb.w r2, [r3, #60] ; 0x3c + 800272e: 687b ldr r3, [r7, #4] + 8002730: 2200 movs r2, #0 + 8002732: f883 203c strb.w r2, [r3, #60] ; 0x3c } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); - 8001bf2: 6878 ldr r0, [r7, #4] - 8001bf4: f000 f839 bl 8001c6a + 8002736: 6878 ldr r0, [r7, #4] + 8002738: f000 f839 bl 80027ae #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8001bf8: 687b ldr r3, [r7, #4] - 8001bfa: 2202 movs r2, #2 - 8001bfc: f883 203d strb.w r2, [r3, #61] ; 0x3d + 800273c: 687b ldr r3, [r7, #4] + 800273e: 2202 movs r2, #2 + 8002740: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); - 8001c00: 687b ldr r3, [r7, #4] - 8001c02: 681a ldr r2, [r3, #0] - 8001c04: 687b ldr r3, [r7, #4] - 8001c06: 3304 adds r3, #4 - 8001c08: 4619 mov r1, r3 - 8001c0a: 4610 mov r0, r2 - 8001c0c: f000 f9ca bl 8001fa4 + 8002744: 687b ldr r3, [r7, #4] + 8002746: 681a ldr r2, [r3, #0] + 8002748: 687b ldr r3, [r7, #4] + 800274a: 3304 adds r3, #4 + 800274c: 4619 mov r1, r3 + 800274e: 4610 mov r0, r2 + 8002750: f000 f9ca bl 8002ae8 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - 8001c10: 687b ldr r3, [r7, #4] - 8001c12: 2201 movs r2, #1 - 8001c14: f883 2046 strb.w r2, [r3, #70] ; 0x46 + 8002754: 687b ldr r3, [r7, #4] + 8002756: 2201 movs r2, #1 + 8002758: f883 2046 strb.w r2, [r3, #70] ; 0x46 /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8001c18: 687b ldr r3, [r7, #4] - 8001c1a: 2201 movs r2, #1 - 8001c1c: f883 203e strb.w r2, [r3, #62] ; 0x3e - 8001c20: 687b ldr r3, [r7, #4] - 8001c22: 2201 movs r2, #1 - 8001c24: f883 203f strb.w r2, [r3, #63] ; 0x3f - 8001c28: 687b ldr r3, [r7, #4] - 8001c2a: 2201 movs r2, #1 - 8001c2c: f883 2040 strb.w r2, [r3, #64] ; 0x40 - 8001c30: 687b ldr r3, [r7, #4] - 8001c32: 2201 movs r2, #1 - 8001c34: f883 2041 strb.w r2, [r3, #65] ; 0x41 + 800275c: 687b ldr r3, [r7, #4] + 800275e: 2201 movs r2, #1 + 8002760: f883 203e strb.w r2, [r3, #62] ; 0x3e + 8002764: 687b ldr r3, [r7, #4] + 8002766: 2201 movs r2, #1 + 8002768: f883 203f strb.w r2, [r3, #63] ; 0x3f + 800276c: 687b ldr r3, [r7, #4] + 800276e: 2201 movs r2, #1 + 8002770: f883 2040 strb.w r2, [r3, #64] ; 0x40 + 8002774: 687b ldr r3, [r7, #4] + 8002776: 2201 movs r2, #1 + 8002778: f883 2041 strb.w r2, [r3, #65] ; 0x41 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - 8001c38: 687b ldr r3, [r7, #4] - 8001c3a: 2201 movs r2, #1 - 8001c3c: f883 2042 strb.w r2, [r3, #66] ; 0x42 - 8001c40: 687b ldr r3, [r7, #4] - 8001c42: 2201 movs r2, #1 - 8001c44: f883 2043 strb.w r2, [r3, #67] ; 0x43 - 8001c48: 687b ldr r3, [r7, #4] - 8001c4a: 2201 movs r2, #1 - 8001c4c: f883 2044 strb.w r2, [r3, #68] ; 0x44 - 8001c50: 687b ldr r3, [r7, #4] - 8001c52: 2201 movs r2, #1 - 8001c54: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 800277c: 687b ldr r3, [r7, #4] + 800277e: 2201 movs r2, #1 + 8002780: f883 2042 strb.w r2, [r3, #66] ; 0x42 + 8002784: 687b ldr r3, [r7, #4] + 8002786: 2201 movs r2, #1 + 8002788: f883 2043 strb.w r2, [r3, #67] ; 0x43 + 800278c: 687b ldr r3, [r7, #4] + 800278e: 2201 movs r2, #1 + 8002790: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 8002794: 687b ldr r3, [r7, #4] + 8002796: 2201 movs r2, #1 + 8002798: f883 2045 strb.w r2, [r3, #69] ; 0x45 /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; - 8001c58: 687b ldr r3, [r7, #4] - 8001c5a: 2201 movs r2, #1 - 8001c5c: f883 203d strb.w r2, [r3, #61] ; 0x3d + 800279c: 687b ldr r3, [r7, #4] + 800279e: 2201 movs r2, #1 + 80027a0: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; - 8001c60: 2300 movs r3, #0 + 80027a4: 2300 movs r3, #0 } - 8001c62: 4618 mov r0, r3 - 8001c64: 3708 adds r7, #8 - 8001c66: 46bd mov sp, r7 - 8001c68: bd80 pop {r7, pc} + 80027a6: 4618 mov r0, r3 + 80027a8: 3708 adds r7, #8 + 80027aa: 46bd mov sp, r7 + 80027ac: bd80 pop {r7, pc} -08001c6a : +080027ae : * @brief Initializes the TIM Base MSP. * @param htim TIM Base handle * @retval None */ __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { - 8001c6a: b480 push {r7} - 8001c6c: b083 sub sp, #12 - 8001c6e: af00 add r7, sp, #0 - 8001c70: 6078 str r0, [r7, #4] + 80027ae: b480 push {r7} + 80027b0: b083 sub sp, #12 + 80027b2: af00 add r7, sp, #0 + 80027b4: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_Base_MspInit could be implemented in the user file */ } - 8001c72: bf00 nop - 8001c74: 370c adds r7, #12 - 8001c76: 46bd mov sp, r7 - 8001c78: f85d 7b04 ldr.w r7, [sp], #4 - 8001c7c: 4770 bx lr + 80027b6: bf00 nop + 80027b8: 370c adds r7, #12 + 80027ba: 46bd mov sp, r7 + 80027bc: f85d 7b04 ldr.w r7, [sp], #4 + 80027c0: 4770 bx lr ... -08001c80 : +080027c4 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { - 8001c80: b480 push {r7} - 8001c82: b085 sub sp, #20 - 8001c84: af00 add r7, sp, #0 - 8001c86: 6078 str r0, [r7, #4] + 80027c4: b480 push {r7} + 80027c6: b085 sub sp, #20 + 80027c8: af00 add r7, sp, #0 + 80027ca: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) - 8001c88: 687b ldr r3, [r7, #4] - 8001c8a: f893 303d ldrb.w r3, [r3, #61] ; 0x3d - 8001c8e: b2db uxtb r3, r3 - 8001c90: 2b01 cmp r3, #1 - 8001c92: d001 beq.n 8001c98 + 80027cc: 687b ldr r3, [r7, #4] + 80027ce: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 80027d2: b2db uxtb r3, r3 + 80027d4: 2b01 cmp r3, #1 + 80027d6: d001 beq.n 80027dc { return HAL_ERROR; - 8001c94: 2301 movs r3, #1 - 8001c96: e044 b.n 8001d22 + 80027d8: 2301 movs r3, #1 + 80027da: e044 b.n 8002866 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; - 8001c98: 687b ldr r3, [r7, #4] - 8001c9a: 2202 movs r2, #2 - 8001c9c: f883 203d strb.w r2, [r3, #61] ; 0x3d + 80027dc: 687b ldr r3, [r7, #4] + 80027de: 2202 movs r2, #2 + 80027e0: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - 8001ca0: 687b ldr r3, [r7, #4] - 8001ca2: 681b ldr r3, [r3, #0] - 8001ca4: 68da ldr r2, [r3, #12] - 8001ca6: 687b ldr r3, [r7, #4] - 8001ca8: 681b ldr r3, [r3, #0] - 8001caa: f042 0201 orr.w r2, r2, #1 - 8001cae: 60da str r2, [r3, #12] + 80027e4: 687b ldr r3, [r7, #4] + 80027e6: 681b ldr r3, [r3, #0] + 80027e8: 68da ldr r2, [r3, #12] + 80027ea: 687b ldr r3, [r7, #4] + 80027ec: 681b ldr r3, [r3, #0] + 80027ee: f042 0201 orr.w r2, r2, #1 + 80027f2: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - 8001cb0: 687b ldr r3, [r7, #4] - 8001cb2: 681b ldr r3, [r3, #0] - 8001cb4: 4a1e ldr r2, [pc, #120] ; (8001d30 ) - 8001cb6: 4293 cmp r3, r2 - 8001cb8: d018 beq.n 8001cec - 8001cba: 687b ldr r3, [r7, #4] - 8001cbc: 681b ldr r3, [r3, #0] - 8001cbe: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 - 8001cc2: d013 beq.n 8001cec - 8001cc4: 687b ldr r3, [r7, #4] - 8001cc6: 681b ldr r3, [r3, #0] - 8001cc8: 4a1a ldr r2, [pc, #104] ; (8001d34 ) - 8001cca: 4293 cmp r3, r2 - 8001ccc: d00e beq.n 8001cec - 8001cce: 687b ldr r3, [r7, #4] - 8001cd0: 681b ldr r3, [r3, #0] - 8001cd2: 4a19 ldr r2, [pc, #100] ; (8001d38 ) - 8001cd4: 4293 cmp r3, r2 - 8001cd6: d009 beq.n 8001cec - 8001cd8: 687b ldr r3, [r7, #4] - 8001cda: 681b ldr r3, [r3, #0] - 8001cdc: 4a17 ldr r2, [pc, #92] ; (8001d3c ) - 8001cde: 4293 cmp r3, r2 - 8001ce0: d004 beq.n 8001cec - 8001ce2: 687b ldr r3, [r7, #4] - 8001ce4: 681b ldr r3, [r3, #0] - 8001ce6: 4a16 ldr r2, [pc, #88] ; (8001d40 ) - 8001ce8: 4293 cmp r3, r2 - 8001cea: d111 bne.n 8001d10 + 80027f4: 687b ldr r3, [r7, #4] + 80027f6: 681b ldr r3, [r3, #0] + 80027f8: 4a1e ldr r2, [pc, #120] ; (8002874 ) + 80027fa: 4293 cmp r3, r2 + 80027fc: d018 beq.n 8002830 + 80027fe: 687b ldr r3, [r7, #4] + 8002800: 681b ldr r3, [r3, #0] + 8002802: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8002806: d013 beq.n 8002830 + 8002808: 687b ldr r3, [r7, #4] + 800280a: 681b ldr r3, [r3, #0] + 800280c: 4a1a ldr r2, [pc, #104] ; (8002878 ) + 800280e: 4293 cmp r3, r2 + 8002810: d00e beq.n 8002830 + 8002812: 687b ldr r3, [r7, #4] + 8002814: 681b ldr r3, [r3, #0] + 8002816: 4a19 ldr r2, [pc, #100] ; (800287c ) + 8002818: 4293 cmp r3, r2 + 800281a: d009 beq.n 8002830 + 800281c: 687b ldr r3, [r7, #4] + 800281e: 681b ldr r3, [r3, #0] + 8002820: 4a17 ldr r2, [pc, #92] ; (8002880 ) + 8002822: 4293 cmp r3, r2 + 8002824: d004 beq.n 8002830 + 8002826: 687b ldr r3, [r7, #4] + 8002828: 681b ldr r3, [r3, #0] + 800282a: 4a16 ldr r2, [pc, #88] ; (8002884 ) + 800282c: 4293 cmp r3, r2 + 800282e: d111 bne.n 8002854 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - 8001cec: 687b ldr r3, [r7, #4] - 8001cee: 681b ldr r3, [r3, #0] - 8001cf0: 689b ldr r3, [r3, #8] - 8001cf2: f003 0307 and.w r3, r3, #7 - 8001cf6: 60fb str r3, [r7, #12] + 8002830: 687b ldr r3, [r7, #4] + 8002832: 681b ldr r3, [r3, #0] + 8002834: 689b ldr r3, [r3, #8] + 8002836: f003 0307 and.w r3, r3, #7 + 800283a: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 8001cf8: 68fb ldr r3, [r7, #12] - 8001cfa: 2b06 cmp r3, #6 - 8001cfc: d010 beq.n 8001d20 + 800283c: 68fb ldr r3, [r7, #12] + 800283e: 2b06 cmp r3, #6 + 8002840: d010 beq.n 8002864 { __HAL_TIM_ENABLE(htim); - 8001cfe: 687b ldr r3, [r7, #4] - 8001d00: 681b ldr r3, [r3, #0] - 8001d02: 681a ldr r2, [r3, #0] - 8001d04: 687b ldr r3, [r7, #4] - 8001d06: 681b ldr r3, [r3, #0] - 8001d08: f042 0201 orr.w r2, r2, #1 - 8001d0c: 601a str r2, [r3, #0] + 8002842: 687b ldr r3, [r7, #4] + 8002844: 681b ldr r3, [r3, #0] + 8002846: 681a ldr r2, [r3, #0] + 8002848: 687b ldr r3, [r7, #4] + 800284a: 681b ldr r3, [r3, #0] + 800284c: f042 0201 orr.w r2, r2, #1 + 8002850: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - 8001d0e: e007 b.n 8001d20 + 8002852: e007 b.n 8002864 } } else { __HAL_TIM_ENABLE(htim); - 8001d10: 687b ldr r3, [r7, #4] - 8001d12: 681b ldr r3, [r3, #0] - 8001d14: 681a ldr r2, [r3, #0] - 8001d16: 687b ldr r3, [r7, #4] - 8001d18: 681b ldr r3, [r3, #0] - 8001d1a: f042 0201 orr.w r2, r2, #1 - 8001d1e: 601a str r2, [r3, #0] + 8002854: 687b ldr r3, [r7, #4] + 8002856: 681b ldr r3, [r3, #0] + 8002858: 681a ldr r2, [r3, #0] + 800285a: 687b ldr r3, [r7, #4] + 800285c: 681b ldr r3, [r3, #0] + 800285e: f042 0201 orr.w r2, r2, #1 + 8002862: 601a str r2, [r3, #0] } /* Return function status */ return HAL_OK; - 8001d20: 2300 movs r3, #0 + 8002864: 2300 movs r3, #0 } - 8001d22: 4618 mov r0, r3 - 8001d24: 3714 adds r7, #20 - 8001d26: 46bd mov sp, r7 - 8001d28: f85d 7b04 ldr.w r7, [sp], #4 - 8001d2c: 4770 bx lr - 8001d2e: bf00 nop - 8001d30: 40010000 .word 0x40010000 - 8001d34: 40000400 .word 0x40000400 - 8001d38: 40000800 .word 0x40000800 - 8001d3c: 40000c00 .word 0x40000c00 - 8001d40: 40014000 .word 0x40014000 + 8002866: 4618 mov r0, r3 + 8002868: 3714 adds r7, #20 + 800286a: 46bd mov sp, r7 + 800286c: f85d 7b04 ldr.w r7, [sp], #4 + 8002870: 4770 bx lr + 8002872: bf00 nop + 8002874: 40010000 .word 0x40010000 + 8002878: 40000400 .word 0x40000400 + 800287c: 40000800 .word 0x40000800 + 8002880: 40000c00 .word 0x40000c00 + 8002884: 40014000 .word 0x40014000 -08001d44 : +08002888 : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { - 8001d44: b580 push {r7, lr} - 8001d46: b082 sub sp, #8 - 8001d48: af00 add r7, sp, #0 - 8001d4a: 6078 str r0, [r7, #4] + 8002888: b580 push {r7, lr} + 800288a: b082 sub sp, #8 + 800288c: af00 add r7, sp, #0 + 800288e: 6078 str r0, [r7, #4] /* Capture compare 1 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - 8001d4c: 687b ldr r3, [r7, #4] - 8001d4e: 681b ldr r3, [r3, #0] - 8001d50: 691b ldr r3, [r3, #16] - 8001d52: f003 0302 and.w r3, r3, #2 - 8001d56: 2b02 cmp r3, #2 - 8001d58: d122 bne.n 8001da0 + 8002890: 687b ldr r3, [r7, #4] + 8002892: 681b ldr r3, [r3, #0] + 8002894: 691b ldr r3, [r3, #16] + 8002896: f003 0302 and.w r3, r3, #2 + 800289a: 2b02 cmp r3, #2 + 800289c: d122 bne.n 80028e4 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET) - 8001d5a: 687b ldr r3, [r7, #4] - 8001d5c: 681b ldr r3, [r3, #0] - 8001d5e: 68db ldr r3, [r3, #12] - 8001d60: f003 0302 and.w r3, r3, #2 - 8001d64: 2b02 cmp r3, #2 - 8001d66: d11b bne.n 8001da0 + 800289e: 687b ldr r3, [r7, #4] + 80028a0: 681b ldr r3, [r3, #0] + 80028a2: 68db ldr r3, [r3, #12] + 80028a4: f003 0302 and.w r3, r3, #2 + 80028a8: 2b02 cmp r3, #2 + 80028aa: d11b bne.n 80028e4 { { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - 8001d68: 687b ldr r3, [r7, #4] - 8001d6a: 681b ldr r3, [r3, #0] - 8001d6c: f06f 0202 mvn.w r2, #2 - 8001d70: 611a str r2, [r3, #16] + 80028ac: 687b ldr r3, [r7, #4] + 80028ae: 681b ldr r3, [r3, #0] + 80028b0: f06f 0202 mvn.w r2, #2 + 80028b4: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - 8001d72: 687b ldr r3, [r7, #4] - 8001d74: 2201 movs r2, #1 - 8001d76: 771a strb r2, [r3, #28] + 80028b6: 687b ldr r3, [r7, #4] + 80028b8: 2201 movs r2, #1 + 80028ba: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - 8001d78: 687b ldr r3, [r7, #4] - 8001d7a: 681b ldr r3, [r3, #0] - 8001d7c: 699b ldr r3, [r3, #24] - 8001d7e: f003 0303 and.w r3, r3, #3 - 8001d82: 2b00 cmp r3, #0 - 8001d84: d003 beq.n 8001d8e + 80028bc: 687b ldr r3, [r7, #4] + 80028be: 681b ldr r3, [r3, #0] + 80028c0: 699b ldr r3, [r3, #24] + 80028c2: f003 0303 and.w r3, r3, #3 + 80028c6: 2b00 cmp r3, #0 + 80028c8: d003 beq.n 80028d2 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8001d86: 6878 ldr r0, [r7, #4] - 8001d88: f000 f8ee bl 8001f68 - 8001d8c: e005 b.n 8001d9a + 80028ca: 6878 ldr r0, [r7, #4] + 80028cc: f000 f8ee bl 8002aac + 80028d0: e005 b.n 80028de { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8001d8e: 6878 ldr r0, [r7, #4] - 8001d90: f000 f8e0 bl 8001f54 + 80028d2: 6878 ldr r0, [r7, #4] + 80028d4: f000 f8e0 bl 8002a98 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8001d94: 6878 ldr r0, [r7, #4] - 8001d96: f000 f8f1 bl 8001f7c + 80028d8: 6878 ldr r0, [r7, #4] + 80028da: f000 f8f1 bl 8002ac0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8001d9a: 687b ldr r3, [r7, #4] - 8001d9c: 2200 movs r2, #0 - 8001d9e: 771a strb r2, [r3, #28] + 80028de: 687b ldr r3, [r7, #4] + 80028e0: 2200 movs r2, #0 + 80028e2: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - 8001da0: 687b ldr r3, [r7, #4] - 8001da2: 681b ldr r3, [r3, #0] - 8001da4: 691b ldr r3, [r3, #16] - 8001da6: f003 0304 and.w r3, r3, #4 - 8001daa: 2b04 cmp r3, #4 - 8001dac: d122 bne.n 8001df4 + 80028e4: 687b ldr r3, [r7, #4] + 80028e6: 681b ldr r3, [r3, #0] + 80028e8: 691b ldr r3, [r3, #16] + 80028ea: f003 0304 and.w r3, r3, #4 + 80028ee: 2b04 cmp r3, #4 + 80028f0: d122 bne.n 8002938 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET) - 8001dae: 687b ldr r3, [r7, #4] - 8001db0: 681b ldr r3, [r3, #0] - 8001db2: 68db ldr r3, [r3, #12] - 8001db4: f003 0304 and.w r3, r3, #4 - 8001db8: 2b04 cmp r3, #4 - 8001dba: d11b bne.n 8001df4 + 80028f2: 687b ldr r3, [r7, #4] + 80028f4: 681b ldr r3, [r3, #0] + 80028f6: 68db ldr r3, [r3, #12] + 80028f8: f003 0304 and.w r3, r3, #4 + 80028fc: 2b04 cmp r3, #4 + 80028fe: d11b bne.n 8002938 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - 8001dbc: 687b ldr r3, [r7, #4] - 8001dbe: 681b ldr r3, [r3, #0] - 8001dc0: f06f 0204 mvn.w r2, #4 - 8001dc4: 611a str r2, [r3, #16] + 8002900: 687b ldr r3, [r7, #4] + 8002902: 681b ldr r3, [r3, #0] + 8002904: f06f 0204 mvn.w r2, #4 + 8002908: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - 8001dc6: 687b ldr r3, [r7, #4] - 8001dc8: 2202 movs r2, #2 - 8001dca: 771a strb r2, [r3, #28] + 800290a: 687b ldr r3, [r7, #4] + 800290c: 2202 movs r2, #2 + 800290e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - 8001dcc: 687b ldr r3, [r7, #4] - 8001dce: 681b ldr r3, [r3, #0] - 8001dd0: 699b ldr r3, [r3, #24] - 8001dd2: f403 7340 and.w r3, r3, #768 ; 0x300 - 8001dd6: 2b00 cmp r3, #0 - 8001dd8: d003 beq.n 8001de2 + 8002910: 687b ldr r3, [r7, #4] + 8002912: 681b ldr r3, [r3, #0] + 8002914: 699b ldr r3, [r3, #24] + 8002916: f403 7340 and.w r3, r3, #768 ; 0x300 + 800291a: 2b00 cmp r3, #0 + 800291c: d003 beq.n 8002926 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8001dda: 6878 ldr r0, [r7, #4] - 8001ddc: f000 f8c4 bl 8001f68 - 8001de0: e005 b.n 8001dee + 800291e: 6878 ldr r0, [r7, #4] + 8002920: f000 f8c4 bl 8002aac + 8002924: e005 b.n 8002932 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8001de2: 6878 ldr r0, [r7, #4] - 8001de4: f000 f8b6 bl 8001f54 + 8002926: 6878 ldr r0, [r7, #4] + 8002928: f000 f8b6 bl 8002a98 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8001de8: 6878 ldr r0, [r7, #4] - 8001dea: f000 f8c7 bl 8001f7c + 800292c: 6878 ldr r0, [r7, #4] + 800292e: f000 f8c7 bl 8002ac0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8001dee: 687b ldr r3, [r7, #4] - 8001df0: 2200 movs r2, #0 - 8001df2: 771a strb r2, [r3, #28] + 8002932: 687b ldr r3, [r7, #4] + 8002934: 2200 movs r2, #0 + 8002936: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - 8001df4: 687b ldr r3, [r7, #4] - 8001df6: 681b ldr r3, [r3, #0] - 8001df8: 691b ldr r3, [r3, #16] - 8001dfa: f003 0308 and.w r3, r3, #8 - 8001dfe: 2b08 cmp r3, #8 - 8001e00: d122 bne.n 8001e48 + 8002938: 687b ldr r3, [r7, #4] + 800293a: 681b ldr r3, [r3, #0] + 800293c: 691b ldr r3, [r3, #16] + 800293e: f003 0308 and.w r3, r3, #8 + 8002942: 2b08 cmp r3, #8 + 8002944: d122 bne.n 800298c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET) - 8001e02: 687b ldr r3, [r7, #4] - 8001e04: 681b ldr r3, [r3, #0] - 8001e06: 68db ldr r3, [r3, #12] - 8001e08: f003 0308 and.w r3, r3, #8 - 8001e0c: 2b08 cmp r3, #8 - 8001e0e: d11b bne.n 8001e48 + 8002946: 687b ldr r3, [r7, #4] + 8002948: 681b ldr r3, [r3, #0] + 800294a: 68db ldr r3, [r3, #12] + 800294c: f003 0308 and.w r3, r3, #8 + 8002950: 2b08 cmp r3, #8 + 8002952: d11b bne.n 800298c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - 8001e10: 687b ldr r3, [r7, #4] - 8001e12: 681b ldr r3, [r3, #0] - 8001e14: f06f 0208 mvn.w r2, #8 - 8001e18: 611a str r2, [r3, #16] + 8002954: 687b ldr r3, [r7, #4] + 8002956: 681b ldr r3, [r3, #0] + 8002958: f06f 0208 mvn.w r2, #8 + 800295c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - 8001e1a: 687b ldr r3, [r7, #4] - 8001e1c: 2204 movs r2, #4 - 8001e1e: 771a strb r2, [r3, #28] + 800295e: 687b ldr r3, [r7, #4] + 8002960: 2204 movs r2, #4 + 8002962: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - 8001e20: 687b ldr r3, [r7, #4] - 8001e22: 681b ldr r3, [r3, #0] - 8001e24: 69db ldr r3, [r3, #28] - 8001e26: f003 0303 and.w r3, r3, #3 - 8001e2a: 2b00 cmp r3, #0 - 8001e2c: d003 beq.n 8001e36 + 8002964: 687b ldr r3, [r7, #4] + 8002966: 681b ldr r3, [r3, #0] + 8002968: 69db ldr r3, [r3, #28] + 800296a: f003 0303 and.w r3, r3, #3 + 800296e: 2b00 cmp r3, #0 + 8002970: d003 beq.n 800297a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8001e2e: 6878 ldr r0, [r7, #4] - 8001e30: f000 f89a bl 8001f68 - 8001e34: e005 b.n 8001e42 + 8002972: 6878 ldr r0, [r7, #4] + 8002974: f000 f89a bl 8002aac + 8002978: e005 b.n 8002986 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8001e36: 6878 ldr r0, [r7, #4] - 8001e38: f000 f88c bl 8001f54 + 800297a: 6878 ldr r0, [r7, #4] + 800297c: f000 f88c bl 8002a98 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8001e3c: 6878 ldr r0, [r7, #4] - 8001e3e: f000 f89d bl 8001f7c + 8002980: 6878 ldr r0, [r7, #4] + 8002982: f000 f89d bl 8002ac0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8001e42: 687b ldr r3, [r7, #4] - 8001e44: 2200 movs r2, #0 - 8001e46: 771a strb r2, [r3, #28] + 8002986: 687b ldr r3, [r7, #4] + 8002988: 2200 movs r2, #0 + 800298a: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - 8001e48: 687b ldr r3, [r7, #4] - 8001e4a: 681b ldr r3, [r3, #0] - 8001e4c: 691b ldr r3, [r3, #16] - 8001e4e: f003 0310 and.w r3, r3, #16 - 8001e52: 2b10 cmp r3, #16 - 8001e54: d122 bne.n 8001e9c + 800298c: 687b ldr r3, [r7, #4] + 800298e: 681b ldr r3, [r3, #0] + 8002990: 691b ldr r3, [r3, #16] + 8002992: f003 0310 and.w r3, r3, #16 + 8002996: 2b10 cmp r3, #16 + 8002998: d122 bne.n 80029e0 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET) - 8001e56: 687b ldr r3, [r7, #4] - 8001e58: 681b ldr r3, [r3, #0] - 8001e5a: 68db ldr r3, [r3, #12] - 8001e5c: f003 0310 and.w r3, r3, #16 - 8001e60: 2b10 cmp r3, #16 - 8001e62: d11b bne.n 8001e9c + 800299a: 687b ldr r3, [r7, #4] + 800299c: 681b ldr r3, [r3, #0] + 800299e: 68db ldr r3, [r3, #12] + 80029a0: f003 0310 and.w r3, r3, #16 + 80029a4: 2b10 cmp r3, #16 + 80029a6: d11b bne.n 80029e0 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - 8001e64: 687b ldr r3, [r7, #4] - 8001e66: 681b ldr r3, [r3, #0] - 8001e68: f06f 0210 mvn.w r2, #16 - 8001e6c: 611a str r2, [r3, #16] + 80029a8: 687b ldr r3, [r7, #4] + 80029aa: 681b ldr r3, [r3, #0] + 80029ac: f06f 0210 mvn.w r2, #16 + 80029b0: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - 8001e6e: 687b ldr r3, [r7, #4] - 8001e70: 2208 movs r2, #8 - 8001e72: 771a strb r2, [r3, #28] + 80029b2: 687b ldr r3, [r7, #4] + 80029b4: 2208 movs r2, #8 + 80029b6: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - 8001e74: 687b ldr r3, [r7, #4] - 8001e76: 681b ldr r3, [r3, #0] - 8001e78: 69db ldr r3, [r3, #28] - 8001e7a: f403 7340 and.w r3, r3, #768 ; 0x300 - 8001e7e: 2b00 cmp r3, #0 - 8001e80: d003 beq.n 8001e8a + 80029b8: 687b ldr r3, [r7, #4] + 80029ba: 681b ldr r3, [r3, #0] + 80029bc: 69db ldr r3, [r3, #28] + 80029be: f403 7340 and.w r3, r3, #768 ; 0x300 + 80029c2: 2b00 cmp r3, #0 + 80029c4: d003 beq.n 80029ce { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); - 8001e82: 6878 ldr r0, [r7, #4] - 8001e84: f000 f870 bl 8001f68 - 8001e88: e005 b.n 8001e96 + 80029c6: 6878 ldr r0, [r7, #4] + 80029c8: f000 f870 bl 8002aac + 80029cc: e005 b.n 80029da { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); - 8001e8a: 6878 ldr r0, [r7, #4] - 8001e8c: f000 f862 bl 8001f54 + 80029ce: 6878 ldr r0, [r7, #4] + 80029d0: f000 f862 bl 8002a98 HAL_TIM_PWM_PulseFinishedCallback(htim); - 8001e90: 6878 ldr r0, [r7, #4] - 8001e92: f000 f873 bl 8001f7c + 80029d4: 6878 ldr r0, [r7, #4] + 80029d6: f000 f873 bl 8002ac0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - 8001e96: 687b ldr r3, [r7, #4] - 8001e98: 2200 movs r2, #0 - 8001e9a: 771a strb r2, [r3, #28] + 80029da: 687b ldr r3, [r7, #4] + 80029dc: 2200 movs r2, #0 + 80029de: 771a strb r2, [r3, #28] } } /* TIM Update event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - 8001e9c: 687b ldr r3, [r7, #4] - 8001e9e: 681b ldr r3, [r3, #0] - 8001ea0: 691b ldr r3, [r3, #16] - 8001ea2: f003 0301 and.w r3, r3, #1 - 8001ea6: 2b01 cmp r3, #1 - 8001ea8: d10e bne.n 8001ec8 + 80029e0: 687b ldr r3, [r7, #4] + 80029e2: 681b ldr r3, [r3, #0] + 80029e4: 691b ldr r3, [r3, #16] + 80029e6: f003 0301 and.w r3, r3, #1 + 80029ea: 2b01 cmp r3, #1 + 80029ec: d10e bne.n 8002a0c { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET) - 8001eaa: 687b ldr r3, [r7, #4] - 8001eac: 681b ldr r3, [r3, #0] - 8001eae: 68db ldr r3, [r3, #12] - 8001eb0: f003 0301 and.w r3, r3, #1 - 8001eb4: 2b01 cmp r3, #1 - 8001eb6: d107 bne.n 8001ec8 + 80029ee: 687b ldr r3, [r7, #4] + 80029f0: 681b ldr r3, [r3, #0] + 80029f2: 68db ldr r3, [r3, #12] + 80029f4: f003 0301 and.w r3, r3, #1 + 80029f8: 2b01 cmp r3, #1 + 80029fa: d107 bne.n 8002a0c { __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - 8001eb8: 687b ldr r3, [r7, #4] - 8001eba: 681b ldr r3, [r3, #0] - 8001ebc: f06f 0201 mvn.w r2, #1 - 8001ec0: 611a str r2, [r3, #16] + 80029fc: 687b ldr r3, [r7, #4] + 80029fe: 681b ldr r3, [r3, #0] + 8002a00: f06f 0201 mvn.w r2, #1 + 8002a04: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); - 8001ec2: 6878 ldr r0, [r7, #4] - 8001ec4: f7fe fd84 bl 80009d0 + 8002a06: 6878 ldr r0, [r7, #4] + 8002a08: f7fe f8c2 bl 8000b90 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET) - 8001ec8: 687b ldr r3, [r7, #4] - 8001eca: 681b ldr r3, [r3, #0] - 8001ecc: 691b ldr r3, [r3, #16] - 8001ece: f003 0380 and.w r3, r3, #128 ; 0x80 - 8001ed2: 2b80 cmp r3, #128 ; 0x80 - 8001ed4: d10e bne.n 8001ef4 + 8002a0c: 687b ldr r3, [r7, #4] + 8002a0e: 681b ldr r3, [r3, #0] + 8002a10: 691b ldr r3, [r3, #16] + 8002a12: f003 0380 and.w r3, r3, #128 ; 0x80 + 8002a16: 2b80 cmp r3, #128 ; 0x80 + 8002a18: d10e bne.n 8002a38 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET) - 8001ed6: 687b ldr r3, [r7, #4] - 8001ed8: 681b ldr r3, [r3, #0] - 8001eda: 68db ldr r3, [r3, #12] - 8001edc: f003 0380 and.w r3, r3, #128 ; 0x80 - 8001ee0: 2b80 cmp r3, #128 ; 0x80 - 8001ee2: d107 bne.n 8001ef4 + 8002a1a: 687b ldr r3, [r7, #4] + 8002a1c: 681b ldr r3, [r3, #0] + 8002a1e: 68db ldr r3, [r3, #12] + 8002a20: f003 0380 and.w r3, r3, #128 ; 0x80 + 8002a24: 2b80 cmp r3, #128 ; 0x80 + 8002a26: d107 bne.n 8002a38 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK); - 8001ee4: 687b ldr r3, [r7, #4] - 8001ee6: 681b ldr r3, [r3, #0] - 8001ee8: f06f 0280 mvn.w r2, #128 ; 0x80 - 8001eec: 611a str r2, [r3, #16] + 8002a28: 687b ldr r3, [r7, #4] + 8002a2a: 681b ldr r3, [r3, #0] + 8002a2c: f06f 0280 mvn.w r2, #128 ; 0x80 + 8002a30: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); - 8001eee: 6878 ldr r0, [r7, #4] - 8001ef0: f000 f8e2 bl 80020b8 + 8002a32: 6878 ldr r0, [r7, #4] + 8002a34: f000 f8e2 bl 8002bfc #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - 8001ef4: 687b ldr r3, [r7, #4] - 8001ef6: 681b ldr r3, [r3, #0] - 8001ef8: 691b ldr r3, [r3, #16] - 8001efa: f003 0340 and.w r3, r3, #64 ; 0x40 - 8001efe: 2b40 cmp r3, #64 ; 0x40 - 8001f00: d10e bne.n 8001f20 + 8002a38: 687b ldr r3, [r7, #4] + 8002a3a: 681b ldr r3, [r3, #0] + 8002a3c: 691b ldr r3, [r3, #16] + 8002a3e: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002a42: 2b40 cmp r3, #64 ; 0x40 + 8002a44: d10e bne.n 8002a64 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET) - 8001f02: 687b ldr r3, [r7, #4] - 8001f04: 681b ldr r3, [r3, #0] - 8001f06: 68db ldr r3, [r3, #12] - 8001f08: f003 0340 and.w r3, r3, #64 ; 0x40 - 8001f0c: 2b40 cmp r3, #64 ; 0x40 - 8001f0e: d107 bne.n 8001f20 + 8002a46: 687b ldr r3, [r7, #4] + 8002a48: 681b ldr r3, [r3, #0] + 8002a4a: 68db ldr r3, [r3, #12] + 8002a4c: f003 0340 and.w r3, r3, #64 ; 0x40 + 8002a50: 2b40 cmp r3, #64 ; 0x40 + 8002a52: d107 bne.n 8002a64 { __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - 8001f10: 687b ldr r3, [r7, #4] - 8001f12: 681b ldr r3, [r3, #0] - 8001f14: f06f 0240 mvn.w r2, #64 ; 0x40 - 8001f18: 611a str r2, [r3, #16] + 8002a54: 687b ldr r3, [r7, #4] + 8002a56: 681b ldr r3, [r3, #0] + 8002a58: f06f 0240 mvn.w r2, #64 ; 0x40 + 8002a5c: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); - 8001f1a: 6878 ldr r0, [r7, #4] - 8001f1c: f000 f838 bl 8001f90 + 8002a5e: 6878 ldr r0, [r7, #4] + 8002a60: f000 f838 bl 8002ad4 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET) - 8001f20: 687b ldr r3, [r7, #4] - 8001f22: 681b ldr r3, [r3, #0] - 8001f24: 691b ldr r3, [r3, #16] - 8001f26: f003 0320 and.w r3, r3, #32 - 8001f2a: 2b20 cmp r3, #32 - 8001f2c: d10e bne.n 8001f4c + 8002a64: 687b ldr r3, [r7, #4] + 8002a66: 681b ldr r3, [r3, #0] + 8002a68: 691b ldr r3, [r3, #16] + 8002a6a: f003 0320 and.w r3, r3, #32 + 8002a6e: 2b20 cmp r3, #32 + 8002a70: d10e bne.n 8002a90 { if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET) - 8001f2e: 687b ldr r3, [r7, #4] - 8001f30: 681b ldr r3, [r3, #0] - 8001f32: 68db ldr r3, [r3, #12] - 8001f34: f003 0320 and.w r3, r3, #32 - 8001f38: 2b20 cmp r3, #32 - 8001f3a: d107 bne.n 8001f4c + 8002a72: 687b ldr r3, [r7, #4] + 8002a74: 681b ldr r3, [r3, #0] + 8002a76: 68db ldr r3, [r3, #12] + 8002a78: f003 0320 and.w r3, r3, #32 + 8002a7c: 2b20 cmp r3, #32 + 8002a7e: d107 bne.n 8002a90 { __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM); - 8001f3c: 687b ldr r3, [r7, #4] - 8001f3e: 681b ldr r3, [r3, #0] - 8001f40: f06f 0220 mvn.w r2, #32 - 8001f44: 611a str r2, [r3, #16] + 8002a80: 687b ldr r3, [r7, #4] + 8002a82: 681b ldr r3, [r3, #0] + 8002a84: f06f 0220 mvn.w r2, #32 + 8002a88: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); - 8001f46: 6878 ldr r0, [r7, #4] - 8001f48: f000 f8ac bl 80020a4 + 8002a8a: 6878 ldr r0, [r7, #4] + 8002a8c: f000 f8ac bl 8002be8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } - 8001f4c: bf00 nop - 8001f4e: 3708 adds r7, #8 - 8001f50: 46bd mov sp, r7 - 8001f52: bd80 pop {r7, pc} + 8002a90: bf00 nop + 8002a92: 3708 adds r7, #8 + 8002a94: 46bd mov sp, r7 + 8002a96: bd80 pop {r7, pc} -08001f54 : +08002a98 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { - 8001f54: b480 push {r7} - 8001f56: b083 sub sp, #12 - 8001f58: af00 add r7, sp, #0 - 8001f5a: 6078 str r0, [r7, #4] + 8002a98: b480 push {r7} + 8002a9a: b083 sub sp, #12 + 8002a9c: af00 add r7, sp, #0 + 8002a9e: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } - 8001f5c: bf00 nop - 8001f5e: 370c adds r7, #12 - 8001f60: 46bd mov sp, r7 - 8001f62: f85d 7b04 ldr.w r7, [sp], #4 - 8001f66: 4770 bx lr + 8002aa0: bf00 nop + 8002aa2: 370c adds r7, #12 + 8002aa4: 46bd mov sp, r7 + 8002aa6: f85d 7b04 ldr.w r7, [sp], #4 + 8002aaa: 4770 bx lr -08001f68 : +08002aac : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { - 8001f68: b480 push {r7} - 8001f6a: b083 sub sp, #12 - 8001f6c: af00 add r7, sp, #0 - 8001f6e: 6078 str r0, [r7, #4] + 8002aac: b480 push {r7} + 8002aae: b083 sub sp, #12 + 8002ab0: af00 add r7, sp, #0 + 8002ab2: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } - 8001f70: bf00 nop - 8001f72: 370c adds r7, #12 - 8001f74: 46bd mov sp, r7 - 8001f76: f85d 7b04 ldr.w r7, [sp], #4 - 8001f7a: 4770 bx lr + 8002ab4: bf00 nop + 8002ab6: 370c adds r7, #12 + 8002ab8: 46bd mov sp, r7 + 8002aba: f85d 7b04 ldr.w r7, [sp], #4 + 8002abe: 4770 bx lr -08001f7c : +08002ac0 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { - 8001f7c: b480 push {r7} - 8001f7e: b083 sub sp, #12 - 8001f80: af00 add r7, sp, #0 - 8001f82: 6078 str r0, [r7, #4] + 8002ac0: b480 push {r7} + 8002ac2: b083 sub sp, #12 + 8002ac4: af00 add r7, sp, #0 + 8002ac6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } - 8001f84: bf00 nop - 8001f86: 370c adds r7, #12 - 8001f88: 46bd mov sp, r7 - 8001f8a: f85d 7b04 ldr.w r7, [sp], #4 - 8001f8e: 4770 bx lr + 8002ac8: bf00 nop + 8002aca: 370c adds r7, #12 + 8002acc: 46bd mov sp, r7 + 8002ace: f85d 7b04 ldr.w r7, [sp], #4 + 8002ad2: 4770 bx lr -08001f90 : +08002ad4 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { - 8001f90: b480 push {r7} - 8001f92: b083 sub sp, #12 - 8001f94: af00 add r7, sp, #0 - 8001f96: 6078 str r0, [r7, #4] + 8002ad4: b480 push {r7} + 8002ad6: b083 sub sp, #12 + 8002ad8: af00 add r7, sp, #0 + 8002ada: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } - 8001f98: bf00 nop - 8001f9a: 370c adds r7, #12 - 8001f9c: 46bd mov sp, r7 - 8001f9e: f85d 7b04 ldr.w r7, [sp], #4 - 8001fa2: 4770 bx lr + 8002adc: bf00 nop + 8002ade: 370c adds r7, #12 + 8002ae0: 46bd mov sp, r7 + 8002ae2: f85d 7b04 ldr.w r7, [sp], #4 + 8002ae6: 4770 bx lr -08001fa4 : +08002ae8 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) { - 8001fa4: b480 push {r7} - 8001fa6: b085 sub sp, #20 - 8001fa8: af00 add r7, sp, #0 - 8001faa: 6078 str r0, [r7, #4] - 8001fac: 6039 str r1, [r7, #0] + 8002ae8: b480 push {r7} + 8002aea: b085 sub sp, #20 + 8002aec: af00 add r7, sp, #0 + 8002aee: 6078 str r0, [r7, #4] + 8002af0: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; - 8001fae: 687b ldr r3, [r7, #4] - 8001fb0: 681b ldr r3, [r3, #0] - 8001fb2: 60fb str r3, [r7, #12] + 8002af2: 687b ldr r3, [r7, #4] + 8002af4: 681b ldr r3, [r3, #0] + 8002af6: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - 8001fb4: 687b ldr r3, [r7, #4] - 8001fb6: 4a34 ldr r2, [pc, #208] ; (8002088 ) - 8001fb8: 4293 cmp r3, r2 - 8001fba: d00f beq.n 8001fdc - 8001fbc: 687b ldr r3, [r7, #4] - 8001fbe: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 - 8001fc2: d00b beq.n 8001fdc - 8001fc4: 687b ldr r3, [r7, #4] - 8001fc6: 4a31 ldr r2, [pc, #196] ; (800208c ) - 8001fc8: 4293 cmp r3, r2 - 8001fca: d007 beq.n 8001fdc - 8001fcc: 687b ldr r3, [r7, #4] - 8001fce: 4a30 ldr r2, [pc, #192] ; (8002090 ) - 8001fd0: 4293 cmp r3, r2 - 8001fd2: d003 beq.n 8001fdc - 8001fd4: 687b ldr r3, [r7, #4] - 8001fd6: 4a2f ldr r2, [pc, #188] ; (8002094 ) - 8001fd8: 4293 cmp r3, r2 - 8001fda: d108 bne.n 8001fee + 8002af8: 687b ldr r3, [r7, #4] + 8002afa: 4a34 ldr r2, [pc, #208] ; (8002bcc ) + 8002afc: 4293 cmp r3, r2 + 8002afe: d00f beq.n 8002b20 + 8002b00: 687b ldr r3, [r7, #4] + 8002b02: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8002b06: d00b beq.n 8002b20 + 8002b08: 687b ldr r3, [r7, #4] + 8002b0a: 4a31 ldr r2, [pc, #196] ; (8002bd0 ) + 8002b0c: 4293 cmp r3, r2 + 8002b0e: d007 beq.n 8002b20 + 8002b10: 687b ldr r3, [r7, #4] + 8002b12: 4a30 ldr r2, [pc, #192] ; (8002bd4 ) + 8002b14: 4293 cmp r3, r2 + 8002b16: d003 beq.n 8002b20 + 8002b18: 687b ldr r3, [r7, #4] + 8002b1a: 4a2f ldr r2, [pc, #188] ; (8002bd8 ) + 8002b1c: 4293 cmp r3, r2 + 8002b1e: d108 bne.n 8002b32 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - 8001fdc: 68fb ldr r3, [r7, #12] - 8001fde: f023 0370 bic.w r3, r3, #112 ; 0x70 - 8001fe2: 60fb str r3, [r7, #12] + 8002b20: 68fb ldr r3, [r7, #12] + 8002b22: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8002b26: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; - 8001fe4: 683b ldr r3, [r7, #0] - 8001fe6: 685b ldr r3, [r3, #4] - 8001fe8: 68fa ldr r2, [r7, #12] - 8001fea: 4313 orrs r3, r2 - 8001fec: 60fb str r3, [r7, #12] + 8002b28: 683b ldr r3, [r7, #0] + 8002b2a: 685b ldr r3, [r3, #4] + 8002b2c: 68fa ldr r2, [r7, #12] + 8002b2e: 4313 orrs r3, r2 + 8002b30: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - 8001fee: 687b ldr r3, [r7, #4] - 8001ff0: 4a25 ldr r2, [pc, #148] ; (8002088 ) - 8001ff2: 4293 cmp r3, r2 - 8001ff4: d01b beq.n 800202e - 8001ff6: 687b ldr r3, [r7, #4] - 8001ff8: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 - 8001ffc: d017 beq.n 800202e - 8001ffe: 687b ldr r3, [r7, #4] - 8002000: 4a22 ldr r2, [pc, #136] ; (800208c ) - 8002002: 4293 cmp r3, r2 - 8002004: d013 beq.n 800202e - 8002006: 687b ldr r3, [r7, #4] - 8002008: 4a21 ldr r2, [pc, #132] ; (8002090 ) - 800200a: 4293 cmp r3, r2 - 800200c: d00f beq.n 800202e - 800200e: 687b ldr r3, [r7, #4] - 8002010: 4a20 ldr r2, [pc, #128] ; (8002094 ) - 8002012: 4293 cmp r3, r2 - 8002014: d00b beq.n 800202e - 8002016: 687b ldr r3, [r7, #4] - 8002018: 4a1f ldr r2, [pc, #124] ; (8002098 ) - 800201a: 4293 cmp r3, r2 - 800201c: d007 beq.n 800202e - 800201e: 687b ldr r3, [r7, #4] - 8002020: 4a1e ldr r2, [pc, #120] ; (800209c ) - 8002022: 4293 cmp r3, r2 - 8002024: d003 beq.n 800202e - 8002026: 687b ldr r3, [r7, #4] - 8002028: 4a1d ldr r2, [pc, #116] ; (80020a0 ) - 800202a: 4293 cmp r3, r2 - 800202c: d108 bne.n 8002040 + 8002b32: 687b ldr r3, [r7, #4] + 8002b34: 4a25 ldr r2, [pc, #148] ; (8002bcc ) + 8002b36: 4293 cmp r3, r2 + 8002b38: d01b beq.n 8002b72 + 8002b3a: 687b ldr r3, [r7, #4] + 8002b3c: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8002b40: d017 beq.n 8002b72 + 8002b42: 687b ldr r3, [r7, #4] + 8002b44: 4a22 ldr r2, [pc, #136] ; (8002bd0 ) + 8002b46: 4293 cmp r3, r2 + 8002b48: d013 beq.n 8002b72 + 8002b4a: 687b ldr r3, [r7, #4] + 8002b4c: 4a21 ldr r2, [pc, #132] ; (8002bd4 ) + 8002b4e: 4293 cmp r3, r2 + 8002b50: d00f beq.n 8002b72 + 8002b52: 687b ldr r3, [r7, #4] + 8002b54: 4a20 ldr r2, [pc, #128] ; (8002bd8 ) + 8002b56: 4293 cmp r3, r2 + 8002b58: d00b beq.n 8002b72 + 8002b5a: 687b ldr r3, [r7, #4] + 8002b5c: 4a1f ldr r2, [pc, #124] ; (8002bdc ) + 8002b5e: 4293 cmp r3, r2 + 8002b60: d007 beq.n 8002b72 + 8002b62: 687b ldr r3, [r7, #4] + 8002b64: 4a1e ldr r2, [pc, #120] ; (8002be0 ) + 8002b66: 4293 cmp r3, r2 + 8002b68: d003 beq.n 8002b72 + 8002b6a: 687b ldr r3, [r7, #4] + 8002b6c: 4a1d ldr r2, [pc, #116] ; (8002be4 ) + 8002b6e: 4293 cmp r3, r2 + 8002b70: d108 bne.n 8002b84 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; - 800202e: 68fb ldr r3, [r7, #12] - 8002030: f423 7340 bic.w r3, r3, #768 ; 0x300 - 8002034: 60fb str r3, [r7, #12] + 8002b72: 68fb ldr r3, [r7, #12] + 8002b74: f423 7340 bic.w r3, r3, #768 ; 0x300 + 8002b78: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; - 8002036: 683b ldr r3, [r7, #0] - 8002038: 68db ldr r3, [r3, #12] - 800203a: 68fa ldr r2, [r7, #12] - 800203c: 4313 orrs r3, r2 - 800203e: 60fb str r3, [r7, #12] + 8002b7a: 683b ldr r3, [r7, #0] + 8002b7c: 68db ldr r3, [r3, #12] + 8002b7e: 68fa ldr r2, [r7, #12] + 8002b80: 4313 orrs r3, r2 + 8002b82: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - 8002040: 68fb ldr r3, [r7, #12] - 8002042: f023 0280 bic.w r2, r3, #128 ; 0x80 - 8002046: 683b ldr r3, [r7, #0] - 8002048: 695b ldr r3, [r3, #20] - 800204a: 4313 orrs r3, r2 - 800204c: 60fb str r3, [r7, #12] + 8002b84: 68fb ldr r3, [r7, #12] + 8002b86: f023 0280 bic.w r2, r3, #128 ; 0x80 + 8002b8a: 683b ldr r3, [r7, #0] + 8002b8c: 695b ldr r3, [r3, #20] + 8002b8e: 4313 orrs r3, r2 + 8002b90: 60fb str r3, [r7, #12] TIMx->CR1 = tmpcr1; - 800204e: 687b ldr r3, [r7, #4] - 8002050: 68fa ldr r2, [r7, #12] - 8002052: 601a str r2, [r3, #0] + 8002b92: 687b ldr r3, [r7, #4] + 8002b94: 68fa ldr r2, [r7, #12] + 8002b96: 601a str r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; - 8002054: 683b ldr r3, [r7, #0] - 8002056: 689a ldr r2, [r3, #8] - 8002058: 687b ldr r3, [r7, #4] - 800205a: 62da str r2, [r3, #44] ; 0x2c + 8002b98: 683b ldr r3, [r7, #0] + 8002b9a: 689a ldr r2, [r3, #8] + 8002b9c: 687b ldr r3, [r7, #4] + 8002b9e: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; - 800205c: 683b ldr r3, [r7, #0] - 800205e: 681a ldr r2, [r3, #0] - 8002060: 687b ldr r3, [r7, #4] - 8002062: 629a str r2, [r3, #40] ; 0x28 + 8002ba0: 683b ldr r3, [r7, #0] + 8002ba2: 681a ldr r2, [r3, #0] + 8002ba4: 687b ldr r3, [r7, #4] + 8002ba6: 629a str r2, [r3, #40] ; 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - 8002064: 687b ldr r3, [r7, #4] - 8002066: 4a08 ldr r2, [pc, #32] ; (8002088 ) - 8002068: 4293 cmp r3, r2 - 800206a: d103 bne.n 8002074 + 8002ba8: 687b ldr r3, [r7, #4] + 8002baa: 4a08 ldr r2, [pc, #32] ; (8002bcc ) + 8002bac: 4293 cmp r3, r2 + 8002bae: d103 bne.n 8002bb8 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; - 800206c: 683b ldr r3, [r7, #0] - 800206e: 691a ldr r2, [r3, #16] - 8002070: 687b ldr r3, [r7, #4] - 8002072: 631a str r2, [r3, #48] ; 0x30 + 8002bb0: 683b ldr r3, [r7, #0] + 8002bb2: 691a ldr r2, [r3, #16] + 8002bb4: 687b ldr r3, [r7, #4] + 8002bb6: 631a str r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - 8002074: 687b ldr r3, [r7, #4] - 8002076: 2201 movs r2, #1 - 8002078: 615a str r2, [r3, #20] + 8002bb8: 687b ldr r3, [r7, #4] + 8002bba: 2201 movs r2, #1 + 8002bbc: 615a str r2, [r3, #20] } - 800207a: bf00 nop - 800207c: 3714 adds r7, #20 - 800207e: 46bd mov sp, r7 - 8002080: f85d 7b04 ldr.w r7, [sp], #4 - 8002084: 4770 bx lr - 8002086: bf00 nop - 8002088: 40010000 .word 0x40010000 - 800208c: 40000400 .word 0x40000400 - 8002090: 40000800 .word 0x40000800 - 8002094: 40000c00 .word 0x40000c00 - 8002098: 40014000 .word 0x40014000 - 800209c: 40014400 .word 0x40014400 - 80020a0: 40014800 .word 0x40014800 + 8002bbe: bf00 nop + 8002bc0: 3714 adds r7, #20 + 8002bc2: 46bd mov sp, r7 + 8002bc4: f85d 7b04 ldr.w r7, [sp], #4 + 8002bc8: 4770 bx lr + 8002bca: bf00 nop + 8002bcc: 40010000 .word 0x40010000 + 8002bd0: 40000400 .word 0x40000400 + 8002bd4: 40000800 .word 0x40000800 + 8002bd8: 40000c00 .word 0x40000c00 + 8002bdc: 40014000 .word 0x40014000 + 8002be0: 40014400 .word 0x40014400 + 8002be4: 40014800 .word 0x40014800 -080020a4 : +08002be8 : * @brief Hall commutation changed callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { - 80020a4: b480 push {r7} - 80020a6: b083 sub sp, #12 - 80020a8: af00 add r7, sp, #0 - 80020aa: 6078 str r0, [r7, #4] + 8002be8: b480 push {r7} + 8002bea: b083 sub sp, #12 + 8002bec: af00 add r7, sp, #0 + 8002bee: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } - 80020ac: bf00 nop - 80020ae: 370c adds r7, #12 - 80020b0: 46bd mov sp, r7 - 80020b2: f85d 7b04 ldr.w r7, [sp], #4 - 80020b6: 4770 bx lr + 8002bf0: bf00 nop + 8002bf2: 370c adds r7, #12 + 8002bf4: 46bd mov sp, r7 + 8002bf6: f85d 7b04 ldr.w r7, [sp], #4 + 8002bfa: 4770 bx lr -080020b8 : +08002bfc : * @brief Hall Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { - 80020b8: b480 push {r7} - 80020ba: b083 sub sp, #12 - 80020bc: af00 add r7, sp, #0 - 80020be: 6078 str r0, [r7, #4] + 8002bfc: b480 push {r7} + 8002bfe: b083 sub sp, #12 + 8002c00: af00 add r7, sp, #0 + 8002c02: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } - 80020c0: bf00 nop - 80020c2: 370c adds r7, #12 - 80020c4: 46bd mov sp, r7 - 80020c6: f85d 7b04 ldr.w r7, [sp], #4 - 80020ca: 4770 bx lr + 8002c04: bf00 nop + 8002c06: 370c adds r7, #12 + 8002c08: 46bd mov sp, r7 + 8002c0a: f85d 7b04 ldr.w r7, [sp], #4 + 8002c0e: 4770 bx lr -080020cc : +08002c10 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { - 80020cc: b580 push {r7, lr} - 80020ce: b082 sub sp, #8 - 80020d0: af00 add r7, sp, #0 - 80020d2: 6078 str r0, [r7, #4] + 8002c10: b580 push {r7, lr} + 8002c12: b082 sub sp, #8 + 8002c14: af00 add r7, sp, #0 + 8002c16: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) - 80020d4: 687b ldr r3, [r7, #4] - 80020d6: 2b00 cmp r3, #0 - 80020d8: d101 bne.n 80020de + 8002c18: 687b ldr r3, [r7, #4] + 8002c1a: 2b00 cmp r3, #0 + 8002c1c: d101 bne.n 8002c22 { return HAL_ERROR; - 80020da: 2301 movs r3, #1 - 80020dc: e03f b.n 800215e + 8002c1e: 2301 movs r3, #1 + 8002c20: e03f b.n 8002ca2 assert_param(IS_UART_INSTANCE(huart->Instance)); } assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); if (huart->gState == HAL_UART_STATE_RESET) - 80020de: 687b ldr r3, [r7, #4] - 80020e0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d - 80020e4: b2db uxtb r3, r3 - 80020e6: 2b00 cmp r3, #0 - 80020e8: d106 bne.n 80020f8 + 8002c22: 687b ldr r3, [r7, #4] + 8002c24: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8002c28: b2db uxtb r3, r3 + 8002c2a: 2b00 cmp r3, #0 + 8002c2c: d106 bne.n 8002c3c { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; - 80020ea: 687b ldr r3, [r7, #4] - 80020ec: 2200 movs r2, #0 - 80020ee: f883 203c strb.w r2, [r3, #60] ; 0x3c + 8002c2e: 687b ldr r3, [r7, #4] + 8002c30: 2200 movs r2, #0 + 8002c32: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); - 80020f2: 6878 ldr r0, [r7, #4] - 80020f4: f7fe fcb0 bl 8000a58 + 8002c36: 6878 ldr r0, [r7, #4] + 8002c38: f7fe f83a bl 8000cb0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; - 80020f8: 687b ldr r3, [r7, #4] - 80020fa: 2224 movs r2, #36 ; 0x24 - 80020fc: f883 203d strb.w r2, [r3, #61] ; 0x3d + 8002c3c: 687b ldr r3, [r7, #4] + 8002c3e: 2224 movs r2, #36 ; 0x24 + 8002c40: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Disable the peripheral */ __HAL_UART_DISABLE(huart); - 8002100: 687b ldr r3, [r7, #4] - 8002102: 681b ldr r3, [r3, #0] - 8002104: 68da ldr r2, [r3, #12] - 8002106: 687b ldr r3, [r7, #4] - 8002108: 681b ldr r3, [r3, #0] - 800210a: f422 5200 bic.w r2, r2, #8192 ; 0x2000 - 800210e: 60da str r2, [r3, #12] + 8002c44: 687b ldr r3, [r7, #4] + 8002c46: 681b ldr r3, [r3, #0] + 8002c48: 68da ldr r2, [r3, #12] + 8002c4a: 687b ldr r3, [r7, #4] + 8002c4c: 681b ldr r3, [r3, #0] + 8002c4e: f422 5200 bic.w r2, r2, #8192 ; 0x2000 + 8002c52: 60da str r2, [r3, #12] /* Set the UART Communication parameters */ UART_SetConfig(huart); - 8002110: 6878 ldr r0, [r7, #4] - 8002112: f000 f9cb bl 80024ac + 8002c54: 6878 ldr r0, [r7, #4] + 8002c56: f000 f9cb bl 8002ff0 /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - 8002116: 687b ldr r3, [r7, #4] - 8002118: 681b ldr r3, [r3, #0] - 800211a: 691a ldr r2, [r3, #16] - 800211c: 687b ldr r3, [r7, #4] - 800211e: 681b ldr r3, [r3, #0] - 8002120: f422 4290 bic.w r2, r2, #18432 ; 0x4800 - 8002124: 611a str r2, [r3, #16] + 8002c5a: 687b ldr r3, [r7, #4] + 8002c5c: 681b ldr r3, [r3, #0] + 8002c5e: 691a ldr r2, [r3, #16] + 8002c60: 687b ldr r3, [r7, #4] + 8002c62: 681b ldr r3, [r3, #0] + 8002c64: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8002c68: 611a str r2, [r3, #16] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - 8002126: 687b ldr r3, [r7, #4] - 8002128: 681b ldr r3, [r3, #0] - 800212a: 695a ldr r2, [r3, #20] - 800212c: 687b ldr r3, [r7, #4] - 800212e: 681b ldr r3, [r3, #0] - 8002130: f022 022a bic.w r2, r2, #42 ; 0x2a - 8002134: 615a str r2, [r3, #20] + 8002c6a: 687b ldr r3, [r7, #4] + 8002c6c: 681b ldr r3, [r3, #0] + 8002c6e: 695a ldr r2, [r3, #20] + 8002c70: 687b ldr r3, [r7, #4] + 8002c72: 681b ldr r3, [r3, #0] + 8002c74: f022 022a bic.w r2, r2, #42 ; 0x2a + 8002c78: 615a str r2, [r3, #20] /* Enable the peripheral */ __HAL_UART_ENABLE(huart); - 8002136: 687b ldr r3, [r7, #4] - 8002138: 681b ldr r3, [r3, #0] - 800213a: 68da ldr r2, [r3, #12] - 800213c: 687b ldr r3, [r7, #4] - 800213e: 681b ldr r3, [r3, #0] - 8002140: f442 5200 orr.w r2, r2, #8192 ; 0x2000 - 8002144: 60da str r2, [r3, #12] + 8002c7a: 687b ldr r3, [r7, #4] + 8002c7c: 681b ldr r3, [r3, #0] + 8002c7e: 68da ldr r2, [r3, #12] + 8002c80: 687b ldr r3, [r7, #4] + 8002c82: 681b ldr r3, [r3, #0] + 8002c84: f442 5200 orr.w r2, r2, #8192 ; 0x2000 + 8002c88: 60da str r2, [r3, #12] /* Initialize the UART state */ huart->ErrorCode = HAL_UART_ERROR_NONE; - 8002146: 687b ldr r3, [r7, #4] - 8002148: 2200 movs r2, #0 - 800214a: 641a str r2, [r3, #64] ; 0x40 + 8002c8a: 687b ldr r3, [r7, #4] + 8002c8c: 2200 movs r2, #0 + 8002c8e: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_READY; - 800214c: 687b ldr r3, [r7, #4] - 800214e: 2220 movs r2, #32 - 8002150: f883 203d strb.w r2, [r3, #61] ; 0x3d + 8002c90: 687b ldr r3, [r7, #4] + 8002c92: 2220 movs r2, #32 + 8002c94: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; - 8002154: 687b ldr r3, [r7, #4] - 8002156: 2220 movs r2, #32 - 8002158: f883 203e strb.w r2, [r3, #62] ; 0x3e + 8002c98: 687b ldr r3, [r7, #4] + 8002c9a: 2220 movs r2, #32 + 8002c9c: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; - 800215c: 2300 movs r3, #0 + 8002ca0: 2300 movs r3, #0 } - 800215e: 4618 mov r0, r3 - 8002160: 3708 adds r7, #8 - 8002162: 46bd mov sp, r7 - 8002164: bd80 pop {r7, pc} + 8002ca2: 4618 mov r0, r3 + 8002ca4: 3708 adds r7, #8 + 8002ca6: 46bd mov sp, r7 + 8002ca8: bd80 pop {r7, pc} -08002166 : +08002caa : * @param Size Amount of data elements (u8 or u16) to be sent * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - 8002166: b580 push {r7, lr} - 8002168: b08a sub sp, #40 ; 0x28 - 800216a: af02 add r7, sp, #8 - 800216c: 60f8 str r0, [r7, #12] - 800216e: 60b9 str r1, [r7, #8] - 8002170: 603b str r3, [r7, #0] - 8002172: 4613 mov r3, r2 - 8002174: 80fb strh r3, [r7, #6] + 8002caa: b580 push {r7, lr} + 8002cac: b08a sub sp, #40 ; 0x28 + 8002cae: af02 add r7, sp, #8 + 8002cb0: 60f8 str r0, [r7, #12] + 8002cb2: 60b9 str r1, [r7, #8] + 8002cb4: 603b str r3, [r7, #0] + 8002cb6: 4613 mov r3, r2 + 8002cb8: 80fb strh r3, [r7, #6] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart = 0U; - 8002176: 2300 movs r3, #0 - 8002178: 617b str r3, [r7, #20] + 8002cba: 2300 movs r3, #0 + 8002cbc: 617b str r3, [r7, #20] /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) - 800217a: 68fb ldr r3, [r7, #12] - 800217c: f893 303d ldrb.w r3, [r3, #61] ; 0x3d - 8002180: b2db uxtb r3, r3 - 8002182: 2b20 cmp r3, #32 - 8002184: d17c bne.n 8002280 + 8002cbe: 68fb ldr r3, [r7, #12] + 8002cc0: f893 303d ldrb.w r3, [r3, #61] ; 0x3d + 8002cc4: b2db uxtb r3, r3 + 8002cc6: 2b20 cmp r3, #32 + 8002cc8: d17c bne.n 8002dc4 { if ((pData == NULL) || (Size == 0U)) - 8002186: 68bb ldr r3, [r7, #8] - 8002188: 2b00 cmp r3, #0 - 800218a: d002 beq.n 8002192 - 800218c: 88fb ldrh r3, [r7, #6] - 800218e: 2b00 cmp r3, #0 - 8002190: d101 bne.n 8002196 + 8002cca: 68bb ldr r3, [r7, #8] + 8002ccc: 2b00 cmp r3, #0 + 8002cce: d002 beq.n 8002cd6 + 8002cd0: 88fb ldrh r3, [r7, #6] + 8002cd2: 2b00 cmp r3, #0 + 8002cd4: d101 bne.n 8002cda { return HAL_ERROR; - 8002192: 2301 movs r3, #1 - 8002194: e075 b.n 8002282 + 8002cd6: 2301 movs r3, #1 + 8002cd8: e075 b.n 8002dc6 } /* Process Locked */ __HAL_LOCK(huart); - 8002196: 68fb ldr r3, [r7, #12] - 8002198: f893 303c ldrb.w r3, [r3, #60] ; 0x3c - 800219c: 2b01 cmp r3, #1 - 800219e: d101 bne.n 80021a4 - 80021a0: 2302 movs r3, #2 - 80021a2: e06e b.n 8002282 - 80021a4: 68fb ldr r3, [r7, #12] - 80021a6: 2201 movs r2, #1 - 80021a8: f883 203c strb.w r2, [r3, #60] ; 0x3c + 8002cda: 68fb ldr r3, [r7, #12] + 8002cdc: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8002ce0: 2b01 cmp r3, #1 + 8002ce2: d101 bne.n 8002ce8 + 8002ce4: 2302 movs r3, #2 + 8002ce6: e06e b.n 8002dc6 + 8002ce8: 68fb ldr r3, [r7, #12] + 8002cea: 2201 movs r2, #1 + 8002cec: f883 203c strb.w r2, [r3, #60] ; 0x3c huart->ErrorCode = HAL_UART_ERROR_NONE; - 80021ac: 68fb ldr r3, [r7, #12] - 80021ae: 2200 movs r2, #0 - 80021b0: 641a str r2, [r3, #64] ; 0x40 + 8002cf0: 68fb ldr r3, [r7, #12] + 8002cf2: 2200 movs r2, #0 + 8002cf4: 641a str r2, [r3, #64] ; 0x40 huart->gState = HAL_UART_STATE_BUSY_TX; - 80021b2: 68fb ldr r3, [r7, #12] - 80021b4: 2221 movs r2, #33 ; 0x21 - 80021b6: f883 203d strb.w r2, [r3, #61] ; 0x3d + 8002cf6: 68fb ldr r3, [r7, #12] + 8002cf8: 2221 movs r2, #33 ; 0x21 + 8002cfa: f883 203d strb.w r2, [r3, #61] ; 0x3d /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 80021ba: f7fe fd99 bl 8000cf0 - 80021be: 6178 str r0, [r7, #20] + 8002cfe: f7fe f92d bl 8000f5c + 8002d02: 6178 str r0, [r7, #20] huart->TxXferSize = Size; - 80021c0: 68fb ldr r3, [r7, #12] - 80021c2: 88fa ldrh r2, [r7, #6] - 80021c4: 849a strh r2, [r3, #36] ; 0x24 + 8002d04: 68fb ldr r3, [r7, #12] + 8002d06: 88fa ldrh r2, [r7, #6] + 8002d08: 849a strh r2, [r3, #36] ; 0x24 huart->TxXferCount = Size; - 80021c6: 68fb ldr r3, [r7, #12] - 80021c8: 88fa ldrh r2, [r7, #6] - 80021ca: 84da strh r2, [r3, #38] ; 0x26 + 8002d0a: 68fb ldr r3, [r7, #12] + 8002d0c: 88fa ldrh r2, [r7, #6] + 8002d0e: 84da strh r2, [r3, #38] ; 0x26 /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 80021cc: 68fb ldr r3, [r7, #12] - 80021ce: 689b ldr r3, [r3, #8] - 80021d0: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 80021d4: d108 bne.n 80021e8 - 80021d6: 68fb ldr r3, [r7, #12] - 80021d8: 691b ldr r3, [r3, #16] - 80021da: 2b00 cmp r3, #0 - 80021dc: d104 bne.n 80021e8 + 8002d10: 68fb ldr r3, [r7, #12] + 8002d12: 689b ldr r3, [r3, #8] + 8002d14: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8002d18: d108 bne.n 8002d2c + 8002d1a: 68fb ldr r3, [r7, #12] + 8002d1c: 691b ldr r3, [r3, #16] + 8002d1e: 2b00 cmp r3, #0 + 8002d20: d104 bne.n 8002d2c { pdata8bits = NULL; - 80021de: 2300 movs r3, #0 - 80021e0: 61fb str r3, [r7, #28] + 8002d22: 2300 movs r3, #0 + 8002d24: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; - 80021e2: 68bb ldr r3, [r7, #8] - 80021e4: 61bb str r3, [r7, #24] - 80021e6: e003 b.n 80021f0 + 8002d26: 68bb ldr r3, [r7, #8] + 8002d28: 61bb str r3, [r7, #24] + 8002d2a: e003 b.n 8002d34 } else { pdata8bits = pData; - 80021e8: 68bb ldr r3, [r7, #8] - 80021ea: 61fb str r3, [r7, #28] + 8002d2c: 68bb ldr r3, [r7, #8] + 8002d2e: 61fb str r3, [r7, #28] pdata16bits = NULL; - 80021ec: 2300 movs r3, #0 - 80021ee: 61bb str r3, [r7, #24] + 8002d30: 2300 movs r3, #0 + 8002d32: 61bb str r3, [r7, #24] } /* Process Unlocked */ __HAL_UNLOCK(huart); - 80021f0: 68fb ldr r3, [r7, #12] - 80021f2: 2200 movs r2, #0 - 80021f4: f883 203c strb.w r2, [r3, #60] ; 0x3c + 8002d34: 68fb ldr r3, [r7, #12] + 8002d36: 2200 movs r2, #0 + 8002d38: f883 203c strb.w r2, [r3, #60] ; 0x3c while (huart->TxXferCount > 0U) - 80021f8: e02a b.n 8002250 + 8002d3c: e02a b.n 8002d94 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - 80021fa: 683b ldr r3, [r7, #0] - 80021fc: 9300 str r3, [sp, #0] - 80021fe: 697b ldr r3, [r7, #20] - 8002200: 2200 movs r2, #0 - 8002202: 2180 movs r1, #128 ; 0x80 - 8002204: 68f8 ldr r0, [r7, #12] - 8002206: f000 f8e2 bl 80023ce - 800220a: 4603 mov r3, r0 - 800220c: 2b00 cmp r3, #0 - 800220e: d001 beq.n 8002214 + 8002d3e: 683b ldr r3, [r7, #0] + 8002d40: 9300 str r3, [sp, #0] + 8002d42: 697b ldr r3, [r7, #20] + 8002d44: 2200 movs r2, #0 + 8002d46: 2180 movs r1, #128 ; 0x80 + 8002d48: 68f8 ldr r0, [r7, #12] + 8002d4a: f000 f8e2 bl 8002f12 + 8002d4e: 4603 mov r3, r0 + 8002d50: 2b00 cmp r3, #0 + 8002d52: d001 beq.n 8002d58 { return HAL_TIMEOUT; - 8002210: 2303 movs r3, #3 - 8002212: e036 b.n 8002282 + 8002d54: 2303 movs r3, #3 + 8002d56: e036 b.n 8002dc6 } if (pdata8bits == NULL) - 8002214: 69fb ldr r3, [r7, #28] - 8002216: 2b00 cmp r3, #0 - 8002218: d10b bne.n 8002232 + 8002d58: 69fb ldr r3, [r7, #28] + 8002d5a: 2b00 cmp r3, #0 + 8002d5c: d10b bne.n 8002d76 { huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU); - 800221a: 69bb ldr r3, [r7, #24] - 800221c: 881b ldrh r3, [r3, #0] - 800221e: 461a mov r2, r3 - 8002220: 68fb ldr r3, [r7, #12] - 8002222: 681b ldr r3, [r3, #0] - 8002224: f3c2 0208 ubfx r2, r2, #0, #9 - 8002228: 605a str r2, [r3, #4] + 8002d5e: 69bb ldr r3, [r7, #24] + 8002d60: 881b ldrh r3, [r3, #0] + 8002d62: 461a mov r2, r3 + 8002d64: 68fb ldr r3, [r7, #12] + 8002d66: 681b ldr r3, [r3, #0] + 8002d68: f3c2 0208 ubfx r2, r2, #0, #9 + 8002d6c: 605a str r2, [r3, #4] pdata16bits++; - 800222a: 69bb ldr r3, [r7, #24] - 800222c: 3302 adds r3, #2 - 800222e: 61bb str r3, [r7, #24] - 8002230: e007 b.n 8002242 + 8002d6e: 69bb ldr r3, [r7, #24] + 8002d70: 3302 adds r3, #2 + 8002d72: 61bb str r3, [r7, #24] + 8002d74: e007 b.n 8002d86 } else { huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU); - 8002232: 69fb ldr r3, [r7, #28] - 8002234: 781a ldrb r2, [r3, #0] - 8002236: 68fb ldr r3, [r7, #12] - 8002238: 681b ldr r3, [r3, #0] - 800223a: 605a str r2, [r3, #4] + 8002d76: 69fb ldr r3, [r7, #28] + 8002d78: 781a ldrb r2, [r3, #0] + 8002d7a: 68fb ldr r3, [r7, #12] + 8002d7c: 681b ldr r3, [r3, #0] + 8002d7e: 605a str r2, [r3, #4] pdata8bits++; - 800223c: 69fb ldr r3, [r7, #28] - 800223e: 3301 adds r3, #1 - 8002240: 61fb str r3, [r7, #28] + 8002d80: 69fb ldr r3, [r7, #28] + 8002d82: 3301 adds r3, #1 + 8002d84: 61fb str r3, [r7, #28] } huart->TxXferCount--; - 8002242: 68fb ldr r3, [r7, #12] - 8002244: 8cdb ldrh r3, [r3, #38] ; 0x26 - 8002246: b29b uxth r3, r3 - 8002248: 3b01 subs r3, #1 - 800224a: b29a uxth r2, r3 - 800224c: 68fb ldr r3, [r7, #12] - 800224e: 84da strh r2, [r3, #38] ; 0x26 + 8002d86: 68fb ldr r3, [r7, #12] + 8002d88: 8cdb ldrh r3, [r3, #38] ; 0x26 + 8002d8a: b29b uxth r3, r3 + 8002d8c: 3b01 subs r3, #1 + 8002d8e: b29a uxth r2, r3 + 8002d90: 68fb ldr r3, [r7, #12] + 8002d92: 84da strh r2, [r3, #38] ; 0x26 while (huart->TxXferCount > 0U) - 8002250: 68fb ldr r3, [r7, #12] - 8002252: 8cdb ldrh r3, [r3, #38] ; 0x26 - 8002254: b29b uxth r3, r3 - 8002256: 2b00 cmp r3, #0 - 8002258: d1cf bne.n 80021fa + 8002d94: 68fb ldr r3, [r7, #12] + 8002d96: 8cdb ldrh r3, [r3, #38] ; 0x26 + 8002d98: b29b uxth r3, r3 + 8002d9a: 2b00 cmp r3, #0 + 8002d9c: d1cf bne.n 8002d3e } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - 800225a: 683b ldr r3, [r7, #0] - 800225c: 9300 str r3, [sp, #0] - 800225e: 697b ldr r3, [r7, #20] - 8002260: 2200 movs r2, #0 - 8002262: 2140 movs r1, #64 ; 0x40 - 8002264: 68f8 ldr r0, [r7, #12] - 8002266: f000 f8b2 bl 80023ce - 800226a: 4603 mov r3, r0 - 800226c: 2b00 cmp r3, #0 - 800226e: d001 beq.n 8002274 + 8002d9e: 683b ldr r3, [r7, #0] + 8002da0: 9300 str r3, [sp, #0] + 8002da2: 697b ldr r3, [r7, #20] + 8002da4: 2200 movs r2, #0 + 8002da6: 2140 movs r1, #64 ; 0x40 + 8002da8: 68f8 ldr r0, [r7, #12] + 8002daa: f000 f8b2 bl 8002f12 + 8002dae: 4603 mov r3, r0 + 8002db0: 2b00 cmp r3, #0 + 8002db2: d001 beq.n 8002db8 { return HAL_TIMEOUT; - 8002270: 2303 movs r3, #3 - 8002272: e006 b.n 8002282 + 8002db4: 2303 movs r3, #3 + 8002db6: e006 b.n 8002dc6 } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; - 8002274: 68fb ldr r3, [r7, #12] - 8002276: 2220 movs r2, #32 - 8002278: f883 203d strb.w r2, [r3, #61] ; 0x3d + 8002db8: 68fb ldr r3, [r7, #12] + 8002dba: 2220 movs r2, #32 + 8002dbc: f883 203d strb.w r2, [r3, #61] ; 0x3d return HAL_OK; - 800227c: 2300 movs r3, #0 - 800227e: e000 b.n 8002282 + 8002dc0: 2300 movs r3, #0 + 8002dc2: e000 b.n 8002dc6 } else { return HAL_BUSY; - 8002280: 2302 movs r3, #2 + 8002dc4: 2302 movs r3, #2 } } - 8002282: 4618 mov r0, r3 - 8002284: 3720 adds r7, #32 - 8002286: 46bd mov sp, r7 - 8002288: bd80 pop {r7, pc} + 8002dc6: 4618 mov r0, r3 + 8002dc8: 3720 adds r7, #32 + 8002dca: 46bd mov sp, r7 + 8002dcc: bd80 pop {r7, pc} -0800228a : +08002dce : * @param Size Amount of data elements (u8 or u16) to be received. * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - 800228a: b580 push {r7, lr} - 800228c: b08a sub sp, #40 ; 0x28 - 800228e: af02 add r7, sp, #8 - 8002290: 60f8 str r0, [r7, #12] - 8002292: 60b9 str r1, [r7, #8] - 8002294: 603b str r3, [r7, #0] - 8002296: 4613 mov r3, r2 - 8002298: 80fb strh r3, [r7, #6] + 8002dce: b580 push {r7, lr} + 8002dd0: b08a sub sp, #40 ; 0x28 + 8002dd2: af02 add r7, sp, #8 + 8002dd4: 60f8 str r0, [r7, #12] + 8002dd6: 60b9 str r1, [r7, #8] + 8002dd8: 603b str r3, [r7, #0] + 8002dda: 4613 mov r3, r2 + 8002ddc: 80fb strh r3, [r7, #6] uint8_t *pdata8bits; uint16_t *pdata16bits; uint32_t tickstart = 0U; - 800229a: 2300 movs r3, #0 - 800229c: 617b str r3, [r7, #20] + 8002dde: 2300 movs r3, #0 + 8002de0: 617b str r3, [r7, #20] /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) - 800229e: 68fb ldr r3, [r7, #12] - 80022a0: f893 303e ldrb.w r3, [r3, #62] ; 0x3e - 80022a4: b2db uxtb r3, r3 - 80022a6: 2b20 cmp r3, #32 - 80022a8: f040 808c bne.w 80023c4 + 8002de2: 68fb ldr r3, [r7, #12] + 8002de4: f893 303e ldrb.w r3, [r3, #62] ; 0x3e + 8002de8: b2db uxtb r3, r3 + 8002dea: 2b20 cmp r3, #32 + 8002dec: f040 808c bne.w 8002f08 { if ((pData == NULL) || (Size == 0U)) - 80022ac: 68bb ldr r3, [r7, #8] - 80022ae: 2b00 cmp r3, #0 - 80022b0: d002 beq.n 80022b8 - 80022b2: 88fb ldrh r3, [r7, #6] - 80022b4: 2b00 cmp r3, #0 - 80022b6: d101 bne.n 80022bc + 8002df0: 68bb ldr r3, [r7, #8] + 8002df2: 2b00 cmp r3, #0 + 8002df4: d002 beq.n 8002dfc + 8002df6: 88fb ldrh r3, [r7, #6] + 8002df8: 2b00 cmp r3, #0 + 8002dfa: d101 bne.n 8002e00 { return HAL_ERROR; - 80022b8: 2301 movs r3, #1 - 80022ba: e084 b.n 80023c6 + 8002dfc: 2301 movs r3, #1 + 8002dfe: e084 b.n 8002f0a } /* Process Locked */ __HAL_LOCK(huart); - 80022bc: 68fb ldr r3, [r7, #12] - 80022be: f893 303c ldrb.w r3, [r3, #60] ; 0x3c - 80022c2: 2b01 cmp r3, #1 - 80022c4: d101 bne.n 80022ca - 80022c6: 2302 movs r3, #2 - 80022c8: e07d b.n 80023c6 - 80022ca: 68fb ldr r3, [r7, #12] - 80022cc: 2201 movs r2, #1 - 80022ce: f883 203c strb.w r2, [r3, #60] ; 0x3c + 8002e00: 68fb ldr r3, [r7, #12] + 8002e02: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 8002e06: 2b01 cmp r3, #1 + 8002e08: d101 bne.n 8002e0e + 8002e0a: 2302 movs r3, #2 + 8002e0c: e07d b.n 8002f0a + 8002e0e: 68fb ldr r3, [r7, #12] + 8002e10: 2201 movs r2, #1 + 8002e12: f883 203c strb.w r2, [r3, #60] ; 0x3c huart->ErrorCode = HAL_UART_ERROR_NONE; - 80022d2: 68fb ldr r3, [r7, #12] - 80022d4: 2200 movs r2, #0 - 80022d6: 641a str r2, [r3, #64] ; 0x40 + 8002e16: 68fb ldr r3, [r7, #12] + 8002e18: 2200 movs r2, #0 + 8002e1a: 641a str r2, [r3, #64] ; 0x40 huart->RxState = HAL_UART_STATE_BUSY_RX; - 80022d8: 68fb ldr r3, [r7, #12] - 80022da: 2222 movs r2, #34 ; 0x22 - 80022dc: f883 203e strb.w r2, [r3, #62] ; 0x3e + 8002e1c: 68fb ldr r3, [r7, #12] + 8002e1e: 2222 movs r2, #34 ; 0x22 + 8002e20: f883 203e strb.w r2, [r3, #62] ; 0x3e huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - 80022e0: 68fb ldr r3, [r7, #12] - 80022e2: 2200 movs r2, #0 - 80022e4: 631a str r2, [r3, #48] ; 0x30 + 8002e24: 68fb ldr r3, [r7, #12] + 8002e26: 2200 movs r2, #0 + 8002e28: 631a str r2, [r3, #48] ; 0x30 /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); - 80022e6: f7fe fd03 bl 8000cf0 - 80022ea: 6178 str r0, [r7, #20] + 8002e2a: f7fe f897 bl 8000f5c + 8002e2e: 6178 str r0, [r7, #20] huart->RxXferSize = Size; - 80022ec: 68fb ldr r3, [r7, #12] - 80022ee: 88fa ldrh r2, [r7, #6] - 80022f0: 859a strh r2, [r3, #44] ; 0x2c + 8002e30: 68fb ldr r3, [r7, #12] + 8002e32: 88fa ldrh r2, [r7, #6] + 8002e34: 859a strh r2, [r3, #44] ; 0x2c huart->RxXferCount = Size; - 80022f2: 68fb ldr r3, [r7, #12] - 80022f4: 88fa ldrh r2, [r7, #6] - 80022f6: 85da strh r2, [r3, #46] ; 0x2e + 8002e36: 68fb ldr r3, [r7, #12] + 8002e38: 88fa ldrh r2, [r7, #6] + 8002e3a: 85da strh r2, [r3, #46] ; 0x2e /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - 80022f8: 68fb ldr r3, [r7, #12] - 80022fa: 689b ldr r3, [r3, #8] - 80022fc: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 8002300: d108 bne.n 8002314 - 8002302: 68fb ldr r3, [r7, #12] - 8002304: 691b ldr r3, [r3, #16] - 8002306: 2b00 cmp r3, #0 - 8002308: d104 bne.n 8002314 + 8002e3c: 68fb ldr r3, [r7, #12] + 8002e3e: 689b ldr r3, [r3, #8] + 8002e40: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8002e44: d108 bne.n 8002e58 + 8002e46: 68fb ldr r3, [r7, #12] + 8002e48: 691b ldr r3, [r3, #16] + 8002e4a: 2b00 cmp r3, #0 + 8002e4c: d104 bne.n 8002e58 { pdata8bits = NULL; - 800230a: 2300 movs r3, #0 - 800230c: 61fb str r3, [r7, #28] + 8002e4e: 2300 movs r3, #0 + 8002e50: 61fb str r3, [r7, #28] pdata16bits = (uint16_t *) pData; - 800230e: 68bb ldr r3, [r7, #8] - 8002310: 61bb str r3, [r7, #24] - 8002312: e003 b.n 800231c + 8002e52: 68bb ldr r3, [r7, #8] + 8002e54: 61bb str r3, [r7, #24] + 8002e56: e003 b.n 8002e60 } else { pdata8bits = pData; - 8002314: 68bb ldr r3, [r7, #8] - 8002316: 61fb str r3, [r7, #28] + 8002e58: 68bb ldr r3, [r7, #8] + 8002e5a: 61fb str r3, [r7, #28] pdata16bits = NULL; - 8002318: 2300 movs r3, #0 - 800231a: 61bb str r3, [r7, #24] + 8002e5c: 2300 movs r3, #0 + 8002e5e: 61bb str r3, [r7, #24] } /* Process Unlocked */ __HAL_UNLOCK(huart); - 800231c: 68fb ldr r3, [r7, #12] - 800231e: 2200 movs r2, #0 - 8002320: f883 203c strb.w r2, [r3, #60] ; 0x3c + 8002e60: 68fb ldr r3, [r7, #12] + 8002e62: 2200 movs r2, #0 + 8002e64: f883 203c strb.w r2, [r3, #60] ; 0x3c /* Check the remain data to be received */ while (huart->RxXferCount > 0U) - 8002324: e043 b.n 80023ae + 8002e68: e043 b.n 8002ef2 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - 8002326: 683b ldr r3, [r7, #0] - 8002328: 9300 str r3, [sp, #0] - 800232a: 697b ldr r3, [r7, #20] - 800232c: 2200 movs r2, #0 - 800232e: 2120 movs r1, #32 - 8002330: 68f8 ldr r0, [r7, #12] - 8002332: f000 f84c bl 80023ce - 8002336: 4603 mov r3, r0 - 8002338: 2b00 cmp r3, #0 - 800233a: d001 beq.n 8002340 + 8002e6a: 683b ldr r3, [r7, #0] + 8002e6c: 9300 str r3, [sp, #0] + 8002e6e: 697b ldr r3, [r7, #20] + 8002e70: 2200 movs r2, #0 + 8002e72: 2120 movs r1, #32 + 8002e74: 68f8 ldr r0, [r7, #12] + 8002e76: f000 f84c bl 8002f12 + 8002e7a: 4603 mov r3, r0 + 8002e7c: 2b00 cmp r3, #0 + 8002e7e: d001 beq.n 8002e84 { return HAL_TIMEOUT; - 800233c: 2303 movs r3, #3 - 800233e: e042 b.n 80023c6 + 8002e80: 2303 movs r3, #3 + 8002e82: e042 b.n 8002f0a } if (pdata8bits == NULL) - 8002340: 69fb ldr r3, [r7, #28] - 8002342: 2b00 cmp r3, #0 - 8002344: d10c bne.n 8002360 + 8002e84: 69fb ldr r3, [r7, #28] + 8002e86: 2b00 cmp r3, #0 + 8002e88: d10c bne.n 8002ea4 { *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF); - 8002346: 68fb ldr r3, [r7, #12] - 8002348: 681b ldr r3, [r3, #0] - 800234a: 685b ldr r3, [r3, #4] - 800234c: b29b uxth r3, r3 - 800234e: f3c3 0308 ubfx r3, r3, #0, #9 - 8002352: b29a uxth r2, r3 - 8002354: 69bb ldr r3, [r7, #24] - 8002356: 801a strh r2, [r3, #0] + 8002e8a: 68fb ldr r3, [r7, #12] + 8002e8c: 681b ldr r3, [r3, #0] + 8002e8e: 685b ldr r3, [r3, #4] + 8002e90: b29b uxth r3, r3 + 8002e92: f3c3 0308 ubfx r3, r3, #0, #9 + 8002e96: b29a uxth r2, r3 + 8002e98: 69bb ldr r3, [r7, #24] + 8002e9a: 801a strh r2, [r3, #0] pdata16bits++; - 8002358: 69bb ldr r3, [r7, #24] - 800235a: 3302 adds r3, #2 - 800235c: 61bb str r3, [r7, #24] - 800235e: e01f b.n 80023a0 + 8002e9c: 69bb ldr r3, [r7, #24] + 8002e9e: 3302 adds r3, #2 + 8002ea0: 61bb str r3, [r7, #24] + 8002ea2: e01f b.n 8002ee4 } else { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) - 8002360: 68fb ldr r3, [r7, #12] - 8002362: 689b ldr r3, [r3, #8] - 8002364: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 - 8002368: d007 beq.n 800237a - 800236a: 68fb ldr r3, [r7, #12] - 800236c: 689b ldr r3, [r3, #8] - 800236e: 2b00 cmp r3, #0 - 8002370: d10a bne.n 8002388 - 8002372: 68fb ldr r3, [r7, #12] - 8002374: 691b ldr r3, [r3, #16] - 8002376: 2b00 cmp r3, #0 - 8002378: d106 bne.n 8002388 + 8002ea4: 68fb ldr r3, [r7, #12] + 8002ea6: 689b ldr r3, [r3, #8] + 8002ea8: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8002eac: d007 beq.n 8002ebe + 8002eae: 68fb ldr r3, [r7, #12] + 8002eb0: 689b ldr r3, [r3, #8] + 8002eb2: 2b00 cmp r3, #0 + 8002eb4: d10a bne.n 8002ecc + 8002eb6: 68fb ldr r3, [r7, #12] + 8002eb8: 691b ldr r3, [r3, #16] + 8002eba: 2b00 cmp r3, #0 + 8002ebc: d106 bne.n 8002ecc { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - 800237a: 68fb ldr r3, [r7, #12] - 800237c: 681b ldr r3, [r3, #0] - 800237e: 685b ldr r3, [r3, #4] - 8002380: b2da uxtb r2, r3 - 8002382: 69fb ldr r3, [r7, #28] - 8002384: 701a strb r2, [r3, #0] - 8002386: e008 b.n 800239a + 8002ebe: 68fb ldr r3, [r7, #12] + 8002ec0: 681b ldr r3, [r3, #0] + 8002ec2: 685b ldr r3, [r3, #4] + 8002ec4: b2da uxtb r2, r3 + 8002ec6: 69fb ldr r3, [r7, #28] + 8002ec8: 701a strb r2, [r3, #0] + 8002eca: e008 b.n 8002ede } else { *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - 8002388: 68fb ldr r3, [r7, #12] - 800238a: 681b ldr r3, [r3, #0] - 800238c: 685b ldr r3, [r3, #4] - 800238e: b2db uxtb r3, r3 - 8002390: f003 037f and.w r3, r3, #127 ; 0x7f - 8002394: b2da uxtb r2, r3 - 8002396: 69fb ldr r3, [r7, #28] - 8002398: 701a strb r2, [r3, #0] + 8002ecc: 68fb ldr r3, [r7, #12] + 8002ece: 681b ldr r3, [r3, #0] + 8002ed0: 685b ldr r3, [r3, #4] + 8002ed2: b2db uxtb r3, r3 + 8002ed4: f003 037f and.w r3, r3, #127 ; 0x7f + 8002ed8: b2da uxtb r2, r3 + 8002eda: 69fb ldr r3, [r7, #28] + 8002edc: 701a strb r2, [r3, #0] } pdata8bits++; - 800239a: 69fb ldr r3, [r7, #28] - 800239c: 3301 adds r3, #1 - 800239e: 61fb str r3, [r7, #28] + 8002ede: 69fb ldr r3, [r7, #28] + 8002ee0: 3301 adds r3, #1 + 8002ee2: 61fb str r3, [r7, #28] } huart->RxXferCount--; - 80023a0: 68fb ldr r3, [r7, #12] - 80023a2: 8ddb ldrh r3, [r3, #46] ; 0x2e - 80023a4: b29b uxth r3, r3 - 80023a6: 3b01 subs r3, #1 - 80023a8: b29a uxth r2, r3 - 80023aa: 68fb ldr r3, [r7, #12] - 80023ac: 85da strh r2, [r3, #46] ; 0x2e + 8002ee4: 68fb ldr r3, [r7, #12] + 8002ee6: 8ddb ldrh r3, [r3, #46] ; 0x2e + 8002ee8: b29b uxth r3, r3 + 8002eea: 3b01 subs r3, #1 + 8002eec: b29a uxth r2, r3 + 8002eee: 68fb ldr r3, [r7, #12] + 8002ef0: 85da strh r2, [r3, #46] ; 0x2e while (huart->RxXferCount > 0U) - 80023ae: 68fb ldr r3, [r7, #12] - 80023b0: 8ddb ldrh r3, [r3, #46] ; 0x2e - 80023b2: b29b uxth r3, r3 - 80023b4: 2b00 cmp r3, #0 - 80023b6: d1b6 bne.n 8002326 + 8002ef2: 68fb ldr r3, [r7, #12] + 8002ef4: 8ddb ldrh r3, [r3, #46] ; 0x2e + 8002ef6: b29b uxth r3, r3 + 8002ef8: 2b00 cmp r3, #0 + 8002efa: d1b6 bne.n 8002e6a } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; - 80023b8: 68fb ldr r3, [r7, #12] - 80023ba: 2220 movs r2, #32 - 80023bc: f883 203e strb.w r2, [r3, #62] ; 0x3e + 8002efc: 68fb ldr r3, [r7, #12] + 8002efe: 2220 movs r2, #32 + 8002f00: f883 203e strb.w r2, [r3, #62] ; 0x3e return HAL_OK; - 80023c0: 2300 movs r3, #0 - 80023c2: e000 b.n 80023c6 + 8002f04: 2300 movs r3, #0 + 8002f06: e000 b.n 8002f0a } else { return HAL_BUSY; - 80023c4: 2302 movs r3, #2 + 8002f08: 2302 movs r3, #2 } } - 80023c6: 4618 mov r0, r3 - 80023c8: 3720 adds r7, #32 - 80023ca: 46bd mov sp, r7 - 80023cc: bd80 pop {r7, pc} + 8002f0a: 4618 mov r0, r3 + 8002f0c: 3720 adds r7, #32 + 8002f0e: 46bd mov sp, r7 + 8002f10: bd80 pop {r7, pc} -080023ce : +08002f12 : * @param Timeout Timeout duration * @retval HAL status */ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { - 80023ce: b580 push {r7, lr} - 80023d0: b090 sub sp, #64 ; 0x40 - 80023d2: af00 add r7, sp, #0 - 80023d4: 60f8 str r0, [r7, #12] - 80023d6: 60b9 str r1, [r7, #8] - 80023d8: 603b str r3, [r7, #0] - 80023da: 4613 mov r3, r2 - 80023dc: 71fb strb r3, [r7, #7] + 8002f12: b580 push {r7, lr} + 8002f14: b090 sub sp, #64 ; 0x40 + 8002f16: af00 add r7, sp, #0 + 8002f18: 60f8 str r0, [r7, #12] + 8002f1a: 60b9 str r1, [r7, #8] + 8002f1c: 603b str r3, [r7, #0] + 8002f1e: 4613 mov r3, r2 + 8002f20: 71fb strb r3, [r7, #7] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 80023de: e050 b.n 8002482 + 8002f22: e050 b.n 8002fc6 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) - 80023e0: 6cbb ldr r3, [r7, #72] ; 0x48 - 80023e2: f1b3 3fff cmp.w r3, #4294967295 - 80023e6: d04c beq.n 8002482 + 8002f24: 6cbb ldr r3, [r7, #72] ; 0x48 + 8002f26: f1b3 3fff cmp.w r3, #4294967295 + 8002f2a: d04c beq.n 8002fc6 { if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) - 80023e8: 6cbb ldr r3, [r7, #72] ; 0x48 - 80023ea: 2b00 cmp r3, #0 - 80023ec: d007 beq.n 80023fe - 80023ee: f7fe fc7f bl 8000cf0 - 80023f2: 4602 mov r2, r0 - 80023f4: 683b ldr r3, [r7, #0] - 80023f6: 1ad3 subs r3, r2, r3 - 80023f8: 6cba ldr r2, [r7, #72] ; 0x48 - 80023fa: 429a cmp r2, r3 - 80023fc: d241 bcs.n 8002482 + 8002f2c: 6cbb ldr r3, [r7, #72] ; 0x48 + 8002f2e: 2b00 cmp r3, #0 + 8002f30: d007 beq.n 8002f42 + 8002f32: f7fe f813 bl 8000f5c + 8002f36: 4602 mov r2, r0 + 8002f38: 683b ldr r3, [r7, #0] + 8002f3a: 1ad3 subs r3, r2, r3 + 8002f3c: 6cba ldr r2, [r7, #72] ; 0x48 + 8002f3e: 429a cmp r2, r3 + 8002f40: d241 bcs.n 8002fc6 { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - 80023fe: 68fb ldr r3, [r7, #12] - 8002400: 681b ldr r3, [r3, #0] - 8002402: 330c adds r3, #12 - 8002404: 62bb str r3, [r7, #40] ; 0x28 + 8002f42: 68fb ldr r3, [r7, #12] + 8002f44: 681b ldr r3, [r3, #0] + 8002f46: 330c adds r3, #12 + 8002f48: 62bb str r3, [r7, #40] ; 0x28 */ __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 8002406: 6abb ldr r3, [r7, #40] ; 0x28 - 8002408: e853 3f00 ldrex r3, [r3] - 800240c: 627b str r3, [r7, #36] ; 0x24 + 8002f4a: 6abb ldr r3, [r7, #40] ; 0x28 + 8002f4c: e853 3f00 ldrex r3, [r3] + 8002f50: 627b str r3, [r7, #36] ; 0x24 return(result); - 800240e: 6a7b ldr r3, [r7, #36] ; 0x24 - 8002410: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 - 8002414: 63fb str r3, [r7, #60] ; 0x3c - 8002416: 68fb ldr r3, [r7, #12] - 8002418: 681b ldr r3, [r3, #0] - 800241a: 330c adds r3, #12 - 800241c: 6bfa ldr r2, [r7, #60] ; 0x3c - 800241e: 637a str r2, [r7, #52] ; 0x34 - 8002420: 633b str r3, [r7, #48] ; 0x30 + 8002f52: 6a7b ldr r3, [r7, #36] ; 0x24 + 8002f54: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 + 8002f58: 63fb str r3, [r7, #60] ; 0x3c + 8002f5a: 68fb ldr r3, [r7, #12] + 8002f5c: 681b ldr r3, [r3, #0] + 8002f5e: 330c adds r3, #12 + 8002f60: 6bfa ldr r2, [r7, #60] ; 0x3c + 8002f62: 637a str r2, [r7, #52] ; 0x34 + 8002f64: 633b str r3, [r7, #48] ; 0x30 */ __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8002422: 6b39 ldr r1, [r7, #48] ; 0x30 - 8002424: 6b7a ldr r2, [r7, #52] ; 0x34 - 8002426: e841 2300 strex r3, r2, [r1] - 800242a: 62fb str r3, [r7, #44] ; 0x2c + 8002f66: 6b39 ldr r1, [r7, #48] ; 0x30 + 8002f68: 6b7a ldr r2, [r7, #52] ; 0x34 + 8002f6a: e841 2300 strex r3, r2, [r1] + 8002f6e: 62fb str r3, [r7, #44] ; 0x2c return(result); - 800242c: 6afb ldr r3, [r7, #44] ; 0x2c - 800242e: 2b00 cmp r3, #0 - 8002430: d1e5 bne.n 80023fe + 8002f70: 6afb ldr r3, [r7, #44] ; 0x2c + 8002f72: 2b00 cmp r3, #0 + 8002f74: d1e5 bne.n 8002f42 ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - 8002432: 68fb ldr r3, [r7, #12] - 8002434: 681b ldr r3, [r3, #0] - 8002436: 3314 adds r3, #20 - 8002438: 617b str r3, [r7, #20] + 8002f76: 68fb ldr r3, [r7, #12] + 8002f78: 681b ldr r3, [r3, #0] + 8002f7a: 3314 adds r3, #20 + 8002f7c: 617b str r3, [r7, #20] __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - 800243a: 697b ldr r3, [r7, #20] - 800243c: e853 3f00 ldrex r3, [r3] - 8002440: 613b str r3, [r7, #16] + 8002f7e: 697b ldr r3, [r7, #20] + 8002f80: e853 3f00 ldrex r3, [r3] + 8002f84: 613b str r3, [r7, #16] return(result); - 8002442: 693b ldr r3, [r7, #16] - 8002444: f023 0301 bic.w r3, r3, #1 - 8002448: 63bb str r3, [r7, #56] ; 0x38 - 800244a: 68fb ldr r3, [r7, #12] - 800244c: 681b ldr r3, [r3, #0] - 800244e: 3314 adds r3, #20 - 8002450: 6bba ldr r2, [r7, #56] ; 0x38 - 8002452: 623a str r2, [r7, #32] - 8002454: 61fb str r3, [r7, #28] + 8002f86: 693b ldr r3, [r7, #16] + 8002f88: f023 0301 bic.w r3, r3, #1 + 8002f8c: 63bb str r3, [r7, #56] ; 0x38 + 8002f8e: 68fb ldr r3, [r7, #12] + 8002f90: 681b ldr r3, [r3, #0] + 8002f92: 3314 adds r3, #20 + 8002f94: 6bba ldr r2, [r7, #56] ; 0x38 + 8002f96: 623a str r2, [r7, #32] + 8002f98: 61fb str r3, [r7, #28] __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - 8002456: 69f9 ldr r1, [r7, #28] - 8002458: 6a3a ldr r2, [r7, #32] - 800245a: e841 2300 strex r3, r2, [r1] - 800245e: 61bb str r3, [r7, #24] + 8002f9a: 69f9 ldr r1, [r7, #28] + 8002f9c: 6a3a ldr r2, [r7, #32] + 8002f9e: e841 2300 strex r3, r2, [r1] + 8002fa2: 61bb str r3, [r7, #24] return(result); - 8002460: 69bb ldr r3, [r7, #24] - 8002462: 2b00 cmp r3, #0 - 8002464: d1e5 bne.n 8002432 + 8002fa4: 69bb ldr r3, [r7, #24] + 8002fa6: 2b00 cmp r3, #0 + 8002fa8: d1e5 bne.n 8002f76 huart->gState = HAL_UART_STATE_READY; - 8002466: 68fb ldr r3, [r7, #12] - 8002468: 2220 movs r2, #32 - 800246a: f883 203d strb.w r2, [r3, #61] ; 0x3d + 8002faa: 68fb ldr r3, [r7, #12] + 8002fac: 2220 movs r2, #32 + 8002fae: f883 203d strb.w r2, [r3, #61] ; 0x3d huart->RxState = HAL_UART_STATE_READY; - 800246e: 68fb ldr r3, [r7, #12] - 8002470: 2220 movs r2, #32 - 8002472: f883 203e strb.w r2, [r3, #62] ; 0x3e + 8002fb2: 68fb ldr r3, [r7, #12] + 8002fb4: 2220 movs r2, #32 + 8002fb6: f883 203e strb.w r2, [r3, #62] ; 0x3e /* Process Unlocked */ __HAL_UNLOCK(huart); - 8002476: 68fb ldr r3, [r7, #12] - 8002478: 2200 movs r2, #0 - 800247a: f883 203c strb.w r2, [r3, #60] ; 0x3c + 8002fba: 68fb ldr r3, [r7, #12] + 8002fbc: 2200 movs r2, #0 + 8002fbe: f883 203c strb.w r2, [r3, #60] ; 0x3c return HAL_TIMEOUT; - 800247e: 2303 movs r3, #3 - 8002480: e00f b.n 80024a2 + 8002fc2: 2303 movs r3, #3 + 8002fc4: e00f b.n 8002fe6 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - 8002482: 68fb ldr r3, [r7, #12] - 8002484: 681b ldr r3, [r3, #0] - 8002486: 681a ldr r2, [r3, #0] - 8002488: 68bb ldr r3, [r7, #8] - 800248a: 4013 ands r3, r2 - 800248c: 68ba ldr r2, [r7, #8] - 800248e: 429a cmp r2, r3 - 8002490: bf0c ite eq - 8002492: 2301 moveq r3, #1 - 8002494: 2300 movne r3, #0 - 8002496: b2db uxtb r3, r3 - 8002498: 461a mov r2, r3 - 800249a: 79fb ldrb r3, [r7, #7] - 800249c: 429a cmp r2, r3 - 800249e: d09f beq.n 80023e0 + 8002fc6: 68fb ldr r3, [r7, #12] + 8002fc8: 681b ldr r3, [r3, #0] + 8002fca: 681a ldr r2, [r3, #0] + 8002fcc: 68bb ldr r3, [r7, #8] + 8002fce: 4013 ands r3, r2 + 8002fd0: 68ba ldr r2, [r7, #8] + 8002fd2: 429a cmp r2, r3 + 8002fd4: bf0c ite eq + 8002fd6: 2301 moveq r3, #1 + 8002fd8: 2300 movne r3, #0 + 8002fda: b2db uxtb r3, r3 + 8002fdc: 461a mov r2, r3 + 8002fde: 79fb ldrb r3, [r7, #7] + 8002fe0: 429a cmp r2, r3 + 8002fe2: d09f beq.n 8002f24 } } } return HAL_OK; - 80024a0: 2300 movs r3, #0 + 8002fe4: 2300 movs r3, #0 } - 80024a2: 4618 mov r0, r3 - 80024a4: 3740 adds r7, #64 ; 0x40 - 80024a6: 46bd mov sp, r7 - 80024a8: bd80 pop {r7, pc} + 8002fe6: 4618 mov r0, r3 + 8002fe8: 3740 adds r7, #64 ; 0x40 + 8002fea: 46bd mov sp, r7 + 8002fec: bd80 pop {r7, pc} ... -080024ac : +08002ff0 : * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval None */ static void UART_SetConfig(UART_HandleTypeDef *huart) { - 80024ac: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} - 80024b0: b0c0 sub sp, #256 ; 0x100 - 80024b2: af00 add r7, sp, #0 - 80024b4: f8c7 00f4 str.w r0, [r7, #244] ; 0xf4 + 8002ff0: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8002ff4: b0c0 sub sp, #256 ; 0x100 + 8002ff6: af00 add r7, sp, #0 + 8002ff8: f8c7 00f4 str.w r0, [r7, #244] ; 0xf4 assert_param(IS_UART_MODE(huart->Init.Mode)); /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - 80024b8: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80024bc: 681b ldr r3, [r3, #0] - 80024be: 691b ldr r3, [r3, #16] - 80024c0: f423 5040 bic.w r0, r3, #12288 ; 0x3000 - 80024c4: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80024c8: 68d9 ldr r1, [r3, #12] - 80024ca: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80024ce: 681a ldr r2, [r3, #0] - 80024d0: ea40 0301 orr.w r3, r0, r1 - 80024d4: 6113 str r3, [r2, #16] + 8002ffc: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003000: 681b ldr r3, [r3, #0] + 8003002: 691b ldr r3, [r3, #16] + 8003004: f423 5040 bic.w r0, r3, #12288 ; 0x3000 + 8003008: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800300c: 68d9 ldr r1, [r3, #12] + 800300e: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003012: 681a ldr r2, [r3, #0] + 8003014: ea40 0301 orr.w r3, r0, r1 + 8003018: 6113 str r3, [r2, #16] Set the M bits according to huart->Init.WordLength value Set PCE and PS bits according to huart->Init.Parity value Set TE and RE bits according to huart->Init.Mode value Set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling; - 80024d6: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80024da: 689a ldr r2, [r3, #8] - 80024dc: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80024e0: 691b ldr r3, [r3, #16] - 80024e2: 431a orrs r2, r3 - 80024e4: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80024e8: 695b ldr r3, [r3, #20] - 80024ea: 431a orrs r2, r3 - 80024ec: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80024f0: 69db ldr r3, [r3, #28] - 80024f2: 4313 orrs r3, r2 - 80024f4: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 + 800301a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800301e: 689a ldr r2, [r3, #8] + 8003020: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003024: 691b ldr r3, [r3, #16] + 8003026: 431a orrs r2, r3 + 8003028: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800302c: 695b ldr r3, [r3, #20] + 800302e: 431a orrs r2, r3 + 8003030: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003034: 69db ldr r3, [r3, #28] + 8003036: 4313 orrs r3, r2 + 8003038: f8c7 30f8 str.w r3, [r7, #248] ; 0xf8 MODIFY_REG(huart->Instance->CR1, - 80024f8: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80024fc: 681b ldr r3, [r3, #0] - 80024fe: 68db ldr r3, [r3, #12] - 8002500: f423 4116 bic.w r1, r3, #38400 ; 0x9600 - 8002504: f021 010c bic.w r1, r1, #12 - 8002508: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800250c: 681a ldr r2, [r3, #0] - 800250e: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 - 8002512: 430b orrs r3, r1 - 8002514: 60d3 str r3, [r2, #12] + 800303c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003040: 681b ldr r3, [r3, #0] + 8003042: 68db ldr r3, [r3, #12] + 8003044: f423 4116 bic.w r1, r3, #38400 ; 0x9600 + 8003048: f021 010c bic.w r1, r1, #12 + 800304c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003050: 681a ldr r2, [r3, #0] + 8003052: f8d7 30f8 ldr.w r3, [r7, #248] ; 0xf8 + 8003056: 430b orrs r3, r1 + 8003058: 60d3 str r3, [r2, #12] (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), tmpreg); /*-------------------------- USART CR3 Configuration -----------------------*/ /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */ MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl); - 8002516: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800251a: 681b ldr r3, [r3, #0] - 800251c: 695b ldr r3, [r3, #20] - 800251e: f423 7040 bic.w r0, r3, #768 ; 0x300 - 8002522: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 8002526: 6999 ldr r1, [r3, #24] - 8002528: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800252c: 681a ldr r2, [r3, #0] - 800252e: ea40 0301 orr.w r3, r0, r1 - 8002532: 6153 str r3, [r2, #20] + 800305a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800305e: 681b ldr r3, [r3, #0] + 8003060: 695b ldr r3, [r3, #20] + 8003062: f423 7040 bic.w r0, r3, #768 ; 0x300 + 8003066: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800306a: 6999 ldr r1, [r3, #24] + 800306c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003070: 681a ldr r2, [r3, #0] + 8003072: ea40 0301 orr.w r3, r0, r1 + 8003076: 6153 str r3, [r2, #20] if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10)) { pclk = HAL_RCC_GetPCLK2Freq(); } #elif defined(USART6) if ((huart->Instance == USART1) || (huart->Instance == USART6)) - 8002534: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 8002538: 681a ldr r2, [r3, #0] - 800253a: 4b8f ldr r3, [pc, #572] ; (8002778 ) - 800253c: 429a cmp r2, r3 - 800253e: d005 beq.n 800254c - 8002540: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 8002544: 681a ldr r2, [r3, #0] - 8002546: 4b8d ldr r3, [pc, #564] ; (800277c ) - 8002548: 429a cmp r2, r3 - 800254a: d104 bne.n 8002556 + 8003078: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800307c: 681a ldr r2, [r3, #0] + 800307e: 4b8f ldr r3, [pc, #572] ; (80032bc ) + 8003080: 429a cmp r2, r3 + 8003082: d005 beq.n 8003090 + 8003084: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003088: 681a ldr r2, [r3, #0] + 800308a: 4b8d ldr r3, [pc, #564] ; (80032c0 ) + 800308c: 429a cmp r2, r3 + 800308e: d104 bne.n 800309a { pclk = HAL_RCC_GetPCLK2Freq(); - 800254c: f7ff faf8 bl 8001b40 - 8002550: f8c7 00fc str.w r0, [r7, #252] ; 0xfc - 8002554: e003 b.n 800255e + 8003090: f7ff faf8 bl 8002684 + 8003094: f8c7 00fc str.w r0, [r7, #252] ; 0xfc + 8003098: e003 b.n 80030a2 pclk = HAL_RCC_GetPCLK2Freq(); } #endif /* USART6 */ else { pclk = HAL_RCC_GetPCLK1Freq(); - 8002556: f7ff fadf bl 8001b18 - 800255a: f8c7 00fc str.w r0, [r7, #252] ; 0xfc + 800309a: f7ff fadf bl 800265c + 800309e: f8c7 00fc str.w r0, [r7, #252] ; 0xfc } /*-------------------------- USART BRR Configuration ---------------------*/ if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - 800255e: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 8002562: 69db ldr r3, [r3, #28] - 8002564: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 - 8002568: f040 810c bne.w 8002784 + 80030a2: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 80030a6: 69db ldr r3, [r3, #28] + 80030a8: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 80030ac: f040 810c bne.w 80032c8 { huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate); - 800256c: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 8002570: 2200 movs r2, #0 - 8002572: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 - 8002576: f8c7 20ec str.w r2, [r7, #236] ; 0xec - 800257a: e9d7 453a ldrd r4, r5, [r7, #232] ; 0xe8 - 800257e: 4622 mov r2, r4 - 8002580: 462b mov r3, r5 - 8002582: 1891 adds r1, r2, r2 - 8002584: 65b9 str r1, [r7, #88] ; 0x58 - 8002586: 415b adcs r3, r3 - 8002588: 65fb str r3, [r7, #92] ; 0x5c - 800258a: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 - 800258e: 4621 mov r1, r4 - 8002590: eb12 0801 adds.w r8, r2, r1 - 8002594: 4629 mov r1, r5 - 8002596: eb43 0901 adc.w r9, r3, r1 - 800259a: f04f 0200 mov.w r2, #0 - 800259e: f04f 0300 mov.w r3, #0 - 80025a2: ea4f 03c9 mov.w r3, r9, lsl #3 - 80025a6: ea43 7358 orr.w r3, r3, r8, lsr #29 - 80025aa: ea4f 02c8 mov.w r2, r8, lsl #3 - 80025ae: 4690 mov r8, r2 - 80025b0: 4699 mov r9, r3 - 80025b2: 4623 mov r3, r4 - 80025b4: eb18 0303 adds.w r3, r8, r3 - 80025b8: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 - 80025bc: 462b mov r3, r5 - 80025be: eb49 0303 adc.w r3, r9, r3 - 80025c2: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 - 80025c6: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80025ca: 685b ldr r3, [r3, #4] - 80025cc: 2200 movs r2, #0 - 80025ce: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 - 80025d2: f8c7 20dc str.w r2, [r7, #220] ; 0xdc - 80025d6: e9d7 1236 ldrd r1, r2, [r7, #216] ; 0xd8 - 80025da: 460b mov r3, r1 - 80025dc: 18db adds r3, r3, r3 - 80025de: 653b str r3, [r7, #80] ; 0x50 - 80025e0: 4613 mov r3, r2 - 80025e2: eb42 0303 adc.w r3, r2, r3 - 80025e6: 657b str r3, [r7, #84] ; 0x54 - 80025e8: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50 - 80025ec: e9d7 0138 ldrd r0, r1, [r7, #224] ; 0xe0 - 80025f0: f7fd fdf6 bl 80001e0 <__aeabi_uldivmod> - 80025f4: 4602 mov r2, r0 - 80025f6: 460b mov r3, r1 - 80025f8: 4b61 ldr r3, [pc, #388] ; (8002780 ) - 80025fa: fba3 2302 umull r2, r3, r3, r2 - 80025fe: 095b lsrs r3, r3, #5 - 8002600: 011c lsls r4, r3, #4 - 8002602: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 8002606: 2200 movs r2, #0 - 8002608: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 - 800260c: f8c7 20d4 str.w r2, [r7, #212] ; 0xd4 - 8002610: e9d7 8934 ldrd r8, r9, [r7, #208] ; 0xd0 - 8002614: 4642 mov r2, r8 - 8002616: 464b mov r3, r9 - 8002618: 1891 adds r1, r2, r2 - 800261a: 64b9 str r1, [r7, #72] ; 0x48 - 800261c: 415b adcs r3, r3 - 800261e: 64fb str r3, [r7, #76] ; 0x4c - 8002620: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48 - 8002624: 4641 mov r1, r8 - 8002626: eb12 0a01 adds.w sl, r2, r1 - 800262a: 4649 mov r1, r9 - 800262c: eb43 0b01 adc.w fp, r3, r1 - 8002630: f04f 0200 mov.w r2, #0 - 8002634: f04f 0300 mov.w r3, #0 - 8002638: ea4f 03cb mov.w r3, fp, lsl #3 - 800263c: ea43 735a orr.w r3, r3, sl, lsr #29 - 8002640: ea4f 02ca mov.w r2, sl, lsl #3 - 8002644: 4692 mov sl, r2 - 8002646: 469b mov fp, r3 - 8002648: 4643 mov r3, r8 - 800264a: eb1a 0303 adds.w r3, sl, r3 - 800264e: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 - 8002652: 464b mov r3, r9 - 8002654: eb4b 0303 adc.w r3, fp, r3 - 8002658: f8c7 30cc str.w r3, [r7, #204] ; 0xcc - 800265c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 8002660: 685b ldr r3, [r3, #4] - 8002662: 2200 movs r2, #0 - 8002664: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 - 8002668: f8c7 20c4 str.w r2, [r7, #196] ; 0xc4 - 800266c: e9d7 1230 ldrd r1, r2, [r7, #192] ; 0xc0 - 8002670: 460b mov r3, r1 - 8002672: 18db adds r3, r3, r3 - 8002674: 643b str r3, [r7, #64] ; 0x40 - 8002676: 4613 mov r3, r2 - 8002678: eb42 0303 adc.w r3, r2, r3 - 800267c: 647b str r3, [r7, #68] ; 0x44 - 800267e: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40 - 8002682: e9d7 0132 ldrd r0, r1, [r7, #200] ; 0xc8 - 8002686: f7fd fdab bl 80001e0 <__aeabi_uldivmod> - 800268a: 4602 mov r2, r0 - 800268c: 460b mov r3, r1 - 800268e: 4611 mov r1, r2 - 8002690: 4b3b ldr r3, [pc, #236] ; (8002780 ) - 8002692: fba3 2301 umull r2, r3, r3, r1 - 8002696: 095b lsrs r3, r3, #5 - 8002698: 2264 movs r2, #100 ; 0x64 - 800269a: fb02 f303 mul.w r3, r2, r3 - 800269e: 1acb subs r3, r1, r3 - 80026a0: 00db lsls r3, r3, #3 - 80026a2: f103 0232 add.w r2, r3, #50 ; 0x32 - 80026a6: 4b36 ldr r3, [pc, #216] ; (8002780 ) - 80026a8: fba3 2302 umull r2, r3, r3, r2 - 80026ac: 095b lsrs r3, r3, #5 - 80026ae: 005b lsls r3, r3, #1 - 80026b0: f403 73f8 and.w r3, r3, #496 ; 0x1f0 - 80026b4: 441c add r4, r3 - 80026b6: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 80026ba: 2200 movs r2, #0 - 80026bc: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 - 80026c0: f8c7 20bc str.w r2, [r7, #188] ; 0xbc - 80026c4: e9d7 892e ldrd r8, r9, [r7, #184] ; 0xb8 - 80026c8: 4642 mov r2, r8 - 80026ca: 464b mov r3, r9 - 80026cc: 1891 adds r1, r2, r2 - 80026ce: 63b9 str r1, [r7, #56] ; 0x38 - 80026d0: 415b adcs r3, r3 - 80026d2: 63fb str r3, [r7, #60] ; 0x3c - 80026d4: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 - 80026d8: 4641 mov r1, r8 - 80026da: 1851 adds r1, r2, r1 - 80026dc: 6339 str r1, [r7, #48] ; 0x30 - 80026de: 4649 mov r1, r9 - 80026e0: 414b adcs r3, r1 - 80026e2: 637b str r3, [r7, #52] ; 0x34 - 80026e4: f04f 0200 mov.w r2, #0 - 80026e8: f04f 0300 mov.w r3, #0 - 80026ec: e9d7 ab0c ldrd sl, fp, [r7, #48] ; 0x30 - 80026f0: 4659 mov r1, fp - 80026f2: 00cb lsls r3, r1, #3 - 80026f4: 4651 mov r1, sl - 80026f6: ea43 7351 orr.w r3, r3, r1, lsr #29 - 80026fa: 4651 mov r1, sl - 80026fc: 00ca lsls r2, r1, #3 - 80026fe: 4610 mov r0, r2 - 8002700: 4619 mov r1, r3 - 8002702: 4603 mov r3, r0 - 8002704: 4642 mov r2, r8 - 8002706: 189b adds r3, r3, r2 - 8002708: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 - 800270c: 464b mov r3, r9 - 800270e: 460a mov r2, r1 - 8002710: eb42 0303 adc.w r3, r2, r3 - 8002714: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 - 8002718: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800271c: 685b ldr r3, [r3, #4] - 800271e: 2200 movs r2, #0 - 8002720: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 - 8002724: f8c7 20ac str.w r2, [r7, #172] ; 0xac - 8002728: e9d7 122a ldrd r1, r2, [r7, #168] ; 0xa8 - 800272c: 460b mov r3, r1 - 800272e: 18db adds r3, r3, r3 - 8002730: 62bb str r3, [r7, #40] ; 0x28 - 8002732: 4613 mov r3, r2 - 8002734: eb42 0303 adc.w r3, r2, r3 - 8002738: 62fb str r3, [r7, #44] ; 0x2c - 800273a: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 - 800273e: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0 - 8002742: f7fd fd4d bl 80001e0 <__aeabi_uldivmod> - 8002746: 4602 mov r2, r0 - 8002748: 460b mov r3, r1 - 800274a: 4b0d ldr r3, [pc, #52] ; (8002780 ) - 800274c: fba3 1302 umull r1, r3, r3, r2 - 8002750: 095b lsrs r3, r3, #5 - 8002752: 2164 movs r1, #100 ; 0x64 - 8002754: fb01 f303 mul.w r3, r1, r3 - 8002758: 1ad3 subs r3, r2, r3 - 800275a: 00db lsls r3, r3, #3 - 800275c: 3332 adds r3, #50 ; 0x32 - 800275e: 4a08 ldr r2, [pc, #32] ; (8002780 ) - 8002760: fba2 2303 umull r2, r3, r2, r3 - 8002764: 095b lsrs r3, r3, #5 - 8002766: f003 0207 and.w r2, r3, #7 - 800276a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800276e: 681b ldr r3, [r3, #0] - 8002770: 4422 add r2, r4 - 8002772: 609a str r2, [r3, #8] + 80030b0: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 80030b4: 2200 movs r2, #0 + 80030b6: f8c7 30e8 str.w r3, [r7, #232] ; 0xe8 + 80030ba: f8c7 20ec str.w r2, [r7, #236] ; 0xec + 80030be: e9d7 453a ldrd r4, r5, [r7, #232] ; 0xe8 + 80030c2: 4622 mov r2, r4 + 80030c4: 462b mov r3, r5 + 80030c6: 1891 adds r1, r2, r2 + 80030c8: 65b9 str r1, [r7, #88] ; 0x58 + 80030ca: 415b adcs r3, r3 + 80030cc: 65fb str r3, [r7, #92] ; 0x5c + 80030ce: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 + 80030d2: 4621 mov r1, r4 + 80030d4: eb12 0801 adds.w r8, r2, r1 + 80030d8: 4629 mov r1, r5 + 80030da: eb43 0901 adc.w r9, r3, r1 + 80030de: f04f 0200 mov.w r2, #0 + 80030e2: f04f 0300 mov.w r3, #0 + 80030e6: ea4f 03c9 mov.w r3, r9, lsl #3 + 80030ea: ea43 7358 orr.w r3, r3, r8, lsr #29 + 80030ee: ea4f 02c8 mov.w r2, r8, lsl #3 + 80030f2: 4690 mov r8, r2 + 80030f4: 4699 mov r9, r3 + 80030f6: 4623 mov r3, r4 + 80030f8: eb18 0303 adds.w r3, r8, r3 + 80030fc: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 + 8003100: 462b mov r3, r5 + 8003102: eb49 0303 adc.w r3, r9, r3 + 8003106: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 + 800310a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800310e: 685b ldr r3, [r3, #4] + 8003110: 2200 movs r2, #0 + 8003112: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 + 8003116: f8c7 20dc str.w r2, [r7, #220] ; 0xdc + 800311a: e9d7 1236 ldrd r1, r2, [r7, #216] ; 0xd8 + 800311e: 460b mov r3, r1 + 8003120: 18db adds r3, r3, r3 + 8003122: 653b str r3, [r7, #80] ; 0x50 + 8003124: 4613 mov r3, r2 + 8003126: eb42 0303 adc.w r3, r2, r3 + 800312a: 657b str r3, [r7, #84] ; 0x54 + 800312c: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50 + 8003130: e9d7 0138 ldrd r0, r1, [r7, #224] ; 0xe0 + 8003134: f7fd f854 bl 80001e0 <__aeabi_uldivmod> + 8003138: 4602 mov r2, r0 + 800313a: 460b mov r3, r1 + 800313c: 4b61 ldr r3, [pc, #388] ; (80032c4 ) + 800313e: fba3 2302 umull r2, r3, r3, r2 + 8003142: 095b lsrs r3, r3, #5 + 8003144: 011c lsls r4, r3, #4 + 8003146: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 800314a: 2200 movs r2, #0 + 800314c: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 8003150: f8c7 20d4 str.w r2, [r7, #212] ; 0xd4 + 8003154: e9d7 8934 ldrd r8, r9, [r7, #208] ; 0xd0 + 8003158: 4642 mov r2, r8 + 800315a: 464b mov r3, r9 + 800315c: 1891 adds r1, r2, r2 + 800315e: 64b9 str r1, [r7, #72] ; 0x48 + 8003160: 415b adcs r3, r3 + 8003162: 64fb str r3, [r7, #76] ; 0x4c + 8003164: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48 + 8003168: 4641 mov r1, r8 + 800316a: eb12 0a01 adds.w sl, r2, r1 + 800316e: 4649 mov r1, r9 + 8003170: eb43 0b01 adc.w fp, r3, r1 + 8003174: f04f 0200 mov.w r2, #0 + 8003178: f04f 0300 mov.w r3, #0 + 800317c: ea4f 03cb mov.w r3, fp, lsl #3 + 8003180: ea43 735a orr.w r3, r3, sl, lsr #29 + 8003184: ea4f 02ca mov.w r2, sl, lsl #3 + 8003188: 4692 mov sl, r2 + 800318a: 469b mov fp, r3 + 800318c: 4643 mov r3, r8 + 800318e: eb1a 0303 adds.w r3, sl, r3 + 8003192: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 + 8003196: 464b mov r3, r9 + 8003198: eb4b 0303 adc.w r3, fp, r3 + 800319c: f8c7 30cc str.w r3, [r7, #204] ; 0xcc + 80031a0: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 80031a4: 685b ldr r3, [r3, #4] + 80031a6: 2200 movs r2, #0 + 80031a8: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 + 80031ac: f8c7 20c4 str.w r2, [r7, #196] ; 0xc4 + 80031b0: e9d7 1230 ldrd r1, r2, [r7, #192] ; 0xc0 + 80031b4: 460b mov r3, r1 + 80031b6: 18db adds r3, r3, r3 + 80031b8: 643b str r3, [r7, #64] ; 0x40 + 80031ba: 4613 mov r3, r2 + 80031bc: eb42 0303 adc.w r3, r2, r3 + 80031c0: 647b str r3, [r7, #68] ; 0x44 + 80031c2: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40 + 80031c6: e9d7 0132 ldrd r0, r1, [r7, #200] ; 0xc8 + 80031ca: f7fd f809 bl 80001e0 <__aeabi_uldivmod> + 80031ce: 4602 mov r2, r0 + 80031d0: 460b mov r3, r1 + 80031d2: 4611 mov r1, r2 + 80031d4: 4b3b ldr r3, [pc, #236] ; (80032c4 ) + 80031d6: fba3 2301 umull r2, r3, r3, r1 + 80031da: 095b lsrs r3, r3, #5 + 80031dc: 2264 movs r2, #100 ; 0x64 + 80031de: fb02 f303 mul.w r3, r2, r3 + 80031e2: 1acb subs r3, r1, r3 + 80031e4: 00db lsls r3, r3, #3 + 80031e6: f103 0232 add.w r2, r3, #50 ; 0x32 + 80031ea: 4b36 ldr r3, [pc, #216] ; (80032c4 ) + 80031ec: fba3 2302 umull r2, r3, r3, r2 + 80031f0: 095b lsrs r3, r3, #5 + 80031f2: 005b lsls r3, r3, #1 + 80031f4: f403 73f8 and.w r3, r3, #496 ; 0x1f0 + 80031f8: 441c add r4, r3 + 80031fa: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 80031fe: 2200 movs r2, #0 + 8003200: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + 8003204: f8c7 20bc str.w r2, [r7, #188] ; 0xbc + 8003208: e9d7 892e ldrd r8, r9, [r7, #184] ; 0xb8 + 800320c: 4642 mov r2, r8 + 800320e: 464b mov r3, r9 + 8003210: 1891 adds r1, r2, r2 + 8003212: 63b9 str r1, [r7, #56] ; 0x38 + 8003214: 415b adcs r3, r3 + 8003216: 63fb str r3, [r7, #60] ; 0x3c + 8003218: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 + 800321c: 4641 mov r1, r8 + 800321e: 1851 adds r1, r2, r1 + 8003220: 6339 str r1, [r7, #48] ; 0x30 + 8003222: 4649 mov r1, r9 + 8003224: 414b adcs r3, r1 + 8003226: 637b str r3, [r7, #52] ; 0x34 + 8003228: f04f 0200 mov.w r2, #0 + 800322c: f04f 0300 mov.w r3, #0 + 8003230: e9d7 ab0c ldrd sl, fp, [r7, #48] ; 0x30 + 8003234: 4659 mov r1, fp + 8003236: 00cb lsls r3, r1, #3 + 8003238: 4651 mov r1, sl + 800323a: ea43 7351 orr.w r3, r3, r1, lsr #29 + 800323e: 4651 mov r1, sl + 8003240: 00ca lsls r2, r1, #3 + 8003242: 4610 mov r0, r2 + 8003244: 4619 mov r1, r3 + 8003246: 4603 mov r3, r0 + 8003248: 4642 mov r2, r8 + 800324a: 189b adds r3, r3, r2 + 800324c: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + 8003250: 464b mov r3, r9 + 8003252: 460a mov r2, r1 + 8003254: eb42 0303 adc.w r3, r2, r3 + 8003258: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + 800325c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003260: 685b ldr r3, [r3, #4] + 8003262: 2200 movs r2, #0 + 8003264: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + 8003268: f8c7 20ac str.w r2, [r7, #172] ; 0xac + 800326c: e9d7 122a ldrd r1, r2, [r7, #168] ; 0xa8 + 8003270: 460b mov r3, r1 + 8003272: 18db adds r3, r3, r3 + 8003274: 62bb str r3, [r7, #40] ; 0x28 + 8003276: 4613 mov r3, r2 + 8003278: eb42 0303 adc.w r3, r2, r3 + 800327c: 62fb str r3, [r7, #44] ; 0x2c + 800327e: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 + 8003282: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0 + 8003286: f7fc ffab bl 80001e0 <__aeabi_uldivmod> + 800328a: 4602 mov r2, r0 + 800328c: 460b mov r3, r1 + 800328e: 4b0d ldr r3, [pc, #52] ; (80032c4 ) + 8003290: fba3 1302 umull r1, r3, r3, r2 + 8003294: 095b lsrs r3, r3, #5 + 8003296: 2164 movs r1, #100 ; 0x64 + 8003298: fb01 f303 mul.w r3, r1, r3 + 800329c: 1ad3 subs r3, r2, r3 + 800329e: 00db lsls r3, r3, #3 + 80032a0: 3332 adds r3, #50 ; 0x32 + 80032a2: 4a08 ldr r2, [pc, #32] ; (80032c4 ) + 80032a4: fba2 2303 umull r2, r3, r2, r3 + 80032a8: 095b lsrs r3, r3, #5 + 80032aa: f003 0207 and.w r2, r3, #7 + 80032ae: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 80032b2: 681b ldr r3, [r3, #0] + 80032b4: 4422 add r2, r4 + 80032b6: 609a str r2, [r3, #8] } else { huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); } } - 8002774: e106 b.n 8002984 - 8002776: bf00 nop - 8002778: 40011000 .word 0x40011000 - 800277c: 40011400 .word 0x40011400 - 8002780: 51eb851f .word 0x51eb851f + 80032b8: e106 b.n 80034c8 + 80032ba: bf00 nop + 80032bc: 40011000 .word 0x40011000 + 80032c0: 40011400 .word 0x40011400 + 80032c4: 51eb851f .word 0x51eb851f huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate); - 8002784: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 8002788: 2200 movs r2, #0 - 800278a: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 - 800278e: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4 - 8002792: e9d7 8928 ldrd r8, r9, [r7, #160] ; 0xa0 - 8002796: 4642 mov r2, r8 - 8002798: 464b mov r3, r9 - 800279a: 1891 adds r1, r2, r2 - 800279c: 6239 str r1, [r7, #32] - 800279e: 415b adcs r3, r3 - 80027a0: 627b str r3, [r7, #36] ; 0x24 - 80027a2: e9d7 2308 ldrd r2, r3, [r7, #32] - 80027a6: 4641 mov r1, r8 - 80027a8: 1854 adds r4, r2, r1 - 80027aa: 4649 mov r1, r9 - 80027ac: eb43 0501 adc.w r5, r3, r1 - 80027b0: f04f 0200 mov.w r2, #0 - 80027b4: f04f 0300 mov.w r3, #0 - 80027b8: 00eb lsls r3, r5, #3 - 80027ba: ea43 7354 orr.w r3, r3, r4, lsr #29 - 80027be: 00e2 lsls r2, r4, #3 - 80027c0: 4614 mov r4, r2 - 80027c2: 461d mov r5, r3 - 80027c4: 4643 mov r3, r8 - 80027c6: 18e3 adds r3, r4, r3 - 80027c8: f8c7 3098 str.w r3, [r7, #152] ; 0x98 - 80027cc: 464b mov r3, r9 - 80027ce: eb45 0303 adc.w r3, r5, r3 - 80027d2: f8c7 309c str.w r3, [r7, #156] ; 0x9c - 80027d6: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 80027da: 685b ldr r3, [r3, #4] - 80027dc: 2200 movs r2, #0 - 80027de: f8c7 3090 str.w r3, [r7, #144] ; 0x90 - 80027e2: f8c7 2094 str.w r2, [r7, #148] ; 0x94 - 80027e6: f04f 0200 mov.w r2, #0 - 80027ea: f04f 0300 mov.w r3, #0 - 80027ee: e9d7 4524 ldrd r4, r5, [r7, #144] ; 0x90 - 80027f2: 4629 mov r1, r5 - 80027f4: 008b lsls r3, r1, #2 - 80027f6: 4621 mov r1, r4 - 80027f8: ea43 7391 orr.w r3, r3, r1, lsr #30 - 80027fc: 4621 mov r1, r4 - 80027fe: 008a lsls r2, r1, #2 - 8002800: e9d7 0126 ldrd r0, r1, [r7, #152] ; 0x98 - 8002804: f7fd fcec bl 80001e0 <__aeabi_uldivmod> - 8002808: 4602 mov r2, r0 - 800280a: 460b mov r3, r1 - 800280c: 4b60 ldr r3, [pc, #384] ; (8002990 ) - 800280e: fba3 2302 umull r2, r3, r3, r2 - 8002812: 095b lsrs r3, r3, #5 - 8002814: 011c lsls r4, r3, #4 - 8002816: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 800281a: 2200 movs r2, #0 - 800281c: f8c7 3088 str.w r3, [r7, #136] ; 0x88 - 8002820: f8c7 208c str.w r2, [r7, #140] ; 0x8c - 8002824: e9d7 8922 ldrd r8, r9, [r7, #136] ; 0x88 - 8002828: 4642 mov r2, r8 - 800282a: 464b mov r3, r9 - 800282c: 1891 adds r1, r2, r2 - 800282e: 61b9 str r1, [r7, #24] - 8002830: 415b adcs r3, r3 - 8002832: 61fb str r3, [r7, #28] - 8002834: e9d7 2306 ldrd r2, r3, [r7, #24] - 8002838: 4641 mov r1, r8 - 800283a: 1851 adds r1, r2, r1 - 800283c: 6139 str r1, [r7, #16] - 800283e: 4649 mov r1, r9 - 8002840: 414b adcs r3, r1 - 8002842: 617b str r3, [r7, #20] - 8002844: f04f 0200 mov.w r2, #0 - 8002848: f04f 0300 mov.w r3, #0 - 800284c: e9d7 ab04 ldrd sl, fp, [r7, #16] - 8002850: 4659 mov r1, fp - 8002852: 00cb lsls r3, r1, #3 - 8002854: 4651 mov r1, sl - 8002856: ea43 7351 orr.w r3, r3, r1, lsr #29 - 800285a: 4651 mov r1, sl - 800285c: 00ca lsls r2, r1, #3 - 800285e: 4610 mov r0, r2 - 8002860: 4619 mov r1, r3 - 8002862: 4603 mov r3, r0 - 8002864: 4642 mov r2, r8 - 8002866: 189b adds r3, r3, r2 - 8002868: f8c7 3080 str.w r3, [r7, #128] ; 0x80 - 800286c: 464b mov r3, r9 - 800286e: 460a mov r2, r1 - 8002870: eb42 0303 adc.w r3, r2, r3 - 8002874: f8c7 3084 str.w r3, [r7, #132] ; 0x84 - 8002878: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800287c: 685b ldr r3, [r3, #4] - 800287e: 2200 movs r2, #0 - 8002880: 67bb str r3, [r7, #120] ; 0x78 - 8002882: 67fa str r2, [r7, #124] ; 0x7c - 8002884: f04f 0200 mov.w r2, #0 - 8002888: f04f 0300 mov.w r3, #0 - 800288c: e9d7 891e ldrd r8, r9, [r7, #120] ; 0x78 - 8002890: 4649 mov r1, r9 - 8002892: 008b lsls r3, r1, #2 - 8002894: 4641 mov r1, r8 - 8002896: ea43 7391 orr.w r3, r3, r1, lsr #30 - 800289a: 4641 mov r1, r8 - 800289c: 008a lsls r2, r1, #2 - 800289e: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80 - 80028a2: f7fd fc9d bl 80001e0 <__aeabi_uldivmod> - 80028a6: 4602 mov r2, r0 - 80028a8: 460b mov r3, r1 - 80028aa: 4611 mov r1, r2 - 80028ac: 4b38 ldr r3, [pc, #224] ; (8002990 ) - 80028ae: fba3 2301 umull r2, r3, r3, r1 - 80028b2: 095b lsrs r3, r3, #5 - 80028b4: 2264 movs r2, #100 ; 0x64 - 80028b6: fb02 f303 mul.w r3, r2, r3 - 80028ba: 1acb subs r3, r1, r3 - 80028bc: 011b lsls r3, r3, #4 - 80028be: 3332 adds r3, #50 ; 0x32 - 80028c0: 4a33 ldr r2, [pc, #204] ; (8002990 ) - 80028c2: fba2 2303 umull r2, r3, r2, r3 - 80028c6: 095b lsrs r3, r3, #5 - 80028c8: f003 03f0 and.w r3, r3, #240 ; 0xf0 - 80028cc: 441c add r4, r3 - 80028ce: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc - 80028d2: 2200 movs r2, #0 - 80028d4: 673b str r3, [r7, #112] ; 0x70 - 80028d6: 677a str r2, [r7, #116] ; 0x74 - 80028d8: e9d7 891c ldrd r8, r9, [r7, #112] ; 0x70 - 80028dc: 4642 mov r2, r8 - 80028de: 464b mov r3, r9 - 80028e0: 1891 adds r1, r2, r2 - 80028e2: 60b9 str r1, [r7, #8] - 80028e4: 415b adcs r3, r3 - 80028e6: 60fb str r3, [r7, #12] - 80028e8: e9d7 2302 ldrd r2, r3, [r7, #8] - 80028ec: 4641 mov r1, r8 - 80028ee: 1851 adds r1, r2, r1 - 80028f0: 6039 str r1, [r7, #0] - 80028f2: 4649 mov r1, r9 - 80028f4: 414b adcs r3, r1 - 80028f6: 607b str r3, [r7, #4] - 80028f8: f04f 0200 mov.w r2, #0 - 80028fc: f04f 0300 mov.w r3, #0 - 8002900: e9d7 ab00 ldrd sl, fp, [r7] - 8002904: 4659 mov r1, fp - 8002906: 00cb lsls r3, r1, #3 - 8002908: 4651 mov r1, sl - 800290a: ea43 7351 orr.w r3, r3, r1, lsr #29 - 800290e: 4651 mov r1, sl - 8002910: 00ca lsls r2, r1, #3 - 8002912: 4610 mov r0, r2 - 8002914: 4619 mov r1, r3 - 8002916: 4603 mov r3, r0 - 8002918: 4642 mov r2, r8 - 800291a: 189b adds r3, r3, r2 - 800291c: 66bb str r3, [r7, #104] ; 0x68 - 800291e: 464b mov r3, r9 - 8002920: 460a mov r2, r1 - 8002922: eb42 0303 adc.w r3, r2, r3 - 8002926: 66fb str r3, [r7, #108] ; 0x6c - 8002928: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800292c: 685b ldr r3, [r3, #4] - 800292e: 2200 movs r2, #0 - 8002930: 663b str r3, [r7, #96] ; 0x60 - 8002932: 667a str r2, [r7, #100] ; 0x64 - 8002934: f04f 0200 mov.w r2, #0 - 8002938: f04f 0300 mov.w r3, #0 - 800293c: e9d7 8918 ldrd r8, r9, [r7, #96] ; 0x60 - 8002940: 4649 mov r1, r9 - 8002942: 008b lsls r3, r1, #2 - 8002944: 4641 mov r1, r8 - 8002946: ea43 7391 orr.w r3, r3, r1, lsr #30 - 800294a: 4641 mov r1, r8 - 800294c: 008a lsls r2, r1, #2 - 800294e: e9d7 011a ldrd r0, r1, [r7, #104] ; 0x68 - 8002952: f7fd fc45 bl 80001e0 <__aeabi_uldivmod> - 8002956: 4602 mov r2, r0 - 8002958: 460b mov r3, r1 - 800295a: 4b0d ldr r3, [pc, #52] ; (8002990 ) - 800295c: fba3 1302 umull r1, r3, r3, r2 - 8002960: 095b lsrs r3, r3, #5 - 8002962: 2164 movs r1, #100 ; 0x64 - 8002964: fb01 f303 mul.w r3, r1, r3 - 8002968: 1ad3 subs r3, r2, r3 - 800296a: 011b lsls r3, r3, #4 - 800296c: 3332 adds r3, #50 ; 0x32 - 800296e: 4a08 ldr r2, [pc, #32] ; (8002990 ) - 8002970: fba2 2303 umull r2, r3, r2, r3 - 8002974: 095b lsrs r3, r3, #5 - 8002976: f003 020f and.w r2, r3, #15 - 800297a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 - 800297e: 681b ldr r3, [r3, #0] - 8002980: 4422 add r2, r4 - 8002982: 609a str r2, [r3, #8] + 80032c8: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 80032cc: 2200 movs r2, #0 + 80032ce: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + 80032d2: f8c7 20a4 str.w r2, [r7, #164] ; 0xa4 + 80032d6: e9d7 8928 ldrd r8, r9, [r7, #160] ; 0xa0 + 80032da: 4642 mov r2, r8 + 80032dc: 464b mov r3, r9 + 80032de: 1891 adds r1, r2, r2 + 80032e0: 6239 str r1, [r7, #32] + 80032e2: 415b adcs r3, r3 + 80032e4: 627b str r3, [r7, #36] ; 0x24 + 80032e6: e9d7 2308 ldrd r2, r3, [r7, #32] + 80032ea: 4641 mov r1, r8 + 80032ec: 1854 adds r4, r2, r1 + 80032ee: 4649 mov r1, r9 + 80032f0: eb43 0501 adc.w r5, r3, r1 + 80032f4: f04f 0200 mov.w r2, #0 + 80032f8: f04f 0300 mov.w r3, #0 + 80032fc: 00eb lsls r3, r5, #3 + 80032fe: ea43 7354 orr.w r3, r3, r4, lsr #29 + 8003302: 00e2 lsls r2, r4, #3 + 8003304: 4614 mov r4, r2 + 8003306: 461d mov r5, r3 + 8003308: 4643 mov r3, r8 + 800330a: 18e3 adds r3, r4, r3 + 800330c: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + 8003310: 464b mov r3, r9 + 8003312: eb45 0303 adc.w r3, r5, r3 + 8003316: f8c7 309c str.w r3, [r7, #156] ; 0x9c + 800331a: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 800331e: 685b ldr r3, [r3, #4] + 8003320: 2200 movs r2, #0 + 8003322: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + 8003326: f8c7 2094 str.w r2, [r7, #148] ; 0x94 + 800332a: f04f 0200 mov.w r2, #0 + 800332e: f04f 0300 mov.w r3, #0 + 8003332: e9d7 4524 ldrd r4, r5, [r7, #144] ; 0x90 + 8003336: 4629 mov r1, r5 + 8003338: 008b lsls r3, r1, #2 + 800333a: 4621 mov r1, r4 + 800333c: ea43 7391 orr.w r3, r3, r1, lsr #30 + 8003340: 4621 mov r1, r4 + 8003342: 008a lsls r2, r1, #2 + 8003344: e9d7 0126 ldrd r0, r1, [r7, #152] ; 0x98 + 8003348: f7fc ff4a bl 80001e0 <__aeabi_uldivmod> + 800334c: 4602 mov r2, r0 + 800334e: 460b mov r3, r1 + 8003350: 4b60 ldr r3, [pc, #384] ; (80034d4 ) + 8003352: fba3 2302 umull r2, r3, r3, r2 + 8003356: 095b lsrs r3, r3, #5 + 8003358: 011c lsls r4, r3, #4 + 800335a: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 800335e: 2200 movs r2, #0 + 8003360: f8c7 3088 str.w r3, [r7, #136] ; 0x88 + 8003364: f8c7 208c str.w r2, [r7, #140] ; 0x8c + 8003368: e9d7 8922 ldrd r8, r9, [r7, #136] ; 0x88 + 800336c: 4642 mov r2, r8 + 800336e: 464b mov r3, r9 + 8003370: 1891 adds r1, r2, r2 + 8003372: 61b9 str r1, [r7, #24] + 8003374: 415b adcs r3, r3 + 8003376: 61fb str r3, [r7, #28] + 8003378: e9d7 2306 ldrd r2, r3, [r7, #24] + 800337c: 4641 mov r1, r8 + 800337e: 1851 adds r1, r2, r1 + 8003380: 6139 str r1, [r7, #16] + 8003382: 4649 mov r1, r9 + 8003384: 414b adcs r3, r1 + 8003386: 617b str r3, [r7, #20] + 8003388: f04f 0200 mov.w r2, #0 + 800338c: f04f 0300 mov.w r3, #0 + 8003390: e9d7 ab04 ldrd sl, fp, [r7, #16] + 8003394: 4659 mov r1, fp + 8003396: 00cb lsls r3, r1, #3 + 8003398: 4651 mov r1, sl + 800339a: ea43 7351 orr.w r3, r3, r1, lsr #29 + 800339e: 4651 mov r1, sl + 80033a0: 00ca lsls r2, r1, #3 + 80033a2: 4610 mov r0, r2 + 80033a4: 4619 mov r1, r3 + 80033a6: 4603 mov r3, r0 + 80033a8: 4642 mov r2, r8 + 80033aa: 189b adds r3, r3, r2 + 80033ac: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + 80033b0: 464b mov r3, r9 + 80033b2: 460a mov r2, r1 + 80033b4: eb42 0303 adc.w r3, r2, r3 + 80033b8: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 80033bc: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 80033c0: 685b ldr r3, [r3, #4] + 80033c2: 2200 movs r2, #0 + 80033c4: 67bb str r3, [r7, #120] ; 0x78 + 80033c6: 67fa str r2, [r7, #124] ; 0x7c + 80033c8: f04f 0200 mov.w r2, #0 + 80033cc: f04f 0300 mov.w r3, #0 + 80033d0: e9d7 891e ldrd r8, r9, [r7, #120] ; 0x78 + 80033d4: 4649 mov r1, r9 + 80033d6: 008b lsls r3, r1, #2 + 80033d8: 4641 mov r1, r8 + 80033da: ea43 7391 orr.w r3, r3, r1, lsr #30 + 80033de: 4641 mov r1, r8 + 80033e0: 008a lsls r2, r1, #2 + 80033e2: e9d7 0120 ldrd r0, r1, [r7, #128] ; 0x80 + 80033e6: f7fc fefb bl 80001e0 <__aeabi_uldivmod> + 80033ea: 4602 mov r2, r0 + 80033ec: 460b mov r3, r1 + 80033ee: 4611 mov r1, r2 + 80033f0: 4b38 ldr r3, [pc, #224] ; (80034d4 ) + 80033f2: fba3 2301 umull r2, r3, r3, r1 + 80033f6: 095b lsrs r3, r3, #5 + 80033f8: 2264 movs r2, #100 ; 0x64 + 80033fa: fb02 f303 mul.w r3, r2, r3 + 80033fe: 1acb subs r3, r1, r3 + 8003400: 011b lsls r3, r3, #4 + 8003402: 3332 adds r3, #50 ; 0x32 + 8003404: 4a33 ldr r2, [pc, #204] ; (80034d4 ) + 8003406: fba2 2303 umull r2, r3, r2, r3 + 800340a: 095b lsrs r3, r3, #5 + 800340c: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 8003410: 441c add r4, r3 + 8003412: f8d7 30fc ldr.w r3, [r7, #252] ; 0xfc + 8003416: 2200 movs r2, #0 + 8003418: 673b str r3, [r7, #112] ; 0x70 + 800341a: 677a str r2, [r7, #116] ; 0x74 + 800341c: e9d7 891c ldrd r8, r9, [r7, #112] ; 0x70 + 8003420: 4642 mov r2, r8 + 8003422: 464b mov r3, r9 + 8003424: 1891 adds r1, r2, r2 + 8003426: 60b9 str r1, [r7, #8] + 8003428: 415b adcs r3, r3 + 800342a: 60fb str r3, [r7, #12] + 800342c: e9d7 2302 ldrd r2, r3, [r7, #8] + 8003430: 4641 mov r1, r8 + 8003432: 1851 adds r1, r2, r1 + 8003434: 6039 str r1, [r7, #0] + 8003436: 4649 mov r1, r9 + 8003438: 414b adcs r3, r1 + 800343a: 607b str r3, [r7, #4] + 800343c: f04f 0200 mov.w r2, #0 + 8003440: f04f 0300 mov.w r3, #0 + 8003444: e9d7 ab00 ldrd sl, fp, [r7] + 8003448: 4659 mov r1, fp + 800344a: 00cb lsls r3, r1, #3 + 800344c: 4651 mov r1, sl + 800344e: ea43 7351 orr.w r3, r3, r1, lsr #29 + 8003452: 4651 mov r1, sl + 8003454: 00ca lsls r2, r1, #3 + 8003456: 4610 mov r0, r2 + 8003458: 4619 mov r1, r3 + 800345a: 4603 mov r3, r0 + 800345c: 4642 mov r2, r8 + 800345e: 189b adds r3, r3, r2 + 8003460: 66bb str r3, [r7, #104] ; 0x68 + 8003462: 464b mov r3, r9 + 8003464: 460a mov r2, r1 + 8003466: eb42 0303 adc.w r3, r2, r3 + 800346a: 66fb str r3, [r7, #108] ; 0x6c + 800346c: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 8003470: 685b ldr r3, [r3, #4] + 8003472: 2200 movs r2, #0 + 8003474: 663b str r3, [r7, #96] ; 0x60 + 8003476: 667a str r2, [r7, #100] ; 0x64 + 8003478: f04f 0200 mov.w r2, #0 + 800347c: f04f 0300 mov.w r3, #0 + 8003480: e9d7 8918 ldrd r8, r9, [r7, #96] ; 0x60 + 8003484: 4649 mov r1, r9 + 8003486: 008b lsls r3, r1, #2 + 8003488: 4641 mov r1, r8 + 800348a: ea43 7391 orr.w r3, r3, r1, lsr #30 + 800348e: 4641 mov r1, r8 + 8003490: 008a lsls r2, r1, #2 + 8003492: e9d7 011a ldrd r0, r1, [r7, #104] ; 0x68 + 8003496: f7fc fea3 bl 80001e0 <__aeabi_uldivmod> + 800349a: 4602 mov r2, r0 + 800349c: 460b mov r3, r1 + 800349e: 4b0d ldr r3, [pc, #52] ; (80034d4 ) + 80034a0: fba3 1302 umull r1, r3, r3, r2 + 80034a4: 095b lsrs r3, r3, #5 + 80034a6: 2164 movs r1, #100 ; 0x64 + 80034a8: fb01 f303 mul.w r3, r1, r3 + 80034ac: 1ad3 subs r3, r2, r3 + 80034ae: 011b lsls r3, r3, #4 + 80034b0: 3332 adds r3, #50 ; 0x32 + 80034b2: 4a08 ldr r2, [pc, #32] ; (80034d4 ) + 80034b4: fba2 2303 umull r2, r3, r2, r3 + 80034b8: 095b lsrs r3, r3, #5 + 80034ba: f003 020f and.w r2, r3, #15 + 80034be: f8d7 30f4 ldr.w r3, [r7, #244] ; 0xf4 + 80034c2: 681b ldr r3, [r3, #0] + 80034c4: 4422 add r2, r4 + 80034c6: 609a str r2, [r3, #8] } - 8002984: bf00 nop - 8002986: f507 7780 add.w r7, r7, #256 ; 0x100 - 800298a: 46bd mov sp, r7 - 800298c: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} - 8002990: 51eb851f .word 0x51eb851f + 80034c8: bf00 nop + 80034ca: f507 7780 add.w r7, r7, #256 ; 0x100 + 80034ce: 46bd mov sp, r7 + 80034d0: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 80034d4: 51eb851f .word 0x51eb851f -08002994 <__NVIC_SetPriority>: +080034d8 <__NVIC_SetPriority>: { - 8002994: b480 push {r7} - 8002996: b083 sub sp, #12 - 8002998: af00 add r7, sp, #0 - 800299a: 4603 mov r3, r0 - 800299c: 6039 str r1, [r7, #0] - 800299e: 71fb strb r3, [r7, #7] + 80034d8: b480 push {r7} + 80034da: b083 sub sp, #12 + 80034dc: af00 add r7, sp, #0 + 80034de: 4603 mov r3, r0 + 80034e0: 6039 str r1, [r7, #0] + 80034e2: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) >= 0) - 80029a0: f997 3007 ldrsb.w r3, [r7, #7] - 80029a4: 2b00 cmp r3, #0 - 80029a6: db0a blt.n 80029be <__NVIC_SetPriority+0x2a> + 80034e4: f997 3007 ldrsb.w r3, [r7, #7] + 80034e8: 2b00 cmp r3, #0 + 80034ea: db0a blt.n 8003502 <__NVIC_SetPriority+0x2a> NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80029a8: 683b ldr r3, [r7, #0] - 80029aa: b2da uxtb r2, r3 - 80029ac: 490c ldr r1, [pc, #48] ; (80029e0 <__NVIC_SetPriority+0x4c>) - 80029ae: f997 3007 ldrsb.w r3, [r7, #7] - 80029b2: 0112 lsls r2, r2, #4 - 80029b4: b2d2 uxtb r2, r2 - 80029b6: 440b add r3, r1 - 80029b8: f883 2300 strb.w r2, [r3, #768] ; 0x300 + 80034ec: 683b ldr r3, [r7, #0] + 80034ee: b2da uxtb r2, r3 + 80034f0: 490c ldr r1, [pc, #48] ; (8003524 <__NVIC_SetPriority+0x4c>) + 80034f2: f997 3007 ldrsb.w r3, [r7, #7] + 80034f6: 0112 lsls r2, r2, #4 + 80034f8: b2d2 uxtb r2, r2 + 80034fa: 440b add r3, r1 + 80034fc: f883 2300 strb.w r2, [r3, #768] ; 0x300 } - 80029bc: e00a b.n 80029d4 <__NVIC_SetPriority+0x40> + 8003500: e00a b.n 8003518 <__NVIC_SetPriority+0x40> SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - 80029be: 683b ldr r3, [r7, #0] - 80029c0: b2da uxtb r2, r3 - 80029c2: 4908 ldr r1, [pc, #32] ; (80029e4 <__NVIC_SetPriority+0x50>) - 80029c4: 79fb ldrb r3, [r7, #7] - 80029c6: f003 030f and.w r3, r3, #15 - 80029ca: 3b04 subs r3, #4 - 80029cc: 0112 lsls r2, r2, #4 - 80029ce: b2d2 uxtb r2, r2 - 80029d0: 440b add r3, r1 - 80029d2: 761a strb r2, [r3, #24] + 8003502: 683b ldr r3, [r7, #0] + 8003504: b2da uxtb r2, r3 + 8003506: 4908 ldr r1, [pc, #32] ; (8003528 <__NVIC_SetPriority+0x50>) + 8003508: 79fb ldrb r3, [r7, #7] + 800350a: f003 030f and.w r3, r3, #15 + 800350e: 3b04 subs r3, #4 + 8003510: 0112 lsls r2, r2, #4 + 8003512: b2d2 uxtb r2, r2 + 8003514: 440b add r3, r1 + 8003516: 761a strb r2, [r3, #24] } - 80029d4: bf00 nop - 80029d6: 370c adds r7, #12 - 80029d8: 46bd mov sp, r7 - 80029da: f85d 7b04 ldr.w r7, [sp], #4 - 80029de: 4770 bx lr - 80029e0: e000e100 .word 0xe000e100 - 80029e4: e000ed00 .word 0xe000ed00 + 8003518: bf00 nop + 800351a: 370c adds r7, #12 + 800351c: 46bd mov sp, r7 + 800351e: f85d 7b04 ldr.w r7, [sp], #4 + 8003522: 4770 bx lr + 8003524: e000e100 .word 0xe000e100 + 8003528: e000ed00 .word 0xe000ed00 -080029e8 : +0800352c : /* SysTick handler implementation that also clears overflow flag. */ #if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0) void SysTick_Handler (void) { - 80029e8: b580 push {r7, lr} - 80029ea: af00 add r7, sp, #0 + 800352c: b580 push {r7, lr} + 800352e: af00 add r7, sp, #0 /* Clear overflow flag */ SysTick->CTRL; - 80029ec: 4b05 ldr r3, [pc, #20] ; (8002a04 ) - 80029ee: 681b ldr r3, [r3, #0] + 8003530: 4b05 ldr r3, [pc, #20] ; (8003548 ) + 8003532: 681b ldr r3, [r3, #0] if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) { - 80029f0: f001 fd0c bl 800440c - 80029f4: 4603 mov r3, r0 - 80029f6: 2b01 cmp r3, #1 - 80029f8: d001 beq.n 80029fe + 8003534: f001 fd28 bl 8004f88 + 8003538: 4603 mov r3, r0 + 800353a: 2b01 cmp r3, #1 + 800353c: d001 beq.n 8003542 /* Call tick handler */ xPortSysTickHandler(); - 80029fa: f002 faf5 bl 8004fe8 + 800353e: f002 fb13 bl 8005b68 } } - 80029fe: bf00 nop - 8002a00: bd80 pop {r7, pc} - 8002a02: bf00 nop - 8002a04: e000e010 .word 0xe000e010 + 8003542: bf00 nop + 8003544: bd80 pop {r7, pc} + 8003546: bf00 nop + 8003548: e000e010 .word 0xe000e010 -08002a08 : +0800354c : #endif /* SysTick */ /* Setup SVC to reset value. */ __STATIC_INLINE void SVC_Setup (void) { - 8002a08: b580 push {r7, lr} - 8002a0a: af00 add r7, sp, #0 + 800354c: b580 push {r7, lr} + 800354e: af00 add r7, sp, #0 #if (__ARM_ARCH_7A__ == 0U) /* Service Call interrupt might be configured before kernel start */ /* and when its priority is lower or equal to BASEPRI, svc intruction */ /* causes a Hard Fault. */ NVIC_SetPriority (SVCall_IRQ_NBR, 0U); - 8002a0c: 2100 movs r1, #0 - 8002a0e: f06f 0004 mvn.w r0, #4 - 8002a12: f7ff ffbf bl 8002994 <__NVIC_SetPriority> + 8003550: 2100 movs r1, #0 + 8003552: f06f 0004 mvn.w r0, #4 + 8003556: f7ff ffbf bl 80034d8 <__NVIC_SetPriority> #endif } - 8002a16: bf00 nop - 8002a18: bd80 pop {r7, pc} + 800355a: bf00 nop + 800355c: bd80 pop {r7, pc} ... -08002a1c : +08003560 : static uint32_t OS_Tick_GetOverflow (void); /* Get OS Tick interval */ static uint32_t OS_Tick_GetInterval (void); /*---------------------------------------------------------------------------*/ osStatus_t osKernelInitialize (void) { - 8002a1c: b480 push {r7} - 8002a1e: b083 sub sp, #12 - 8002a20: af00 add r7, sp, #0 + 8003560: b480 push {r7} + 8003562: b083 sub sp, #12 + 8003564: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - 8002a22: f3ef 8305 mrs r3, IPSR - 8002a26: 603b str r3, [r7, #0] + 8003566: f3ef 8305 mrs r3, IPSR + 800356a: 603b str r3, [r7, #0] return(result); - 8002a28: 683b ldr r3, [r7, #0] + 800356c: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { - 8002a2a: 2b00 cmp r3, #0 - 8002a2c: d003 beq.n 8002a36 + 800356e: 2b00 cmp r3, #0 + 8003570: d003 beq.n 800357a stat = osErrorISR; - 8002a2e: f06f 0305 mvn.w r3, #5 - 8002a32: 607b str r3, [r7, #4] - 8002a34: e00c b.n 8002a50 + 8003572: f06f 0305 mvn.w r3, #5 + 8003576: 607b str r3, [r7, #4] + 8003578: e00c b.n 8003594 } else { if (KernelState == osKernelInactive) { - 8002a36: 4b0a ldr r3, [pc, #40] ; (8002a60 ) - 8002a38: 681b ldr r3, [r3, #0] - 8002a3a: 2b00 cmp r3, #0 - 8002a3c: d105 bne.n 8002a4a + 800357a: 4b0a ldr r3, [pc, #40] ; (80035a4 ) + 800357c: 681b ldr r3, [r3, #0] + 800357e: 2b00 cmp r3, #0 + 8003580: d105 bne.n 800358e EvrFreeRTOSSetup(0U); #endif #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1) vPortDefineHeapRegions (configHEAP_5_REGIONS); #endif KernelState = osKernelReady; - 8002a3e: 4b08 ldr r3, [pc, #32] ; (8002a60 ) - 8002a40: 2201 movs r2, #1 - 8002a42: 601a str r2, [r3, #0] + 8003582: 4b08 ldr r3, [pc, #32] ; (80035a4 ) + 8003584: 2201 movs r2, #1 + 8003586: 601a str r2, [r3, #0] stat = osOK; - 8002a44: 2300 movs r3, #0 - 8002a46: 607b str r3, [r7, #4] - 8002a48: e002 b.n 8002a50 + 8003588: 2300 movs r3, #0 + 800358a: 607b str r3, [r7, #4] + 800358c: e002 b.n 8003594 } else { stat = osError; - 8002a4a: f04f 33ff mov.w r3, #4294967295 - 8002a4e: 607b str r3, [r7, #4] + 800358e: f04f 33ff mov.w r3, #4294967295 + 8003592: 607b str r3, [r7, #4] } } return (stat); - 8002a50: 687b ldr r3, [r7, #4] + 8003594: 687b ldr r3, [r7, #4] } - 8002a52: 4618 mov r0, r3 - 8002a54: 370c adds r7, #12 - 8002a56: 46bd mov sp, r7 - 8002a58: f85d 7b04 ldr.w r7, [sp], #4 - 8002a5c: 4770 bx lr - 8002a5e: bf00 nop - 8002a60: 2000012c .word 0x2000012c + 8003596: 4618 mov r0, r3 + 8003598: 370c adds r7, #12 + 800359a: 46bd mov sp, r7 + 800359c: f85d 7b04 ldr.w r7, [sp], #4 + 80035a0: 4770 bx lr + 80035a2: bf00 nop + 80035a4: 2000017c .word 0x2000017c -08002a64 : +080035a8 : } return (state); } osStatus_t osKernelStart (void) { - 8002a64: b580 push {r7, lr} - 8002a66: b082 sub sp, #8 - 8002a68: af00 add r7, sp, #0 + 80035a8: b580 push {r7, lr} + 80035aa: b082 sub sp, #8 + 80035ac: af00 add r7, sp, #0 __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - 8002a6a: f3ef 8305 mrs r3, IPSR - 8002a6e: 603b str r3, [r7, #0] + 80035ae: f3ef 8305 mrs r3, IPSR + 80035b2: 603b str r3, [r7, #0] return(result); - 8002a70: 683b ldr r3, [r7, #0] + 80035b4: 683b ldr r3, [r7, #0] osStatus_t stat; if (IS_IRQ()) { - 8002a72: 2b00 cmp r3, #0 - 8002a74: d003 beq.n 8002a7e + 80035b6: 2b00 cmp r3, #0 + 80035b8: d003 beq.n 80035c2 stat = osErrorISR; - 8002a76: f06f 0305 mvn.w r3, #5 - 8002a7a: 607b str r3, [r7, #4] - 8002a7c: e010 b.n 8002aa0 + 80035ba: f06f 0305 mvn.w r3, #5 + 80035be: 607b str r3, [r7, #4] + 80035c0: e010 b.n 80035e4 } else { if (KernelState == osKernelReady) { - 8002a7e: 4b0b ldr r3, [pc, #44] ; (8002aac ) - 8002a80: 681b ldr r3, [r3, #0] - 8002a82: 2b01 cmp r3, #1 - 8002a84: d109 bne.n 8002a9a + 80035c2: 4b0b ldr r3, [pc, #44] ; (80035f0 ) + 80035c4: 681b ldr r3, [r3, #0] + 80035c6: 2b01 cmp r3, #1 + 80035c8: d109 bne.n 80035de /* Ensure SVC priority is at the reset value */ SVC_Setup(); - 8002a86: f7ff ffbf bl 8002a08 + 80035ca: f7ff ffbf bl 800354c /* Change state to enable IRQ masking check */ KernelState = osKernelRunning; - 8002a8a: 4b08 ldr r3, [pc, #32] ; (8002aac ) - 8002a8c: 2202 movs r2, #2 - 8002a8e: 601a str r2, [r3, #0] + 80035ce: 4b08 ldr r3, [pc, #32] ; (80035f0 ) + 80035d0: 2202 movs r2, #2 + 80035d2: 601a str r2, [r3, #0] /* Start the kernel scheduler */ vTaskStartScheduler(); - 8002a90: f001 f860 bl 8003b54 + 80035d4: f001 f87c bl 80046d0 stat = osOK; - 8002a94: 2300 movs r3, #0 - 8002a96: 607b str r3, [r7, #4] - 8002a98: e002 b.n 8002aa0 + 80035d8: 2300 movs r3, #0 + 80035da: 607b str r3, [r7, #4] + 80035dc: e002 b.n 80035e4 } else { stat = osError; - 8002a9a: f04f 33ff mov.w r3, #4294967295 - 8002a9e: 607b str r3, [r7, #4] + 80035de: f04f 33ff mov.w r3, #4294967295 + 80035e2: 607b str r3, [r7, #4] } } return (stat); - 8002aa0: 687b ldr r3, [r7, #4] + 80035e4: 687b ldr r3, [r7, #4] } - 8002aa2: 4618 mov r0, r3 - 8002aa4: 3708 adds r7, #8 - 8002aa6: 46bd mov sp, r7 - 8002aa8: bd80 pop {r7, pc} - 8002aaa: bf00 nop - 8002aac: 2000012c .word 0x2000012c + 80035e6: 4618 mov r0, r3 + 80035e8: 3708 adds r7, #8 + 80035ea: 46bd mov sp, r7 + 80035ec: bd80 pop {r7, pc} + 80035ee: bf00 nop + 80035f0: 2000017c .word 0x2000017c -08002ab0 : +080035f4 : return (configCPU_CLOCK_HZ); } /*---------------------------------------------------------------------------*/ osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) { - 8002ab0: b580 push {r7, lr} - 8002ab2: b08e sub sp, #56 ; 0x38 - 8002ab4: af04 add r7, sp, #16 - 8002ab6: 60f8 str r0, [r7, #12] - 8002ab8: 60b9 str r1, [r7, #8] - 8002aba: 607a str r2, [r7, #4] + 80035f4: b580 push {r7, lr} + 80035f6: b08e sub sp, #56 ; 0x38 + 80035f8: af04 add r7, sp, #16 + 80035fa: 60f8 str r0, [r7, #12] + 80035fc: 60b9 str r1, [r7, #8] + 80035fe: 607a str r2, [r7, #4] uint32_t stack; TaskHandle_t hTask; UBaseType_t prio; int32_t mem; hTask = NULL; - 8002abc: 2300 movs r3, #0 - 8002abe: 613b str r3, [r7, #16] + 8003600: 2300 movs r3, #0 + 8003602: 613b str r3, [r7, #16] __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - 8002ac0: f3ef 8305 mrs r3, IPSR - 8002ac4: 617b str r3, [r7, #20] + 8003604: f3ef 8305 mrs r3, IPSR + 8003608: 617b str r3, [r7, #20] return(result); - 8002ac6: 697b ldr r3, [r7, #20] + 800360a: 697b ldr r3, [r7, #20] if (!IS_IRQ() && (func != NULL)) { - 8002ac8: 2b00 cmp r3, #0 - 8002aca: d17e bne.n 8002bca - 8002acc: 68fb ldr r3, [r7, #12] - 8002ace: 2b00 cmp r3, #0 - 8002ad0: d07b beq.n 8002bca + 800360c: 2b00 cmp r3, #0 + 800360e: d17e bne.n 800370e + 8003610: 68fb ldr r3, [r7, #12] + 8003612: 2b00 cmp r3, #0 + 8003614: d07b beq.n 800370e stack = configMINIMAL_STACK_SIZE; - 8002ad2: 2380 movs r3, #128 ; 0x80 - 8002ad4: 623b str r3, [r7, #32] + 8003616: 2380 movs r3, #128 ; 0x80 + 8003618: 623b str r3, [r7, #32] prio = (UBaseType_t)osPriorityNormal; - 8002ad6: 2318 movs r3, #24 - 8002ad8: 61fb str r3, [r7, #28] + 800361a: 2318 movs r3, #24 + 800361c: 61fb str r3, [r7, #28] name = NULL; - 8002ada: 2300 movs r3, #0 - 8002adc: 627b str r3, [r7, #36] ; 0x24 + 800361e: 2300 movs r3, #0 + 8003620: 627b str r3, [r7, #36] ; 0x24 mem = -1; - 8002ade: f04f 33ff mov.w r3, #4294967295 - 8002ae2: 61bb str r3, [r7, #24] + 8003622: f04f 33ff mov.w r3, #4294967295 + 8003626: 61bb str r3, [r7, #24] if (attr != NULL) { - 8002ae4: 687b ldr r3, [r7, #4] - 8002ae6: 2b00 cmp r3, #0 - 8002ae8: d045 beq.n 8002b76 + 8003628: 687b ldr r3, [r7, #4] + 800362a: 2b00 cmp r3, #0 + 800362c: d045 beq.n 80036ba if (attr->name != NULL) { - 8002aea: 687b ldr r3, [r7, #4] - 8002aec: 681b ldr r3, [r3, #0] - 8002aee: 2b00 cmp r3, #0 - 8002af0: d002 beq.n 8002af8 + 800362e: 687b ldr r3, [r7, #4] + 8003630: 681b ldr r3, [r3, #0] + 8003632: 2b00 cmp r3, #0 + 8003634: d002 beq.n 800363c name = attr->name; - 8002af2: 687b ldr r3, [r7, #4] - 8002af4: 681b ldr r3, [r3, #0] - 8002af6: 627b str r3, [r7, #36] ; 0x24 + 8003636: 687b ldr r3, [r7, #4] + 8003638: 681b ldr r3, [r3, #0] + 800363a: 627b str r3, [r7, #36] ; 0x24 } if (attr->priority != osPriorityNone) { - 8002af8: 687b ldr r3, [r7, #4] - 8002afa: 699b ldr r3, [r3, #24] - 8002afc: 2b00 cmp r3, #0 - 8002afe: d002 beq.n 8002b06 + 800363c: 687b ldr r3, [r7, #4] + 800363e: 699b ldr r3, [r3, #24] + 8003640: 2b00 cmp r3, #0 + 8003642: d002 beq.n 800364a prio = (UBaseType_t)attr->priority; - 8002b00: 687b ldr r3, [r7, #4] - 8002b02: 699b ldr r3, [r3, #24] - 8002b04: 61fb str r3, [r7, #28] + 8003644: 687b ldr r3, [r7, #4] + 8003646: 699b ldr r3, [r3, #24] + 8003648: 61fb str r3, [r7, #28] } if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) { - 8002b06: 69fb ldr r3, [r7, #28] - 8002b08: 2b00 cmp r3, #0 - 8002b0a: d008 beq.n 8002b1e - 8002b0c: 69fb ldr r3, [r7, #28] - 8002b0e: 2b38 cmp r3, #56 ; 0x38 - 8002b10: d805 bhi.n 8002b1e - 8002b12: 687b ldr r3, [r7, #4] - 8002b14: 685b ldr r3, [r3, #4] - 8002b16: f003 0301 and.w r3, r3, #1 - 8002b1a: 2b00 cmp r3, #0 - 8002b1c: d001 beq.n 8002b22 + 800364a: 69fb ldr r3, [r7, #28] + 800364c: 2b00 cmp r3, #0 + 800364e: d008 beq.n 8003662 + 8003650: 69fb ldr r3, [r7, #28] + 8003652: 2b38 cmp r3, #56 ; 0x38 + 8003654: d805 bhi.n 8003662 + 8003656: 687b ldr r3, [r7, #4] + 8003658: 685b ldr r3, [r3, #4] + 800365a: f003 0301 and.w r3, r3, #1 + 800365e: 2b00 cmp r3, #0 + 8003660: d001 beq.n 8003666 return (NULL); - 8002b1e: 2300 movs r3, #0 - 8002b20: e054 b.n 8002bcc + 8003662: 2300 movs r3, #0 + 8003664: e054 b.n 8003710 } if (attr->stack_size > 0U) { - 8002b22: 687b ldr r3, [r7, #4] - 8002b24: 695b ldr r3, [r3, #20] - 8002b26: 2b00 cmp r3, #0 - 8002b28: d003 beq.n 8002b32 + 8003666: 687b ldr r3, [r7, #4] + 8003668: 695b ldr r3, [r3, #20] + 800366a: 2b00 cmp r3, #0 + 800366c: d003 beq.n 8003676 /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports. */ /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */ stack = attr->stack_size / sizeof(StackType_t); - 8002b2a: 687b ldr r3, [r7, #4] - 8002b2c: 695b ldr r3, [r3, #20] - 8002b2e: 089b lsrs r3, r3, #2 - 8002b30: 623b str r3, [r7, #32] + 800366e: 687b ldr r3, [r7, #4] + 8003670: 695b ldr r3, [r3, #20] + 8003672: 089b lsrs r3, r3, #2 + 8003674: 623b str r3, [r7, #32] } if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && - 8002b32: 687b ldr r3, [r7, #4] - 8002b34: 689b ldr r3, [r3, #8] - 8002b36: 2b00 cmp r3, #0 - 8002b38: d00e beq.n 8002b58 - 8002b3a: 687b ldr r3, [r7, #4] - 8002b3c: 68db ldr r3, [r3, #12] - 8002b3e: 2ba7 cmp r3, #167 ; 0xa7 - 8002b40: d90a bls.n 8002b58 + 8003676: 687b ldr r3, [r7, #4] + 8003678: 689b ldr r3, [r3, #8] + 800367a: 2b00 cmp r3, #0 + 800367c: d00e beq.n 800369c + 800367e: 687b ldr r3, [r7, #4] + 8003680: 68db ldr r3, [r3, #12] + 8003682: 2ba7 cmp r3, #167 ; 0xa7 + 8003684: d90a bls.n 800369c (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { - 8002b42: 687b ldr r3, [r7, #4] - 8002b44: 691b ldr r3, [r3, #16] + 8003686: 687b ldr r3, [r7, #4] + 8003688: 691b ldr r3, [r3, #16] if ((attr->cb_mem != NULL) && (attr->cb_size >= sizeof(StaticTask_t)) && - 8002b46: 2b00 cmp r3, #0 - 8002b48: d006 beq.n 8002b58 + 800368a: 2b00 cmp r3, #0 + 800368c: d006 beq.n 800369c (attr->stack_mem != NULL) && (attr->stack_size > 0U)) { - 8002b4a: 687b ldr r3, [r7, #4] - 8002b4c: 695b ldr r3, [r3, #20] - 8002b4e: 2b00 cmp r3, #0 - 8002b50: d002 beq.n 8002b58 + 800368e: 687b ldr r3, [r7, #4] + 8003690: 695b ldr r3, [r3, #20] + 8003692: 2b00 cmp r3, #0 + 8003694: d002 beq.n 800369c mem = 1; - 8002b52: 2301 movs r3, #1 - 8002b54: 61bb str r3, [r7, #24] - 8002b56: e010 b.n 8002b7a + 8003696: 2301 movs r3, #1 + 8003698: 61bb str r3, [r7, #24] + 800369a: e010 b.n 80036be } else { if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) { - 8002b58: 687b ldr r3, [r7, #4] - 8002b5a: 689b ldr r3, [r3, #8] - 8002b5c: 2b00 cmp r3, #0 - 8002b5e: d10c bne.n 8002b7a - 8002b60: 687b ldr r3, [r7, #4] - 8002b62: 68db ldr r3, [r3, #12] - 8002b64: 2b00 cmp r3, #0 - 8002b66: d108 bne.n 8002b7a - 8002b68: 687b ldr r3, [r7, #4] - 8002b6a: 691b ldr r3, [r3, #16] - 8002b6c: 2b00 cmp r3, #0 - 8002b6e: d104 bne.n 8002b7a + 800369c: 687b ldr r3, [r7, #4] + 800369e: 689b ldr r3, [r3, #8] + 80036a0: 2b00 cmp r3, #0 + 80036a2: d10c bne.n 80036be + 80036a4: 687b ldr r3, [r7, #4] + 80036a6: 68db ldr r3, [r3, #12] + 80036a8: 2b00 cmp r3, #0 + 80036aa: d108 bne.n 80036be + 80036ac: 687b ldr r3, [r7, #4] + 80036ae: 691b ldr r3, [r3, #16] + 80036b0: 2b00 cmp r3, #0 + 80036b2: d104 bne.n 80036be mem = 0; - 8002b70: 2300 movs r3, #0 - 8002b72: 61bb str r3, [r7, #24] - 8002b74: e001 b.n 8002b7a + 80036b4: 2300 movs r3, #0 + 80036b6: 61bb str r3, [r7, #24] + 80036b8: e001 b.n 80036be } } } else { mem = 0; - 8002b76: 2300 movs r3, #0 - 8002b78: 61bb str r3, [r7, #24] + 80036ba: 2300 movs r3, #0 + 80036bc: 61bb str r3, [r7, #24] } if (mem == 1) { - 8002b7a: 69bb ldr r3, [r7, #24] - 8002b7c: 2b01 cmp r3, #1 - 8002b7e: d110 bne.n 8002ba2 + 80036be: 69bb ldr r3, [r7, #24] + 80036c0: 2b01 cmp r3, #1 + 80036c2: d110 bne.n 80036e6 #if (configSUPPORT_STATIC_ALLOCATION == 1) hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, - 8002b80: 687b ldr r3, [r7, #4] - 8002b82: 691b ldr r3, [r3, #16] + 80036c4: 687b ldr r3, [r7, #4] + 80036c6: 691b ldr r3, [r3, #16] (StaticTask_t *)attr->cb_mem); - 8002b84: 687a ldr r2, [r7, #4] - 8002b86: 6892 ldr r2, [r2, #8] + 80036c8: 687a ldr r2, [r7, #4] + 80036ca: 6892 ldr r2, [r2, #8] hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t *)attr->stack_mem, - 8002b88: 9202 str r2, [sp, #8] - 8002b8a: 9301 str r3, [sp, #4] - 8002b8c: 69fb ldr r3, [r7, #28] - 8002b8e: 9300 str r3, [sp, #0] - 8002b90: 68bb ldr r3, [r7, #8] - 8002b92: 6a3a ldr r2, [r7, #32] - 8002b94: 6a79 ldr r1, [r7, #36] ; 0x24 - 8002b96: 68f8 ldr r0, [r7, #12] - 8002b98: f000 fdf0 bl 800377c - 8002b9c: 4603 mov r3, r0 - 8002b9e: 613b str r3, [r7, #16] - 8002ba0: e013 b.n 8002bca + 80036cc: 9202 str r2, [sp, #8] + 80036ce: 9301 str r3, [sp, #4] + 80036d0: 69fb ldr r3, [r7, #28] + 80036d2: 9300 str r3, [sp, #0] + 80036d4: 68bb ldr r3, [r7, #8] + 80036d6: 6a3a ldr r2, [r7, #32] + 80036d8: 6a79 ldr r1, [r7, #36] ; 0x24 + 80036da: 68f8 ldr r0, [r7, #12] + 80036dc: f000 fe0c bl 80042f8 + 80036e0: 4603 mov r3, r0 + 80036e2: 613b str r3, [r7, #16] + 80036e4: e013 b.n 800370e #endif } else { if (mem == 0) { - 8002ba2: 69bb ldr r3, [r7, #24] - 8002ba4: 2b00 cmp r3, #0 - 8002ba6: d110 bne.n 8002bca + 80036e6: 69bb ldr r3, [r7, #24] + 80036e8: 2b00 cmp r3, #0 + 80036ea: d110 bne.n 800370e #if (configSUPPORT_DYNAMIC_ALLOCATION == 1) if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) { - 8002ba8: 6a3b ldr r3, [r7, #32] - 8002baa: b29a uxth r2, r3 - 8002bac: f107 0310 add.w r3, r7, #16 - 8002bb0: 9301 str r3, [sp, #4] - 8002bb2: 69fb ldr r3, [r7, #28] - 8002bb4: 9300 str r3, [sp, #0] - 8002bb6: 68bb ldr r3, [r7, #8] - 8002bb8: 6a79 ldr r1, [r7, #36] ; 0x24 - 8002bba: 68f8 ldr r0, [r7, #12] - 8002bbc: f000 fe3b bl 8003836 - 8002bc0: 4603 mov r3, r0 - 8002bc2: 2b01 cmp r3, #1 - 8002bc4: d001 beq.n 8002bca + 80036ec: 6a3b ldr r3, [r7, #32] + 80036ee: b29a uxth r2, r3 + 80036f0: f107 0310 add.w r3, r7, #16 + 80036f4: 9301 str r3, [sp, #4] + 80036f6: 69fb ldr r3, [r7, #28] + 80036f8: 9300 str r3, [sp, #0] + 80036fa: 68bb ldr r3, [r7, #8] + 80036fc: 6a79 ldr r1, [r7, #36] ; 0x24 + 80036fe: 68f8 ldr r0, [r7, #12] + 8003700: f000 fe57 bl 80043b2 + 8003704: 4603 mov r3, r0 + 8003706: 2b01 cmp r3, #1 + 8003708: d001 beq.n 800370e hTask = NULL; - 8002bc6: 2300 movs r3, #0 - 8002bc8: 613b str r3, [r7, #16] + 800370a: 2300 movs r3, #0 + 800370c: 613b str r3, [r7, #16] #endif } } } return ((osThreadId_t)hTask); - 8002bca: 693b ldr r3, [r7, #16] + 800370e: 693b ldr r3, [r7, #16] } - 8002bcc: 4618 mov r0, r3 - 8002bce: 3728 adds r7, #40 ; 0x28 - 8002bd0: 46bd mov sp, r7 - 8002bd2: bd80 pop {r7, pc} + 8003710: 4618 mov r0, r3 + 8003712: 3728 adds r7, #40 ; 0x28 + 8003714: 46bd mov sp, r7 + 8003716: bd80 pop {r7, pc} -08002bd4 : +08003718 : + /* Return flags before clearing */ + return (rflags); +} +#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */ + +osStatus_t osDelay (uint32_t ticks) { + 8003718: b580 push {r7, lr} + 800371a: b084 sub sp, #16 + 800371c: af00 add r7, sp, #0 + 800371e: 6078 str r0, [r7, #4] + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + 8003720: f3ef 8305 mrs r3, IPSR + 8003724: 60bb str r3, [r7, #8] + return(result); + 8003726: 68bb ldr r3, [r7, #8] + osStatus_t stat; + + if (IS_IRQ()) { + 8003728: 2b00 cmp r3, #0 + 800372a: d003 beq.n 8003734 + stat = osErrorISR; + 800372c: f06f 0305 mvn.w r3, #5 + 8003730: 60fb str r3, [r7, #12] + 8003732: e007 b.n 8003744 + } + else { + stat = osOK; + 8003734: 2300 movs r3, #0 + 8003736: 60fb str r3, [r7, #12] + + if (ticks != 0U) { + 8003738: 687b ldr r3, [r7, #4] + 800373a: 2b00 cmp r3, #0 + 800373c: d002 beq.n 8003744 + vTaskDelay(ticks); + 800373e: 6878 ldr r0, [r7, #4] + 8003740: f000 ff92 bl 8004668 + } + } + + return (stat); + 8003744: 68fb ldr r3, [r7, #12] +} + 8003746: 4618 mov r0, r3 + 8003748: 3710 adds r7, #16 + 800374a: 46bd mov sp, r7 + 800374c: bd80 pop {r7, pc} + ... + +08003750 : /* vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) { - 8002bd4: b480 push {r7} - 8002bd6: b085 sub sp, #20 - 8002bd8: af00 add r7, sp, #0 - 8002bda: 60f8 str r0, [r7, #12] - 8002bdc: 60b9 str r1, [r7, #8] - 8002bde: 607a str r2, [r7, #4] + 8003750: b480 push {r7} + 8003752: b085 sub sp, #20 + 8003754: af00 add r7, sp, #0 + 8003756: 60f8 str r0, [r7, #12] + 8003758: 60b9 str r1, [r7, #8] + 800375a: 607a str r2, [r7, #4] /* Idle task control block and stack */ static StaticTask_t Idle_TCB; static StackType_t Idle_Stack[configMINIMAL_STACK_SIZE]; *ppxIdleTaskTCBBuffer = &Idle_TCB; - 8002be0: 68fb ldr r3, [r7, #12] - 8002be2: 4a07 ldr r2, [pc, #28] ; (8002c00 ) - 8002be4: 601a str r2, [r3, #0] + 800375c: 68fb ldr r3, [r7, #12] + 800375e: 4a07 ldr r2, [pc, #28] ; (800377c ) + 8003760: 601a str r2, [r3, #0] *ppxIdleTaskStackBuffer = &Idle_Stack[0]; - 8002be6: 68bb ldr r3, [r7, #8] - 8002be8: 4a06 ldr r2, [pc, #24] ; (8002c04 ) - 8002bea: 601a str r2, [r3, #0] + 8003762: 68bb ldr r3, [r7, #8] + 8003764: 4a06 ldr r2, [pc, #24] ; (8003780 ) + 8003766: 601a str r2, [r3, #0] *pulIdleTaskStackSize = (uint32_t)configMINIMAL_STACK_SIZE; - 8002bec: 687b ldr r3, [r7, #4] - 8002bee: 2280 movs r2, #128 ; 0x80 - 8002bf0: 601a str r2, [r3, #0] + 8003768: 687b ldr r3, [r7, #4] + 800376a: 2280 movs r2, #128 ; 0x80 + 800376c: 601a str r2, [r3, #0] } - 8002bf2: bf00 nop - 8002bf4: 3714 adds r7, #20 - 8002bf6: 46bd mov sp, r7 - 8002bf8: f85d 7b04 ldr.w r7, [sp], #4 - 8002bfc: 4770 bx lr - 8002bfe: bf00 nop - 8002c00: 20000130 .word 0x20000130 - 8002c04: 200001d8 .word 0x200001d8 + 800376e: bf00 nop + 8003770: 3714 adds r7, #20 + 8003772: 46bd mov sp, r7 + 8003774: f85d 7b04 ldr.w r7, [sp], #4 + 8003778: 4770 bx lr + 800377a: bf00 nop + 800377c: 20000180 .word 0x20000180 + 8003780: 20000228 .word 0x20000228 -08002c08 : +08003784 : /* vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION equals to 1 and is required for static memory allocation support. */ __WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) { - 8002c08: b480 push {r7} - 8002c0a: b085 sub sp, #20 - 8002c0c: af00 add r7, sp, #0 - 8002c0e: 60f8 str r0, [r7, #12] - 8002c10: 60b9 str r1, [r7, #8] - 8002c12: 607a str r2, [r7, #4] + 8003784: b480 push {r7} + 8003786: b085 sub sp, #20 + 8003788: af00 add r7, sp, #0 + 800378a: 60f8 str r0, [r7, #12] + 800378c: 60b9 str r1, [r7, #8] + 800378e: 607a str r2, [r7, #4] /* Timer task control block and stack */ static StaticTask_t Timer_TCB; static StackType_t Timer_Stack[configTIMER_TASK_STACK_DEPTH]; *ppxTimerTaskTCBBuffer = &Timer_TCB; - 8002c14: 68fb ldr r3, [r7, #12] - 8002c16: 4a07 ldr r2, [pc, #28] ; (8002c34 ) - 8002c18: 601a str r2, [r3, #0] + 8003790: 68fb ldr r3, [r7, #12] + 8003792: 4a07 ldr r2, [pc, #28] ; (80037b0 ) + 8003794: 601a str r2, [r3, #0] *ppxTimerTaskStackBuffer = &Timer_Stack[0]; - 8002c1a: 68bb ldr r3, [r7, #8] - 8002c1c: 4a06 ldr r2, [pc, #24] ; (8002c38 ) - 8002c1e: 601a str r2, [r3, #0] + 8003796: 68bb ldr r3, [r7, #8] + 8003798: 4a06 ldr r2, [pc, #24] ; (80037b4 ) + 800379a: 601a str r2, [r3, #0] *pulTimerTaskStackSize = (uint32_t)configTIMER_TASK_STACK_DEPTH; - 8002c20: 687b ldr r3, [r7, #4] - 8002c22: f44f 7280 mov.w r2, #256 ; 0x100 - 8002c26: 601a str r2, [r3, #0] + 800379c: 687b ldr r3, [r7, #4] + 800379e: f44f 7280 mov.w r2, #256 ; 0x100 + 80037a2: 601a str r2, [r3, #0] } - 8002c28: bf00 nop - 8002c2a: 3714 adds r7, #20 - 8002c2c: 46bd mov sp, r7 - 8002c2e: f85d 7b04 ldr.w r7, [sp], #4 - 8002c32: 4770 bx lr - 8002c34: 200003d8 .word 0x200003d8 - 8002c38: 20000480 .word 0x20000480 + 80037a4: bf00 nop + 80037a6: 3714 adds r7, #20 + 80037a8: 46bd mov sp, r7 + 80037aa: f85d 7b04 ldr.w r7, [sp], #4 + 80037ae: 4770 bx lr + 80037b0: 20000428 .word 0x20000428 + 80037b4: 200004d0 .word 0x200004d0 -08002c3c : +080037b8 : /*----------------------------------------------------------- * PUBLIC LIST API documented in list.h *----------------------------------------------------------*/ void vListInitialise( List_t * const pxList ) { - 8002c3c: b480 push {r7} - 8002c3e: b083 sub sp, #12 - 8002c40: af00 add r7, sp, #0 - 8002c42: 6078 str r0, [r7, #4] + 80037b8: b480 push {r7} + 80037ba: b083 sub sp, #12 + 80037bc: af00 add r7, sp, #0 + 80037be: 6078 str r0, [r7, #4] /* The list structure contains a list item which is used to mark the end of the list. To initialise the list the list end is inserted as the only list entry. */ pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - 8002c44: 687b ldr r3, [r7, #4] - 8002c46: f103 0208 add.w r2, r3, #8 - 8002c4a: 687b ldr r3, [r7, #4] - 8002c4c: 605a str r2, [r3, #4] + 80037c0: 687b ldr r3, [r7, #4] + 80037c2: f103 0208 add.w r2, r3, #8 + 80037c6: 687b ldr r3, [r7, #4] + 80037c8: 605a str r2, [r3, #4] /* The list end value is the highest possible value in the list to ensure it remains at the end of the list. */ pxList->xListEnd.xItemValue = portMAX_DELAY; - 8002c4e: 687b ldr r3, [r7, #4] - 8002c50: f04f 32ff mov.w r2, #4294967295 - 8002c54: 609a str r2, [r3, #8] + 80037ca: 687b ldr r3, [r7, #4] + 80037cc: f04f 32ff mov.w r2, #4294967295 + 80037d0: 609a str r2, [r3, #8] /* The list end next and previous pointers point to itself so we know when the list is empty. */ pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - 8002c56: 687b ldr r3, [r7, #4] - 8002c58: f103 0208 add.w r2, r3, #8 - 8002c5c: 687b ldr r3, [r7, #4] - 8002c5e: 60da str r2, [r3, #12] + 80037d2: 687b ldr r3, [r7, #4] + 80037d4: f103 0208 add.w r2, r3, #8 + 80037d8: 687b ldr r3, [r7, #4] + 80037da: 60da str r2, [r3, #12] pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - 8002c60: 687b ldr r3, [r7, #4] - 8002c62: f103 0208 add.w r2, r3, #8 - 8002c66: 687b ldr r3, [r7, #4] - 8002c68: 611a str r2, [r3, #16] + 80037dc: 687b ldr r3, [r7, #4] + 80037de: f103 0208 add.w r2, r3, #8 + 80037e2: 687b ldr r3, [r7, #4] + 80037e4: 611a str r2, [r3, #16] pxList->uxNumberOfItems = ( UBaseType_t ) 0U; - 8002c6a: 687b ldr r3, [r7, #4] - 8002c6c: 2200 movs r2, #0 - 8002c6e: 601a str r2, [r3, #0] + 80037e6: 687b ldr r3, [r7, #4] + 80037e8: 2200 movs r2, #0 + 80037ea: 601a str r2, [r3, #0] /* Write known values into the list if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ); listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ); } - 8002c70: bf00 nop - 8002c72: 370c adds r7, #12 - 8002c74: 46bd mov sp, r7 - 8002c76: f85d 7b04 ldr.w r7, [sp], #4 - 8002c7a: 4770 bx lr + 80037ec: bf00 nop + 80037ee: 370c adds r7, #12 + 80037f0: 46bd mov sp, r7 + 80037f2: f85d 7b04 ldr.w r7, [sp], #4 + 80037f6: 4770 bx lr -08002c7c : +080037f8 : /*-----------------------------------------------------------*/ void vListInitialiseItem( ListItem_t * const pxItem ) { - 8002c7c: b480 push {r7} - 8002c7e: b083 sub sp, #12 - 8002c80: af00 add r7, sp, #0 - 8002c82: 6078 str r0, [r7, #4] + 80037f8: b480 push {r7} + 80037fa: b083 sub sp, #12 + 80037fc: af00 add r7, sp, #0 + 80037fe: 6078 str r0, [r7, #4] /* Make sure the list item is not recorded as being on a list. */ pxItem->pxContainer = NULL; - 8002c84: 687b ldr r3, [r7, #4] - 8002c86: 2200 movs r2, #0 - 8002c88: 611a str r2, [r3, #16] + 8003800: 687b ldr r3, [r7, #4] + 8003802: 2200 movs r2, #0 + 8003804: 611a str r2, [r3, #16] /* Write known values into the list item if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ); } - 8002c8a: bf00 nop - 8002c8c: 370c adds r7, #12 - 8002c8e: 46bd mov sp, r7 - 8002c90: f85d 7b04 ldr.w r7, [sp], #4 - 8002c94: 4770 bx lr + 8003806: bf00 nop + 8003808: 370c adds r7, #12 + 800380a: 46bd mov sp, r7 + 800380c: f85d 7b04 ldr.w r7, [sp], #4 + 8003810: 4770 bx lr -08002c96 : +08003812 : /*-----------------------------------------------------------*/ void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) { - 8002c96: b480 push {r7} - 8002c98: b085 sub sp, #20 - 8002c9a: af00 add r7, sp, #0 - 8002c9c: 6078 str r0, [r7, #4] - 8002c9e: 6039 str r1, [r7, #0] + 8003812: b480 push {r7} + 8003814: b085 sub sp, #20 + 8003816: af00 add r7, sp, #0 + 8003818: 6078 str r0, [r7, #4] + 800381a: 6039 str r1, [r7, #0] ListItem_t * const pxIndex = pxList->pxIndex; - 8002ca0: 687b ldr r3, [r7, #4] - 8002ca2: 685b ldr r3, [r3, #4] - 8002ca4: 60fb str r3, [r7, #12] + 800381c: 687b ldr r3, [r7, #4] + 800381e: 685b ldr r3, [r3, #4] + 8003820: 60fb str r3, [r7, #12] listTEST_LIST_ITEM_INTEGRITY( pxNewListItem ); /* Insert a new list item into pxList, but rather than sort the list, makes the new list item the last item to be removed by a call to listGET_OWNER_OF_NEXT_ENTRY(). */ pxNewListItem->pxNext = pxIndex; - 8002ca6: 683b ldr r3, [r7, #0] - 8002ca8: 68fa ldr r2, [r7, #12] - 8002caa: 605a str r2, [r3, #4] + 8003822: 683b ldr r3, [r7, #0] + 8003824: 68fa ldr r2, [r7, #12] + 8003826: 605a str r2, [r3, #4] pxNewListItem->pxPrevious = pxIndex->pxPrevious; - 8002cac: 68fb ldr r3, [r7, #12] - 8002cae: 689a ldr r2, [r3, #8] - 8002cb0: 683b ldr r3, [r7, #0] - 8002cb2: 609a str r2, [r3, #8] + 8003828: 68fb ldr r3, [r7, #12] + 800382a: 689a ldr r2, [r3, #8] + 800382c: 683b ldr r3, [r7, #0] + 800382e: 609a str r2, [r3, #8] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); pxIndex->pxPrevious->pxNext = pxNewListItem; - 8002cb4: 68fb ldr r3, [r7, #12] - 8002cb6: 689b ldr r3, [r3, #8] - 8002cb8: 683a ldr r2, [r7, #0] - 8002cba: 605a str r2, [r3, #4] + 8003830: 68fb ldr r3, [r7, #12] + 8003832: 689b ldr r3, [r3, #8] + 8003834: 683a ldr r2, [r7, #0] + 8003836: 605a str r2, [r3, #4] pxIndex->pxPrevious = pxNewListItem; - 8002cbc: 68fb ldr r3, [r7, #12] - 8002cbe: 683a ldr r2, [r7, #0] - 8002cc0: 609a str r2, [r3, #8] + 8003838: 68fb ldr r3, [r7, #12] + 800383a: 683a ldr r2, [r7, #0] + 800383c: 609a str r2, [r3, #8] /* Remember which list the item is in. */ pxNewListItem->pxContainer = pxList; - 8002cc2: 683b ldr r3, [r7, #0] - 8002cc4: 687a ldr r2, [r7, #4] - 8002cc6: 611a str r2, [r3, #16] + 800383e: 683b ldr r3, [r7, #0] + 8003840: 687a ldr r2, [r7, #4] + 8003842: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; - 8002cc8: 687b ldr r3, [r7, #4] - 8002cca: 681b ldr r3, [r3, #0] - 8002ccc: 1c5a adds r2, r3, #1 - 8002cce: 687b ldr r3, [r7, #4] - 8002cd0: 601a str r2, [r3, #0] + 8003844: 687b ldr r3, [r7, #4] + 8003846: 681b ldr r3, [r3, #0] + 8003848: 1c5a adds r2, r3, #1 + 800384a: 687b ldr r3, [r7, #4] + 800384c: 601a str r2, [r3, #0] } - 8002cd2: bf00 nop - 8002cd4: 3714 adds r7, #20 - 8002cd6: 46bd mov sp, r7 - 8002cd8: f85d 7b04 ldr.w r7, [sp], #4 - 8002cdc: 4770 bx lr + 800384e: bf00 nop + 8003850: 3714 adds r7, #20 + 8003852: 46bd mov sp, r7 + 8003854: f85d 7b04 ldr.w r7, [sp], #4 + 8003858: 4770 bx lr -08002cde : +0800385a : /*-----------------------------------------------------------*/ void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) { - 8002cde: b480 push {r7} - 8002ce0: b085 sub sp, #20 - 8002ce2: af00 add r7, sp, #0 - 8002ce4: 6078 str r0, [r7, #4] - 8002ce6: 6039 str r1, [r7, #0] + 800385a: b480 push {r7} + 800385c: b085 sub sp, #20 + 800385e: af00 add r7, sp, #0 + 8003860: 6078 str r0, [r7, #4] + 8003862: 6039 str r1, [r7, #0] ListItem_t *pxIterator; const TickType_t xValueOfInsertion = pxNewListItem->xItemValue; - 8002ce8: 683b ldr r3, [r7, #0] - 8002cea: 681b ldr r3, [r3, #0] - 8002cec: 60bb str r3, [r7, #8] + 8003864: 683b ldr r3, [r7, #0] + 8003866: 681b ldr r3, [r3, #0] + 8003868: 60bb str r3, [r7, #8] new list item should be placed after it. This ensures that TCBs which are stored in ready lists (all of which have the same xItemValue value) get a share of the CPU. However, if the xItemValue is the same as the back marker the iteration loop below will not end. Therefore the value is checked first, and the algorithm slightly modified if necessary. */ if( xValueOfInsertion == portMAX_DELAY ) - 8002cee: 68bb ldr r3, [r7, #8] - 8002cf0: f1b3 3fff cmp.w r3, #4294967295 - 8002cf4: d103 bne.n 8002cfe + 800386a: 68bb ldr r3, [r7, #8] + 800386c: f1b3 3fff cmp.w r3, #4294967295 + 8003870: d103 bne.n 800387a { pxIterator = pxList->xListEnd.pxPrevious; - 8002cf6: 687b ldr r3, [r7, #4] - 8002cf8: 691b ldr r3, [r3, #16] - 8002cfa: 60fb str r3, [r7, #12] - 8002cfc: e00c b.n 8002d18 + 8003872: 687b ldr r3, [r7, #4] + 8003874: 691b ldr r3, [r3, #16] + 8003876: 60fb str r3, [r7, #12] + 8003878: e00c b.n 8003894 4) Using a queue or semaphore before it has been initialised or before the scheduler has been started (are interrupts firing before vTaskStartScheduler() has been called?). **********************************************************************/ for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */ - 8002cfe: 687b ldr r3, [r7, #4] - 8002d00: 3308 adds r3, #8 - 8002d02: 60fb str r3, [r7, #12] - 8002d04: e002 b.n 8002d0c - 8002d06: 68fb ldr r3, [r7, #12] - 8002d08: 685b ldr r3, [r3, #4] - 8002d0a: 60fb str r3, [r7, #12] - 8002d0c: 68fb ldr r3, [r7, #12] - 8002d0e: 685b ldr r3, [r3, #4] - 8002d10: 681b ldr r3, [r3, #0] - 8002d12: 68ba ldr r2, [r7, #8] - 8002d14: 429a cmp r2, r3 - 8002d16: d2f6 bcs.n 8002d06 + 800387a: 687b ldr r3, [r7, #4] + 800387c: 3308 adds r3, #8 + 800387e: 60fb str r3, [r7, #12] + 8003880: e002 b.n 8003888 + 8003882: 68fb ldr r3, [r7, #12] + 8003884: 685b ldr r3, [r3, #4] + 8003886: 60fb str r3, [r7, #12] + 8003888: 68fb ldr r3, [r7, #12] + 800388a: 685b ldr r3, [r3, #4] + 800388c: 681b ldr r3, [r3, #0] + 800388e: 68ba ldr r2, [r7, #8] + 8003890: 429a cmp r2, r3 + 8003892: d2f6 bcs.n 8003882 /* There is nothing to do here, just iterating to the wanted insertion position. */ } } pxNewListItem->pxNext = pxIterator->pxNext; - 8002d18: 68fb ldr r3, [r7, #12] - 8002d1a: 685a ldr r2, [r3, #4] - 8002d1c: 683b ldr r3, [r7, #0] - 8002d1e: 605a str r2, [r3, #4] + 8003894: 68fb ldr r3, [r7, #12] + 8003896: 685a ldr r2, [r3, #4] + 8003898: 683b ldr r3, [r7, #0] + 800389a: 605a str r2, [r3, #4] pxNewListItem->pxNext->pxPrevious = pxNewListItem; - 8002d20: 683b ldr r3, [r7, #0] - 8002d22: 685b ldr r3, [r3, #4] - 8002d24: 683a ldr r2, [r7, #0] - 8002d26: 609a str r2, [r3, #8] + 800389c: 683b ldr r3, [r7, #0] + 800389e: 685b ldr r3, [r3, #4] + 80038a0: 683a ldr r2, [r7, #0] + 80038a2: 609a str r2, [r3, #8] pxNewListItem->pxPrevious = pxIterator; - 8002d28: 683b ldr r3, [r7, #0] - 8002d2a: 68fa ldr r2, [r7, #12] - 8002d2c: 609a str r2, [r3, #8] + 80038a4: 683b ldr r3, [r7, #0] + 80038a6: 68fa ldr r2, [r7, #12] + 80038a8: 609a str r2, [r3, #8] pxIterator->pxNext = pxNewListItem; - 8002d2e: 68fb ldr r3, [r7, #12] - 8002d30: 683a ldr r2, [r7, #0] - 8002d32: 605a str r2, [r3, #4] + 80038aa: 68fb ldr r3, [r7, #12] + 80038ac: 683a ldr r2, [r7, #0] + 80038ae: 605a str r2, [r3, #4] /* Remember which list the item is in. This allows fast removal of the item later. */ pxNewListItem->pxContainer = pxList; - 8002d34: 683b ldr r3, [r7, #0] - 8002d36: 687a ldr r2, [r7, #4] - 8002d38: 611a str r2, [r3, #16] + 80038b0: 683b ldr r3, [r7, #0] + 80038b2: 687a ldr r2, [r7, #4] + 80038b4: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )++; - 8002d3a: 687b ldr r3, [r7, #4] - 8002d3c: 681b ldr r3, [r3, #0] - 8002d3e: 1c5a adds r2, r3, #1 - 8002d40: 687b ldr r3, [r7, #4] - 8002d42: 601a str r2, [r3, #0] + 80038b6: 687b ldr r3, [r7, #4] + 80038b8: 681b ldr r3, [r3, #0] + 80038ba: 1c5a adds r2, r3, #1 + 80038bc: 687b ldr r3, [r7, #4] + 80038be: 601a str r2, [r3, #0] } - 8002d44: bf00 nop - 8002d46: 3714 adds r7, #20 - 8002d48: 46bd mov sp, r7 - 8002d4a: f85d 7b04 ldr.w r7, [sp], #4 - 8002d4e: 4770 bx lr + 80038c0: bf00 nop + 80038c2: 3714 adds r7, #20 + 80038c4: 46bd mov sp, r7 + 80038c6: f85d 7b04 ldr.w r7, [sp], #4 + 80038ca: 4770 bx lr -08002d50 : +080038cc : /*-----------------------------------------------------------*/ UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) { - 8002d50: b480 push {r7} - 8002d52: b085 sub sp, #20 - 8002d54: af00 add r7, sp, #0 - 8002d56: 6078 str r0, [r7, #4] + 80038cc: b480 push {r7} + 80038ce: b085 sub sp, #20 + 80038d0: af00 add r7, sp, #0 + 80038d2: 6078 str r0, [r7, #4] /* The list item knows which list it is in. Obtain the list from the list item. */ List_t * const pxList = pxItemToRemove->pxContainer; - 8002d58: 687b ldr r3, [r7, #4] - 8002d5a: 691b ldr r3, [r3, #16] - 8002d5c: 60fb str r3, [r7, #12] + 80038d4: 687b ldr r3, [r7, #4] + 80038d6: 691b ldr r3, [r3, #16] + 80038d8: 60fb str r3, [r7, #12] pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious; - 8002d5e: 687b ldr r3, [r7, #4] - 8002d60: 685b ldr r3, [r3, #4] - 8002d62: 687a ldr r2, [r7, #4] - 8002d64: 6892 ldr r2, [r2, #8] - 8002d66: 609a str r2, [r3, #8] + 80038da: 687b ldr r3, [r7, #4] + 80038dc: 685b ldr r3, [r3, #4] + 80038de: 687a ldr r2, [r7, #4] + 80038e0: 6892 ldr r2, [r2, #8] + 80038e2: 609a str r2, [r3, #8] pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext; - 8002d68: 687b ldr r3, [r7, #4] - 8002d6a: 689b ldr r3, [r3, #8] - 8002d6c: 687a ldr r2, [r7, #4] - 8002d6e: 6852 ldr r2, [r2, #4] - 8002d70: 605a str r2, [r3, #4] + 80038e4: 687b ldr r3, [r7, #4] + 80038e6: 689b ldr r3, [r3, #8] + 80038e8: 687a ldr r2, [r7, #4] + 80038ea: 6852 ldr r2, [r2, #4] + 80038ec: 605a str r2, [r3, #4] /* Only used during decision coverage testing. */ mtCOVERAGE_TEST_DELAY(); /* Make sure the index is left pointing to a valid item. */ if( pxList->pxIndex == pxItemToRemove ) - 8002d72: 68fb ldr r3, [r7, #12] - 8002d74: 685b ldr r3, [r3, #4] - 8002d76: 687a ldr r2, [r7, #4] - 8002d78: 429a cmp r2, r3 - 8002d7a: d103 bne.n 8002d84 + 80038ee: 68fb ldr r3, [r7, #12] + 80038f0: 685b ldr r3, [r3, #4] + 80038f2: 687a ldr r2, [r7, #4] + 80038f4: 429a cmp r2, r3 + 80038f6: d103 bne.n 8003900 { pxList->pxIndex = pxItemToRemove->pxPrevious; - 8002d7c: 687b ldr r3, [r7, #4] - 8002d7e: 689a ldr r2, [r3, #8] - 8002d80: 68fb ldr r3, [r7, #12] - 8002d82: 605a str r2, [r3, #4] + 80038f8: 687b ldr r3, [r7, #4] + 80038fa: 689a ldr r2, [r3, #8] + 80038fc: 68fb ldr r3, [r7, #12] + 80038fe: 605a str r2, [r3, #4] else { mtCOVERAGE_TEST_MARKER(); } pxItemToRemove->pxContainer = NULL; - 8002d84: 687b ldr r3, [r7, #4] - 8002d86: 2200 movs r2, #0 - 8002d88: 611a str r2, [r3, #16] + 8003900: 687b ldr r3, [r7, #4] + 8003902: 2200 movs r2, #0 + 8003904: 611a str r2, [r3, #16] ( pxList->uxNumberOfItems )--; - 8002d8a: 68fb ldr r3, [r7, #12] - 8002d8c: 681b ldr r3, [r3, #0] - 8002d8e: 1e5a subs r2, r3, #1 - 8002d90: 68fb ldr r3, [r7, #12] - 8002d92: 601a str r2, [r3, #0] + 8003906: 68fb ldr r3, [r7, #12] + 8003908: 681b ldr r3, [r3, #0] + 800390a: 1e5a subs r2, r3, #1 + 800390c: 68fb ldr r3, [r7, #12] + 800390e: 601a str r2, [r3, #0] return pxList->uxNumberOfItems; - 8002d94: 68fb ldr r3, [r7, #12] - 8002d96: 681b ldr r3, [r3, #0] + 8003910: 68fb ldr r3, [r7, #12] + 8003912: 681b ldr r3, [r3, #0] } - 8002d98: 4618 mov r0, r3 - 8002d9a: 3714 adds r7, #20 - 8002d9c: 46bd mov sp, r7 - 8002d9e: f85d 7b04 ldr.w r7, [sp], #4 - 8002da2: 4770 bx lr + 8003914: 4618 mov r0, r3 + 8003916: 3714 adds r7, #20 + 8003918: 46bd mov sp, r7 + 800391a: f85d 7b04 ldr.w r7, [sp], #4 + 800391e: 4770 bx lr -08002da4 : +08003920 : } \ taskEXIT_CRITICAL() /*-----------------------------------------------------------*/ BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) { - 8002da4: b580 push {r7, lr} - 8002da6: b084 sub sp, #16 - 8002da8: af00 add r7, sp, #0 - 8002daa: 6078 str r0, [r7, #4] - 8002dac: 6039 str r1, [r7, #0] + 8003920: b580 push {r7, lr} + 8003922: b084 sub sp, #16 + 8003924: af00 add r7, sp, #0 + 8003926: 6078 str r0, [r7, #4] + 8003928: 6039 str r1, [r7, #0] Queue_t * const pxQueue = xQueue; - 8002dae: 687b ldr r3, [r7, #4] - 8002db0: 60fb str r3, [r7, #12] + 800392a: 687b ldr r3, [r7, #4] + 800392c: 60fb str r3, [r7, #12] configASSERT( pxQueue ); - 8002db2: 68fb ldr r3, [r7, #12] - 8002db4: 2b00 cmp r3, #0 - 8002db6: d10a bne.n 8002dce + 800392e: 68fb ldr r3, [r7, #12] + 8003930: 2b00 cmp r3, #0 + 8003932: d10a bne.n 800394a portFORCE_INLINE static void vPortRaiseBASEPRI( void ) { uint32_t ulNewBASEPRI; __asm volatile - 8002db8: f04f 0350 mov.w r3, #80 ; 0x50 - 8002dbc: f383 8811 msr BASEPRI, r3 - 8002dc0: f3bf 8f6f isb sy - 8002dc4: f3bf 8f4f dsb sy - 8002dc8: 60bb str r3, [r7, #8] + 8003934: f04f 0350 mov.w r3, #80 ; 0x50 + 8003938: f383 8811 msr BASEPRI, r3 + 800393c: f3bf 8f6f isb sy + 8003940: f3bf 8f4f dsb sy + 8003944: 60bb str r3, [r7, #8] " msr basepri, %0 \n" \ " isb \n" \ " dsb \n" \ :"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); } - 8002dca: bf00 nop - 8002dcc: e7fe b.n 8002dcc + 8003946: bf00 nop + 8003948: e7fe b.n 8003948 taskENTER_CRITICAL(); - 8002dce: f002 f879 bl 8004ec4 + 800394a: f002 f87b bl 8005a44 { pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ - 8002dd2: 68fb ldr r3, [r7, #12] - 8002dd4: 681a ldr r2, [r3, #0] - 8002dd6: 68fb ldr r3, [r7, #12] - 8002dd8: 6bdb ldr r3, [r3, #60] ; 0x3c - 8002dda: 68f9 ldr r1, [r7, #12] - 8002ddc: 6c09 ldr r1, [r1, #64] ; 0x40 - 8002dde: fb01 f303 mul.w r3, r1, r3 - 8002de2: 441a add r2, r3 - 8002de4: 68fb ldr r3, [r7, #12] - 8002de6: 609a str r2, [r3, #8] + 800394e: 68fb ldr r3, [r7, #12] + 8003950: 681a ldr r2, [r3, #0] + 8003952: 68fb ldr r3, [r7, #12] + 8003954: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003956: 68f9 ldr r1, [r7, #12] + 8003958: 6c09 ldr r1, [r1, #64] ; 0x40 + 800395a: fb01 f303 mul.w r3, r1, r3 + 800395e: 441a add r2, r3 + 8003960: 68fb ldr r3, [r7, #12] + 8003962: 609a str r2, [r3, #8] pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U; - 8002de8: 68fb ldr r3, [r7, #12] - 8002dea: 2200 movs r2, #0 - 8002dec: 639a str r2, [r3, #56] ; 0x38 + 8003964: 68fb ldr r3, [r7, #12] + 8003966: 2200 movs r2, #0 + 8003968: 639a str r2, [r3, #56] ; 0x38 pxQueue->pcWriteTo = pxQueue->pcHead; - 8002dee: 68fb ldr r3, [r7, #12] - 8002df0: 681a ldr r2, [r3, #0] - 8002df2: 68fb ldr r3, [r7, #12] - 8002df4: 605a str r2, [r3, #4] + 800396a: 68fb ldr r3, [r7, #12] + 800396c: 681a ldr r2, [r3, #0] + 800396e: 68fb ldr r3, [r7, #12] + 8003970: 605a str r2, [r3, #4] pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */ - 8002df6: 68fb ldr r3, [r7, #12] - 8002df8: 681a ldr r2, [r3, #0] - 8002dfa: 68fb ldr r3, [r7, #12] - 8002dfc: 6bdb ldr r3, [r3, #60] ; 0x3c - 8002dfe: 3b01 subs r3, #1 - 8002e00: 68f9 ldr r1, [r7, #12] - 8002e02: 6c09 ldr r1, [r1, #64] ; 0x40 - 8002e04: fb01 f303 mul.w r3, r1, r3 - 8002e08: 441a add r2, r3 - 8002e0a: 68fb ldr r3, [r7, #12] - 8002e0c: 60da str r2, [r3, #12] + 8003972: 68fb ldr r3, [r7, #12] + 8003974: 681a ldr r2, [r3, #0] + 8003976: 68fb ldr r3, [r7, #12] + 8003978: 6bdb ldr r3, [r3, #60] ; 0x3c + 800397a: 3b01 subs r3, #1 + 800397c: 68f9 ldr r1, [r7, #12] + 800397e: 6c09 ldr r1, [r1, #64] ; 0x40 + 8003980: fb01 f303 mul.w r3, r1, r3 + 8003984: 441a add r2, r3 + 8003986: 68fb ldr r3, [r7, #12] + 8003988: 60da str r2, [r3, #12] pxQueue->cRxLock = queueUNLOCKED; - 8002e0e: 68fb ldr r3, [r7, #12] - 8002e10: 22ff movs r2, #255 ; 0xff - 8002e12: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 800398a: 68fb ldr r3, [r7, #12] + 800398c: 22ff movs r2, #255 ; 0xff + 800398e: f883 2044 strb.w r2, [r3, #68] ; 0x44 pxQueue->cTxLock = queueUNLOCKED; - 8002e16: 68fb ldr r3, [r7, #12] - 8002e18: 22ff movs r2, #255 ; 0xff - 8002e1a: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 8003992: 68fb ldr r3, [r7, #12] + 8003994: 22ff movs r2, #255 ; 0xff + 8003996: f883 2045 strb.w r2, [r3, #69] ; 0x45 if( xNewQueue == pdFALSE ) - 8002e1e: 683b ldr r3, [r7, #0] - 8002e20: 2b00 cmp r3, #0 - 8002e22: d114 bne.n 8002e4e + 800399a: 683b ldr r3, [r7, #0] + 800399c: 2b00 cmp r3, #0 + 800399e: d114 bne.n 80039ca /* If there are tasks blocked waiting to read from the queue, then the tasks will remain blocked as after this function exits the queue will still be empty. If there are tasks blocked waiting to write to the queue, then one should be unblocked as after this function exits it will be possible to write to it. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) - 8002e24: 68fb ldr r3, [r7, #12] - 8002e26: 691b ldr r3, [r3, #16] - 8002e28: 2b00 cmp r3, #0 - 8002e2a: d01a beq.n 8002e62 + 80039a0: 68fb ldr r3, [r7, #12] + 80039a2: 691b ldr r3, [r3, #16] + 80039a4: 2b00 cmp r3, #0 + 80039a6: d01a beq.n 80039de { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - 8002e2c: 68fb ldr r3, [r7, #12] - 8002e2e: 3310 adds r3, #16 - 8002e30: 4618 mov r0, r3 - 8002e32: f001 f929 bl 8004088 - 8002e36: 4603 mov r3, r0 - 8002e38: 2b00 cmp r3, #0 - 8002e3a: d012 beq.n 8002e62 + 80039a8: 68fb ldr r3, [r7, #12] + 80039aa: 3310 adds r3, #16 + 80039ac: 4618 mov r0, r3 + 80039ae: f001 f929 bl 8004c04 + 80039b2: 4603 mov r3, r0 + 80039b4: 2b00 cmp r3, #0 + 80039b6: d012 beq.n 80039de { queueYIELD_IF_USING_PREEMPTION(); - 8002e3c: 4b0c ldr r3, [pc, #48] ; (8002e70 ) - 8002e3e: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 8002e42: 601a str r2, [r3, #0] - 8002e44: f3bf 8f4f dsb sy - 8002e48: f3bf 8f6f isb sy - 8002e4c: e009 b.n 8002e62 + 80039b8: 4b0c ldr r3, [pc, #48] ; (80039ec ) + 80039ba: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80039be: 601a str r2, [r3, #0] + 80039c0: f3bf 8f4f dsb sy + 80039c4: f3bf 8f6f isb sy + 80039c8: e009 b.n 80039de } } else { /* Ensure the event queues start in the correct state. */ vListInitialise( &( pxQueue->xTasksWaitingToSend ) ); - 8002e4e: 68fb ldr r3, [r7, #12] - 8002e50: 3310 adds r3, #16 - 8002e52: 4618 mov r0, r3 - 8002e54: f7ff fef2 bl 8002c3c + 80039ca: 68fb ldr r3, [r7, #12] + 80039cc: 3310 adds r3, #16 + 80039ce: 4618 mov r0, r3 + 80039d0: f7ff fef2 bl 80037b8 vListInitialise( &( pxQueue->xTasksWaitingToReceive ) ); - 8002e58: 68fb ldr r3, [r7, #12] - 8002e5a: 3324 adds r3, #36 ; 0x24 - 8002e5c: 4618 mov r0, r3 - 8002e5e: f7ff feed bl 8002c3c + 80039d4: 68fb ldr r3, [r7, #12] + 80039d6: 3324 adds r3, #36 ; 0x24 + 80039d8: 4618 mov r0, r3 + 80039da: f7ff feed bl 80037b8 } } taskEXIT_CRITICAL(); - 8002e62: f002 f85f bl 8004f24 + 80039de: f002 f861 bl 8005aa4 /* A value is returned for calling semantic consistency with previous versions. */ return pdPASS; - 8002e66: 2301 movs r3, #1 + 80039e2: 2301 movs r3, #1 } - 8002e68: 4618 mov r0, r3 - 8002e6a: 3710 adds r7, #16 - 8002e6c: 46bd mov sp, r7 - 8002e6e: bd80 pop {r7, pc} - 8002e70: e000ed04 .word 0xe000ed04 + 80039e4: 4618 mov r0, r3 + 80039e6: 3710 adds r7, #16 + 80039e8: 46bd mov sp, r7 + 80039ea: bd80 pop {r7, pc} + 80039ec: e000ed04 .word 0xe000ed04 -08002e74 : +080039f0 : /*-----------------------------------------------------------*/ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) { - 8002e74: b580 push {r7, lr} - 8002e76: b08e sub sp, #56 ; 0x38 - 8002e78: af02 add r7, sp, #8 - 8002e7a: 60f8 str r0, [r7, #12] - 8002e7c: 60b9 str r1, [r7, #8] - 8002e7e: 607a str r2, [r7, #4] - 8002e80: 603b str r3, [r7, #0] + 80039f0: b580 push {r7, lr} + 80039f2: b08e sub sp, #56 ; 0x38 + 80039f4: af02 add r7, sp, #8 + 80039f6: 60f8 str r0, [r7, #12] + 80039f8: 60b9 str r1, [r7, #8] + 80039fa: 607a str r2, [r7, #4] + 80039fc: 603b str r3, [r7, #0] Queue_t *pxNewQueue; configASSERT( uxQueueLength > ( UBaseType_t ) 0 ); - 8002e82: 68fb ldr r3, [r7, #12] - 8002e84: 2b00 cmp r3, #0 - 8002e86: d10a bne.n 8002e9e + 80039fe: 68fb ldr r3, [r7, #12] + 8003a00: 2b00 cmp r3, #0 + 8003a02: d10a bne.n 8003a1a __asm volatile - 8002e88: f04f 0350 mov.w r3, #80 ; 0x50 - 8002e8c: f383 8811 msr BASEPRI, r3 - 8002e90: f3bf 8f6f isb sy - 8002e94: f3bf 8f4f dsb sy - 8002e98: 62bb str r3, [r7, #40] ; 0x28 + 8003a04: f04f 0350 mov.w r3, #80 ; 0x50 + 8003a08: f383 8811 msr BASEPRI, r3 + 8003a0c: f3bf 8f6f isb sy + 8003a10: f3bf 8f4f dsb sy + 8003a14: 62bb str r3, [r7, #40] ; 0x28 } - 8002e9a: bf00 nop - 8002e9c: e7fe b.n 8002e9c + 8003a16: bf00 nop + 8003a18: e7fe b.n 8003a18 /* The StaticQueue_t structure and the queue storage area must be supplied. */ configASSERT( pxStaticQueue != NULL ); - 8002e9e: 683b ldr r3, [r7, #0] - 8002ea0: 2b00 cmp r3, #0 - 8002ea2: d10a bne.n 8002eba + 8003a1a: 683b ldr r3, [r7, #0] + 8003a1c: 2b00 cmp r3, #0 + 8003a1e: d10a bne.n 8003a36 __asm volatile - 8002ea4: f04f 0350 mov.w r3, #80 ; 0x50 - 8002ea8: f383 8811 msr BASEPRI, r3 - 8002eac: f3bf 8f6f isb sy - 8002eb0: f3bf 8f4f dsb sy - 8002eb4: 627b str r3, [r7, #36] ; 0x24 + 8003a20: f04f 0350 mov.w r3, #80 ; 0x50 + 8003a24: f383 8811 msr BASEPRI, r3 + 8003a28: f3bf 8f6f isb sy + 8003a2c: f3bf 8f4f dsb sy + 8003a30: 627b str r3, [r7, #36] ; 0x24 } - 8002eb6: bf00 nop - 8002eb8: e7fe b.n 8002eb8 + 8003a32: bf00 nop + 8003a34: e7fe b.n 8003a34 /* A queue storage area should be provided if the item size is not 0, and should not be provided if the item size is 0. */ configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) ); - 8002eba: 687b ldr r3, [r7, #4] - 8002ebc: 2b00 cmp r3, #0 - 8002ebe: d002 beq.n 8002ec6 - 8002ec0: 68bb ldr r3, [r7, #8] - 8002ec2: 2b00 cmp r3, #0 - 8002ec4: d001 beq.n 8002eca - 8002ec6: 2301 movs r3, #1 - 8002ec8: e000 b.n 8002ecc - 8002eca: 2300 movs r3, #0 - 8002ecc: 2b00 cmp r3, #0 - 8002ece: d10a bne.n 8002ee6 + 8003a36: 687b ldr r3, [r7, #4] + 8003a38: 2b00 cmp r3, #0 + 8003a3a: d002 beq.n 8003a42 + 8003a3c: 68bb ldr r3, [r7, #8] + 8003a3e: 2b00 cmp r3, #0 + 8003a40: d001 beq.n 8003a46 + 8003a42: 2301 movs r3, #1 + 8003a44: e000 b.n 8003a48 + 8003a46: 2300 movs r3, #0 + 8003a48: 2b00 cmp r3, #0 + 8003a4a: d10a bne.n 8003a62 __asm volatile - 8002ed0: f04f 0350 mov.w r3, #80 ; 0x50 - 8002ed4: f383 8811 msr BASEPRI, r3 - 8002ed8: f3bf 8f6f isb sy - 8002edc: f3bf 8f4f dsb sy - 8002ee0: 623b str r3, [r7, #32] + 8003a4c: f04f 0350 mov.w r3, #80 ; 0x50 + 8003a50: f383 8811 msr BASEPRI, r3 + 8003a54: f3bf 8f6f isb sy + 8003a58: f3bf 8f4f dsb sy + 8003a5c: 623b str r3, [r7, #32] } - 8002ee2: bf00 nop - 8002ee4: e7fe b.n 8002ee4 + 8003a5e: bf00 nop + 8003a60: e7fe b.n 8003a60 configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) ); - 8002ee6: 687b ldr r3, [r7, #4] - 8002ee8: 2b00 cmp r3, #0 - 8002eea: d102 bne.n 8002ef2 - 8002eec: 68bb ldr r3, [r7, #8] - 8002eee: 2b00 cmp r3, #0 - 8002ef0: d101 bne.n 8002ef6 - 8002ef2: 2301 movs r3, #1 - 8002ef4: e000 b.n 8002ef8 - 8002ef6: 2300 movs r3, #0 - 8002ef8: 2b00 cmp r3, #0 - 8002efa: d10a bne.n 8002f12 + 8003a62: 687b ldr r3, [r7, #4] + 8003a64: 2b00 cmp r3, #0 + 8003a66: d102 bne.n 8003a6e + 8003a68: 68bb ldr r3, [r7, #8] + 8003a6a: 2b00 cmp r3, #0 + 8003a6c: d101 bne.n 8003a72 + 8003a6e: 2301 movs r3, #1 + 8003a70: e000 b.n 8003a74 + 8003a72: 2300 movs r3, #0 + 8003a74: 2b00 cmp r3, #0 + 8003a76: d10a bne.n 8003a8e __asm volatile - 8002efc: f04f 0350 mov.w r3, #80 ; 0x50 - 8002f00: f383 8811 msr BASEPRI, r3 - 8002f04: f3bf 8f6f isb sy - 8002f08: f3bf 8f4f dsb sy - 8002f0c: 61fb str r3, [r7, #28] + 8003a78: f04f 0350 mov.w r3, #80 ; 0x50 + 8003a7c: f383 8811 msr BASEPRI, r3 + 8003a80: f3bf 8f6f isb sy + 8003a84: f3bf 8f4f dsb sy + 8003a88: 61fb str r3, [r7, #28] } - 8002f0e: bf00 nop - 8002f10: e7fe b.n 8002f10 + 8003a8a: bf00 nop + 8003a8c: e7fe b.n 8003a8c #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticQueue_t or StaticSemaphore_t equals the size of the real queue and semaphore structures. */ volatile size_t xSize = sizeof( StaticQueue_t ); - 8002f12: 2350 movs r3, #80 ; 0x50 - 8002f14: 617b str r3, [r7, #20] + 8003a8e: 2350 movs r3, #80 ; 0x50 + 8003a90: 617b str r3, [r7, #20] configASSERT( xSize == sizeof( Queue_t ) ); - 8002f16: 697b ldr r3, [r7, #20] - 8002f18: 2b50 cmp r3, #80 ; 0x50 - 8002f1a: d00a beq.n 8002f32 + 8003a92: 697b ldr r3, [r7, #20] + 8003a94: 2b50 cmp r3, #80 ; 0x50 + 8003a96: d00a beq.n 8003aae __asm volatile - 8002f1c: f04f 0350 mov.w r3, #80 ; 0x50 - 8002f20: f383 8811 msr BASEPRI, r3 - 8002f24: f3bf 8f6f isb sy - 8002f28: f3bf 8f4f dsb sy - 8002f2c: 61bb str r3, [r7, #24] + 8003a98: f04f 0350 mov.w r3, #80 ; 0x50 + 8003a9c: f383 8811 msr BASEPRI, r3 + 8003aa0: f3bf 8f6f isb sy + 8003aa4: f3bf 8f4f dsb sy + 8003aa8: 61bb str r3, [r7, #24] } - 8002f2e: bf00 nop - 8002f30: e7fe b.n 8002f30 + 8003aaa: bf00 nop + 8003aac: e7fe b.n 8003aac ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */ - 8002f32: 697b ldr r3, [r7, #20] + 8003aae: 697b ldr r3, [r7, #20] #endif /* configASSERT_DEFINED */ /* The address of a statically allocated queue was passed in, use it. The address of a statically allocated storage area was also passed in but is already set. */ pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ - 8002f34: 683b ldr r3, [r7, #0] - 8002f36: 62fb str r3, [r7, #44] ; 0x2c + 8003ab0: 683b ldr r3, [r7, #0] + 8003ab2: 62fb str r3, [r7, #44] ; 0x2c if( pxNewQueue != NULL ) - 8002f38: 6afb ldr r3, [r7, #44] ; 0x2c - 8002f3a: 2b00 cmp r3, #0 - 8002f3c: d00d beq.n 8002f5a + 8003ab4: 6afb ldr r3, [r7, #44] ; 0x2c + 8003ab6: 2b00 cmp r3, #0 + 8003ab8: d00d beq.n 8003ad6 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* Queues can be allocated wither statically or dynamically, so note this queue was allocated statically in case the queue is later deleted. */ pxNewQueue->ucStaticallyAllocated = pdTRUE; - 8002f3e: 6afb ldr r3, [r7, #44] ; 0x2c - 8002f40: 2201 movs r2, #1 - 8002f42: f883 2046 strb.w r2, [r3, #70] ; 0x46 + 8003aba: 6afb ldr r3, [r7, #44] ; 0x2c + 8003abc: 2201 movs r2, #1 + 8003abe: f883 2046 strb.w r2, [r3, #70] ; 0x46 } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue ); - 8002f46: f897 2038 ldrb.w r2, [r7, #56] ; 0x38 - 8002f4a: 6afb ldr r3, [r7, #44] ; 0x2c - 8002f4c: 9300 str r3, [sp, #0] - 8002f4e: 4613 mov r3, r2 - 8002f50: 687a ldr r2, [r7, #4] - 8002f52: 68b9 ldr r1, [r7, #8] - 8002f54: 68f8 ldr r0, [r7, #12] - 8002f56: f000 f805 bl 8002f64 + 8003ac2: f897 2038 ldrb.w r2, [r7, #56] ; 0x38 + 8003ac6: 6afb ldr r3, [r7, #44] ; 0x2c + 8003ac8: 9300 str r3, [sp, #0] + 8003aca: 4613 mov r3, r2 + 8003acc: 687a ldr r2, [r7, #4] + 8003ace: 68b9 ldr r1, [r7, #8] + 8003ad0: 68f8 ldr r0, [r7, #12] + 8003ad2: f000 f805 bl 8003ae0 { traceQUEUE_CREATE_FAILED( ucQueueType ); mtCOVERAGE_TEST_MARKER(); } return pxNewQueue; - 8002f5a: 6afb ldr r3, [r7, #44] ; 0x2c + 8003ad6: 6afb ldr r3, [r7, #44] ; 0x2c } - 8002f5c: 4618 mov r0, r3 - 8002f5e: 3730 adds r7, #48 ; 0x30 - 8002f60: 46bd mov sp, r7 - 8002f62: bd80 pop {r7, pc} + 8003ad8: 4618 mov r0, r3 + 8003ada: 3730 adds r7, #48 ; 0x30 + 8003adc: 46bd mov sp, r7 + 8003ade: bd80 pop {r7, pc} -08002f64 : +08003ae0 : #endif /* configSUPPORT_STATIC_ALLOCATION */ /*-----------------------------------------------------------*/ static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) { - 8002f64: b580 push {r7, lr} - 8002f66: b084 sub sp, #16 - 8002f68: af00 add r7, sp, #0 - 8002f6a: 60f8 str r0, [r7, #12] - 8002f6c: 60b9 str r1, [r7, #8] - 8002f6e: 607a str r2, [r7, #4] - 8002f70: 70fb strb r3, [r7, #3] + 8003ae0: b580 push {r7, lr} + 8003ae2: b084 sub sp, #16 + 8003ae4: af00 add r7, sp, #0 + 8003ae6: 60f8 str r0, [r7, #12] + 8003ae8: 60b9 str r1, [r7, #8] + 8003aea: 607a str r2, [r7, #4] + 8003aec: 70fb strb r3, [r7, #3] /* Remove compiler warnings about unused parameters should configUSE_TRACE_FACILITY not be set to 1. */ ( void ) ucQueueType; if( uxItemSize == ( UBaseType_t ) 0 ) - 8002f72: 68bb ldr r3, [r7, #8] - 8002f74: 2b00 cmp r3, #0 - 8002f76: d103 bne.n 8002f80 + 8003aee: 68bb ldr r3, [r7, #8] + 8003af0: 2b00 cmp r3, #0 + 8003af2: d103 bne.n 8003afc { /* No RAM was allocated for the queue storage area, but PC head cannot be set to NULL because NULL is used as a key to say the queue is used as a mutex. Therefore just set pcHead to point to the queue as a benign value that is known to be within the memory map. */ pxNewQueue->pcHead = ( int8_t * ) pxNewQueue; - 8002f78: 69bb ldr r3, [r7, #24] - 8002f7a: 69ba ldr r2, [r7, #24] - 8002f7c: 601a str r2, [r3, #0] - 8002f7e: e002 b.n 8002f86 + 8003af4: 69bb ldr r3, [r7, #24] + 8003af6: 69ba ldr r2, [r7, #24] + 8003af8: 601a str r2, [r3, #0] + 8003afa: e002 b.n 8003b02 } else { /* Set the head to the start of the queue storage area. */ pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage; - 8002f80: 69bb ldr r3, [r7, #24] - 8002f82: 687a ldr r2, [r7, #4] - 8002f84: 601a str r2, [r3, #0] + 8003afc: 69bb ldr r3, [r7, #24] + 8003afe: 687a ldr r2, [r7, #4] + 8003b00: 601a str r2, [r3, #0] } /* Initialise the queue members as described where the queue type is defined. */ pxNewQueue->uxLength = uxQueueLength; - 8002f86: 69bb ldr r3, [r7, #24] - 8002f88: 68fa ldr r2, [r7, #12] - 8002f8a: 63da str r2, [r3, #60] ; 0x3c + 8003b02: 69bb ldr r3, [r7, #24] + 8003b04: 68fa ldr r2, [r7, #12] + 8003b06: 63da str r2, [r3, #60] ; 0x3c pxNewQueue->uxItemSize = uxItemSize; - 8002f8c: 69bb ldr r3, [r7, #24] - 8002f8e: 68ba ldr r2, [r7, #8] - 8002f90: 641a str r2, [r3, #64] ; 0x40 + 8003b08: 69bb ldr r3, [r7, #24] + 8003b0a: 68ba ldr r2, [r7, #8] + 8003b0c: 641a str r2, [r3, #64] ; 0x40 ( void ) xQueueGenericReset( pxNewQueue, pdTRUE ); - 8002f92: 2101 movs r1, #1 - 8002f94: 69b8 ldr r0, [r7, #24] - 8002f96: f7ff ff05 bl 8002da4 + 8003b0e: 2101 movs r1, #1 + 8003b10: 69b8 ldr r0, [r7, #24] + 8003b12: f7ff ff05 bl 8003920 #if ( configUSE_TRACE_FACILITY == 1 ) { pxNewQueue->ucQueueType = ucQueueType; - 8002f9a: 69bb ldr r3, [r7, #24] - 8002f9c: 78fa ldrb r2, [r7, #3] - 8002f9e: f883 204c strb.w r2, [r3, #76] ; 0x4c + 8003b16: 69bb ldr r3, [r7, #24] + 8003b18: 78fa ldrb r2, [r7, #3] + 8003b1a: f883 204c strb.w r2, [r3, #76] ; 0x4c pxNewQueue->pxQueueSetContainer = NULL; } #endif /* configUSE_QUEUE_SETS */ traceQUEUE_CREATE( pxNewQueue ); } - 8002fa2: bf00 nop - 8002fa4: 3710 adds r7, #16 - 8002fa6: 46bd mov sp, r7 - 8002fa8: bd80 pop {r7, pc} + 8003b1e: bf00 nop + 8003b20: 3710 adds r7, #16 + 8003b22: 46bd mov sp, r7 + 8003b24: bd80 pop {r7, pc} ... -08002fac : +08003b28 : #endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */ /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) { - 8002fac: b580 push {r7, lr} - 8002fae: b08e sub sp, #56 ; 0x38 - 8002fb0: af00 add r7, sp, #0 - 8002fb2: 60f8 str r0, [r7, #12] - 8002fb4: 60b9 str r1, [r7, #8] - 8002fb6: 607a str r2, [r7, #4] - 8002fb8: 603b str r3, [r7, #0] + 8003b28: b580 push {r7, lr} + 8003b2a: b08e sub sp, #56 ; 0x38 + 8003b2c: af00 add r7, sp, #0 + 8003b2e: 60f8 str r0, [r7, #12] + 8003b30: 60b9 str r1, [r7, #8] + 8003b32: 607a str r2, [r7, #4] + 8003b34: 603b str r3, [r7, #0] BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired; - 8002fba: 2300 movs r3, #0 - 8002fbc: 637b str r3, [r7, #52] ; 0x34 + 8003b36: 2300 movs r3, #0 + 8003b38: 637b str r3, [r7, #52] ; 0x34 TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; - 8002fbe: 68fb ldr r3, [r7, #12] - 8002fc0: 633b str r3, [r7, #48] ; 0x30 + 8003b3a: 68fb ldr r3, [r7, #12] + 8003b3c: 633b str r3, [r7, #48] ; 0x30 configASSERT( pxQueue ); - 8002fc2: 6b3b ldr r3, [r7, #48] ; 0x30 - 8002fc4: 2b00 cmp r3, #0 - 8002fc6: d10a bne.n 8002fde + 8003b3e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003b40: 2b00 cmp r3, #0 + 8003b42: d10a bne.n 8003b5a __asm volatile - 8002fc8: f04f 0350 mov.w r3, #80 ; 0x50 - 8002fcc: f383 8811 msr BASEPRI, r3 - 8002fd0: f3bf 8f6f isb sy - 8002fd4: f3bf 8f4f dsb sy - 8002fd8: 62bb str r3, [r7, #40] ; 0x28 + 8003b44: f04f 0350 mov.w r3, #80 ; 0x50 + 8003b48: f383 8811 msr BASEPRI, r3 + 8003b4c: f3bf 8f6f isb sy + 8003b50: f3bf 8f4f dsb sy + 8003b54: 62bb str r3, [r7, #40] ; 0x28 } - 8002fda: bf00 nop - 8002fdc: e7fe b.n 8002fdc + 8003b56: bf00 nop + 8003b58: e7fe b.n 8003b58 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); - 8002fde: 68bb ldr r3, [r7, #8] - 8002fe0: 2b00 cmp r3, #0 - 8002fe2: d103 bne.n 8002fec - 8002fe4: 6b3b ldr r3, [r7, #48] ; 0x30 - 8002fe6: 6c1b ldr r3, [r3, #64] ; 0x40 - 8002fe8: 2b00 cmp r3, #0 - 8002fea: d101 bne.n 8002ff0 - 8002fec: 2301 movs r3, #1 - 8002fee: e000 b.n 8002ff2 - 8002ff0: 2300 movs r3, #0 - 8002ff2: 2b00 cmp r3, #0 - 8002ff4: d10a bne.n 800300c + 8003b5a: 68bb ldr r3, [r7, #8] + 8003b5c: 2b00 cmp r3, #0 + 8003b5e: d103 bne.n 8003b68 + 8003b60: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003b62: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003b64: 2b00 cmp r3, #0 + 8003b66: d101 bne.n 8003b6c + 8003b68: 2301 movs r3, #1 + 8003b6a: e000 b.n 8003b6e + 8003b6c: 2300 movs r3, #0 + 8003b6e: 2b00 cmp r3, #0 + 8003b70: d10a bne.n 8003b88 __asm volatile - 8002ff6: f04f 0350 mov.w r3, #80 ; 0x50 - 8002ffa: f383 8811 msr BASEPRI, r3 - 8002ffe: f3bf 8f6f isb sy - 8003002: f3bf 8f4f dsb sy - 8003006: 627b str r3, [r7, #36] ; 0x24 + 8003b72: f04f 0350 mov.w r3, #80 ; 0x50 + 8003b76: f383 8811 msr BASEPRI, r3 + 8003b7a: f3bf 8f6f isb sy + 8003b7e: f3bf 8f4f dsb sy + 8003b82: 627b str r3, [r7, #36] ; 0x24 } - 8003008: bf00 nop - 800300a: e7fe b.n 800300a + 8003b84: bf00 nop + 8003b86: e7fe b.n 8003b86 configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); - 800300c: 683b ldr r3, [r7, #0] - 800300e: 2b02 cmp r3, #2 - 8003010: d103 bne.n 800301a - 8003012: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003014: 6bdb ldr r3, [r3, #60] ; 0x3c - 8003016: 2b01 cmp r3, #1 - 8003018: d101 bne.n 800301e - 800301a: 2301 movs r3, #1 - 800301c: e000 b.n 8003020 - 800301e: 2300 movs r3, #0 - 8003020: 2b00 cmp r3, #0 - 8003022: d10a bne.n 800303a + 8003b88: 683b ldr r3, [r7, #0] + 8003b8a: 2b02 cmp r3, #2 + 8003b8c: d103 bne.n 8003b96 + 8003b8e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003b90: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003b92: 2b01 cmp r3, #1 + 8003b94: d101 bne.n 8003b9a + 8003b96: 2301 movs r3, #1 + 8003b98: e000 b.n 8003b9c + 8003b9a: 2300 movs r3, #0 + 8003b9c: 2b00 cmp r3, #0 + 8003b9e: d10a bne.n 8003bb6 __asm volatile - 8003024: f04f 0350 mov.w r3, #80 ; 0x50 - 8003028: f383 8811 msr BASEPRI, r3 - 800302c: f3bf 8f6f isb sy - 8003030: f3bf 8f4f dsb sy - 8003034: 623b str r3, [r7, #32] + 8003ba0: f04f 0350 mov.w r3, #80 ; 0x50 + 8003ba4: f383 8811 msr BASEPRI, r3 + 8003ba8: f3bf 8f6f isb sy + 8003bac: f3bf 8f4f dsb sy + 8003bb0: 623b str r3, [r7, #32] } - 8003036: bf00 nop - 8003038: e7fe b.n 8003038 + 8003bb2: bf00 nop + 8003bb4: e7fe b.n 8003bb4 #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); - 800303a: f001 f9e7 bl 800440c - 800303e: 4603 mov r3, r0 - 8003040: 2b00 cmp r3, #0 - 8003042: d102 bne.n 800304a - 8003044: 687b ldr r3, [r7, #4] - 8003046: 2b00 cmp r3, #0 - 8003048: d101 bne.n 800304e - 800304a: 2301 movs r3, #1 - 800304c: e000 b.n 8003050 - 800304e: 2300 movs r3, #0 - 8003050: 2b00 cmp r3, #0 - 8003052: d10a bne.n 800306a + 8003bb6: f001 f9e7 bl 8004f88 + 8003bba: 4603 mov r3, r0 + 8003bbc: 2b00 cmp r3, #0 + 8003bbe: d102 bne.n 8003bc6 + 8003bc0: 687b ldr r3, [r7, #4] + 8003bc2: 2b00 cmp r3, #0 + 8003bc4: d101 bne.n 8003bca + 8003bc6: 2301 movs r3, #1 + 8003bc8: e000 b.n 8003bcc + 8003bca: 2300 movs r3, #0 + 8003bcc: 2b00 cmp r3, #0 + 8003bce: d10a bne.n 8003be6 __asm volatile - 8003054: f04f 0350 mov.w r3, #80 ; 0x50 - 8003058: f383 8811 msr BASEPRI, r3 - 800305c: f3bf 8f6f isb sy - 8003060: f3bf 8f4f dsb sy - 8003064: 61fb str r3, [r7, #28] + 8003bd0: f04f 0350 mov.w r3, #80 ; 0x50 + 8003bd4: f383 8811 msr BASEPRI, r3 + 8003bd8: f3bf 8f6f isb sy + 8003bdc: f3bf 8f4f dsb sy + 8003be0: 61fb str r3, [r7, #28] } - 8003066: bf00 nop - 8003068: e7fe b.n 8003068 + 8003be2: bf00 nop + 8003be4: e7fe b.n 8003be4 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); - 800306a: f001 ff2b bl 8004ec4 + 8003be6: f001 ff2d bl 8005a44 { /* Is there room on the queue now? The running task must be the highest priority task wanting to access the queue. If the head item in the queue is to be overwritten then it does not matter if the queue is full. */ if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) - 800306e: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003070: 6b9a ldr r2, [r3, #56] ; 0x38 - 8003072: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003074: 6bdb ldr r3, [r3, #60] ; 0x3c - 8003076: 429a cmp r2, r3 - 8003078: d302 bcc.n 8003080 - 800307a: 683b ldr r3, [r7, #0] - 800307c: 2b02 cmp r3, #2 - 800307e: d129 bne.n 80030d4 + 8003bea: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003bec: 6b9a ldr r2, [r3, #56] ; 0x38 + 8003bee: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003bf0: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003bf2: 429a cmp r2, r3 + 8003bf4: d302 bcc.n 8003bfc + 8003bf6: 683b ldr r3, [r7, #0] + 8003bf8: 2b02 cmp r3, #2 + 8003bfa: d129 bne.n 8003c50 } } } #else /* configUSE_QUEUE_SETS */ { xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); - 8003080: 683a ldr r2, [r7, #0] - 8003082: 68b9 ldr r1, [r7, #8] - 8003084: 6b38 ldr r0, [r7, #48] ; 0x30 - 8003086: f000 fa0b bl 80034a0 - 800308a: 62f8 str r0, [r7, #44] ; 0x2c + 8003bfc: 683a ldr r2, [r7, #0] + 8003bfe: 68b9 ldr r1, [r7, #8] + 8003c00: 6b38 ldr r0, [r7, #48] ; 0x30 + 8003c02: f000 fa0b bl 800401c + 8003c06: 62f8 str r0, [r7, #44] ; 0x2c /* If there was a task waiting for data to arrive on the queue then unblock it now. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) - 800308c: 6b3b ldr r3, [r7, #48] ; 0x30 - 800308e: 6a5b ldr r3, [r3, #36] ; 0x24 - 8003090: 2b00 cmp r3, #0 - 8003092: d010 beq.n 80030b6 + 8003c08: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003c0a: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003c0c: 2b00 cmp r3, #0 + 8003c0e: d010 beq.n 8003c32 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - 8003094: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003096: 3324 adds r3, #36 ; 0x24 - 8003098: 4618 mov r0, r3 - 800309a: f000 fff5 bl 8004088 - 800309e: 4603 mov r3, r0 - 80030a0: 2b00 cmp r3, #0 - 80030a2: d013 beq.n 80030cc + 8003c10: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003c12: 3324 adds r3, #36 ; 0x24 + 8003c14: 4618 mov r0, r3 + 8003c16: f000 fff5 bl 8004c04 + 8003c1a: 4603 mov r3, r0 + 8003c1c: 2b00 cmp r3, #0 + 8003c1e: d013 beq.n 8003c48 { /* The unblocked task has a priority higher than our own so yield immediately. Yes it is ok to do this from within the critical section - the kernel takes care of that. */ queueYIELD_IF_USING_PREEMPTION(); - 80030a4: 4b3f ldr r3, [pc, #252] ; (80031a4 ) - 80030a6: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 80030aa: 601a str r2, [r3, #0] - 80030ac: f3bf 8f4f dsb sy - 80030b0: f3bf 8f6f isb sy - 80030b4: e00a b.n 80030cc + 8003c20: 4b3f ldr r3, [pc, #252] ; (8003d20 ) + 8003c22: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8003c26: 601a str r2, [r3, #0] + 8003c28: f3bf 8f4f dsb sy + 8003c2c: f3bf 8f6f isb sy + 8003c30: e00a b.n 8003c48 else { mtCOVERAGE_TEST_MARKER(); } } else if( xYieldRequired != pdFALSE ) - 80030b6: 6afb ldr r3, [r7, #44] ; 0x2c - 80030b8: 2b00 cmp r3, #0 - 80030ba: d007 beq.n 80030cc + 8003c32: 6afb ldr r3, [r7, #44] ; 0x2c + 8003c34: 2b00 cmp r3, #0 + 8003c36: d007 beq.n 8003c48 { /* This path is a special case that will only get executed if the task was holding multiple mutexes and the mutexes were given back in an order that is different to that in which they were taken. */ queueYIELD_IF_USING_PREEMPTION(); - 80030bc: 4b39 ldr r3, [pc, #228] ; (80031a4 ) - 80030be: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 80030c2: 601a str r2, [r3, #0] - 80030c4: f3bf 8f4f dsb sy - 80030c8: f3bf 8f6f isb sy + 8003c38: 4b39 ldr r3, [pc, #228] ; (8003d20 ) + 8003c3a: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8003c3e: 601a str r2, [r3, #0] + 8003c40: f3bf 8f4f dsb sy + 8003c44: f3bf 8f6f isb sy mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_QUEUE_SETS */ taskEXIT_CRITICAL(); - 80030cc: f001 ff2a bl 8004f24 + 8003c48: f001 ff2c bl 8005aa4 return pdPASS; - 80030d0: 2301 movs r3, #1 - 80030d2: e063 b.n 800319c + 8003c4c: 2301 movs r3, #1 + 8003c4e: e063 b.n 8003d18 } else { if( xTicksToWait == ( TickType_t ) 0 ) - 80030d4: 687b ldr r3, [r7, #4] - 80030d6: 2b00 cmp r3, #0 - 80030d8: d103 bne.n 80030e2 + 8003c50: 687b ldr r3, [r7, #4] + 8003c52: 2b00 cmp r3, #0 + 8003c54: d103 bne.n 8003c5e { /* The queue was full and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); - 80030da: f001 ff23 bl 8004f24 + 8003c56: f001 ff25 bl 8005aa4 /* Return to the original privilege level before exiting the function. */ traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; - 80030de: 2300 movs r3, #0 - 80030e0: e05c b.n 800319c + 8003c5a: 2300 movs r3, #0 + 8003c5c: e05c b.n 8003d18 } else if( xEntryTimeSet == pdFALSE ) - 80030e2: 6b7b ldr r3, [r7, #52] ; 0x34 - 80030e4: 2b00 cmp r3, #0 - 80030e6: d106 bne.n 80030f6 + 8003c5e: 6b7b ldr r3, [r7, #52] ; 0x34 + 8003c60: 2b00 cmp r3, #0 + 8003c62: d106 bne.n 8003c72 { /* The queue was full and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); - 80030e8: f107 0314 add.w r3, r7, #20 - 80030ec: 4618 mov r0, r3 - 80030ee: f001 f82f bl 8004150 + 8003c64: f107 0314 add.w r3, r7, #20 + 8003c68: 4618 mov r0, r3 + 8003c6a: f001 f82f bl 8004ccc xEntryTimeSet = pdTRUE; - 80030f2: 2301 movs r3, #1 - 80030f4: 637b str r3, [r7, #52] ; 0x34 + 8003c6e: 2301 movs r3, #1 + 8003c70: 637b str r3, [r7, #52] ; 0x34 /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); - 80030f6: f001 ff15 bl 8004f24 + 8003c72: f001 ff17 bl 8005aa4 /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); - 80030fa: f000 fd9b bl 8003c34 + 8003c76: f000 fd9b bl 80047b0 prvLockQueue( pxQueue ); - 80030fe: f001 fee1 bl 8004ec4 - 8003102: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003104: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 - 8003108: b25b sxtb r3, r3 - 800310a: f1b3 3fff cmp.w r3, #4294967295 - 800310e: d103 bne.n 8003118 - 8003110: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003112: 2200 movs r2, #0 - 8003114: f883 2044 strb.w r2, [r3, #68] ; 0x44 - 8003118: 6b3b ldr r3, [r7, #48] ; 0x30 - 800311a: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 - 800311e: b25b sxtb r3, r3 - 8003120: f1b3 3fff cmp.w r3, #4294967295 - 8003124: d103 bne.n 800312e - 8003126: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003128: 2200 movs r2, #0 - 800312a: f883 2045 strb.w r2, [r3, #69] ; 0x45 - 800312e: f001 fef9 bl 8004f24 + 8003c7a: f001 fee3 bl 8005a44 + 8003c7e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003c80: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 + 8003c84: b25b sxtb r3, r3 + 8003c86: f1b3 3fff cmp.w r3, #4294967295 + 8003c8a: d103 bne.n 8003c94 + 8003c8c: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003c8e: 2200 movs r2, #0 + 8003c90: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 8003c94: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003c96: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 8003c9a: b25b sxtb r3, r3 + 8003c9c: f1b3 3fff cmp.w r3, #4294967295 + 8003ca0: d103 bne.n 8003caa + 8003ca2: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003ca4: 2200 movs r2, #0 + 8003ca6: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 8003caa: f001 fefb bl 8005aa4 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - 8003132: 1d3a adds r2, r7, #4 - 8003134: f107 0314 add.w r3, r7, #20 - 8003138: 4611 mov r1, r2 - 800313a: 4618 mov r0, r3 - 800313c: f001 f81e bl 800417c - 8003140: 4603 mov r3, r0 - 8003142: 2b00 cmp r3, #0 - 8003144: d124 bne.n 8003190 + 8003cae: 1d3a adds r2, r7, #4 + 8003cb0: f107 0314 add.w r3, r7, #20 + 8003cb4: 4611 mov r1, r2 + 8003cb6: 4618 mov r0, r3 + 8003cb8: f001 f81e bl 8004cf8 + 8003cbc: 4603 mov r3, r0 + 8003cbe: 2b00 cmp r3, #0 + 8003cc0: d124 bne.n 8003d0c { if( prvIsQueueFull( pxQueue ) != pdFALSE ) - 8003146: 6b38 ldr r0, [r7, #48] ; 0x30 - 8003148: f000 faa2 bl 8003690 - 800314c: 4603 mov r3, r0 - 800314e: 2b00 cmp r3, #0 - 8003150: d018 beq.n 8003184 + 8003cc2: 6b38 ldr r0, [r7, #48] ; 0x30 + 8003cc4: f000 faa2 bl 800420c + 8003cc8: 4603 mov r3, r0 + 8003cca: 2b00 cmp r3, #0 + 8003ccc: d018 beq.n 8003d00 { traceBLOCKING_ON_QUEUE_SEND( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait ); - 8003152: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003154: 3310 adds r3, #16 - 8003156: 687a ldr r2, [r7, #4] - 8003158: 4611 mov r1, r2 - 800315a: 4618 mov r0, r3 - 800315c: f000 ff44 bl 8003fe8 + 8003cce: 6b3b ldr r3, [r7, #48] ; 0x30 + 8003cd0: 3310 adds r3, #16 + 8003cd2: 687a ldr r2, [r7, #4] + 8003cd4: 4611 mov r1, r2 + 8003cd6: 4618 mov r0, r3 + 8003cd8: f000 ff44 bl 8004b64 /* Unlocking the queue means queue events can effect the event list. It is possible that interrupts occurring now remove this task from the event list again - but as the scheduler is suspended the task will go onto the pending ready last instead of the actual ready list. */ prvUnlockQueue( pxQueue ); - 8003160: 6b38 ldr r0, [r7, #48] ; 0x30 - 8003162: f000 fa2d bl 80035c0 + 8003cdc: 6b38 ldr r0, [r7, #48] ; 0x30 + 8003cde: f000 fa2d bl 800413c /* Resuming the scheduler will move tasks from the pending ready list into the ready list - so it is feasible that this task is already in a ready list before it yields - in which case the yield will not cause a context switch unless there is also a higher priority task in the pending ready list. */ if( xTaskResumeAll() == pdFALSE ) - 8003166: f000 fd73 bl 8003c50 - 800316a: 4603 mov r3, r0 - 800316c: 2b00 cmp r3, #0 - 800316e: f47f af7c bne.w 800306a + 8003ce2: f000 fd73 bl 80047cc + 8003ce6: 4603 mov r3, r0 + 8003ce8: 2b00 cmp r3, #0 + 8003cea: f47f af7c bne.w 8003be6 { portYIELD_WITHIN_API(); - 8003172: 4b0c ldr r3, [pc, #48] ; (80031a4 ) - 8003174: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 8003178: 601a str r2, [r3, #0] - 800317a: f3bf 8f4f dsb sy - 800317e: f3bf 8f6f isb sy - 8003182: e772 b.n 800306a + 8003cee: 4b0c ldr r3, [pc, #48] ; (8003d20 ) + 8003cf0: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8003cf4: 601a str r2, [r3, #0] + 8003cf6: f3bf 8f4f dsb sy + 8003cfa: f3bf 8f6f isb sy + 8003cfe: e772 b.n 8003be6 } } else { /* Try again. */ prvUnlockQueue( pxQueue ); - 8003184: 6b38 ldr r0, [r7, #48] ; 0x30 - 8003186: f000 fa1b bl 80035c0 + 8003d00: 6b38 ldr r0, [r7, #48] ; 0x30 + 8003d02: f000 fa1b bl 800413c ( void ) xTaskResumeAll(); - 800318a: f000 fd61 bl 8003c50 - 800318e: e76c b.n 800306a + 8003d06: f000 fd61 bl 80047cc + 8003d0a: e76c b.n 8003be6 } } else { /* The timeout has expired. */ prvUnlockQueue( pxQueue ); - 8003190: 6b38 ldr r0, [r7, #48] ; 0x30 - 8003192: f000 fa15 bl 80035c0 + 8003d0c: 6b38 ldr r0, [r7, #48] ; 0x30 + 8003d0e: f000 fa15 bl 800413c ( void ) xTaskResumeAll(); - 8003196: f000 fd5b bl 8003c50 + 8003d12: f000 fd5b bl 80047cc traceQUEUE_SEND_FAILED( pxQueue ); return errQUEUE_FULL; - 800319a: 2300 movs r3, #0 + 8003d16: 2300 movs r3, #0 } } /*lint -restore */ } - 800319c: 4618 mov r0, r3 - 800319e: 3738 adds r7, #56 ; 0x38 - 80031a0: 46bd mov sp, r7 - 80031a2: bd80 pop {r7, pc} - 80031a4: e000ed04 .word 0xe000ed04 + 8003d18: 4618 mov r0, r3 + 8003d1a: 3738 adds r7, #56 ; 0x38 + 8003d1c: 46bd mov sp, r7 + 8003d1e: bd80 pop {r7, pc} + 8003d20: e000ed04 .word 0xe000ed04 -080031a8 : +08003d24 : /*-----------------------------------------------------------*/ BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) { - 80031a8: b580 push {r7, lr} - 80031aa: b090 sub sp, #64 ; 0x40 - 80031ac: af00 add r7, sp, #0 - 80031ae: 60f8 str r0, [r7, #12] - 80031b0: 60b9 str r1, [r7, #8] - 80031b2: 607a str r2, [r7, #4] - 80031b4: 603b str r3, [r7, #0] + 8003d24: b580 push {r7, lr} + 8003d26: b090 sub sp, #64 ; 0x40 + 8003d28: af00 add r7, sp, #0 + 8003d2a: 60f8 str r0, [r7, #12] + 8003d2c: 60b9 str r1, [r7, #8] + 8003d2e: 607a str r2, [r7, #4] + 8003d30: 603b str r3, [r7, #0] BaseType_t xReturn; UBaseType_t uxSavedInterruptStatus; Queue_t * const pxQueue = xQueue; - 80031b6: 68fb ldr r3, [r7, #12] - 80031b8: 63bb str r3, [r7, #56] ; 0x38 + 8003d32: 68fb ldr r3, [r7, #12] + 8003d34: 63bb str r3, [r7, #56] ; 0x38 configASSERT( pxQueue ); - 80031ba: 6bbb ldr r3, [r7, #56] ; 0x38 - 80031bc: 2b00 cmp r3, #0 - 80031be: d10a bne.n 80031d6 + 8003d36: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003d38: 2b00 cmp r3, #0 + 8003d3a: d10a bne.n 8003d52 __asm volatile - 80031c0: f04f 0350 mov.w r3, #80 ; 0x50 - 80031c4: f383 8811 msr BASEPRI, r3 - 80031c8: f3bf 8f6f isb sy - 80031cc: f3bf 8f4f dsb sy - 80031d0: 62bb str r3, [r7, #40] ; 0x28 + 8003d3c: f04f 0350 mov.w r3, #80 ; 0x50 + 8003d40: f383 8811 msr BASEPRI, r3 + 8003d44: f3bf 8f6f isb sy + 8003d48: f3bf 8f4f dsb sy + 8003d4c: 62bb str r3, [r7, #40] ; 0x28 } - 80031d2: bf00 nop - 80031d4: e7fe b.n 80031d4 + 8003d4e: bf00 nop + 8003d50: e7fe b.n 8003d50 configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) ); - 80031d6: 68bb ldr r3, [r7, #8] - 80031d8: 2b00 cmp r3, #0 - 80031da: d103 bne.n 80031e4 - 80031dc: 6bbb ldr r3, [r7, #56] ; 0x38 - 80031de: 6c1b ldr r3, [r3, #64] ; 0x40 - 80031e0: 2b00 cmp r3, #0 - 80031e2: d101 bne.n 80031e8 - 80031e4: 2301 movs r3, #1 - 80031e6: e000 b.n 80031ea - 80031e8: 2300 movs r3, #0 - 80031ea: 2b00 cmp r3, #0 - 80031ec: d10a bne.n 8003204 + 8003d52: 68bb ldr r3, [r7, #8] + 8003d54: 2b00 cmp r3, #0 + 8003d56: d103 bne.n 8003d60 + 8003d58: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003d5a: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003d5c: 2b00 cmp r3, #0 + 8003d5e: d101 bne.n 8003d64 + 8003d60: 2301 movs r3, #1 + 8003d62: e000 b.n 8003d66 + 8003d64: 2300 movs r3, #0 + 8003d66: 2b00 cmp r3, #0 + 8003d68: d10a bne.n 8003d80 __asm volatile - 80031ee: f04f 0350 mov.w r3, #80 ; 0x50 - 80031f2: f383 8811 msr BASEPRI, r3 - 80031f6: f3bf 8f6f isb sy - 80031fa: f3bf 8f4f dsb sy - 80031fe: 627b str r3, [r7, #36] ; 0x24 + 8003d6a: f04f 0350 mov.w r3, #80 ; 0x50 + 8003d6e: f383 8811 msr BASEPRI, r3 + 8003d72: f3bf 8f6f isb sy + 8003d76: f3bf 8f4f dsb sy + 8003d7a: 627b str r3, [r7, #36] ; 0x24 } - 8003200: bf00 nop - 8003202: e7fe b.n 8003202 + 8003d7c: bf00 nop + 8003d7e: e7fe b.n 8003d7e configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) ); - 8003204: 683b ldr r3, [r7, #0] - 8003206: 2b02 cmp r3, #2 - 8003208: d103 bne.n 8003212 - 800320a: 6bbb ldr r3, [r7, #56] ; 0x38 - 800320c: 6bdb ldr r3, [r3, #60] ; 0x3c - 800320e: 2b01 cmp r3, #1 - 8003210: d101 bne.n 8003216 - 8003212: 2301 movs r3, #1 - 8003214: e000 b.n 8003218 - 8003216: 2300 movs r3, #0 - 8003218: 2b00 cmp r3, #0 - 800321a: d10a bne.n 8003232 + 8003d80: 683b ldr r3, [r7, #0] + 8003d82: 2b02 cmp r3, #2 + 8003d84: d103 bne.n 8003d8e + 8003d86: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003d88: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003d8a: 2b01 cmp r3, #1 + 8003d8c: d101 bne.n 8003d92 + 8003d8e: 2301 movs r3, #1 + 8003d90: e000 b.n 8003d94 + 8003d92: 2300 movs r3, #0 + 8003d94: 2b00 cmp r3, #0 + 8003d96: d10a bne.n 8003dae __asm volatile - 800321c: f04f 0350 mov.w r3, #80 ; 0x50 - 8003220: f383 8811 msr BASEPRI, r3 - 8003224: f3bf 8f6f isb sy - 8003228: f3bf 8f4f dsb sy - 800322c: 623b str r3, [r7, #32] + 8003d98: f04f 0350 mov.w r3, #80 ; 0x50 + 8003d9c: f383 8811 msr BASEPRI, r3 + 8003da0: f3bf 8f6f isb sy + 8003da4: f3bf 8f4f dsb sy + 8003da8: 623b str r3, [r7, #32] } - 800322e: bf00 nop - 8003230: e7fe b.n 8003230 + 8003daa: bf00 nop + 8003dac: e7fe b.n 8003dac that have been assigned a priority at or (logically) below the maximum system call interrupt priority. FreeRTOS maintains a separate interrupt safe API to ensure interrupt entry is as fast and as simple as possible. More information (albeit Cortex-M specific) is provided on the following link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */ portASSERT_IF_INTERRUPT_PRIORITY_INVALID(); - 8003232: f001 ff29 bl 8005088 + 8003dae: f001 ff2b bl 8005c08 portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void ) { uint32_t ulOriginalBASEPRI, ulNewBASEPRI; __asm volatile - 8003236: f3ef 8211 mrs r2, BASEPRI - 800323a: f04f 0350 mov.w r3, #80 ; 0x50 - 800323e: f383 8811 msr BASEPRI, r3 - 8003242: f3bf 8f6f isb sy - 8003246: f3bf 8f4f dsb sy - 800324a: 61fa str r2, [r7, #28] - 800324c: 61bb str r3, [r7, #24] + 8003db2: f3ef 8211 mrs r2, BASEPRI + 8003db6: f04f 0350 mov.w r3, #80 ; 0x50 + 8003dba: f383 8811 msr BASEPRI, r3 + 8003dbe: f3bf 8f6f isb sy + 8003dc2: f3bf 8f4f dsb sy + 8003dc6: 61fa str r2, [r7, #28] + 8003dc8: 61bb str r3, [r7, #24] :"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory" ); /* This return will not be reached but is necessary to prevent compiler warnings. */ return ulOriginalBASEPRI; - 800324e: 69fb ldr r3, [r7, #28] + 8003dca: 69fb ldr r3, [r7, #28] /* Similar to xQueueGenericSend, except without blocking if there is no room in the queue. Also don't directly wake a task that was blocked on a queue read, instead return a flag to say whether a context switch is required or not (i.e. has a task with a higher priority than us been woken by this post). */ uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); - 8003250: 637b str r3, [r7, #52] ; 0x34 + 8003dcc: 637b str r3, [r7, #52] ; 0x34 { if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) ) - 8003252: 6bbb ldr r3, [r7, #56] ; 0x38 - 8003254: 6b9a ldr r2, [r3, #56] ; 0x38 - 8003256: 6bbb ldr r3, [r7, #56] ; 0x38 - 8003258: 6bdb ldr r3, [r3, #60] ; 0x3c - 800325a: 429a cmp r2, r3 - 800325c: d302 bcc.n 8003264 - 800325e: 683b ldr r3, [r7, #0] - 8003260: 2b02 cmp r3, #2 - 8003262: d12f bne.n 80032c4 + 8003dce: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003dd0: 6b9a ldr r2, [r3, #56] ; 0x38 + 8003dd2: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003dd4: 6bdb ldr r3, [r3, #60] ; 0x3c + 8003dd6: 429a cmp r2, r3 + 8003dd8: d302 bcc.n 8003de0 + 8003dda: 683b ldr r3, [r7, #0] + 8003ddc: 2b02 cmp r3, #2 + 8003dde: d12f bne.n 8003e40 { const int8_t cTxLock = pxQueue->cTxLock; - 8003264: 6bbb ldr r3, [r7, #56] ; 0x38 - 8003266: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 - 800326a: f887 3033 strb.w r3, [r7, #51] ; 0x33 + 8003de0: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003de2: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 8003de6: f887 3033 strb.w r3, [r7, #51] ; 0x33 const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting; - 800326e: 6bbb ldr r3, [r7, #56] ; 0x38 - 8003270: 6b9b ldr r3, [r3, #56] ; 0x38 - 8003272: 62fb str r3, [r7, #44] ; 0x2c + 8003dea: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003dec: 6b9b ldr r3, [r3, #56] ; 0x38 + 8003dee: 62fb str r3, [r7, #44] ; 0x2c /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a semaphore or mutex. That means prvCopyDataToQueue() cannot result in a task disinheriting a priority and prvCopyDataToQueue() can be called here even though the disinherit function does not check if the scheduler is suspended before accessing the ready lists. */ ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition ); - 8003274: 683a ldr r2, [r7, #0] - 8003276: 68b9 ldr r1, [r7, #8] - 8003278: 6bb8 ldr r0, [r7, #56] ; 0x38 - 800327a: f000 f911 bl 80034a0 + 8003df0: 683a ldr r2, [r7, #0] + 8003df2: 68b9 ldr r1, [r7, #8] + 8003df4: 6bb8 ldr r0, [r7, #56] ; 0x38 + 8003df6: f000 f911 bl 800401c /* The event list is not altered if the queue is locked. This will be done when the queue is unlocked later. */ if( cTxLock == queueUNLOCKED ) - 800327e: f997 3033 ldrsb.w r3, [r7, #51] ; 0x33 - 8003282: f1b3 3fff cmp.w r3, #4294967295 - 8003286: d112 bne.n 80032ae + 8003dfa: f997 3033 ldrsb.w r3, [r7, #51] ; 0x33 + 8003dfe: f1b3 3fff cmp.w r3, #4294967295 + 8003e02: d112 bne.n 8003e2a } } } #else /* configUSE_QUEUE_SETS */ { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) - 8003288: 6bbb ldr r3, [r7, #56] ; 0x38 - 800328a: 6a5b ldr r3, [r3, #36] ; 0x24 - 800328c: 2b00 cmp r3, #0 - 800328e: d016 beq.n 80032be + 8003e04: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003e06: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003e08: 2b00 cmp r3, #0 + 8003e0a: d016 beq.n 8003e3a { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - 8003290: 6bbb ldr r3, [r7, #56] ; 0x38 - 8003292: 3324 adds r3, #36 ; 0x24 - 8003294: 4618 mov r0, r3 - 8003296: f000 fef7 bl 8004088 - 800329a: 4603 mov r3, r0 - 800329c: 2b00 cmp r3, #0 - 800329e: d00e beq.n 80032be + 8003e0c: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003e0e: 3324 adds r3, #36 ; 0x24 + 8003e10: 4618 mov r0, r3 + 8003e12: f000 fef7 bl 8004c04 + 8003e16: 4603 mov r3, r0 + 8003e18: 2b00 cmp r3, #0 + 8003e1a: d00e beq.n 8003e3a { /* The task waiting has a higher priority so record that a context switch is required. */ if( pxHigherPriorityTaskWoken != NULL ) - 80032a0: 687b ldr r3, [r7, #4] - 80032a2: 2b00 cmp r3, #0 - 80032a4: d00b beq.n 80032be + 8003e1c: 687b ldr r3, [r7, #4] + 8003e1e: 2b00 cmp r3, #0 + 8003e20: d00b beq.n 8003e3a { *pxHigherPriorityTaskWoken = pdTRUE; - 80032a6: 687b ldr r3, [r7, #4] - 80032a8: 2201 movs r2, #1 - 80032aa: 601a str r2, [r3, #0] - 80032ac: e007 b.n 80032be + 8003e22: 687b ldr r3, [r7, #4] + 8003e24: 2201 movs r2, #1 + 8003e26: 601a str r2, [r3, #0] + 8003e28: e007 b.n 8003e3a } else { /* Increment the lock count so the task that unlocks the queue knows that data was posted while it was locked. */ pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 ); - 80032ae: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 - 80032b2: 3301 adds r3, #1 - 80032b4: b2db uxtb r3, r3 - 80032b6: b25a sxtb r2, r3 - 80032b8: 6bbb ldr r3, [r7, #56] ; 0x38 - 80032ba: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 8003e2a: f897 3033 ldrb.w r3, [r7, #51] ; 0x33 + 8003e2e: 3301 adds r3, #1 + 8003e30: b2db uxtb r3, r3 + 8003e32: b25a sxtb r2, r3 + 8003e34: 6bbb ldr r3, [r7, #56] ; 0x38 + 8003e36: f883 2045 strb.w r2, [r3, #69] ; 0x45 } xReturn = pdPASS; - 80032be: 2301 movs r3, #1 - 80032c0: 63fb str r3, [r7, #60] ; 0x3c + 8003e3a: 2301 movs r3, #1 + 8003e3c: 63fb str r3, [r7, #60] ; 0x3c { - 80032c2: e001 b.n 80032c8 + 8003e3e: e001 b.n 8003e44 } else { traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ); xReturn = errQUEUE_FULL; - 80032c4: 2300 movs r3, #0 - 80032c6: 63fb str r3, [r7, #60] ; 0x3c - 80032c8: 6b7b ldr r3, [r7, #52] ; 0x34 - 80032ca: 617b str r3, [r7, #20] + 8003e40: 2300 movs r3, #0 + 8003e42: 63fb str r3, [r7, #60] ; 0x3c + 8003e44: 6b7b ldr r3, [r7, #52] ; 0x34 + 8003e46: 617b str r3, [r7, #20] } /*-----------------------------------------------------------*/ portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue ) { __asm volatile - 80032cc: 697b ldr r3, [r7, #20] - 80032ce: f383 8811 msr BASEPRI, r3 + 8003e48: 697b ldr r3, [r7, #20] + 8003e4a: f383 8811 msr BASEPRI, r3 ( " msr basepri, %0 " :: "r" ( ulNewMaskValue ) : "memory" ); } - 80032d2: bf00 nop + 8003e4e: bf00 nop } } portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); return xReturn; - 80032d4: 6bfb ldr r3, [r7, #60] ; 0x3c + 8003e50: 6bfb ldr r3, [r7, #60] ; 0x3c } - 80032d6: 4618 mov r0, r3 - 80032d8: 3740 adds r7, #64 ; 0x40 - 80032da: 46bd mov sp, r7 - 80032dc: bd80 pop {r7, pc} + 8003e52: 4618 mov r0, r3 + 8003e54: 3740 adds r7, #64 ; 0x40 + 8003e56: 46bd mov sp, r7 + 8003e58: bd80 pop {r7, pc} ... -080032e0 : +08003e5c : return xReturn; } /*-----------------------------------------------------------*/ BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) { - 80032e0: b580 push {r7, lr} - 80032e2: b08c sub sp, #48 ; 0x30 - 80032e4: af00 add r7, sp, #0 - 80032e6: 60f8 str r0, [r7, #12] - 80032e8: 60b9 str r1, [r7, #8] - 80032ea: 607a str r2, [r7, #4] + 8003e5c: b580 push {r7, lr} + 8003e5e: b08c sub sp, #48 ; 0x30 + 8003e60: af00 add r7, sp, #0 + 8003e62: 60f8 str r0, [r7, #12] + 8003e64: 60b9 str r1, [r7, #8] + 8003e66: 607a str r2, [r7, #4] BaseType_t xEntryTimeSet = pdFALSE; - 80032ec: 2300 movs r3, #0 - 80032ee: 62fb str r3, [r7, #44] ; 0x2c + 8003e68: 2300 movs r3, #0 + 8003e6a: 62fb str r3, [r7, #44] ; 0x2c TimeOut_t xTimeOut; Queue_t * const pxQueue = xQueue; - 80032f0: 68fb ldr r3, [r7, #12] - 80032f2: 62bb str r3, [r7, #40] ; 0x28 + 8003e6c: 68fb ldr r3, [r7, #12] + 8003e6e: 62bb str r3, [r7, #40] ; 0x28 /* Check the pointer is not NULL. */ configASSERT( ( pxQueue ) ); - 80032f4: 6abb ldr r3, [r7, #40] ; 0x28 - 80032f6: 2b00 cmp r3, #0 - 80032f8: d10a bne.n 8003310 + 8003e70: 6abb ldr r3, [r7, #40] ; 0x28 + 8003e72: 2b00 cmp r3, #0 + 8003e74: d10a bne.n 8003e8c __asm volatile - 80032fa: f04f 0350 mov.w r3, #80 ; 0x50 - 80032fe: f383 8811 msr BASEPRI, r3 - 8003302: f3bf 8f6f isb sy - 8003306: f3bf 8f4f dsb sy - 800330a: 623b str r3, [r7, #32] + 8003e76: f04f 0350 mov.w r3, #80 ; 0x50 + 8003e7a: f383 8811 msr BASEPRI, r3 + 8003e7e: f3bf 8f6f isb sy + 8003e82: f3bf 8f4f dsb sy + 8003e86: 623b str r3, [r7, #32] } - 800330c: bf00 nop - 800330e: e7fe b.n 800330e + 8003e88: bf00 nop + 8003e8a: e7fe b.n 8003e8a /* The buffer into which data is received can only be NULL if the data size is zero (so no data is copied into the buffer. */ configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) ); - 8003310: 68bb ldr r3, [r7, #8] - 8003312: 2b00 cmp r3, #0 - 8003314: d103 bne.n 800331e - 8003316: 6abb ldr r3, [r7, #40] ; 0x28 - 8003318: 6c1b ldr r3, [r3, #64] ; 0x40 - 800331a: 2b00 cmp r3, #0 - 800331c: d101 bne.n 8003322 - 800331e: 2301 movs r3, #1 - 8003320: e000 b.n 8003324 - 8003322: 2300 movs r3, #0 - 8003324: 2b00 cmp r3, #0 - 8003326: d10a bne.n 800333e + 8003e8c: 68bb ldr r3, [r7, #8] + 8003e8e: 2b00 cmp r3, #0 + 8003e90: d103 bne.n 8003e9a + 8003e92: 6abb ldr r3, [r7, #40] ; 0x28 + 8003e94: 6c1b ldr r3, [r3, #64] ; 0x40 + 8003e96: 2b00 cmp r3, #0 + 8003e98: d101 bne.n 8003e9e + 8003e9a: 2301 movs r3, #1 + 8003e9c: e000 b.n 8003ea0 + 8003e9e: 2300 movs r3, #0 + 8003ea0: 2b00 cmp r3, #0 + 8003ea2: d10a bne.n 8003eba __asm volatile - 8003328: f04f 0350 mov.w r3, #80 ; 0x50 - 800332c: f383 8811 msr BASEPRI, r3 - 8003330: f3bf 8f6f isb sy - 8003334: f3bf 8f4f dsb sy - 8003338: 61fb str r3, [r7, #28] + 8003ea4: f04f 0350 mov.w r3, #80 ; 0x50 + 8003ea8: f383 8811 msr BASEPRI, r3 + 8003eac: f3bf 8f6f isb sy + 8003eb0: f3bf 8f4f dsb sy + 8003eb4: 61fb str r3, [r7, #28] } - 800333a: bf00 nop - 800333c: e7fe b.n 800333c + 8003eb6: bf00 nop + 8003eb8: e7fe b.n 8003eb8 /* Cannot block if the scheduler is suspended. */ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) { configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); - 800333e: f001 f865 bl 800440c - 8003342: 4603 mov r3, r0 - 8003344: 2b00 cmp r3, #0 - 8003346: d102 bne.n 800334e - 8003348: 687b ldr r3, [r7, #4] - 800334a: 2b00 cmp r3, #0 - 800334c: d101 bne.n 8003352 - 800334e: 2301 movs r3, #1 - 8003350: e000 b.n 8003354 - 8003352: 2300 movs r3, #0 - 8003354: 2b00 cmp r3, #0 - 8003356: d10a bne.n 800336e + 8003eba: f001 f865 bl 8004f88 + 8003ebe: 4603 mov r3, r0 + 8003ec0: 2b00 cmp r3, #0 + 8003ec2: d102 bne.n 8003eca + 8003ec4: 687b ldr r3, [r7, #4] + 8003ec6: 2b00 cmp r3, #0 + 8003ec8: d101 bne.n 8003ece + 8003eca: 2301 movs r3, #1 + 8003ecc: e000 b.n 8003ed0 + 8003ece: 2300 movs r3, #0 + 8003ed0: 2b00 cmp r3, #0 + 8003ed2: d10a bne.n 8003eea __asm volatile - 8003358: f04f 0350 mov.w r3, #80 ; 0x50 - 800335c: f383 8811 msr BASEPRI, r3 - 8003360: f3bf 8f6f isb sy - 8003364: f3bf 8f4f dsb sy - 8003368: 61bb str r3, [r7, #24] + 8003ed4: f04f 0350 mov.w r3, #80 ; 0x50 + 8003ed8: f383 8811 msr BASEPRI, r3 + 8003edc: f3bf 8f6f isb sy + 8003ee0: f3bf 8f4f dsb sy + 8003ee4: 61bb str r3, [r7, #24] } - 800336a: bf00 nop - 800336c: e7fe b.n 800336c + 8003ee6: bf00 nop + 8003ee8: e7fe b.n 8003ee8 /*lint -save -e904 This function relaxes the coding standard somewhat to allow return statements within the function itself. This is done in the interest of execution time efficiency. */ for( ;; ) { taskENTER_CRITICAL(); - 800336e: f001 fda9 bl 8004ec4 + 8003eea: f001 fdab bl 8005a44 { const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting; - 8003372: 6abb ldr r3, [r7, #40] ; 0x28 - 8003374: 6b9b ldr r3, [r3, #56] ; 0x38 - 8003376: 627b str r3, [r7, #36] ; 0x24 + 8003eee: 6abb ldr r3, [r7, #40] ; 0x28 + 8003ef0: 6b9b ldr r3, [r3, #56] ; 0x38 + 8003ef2: 627b str r3, [r7, #36] ; 0x24 /* Is there data in the queue now? To be running the calling task must be the highest priority task wanting to access the queue. */ if( uxMessagesWaiting > ( UBaseType_t ) 0 ) - 8003378: 6a7b ldr r3, [r7, #36] ; 0x24 - 800337a: 2b00 cmp r3, #0 - 800337c: d01f beq.n 80033be + 8003ef4: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003ef6: 2b00 cmp r3, #0 + 8003ef8: d01f beq.n 8003f3a { /* Data available, remove one item. */ prvCopyDataFromQueue( pxQueue, pvBuffer ); - 800337e: 68b9 ldr r1, [r7, #8] - 8003380: 6ab8 ldr r0, [r7, #40] ; 0x28 - 8003382: f000 f8f7 bl 8003574 + 8003efa: 68b9 ldr r1, [r7, #8] + 8003efc: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8003efe: f000 f8f7 bl 80040f0 traceQUEUE_RECEIVE( pxQueue ); pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1; - 8003386: 6a7b ldr r3, [r7, #36] ; 0x24 - 8003388: 1e5a subs r2, r3, #1 - 800338a: 6abb ldr r3, [r7, #40] ; 0x28 - 800338c: 639a str r2, [r3, #56] ; 0x38 + 8003f02: 6a7b ldr r3, [r7, #36] ; 0x24 + 8003f04: 1e5a subs r2, r3, #1 + 8003f06: 6abb ldr r3, [r7, #40] ; 0x28 + 8003f08: 639a str r2, [r3, #56] ; 0x38 /* There is now space in the queue, were any tasks waiting to post to the queue? If so, unblock the highest priority waiting task. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) - 800338e: 6abb ldr r3, [r7, #40] ; 0x28 - 8003390: 691b ldr r3, [r3, #16] - 8003392: 2b00 cmp r3, #0 - 8003394: d00f beq.n 80033b6 + 8003f0a: 6abb ldr r3, [r7, #40] ; 0x28 + 8003f0c: 691b ldr r3, [r3, #16] + 8003f0e: 2b00 cmp r3, #0 + 8003f10: d00f beq.n 8003f32 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - 8003396: 6abb ldr r3, [r7, #40] ; 0x28 - 8003398: 3310 adds r3, #16 - 800339a: 4618 mov r0, r3 - 800339c: f000 fe74 bl 8004088 - 80033a0: 4603 mov r3, r0 - 80033a2: 2b00 cmp r3, #0 - 80033a4: d007 beq.n 80033b6 + 8003f12: 6abb ldr r3, [r7, #40] ; 0x28 + 8003f14: 3310 adds r3, #16 + 8003f16: 4618 mov r0, r3 + 8003f18: f000 fe74 bl 8004c04 + 8003f1c: 4603 mov r3, r0 + 8003f1e: 2b00 cmp r3, #0 + 8003f20: d007 beq.n 8003f32 { queueYIELD_IF_USING_PREEMPTION(); - 80033a6: 4b3d ldr r3, [pc, #244] ; (800349c ) - 80033a8: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 80033ac: 601a str r2, [r3, #0] - 80033ae: f3bf 8f4f dsb sy - 80033b2: f3bf 8f6f isb sy + 8003f22: 4b3d ldr r3, [pc, #244] ; (8004018 ) + 8003f24: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8003f28: 601a str r2, [r3, #0] + 8003f2a: f3bf 8f4f dsb sy + 8003f2e: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } taskEXIT_CRITICAL(); - 80033b6: f001 fdb5 bl 8004f24 + 8003f32: f001 fdb7 bl 8005aa4 return pdPASS; - 80033ba: 2301 movs r3, #1 - 80033bc: e069 b.n 8003492 + 8003f36: 2301 movs r3, #1 + 8003f38: e069 b.n 800400e } else { if( xTicksToWait == ( TickType_t ) 0 ) - 80033be: 687b ldr r3, [r7, #4] - 80033c0: 2b00 cmp r3, #0 - 80033c2: d103 bne.n 80033cc + 8003f3a: 687b ldr r3, [r7, #4] + 8003f3c: 2b00 cmp r3, #0 + 8003f3e: d103 bne.n 8003f48 { /* The queue was empty and no block time is specified (or the block time has expired) so leave now. */ taskEXIT_CRITICAL(); - 80033c4: f001 fdae bl 8004f24 + 8003f40: f001 fdb0 bl 8005aa4 traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; - 80033c8: 2300 movs r3, #0 - 80033ca: e062 b.n 8003492 + 8003f44: 2300 movs r3, #0 + 8003f46: e062 b.n 800400e } else if( xEntryTimeSet == pdFALSE ) - 80033cc: 6afb ldr r3, [r7, #44] ; 0x2c - 80033ce: 2b00 cmp r3, #0 - 80033d0: d106 bne.n 80033e0 + 8003f48: 6afb ldr r3, [r7, #44] ; 0x2c + 8003f4a: 2b00 cmp r3, #0 + 8003f4c: d106 bne.n 8003f5c { /* The queue was empty and a block time was specified so configure the timeout structure. */ vTaskInternalSetTimeOutState( &xTimeOut ); - 80033d2: f107 0310 add.w r3, r7, #16 - 80033d6: 4618 mov r0, r3 - 80033d8: f000 feba bl 8004150 + 8003f4e: f107 0310 add.w r3, r7, #16 + 8003f52: 4618 mov r0, r3 + 8003f54: f000 feba bl 8004ccc xEntryTimeSet = pdTRUE; - 80033dc: 2301 movs r3, #1 - 80033de: 62fb str r3, [r7, #44] ; 0x2c + 8003f58: 2301 movs r3, #1 + 8003f5a: 62fb str r3, [r7, #44] ; 0x2c /* Entry time was already set. */ mtCOVERAGE_TEST_MARKER(); } } } taskEXIT_CRITICAL(); - 80033e0: f001 fda0 bl 8004f24 + 8003f5c: f001 fda2 bl 8005aa4 /* Interrupts and other tasks can send to and receive from the queue now the critical section has been exited. */ vTaskSuspendAll(); - 80033e4: f000 fc26 bl 8003c34 + 8003f60: f000 fc26 bl 80047b0 prvLockQueue( pxQueue ); - 80033e8: f001 fd6c bl 8004ec4 - 80033ec: 6abb ldr r3, [r7, #40] ; 0x28 - 80033ee: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 - 80033f2: b25b sxtb r3, r3 - 80033f4: f1b3 3fff cmp.w r3, #4294967295 - 80033f8: d103 bne.n 8003402 - 80033fa: 6abb ldr r3, [r7, #40] ; 0x28 - 80033fc: 2200 movs r2, #0 - 80033fe: f883 2044 strb.w r2, [r3, #68] ; 0x44 - 8003402: 6abb ldr r3, [r7, #40] ; 0x28 - 8003404: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 - 8003408: b25b sxtb r3, r3 - 800340a: f1b3 3fff cmp.w r3, #4294967295 - 800340e: d103 bne.n 8003418 - 8003410: 6abb ldr r3, [r7, #40] ; 0x28 - 8003412: 2200 movs r2, #0 - 8003414: f883 2045 strb.w r2, [r3, #69] ; 0x45 - 8003418: f001 fd84 bl 8004f24 + 8003f64: f001 fd6e bl 8005a44 + 8003f68: 6abb ldr r3, [r7, #40] ; 0x28 + 8003f6a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 + 8003f6e: b25b sxtb r3, r3 + 8003f70: f1b3 3fff cmp.w r3, #4294967295 + 8003f74: d103 bne.n 8003f7e + 8003f76: 6abb ldr r3, [r7, #40] ; 0x28 + 8003f78: 2200 movs r2, #0 + 8003f7a: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 8003f7e: 6abb ldr r3, [r7, #40] ; 0x28 + 8003f80: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 8003f84: b25b sxtb r3, r3 + 8003f86: f1b3 3fff cmp.w r3, #4294967295 + 8003f8a: d103 bne.n 8003f94 + 8003f8c: 6abb ldr r3, [r7, #40] ; 0x28 + 8003f8e: 2200 movs r2, #0 + 8003f90: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 8003f94: f001 fd86 bl 8005aa4 /* Update the timeout state to see if it has expired yet. */ if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE ) - 800341c: 1d3a adds r2, r7, #4 - 800341e: f107 0310 add.w r3, r7, #16 - 8003422: 4611 mov r1, r2 - 8003424: 4618 mov r0, r3 - 8003426: f000 fea9 bl 800417c - 800342a: 4603 mov r3, r0 - 800342c: 2b00 cmp r3, #0 - 800342e: d123 bne.n 8003478 + 8003f98: 1d3a adds r2, r7, #4 + 8003f9a: f107 0310 add.w r3, r7, #16 + 8003f9e: 4611 mov r1, r2 + 8003fa0: 4618 mov r0, r3 + 8003fa2: f000 fea9 bl 8004cf8 + 8003fa6: 4603 mov r3, r0 + 8003fa8: 2b00 cmp r3, #0 + 8003faa: d123 bne.n 8003ff4 { /* The timeout has not expired. If the queue is still empty place the task on the list of tasks waiting to receive from the queue. */ if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) - 8003430: 6ab8 ldr r0, [r7, #40] ; 0x28 - 8003432: f000 f917 bl 8003664 - 8003436: 4603 mov r3, r0 - 8003438: 2b00 cmp r3, #0 - 800343a: d017 beq.n 800346c + 8003fac: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8003fae: f000 f917 bl 80041e0 + 8003fb2: 4603 mov r3, r0 + 8003fb4: 2b00 cmp r3, #0 + 8003fb6: d017 beq.n 8003fe8 { traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ); vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait ); - 800343c: 6abb ldr r3, [r7, #40] ; 0x28 - 800343e: 3324 adds r3, #36 ; 0x24 - 8003440: 687a ldr r2, [r7, #4] - 8003442: 4611 mov r1, r2 - 8003444: 4618 mov r0, r3 - 8003446: f000 fdcf bl 8003fe8 + 8003fb8: 6abb ldr r3, [r7, #40] ; 0x28 + 8003fba: 3324 adds r3, #36 ; 0x24 + 8003fbc: 687a ldr r2, [r7, #4] + 8003fbe: 4611 mov r1, r2 + 8003fc0: 4618 mov r0, r3 + 8003fc2: f000 fdcf bl 8004b64 prvUnlockQueue( pxQueue ); - 800344a: 6ab8 ldr r0, [r7, #40] ; 0x28 - 800344c: f000 f8b8 bl 80035c0 + 8003fc6: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8003fc8: f000 f8b8 bl 800413c if( xTaskResumeAll() == pdFALSE ) - 8003450: f000 fbfe bl 8003c50 - 8003454: 4603 mov r3, r0 - 8003456: 2b00 cmp r3, #0 - 8003458: d189 bne.n 800336e + 8003fcc: f000 fbfe bl 80047cc + 8003fd0: 4603 mov r3, r0 + 8003fd2: 2b00 cmp r3, #0 + 8003fd4: d189 bne.n 8003eea { portYIELD_WITHIN_API(); - 800345a: 4b10 ldr r3, [pc, #64] ; (800349c ) - 800345c: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 8003460: 601a str r2, [r3, #0] - 8003462: f3bf 8f4f dsb sy - 8003466: f3bf 8f6f isb sy - 800346a: e780 b.n 800336e + 8003fd6: 4b10 ldr r3, [pc, #64] ; (8004018 ) + 8003fd8: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8003fdc: 601a str r2, [r3, #0] + 8003fde: f3bf 8f4f dsb sy + 8003fe2: f3bf 8f6f isb sy + 8003fe6: e780 b.n 8003eea } else { /* The queue contains data again. Loop back to try and read the data. */ prvUnlockQueue( pxQueue ); - 800346c: 6ab8 ldr r0, [r7, #40] ; 0x28 - 800346e: f000 f8a7 bl 80035c0 + 8003fe8: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8003fea: f000 f8a7 bl 800413c ( void ) xTaskResumeAll(); - 8003472: f000 fbed bl 8003c50 - 8003476: e77a b.n 800336e + 8003fee: f000 fbed bl 80047cc + 8003ff2: e77a b.n 8003eea } else { /* Timed out. If there is no data in the queue exit, otherwise loop back and attempt to read the data. */ prvUnlockQueue( pxQueue ); - 8003478: 6ab8 ldr r0, [r7, #40] ; 0x28 - 800347a: f000 f8a1 bl 80035c0 + 8003ff4: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8003ff6: f000 f8a1 bl 800413c ( void ) xTaskResumeAll(); - 800347e: f000 fbe7 bl 8003c50 + 8003ffa: f000 fbe7 bl 80047cc if( prvIsQueueEmpty( pxQueue ) != pdFALSE ) - 8003482: 6ab8 ldr r0, [r7, #40] ; 0x28 - 8003484: f000 f8ee bl 8003664 - 8003488: 4603 mov r3, r0 - 800348a: 2b00 cmp r3, #0 - 800348c: f43f af6f beq.w 800336e + 8003ffe: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8004000: f000 f8ee bl 80041e0 + 8004004: 4603 mov r3, r0 + 8004006: 2b00 cmp r3, #0 + 8004008: f43f af6f beq.w 8003eea { traceQUEUE_RECEIVE_FAILED( pxQueue ); return errQUEUE_EMPTY; - 8003490: 2300 movs r3, #0 + 800400c: 2300 movs r3, #0 { mtCOVERAGE_TEST_MARKER(); } } } /*lint -restore */ } - 8003492: 4618 mov r0, r3 - 8003494: 3730 adds r7, #48 ; 0x30 - 8003496: 46bd mov sp, r7 - 8003498: bd80 pop {r7, pc} - 800349a: bf00 nop - 800349c: e000ed04 .word 0xe000ed04 + 800400e: 4618 mov r0, r3 + 8004010: 3730 adds r7, #48 ; 0x30 + 8004012: 46bd mov sp, r7 + 8004014: bd80 pop {r7, pc} + 8004016: bf00 nop + 8004018: e000ed04 .word 0xe000ed04 -080034a0 : +0800401c : #endif /* configUSE_MUTEXES */ /*-----------------------------------------------------------*/ static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) { - 80034a0: b580 push {r7, lr} - 80034a2: b086 sub sp, #24 - 80034a4: af00 add r7, sp, #0 - 80034a6: 60f8 str r0, [r7, #12] - 80034a8: 60b9 str r1, [r7, #8] - 80034aa: 607a str r2, [r7, #4] + 800401c: b580 push {r7, lr} + 800401e: b086 sub sp, #24 + 8004020: af00 add r7, sp, #0 + 8004022: 60f8 str r0, [r7, #12] + 8004024: 60b9 str r1, [r7, #8] + 8004026: 607a str r2, [r7, #4] BaseType_t xReturn = pdFALSE; - 80034ac: 2300 movs r3, #0 - 80034ae: 617b str r3, [r7, #20] + 8004028: 2300 movs r3, #0 + 800402a: 617b str r3, [r7, #20] UBaseType_t uxMessagesWaiting; /* This function is called from a critical section. */ uxMessagesWaiting = pxQueue->uxMessagesWaiting; - 80034b0: 68fb ldr r3, [r7, #12] - 80034b2: 6b9b ldr r3, [r3, #56] ; 0x38 - 80034b4: 613b str r3, [r7, #16] + 800402c: 68fb ldr r3, [r7, #12] + 800402e: 6b9b ldr r3, [r3, #56] ; 0x38 + 8004030: 613b str r3, [r7, #16] if( pxQueue->uxItemSize == ( UBaseType_t ) 0 ) - 80034b6: 68fb ldr r3, [r7, #12] - 80034b8: 6c1b ldr r3, [r3, #64] ; 0x40 - 80034ba: 2b00 cmp r3, #0 - 80034bc: d10d bne.n 80034da + 8004032: 68fb ldr r3, [r7, #12] + 8004034: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004036: 2b00 cmp r3, #0 + 8004038: d10d bne.n 8004056 { #if ( configUSE_MUTEXES == 1 ) { if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) - 80034be: 68fb ldr r3, [r7, #12] - 80034c0: 681b ldr r3, [r3, #0] - 80034c2: 2b00 cmp r3, #0 - 80034c4: d14d bne.n 8003562 + 800403a: 68fb ldr r3, [r7, #12] + 800403c: 681b ldr r3, [r3, #0] + 800403e: 2b00 cmp r3, #0 + 8004040: d14d bne.n 80040de { /* The mutex is no longer being held. */ xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder ); - 80034c6: 68fb ldr r3, [r7, #12] - 80034c8: 689b ldr r3, [r3, #8] - 80034ca: 4618 mov r0, r3 - 80034cc: f000 ffbc bl 8004448 - 80034d0: 6178 str r0, [r7, #20] + 8004042: 68fb ldr r3, [r7, #12] + 8004044: 689b ldr r3, [r3, #8] + 8004046: 4618 mov r0, r3 + 8004048: f000 ffbc bl 8004fc4 + 800404c: 6178 str r0, [r7, #20] pxQueue->u.xSemaphore.xMutexHolder = NULL; - 80034d2: 68fb ldr r3, [r7, #12] - 80034d4: 2200 movs r2, #0 - 80034d6: 609a str r2, [r3, #8] - 80034d8: e043 b.n 8003562 + 800404e: 68fb ldr r3, [r7, #12] + 8004050: 2200 movs r2, #0 + 8004052: 609a str r2, [r3, #8] + 8004054: e043 b.n 80040de mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_MUTEXES */ } else if( xPosition == queueSEND_TO_BACK ) - 80034da: 687b ldr r3, [r7, #4] - 80034dc: 2b00 cmp r3, #0 - 80034de: d119 bne.n 8003514 + 8004056: 687b ldr r3, [r7, #4] + 8004058: 2b00 cmp r3, #0 + 800405a: d119 bne.n 8004090 { ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ - 80034e0: 68fb ldr r3, [r7, #12] - 80034e2: 6858 ldr r0, [r3, #4] - 80034e4: 68fb ldr r3, [r7, #12] - 80034e6: 6c1b ldr r3, [r3, #64] ; 0x40 - 80034e8: 461a mov r2, r3 - 80034ea: 68b9 ldr r1, [r7, #8] - 80034ec: f002 f87a bl 80055e4 + 800405c: 68fb ldr r3, [r7, #12] + 800405e: 6858 ldr r0, [r3, #4] + 8004060: 68fb ldr r3, [r7, #12] + 8004062: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004064: 461a mov r2, r3 + 8004066: 68b9 ldr r1, [r7, #8] + 8004068: f002 f87c bl 8006164 pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ - 80034f0: 68fb ldr r3, [r7, #12] - 80034f2: 685a ldr r2, [r3, #4] - 80034f4: 68fb ldr r3, [r7, #12] - 80034f6: 6c1b ldr r3, [r3, #64] ; 0x40 - 80034f8: 441a add r2, r3 - 80034fa: 68fb ldr r3, [r7, #12] - 80034fc: 605a str r2, [r3, #4] + 800406c: 68fb ldr r3, [r7, #12] + 800406e: 685a ldr r2, [r3, #4] + 8004070: 68fb ldr r3, [r7, #12] + 8004072: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004074: 441a add r2, r3 + 8004076: 68fb ldr r3, [r7, #12] + 8004078: 605a str r2, [r3, #4] if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ - 80034fe: 68fb ldr r3, [r7, #12] - 8003500: 685a ldr r2, [r3, #4] - 8003502: 68fb ldr r3, [r7, #12] - 8003504: 689b ldr r3, [r3, #8] - 8003506: 429a cmp r2, r3 - 8003508: d32b bcc.n 8003562 + 800407a: 68fb ldr r3, [r7, #12] + 800407c: 685a ldr r2, [r3, #4] + 800407e: 68fb ldr r3, [r7, #12] + 8004080: 689b ldr r3, [r3, #8] + 8004082: 429a cmp r2, r3 + 8004084: d32b bcc.n 80040de { pxQueue->pcWriteTo = pxQueue->pcHead; - 800350a: 68fb ldr r3, [r7, #12] - 800350c: 681a ldr r2, [r3, #0] - 800350e: 68fb ldr r3, [r7, #12] - 8003510: 605a str r2, [r3, #4] - 8003512: e026 b.n 8003562 + 8004086: 68fb ldr r3, [r7, #12] + 8004088: 681a ldr r2, [r3, #0] + 800408a: 68fb ldr r3, [r7, #12] + 800408c: 605a str r2, [r3, #4] + 800408e: e026 b.n 80040de mtCOVERAGE_TEST_MARKER(); } } else { ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. Assert checks null pointer only used when length is 0. */ - 8003514: 68fb ldr r3, [r7, #12] - 8003516: 68d8 ldr r0, [r3, #12] - 8003518: 68fb ldr r3, [r7, #12] - 800351a: 6c1b ldr r3, [r3, #64] ; 0x40 - 800351c: 461a mov r2, r3 - 800351e: 68b9 ldr r1, [r7, #8] - 8003520: f002 f860 bl 80055e4 + 8004090: 68fb ldr r3, [r7, #12] + 8004092: 68d8 ldr r0, [r3, #12] + 8004094: 68fb ldr r3, [r7, #12] + 8004096: 6c1b ldr r3, [r3, #64] ; 0x40 + 8004098: 461a mov r2, r3 + 800409a: 68b9 ldr r1, [r7, #8] + 800409c: f002 f862 bl 8006164 pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize; - 8003524: 68fb ldr r3, [r7, #12] - 8003526: 68da ldr r2, [r3, #12] - 8003528: 68fb ldr r3, [r7, #12] - 800352a: 6c1b ldr r3, [r3, #64] ; 0x40 - 800352c: 425b negs r3, r3 - 800352e: 441a add r2, r3 - 8003530: 68fb ldr r3, [r7, #12] - 8003532: 60da str r2, [r3, #12] + 80040a0: 68fb ldr r3, [r7, #12] + 80040a2: 68da ldr r2, [r3, #12] + 80040a4: 68fb ldr r3, [r7, #12] + 80040a6: 6c1b ldr r3, [r3, #64] ; 0x40 + 80040a8: 425b negs r3, r3 + 80040aa: 441a add r2, r3 + 80040ac: 68fb ldr r3, [r7, #12] + 80040ae: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */ - 8003534: 68fb ldr r3, [r7, #12] - 8003536: 68da ldr r2, [r3, #12] - 8003538: 68fb ldr r3, [r7, #12] - 800353a: 681b ldr r3, [r3, #0] - 800353c: 429a cmp r2, r3 - 800353e: d207 bcs.n 8003550 + 80040b0: 68fb ldr r3, [r7, #12] + 80040b2: 68da ldr r2, [r3, #12] + 80040b4: 68fb ldr r3, [r7, #12] + 80040b6: 681b ldr r3, [r3, #0] + 80040b8: 429a cmp r2, r3 + 80040ba: d207 bcs.n 80040cc { pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize ); - 8003540: 68fb ldr r3, [r7, #12] - 8003542: 689a ldr r2, [r3, #8] - 8003544: 68fb ldr r3, [r7, #12] - 8003546: 6c1b ldr r3, [r3, #64] ; 0x40 - 8003548: 425b negs r3, r3 - 800354a: 441a add r2, r3 - 800354c: 68fb ldr r3, [r7, #12] - 800354e: 60da str r2, [r3, #12] + 80040bc: 68fb ldr r3, [r7, #12] + 80040be: 689a ldr r2, [r3, #8] + 80040c0: 68fb ldr r3, [r7, #12] + 80040c2: 6c1b ldr r3, [r3, #64] ; 0x40 + 80040c4: 425b negs r3, r3 + 80040c6: 441a add r2, r3 + 80040c8: 68fb ldr r3, [r7, #12] + 80040ca: 60da str r2, [r3, #12] else { mtCOVERAGE_TEST_MARKER(); } if( xPosition == queueOVERWRITE ) - 8003550: 687b ldr r3, [r7, #4] - 8003552: 2b02 cmp r3, #2 - 8003554: d105 bne.n 8003562 + 80040cc: 687b ldr r3, [r7, #4] + 80040ce: 2b02 cmp r3, #2 + 80040d0: d105 bne.n 80040de { if( uxMessagesWaiting > ( UBaseType_t ) 0 ) - 8003556: 693b ldr r3, [r7, #16] - 8003558: 2b00 cmp r3, #0 - 800355a: d002 beq.n 8003562 + 80040d2: 693b ldr r3, [r7, #16] + 80040d4: 2b00 cmp r3, #0 + 80040d6: d002 beq.n 80040de { /* An item is not being added but overwritten, so subtract one from the recorded number of items in the queue so when one is added again below the number of recorded items remains correct. */ --uxMessagesWaiting; - 800355c: 693b ldr r3, [r7, #16] - 800355e: 3b01 subs r3, #1 - 8003560: 613b str r3, [r7, #16] + 80040d8: 693b ldr r3, [r7, #16] + 80040da: 3b01 subs r3, #1 + 80040dc: 613b str r3, [r7, #16] { mtCOVERAGE_TEST_MARKER(); } } pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1; - 8003562: 693b ldr r3, [r7, #16] - 8003564: 1c5a adds r2, r3, #1 - 8003566: 68fb ldr r3, [r7, #12] - 8003568: 639a str r2, [r3, #56] ; 0x38 + 80040de: 693b ldr r3, [r7, #16] + 80040e0: 1c5a adds r2, r3, #1 + 80040e2: 68fb ldr r3, [r7, #12] + 80040e4: 639a str r2, [r3, #56] ; 0x38 return xReturn; - 800356a: 697b ldr r3, [r7, #20] + 80040e6: 697b ldr r3, [r7, #20] } - 800356c: 4618 mov r0, r3 - 800356e: 3718 adds r7, #24 - 8003570: 46bd mov sp, r7 - 8003572: bd80 pop {r7, pc} + 80040e8: 4618 mov r0, r3 + 80040ea: 3718 adds r7, #24 + 80040ec: 46bd mov sp, r7 + 80040ee: bd80 pop {r7, pc} -08003574 : +080040f0 : /*-----------------------------------------------------------*/ static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) { - 8003574: b580 push {r7, lr} - 8003576: b082 sub sp, #8 - 8003578: af00 add r7, sp, #0 - 800357a: 6078 str r0, [r7, #4] - 800357c: 6039 str r1, [r7, #0] + 80040f0: b580 push {r7, lr} + 80040f2: b082 sub sp, #8 + 80040f4: af00 add r7, sp, #0 + 80040f6: 6078 str r0, [r7, #4] + 80040f8: 6039 str r1, [r7, #0] if( pxQueue->uxItemSize != ( UBaseType_t ) 0 ) - 800357e: 687b ldr r3, [r7, #4] - 8003580: 6c1b ldr r3, [r3, #64] ; 0x40 - 8003582: 2b00 cmp r3, #0 - 8003584: d018 beq.n 80035b8 + 80040fa: 687b ldr r3, [r7, #4] + 80040fc: 6c1b ldr r3, [r3, #64] ; 0x40 + 80040fe: 2b00 cmp r3, #0 + 8004100: d018 beq.n 8004134 { pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */ - 8003586: 687b ldr r3, [r7, #4] - 8003588: 68da ldr r2, [r3, #12] - 800358a: 687b ldr r3, [r7, #4] - 800358c: 6c1b ldr r3, [r3, #64] ; 0x40 - 800358e: 441a add r2, r3 - 8003590: 687b ldr r3, [r7, #4] - 8003592: 60da str r2, [r3, #12] + 8004102: 687b ldr r3, [r7, #4] + 8004104: 68da ldr r2, [r3, #12] + 8004106: 687b ldr r3, [r7, #4] + 8004108: 6c1b ldr r3, [r3, #64] ; 0x40 + 800410a: 441a add r2, r3 + 800410c: 687b ldr r3, [r7, #4] + 800410e: 60da str r2, [r3, #12] if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */ - 8003594: 687b ldr r3, [r7, #4] - 8003596: 68da ldr r2, [r3, #12] - 8003598: 687b ldr r3, [r7, #4] - 800359a: 689b ldr r3, [r3, #8] - 800359c: 429a cmp r2, r3 - 800359e: d303 bcc.n 80035a8 + 8004110: 687b ldr r3, [r7, #4] + 8004112: 68da ldr r2, [r3, #12] + 8004114: 687b ldr r3, [r7, #4] + 8004116: 689b ldr r3, [r3, #8] + 8004118: 429a cmp r2, r3 + 800411a: d303 bcc.n 8004124 { pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead; - 80035a0: 687b ldr r3, [r7, #4] - 80035a2: 681a ldr r2, [r3, #0] - 80035a4: 687b ldr r3, [r7, #4] - 80035a6: 60da str r2, [r3, #12] + 800411c: 687b ldr r3, [r7, #4] + 800411e: 681a ldr r2, [r3, #0] + 8004120: 687b ldr r3, [r7, #4] + 8004122: 60da str r2, [r3, #12] } else { mtCOVERAGE_TEST_MARKER(); } ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports. Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */ - 80035a8: 687b ldr r3, [r7, #4] - 80035aa: 68d9 ldr r1, [r3, #12] - 80035ac: 687b ldr r3, [r7, #4] - 80035ae: 6c1b ldr r3, [r3, #64] ; 0x40 - 80035b0: 461a mov r2, r3 - 80035b2: 6838 ldr r0, [r7, #0] - 80035b4: f002 f816 bl 80055e4 + 8004124: 687b ldr r3, [r7, #4] + 8004126: 68d9 ldr r1, [r3, #12] + 8004128: 687b ldr r3, [r7, #4] + 800412a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800412c: 461a mov r2, r3 + 800412e: 6838 ldr r0, [r7, #0] + 8004130: f002 f818 bl 8006164 } } - 80035b8: bf00 nop - 80035ba: 3708 adds r7, #8 - 80035bc: 46bd mov sp, r7 - 80035be: bd80 pop {r7, pc} + 8004134: bf00 nop + 8004136: 3708 adds r7, #8 + 8004138: 46bd mov sp, r7 + 800413a: bd80 pop {r7, pc} -080035c0 : +0800413c : /*-----------------------------------------------------------*/ static void prvUnlockQueue( Queue_t * const pxQueue ) { - 80035c0: b580 push {r7, lr} - 80035c2: b084 sub sp, #16 - 80035c4: af00 add r7, sp, #0 - 80035c6: 6078 str r0, [r7, #4] + 800413c: b580 push {r7, lr} + 800413e: b084 sub sp, #16 + 8004140: af00 add r7, sp, #0 + 8004142: 6078 str r0, [r7, #4] /* The lock counts contains the number of extra data items placed or removed from the queue while the queue was locked. When a queue is locked items can be added or removed, but the event lists cannot be updated. */ taskENTER_CRITICAL(); - 80035c8: f001 fc7c bl 8004ec4 + 8004144: f001 fc7e bl 8005a44 { int8_t cTxLock = pxQueue->cTxLock; - 80035cc: 687b ldr r3, [r7, #4] - 80035ce: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 - 80035d2: 73fb strb r3, [r7, #15] + 8004148: 687b ldr r3, [r7, #4] + 800414a: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 800414e: 73fb strb r3, [r7, #15] /* See if data was added to the queue while it was locked. */ while( cTxLock > queueLOCKED_UNMODIFIED ) - 80035d4: e011 b.n 80035fa + 8004150: e011 b.n 8004176 } #else /* configUSE_QUEUE_SETS */ { /* Tasks that are removed from the event list will get added to the pending ready list as the scheduler is still suspended. */ if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE ) - 80035d6: 687b ldr r3, [r7, #4] - 80035d8: 6a5b ldr r3, [r3, #36] ; 0x24 - 80035da: 2b00 cmp r3, #0 - 80035dc: d012 beq.n 8003604 + 8004152: 687b ldr r3, [r7, #4] + 8004154: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004156: 2b00 cmp r3, #0 + 8004158: d012 beq.n 8004180 { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE ) - 80035de: 687b ldr r3, [r7, #4] - 80035e0: 3324 adds r3, #36 ; 0x24 - 80035e2: 4618 mov r0, r3 - 80035e4: f000 fd50 bl 8004088 - 80035e8: 4603 mov r3, r0 - 80035ea: 2b00 cmp r3, #0 - 80035ec: d001 beq.n 80035f2 + 800415a: 687b ldr r3, [r7, #4] + 800415c: 3324 adds r3, #36 ; 0x24 + 800415e: 4618 mov r0, r3 + 8004160: f000 fd50 bl 8004c04 + 8004164: 4603 mov r3, r0 + 8004166: 2b00 cmp r3, #0 + 8004168: d001 beq.n 800416e { /* The task waiting has a higher priority so record that a context switch is required. */ vTaskMissedYield(); - 80035ee: f000 fe27 bl 8004240 + 800416a: f000 fe27 bl 8004dbc break; } } #endif /* configUSE_QUEUE_SETS */ --cTxLock; - 80035f2: 7bfb ldrb r3, [r7, #15] - 80035f4: 3b01 subs r3, #1 - 80035f6: b2db uxtb r3, r3 - 80035f8: 73fb strb r3, [r7, #15] + 800416e: 7bfb ldrb r3, [r7, #15] + 8004170: 3b01 subs r3, #1 + 8004172: b2db uxtb r3, r3 + 8004174: 73fb strb r3, [r7, #15] while( cTxLock > queueLOCKED_UNMODIFIED ) - 80035fa: f997 300f ldrsb.w r3, [r7, #15] - 80035fe: 2b00 cmp r3, #0 - 8003600: dce9 bgt.n 80035d6 - 8003602: e000 b.n 8003606 + 8004176: f997 300f ldrsb.w r3, [r7, #15] + 800417a: 2b00 cmp r3, #0 + 800417c: dce9 bgt.n 8004152 + 800417e: e000 b.n 8004182 break; - 8003604: bf00 nop + 8004180: bf00 nop } pxQueue->cTxLock = queueUNLOCKED; - 8003606: 687b ldr r3, [r7, #4] - 8003608: 22ff movs r2, #255 ; 0xff - 800360a: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 8004182: 687b ldr r3, [r7, #4] + 8004184: 22ff movs r2, #255 ; 0xff + 8004186: f883 2045 strb.w r2, [r3, #69] ; 0x45 } taskEXIT_CRITICAL(); - 800360e: f001 fc89 bl 8004f24 + 800418a: f001 fc8b bl 8005aa4 /* Do the same for the Rx lock. */ taskENTER_CRITICAL(); - 8003612: f001 fc57 bl 8004ec4 + 800418e: f001 fc59 bl 8005a44 { int8_t cRxLock = pxQueue->cRxLock; - 8003616: 687b ldr r3, [r7, #4] - 8003618: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 - 800361c: 73bb strb r3, [r7, #14] + 8004192: 687b ldr r3, [r7, #4] + 8004194: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 + 8004198: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) - 800361e: e011 b.n 8003644 + 800419a: e011 b.n 80041c0 { if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE ) - 8003620: 687b ldr r3, [r7, #4] - 8003622: 691b ldr r3, [r3, #16] - 8003624: 2b00 cmp r3, #0 - 8003626: d012 beq.n 800364e + 800419c: 687b ldr r3, [r7, #4] + 800419e: 691b ldr r3, [r3, #16] + 80041a0: 2b00 cmp r3, #0 + 80041a2: d012 beq.n 80041ca { if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE ) - 8003628: 687b ldr r3, [r7, #4] - 800362a: 3310 adds r3, #16 - 800362c: 4618 mov r0, r3 - 800362e: f000 fd2b bl 8004088 - 8003632: 4603 mov r3, r0 - 8003634: 2b00 cmp r3, #0 - 8003636: d001 beq.n 800363c + 80041a4: 687b ldr r3, [r7, #4] + 80041a6: 3310 adds r3, #16 + 80041a8: 4618 mov r0, r3 + 80041aa: f000 fd2b bl 8004c04 + 80041ae: 4603 mov r3, r0 + 80041b0: 2b00 cmp r3, #0 + 80041b2: d001 beq.n 80041b8 { vTaskMissedYield(); - 8003638: f000 fe02 bl 8004240 + 80041b4: f000 fe02 bl 8004dbc else { mtCOVERAGE_TEST_MARKER(); } --cRxLock; - 800363c: 7bbb ldrb r3, [r7, #14] - 800363e: 3b01 subs r3, #1 - 8003640: b2db uxtb r3, r3 - 8003642: 73bb strb r3, [r7, #14] + 80041b8: 7bbb ldrb r3, [r7, #14] + 80041ba: 3b01 subs r3, #1 + 80041bc: b2db uxtb r3, r3 + 80041be: 73bb strb r3, [r7, #14] while( cRxLock > queueLOCKED_UNMODIFIED ) - 8003644: f997 300e ldrsb.w r3, [r7, #14] - 8003648: 2b00 cmp r3, #0 - 800364a: dce9 bgt.n 8003620 - 800364c: e000 b.n 8003650 + 80041c0: f997 300e ldrsb.w r3, [r7, #14] + 80041c4: 2b00 cmp r3, #0 + 80041c6: dce9 bgt.n 800419c + 80041c8: e000 b.n 80041cc } else { break; - 800364e: bf00 nop + 80041ca: bf00 nop } } pxQueue->cRxLock = queueUNLOCKED; - 8003650: 687b ldr r3, [r7, #4] - 8003652: 22ff movs r2, #255 ; 0xff - 8003654: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 80041cc: 687b ldr r3, [r7, #4] + 80041ce: 22ff movs r2, #255 ; 0xff + 80041d0: f883 2044 strb.w r2, [r3, #68] ; 0x44 } taskEXIT_CRITICAL(); - 8003658: f001 fc64 bl 8004f24 + 80041d4: f001 fc66 bl 8005aa4 } - 800365c: bf00 nop - 800365e: 3710 adds r7, #16 - 8003660: 46bd mov sp, r7 - 8003662: bd80 pop {r7, pc} + 80041d8: bf00 nop + 80041da: 3710 adds r7, #16 + 80041dc: 46bd mov sp, r7 + 80041de: bd80 pop {r7, pc} -08003664 : +080041e0 : /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) { - 8003664: b580 push {r7, lr} - 8003666: b084 sub sp, #16 - 8003668: af00 add r7, sp, #0 - 800366a: 6078 str r0, [r7, #4] + 80041e0: b580 push {r7, lr} + 80041e2: b084 sub sp, #16 + 80041e4: af00 add r7, sp, #0 + 80041e6: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); - 800366c: f001 fc2a bl 8004ec4 + 80041e8: f001 fc2c bl 8005a44 { if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 ) - 8003670: 687b ldr r3, [r7, #4] - 8003672: 6b9b ldr r3, [r3, #56] ; 0x38 - 8003674: 2b00 cmp r3, #0 - 8003676: d102 bne.n 800367e + 80041ec: 687b ldr r3, [r7, #4] + 80041ee: 6b9b ldr r3, [r3, #56] ; 0x38 + 80041f0: 2b00 cmp r3, #0 + 80041f2: d102 bne.n 80041fa { xReturn = pdTRUE; - 8003678: 2301 movs r3, #1 - 800367a: 60fb str r3, [r7, #12] - 800367c: e001 b.n 8003682 + 80041f4: 2301 movs r3, #1 + 80041f6: 60fb str r3, [r7, #12] + 80041f8: e001 b.n 80041fe } else { xReturn = pdFALSE; - 800367e: 2300 movs r3, #0 - 8003680: 60fb str r3, [r7, #12] + 80041fa: 2300 movs r3, #0 + 80041fc: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); - 8003682: f001 fc4f bl 8004f24 + 80041fe: f001 fc51 bl 8005aa4 return xReturn; - 8003686: 68fb ldr r3, [r7, #12] + 8004202: 68fb ldr r3, [r7, #12] } - 8003688: 4618 mov r0, r3 - 800368a: 3710 adds r7, #16 - 800368c: 46bd mov sp, r7 - 800368e: bd80 pop {r7, pc} + 8004204: 4618 mov r0, r3 + 8004206: 3710 adds r7, #16 + 8004208: 46bd mov sp, r7 + 800420a: bd80 pop {r7, pc} -08003690 : +0800420c : return xReturn; } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */ /*-----------------------------------------------------------*/ static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) { - 8003690: b580 push {r7, lr} - 8003692: b084 sub sp, #16 - 8003694: af00 add r7, sp, #0 - 8003696: 6078 str r0, [r7, #4] + 800420c: b580 push {r7, lr} + 800420e: b084 sub sp, #16 + 8004210: af00 add r7, sp, #0 + 8004212: 6078 str r0, [r7, #4] BaseType_t xReturn; taskENTER_CRITICAL(); - 8003698: f001 fc14 bl 8004ec4 + 8004214: f001 fc16 bl 8005a44 { if( pxQueue->uxMessagesWaiting == pxQueue->uxLength ) - 800369c: 687b ldr r3, [r7, #4] - 800369e: 6b9a ldr r2, [r3, #56] ; 0x38 - 80036a0: 687b ldr r3, [r7, #4] - 80036a2: 6bdb ldr r3, [r3, #60] ; 0x3c - 80036a4: 429a cmp r2, r3 - 80036a6: d102 bne.n 80036ae + 8004218: 687b ldr r3, [r7, #4] + 800421a: 6b9a ldr r2, [r3, #56] ; 0x38 + 800421c: 687b ldr r3, [r7, #4] + 800421e: 6bdb ldr r3, [r3, #60] ; 0x3c + 8004220: 429a cmp r2, r3 + 8004222: d102 bne.n 800422a { xReturn = pdTRUE; - 80036a8: 2301 movs r3, #1 - 80036aa: 60fb str r3, [r7, #12] - 80036ac: e001 b.n 80036b2 + 8004224: 2301 movs r3, #1 + 8004226: 60fb str r3, [r7, #12] + 8004228: e001 b.n 800422e } else { xReturn = pdFALSE; - 80036ae: 2300 movs r3, #0 - 80036b0: 60fb str r3, [r7, #12] + 800422a: 2300 movs r3, #0 + 800422c: 60fb str r3, [r7, #12] } } taskEXIT_CRITICAL(); - 80036b2: f001 fc37 bl 8004f24 + 800422e: f001 fc39 bl 8005aa4 return xReturn; - 80036b6: 68fb ldr r3, [r7, #12] + 8004232: 68fb ldr r3, [r7, #12] } - 80036b8: 4618 mov r0, r3 - 80036ba: 3710 adds r7, #16 - 80036bc: 46bd mov sp, r7 - 80036be: bd80 pop {r7, pc} + 8004234: 4618 mov r0, r3 + 8004236: 3710 adds r7, #16 + 8004238: 46bd mov sp, r7 + 800423a: bd80 pop {r7, pc} -080036c0 : +0800423c : /*-----------------------------------------------------------*/ #if ( configQUEUE_REGISTRY_SIZE > 0 ) void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ { - 80036c0: b480 push {r7} - 80036c2: b085 sub sp, #20 - 80036c4: af00 add r7, sp, #0 - 80036c6: 6078 str r0, [r7, #4] - 80036c8: 6039 str r1, [r7, #0] + 800423c: b480 push {r7} + 800423e: b085 sub sp, #20 + 8004240: af00 add r7, sp, #0 + 8004242: 6078 str r0, [r7, #4] + 8004244: 6039 str r1, [r7, #0] UBaseType_t ux; /* See if there is an empty space in the registry. A NULL name denotes a free slot. */ for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) - 80036ca: 2300 movs r3, #0 - 80036cc: 60fb str r3, [r7, #12] - 80036ce: e014 b.n 80036fa + 8004246: 2300 movs r3, #0 + 8004248: 60fb str r3, [r7, #12] + 800424a: e014 b.n 8004276 { if( xQueueRegistry[ ux ].pcQueueName == NULL ) - 80036d0: 4a0f ldr r2, [pc, #60] ; (8003710 ) - 80036d2: 68fb ldr r3, [r7, #12] - 80036d4: f852 3033 ldr.w r3, [r2, r3, lsl #3] - 80036d8: 2b00 cmp r3, #0 - 80036da: d10b bne.n 80036f4 + 800424c: 4a0f ldr r2, [pc, #60] ; (800428c ) + 800424e: 68fb ldr r3, [r7, #12] + 8004250: f852 3033 ldr.w r3, [r2, r3, lsl #3] + 8004254: 2b00 cmp r3, #0 + 8004256: d10b bne.n 8004270 { /* Store the information on this queue. */ xQueueRegistry[ ux ].pcQueueName = pcQueueName; - 80036dc: 490c ldr r1, [pc, #48] ; (8003710 ) - 80036de: 68fb ldr r3, [r7, #12] - 80036e0: 683a ldr r2, [r7, #0] - 80036e2: f841 2033 str.w r2, [r1, r3, lsl #3] + 8004258: 490c ldr r1, [pc, #48] ; (800428c ) + 800425a: 68fb ldr r3, [r7, #12] + 800425c: 683a ldr r2, [r7, #0] + 800425e: f841 2033 str.w r2, [r1, r3, lsl #3] xQueueRegistry[ ux ].xHandle = xQueue; - 80036e6: 4a0a ldr r2, [pc, #40] ; (8003710 ) - 80036e8: 68fb ldr r3, [r7, #12] - 80036ea: 00db lsls r3, r3, #3 - 80036ec: 4413 add r3, r2 - 80036ee: 687a ldr r2, [r7, #4] - 80036f0: 605a str r2, [r3, #4] + 8004262: 4a0a ldr r2, [pc, #40] ; (800428c ) + 8004264: 68fb ldr r3, [r7, #12] + 8004266: 00db lsls r3, r3, #3 + 8004268: 4413 add r3, r2 + 800426a: 687a ldr r2, [r7, #4] + 800426c: 605a str r2, [r3, #4] traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName ); break; - 80036f2: e006 b.n 8003702 + 800426e: e006 b.n 800427e for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ ) - 80036f4: 68fb ldr r3, [r7, #12] - 80036f6: 3301 adds r3, #1 - 80036f8: 60fb str r3, [r7, #12] - 80036fa: 68fb ldr r3, [r7, #12] - 80036fc: 2b07 cmp r3, #7 - 80036fe: d9e7 bls.n 80036d0 + 8004270: 68fb ldr r3, [r7, #12] + 8004272: 3301 adds r3, #1 + 8004274: 60fb str r3, [r7, #12] + 8004276: 68fb ldr r3, [r7, #12] + 8004278: 2b07 cmp r3, #7 + 800427a: d9e7 bls.n 800424c else { mtCOVERAGE_TEST_MARKER(); } } } - 8003700: bf00 nop - 8003702: bf00 nop - 8003704: 3714 adds r7, #20 - 8003706: 46bd mov sp, r7 - 8003708: f85d 7b04 ldr.w r7, [sp], #4 - 800370c: 4770 bx lr - 800370e: bf00 nop - 8003710: 20000880 .word 0x20000880 + 800427c: bf00 nop + 800427e: bf00 nop + 8004280: 3714 adds r7, #20 + 8004282: 46bd mov sp, r7 + 8004284: f85d 7b04 ldr.w r7, [sp], #4 + 8004288: 4770 bx lr + 800428a: bf00 nop + 800428c: 200008d0 .word 0x200008d0 -08003714 : +08004290 : /*-----------------------------------------------------------*/ #if ( configUSE_TIMERS == 1 ) void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { - 8003714: b580 push {r7, lr} - 8003716: b086 sub sp, #24 - 8003718: af00 add r7, sp, #0 - 800371a: 60f8 str r0, [r7, #12] - 800371c: 60b9 str r1, [r7, #8] - 800371e: 607a str r2, [r7, #4] + 8004290: b580 push {r7, lr} + 8004292: b086 sub sp, #24 + 8004294: af00 add r7, sp, #0 + 8004296: 60f8 str r0, [r7, #12] + 8004298: 60b9 str r1, [r7, #8] + 800429a: 607a str r2, [r7, #4] Queue_t * const pxQueue = xQueue; - 8003720: 68fb ldr r3, [r7, #12] - 8003722: 617b str r3, [r7, #20] + 800429c: 68fb ldr r3, [r7, #12] + 800429e: 617b str r3, [r7, #20] will not actually cause the task to block, just place it on a blocked list. It will not block until the scheduler is unlocked - at which time a yield will be performed. If an item is added to the queue while the queue is locked, and the calling task blocks on the queue, then the calling task will be immediately unblocked when the queue is unlocked. */ prvLockQueue( pxQueue ); - 8003724: f001 fbce bl 8004ec4 - 8003728: 697b ldr r3, [r7, #20] - 800372a: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 - 800372e: b25b sxtb r3, r3 - 8003730: f1b3 3fff cmp.w r3, #4294967295 - 8003734: d103 bne.n 800373e - 8003736: 697b ldr r3, [r7, #20] - 8003738: 2200 movs r2, #0 - 800373a: f883 2044 strb.w r2, [r3, #68] ; 0x44 - 800373e: 697b ldr r3, [r7, #20] - 8003740: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 - 8003744: b25b sxtb r3, r3 - 8003746: f1b3 3fff cmp.w r3, #4294967295 - 800374a: d103 bne.n 8003754 - 800374c: 697b ldr r3, [r7, #20] - 800374e: 2200 movs r2, #0 - 8003750: f883 2045 strb.w r2, [r3, #69] ; 0x45 - 8003754: f001 fbe6 bl 8004f24 + 80042a0: f001 fbd0 bl 8005a44 + 80042a4: 697b ldr r3, [r7, #20] + 80042a6: f893 3044 ldrb.w r3, [r3, #68] ; 0x44 + 80042aa: b25b sxtb r3, r3 + 80042ac: f1b3 3fff cmp.w r3, #4294967295 + 80042b0: d103 bne.n 80042ba + 80042b2: 697b ldr r3, [r7, #20] + 80042b4: 2200 movs r2, #0 + 80042b6: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 80042ba: 697b ldr r3, [r7, #20] + 80042bc: f893 3045 ldrb.w r3, [r3, #69] ; 0x45 + 80042c0: b25b sxtb r3, r3 + 80042c2: f1b3 3fff cmp.w r3, #4294967295 + 80042c6: d103 bne.n 80042d0 + 80042c8: 697b ldr r3, [r7, #20] + 80042ca: 2200 movs r2, #0 + 80042cc: f883 2045 strb.w r2, [r3, #69] ; 0x45 + 80042d0: f001 fbe8 bl 8005aa4 if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U ) - 8003758: 697b ldr r3, [r7, #20] - 800375a: 6b9b ldr r3, [r3, #56] ; 0x38 - 800375c: 2b00 cmp r3, #0 - 800375e: d106 bne.n 800376e + 80042d4: 697b ldr r3, [r7, #20] + 80042d6: 6b9b ldr r3, [r3, #56] ; 0x38 + 80042d8: 2b00 cmp r3, #0 + 80042da: d106 bne.n 80042ea { /* There is nothing in the queue, block for the specified period. */ vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely ); - 8003760: 697b ldr r3, [r7, #20] - 8003762: 3324 adds r3, #36 ; 0x24 - 8003764: 687a ldr r2, [r7, #4] - 8003766: 68b9 ldr r1, [r7, #8] - 8003768: 4618 mov r0, r3 - 800376a: f000 fc61 bl 8004030 + 80042dc: 697b ldr r3, [r7, #20] + 80042de: 3324 adds r3, #36 ; 0x24 + 80042e0: 687a ldr r2, [r7, #4] + 80042e2: 68b9 ldr r1, [r7, #8] + 80042e4: 4618 mov r0, r3 + 80042e6: f000 fc61 bl 8004bac } else { mtCOVERAGE_TEST_MARKER(); } prvUnlockQueue( pxQueue ); - 800376e: 6978 ldr r0, [r7, #20] - 8003770: f7ff ff26 bl 80035c0 + 80042ea: 6978 ldr r0, [r7, #20] + 80042ec: f7ff ff26 bl 800413c } - 8003774: bf00 nop - 8003776: 3718 adds r7, #24 - 8003778: 46bd mov sp, r7 - 800377a: bd80 pop {r7, pc} + 80042f0: bf00 nop + 80042f2: 3718 adds r7, #24 + 80042f4: 46bd mov sp, r7 + 80042f6: bd80 pop {r7, pc} -0800377c : +080042f8 : const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) { - 800377c: b580 push {r7, lr} - 800377e: b08e sub sp, #56 ; 0x38 - 8003780: af04 add r7, sp, #16 - 8003782: 60f8 str r0, [r7, #12] - 8003784: 60b9 str r1, [r7, #8] - 8003786: 607a str r2, [r7, #4] - 8003788: 603b str r3, [r7, #0] + 80042f8: b580 push {r7, lr} + 80042fa: b08e sub sp, #56 ; 0x38 + 80042fc: af04 add r7, sp, #16 + 80042fe: 60f8 str r0, [r7, #12] + 8004300: 60b9 str r1, [r7, #8] + 8004302: 607a str r2, [r7, #4] + 8004304: 603b str r3, [r7, #0] TCB_t *pxNewTCB; TaskHandle_t xReturn; configASSERT( puxStackBuffer != NULL ); - 800378a: 6b7b ldr r3, [r7, #52] ; 0x34 - 800378c: 2b00 cmp r3, #0 - 800378e: d10a bne.n 80037a6 + 8004306: 6b7b ldr r3, [r7, #52] ; 0x34 + 8004308: 2b00 cmp r3, #0 + 800430a: d10a bne.n 8004322 __asm volatile - 8003790: f04f 0350 mov.w r3, #80 ; 0x50 - 8003794: f383 8811 msr BASEPRI, r3 - 8003798: f3bf 8f6f isb sy - 800379c: f3bf 8f4f dsb sy - 80037a0: 623b str r3, [r7, #32] + 800430c: f04f 0350 mov.w r3, #80 ; 0x50 + 8004310: f383 8811 msr BASEPRI, r3 + 8004314: f3bf 8f6f isb sy + 8004318: f3bf 8f4f dsb sy + 800431c: 623b str r3, [r7, #32] } - 80037a2: bf00 nop - 80037a4: e7fe b.n 80037a4 + 800431e: bf00 nop + 8004320: e7fe b.n 8004320 configASSERT( pxTaskBuffer != NULL ); - 80037a6: 6bbb ldr r3, [r7, #56] ; 0x38 - 80037a8: 2b00 cmp r3, #0 - 80037aa: d10a bne.n 80037c2 + 8004322: 6bbb ldr r3, [r7, #56] ; 0x38 + 8004324: 2b00 cmp r3, #0 + 8004326: d10a bne.n 800433e __asm volatile - 80037ac: f04f 0350 mov.w r3, #80 ; 0x50 - 80037b0: f383 8811 msr BASEPRI, r3 - 80037b4: f3bf 8f6f isb sy - 80037b8: f3bf 8f4f dsb sy - 80037bc: 61fb str r3, [r7, #28] + 8004328: f04f 0350 mov.w r3, #80 ; 0x50 + 800432c: f383 8811 msr BASEPRI, r3 + 8004330: f3bf 8f6f isb sy + 8004334: f3bf 8f4f dsb sy + 8004338: 61fb str r3, [r7, #28] } - 80037be: bf00 nop - 80037c0: e7fe b.n 80037c0 + 800433a: bf00 nop + 800433c: e7fe b.n 800433c #if( configASSERT_DEFINED == 1 ) { /* Sanity check that the size of the structure used to declare a variable of type StaticTask_t equals the size of the real task structure. */ volatile size_t xSize = sizeof( StaticTask_t ); - 80037c2: 23a8 movs r3, #168 ; 0xa8 - 80037c4: 613b str r3, [r7, #16] + 800433e: 23a8 movs r3, #168 ; 0xa8 + 8004340: 613b str r3, [r7, #16] configASSERT( xSize == sizeof( TCB_t ) ); - 80037c6: 693b ldr r3, [r7, #16] - 80037c8: 2ba8 cmp r3, #168 ; 0xa8 - 80037ca: d00a beq.n 80037e2 + 8004342: 693b ldr r3, [r7, #16] + 8004344: 2ba8 cmp r3, #168 ; 0xa8 + 8004346: d00a beq.n 800435e __asm volatile - 80037cc: f04f 0350 mov.w r3, #80 ; 0x50 - 80037d0: f383 8811 msr BASEPRI, r3 - 80037d4: f3bf 8f6f isb sy - 80037d8: f3bf 8f4f dsb sy - 80037dc: 61bb str r3, [r7, #24] + 8004348: f04f 0350 mov.w r3, #80 ; 0x50 + 800434c: f383 8811 msr BASEPRI, r3 + 8004350: f3bf 8f6f isb sy + 8004354: f3bf 8f4f dsb sy + 8004358: 61bb str r3, [r7, #24] } - 80037de: bf00 nop - 80037e0: e7fe b.n 80037e0 + 800435a: bf00 nop + 800435c: e7fe b.n 800435c ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */ - 80037e2: 693b ldr r3, [r7, #16] + 800435e: 693b ldr r3, [r7, #16] } #endif /* configASSERT_DEFINED */ if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) ) - 80037e4: 6bbb ldr r3, [r7, #56] ; 0x38 - 80037e6: 2b00 cmp r3, #0 - 80037e8: d01e beq.n 8003828 - 80037ea: 6b7b ldr r3, [r7, #52] ; 0x34 - 80037ec: 2b00 cmp r3, #0 - 80037ee: d01b beq.n 8003828 + 8004360: 6bbb ldr r3, [r7, #56] ; 0x38 + 8004362: 2b00 cmp r3, #0 + 8004364: d01e beq.n 80043a4 + 8004366: 6b7b ldr r3, [r7, #52] ; 0x34 + 8004368: 2b00 cmp r3, #0 + 800436a: d01b beq.n 80043a4 { /* The memory used for the task's TCB and stack are passed into this function - use them. */ pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */ - 80037f0: 6bbb ldr r3, [r7, #56] ; 0x38 - 80037f2: 627b str r3, [r7, #36] ; 0x24 + 800436c: 6bbb ldr r3, [r7, #56] ; 0x38 + 800436e: 627b str r3, [r7, #36] ; 0x24 pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer; - 80037f4: 6a7b ldr r3, [r7, #36] ; 0x24 - 80037f6: 6b7a ldr r2, [r7, #52] ; 0x34 - 80037f8: 631a str r2, [r3, #48] ; 0x30 + 8004370: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004372: 6b7a ldr r2, [r7, #52] ; 0x34 + 8004374: 631a str r2, [r3, #48] ; 0x30 #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created statically in case the task is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB; - 80037fa: 6a7b ldr r3, [r7, #36] ; 0x24 - 80037fc: 2202 movs r2, #2 - 80037fe: f883 20a5 strb.w r2, [r3, #165] ; 0xa5 + 8004376: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004378: 2202 movs r2, #2 + 800437a: f883 20a5 strb.w r2, [r3, #165] ; 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL ); - 8003802: 2300 movs r3, #0 - 8003804: 9303 str r3, [sp, #12] - 8003806: 6a7b ldr r3, [r7, #36] ; 0x24 - 8003808: 9302 str r3, [sp, #8] - 800380a: f107 0314 add.w r3, r7, #20 - 800380e: 9301 str r3, [sp, #4] - 8003810: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003812: 9300 str r3, [sp, #0] - 8003814: 683b ldr r3, [r7, #0] - 8003816: 687a ldr r2, [r7, #4] - 8003818: 68b9 ldr r1, [r7, #8] - 800381a: 68f8 ldr r0, [r7, #12] - 800381c: f000 f850 bl 80038c0 + 800437e: 2300 movs r3, #0 + 8004380: 9303 str r3, [sp, #12] + 8004382: 6a7b ldr r3, [r7, #36] ; 0x24 + 8004384: 9302 str r3, [sp, #8] + 8004386: f107 0314 add.w r3, r7, #20 + 800438a: 9301 str r3, [sp, #4] + 800438c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800438e: 9300 str r3, [sp, #0] + 8004390: 683b ldr r3, [r7, #0] + 8004392: 687a ldr r2, [r7, #4] + 8004394: 68b9 ldr r1, [r7, #8] + 8004396: 68f8 ldr r0, [r7, #12] + 8004398: f000 f850 bl 800443c prvAddNewTaskToReadyList( pxNewTCB ); - 8003820: 6a78 ldr r0, [r7, #36] ; 0x24 - 8003822: f000 f8f3 bl 8003a0c - 8003826: e001 b.n 800382c + 800439c: 6a78 ldr r0, [r7, #36] ; 0x24 + 800439e: f000 f8f3 bl 8004588 + 80043a2: e001 b.n 80043a8 } else { xReturn = NULL; - 8003828: 2300 movs r3, #0 - 800382a: 617b str r3, [r7, #20] + 80043a4: 2300 movs r3, #0 + 80043a6: 617b str r3, [r7, #20] } return xReturn; - 800382c: 697b ldr r3, [r7, #20] + 80043a8: 697b ldr r3, [r7, #20] } - 800382e: 4618 mov r0, r3 - 8003830: 3728 adds r7, #40 ; 0x28 - 8003832: 46bd mov sp, r7 - 8003834: bd80 pop {r7, pc} + 80043aa: 4618 mov r0, r3 + 80043ac: 3728 adds r7, #40 ; 0x28 + 80043ae: 46bd mov sp, r7 + 80043b0: bd80 pop {r7, pc} -08003836 : +080043b2 : const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ const configSTACK_DEPTH_TYPE usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) { - 8003836: b580 push {r7, lr} - 8003838: b08c sub sp, #48 ; 0x30 - 800383a: af04 add r7, sp, #16 - 800383c: 60f8 str r0, [r7, #12] - 800383e: 60b9 str r1, [r7, #8] - 8003840: 603b str r3, [r7, #0] - 8003842: 4613 mov r3, r2 - 8003844: 80fb strh r3, [r7, #6] + 80043b2: b580 push {r7, lr} + 80043b4: b08c sub sp, #48 ; 0x30 + 80043b6: af04 add r7, sp, #16 + 80043b8: 60f8 str r0, [r7, #12] + 80043ba: 60b9 str r1, [r7, #8] + 80043bc: 603b str r3, [r7, #0] + 80043be: 4613 mov r3, r2 + 80043c0: 80fb strh r3, [r7, #6] #else /* portSTACK_GROWTH */ { StackType_t *pxStack; /* Allocate space for the stack used by the task being created. */ pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */ - 8003846: 88fb ldrh r3, [r7, #6] - 8003848: 009b lsls r3, r3, #2 - 800384a: 4618 mov r0, r3 - 800384c: f001 fc5c bl 8005108 - 8003850: 6178 str r0, [r7, #20] + 80043c2: 88fb ldrh r3, [r7, #6] + 80043c4: 009b lsls r3, r3, #2 + 80043c6: 4618 mov r0, r3 + 80043c8: f001 fc5e bl 8005c88 + 80043cc: 6178 str r0, [r7, #20] if( pxStack != NULL ) - 8003852: 697b ldr r3, [r7, #20] - 8003854: 2b00 cmp r3, #0 - 8003856: d00e beq.n 8003876 + 80043ce: 697b ldr r3, [r7, #20] + 80043d0: 2b00 cmp r3, #0 + 80043d2: d00e beq.n 80043f2 { /* Allocate space for the TCB. */ pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */ - 8003858: 20a8 movs r0, #168 ; 0xa8 - 800385a: f001 fc55 bl 8005108 - 800385e: 61f8 str r0, [r7, #28] + 80043d4: 20a8 movs r0, #168 ; 0xa8 + 80043d6: f001 fc57 bl 8005c88 + 80043da: 61f8 str r0, [r7, #28] if( pxNewTCB != NULL ) - 8003860: 69fb ldr r3, [r7, #28] - 8003862: 2b00 cmp r3, #0 - 8003864: d003 beq.n 800386e + 80043dc: 69fb ldr r3, [r7, #28] + 80043de: 2b00 cmp r3, #0 + 80043e0: d003 beq.n 80043ea { /* Store the stack location in the TCB. */ pxNewTCB->pxStack = pxStack; - 8003866: 69fb ldr r3, [r7, #28] - 8003868: 697a ldr r2, [r7, #20] - 800386a: 631a str r2, [r3, #48] ; 0x30 - 800386c: e005 b.n 800387a + 80043e2: 69fb ldr r3, [r7, #28] + 80043e4: 697a ldr r2, [r7, #20] + 80043e6: 631a str r2, [r3, #48] ; 0x30 + 80043e8: e005 b.n 80043f6 } else { /* The stack cannot be used as the TCB was not created. Free it again. */ vPortFree( pxStack ); - 800386e: 6978 ldr r0, [r7, #20] - 8003870: f001 fd16 bl 80052a0 - 8003874: e001 b.n 800387a + 80043ea: 6978 ldr r0, [r7, #20] + 80043ec: f001 fd18 bl 8005e20 + 80043f0: e001 b.n 80043f6 } } else { pxNewTCB = NULL; - 8003876: 2300 movs r3, #0 - 8003878: 61fb str r3, [r7, #28] + 80043f2: 2300 movs r3, #0 + 80043f4: 61fb str r3, [r7, #28] } } #endif /* portSTACK_GROWTH */ if( pxNewTCB != NULL ) - 800387a: 69fb ldr r3, [r7, #28] - 800387c: 2b00 cmp r3, #0 - 800387e: d017 beq.n 80038b0 + 80043f6: 69fb ldr r3, [r7, #28] + 80043f8: 2b00 cmp r3, #0 + 80043fa: d017 beq.n 800442c { #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */ { /* Tasks can be created statically or dynamically, so note this task was created dynamically in case it is later deleted. */ pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB; - 8003880: 69fb ldr r3, [r7, #28] - 8003882: 2200 movs r2, #0 - 8003884: f883 20a5 strb.w r2, [r3, #165] ; 0xa5 + 80043fc: 69fb ldr r3, [r7, #28] + 80043fe: 2200 movs r2, #0 + 8004400: f883 20a5 strb.w r2, [r3, #165] ; 0xa5 } #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */ prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL ); - 8003888: 88fa ldrh r2, [r7, #6] - 800388a: 2300 movs r3, #0 - 800388c: 9303 str r3, [sp, #12] - 800388e: 69fb ldr r3, [r7, #28] - 8003890: 9302 str r3, [sp, #8] - 8003892: 6afb ldr r3, [r7, #44] ; 0x2c - 8003894: 9301 str r3, [sp, #4] - 8003896: 6abb ldr r3, [r7, #40] ; 0x28 - 8003898: 9300 str r3, [sp, #0] - 800389a: 683b ldr r3, [r7, #0] - 800389c: 68b9 ldr r1, [r7, #8] - 800389e: 68f8 ldr r0, [r7, #12] - 80038a0: f000 f80e bl 80038c0 + 8004404: 88fa ldrh r2, [r7, #6] + 8004406: 2300 movs r3, #0 + 8004408: 9303 str r3, [sp, #12] + 800440a: 69fb ldr r3, [r7, #28] + 800440c: 9302 str r3, [sp, #8] + 800440e: 6afb ldr r3, [r7, #44] ; 0x2c + 8004410: 9301 str r3, [sp, #4] + 8004412: 6abb ldr r3, [r7, #40] ; 0x28 + 8004414: 9300 str r3, [sp, #0] + 8004416: 683b ldr r3, [r7, #0] + 8004418: 68b9 ldr r1, [r7, #8] + 800441a: 68f8 ldr r0, [r7, #12] + 800441c: f000 f80e bl 800443c prvAddNewTaskToReadyList( pxNewTCB ); - 80038a4: 69f8 ldr r0, [r7, #28] - 80038a6: f000 f8b1 bl 8003a0c + 8004420: 69f8 ldr r0, [r7, #28] + 8004422: f000 f8b1 bl 8004588 xReturn = pdPASS; - 80038aa: 2301 movs r3, #1 - 80038ac: 61bb str r3, [r7, #24] - 80038ae: e002 b.n 80038b6 + 8004426: 2301 movs r3, #1 + 8004428: 61bb str r3, [r7, #24] + 800442a: e002 b.n 8004432 } else { xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY; - 80038b0: f04f 33ff mov.w r3, #4294967295 - 80038b4: 61bb str r3, [r7, #24] + 800442c: f04f 33ff mov.w r3, #4294967295 + 8004430: 61bb str r3, [r7, #24] } return xReturn; - 80038b6: 69bb ldr r3, [r7, #24] + 8004432: 69bb ldr r3, [r7, #24] } - 80038b8: 4618 mov r0, r3 - 80038ba: 3720 adds r7, #32 - 80038bc: 46bd mov sp, r7 - 80038be: bd80 pop {r7, pc} + 8004434: 4618 mov r0, r3 + 8004436: 3720 adds r7, #32 + 8004438: 46bd mov sp, r7 + 800443a: bd80 pop {r7, pc} -080038c0 : +0800443c : void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask, TCB_t *pxNewTCB, const MemoryRegion_t * const xRegions ) { - 80038c0: b580 push {r7, lr} - 80038c2: b088 sub sp, #32 - 80038c4: af00 add r7, sp, #0 - 80038c6: 60f8 str r0, [r7, #12] - 80038c8: 60b9 str r1, [r7, #8] - 80038ca: 607a str r2, [r7, #4] - 80038cc: 603b str r3, [r7, #0] + 800443c: b580 push {r7, lr} + 800443e: b088 sub sp, #32 + 8004440: af00 add r7, sp, #0 + 8004442: 60f8 str r0, [r7, #12] + 8004444: 60b9 str r1, [r7, #8] + 8004446: 607a str r2, [r7, #4] + 8004448: 603b str r3, [r7, #0] /* Avoid dependency on memset() if it is not required. */ #if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 ) { /* Fill the stack with a known value to assist debugging. */ ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) ); - 80038ce: 6b3b ldr r3, [r7, #48] ; 0x30 - 80038d0: 6b18 ldr r0, [r3, #48] ; 0x30 - 80038d2: 687b ldr r3, [r7, #4] - 80038d4: 009b lsls r3, r3, #2 - 80038d6: 461a mov r2, r3 - 80038d8: 21a5 movs r1, #165 ; 0xa5 - 80038da: f001 fdff bl 80054dc + 800444a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800444c: 6b18 ldr r0, [r3, #48] ; 0x30 + 800444e: 687b ldr r3, [r7, #4] + 8004450: 009b lsls r3, r3, #2 + 8004452: 461a mov r2, r3 + 8004454: 21a5 movs r1, #165 ; 0xa5 + 8004456: f001 fe01 bl 800605c grows from high memory to low (as per the 80x86) or vice versa. portSTACK_GROWTH is used to make the result positive or negative as required by the port. */ #if( portSTACK_GROWTH < 0 ) { pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] ); - 80038de: 6b3b ldr r3, [r7, #48] ; 0x30 - 80038e0: 6b1a ldr r2, [r3, #48] ; 0x30 - 80038e2: 687b ldr r3, [r7, #4] - 80038e4: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 - 80038e8: 3b01 subs r3, #1 - 80038ea: 009b lsls r3, r3, #2 - 80038ec: 4413 add r3, r2 - 80038ee: 61bb str r3, [r7, #24] + 800445a: 6b3b ldr r3, [r7, #48] ; 0x30 + 800445c: 6b1a ldr r2, [r3, #48] ; 0x30 + 800445e: 687b ldr r3, [r7, #4] + 8004460: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 + 8004464: 3b01 subs r3, #1 + 8004466: 009b lsls r3, r3, #2 + 8004468: 4413 add r3, r2 + 800446a: 61bb str r3, [r7, #24] pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception. Avoiding casts between pointers and integers is not practical. Size differences accounted for using portPOINTER_SIZE_TYPE type. Checked by assert(). */ - 80038f0: 69bb ldr r3, [r7, #24] - 80038f2: f023 0307 bic.w r3, r3, #7 - 80038f6: 61bb str r3, [r7, #24] + 800446c: 69bb ldr r3, [r7, #24] + 800446e: f023 0307 bic.w r3, r3, #7 + 8004472: 61bb str r3, [r7, #24] /* Check the alignment of the calculated top of stack is correct. */ configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) ); - 80038f8: 69bb ldr r3, [r7, #24] - 80038fa: f003 0307 and.w r3, r3, #7 - 80038fe: 2b00 cmp r3, #0 - 8003900: d00a beq.n 8003918 + 8004474: 69bb ldr r3, [r7, #24] + 8004476: f003 0307 and.w r3, r3, #7 + 800447a: 2b00 cmp r3, #0 + 800447c: d00a beq.n 8004494 __asm volatile - 8003902: f04f 0350 mov.w r3, #80 ; 0x50 - 8003906: f383 8811 msr BASEPRI, r3 - 800390a: f3bf 8f6f isb sy - 800390e: f3bf 8f4f dsb sy - 8003912: 617b str r3, [r7, #20] + 800447e: f04f 0350 mov.w r3, #80 ; 0x50 + 8004482: f383 8811 msr BASEPRI, r3 + 8004486: f3bf 8f6f isb sy + 800448a: f3bf 8f4f dsb sy + 800448e: 617b str r3, [r7, #20] } - 8003914: bf00 nop - 8003916: e7fe b.n 8003916 + 8004490: bf00 nop + 8004492: e7fe b.n 8004492 pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 ); } #endif /* portSTACK_GROWTH */ /* Store the task name in the TCB. */ if( pcName != NULL ) - 8003918: 68bb ldr r3, [r7, #8] - 800391a: 2b00 cmp r3, #0 - 800391c: d01f beq.n 800395e + 8004494: 68bb ldr r3, [r7, #8] + 8004496: 2b00 cmp r3, #0 + 8004498: d01f beq.n 80044da { for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) - 800391e: 2300 movs r3, #0 - 8003920: 61fb str r3, [r7, #28] - 8003922: e012 b.n 800394a + 800449a: 2300 movs r3, #0 + 800449c: 61fb str r3, [r7, #28] + 800449e: e012 b.n 80044c6 { pxNewTCB->pcTaskName[ x ] = pcName[ x ]; - 8003924: 68ba ldr r2, [r7, #8] - 8003926: 69fb ldr r3, [r7, #28] - 8003928: 4413 add r3, r2 - 800392a: 7819 ldrb r1, [r3, #0] - 800392c: 6b3a ldr r2, [r7, #48] ; 0x30 - 800392e: 69fb ldr r3, [r7, #28] - 8003930: 4413 add r3, r2 - 8003932: 3334 adds r3, #52 ; 0x34 - 8003934: 460a mov r2, r1 - 8003936: 701a strb r2, [r3, #0] + 80044a0: 68ba ldr r2, [r7, #8] + 80044a2: 69fb ldr r3, [r7, #28] + 80044a4: 4413 add r3, r2 + 80044a6: 7819 ldrb r1, [r3, #0] + 80044a8: 6b3a ldr r2, [r7, #48] ; 0x30 + 80044aa: 69fb ldr r3, [r7, #28] + 80044ac: 4413 add r3, r2 + 80044ae: 3334 adds r3, #52 ; 0x34 + 80044b0: 460a mov r2, r1 + 80044b2: 701a strb r2, [r3, #0] /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than configMAX_TASK_NAME_LEN characters just in case the memory after the string is not accessible (extremely unlikely). */ if( pcName[ x ] == ( char ) 0x00 ) - 8003938: 68ba ldr r2, [r7, #8] - 800393a: 69fb ldr r3, [r7, #28] - 800393c: 4413 add r3, r2 - 800393e: 781b ldrb r3, [r3, #0] - 8003940: 2b00 cmp r3, #0 - 8003942: d006 beq.n 8003952 + 80044b4: 68ba ldr r2, [r7, #8] + 80044b6: 69fb ldr r3, [r7, #28] + 80044b8: 4413 add r3, r2 + 80044ba: 781b ldrb r3, [r3, #0] + 80044bc: 2b00 cmp r3, #0 + 80044be: d006 beq.n 80044ce for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ ) - 8003944: 69fb ldr r3, [r7, #28] - 8003946: 3301 adds r3, #1 - 8003948: 61fb str r3, [r7, #28] - 800394a: 69fb ldr r3, [r7, #28] - 800394c: 2b0f cmp r3, #15 - 800394e: d9e9 bls.n 8003924 - 8003950: e000 b.n 8003954 + 80044c0: 69fb ldr r3, [r7, #28] + 80044c2: 3301 adds r3, #1 + 80044c4: 61fb str r3, [r7, #28] + 80044c6: 69fb ldr r3, [r7, #28] + 80044c8: 2b0f cmp r3, #15 + 80044ca: d9e9 bls.n 80044a0 + 80044cc: e000 b.n 80044d0 { break; - 8003952: bf00 nop + 80044ce: bf00 nop } } /* Ensure the name string is terminated in the case that the string length was greater or equal to configMAX_TASK_NAME_LEN. */ pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0'; - 8003954: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003956: 2200 movs r2, #0 - 8003958: f883 2043 strb.w r2, [r3, #67] ; 0x43 - 800395c: e003 b.n 8003966 + 80044d0: 6b3b ldr r3, [r7, #48] ; 0x30 + 80044d2: 2200 movs r2, #0 + 80044d4: f883 2043 strb.w r2, [r3, #67] ; 0x43 + 80044d8: e003 b.n 80044e2 } else { /* The task has not been given a name, so just ensure there is a NULL terminator when it is read out. */ pxNewTCB->pcTaskName[ 0 ] = 0x00; - 800395e: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003960: 2200 movs r2, #0 - 8003962: f883 2034 strb.w r2, [r3, #52] ; 0x34 + 80044da: 6b3b ldr r3, [r7, #48] ; 0x30 + 80044dc: 2200 movs r2, #0 + 80044de: f883 2034 strb.w r2, [r3, #52] ; 0x34 } /* This is used as an array index so must ensure it's not too large. First remove the privilege bit if one is present. */ if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES ) - 8003966: 6abb ldr r3, [r7, #40] ; 0x28 - 8003968: 2b37 cmp r3, #55 ; 0x37 - 800396a: d901 bls.n 8003970 + 80044e2: 6abb ldr r3, [r7, #40] ; 0x28 + 80044e4: 2b37 cmp r3, #55 ; 0x37 + 80044e6: d901 bls.n 80044ec { uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U; - 800396c: 2337 movs r3, #55 ; 0x37 - 800396e: 62bb str r3, [r7, #40] ; 0x28 + 80044e8: 2337 movs r3, #55 ; 0x37 + 80044ea: 62bb str r3, [r7, #40] ; 0x28 else { mtCOVERAGE_TEST_MARKER(); } pxNewTCB->uxPriority = uxPriority; - 8003970: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003972: 6aba ldr r2, [r7, #40] ; 0x28 - 8003974: 62da str r2, [r3, #44] ; 0x2c + 80044ec: 6b3b ldr r3, [r7, #48] ; 0x30 + 80044ee: 6aba ldr r2, [r7, #40] ; 0x28 + 80044f0: 62da str r2, [r3, #44] ; 0x2c #if ( configUSE_MUTEXES == 1 ) { pxNewTCB->uxBasePriority = uxPriority; - 8003976: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003978: 6aba ldr r2, [r7, #40] ; 0x28 - 800397a: 64da str r2, [r3, #76] ; 0x4c + 80044f2: 6b3b ldr r3, [r7, #48] ; 0x30 + 80044f4: 6aba ldr r2, [r7, #40] ; 0x28 + 80044f6: 64da str r2, [r3, #76] ; 0x4c pxNewTCB->uxMutexesHeld = 0; - 800397c: 6b3b ldr r3, [r7, #48] ; 0x30 - 800397e: 2200 movs r2, #0 - 8003980: 651a str r2, [r3, #80] ; 0x50 + 80044f8: 6b3b ldr r3, [r7, #48] ; 0x30 + 80044fa: 2200 movs r2, #0 + 80044fc: 651a str r2, [r3, #80] ; 0x50 } #endif /* configUSE_MUTEXES */ vListInitialiseItem( &( pxNewTCB->xStateListItem ) ); - 8003982: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003984: 3304 adds r3, #4 - 8003986: 4618 mov r0, r3 - 8003988: f7ff f978 bl 8002c7c + 80044fe: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004500: 3304 adds r3, #4 + 8004502: 4618 mov r0, r3 + 8004504: f7ff f978 bl 80037f8 vListInitialiseItem( &( pxNewTCB->xEventListItem ) ); - 800398c: 6b3b ldr r3, [r7, #48] ; 0x30 - 800398e: 3318 adds r3, #24 - 8003990: 4618 mov r0, r3 - 8003992: f7ff f973 bl 8002c7c + 8004508: 6b3b ldr r3, [r7, #48] ; 0x30 + 800450a: 3318 adds r3, #24 + 800450c: 4618 mov r0, r3 + 800450e: f7ff f973 bl 80037f8 /* Set the pxNewTCB as a link back from the ListItem_t. This is so we can get back to the containing TCB from a generic item in a list. */ listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB ); - 8003996: 6b3b ldr r3, [r7, #48] ; 0x30 - 8003998: 6b3a ldr r2, [r7, #48] ; 0x30 - 800399a: 611a str r2, [r3, #16] + 8004512: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004514: 6b3a ldr r2, [r7, #48] ; 0x30 + 8004516: 611a str r2, [r3, #16] /* Event lists are always in priority order. */ listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - 800399c: 6abb ldr r3, [r7, #40] ; 0x28 - 800399e: f1c3 0238 rsb r2, r3, #56 ; 0x38 - 80039a2: 6b3b ldr r3, [r7, #48] ; 0x30 - 80039a4: 619a str r2, [r3, #24] + 8004518: 6abb ldr r3, [r7, #40] ; 0x28 + 800451a: f1c3 0238 rsb r2, r3, #56 ; 0x38 + 800451e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004520: 619a str r2, [r3, #24] listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB ); - 80039a6: 6b3b ldr r3, [r7, #48] ; 0x30 - 80039a8: 6b3a ldr r2, [r7, #48] ; 0x30 - 80039aa: 625a str r2, [r3, #36] ; 0x24 + 8004522: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004524: 6b3a ldr r2, [r7, #48] ; 0x30 + 8004526: 625a str r2, [r3, #36] ; 0x24 } #endif #if ( configUSE_TASK_NOTIFICATIONS == 1 ) { pxNewTCB->ulNotifiedValue = 0; - 80039ac: 6b3b ldr r3, [r7, #48] ; 0x30 - 80039ae: 2200 movs r2, #0 - 80039b0: f8c3 20a0 str.w r2, [r3, #160] ; 0xa0 + 8004528: 6b3b ldr r3, [r7, #48] ; 0x30 + 800452a: 2200 movs r2, #0 + 800452c: f8c3 20a0 str.w r2, [r3, #160] ; 0xa0 pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION; - 80039b4: 6b3b ldr r3, [r7, #48] ; 0x30 - 80039b6: 2200 movs r2, #0 - 80039b8: f883 20a4 strb.w r2, [r3, #164] ; 0xa4 + 8004530: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004532: 2200 movs r2, #0 + 8004534: f883 20a4 strb.w r2, [r3, #164] ; 0xa4 #if ( configUSE_NEWLIB_REENTRANT == 1 ) { /* Initialise this task's Newlib reent structure. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) ); - 80039bc: 6b3b ldr r3, [r7, #48] ; 0x30 - 80039be: 3354 adds r3, #84 ; 0x54 - 80039c0: 224c movs r2, #76 ; 0x4c - 80039c2: 2100 movs r1, #0 - 80039c4: 4618 mov r0, r3 - 80039c6: f001 fd89 bl 80054dc - 80039ca: 6b3b ldr r3, [r7, #48] ; 0x30 - 80039cc: 4a0c ldr r2, [pc, #48] ; (8003a00 ) - 80039ce: 659a str r2, [r3, #88] ; 0x58 - 80039d0: 6b3b ldr r3, [r7, #48] ; 0x30 - 80039d2: 4a0c ldr r2, [pc, #48] ; (8003a04 ) - 80039d4: 65da str r2, [r3, #92] ; 0x5c - 80039d6: 6b3b ldr r3, [r7, #48] ; 0x30 - 80039d8: 4a0b ldr r2, [pc, #44] ; (8003a08 ) - 80039da: 661a str r2, [r3, #96] ; 0x60 + 8004538: 6b3b ldr r3, [r7, #48] ; 0x30 + 800453a: 3354 adds r3, #84 ; 0x54 + 800453c: 224c movs r2, #76 ; 0x4c + 800453e: 2100 movs r1, #0 + 8004540: 4618 mov r0, r3 + 8004542: f001 fd8b bl 800605c + 8004546: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004548: 4a0c ldr r2, [pc, #48] ; (800457c ) + 800454a: 659a str r2, [r3, #88] ; 0x58 + 800454c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800454e: 4a0c ldr r2, [pc, #48] ; (8004580 ) + 8004550: 65da str r2, [r3, #92] ; 0x5c + 8004552: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004554: 4a0b ldr r2, [pc, #44] ; (8004584 ) + 8004556: 661a str r2, [r3, #96] ; 0x60 } #endif /* portSTACK_GROWTH */ } #else /* portHAS_STACK_OVERFLOW_CHECKING */ { pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters ); - 80039dc: 683a ldr r2, [r7, #0] - 80039de: 68f9 ldr r1, [r7, #12] - 80039e0: 69b8 ldr r0, [r7, #24] - 80039e2: f001 f941 bl 8004c68 - 80039e6: 4602 mov r2, r0 - 80039e8: 6b3b ldr r3, [r7, #48] ; 0x30 - 80039ea: 601a str r2, [r3, #0] + 8004558: 683a ldr r2, [r7, #0] + 800455a: 68f9 ldr r1, [r7, #12] + 800455c: 69b8 ldr r0, [r7, #24] + 800455e: f001 f941 bl 80057e4 + 8004562: 4602 mov r2, r0 + 8004564: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004566: 601a str r2, [r3, #0] } #endif /* portHAS_STACK_OVERFLOW_CHECKING */ } #endif /* portUSING_MPU_WRAPPERS */ if( pxCreatedTask != NULL ) - 80039ec: 6afb ldr r3, [r7, #44] ; 0x2c - 80039ee: 2b00 cmp r3, #0 - 80039f0: d002 beq.n 80039f8 + 8004568: 6afb ldr r3, [r7, #44] ; 0x2c + 800456a: 2b00 cmp r3, #0 + 800456c: d002 beq.n 8004574 { /* Pass the handle out in an anonymous way. The handle can be used to change the created task's priority, delete the created task, etc.*/ *pxCreatedTask = ( TaskHandle_t ) pxNewTCB; - 80039f2: 6afb ldr r3, [r7, #44] ; 0x2c - 80039f4: 6b3a ldr r2, [r7, #48] ; 0x30 - 80039f6: 601a str r2, [r3, #0] + 800456e: 6afb ldr r3, [r7, #44] ; 0x2c + 8004570: 6b3a ldr r2, [r7, #48] ; 0x30 + 8004572: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } - 80039f8: bf00 nop - 80039fa: 3720 adds r7, #32 - 80039fc: 46bd mov sp, r7 - 80039fe: bd80 pop {r7, pc} - 8003a00: 20004b14 .word 0x20004b14 - 8003a04: 20004b7c .word 0x20004b7c - 8003a08: 20004be4 .word 0x20004be4 + 8004574: bf00 nop + 8004576: 3720 adds r7, #32 + 8004578: 46bd mov sp, r7 + 800457a: bd80 pop {r7, pc} + 800457c: 20004b64 .word 0x20004b64 + 8004580: 20004bcc .word 0x20004bcc + 8004584: 20004c34 .word 0x20004c34 -08003a0c : +08004588 : /*-----------------------------------------------------------*/ static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) { - 8003a0c: b580 push {r7, lr} - 8003a0e: b082 sub sp, #8 - 8003a10: af00 add r7, sp, #0 - 8003a12: 6078 str r0, [r7, #4] + 8004588: b580 push {r7, lr} + 800458a: b082 sub sp, #8 + 800458c: af00 add r7, sp, #0 + 800458e: 6078 str r0, [r7, #4] /* Ensure interrupts don't access the task lists while the lists are being updated. */ taskENTER_CRITICAL(); - 8003a14: f001 fa56 bl 8004ec4 + 8004590: f001 fa58 bl 8005a44 { uxCurrentNumberOfTasks++; - 8003a18: 4b2d ldr r3, [pc, #180] ; (8003ad0 ) - 8003a1a: 681b ldr r3, [r3, #0] - 8003a1c: 3301 adds r3, #1 - 8003a1e: 4a2c ldr r2, [pc, #176] ; (8003ad0 ) - 8003a20: 6013 str r3, [r2, #0] + 8004594: 4b2d ldr r3, [pc, #180] ; (800464c ) + 8004596: 681b ldr r3, [r3, #0] + 8004598: 3301 adds r3, #1 + 800459a: 4a2c ldr r2, [pc, #176] ; (800464c ) + 800459c: 6013 str r3, [r2, #0] if( pxCurrentTCB == NULL ) - 8003a22: 4b2c ldr r3, [pc, #176] ; (8003ad4 ) - 8003a24: 681b ldr r3, [r3, #0] - 8003a26: 2b00 cmp r3, #0 - 8003a28: d109 bne.n 8003a3e + 800459e: 4b2c ldr r3, [pc, #176] ; (8004650 ) + 80045a0: 681b ldr r3, [r3, #0] + 80045a2: 2b00 cmp r3, #0 + 80045a4: d109 bne.n 80045ba { /* There are no other tasks, or all the other tasks are in the suspended state - make this the current task. */ pxCurrentTCB = pxNewTCB; - 8003a2a: 4a2a ldr r2, [pc, #168] ; (8003ad4 ) - 8003a2c: 687b ldr r3, [r7, #4] - 8003a2e: 6013 str r3, [r2, #0] + 80045a6: 4a2a ldr r2, [pc, #168] ; (8004650 ) + 80045a8: 687b ldr r3, [r7, #4] + 80045aa: 6013 str r3, [r2, #0] if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 ) - 8003a30: 4b27 ldr r3, [pc, #156] ; (8003ad0 ) - 8003a32: 681b ldr r3, [r3, #0] - 8003a34: 2b01 cmp r3, #1 - 8003a36: d110 bne.n 8003a5a + 80045ac: 4b27 ldr r3, [pc, #156] ; (800464c ) + 80045ae: 681b ldr r3, [r3, #0] + 80045b0: 2b01 cmp r3, #1 + 80045b2: d110 bne.n 80045d6 { /* This is the first task to be created so do the preliminary initialisation required. We will not recover if this call fails, but we will report the failure. */ prvInitialiseTaskLists(); - 8003a38: f000 fc26 bl 8004288 - 8003a3c: e00d b.n 8003a5a + 80045b4: f000 fc26 bl 8004e04 + 80045b8: e00d b.n 80045d6 else { /* If the scheduler is not already running, make this task the current task if it is the highest priority task to be created so far. */ if( xSchedulerRunning == pdFALSE ) - 8003a3e: 4b26 ldr r3, [pc, #152] ; (8003ad8 ) - 8003a40: 681b ldr r3, [r3, #0] - 8003a42: 2b00 cmp r3, #0 - 8003a44: d109 bne.n 8003a5a + 80045ba: 4b26 ldr r3, [pc, #152] ; (8004654 ) + 80045bc: 681b ldr r3, [r3, #0] + 80045be: 2b00 cmp r3, #0 + 80045c0: d109 bne.n 80045d6 { if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority ) - 8003a46: 4b23 ldr r3, [pc, #140] ; (8003ad4 ) - 8003a48: 681b ldr r3, [r3, #0] - 8003a4a: 6ada ldr r2, [r3, #44] ; 0x2c - 8003a4c: 687b ldr r3, [r7, #4] - 8003a4e: 6adb ldr r3, [r3, #44] ; 0x2c - 8003a50: 429a cmp r2, r3 - 8003a52: d802 bhi.n 8003a5a + 80045c2: 4b23 ldr r3, [pc, #140] ; (8004650 ) + 80045c4: 681b ldr r3, [r3, #0] + 80045c6: 6ada ldr r2, [r3, #44] ; 0x2c + 80045c8: 687b ldr r3, [r7, #4] + 80045ca: 6adb ldr r3, [r3, #44] ; 0x2c + 80045cc: 429a cmp r2, r3 + 80045ce: d802 bhi.n 80045d6 { pxCurrentTCB = pxNewTCB; - 8003a54: 4a1f ldr r2, [pc, #124] ; (8003ad4 ) - 8003a56: 687b ldr r3, [r7, #4] - 8003a58: 6013 str r3, [r2, #0] + 80045d0: 4a1f ldr r2, [pc, #124] ; (8004650 ) + 80045d2: 687b ldr r3, [r7, #4] + 80045d4: 6013 str r3, [r2, #0] { mtCOVERAGE_TEST_MARKER(); } } uxTaskNumber++; - 8003a5a: 4b20 ldr r3, [pc, #128] ; (8003adc ) - 8003a5c: 681b ldr r3, [r3, #0] - 8003a5e: 3301 adds r3, #1 - 8003a60: 4a1e ldr r2, [pc, #120] ; (8003adc ) - 8003a62: 6013 str r3, [r2, #0] + 80045d6: 4b20 ldr r3, [pc, #128] ; (8004658 ) + 80045d8: 681b ldr r3, [r3, #0] + 80045da: 3301 adds r3, #1 + 80045dc: 4a1e ldr r2, [pc, #120] ; (8004658 ) + 80045de: 6013 str r3, [r2, #0] #if ( configUSE_TRACE_FACILITY == 1 ) { /* Add a counter into the TCB for tracing only. */ pxNewTCB->uxTCBNumber = uxTaskNumber; - 8003a64: 4b1d ldr r3, [pc, #116] ; (8003adc ) - 8003a66: 681a ldr r2, [r3, #0] - 8003a68: 687b ldr r3, [r7, #4] - 8003a6a: 645a str r2, [r3, #68] ; 0x44 + 80045e0: 4b1d ldr r3, [pc, #116] ; (8004658 ) + 80045e2: 681a ldr r2, [r3, #0] + 80045e4: 687b ldr r3, [r7, #4] + 80045e6: 645a str r2, [r3, #68] ; 0x44 } #endif /* configUSE_TRACE_FACILITY */ traceTASK_CREATE( pxNewTCB ); prvAddTaskToReadyList( pxNewTCB ); - 8003a6c: 687b ldr r3, [r7, #4] - 8003a6e: 6ada ldr r2, [r3, #44] ; 0x2c - 8003a70: 4b1b ldr r3, [pc, #108] ; (8003ae0 ) - 8003a72: 681b ldr r3, [r3, #0] - 8003a74: 429a cmp r2, r3 - 8003a76: d903 bls.n 8003a80 - 8003a78: 687b ldr r3, [r7, #4] - 8003a7a: 6adb ldr r3, [r3, #44] ; 0x2c - 8003a7c: 4a18 ldr r2, [pc, #96] ; (8003ae0 ) - 8003a7e: 6013 str r3, [r2, #0] - 8003a80: 687b ldr r3, [r7, #4] - 8003a82: 6ada ldr r2, [r3, #44] ; 0x2c - 8003a84: 4613 mov r3, r2 - 8003a86: 009b lsls r3, r3, #2 - 8003a88: 4413 add r3, r2 - 8003a8a: 009b lsls r3, r3, #2 - 8003a8c: 4a15 ldr r2, [pc, #84] ; (8003ae4 ) - 8003a8e: 441a add r2, r3 - 8003a90: 687b ldr r3, [r7, #4] - 8003a92: 3304 adds r3, #4 - 8003a94: 4619 mov r1, r3 - 8003a96: 4610 mov r0, r2 - 8003a98: f7ff f8fd bl 8002c96 + 80045e8: 687b ldr r3, [r7, #4] + 80045ea: 6ada ldr r2, [r3, #44] ; 0x2c + 80045ec: 4b1b ldr r3, [pc, #108] ; (800465c ) + 80045ee: 681b ldr r3, [r3, #0] + 80045f0: 429a cmp r2, r3 + 80045f2: d903 bls.n 80045fc + 80045f4: 687b ldr r3, [r7, #4] + 80045f6: 6adb ldr r3, [r3, #44] ; 0x2c + 80045f8: 4a18 ldr r2, [pc, #96] ; (800465c ) + 80045fa: 6013 str r3, [r2, #0] + 80045fc: 687b ldr r3, [r7, #4] + 80045fe: 6ada ldr r2, [r3, #44] ; 0x2c + 8004600: 4613 mov r3, r2 + 8004602: 009b lsls r3, r3, #2 + 8004604: 4413 add r3, r2 + 8004606: 009b lsls r3, r3, #2 + 8004608: 4a15 ldr r2, [pc, #84] ; (8004660 ) + 800460a: 441a add r2, r3 + 800460c: 687b ldr r3, [r7, #4] + 800460e: 3304 adds r3, #4 + 8004610: 4619 mov r1, r3 + 8004612: 4610 mov r0, r2 + 8004614: f7ff f8fd bl 8003812 portSETUP_TCB( pxNewTCB ); } taskEXIT_CRITICAL(); - 8003a9c: f001 fa42 bl 8004f24 + 8004618: f001 fa44 bl 8005aa4 if( xSchedulerRunning != pdFALSE ) - 8003aa0: 4b0d ldr r3, [pc, #52] ; (8003ad8 ) - 8003aa2: 681b ldr r3, [r3, #0] - 8003aa4: 2b00 cmp r3, #0 - 8003aa6: d00e beq.n 8003ac6 + 800461c: 4b0d ldr r3, [pc, #52] ; (8004654 ) + 800461e: 681b ldr r3, [r3, #0] + 8004620: 2b00 cmp r3, #0 + 8004622: d00e beq.n 8004642 { /* If the created task is of a higher priority than the current task then it should run now. */ if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority ) - 8003aa8: 4b0a ldr r3, [pc, #40] ; (8003ad4 ) - 8003aaa: 681b ldr r3, [r3, #0] - 8003aac: 6ada ldr r2, [r3, #44] ; 0x2c - 8003aae: 687b ldr r3, [r7, #4] - 8003ab0: 6adb ldr r3, [r3, #44] ; 0x2c - 8003ab2: 429a cmp r2, r3 - 8003ab4: d207 bcs.n 8003ac6 + 8004624: 4b0a ldr r3, [pc, #40] ; (8004650 ) + 8004626: 681b ldr r3, [r3, #0] + 8004628: 6ada ldr r2, [r3, #44] ; 0x2c + 800462a: 687b ldr r3, [r7, #4] + 800462c: 6adb ldr r3, [r3, #44] ; 0x2c + 800462e: 429a cmp r2, r3 + 8004630: d207 bcs.n 8004642 { taskYIELD_IF_USING_PREEMPTION(); - 8003ab6: 4b0c ldr r3, [pc, #48] ; (8003ae8 ) - 8003ab8: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 8003abc: 601a str r2, [r3, #0] - 8003abe: f3bf 8f4f dsb sy - 8003ac2: f3bf 8f6f isb sy + 8004632: 4b0c ldr r3, [pc, #48] ; (8004664 ) + 8004634: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8004638: 601a str r2, [r3, #0] + 800463a: f3bf 8f4f dsb sy + 800463e: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } - 8003ac6: bf00 nop - 8003ac8: 3708 adds r7, #8 - 8003aca: 46bd mov sp, r7 - 8003acc: bd80 pop {r7, pc} - 8003ace: bf00 nop - 8003ad0: 20000d94 .word 0x20000d94 - 8003ad4: 200008c0 .word 0x200008c0 - 8003ad8: 20000da0 .word 0x20000da0 - 8003adc: 20000db0 .word 0x20000db0 - 8003ae0: 20000d9c .word 0x20000d9c - 8003ae4: 200008c4 .word 0x200008c4 - 8003ae8: e000ed04 .word 0xe000ed04 + 8004642: bf00 nop + 8004644: 3708 adds r7, #8 + 8004646: 46bd mov sp, r7 + 8004648: bd80 pop {r7, pc} + 800464a: bf00 nop + 800464c: 20000de4 .word 0x20000de4 + 8004650: 20000910 .word 0x20000910 + 8004654: 20000df0 .word 0x20000df0 + 8004658: 20000e00 .word 0x20000e00 + 800465c: 20000dec .word 0x20000dec + 8004660: 20000914 .word 0x20000914 + 8004664: e000ed04 .word 0xe000ed04 -08003aec : +08004668 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelay == 1 ) void vTaskDelay( const TickType_t xTicksToDelay ) { - 8003aec: b580 push {r7, lr} - 8003aee: b084 sub sp, #16 - 8003af0: af00 add r7, sp, #0 - 8003af2: 6078 str r0, [r7, #4] + 8004668: b580 push {r7, lr} + 800466a: b084 sub sp, #16 + 800466c: af00 add r7, sp, #0 + 800466e: 6078 str r0, [r7, #4] BaseType_t xAlreadyYielded = pdFALSE; - 8003af4: 2300 movs r3, #0 - 8003af6: 60fb str r3, [r7, #12] + 8004670: 2300 movs r3, #0 + 8004672: 60fb str r3, [r7, #12] /* A delay time of zero just forces a reschedule. */ if( xTicksToDelay > ( TickType_t ) 0U ) - 8003af8: 687b ldr r3, [r7, #4] - 8003afa: 2b00 cmp r3, #0 - 8003afc: d017 beq.n 8003b2e + 8004674: 687b ldr r3, [r7, #4] + 8004676: 2b00 cmp r3, #0 + 8004678: d017 beq.n 80046aa { configASSERT( uxSchedulerSuspended == 0 ); - 8003afe: 4b13 ldr r3, [pc, #76] ; (8003b4c ) - 8003b00: 681b ldr r3, [r3, #0] - 8003b02: 2b00 cmp r3, #0 - 8003b04: d00a beq.n 8003b1c + 800467a: 4b13 ldr r3, [pc, #76] ; (80046c8 ) + 800467c: 681b ldr r3, [r3, #0] + 800467e: 2b00 cmp r3, #0 + 8004680: d00a beq.n 8004698 __asm volatile - 8003b06: f04f 0350 mov.w r3, #80 ; 0x50 - 8003b0a: f383 8811 msr BASEPRI, r3 - 8003b0e: f3bf 8f6f isb sy - 8003b12: f3bf 8f4f dsb sy - 8003b16: 60bb str r3, [r7, #8] + 8004682: f04f 0350 mov.w r3, #80 ; 0x50 + 8004686: f383 8811 msr BASEPRI, r3 + 800468a: f3bf 8f6f isb sy + 800468e: f3bf 8f4f dsb sy + 8004692: 60bb str r3, [r7, #8] } - 8003b18: bf00 nop - 8003b1a: e7fe b.n 8003b1a + 8004694: bf00 nop + 8004696: e7fe b.n 8004696 vTaskSuspendAll(); - 8003b1c: f000 f88a bl 8003c34 + 8004698: f000 f88a bl 80047b0 list or removed from the blocked list until the scheduler is resumed. This task cannot be in an event list as it is the currently executing task. */ prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE ); - 8003b20: 2100 movs r1, #0 - 8003b22: 6878 ldr r0, [r7, #4] - 8003b24: f000 fcfe bl 8004524 + 800469c: 2100 movs r1, #0 + 800469e: 6878 ldr r0, [r7, #4] + 80046a0: f000 fcfe bl 80050a0 } xAlreadyYielded = xTaskResumeAll(); - 8003b28: f000 f892 bl 8003c50 - 8003b2c: 60f8 str r0, [r7, #12] + 80046a4: f000 f892 bl 80047cc + 80046a8: 60f8 str r0, [r7, #12] mtCOVERAGE_TEST_MARKER(); } /* Force a reschedule if xTaskResumeAll has not already done so, we may have put ourselves to sleep. */ if( xAlreadyYielded == pdFALSE ) - 8003b2e: 68fb ldr r3, [r7, #12] - 8003b30: 2b00 cmp r3, #0 - 8003b32: d107 bne.n 8003b44 + 80046aa: 68fb ldr r3, [r7, #12] + 80046ac: 2b00 cmp r3, #0 + 80046ae: d107 bne.n 80046c0 { portYIELD_WITHIN_API(); - 8003b34: 4b06 ldr r3, [pc, #24] ; (8003b50 ) - 8003b36: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 8003b3a: 601a str r2, [r3, #0] - 8003b3c: f3bf 8f4f dsb sy - 8003b40: f3bf 8f6f isb sy + 80046b0: 4b06 ldr r3, [pc, #24] ; (80046cc ) + 80046b2: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80046b6: 601a str r2, [r3, #0] + 80046b8: f3bf 8f4f dsb sy + 80046bc: f3bf 8f6f isb sy } else { mtCOVERAGE_TEST_MARKER(); } } - 8003b44: bf00 nop - 8003b46: 3710 adds r7, #16 - 8003b48: 46bd mov sp, r7 - 8003b4a: bd80 pop {r7, pc} - 8003b4c: 20000dbc .word 0x20000dbc - 8003b50: e000ed04 .word 0xe000ed04 + 80046c0: bf00 nop + 80046c2: 3710 adds r7, #16 + 80046c4: 46bd mov sp, r7 + 80046c6: bd80 pop {r7, pc} + 80046c8: 20000e0c .word 0x20000e0c + 80046cc: e000ed04 .word 0xe000ed04 -08003b54 : +080046d0 : #endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */ /*-----------------------------------------------------------*/ void vTaskStartScheduler( void ) { - 8003b54: b580 push {r7, lr} - 8003b56: b08a sub sp, #40 ; 0x28 - 8003b58: af04 add r7, sp, #16 + 80046d0: b580 push {r7, lr} + 80046d2: b08a sub sp, #40 ; 0x28 + 80046d4: af04 add r7, sp, #16 BaseType_t xReturn; /* Add the idle task at the lowest priority. */ #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxIdleTaskTCBBuffer = NULL; - 8003b5a: 2300 movs r3, #0 - 8003b5c: 60bb str r3, [r7, #8] + 80046d6: 2300 movs r3, #0 + 80046d8: 60bb str r3, [r7, #8] StackType_t *pxIdleTaskStackBuffer = NULL; - 8003b5e: 2300 movs r3, #0 - 8003b60: 607b str r3, [r7, #4] + 80046da: 2300 movs r3, #0 + 80046dc: 607b str r3, [r7, #4] uint32_t ulIdleTaskStackSize; /* The Idle task is created using user provided RAM - obtain the address of the RAM then create the idle task. */ vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize ); - 8003b62: 463a mov r2, r7 - 8003b64: 1d39 adds r1, r7, #4 - 8003b66: f107 0308 add.w r3, r7, #8 - 8003b6a: 4618 mov r0, r3 - 8003b6c: f7ff f832 bl 8002bd4 + 80046de: 463a mov r2, r7 + 80046e0: 1d39 adds r1, r7, #4 + 80046e2: f107 0308 add.w r3, r7, #8 + 80046e6: 4618 mov r0, r3 + 80046e8: f7ff f832 bl 8003750 xIdleTaskHandle = xTaskCreateStatic( prvIdleTask, - 8003b70: 6839 ldr r1, [r7, #0] - 8003b72: 687b ldr r3, [r7, #4] - 8003b74: 68ba ldr r2, [r7, #8] - 8003b76: 9202 str r2, [sp, #8] - 8003b78: 9301 str r3, [sp, #4] - 8003b7a: 2300 movs r3, #0 - 8003b7c: 9300 str r3, [sp, #0] - 8003b7e: 2300 movs r3, #0 - 8003b80: 460a mov r2, r1 - 8003b82: 4924 ldr r1, [pc, #144] ; (8003c14 ) - 8003b84: 4824 ldr r0, [pc, #144] ; (8003c18 ) - 8003b86: f7ff fdf9 bl 800377c - 8003b8a: 4603 mov r3, r0 - 8003b8c: 4a23 ldr r2, [pc, #140] ; (8003c1c ) - 8003b8e: 6013 str r3, [r2, #0] + 80046ec: 6839 ldr r1, [r7, #0] + 80046ee: 687b ldr r3, [r7, #4] + 80046f0: 68ba ldr r2, [r7, #8] + 80046f2: 9202 str r2, [sp, #8] + 80046f4: 9301 str r3, [sp, #4] + 80046f6: 2300 movs r3, #0 + 80046f8: 9300 str r3, [sp, #0] + 80046fa: 2300 movs r3, #0 + 80046fc: 460a mov r2, r1 + 80046fe: 4924 ldr r1, [pc, #144] ; (8004790 ) + 8004700: 4824 ldr r0, [pc, #144] ; (8004794 ) + 8004702: f7ff fdf9 bl 80042f8 + 8004706: 4603 mov r3, r0 + 8004708: 4a23 ldr r2, [pc, #140] ; (8004798 ) + 800470a: 6013 str r3, [r2, #0] ( void * ) NULL, /*lint !e961. The cast is not redundant for all compilers. */ portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */ pxIdleTaskStackBuffer, pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */ if( xIdleTaskHandle != NULL ) - 8003b90: 4b22 ldr r3, [pc, #136] ; (8003c1c ) - 8003b92: 681b ldr r3, [r3, #0] - 8003b94: 2b00 cmp r3, #0 - 8003b96: d002 beq.n 8003b9e + 800470c: 4b22 ldr r3, [pc, #136] ; (8004798 ) + 800470e: 681b ldr r3, [r3, #0] + 8004710: 2b00 cmp r3, #0 + 8004712: d002 beq.n 800471a { xReturn = pdPASS; - 8003b98: 2301 movs r3, #1 - 8003b9a: 617b str r3, [r7, #20] - 8003b9c: e001 b.n 8003ba2 + 8004714: 2301 movs r3, #1 + 8004716: 617b str r3, [r7, #20] + 8004718: e001 b.n 800471e } else { xReturn = pdFAIL; - 8003b9e: 2300 movs r3, #0 - 8003ba0: 617b str r3, [r7, #20] + 800471a: 2300 movs r3, #0 + 800471c: 617b str r3, [r7, #20] } #endif /* configSUPPORT_STATIC_ALLOCATION */ #if ( configUSE_TIMERS == 1 ) { if( xReturn == pdPASS ) - 8003ba2: 697b ldr r3, [r7, #20] - 8003ba4: 2b01 cmp r3, #1 - 8003ba6: d102 bne.n 8003bae + 800471e: 697b ldr r3, [r7, #20] + 8004720: 2b01 cmp r3, #1 + 8004722: d102 bne.n 800472a { xReturn = xTimerCreateTimerTask(); - 8003ba8: f000 fd10 bl 80045cc - 8003bac: 6178 str r0, [r7, #20] + 8004724: f000 fd10 bl 8005148 + 8004728: 6178 str r0, [r7, #20] mtCOVERAGE_TEST_MARKER(); } } #endif /* configUSE_TIMERS */ if( xReturn == pdPASS ) - 8003bae: 697b ldr r3, [r7, #20] - 8003bb0: 2b01 cmp r3, #1 - 8003bb2: d11b bne.n 8003bec + 800472a: 697b ldr r3, [r7, #20] + 800472c: 2b01 cmp r3, #1 + 800472e: d11b bne.n 8004768 __asm volatile - 8003bb4: f04f 0350 mov.w r3, #80 ; 0x50 - 8003bb8: f383 8811 msr BASEPRI, r3 - 8003bbc: f3bf 8f6f isb sy - 8003bc0: f3bf 8f4f dsb sy - 8003bc4: 613b str r3, [r7, #16] + 8004730: f04f 0350 mov.w r3, #80 ; 0x50 + 8004734: f383 8811 msr BASEPRI, r3 + 8004738: f3bf 8f6f isb sy + 800473c: f3bf 8f4f dsb sy + 8004740: 613b str r3, [r7, #16] } - 8003bc6: bf00 nop + 8004742: bf00 nop { /* Switch Newlib's _impure_ptr variable to point to the _reent structure specific to the task that will run first. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); - 8003bc8: 4b15 ldr r3, [pc, #84] ; (8003c20 ) - 8003bca: 681b ldr r3, [r3, #0] - 8003bcc: 3354 adds r3, #84 ; 0x54 - 8003bce: 4a15 ldr r2, [pc, #84] ; (8003c24 ) - 8003bd0: 6013 str r3, [r2, #0] + 8004744: 4b15 ldr r3, [pc, #84] ; (800479c ) + 8004746: 681b ldr r3, [r3, #0] + 8004748: 3354 adds r3, #84 ; 0x54 + 800474a: 4a15 ldr r2, [pc, #84] ; (80047a0 ) + 800474c: 6013 str r3, [r2, #0] } #endif /* configUSE_NEWLIB_REENTRANT */ xNextTaskUnblockTime = portMAX_DELAY; - 8003bd2: 4b15 ldr r3, [pc, #84] ; (8003c28 ) - 8003bd4: f04f 32ff mov.w r2, #4294967295 - 8003bd8: 601a str r2, [r3, #0] + 800474e: 4b15 ldr r3, [pc, #84] ; (80047a4 ) + 8004750: f04f 32ff mov.w r2, #4294967295 + 8004754: 601a str r2, [r3, #0] xSchedulerRunning = pdTRUE; - 8003bda: 4b14 ldr r3, [pc, #80] ; (8003c2c ) - 8003bdc: 2201 movs r2, #1 - 8003bde: 601a str r2, [r3, #0] + 8004756: 4b14 ldr r3, [pc, #80] ; (80047a8 ) + 8004758: 2201 movs r2, #1 + 800475a: 601a str r2, [r3, #0] xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT; - 8003be0: 4b13 ldr r3, [pc, #76] ; (8003c30 ) - 8003be2: 2200 movs r2, #0 - 8003be4: 601a str r2, [r3, #0] + 800475c: 4b13 ldr r3, [pc, #76] ; (80047ac ) + 800475e: 2200 movs r2, #0 + 8004760: 601a str r2, [r3, #0] traceTASK_SWITCHED_IN(); /* Setting up the timer tick is hardware specific and thus in the portable interface. */ if( xPortStartScheduler() != pdFALSE ) - 8003be6: f001 f8cb bl 8004d80 + 8004762: f001 f8cd bl 8005900 } /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0, meaning xIdleTaskHandle is not used anywhere else. */ ( void ) xIdleTaskHandle; } - 8003bea: e00e b.n 8003c0a + 8004766: e00e b.n 8004786 configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ); - 8003bec: 697b ldr r3, [r7, #20] - 8003bee: f1b3 3fff cmp.w r3, #4294967295 - 8003bf2: d10a bne.n 8003c0a + 8004768: 697b ldr r3, [r7, #20] + 800476a: f1b3 3fff cmp.w r3, #4294967295 + 800476e: d10a bne.n 8004786 __asm volatile - 8003bf4: f04f 0350 mov.w r3, #80 ; 0x50 - 8003bf8: f383 8811 msr BASEPRI, r3 - 8003bfc: f3bf 8f6f isb sy - 8003c00: f3bf 8f4f dsb sy - 8003c04: 60fb str r3, [r7, #12] + 8004770: f04f 0350 mov.w r3, #80 ; 0x50 + 8004774: f383 8811 msr BASEPRI, r3 + 8004778: f3bf 8f6f isb sy + 800477c: f3bf 8f4f dsb sy + 8004780: 60fb str r3, [r7, #12] } - 8003c06: bf00 nop - 8003c08: e7fe b.n 8003c08 + 8004782: bf00 nop + 8004784: e7fe b.n 8004784 } - 8003c0a: bf00 nop - 8003c0c: 3718 adds r7, #24 - 8003c0e: 46bd mov sp, r7 - 8003c10: bd80 pop {r7, pc} - 8003c12: bf00 nop - 8003c14: 080056e0 .word 0x080056e0 - 8003c18: 08004259 .word 0x08004259 - 8003c1c: 20000db8 .word 0x20000db8 - 8003c20: 200008c0 .word 0x200008c0 - 8003c24: 2000005c .word 0x2000005c - 8003c28: 20000db4 .word 0x20000db4 - 8003c2c: 20000da0 .word 0x20000da0 - 8003c30: 20000d98 .word 0x20000d98 + 8004786: bf00 nop + 8004788: 3718 adds r7, #24 + 800478a: 46bd mov sp, r7 + 800478c: bd80 pop {r7, pc} + 800478e: bf00 nop + 8004790: 0800627c .word 0x0800627c + 8004794: 08004dd5 .word 0x08004dd5 + 8004798: 20000e08 .word 0x20000e08 + 800479c: 20000910 .word 0x20000910 + 80047a0: 2000005c .word 0x2000005c + 80047a4: 20000e04 .word 0x20000e04 + 80047a8: 20000df0 .word 0x20000df0 + 80047ac: 20000de8 .word 0x20000de8 -08003c34 : +080047b0 : vPortEndScheduler(); } /*----------------------------------------------------------*/ void vTaskSuspendAll( void ) { - 8003c34: b480 push {r7} - 8003c36: af00 add r7, sp, #0 + 80047b0: b480 push {r7} + 80047b2: af00 add r7, sp, #0 do not otherwise exhibit real time behaviour. */ portSOFTWARE_BARRIER(); /* The scheduler is suspended if uxSchedulerSuspended is non-zero. An increment is used to allow calls to vTaskSuspendAll() to nest. */ ++uxSchedulerSuspended; - 8003c38: 4b04 ldr r3, [pc, #16] ; (8003c4c ) - 8003c3a: 681b ldr r3, [r3, #0] - 8003c3c: 3301 adds r3, #1 - 8003c3e: 4a03 ldr r2, [pc, #12] ; (8003c4c ) - 8003c40: 6013 str r3, [r2, #0] + 80047b4: 4b04 ldr r3, [pc, #16] ; (80047c8 ) + 80047b6: 681b ldr r3, [r3, #0] + 80047b8: 3301 adds r3, #1 + 80047ba: 4a03 ldr r2, [pc, #12] ; (80047c8 ) + 80047bc: 6013 str r3, [r2, #0] /* Enforces ordering for ports and optimised compilers that may otherwise place the above increment elsewhere. */ portMEMORY_BARRIER(); } - 8003c42: bf00 nop - 8003c44: 46bd mov sp, r7 - 8003c46: f85d 7b04 ldr.w r7, [sp], #4 - 8003c4a: 4770 bx lr - 8003c4c: 20000dbc .word 0x20000dbc + 80047be: bf00 nop + 80047c0: 46bd mov sp, r7 + 80047c2: f85d 7b04 ldr.w r7, [sp], #4 + 80047c6: 4770 bx lr + 80047c8: 20000e0c .word 0x20000e0c -08003c50 : +080047cc : #endif /* configUSE_TICKLESS_IDLE */ /*----------------------------------------------------------*/ BaseType_t xTaskResumeAll( void ) { - 8003c50: b580 push {r7, lr} - 8003c52: b084 sub sp, #16 - 8003c54: af00 add r7, sp, #0 + 80047cc: b580 push {r7, lr} + 80047ce: b084 sub sp, #16 + 80047d0: af00 add r7, sp, #0 TCB_t *pxTCB = NULL; - 8003c56: 2300 movs r3, #0 - 8003c58: 60fb str r3, [r7, #12] + 80047d2: 2300 movs r3, #0 + 80047d4: 60fb str r3, [r7, #12] BaseType_t xAlreadyYielded = pdFALSE; - 8003c5a: 2300 movs r3, #0 - 8003c5c: 60bb str r3, [r7, #8] + 80047d6: 2300 movs r3, #0 + 80047d8: 60bb str r3, [r7, #8] /* If uxSchedulerSuspended is zero then this function does not match a previous call to vTaskSuspendAll(). */ configASSERT( uxSchedulerSuspended ); - 8003c5e: 4b42 ldr r3, [pc, #264] ; (8003d68 ) - 8003c60: 681b ldr r3, [r3, #0] - 8003c62: 2b00 cmp r3, #0 - 8003c64: d10a bne.n 8003c7c + 80047da: 4b42 ldr r3, [pc, #264] ; (80048e4 ) + 80047dc: 681b ldr r3, [r3, #0] + 80047de: 2b00 cmp r3, #0 + 80047e0: d10a bne.n 80047f8 __asm volatile - 8003c66: f04f 0350 mov.w r3, #80 ; 0x50 - 8003c6a: f383 8811 msr BASEPRI, r3 - 8003c6e: f3bf 8f6f isb sy - 8003c72: f3bf 8f4f dsb sy - 8003c76: 603b str r3, [r7, #0] + 80047e2: f04f 0350 mov.w r3, #80 ; 0x50 + 80047e6: f383 8811 msr BASEPRI, r3 + 80047ea: f3bf 8f6f isb sy + 80047ee: f3bf 8f4f dsb sy + 80047f2: 603b str r3, [r7, #0] } - 8003c78: bf00 nop - 8003c7a: e7fe b.n 8003c7a + 80047f4: bf00 nop + 80047f6: e7fe b.n 80047f6 /* It is possible that an ISR caused a task to be removed from an event list while the scheduler was suspended. If this was the case then the removed task will have been added to the xPendingReadyList. Once the scheduler has been resumed it is safe to move all the pending ready tasks from this list into their appropriate ready list. */ taskENTER_CRITICAL(); - 8003c7c: f001 f922 bl 8004ec4 + 80047f8: f001 f924 bl 8005a44 { --uxSchedulerSuspended; - 8003c80: 4b39 ldr r3, [pc, #228] ; (8003d68 ) - 8003c82: 681b ldr r3, [r3, #0] - 8003c84: 3b01 subs r3, #1 - 8003c86: 4a38 ldr r2, [pc, #224] ; (8003d68 ) - 8003c88: 6013 str r3, [r2, #0] + 80047fc: 4b39 ldr r3, [pc, #228] ; (80048e4 ) + 80047fe: 681b ldr r3, [r3, #0] + 8004800: 3b01 subs r3, #1 + 8004802: 4a38 ldr r2, [pc, #224] ; (80048e4 ) + 8004804: 6013 str r3, [r2, #0] if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) - 8003c8a: 4b37 ldr r3, [pc, #220] ; (8003d68 ) - 8003c8c: 681b ldr r3, [r3, #0] - 8003c8e: 2b00 cmp r3, #0 - 8003c90: d162 bne.n 8003d58 + 8004806: 4b37 ldr r3, [pc, #220] ; (80048e4 ) + 8004808: 681b ldr r3, [r3, #0] + 800480a: 2b00 cmp r3, #0 + 800480c: d162 bne.n 80048d4 { if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U ) - 8003c92: 4b36 ldr r3, [pc, #216] ; (8003d6c ) - 8003c94: 681b ldr r3, [r3, #0] - 8003c96: 2b00 cmp r3, #0 - 8003c98: d05e beq.n 8003d58 + 800480e: 4b36 ldr r3, [pc, #216] ; (80048e8 ) + 8004810: 681b ldr r3, [r3, #0] + 8004812: 2b00 cmp r3, #0 + 8004814: d05e beq.n 80048d4 { /* Move any readied tasks from the pending list into the appropriate ready list. */ while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) - 8003c9a: e02f b.n 8003cfc + 8004816: e02f b.n 8004878 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8003c9c: 4b34 ldr r3, [pc, #208] ; (8003d70 ) - 8003c9e: 68db ldr r3, [r3, #12] - 8003ca0: 68db ldr r3, [r3, #12] - 8003ca2: 60fb str r3, [r7, #12] + 8004818: 4b34 ldr r3, [pc, #208] ; (80048ec ) + 800481a: 68db ldr r3, [r3, #12] + 800481c: 68db ldr r3, [r3, #12] + 800481e: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); - 8003ca4: 68fb ldr r3, [r7, #12] - 8003ca6: 3318 adds r3, #24 - 8003ca8: 4618 mov r0, r3 - 8003caa: f7ff f851 bl 8002d50 + 8004820: 68fb ldr r3, [r7, #12] + 8004822: 3318 adds r3, #24 + 8004824: 4618 mov r0, r3 + 8004826: f7ff f851 bl 80038cc ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); - 8003cae: 68fb ldr r3, [r7, #12] - 8003cb0: 3304 adds r3, #4 - 8003cb2: 4618 mov r0, r3 - 8003cb4: f7ff f84c bl 8002d50 + 800482a: 68fb ldr r3, [r7, #12] + 800482c: 3304 adds r3, #4 + 800482e: 4618 mov r0, r3 + 8004830: f7ff f84c bl 80038cc prvAddTaskToReadyList( pxTCB ); - 8003cb8: 68fb ldr r3, [r7, #12] - 8003cba: 6ada ldr r2, [r3, #44] ; 0x2c - 8003cbc: 4b2d ldr r3, [pc, #180] ; (8003d74 ) - 8003cbe: 681b ldr r3, [r3, #0] - 8003cc0: 429a cmp r2, r3 - 8003cc2: d903 bls.n 8003ccc - 8003cc4: 68fb ldr r3, [r7, #12] - 8003cc6: 6adb ldr r3, [r3, #44] ; 0x2c - 8003cc8: 4a2a ldr r2, [pc, #168] ; (8003d74 ) - 8003cca: 6013 str r3, [r2, #0] - 8003ccc: 68fb ldr r3, [r7, #12] - 8003cce: 6ada ldr r2, [r3, #44] ; 0x2c - 8003cd0: 4613 mov r3, r2 - 8003cd2: 009b lsls r3, r3, #2 - 8003cd4: 4413 add r3, r2 - 8003cd6: 009b lsls r3, r3, #2 - 8003cd8: 4a27 ldr r2, [pc, #156] ; (8003d78 ) - 8003cda: 441a add r2, r3 - 8003cdc: 68fb ldr r3, [r7, #12] - 8003cde: 3304 adds r3, #4 - 8003ce0: 4619 mov r1, r3 - 8003ce2: 4610 mov r0, r2 - 8003ce4: f7fe ffd7 bl 8002c96 + 8004834: 68fb ldr r3, [r7, #12] + 8004836: 6ada ldr r2, [r3, #44] ; 0x2c + 8004838: 4b2d ldr r3, [pc, #180] ; (80048f0 ) + 800483a: 681b ldr r3, [r3, #0] + 800483c: 429a cmp r2, r3 + 800483e: d903 bls.n 8004848 + 8004840: 68fb ldr r3, [r7, #12] + 8004842: 6adb ldr r3, [r3, #44] ; 0x2c + 8004844: 4a2a ldr r2, [pc, #168] ; (80048f0 ) + 8004846: 6013 str r3, [r2, #0] + 8004848: 68fb ldr r3, [r7, #12] + 800484a: 6ada ldr r2, [r3, #44] ; 0x2c + 800484c: 4613 mov r3, r2 + 800484e: 009b lsls r3, r3, #2 + 8004850: 4413 add r3, r2 + 8004852: 009b lsls r3, r3, #2 + 8004854: 4a27 ldr r2, [pc, #156] ; (80048f4 ) + 8004856: 441a add r2, r3 + 8004858: 68fb ldr r3, [r7, #12] + 800485a: 3304 adds r3, #4 + 800485c: 4619 mov r1, r3 + 800485e: 4610 mov r0, r2 + 8004860: f7fe ffd7 bl 8003812 /* If the moved task has a priority higher than the current task then a yield must be performed. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - 8003ce8: 68fb ldr r3, [r7, #12] - 8003cea: 6ada ldr r2, [r3, #44] ; 0x2c - 8003cec: 4b23 ldr r3, [pc, #140] ; (8003d7c ) - 8003cee: 681b ldr r3, [r3, #0] - 8003cf0: 6adb ldr r3, [r3, #44] ; 0x2c - 8003cf2: 429a cmp r2, r3 - 8003cf4: d302 bcc.n 8003cfc + 8004864: 68fb ldr r3, [r7, #12] + 8004866: 6ada ldr r2, [r3, #44] ; 0x2c + 8004868: 4b23 ldr r3, [pc, #140] ; (80048f8 ) + 800486a: 681b ldr r3, [r3, #0] + 800486c: 6adb ldr r3, [r3, #44] ; 0x2c + 800486e: 429a cmp r2, r3 + 8004870: d302 bcc.n 8004878 { xYieldPending = pdTRUE; - 8003cf6: 4b22 ldr r3, [pc, #136] ; (8003d80 ) - 8003cf8: 2201 movs r2, #1 - 8003cfa: 601a str r2, [r3, #0] + 8004872: 4b22 ldr r3, [pc, #136] ; (80048fc ) + 8004874: 2201 movs r2, #1 + 8004876: 601a str r2, [r3, #0] while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE ) - 8003cfc: 4b1c ldr r3, [pc, #112] ; (8003d70 ) - 8003cfe: 681b ldr r3, [r3, #0] - 8003d00: 2b00 cmp r3, #0 - 8003d02: d1cb bne.n 8003c9c + 8004878: 4b1c ldr r3, [pc, #112] ; (80048ec ) + 800487a: 681b ldr r3, [r3, #0] + 800487c: 2b00 cmp r3, #0 + 800487e: d1cb bne.n 8004818 { mtCOVERAGE_TEST_MARKER(); } } if( pxTCB != NULL ) - 8003d04: 68fb ldr r3, [r7, #12] - 8003d06: 2b00 cmp r3, #0 - 8003d08: d001 beq.n 8003d0e + 8004880: 68fb ldr r3, [r7, #12] + 8004882: 2b00 cmp r3, #0 + 8004884: d001 beq.n 800488a which may have prevented the next unblock time from being re-calculated, in which case re-calculate it now. Mainly important for low power tickless implementations, where this can prevent an unnecessary exit from low power state. */ prvResetNextTaskUnblockTime(); - 8003d0a: f000 fb5f bl 80043cc + 8004886: f000 fb5f bl 8004f48 /* If any ticks occurred while the scheduler was suspended then they should be processed now. This ensures the tick count does not slip, and that any delayed tasks are resumed at the correct time. */ { TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */ - 8003d0e: 4b1d ldr r3, [pc, #116] ; (8003d84 ) - 8003d10: 681b ldr r3, [r3, #0] - 8003d12: 607b str r3, [r7, #4] + 800488a: 4b1d ldr r3, [pc, #116] ; (8004900 ) + 800488c: 681b ldr r3, [r3, #0] + 800488e: 607b str r3, [r7, #4] if( xPendedCounts > ( TickType_t ) 0U ) - 8003d14: 687b ldr r3, [r7, #4] - 8003d16: 2b00 cmp r3, #0 - 8003d18: d010 beq.n 8003d3c + 8004890: 687b ldr r3, [r7, #4] + 8004892: 2b00 cmp r3, #0 + 8004894: d010 beq.n 80048b8 { do { if( xTaskIncrementTick() != pdFALSE ) - 8003d1a: f000 f847 bl 8003dac - 8003d1e: 4603 mov r3, r0 - 8003d20: 2b00 cmp r3, #0 - 8003d22: d002 beq.n 8003d2a + 8004896: f000 f847 bl 8004928 + 800489a: 4603 mov r3, r0 + 800489c: 2b00 cmp r3, #0 + 800489e: d002 beq.n 80048a6 { xYieldPending = pdTRUE; - 8003d24: 4b16 ldr r3, [pc, #88] ; (8003d80 ) - 8003d26: 2201 movs r2, #1 - 8003d28: 601a str r2, [r3, #0] + 80048a0: 4b16 ldr r3, [pc, #88] ; (80048fc ) + 80048a2: 2201 movs r2, #1 + 80048a4: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } --xPendedCounts; - 8003d2a: 687b ldr r3, [r7, #4] - 8003d2c: 3b01 subs r3, #1 - 8003d2e: 607b str r3, [r7, #4] + 80048a6: 687b ldr r3, [r7, #4] + 80048a8: 3b01 subs r3, #1 + 80048aa: 607b str r3, [r7, #4] } while( xPendedCounts > ( TickType_t ) 0U ); - 8003d30: 687b ldr r3, [r7, #4] - 8003d32: 2b00 cmp r3, #0 - 8003d34: d1f1 bne.n 8003d1a + 80048ac: 687b ldr r3, [r7, #4] + 80048ae: 2b00 cmp r3, #0 + 80048b0: d1f1 bne.n 8004896 xPendedTicks = 0; - 8003d36: 4b13 ldr r3, [pc, #76] ; (8003d84 ) - 8003d38: 2200 movs r2, #0 - 8003d3a: 601a str r2, [r3, #0] + 80048b2: 4b13 ldr r3, [pc, #76] ; (8004900 ) + 80048b4: 2200 movs r2, #0 + 80048b6: 601a str r2, [r3, #0] { mtCOVERAGE_TEST_MARKER(); } } if( xYieldPending != pdFALSE ) - 8003d3c: 4b10 ldr r3, [pc, #64] ; (8003d80 ) - 8003d3e: 681b ldr r3, [r3, #0] - 8003d40: 2b00 cmp r3, #0 - 8003d42: d009 beq.n 8003d58 + 80048b8: 4b10 ldr r3, [pc, #64] ; (80048fc ) + 80048ba: 681b ldr r3, [r3, #0] + 80048bc: 2b00 cmp r3, #0 + 80048be: d009 beq.n 80048d4 { #if( configUSE_PREEMPTION != 0 ) { xAlreadyYielded = pdTRUE; - 8003d44: 2301 movs r3, #1 - 8003d46: 60bb str r3, [r7, #8] + 80048c0: 2301 movs r3, #1 + 80048c2: 60bb str r3, [r7, #8] } #endif taskYIELD_IF_USING_PREEMPTION(); - 8003d48: 4b0f ldr r3, [pc, #60] ; (8003d88 ) - 8003d4a: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 8003d4e: 601a str r2, [r3, #0] - 8003d50: f3bf 8f4f dsb sy - 8003d54: f3bf 8f6f isb sy + 80048c4: 4b0f ldr r3, [pc, #60] ; (8004904 ) + 80048c6: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80048ca: 601a str r2, [r3, #0] + 80048cc: f3bf 8f4f dsb sy + 80048d0: f3bf 8f6f isb sy else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); - 8003d58: f001 f8e4 bl 8004f24 + 80048d4: f001 f8e6 bl 8005aa4 return xAlreadyYielded; - 8003d5c: 68bb ldr r3, [r7, #8] + 80048d8: 68bb ldr r3, [r7, #8] } - 8003d5e: 4618 mov r0, r3 - 8003d60: 3710 adds r7, #16 - 8003d62: 46bd mov sp, r7 - 8003d64: bd80 pop {r7, pc} - 8003d66: bf00 nop - 8003d68: 20000dbc .word 0x20000dbc - 8003d6c: 20000d94 .word 0x20000d94 - 8003d70: 20000d54 .word 0x20000d54 - 8003d74: 20000d9c .word 0x20000d9c - 8003d78: 200008c4 .word 0x200008c4 - 8003d7c: 200008c0 .word 0x200008c0 - 8003d80: 20000da8 .word 0x20000da8 - 8003d84: 20000da4 .word 0x20000da4 - 8003d88: e000ed04 .word 0xe000ed04 + 80048da: 4618 mov r0, r3 + 80048dc: 3710 adds r7, #16 + 80048de: 46bd mov sp, r7 + 80048e0: bd80 pop {r7, pc} + 80048e2: bf00 nop + 80048e4: 20000e0c .word 0x20000e0c + 80048e8: 20000de4 .word 0x20000de4 + 80048ec: 20000da4 .word 0x20000da4 + 80048f0: 20000dec .word 0x20000dec + 80048f4: 20000914 .word 0x20000914 + 80048f8: 20000910 .word 0x20000910 + 80048fc: 20000df8 .word 0x20000df8 + 8004900: 20000df4 .word 0x20000df4 + 8004904: e000ed04 .word 0xe000ed04 -08003d8c : +08004908 : /*-----------------------------------------------------------*/ TickType_t xTaskGetTickCount( void ) { - 8003d8c: b480 push {r7} - 8003d8e: b083 sub sp, #12 - 8003d90: af00 add r7, sp, #0 + 8004908: b480 push {r7} + 800490a: b083 sub sp, #12 + 800490c: af00 add r7, sp, #0 TickType_t xTicks; /* Critical section required if running on a 16 bit processor. */ portTICK_TYPE_ENTER_CRITICAL(); { xTicks = xTickCount; - 8003d92: 4b05 ldr r3, [pc, #20] ; (8003da8 ) - 8003d94: 681b ldr r3, [r3, #0] - 8003d96: 607b str r3, [r7, #4] + 800490e: 4b05 ldr r3, [pc, #20] ; (8004924 ) + 8004910: 681b ldr r3, [r3, #0] + 8004912: 607b str r3, [r7, #4] } portTICK_TYPE_EXIT_CRITICAL(); return xTicks; - 8003d98: 687b ldr r3, [r7, #4] + 8004914: 687b ldr r3, [r7, #4] } - 8003d9a: 4618 mov r0, r3 - 8003d9c: 370c adds r7, #12 - 8003d9e: 46bd mov sp, r7 - 8003da0: f85d 7b04 ldr.w r7, [sp], #4 - 8003da4: 4770 bx lr - 8003da6: bf00 nop - 8003da8: 20000d98 .word 0x20000d98 + 8004916: 4618 mov r0, r3 + 8004918: 370c adds r7, #12 + 800491a: 46bd mov sp, r7 + 800491c: f85d 7b04 ldr.w r7, [sp], #4 + 8004920: 4770 bx lr + 8004922: bf00 nop + 8004924: 20000de8 .word 0x20000de8 -08003dac : +08004928 : #endif /* INCLUDE_xTaskAbortDelay */ /*----------------------------------------------------------*/ BaseType_t xTaskIncrementTick( void ) { - 8003dac: b580 push {r7, lr} - 8003dae: b086 sub sp, #24 - 8003db0: af00 add r7, sp, #0 + 8004928: b580 push {r7, lr} + 800492a: b086 sub sp, #24 + 800492c: af00 add r7, sp, #0 TCB_t * pxTCB; TickType_t xItemValue; BaseType_t xSwitchRequired = pdFALSE; - 8003db2: 2300 movs r3, #0 - 8003db4: 617b str r3, [r7, #20] + 800492e: 2300 movs r3, #0 + 8004930: 617b str r3, [r7, #20] /* Called by the portable layer each time a tick interrupt occurs. Increments the tick then checks to see if the new tick value will cause any tasks to be unblocked. */ traceTASK_INCREMENT_TICK( xTickCount ); if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) - 8003db6: 4b4f ldr r3, [pc, #316] ; (8003ef4 ) - 8003db8: 681b ldr r3, [r3, #0] - 8003dba: 2b00 cmp r3, #0 - 8003dbc: f040 808f bne.w 8003ede + 8004932: 4b4f ldr r3, [pc, #316] ; (8004a70 ) + 8004934: 681b ldr r3, [r3, #0] + 8004936: 2b00 cmp r3, #0 + 8004938: f040 808f bne.w 8004a5a { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1; - 8003dc0: 4b4d ldr r3, [pc, #308] ; (8003ef8 ) - 8003dc2: 681b ldr r3, [r3, #0] - 8003dc4: 3301 adds r3, #1 - 8003dc6: 613b str r3, [r7, #16] + 800493c: 4b4d ldr r3, [pc, #308] ; (8004a74 ) + 800493e: 681b ldr r3, [r3, #0] + 8004940: 3301 adds r3, #1 + 8004942: 613b str r3, [r7, #16] /* Increment the RTOS tick, switching the delayed and overflowed delayed lists if it wraps to 0. */ xTickCount = xConstTickCount; - 8003dc8: 4a4b ldr r2, [pc, #300] ; (8003ef8 ) - 8003dca: 693b ldr r3, [r7, #16] - 8003dcc: 6013 str r3, [r2, #0] + 8004944: 4a4b ldr r2, [pc, #300] ; (8004a74 ) + 8004946: 693b ldr r3, [r7, #16] + 8004948: 6013 str r3, [r2, #0] if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */ - 8003dce: 693b ldr r3, [r7, #16] - 8003dd0: 2b00 cmp r3, #0 - 8003dd2: d120 bne.n 8003e16 + 800494a: 693b ldr r3, [r7, #16] + 800494c: 2b00 cmp r3, #0 + 800494e: d120 bne.n 8004992 { taskSWITCH_DELAYED_LISTS(); - 8003dd4: 4b49 ldr r3, [pc, #292] ; (8003efc ) - 8003dd6: 681b ldr r3, [r3, #0] - 8003dd8: 681b ldr r3, [r3, #0] - 8003dda: 2b00 cmp r3, #0 - 8003ddc: d00a beq.n 8003df4 + 8004950: 4b49 ldr r3, [pc, #292] ; (8004a78 ) + 8004952: 681b ldr r3, [r3, #0] + 8004954: 681b ldr r3, [r3, #0] + 8004956: 2b00 cmp r3, #0 + 8004958: d00a beq.n 8004970 __asm volatile - 8003dde: f04f 0350 mov.w r3, #80 ; 0x50 - 8003de2: f383 8811 msr BASEPRI, r3 - 8003de6: f3bf 8f6f isb sy - 8003dea: f3bf 8f4f dsb sy - 8003dee: 603b str r3, [r7, #0] + 800495a: f04f 0350 mov.w r3, #80 ; 0x50 + 800495e: f383 8811 msr BASEPRI, r3 + 8004962: f3bf 8f6f isb sy + 8004966: f3bf 8f4f dsb sy + 800496a: 603b str r3, [r7, #0] } - 8003df0: bf00 nop - 8003df2: e7fe b.n 8003df2 - 8003df4: 4b41 ldr r3, [pc, #260] ; (8003efc ) - 8003df6: 681b ldr r3, [r3, #0] - 8003df8: 60fb str r3, [r7, #12] - 8003dfa: 4b41 ldr r3, [pc, #260] ; (8003f00 ) - 8003dfc: 681b ldr r3, [r3, #0] - 8003dfe: 4a3f ldr r2, [pc, #252] ; (8003efc ) - 8003e00: 6013 str r3, [r2, #0] - 8003e02: 4a3f ldr r2, [pc, #252] ; (8003f00 ) - 8003e04: 68fb ldr r3, [r7, #12] - 8003e06: 6013 str r3, [r2, #0] - 8003e08: 4b3e ldr r3, [pc, #248] ; (8003f04 ) - 8003e0a: 681b ldr r3, [r3, #0] - 8003e0c: 3301 adds r3, #1 - 8003e0e: 4a3d ldr r2, [pc, #244] ; (8003f04 ) - 8003e10: 6013 str r3, [r2, #0] - 8003e12: f000 fadb bl 80043cc + 800496c: bf00 nop + 800496e: e7fe b.n 800496e + 8004970: 4b41 ldr r3, [pc, #260] ; (8004a78 ) + 8004972: 681b ldr r3, [r3, #0] + 8004974: 60fb str r3, [r7, #12] + 8004976: 4b41 ldr r3, [pc, #260] ; (8004a7c ) + 8004978: 681b ldr r3, [r3, #0] + 800497a: 4a3f ldr r2, [pc, #252] ; (8004a78 ) + 800497c: 6013 str r3, [r2, #0] + 800497e: 4a3f ldr r2, [pc, #252] ; (8004a7c ) + 8004980: 68fb ldr r3, [r7, #12] + 8004982: 6013 str r3, [r2, #0] + 8004984: 4b3e ldr r3, [pc, #248] ; (8004a80 ) + 8004986: 681b ldr r3, [r3, #0] + 8004988: 3301 adds r3, #1 + 800498a: 4a3d ldr r2, [pc, #244] ; (8004a80 ) + 800498c: 6013 str r3, [r2, #0] + 800498e: f000 fadb bl 8004f48 /* See if this tick has made a timeout expire. Tasks are stored in the queue in the order of their wake time - meaning once one task has been found whose block time has not expired there is no need to look any further down the list. */ if( xConstTickCount >= xNextTaskUnblockTime ) - 8003e16: 4b3c ldr r3, [pc, #240] ; (8003f08 ) - 8003e18: 681b ldr r3, [r3, #0] - 8003e1a: 693a ldr r2, [r7, #16] - 8003e1c: 429a cmp r2, r3 - 8003e1e: d349 bcc.n 8003eb4 + 8004992: 4b3c ldr r3, [pc, #240] ; (8004a84 ) + 8004994: 681b ldr r3, [r3, #0] + 8004996: 693a ldr r2, [r7, #16] + 8004998: 429a cmp r2, r3 + 800499a: d349 bcc.n 8004a30 { for( ;; ) { if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) - 8003e20: 4b36 ldr r3, [pc, #216] ; (8003efc ) - 8003e22: 681b ldr r3, [r3, #0] - 8003e24: 681b ldr r3, [r3, #0] - 8003e26: 2b00 cmp r3, #0 - 8003e28: d104 bne.n 8003e34 + 800499c: 4b36 ldr r3, [pc, #216] ; (8004a78 ) + 800499e: 681b ldr r3, [r3, #0] + 80049a0: 681b ldr r3, [r3, #0] + 80049a2: 2b00 cmp r3, #0 + 80049a4: d104 bne.n 80049b0 /* The delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass next time through. */ xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - 8003e2a: 4b37 ldr r3, [pc, #220] ; (8003f08 ) - 8003e2c: f04f 32ff mov.w r2, #4294967295 - 8003e30: 601a str r2, [r3, #0] + 80049a6: 4b37 ldr r3, [pc, #220] ; (8004a84 ) + 80049a8: f04f 32ff mov.w r2, #4294967295 + 80049ac: 601a str r2, [r3, #0] break; - 8003e32: e03f b.n 8003eb4 + 80049ae: e03f b.n 8004a30 { /* The delayed list is not empty, get the value of the item at the head of the delayed list. This is the time at which the task at the head of the delayed list must be removed from the Blocked state. */ pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8003e34: 4b31 ldr r3, [pc, #196] ; (8003efc ) - 8003e36: 681b ldr r3, [r3, #0] - 8003e38: 68db ldr r3, [r3, #12] - 8003e3a: 68db ldr r3, [r3, #12] - 8003e3c: 60bb str r3, [r7, #8] + 80049b0: 4b31 ldr r3, [pc, #196] ; (8004a78 ) + 80049b2: 681b ldr r3, [r3, #0] + 80049b4: 68db ldr r3, [r3, #12] + 80049b6: 68db ldr r3, [r3, #12] + 80049b8: 60bb str r3, [r7, #8] xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) ); - 8003e3e: 68bb ldr r3, [r7, #8] - 8003e40: 685b ldr r3, [r3, #4] - 8003e42: 607b str r3, [r7, #4] + 80049ba: 68bb ldr r3, [r7, #8] + 80049bc: 685b ldr r3, [r3, #4] + 80049be: 607b str r3, [r7, #4] if( xConstTickCount < xItemValue ) - 8003e44: 693a ldr r2, [r7, #16] - 8003e46: 687b ldr r3, [r7, #4] - 8003e48: 429a cmp r2, r3 - 8003e4a: d203 bcs.n 8003e54 + 80049c0: 693a ldr r2, [r7, #16] + 80049c2: 687b ldr r3, [r7, #4] + 80049c4: 429a cmp r2, r3 + 80049c6: d203 bcs.n 80049d0 /* It is not time to unblock this item yet, but the item value is the time at which the task at the head of the blocked list must be removed from the Blocked state - so record the item value in xNextTaskUnblockTime. */ xNextTaskUnblockTime = xItemValue; - 8003e4c: 4a2e ldr r2, [pc, #184] ; (8003f08 ) - 8003e4e: 687b ldr r3, [r7, #4] - 8003e50: 6013 str r3, [r2, #0] + 80049c8: 4a2e ldr r2, [pc, #184] ; (8004a84 ) + 80049ca: 687b ldr r3, [r7, #4] + 80049cc: 6013 str r3, [r2, #0] break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */ - 8003e52: e02f b.n 8003eb4 + 80049ce: e02f b.n 8004a30 { mtCOVERAGE_TEST_MARKER(); } /* It is time to remove the item from the Blocked state. */ ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); - 8003e54: 68bb ldr r3, [r7, #8] - 8003e56: 3304 adds r3, #4 - 8003e58: 4618 mov r0, r3 - 8003e5a: f7fe ff79 bl 8002d50 + 80049d0: 68bb ldr r3, [r7, #8] + 80049d2: 3304 adds r3, #4 + 80049d4: 4618 mov r0, r3 + 80049d6: f7fe ff79 bl 80038cc /* Is the task waiting on an event also? If so remove it from the event list. */ if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL ) - 8003e5e: 68bb ldr r3, [r7, #8] - 8003e60: 6a9b ldr r3, [r3, #40] ; 0x28 - 8003e62: 2b00 cmp r3, #0 - 8003e64: d004 beq.n 8003e70 + 80049da: 68bb ldr r3, [r7, #8] + 80049dc: 6a9b ldr r3, [r3, #40] ; 0x28 + 80049de: 2b00 cmp r3, #0 + 80049e0: d004 beq.n 80049ec { ( void ) uxListRemove( &( pxTCB->xEventListItem ) ); - 8003e66: 68bb ldr r3, [r7, #8] - 8003e68: 3318 adds r3, #24 - 8003e6a: 4618 mov r0, r3 - 8003e6c: f7fe ff70 bl 8002d50 + 80049e2: 68bb ldr r3, [r7, #8] + 80049e4: 3318 adds r3, #24 + 80049e6: 4618 mov r0, r3 + 80049e8: f7fe ff70 bl 80038cc mtCOVERAGE_TEST_MARKER(); } /* Place the unblocked task into the appropriate ready list. */ prvAddTaskToReadyList( pxTCB ); - 8003e70: 68bb ldr r3, [r7, #8] - 8003e72: 6ada ldr r2, [r3, #44] ; 0x2c - 8003e74: 4b25 ldr r3, [pc, #148] ; (8003f0c ) - 8003e76: 681b ldr r3, [r3, #0] - 8003e78: 429a cmp r2, r3 - 8003e7a: d903 bls.n 8003e84 - 8003e7c: 68bb ldr r3, [r7, #8] - 8003e7e: 6adb ldr r3, [r3, #44] ; 0x2c - 8003e80: 4a22 ldr r2, [pc, #136] ; (8003f0c ) - 8003e82: 6013 str r3, [r2, #0] - 8003e84: 68bb ldr r3, [r7, #8] - 8003e86: 6ada ldr r2, [r3, #44] ; 0x2c - 8003e88: 4613 mov r3, r2 - 8003e8a: 009b lsls r3, r3, #2 - 8003e8c: 4413 add r3, r2 - 8003e8e: 009b lsls r3, r3, #2 - 8003e90: 4a1f ldr r2, [pc, #124] ; (8003f10 ) - 8003e92: 441a add r2, r3 - 8003e94: 68bb ldr r3, [r7, #8] - 8003e96: 3304 adds r3, #4 - 8003e98: 4619 mov r1, r3 - 8003e9a: 4610 mov r0, r2 - 8003e9c: f7fe fefb bl 8002c96 + 80049ec: 68bb ldr r3, [r7, #8] + 80049ee: 6ada ldr r2, [r3, #44] ; 0x2c + 80049f0: 4b25 ldr r3, [pc, #148] ; (8004a88 ) + 80049f2: 681b ldr r3, [r3, #0] + 80049f4: 429a cmp r2, r3 + 80049f6: d903 bls.n 8004a00 + 80049f8: 68bb ldr r3, [r7, #8] + 80049fa: 6adb ldr r3, [r3, #44] ; 0x2c + 80049fc: 4a22 ldr r2, [pc, #136] ; (8004a88 ) + 80049fe: 6013 str r3, [r2, #0] + 8004a00: 68bb ldr r3, [r7, #8] + 8004a02: 6ada ldr r2, [r3, #44] ; 0x2c + 8004a04: 4613 mov r3, r2 + 8004a06: 009b lsls r3, r3, #2 + 8004a08: 4413 add r3, r2 + 8004a0a: 009b lsls r3, r3, #2 + 8004a0c: 4a1f ldr r2, [pc, #124] ; (8004a8c ) + 8004a0e: 441a add r2, r3 + 8004a10: 68bb ldr r3, [r7, #8] + 8004a12: 3304 adds r3, #4 + 8004a14: 4619 mov r1, r3 + 8004a16: 4610 mov r0, r2 + 8004a18: f7fe fefb bl 8003812 { /* Preemption is on, but a context switch should only be performed if the unblocked task has a priority that is equal to or higher than the currently executing task. */ if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority ) - 8003ea0: 68bb ldr r3, [r7, #8] - 8003ea2: 6ada ldr r2, [r3, #44] ; 0x2c - 8003ea4: 4b1b ldr r3, [pc, #108] ; (8003f14 ) - 8003ea6: 681b ldr r3, [r3, #0] - 8003ea8: 6adb ldr r3, [r3, #44] ; 0x2c - 8003eaa: 429a cmp r2, r3 - 8003eac: d3b8 bcc.n 8003e20 + 8004a1c: 68bb ldr r3, [r7, #8] + 8004a1e: 6ada ldr r2, [r3, #44] ; 0x2c + 8004a20: 4b1b ldr r3, [pc, #108] ; (8004a90 ) + 8004a22: 681b ldr r3, [r3, #0] + 8004a24: 6adb ldr r3, [r3, #44] ; 0x2c + 8004a26: 429a cmp r2, r3 + 8004a28: d3b8 bcc.n 800499c { xSwitchRequired = pdTRUE; - 8003eae: 2301 movs r3, #1 - 8003eb0: 617b str r3, [r7, #20] + 8004a2a: 2301 movs r3, #1 + 8004a2c: 617b str r3, [r7, #20] if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) - 8003eb2: e7b5 b.n 8003e20 + 8004a2e: e7b5 b.n 800499c /* Tasks of equal priority to the currently running task will share processing time (time slice) if preemption is on, and the application writer has not explicitly turned time slicing off. */ #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) { if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 ) - 8003eb4: 4b17 ldr r3, [pc, #92] ; (8003f14 ) - 8003eb6: 681b ldr r3, [r3, #0] - 8003eb8: 6ada ldr r2, [r3, #44] ; 0x2c - 8003eba: 4915 ldr r1, [pc, #84] ; (8003f10 ) - 8003ebc: 4613 mov r3, r2 - 8003ebe: 009b lsls r3, r3, #2 - 8003ec0: 4413 add r3, r2 - 8003ec2: 009b lsls r3, r3, #2 - 8003ec4: 440b add r3, r1 - 8003ec6: 681b ldr r3, [r3, #0] - 8003ec8: 2b01 cmp r3, #1 - 8003eca: d901 bls.n 8003ed0 + 8004a30: 4b17 ldr r3, [pc, #92] ; (8004a90 ) + 8004a32: 681b ldr r3, [r3, #0] + 8004a34: 6ada ldr r2, [r3, #44] ; 0x2c + 8004a36: 4915 ldr r1, [pc, #84] ; (8004a8c ) + 8004a38: 4613 mov r3, r2 + 8004a3a: 009b lsls r3, r3, #2 + 8004a3c: 4413 add r3, r2 + 8004a3e: 009b lsls r3, r3, #2 + 8004a40: 440b add r3, r1 + 8004a42: 681b ldr r3, [r3, #0] + 8004a44: 2b01 cmp r3, #1 + 8004a46: d901 bls.n 8004a4c { xSwitchRequired = pdTRUE; - 8003ecc: 2301 movs r3, #1 - 8003ece: 617b str r3, [r7, #20] + 8004a48: 2301 movs r3, #1 + 8004a4a: 617b str r3, [r7, #20] } #endif /* configUSE_TICK_HOOK */ #if ( configUSE_PREEMPTION == 1 ) { if( xYieldPending != pdFALSE ) - 8003ed0: 4b11 ldr r3, [pc, #68] ; (8003f18 ) - 8003ed2: 681b ldr r3, [r3, #0] - 8003ed4: 2b00 cmp r3, #0 - 8003ed6: d007 beq.n 8003ee8 + 8004a4c: 4b11 ldr r3, [pc, #68] ; (8004a94 ) + 8004a4e: 681b ldr r3, [r3, #0] + 8004a50: 2b00 cmp r3, #0 + 8004a52: d007 beq.n 8004a64 { xSwitchRequired = pdTRUE; - 8003ed8: 2301 movs r3, #1 - 8003eda: 617b str r3, [r7, #20] - 8003edc: e004 b.n 8003ee8 + 8004a54: 2301 movs r3, #1 + 8004a56: 617b str r3, [r7, #20] + 8004a58: e004 b.n 8004a64 } #endif /* configUSE_PREEMPTION */ } else { ++xPendedTicks; - 8003ede: 4b0f ldr r3, [pc, #60] ; (8003f1c ) - 8003ee0: 681b ldr r3, [r3, #0] - 8003ee2: 3301 adds r3, #1 - 8003ee4: 4a0d ldr r2, [pc, #52] ; (8003f1c ) - 8003ee6: 6013 str r3, [r2, #0] + 8004a5a: 4b0f ldr r3, [pc, #60] ; (8004a98 ) + 8004a5c: 681b ldr r3, [r3, #0] + 8004a5e: 3301 adds r3, #1 + 8004a60: 4a0d ldr r2, [pc, #52] ; (8004a98 ) + 8004a62: 6013 str r3, [r2, #0] vApplicationTickHook(); } #endif } return xSwitchRequired; - 8003ee8: 697b ldr r3, [r7, #20] + 8004a64: 697b ldr r3, [r7, #20] } - 8003eea: 4618 mov r0, r3 - 8003eec: 3718 adds r7, #24 - 8003eee: 46bd mov sp, r7 - 8003ef0: bd80 pop {r7, pc} - 8003ef2: bf00 nop - 8003ef4: 20000dbc .word 0x20000dbc - 8003ef8: 20000d98 .word 0x20000d98 - 8003efc: 20000d4c .word 0x20000d4c - 8003f00: 20000d50 .word 0x20000d50 - 8003f04: 20000dac .word 0x20000dac - 8003f08: 20000db4 .word 0x20000db4 - 8003f0c: 20000d9c .word 0x20000d9c - 8003f10: 200008c4 .word 0x200008c4 - 8003f14: 200008c0 .word 0x200008c0 - 8003f18: 20000da8 .word 0x20000da8 - 8003f1c: 20000da4 .word 0x20000da4 + 8004a66: 4618 mov r0, r3 + 8004a68: 3718 adds r7, #24 + 8004a6a: 46bd mov sp, r7 + 8004a6c: bd80 pop {r7, pc} + 8004a6e: bf00 nop + 8004a70: 20000e0c .word 0x20000e0c + 8004a74: 20000de8 .word 0x20000de8 + 8004a78: 20000d9c .word 0x20000d9c + 8004a7c: 20000da0 .word 0x20000da0 + 8004a80: 20000dfc .word 0x20000dfc + 8004a84: 20000e04 .word 0x20000e04 + 8004a88: 20000dec .word 0x20000dec + 8004a8c: 20000914 .word 0x20000914 + 8004a90: 20000910 .word 0x20000910 + 8004a94: 20000df8 .word 0x20000df8 + 8004a98: 20000df4 .word 0x20000df4 -08003f20 : +08004a9c : #endif /* configUSE_APPLICATION_TASK_TAG */ /*-----------------------------------------------------------*/ void vTaskSwitchContext( void ) { - 8003f20: b480 push {r7} - 8003f22: b085 sub sp, #20 - 8003f24: af00 add r7, sp, #0 + 8004a9c: b480 push {r7} + 8004a9e: b085 sub sp, #20 + 8004aa0: af00 add r7, sp, #0 if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE ) - 8003f26: 4b2a ldr r3, [pc, #168] ; (8003fd0 ) - 8003f28: 681b ldr r3, [r3, #0] - 8003f2a: 2b00 cmp r3, #0 - 8003f2c: d003 beq.n 8003f36 + 8004aa2: 4b2a ldr r3, [pc, #168] ; (8004b4c ) + 8004aa4: 681b ldr r3, [r3, #0] + 8004aa6: 2b00 cmp r3, #0 + 8004aa8: d003 beq.n 8004ab2 { /* The scheduler is currently suspended - do not allow a context switch. */ xYieldPending = pdTRUE; - 8003f2e: 4b29 ldr r3, [pc, #164] ; (8003fd4 ) - 8003f30: 2201 movs r2, #1 - 8003f32: 601a str r2, [r3, #0] + 8004aaa: 4b29 ldr r3, [pc, #164] ; (8004b50 ) + 8004aac: 2201 movs r2, #1 + 8004aae: 601a str r2, [r3, #0] for additional information. */ _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); } #endif /* configUSE_NEWLIB_REENTRANT */ } } - 8003f34: e046 b.n 8003fc4 + 8004ab0: e046 b.n 8004b40 xYieldPending = pdFALSE; - 8003f36: 4b27 ldr r3, [pc, #156] ; (8003fd4 ) - 8003f38: 2200 movs r2, #0 - 8003f3a: 601a str r2, [r3, #0] + 8004ab2: 4b27 ldr r3, [pc, #156] ; (8004b50 ) + 8004ab4: 2200 movs r2, #0 + 8004ab6: 601a str r2, [r3, #0] taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8003f3c: 4b26 ldr r3, [pc, #152] ; (8003fd8 ) - 8003f3e: 681b ldr r3, [r3, #0] - 8003f40: 60fb str r3, [r7, #12] - 8003f42: e010 b.n 8003f66 - 8003f44: 68fb ldr r3, [r7, #12] - 8003f46: 2b00 cmp r3, #0 - 8003f48: d10a bne.n 8003f60 + 8004ab8: 4b26 ldr r3, [pc, #152] ; (8004b54 ) + 8004aba: 681b ldr r3, [r3, #0] + 8004abc: 60fb str r3, [r7, #12] + 8004abe: e010 b.n 8004ae2 + 8004ac0: 68fb ldr r3, [r7, #12] + 8004ac2: 2b00 cmp r3, #0 + 8004ac4: d10a bne.n 8004adc __asm volatile - 8003f4a: f04f 0350 mov.w r3, #80 ; 0x50 - 8003f4e: f383 8811 msr BASEPRI, r3 - 8003f52: f3bf 8f6f isb sy - 8003f56: f3bf 8f4f dsb sy - 8003f5a: 607b str r3, [r7, #4] + 8004ac6: f04f 0350 mov.w r3, #80 ; 0x50 + 8004aca: f383 8811 msr BASEPRI, r3 + 8004ace: f3bf 8f6f isb sy + 8004ad2: f3bf 8f4f dsb sy + 8004ad6: 607b str r3, [r7, #4] } - 8003f5c: bf00 nop - 8003f5e: e7fe b.n 8003f5e - 8003f60: 68fb ldr r3, [r7, #12] - 8003f62: 3b01 subs r3, #1 - 8003f64: 60fb str r3, [r7, #12] - 8003f66: 491d ldr r1, [pc, #116] ; (8003fdc ) - 8003f68: 68fa ldr r2, [r7, #12] - 8003f6a: 4613 mov r3, r2 - 8003f6c: 009b lsls r3, r3, #2 - 8003f6e: 4413 add r3, r2 - 8003f70: 009b lsls r3, r3, #2 - 8003f72: 440b add r3, r1 - 8003f74: 681b ldr r3, [r3, #0] - 8003f76: 2b00 cmp r3, #0 - 8003f78: d0e4 beq.n 8003f44 - 8003f7a: 68fa ldr r2, [r7, #12] - 8003f7c: 4613 mov r3, r2 - 8003f7e: 009b lsls r3, r3, #2 - 8003f80: 4413 add r3, r2 - 8003f82: 009b lsls r3, r3, #2 - 8003f84: 4a15 ldr r2, [pc, #84] ; (8003fdc ) - 8003f86: 4413 add r3, r2 - 8003f88: 60bb str r3, [r7, #8] - 8003f8a: 68bb ldr r3, [r7, #8] - 8003f8c: 685b ldr r3, [r3, #4] - 8003f8e: 685a ldr r2, [r3, #4] - 8003f90: 68bb ldr r3, [r7, #8] - 8003f92: 605a str r2, [r3, #4] - 8003f94: 68bb ldr r3, [r7, #8] - 8003f96: 685a ldr r2, [r3, #4] - 8003f98: 68bb ldr r3, [r7, #8] - 8003f9a: 3308 adds r3, #8 - 8003f9c: 429a cmp r2, r3 - 8003f9e: d104 bne.n 8003faa - 8003fa0: 68bb ldr r3, [r7, #8] - 8003fa2: 685b ldr r3, [r3, #4] - 8003fa4: 685a ldr r2, [r3, #4] - 8003fa6: 68bb ldr r3, [r7, #8] - 8003fa8: 605a str r2, [r3, #4] - 8003faa: 68bb ldr r3, [r7, #8] - 8003fac: 685b ldr r3, [r3, #4] - 8003fae: 68db ldr r3, [r3, #12] - 8003fb0: 4a0b ldr r2, [pc, #44] ; (8003fe0 ) - 8003fb2: 6013 str r3, [r2, #0] - 8003fb4: 4a08 ldr r2, [pc, #32] ; (8003fd8 ) - 8003fb6: 68fb ldr r3, [r7, #12] - 8003fb8: 6013 str r3, [r2, #0] + 8004ad8: bf00 nop + 8004ada: e7fe b.n 8004ada + 8004adc: 68fb ldr r3, [r7, #12] + 8004ade: 3b01 subs r3, #1 + 8004ae0: 60fb str r3, [r7, #12] + 8004ae2: 491d ldr r1, [pc, #116] ; (8004b58 ) + 8004ae4: 68fa ldr r2, [r7, #12] + 8004ae6: 4613 mov r3, r2 + 8004ae8: 009b lsls r3, r3, #2 + 8004aea: 4413 add r3, r2 + 8004aec: 009b lsls r3, r3, #2 + 8004aee: 440b add r3, r1 + 8004af0: 681b ldr r3, [r3, #0] + 8004af2: 2b00 cmp r3, #0 + 8004af4: d0e4 beq.n 8004ac0 + 8004af6: 68fa ldr r2, [r7, #12] + 8004af8: 4613 mov r3, r2 + 8004afa: 009b lsls r3, r3, #2 + 8004afc: 4413 add r3, r2 + 8004afe: 009b lsls r3, r3, #2 + 8004b00: 4a15 ldr r2, [pc, #84] ; (8004b58 ) + 8004b02: 4413 add r3, r2 + 8004b04: 60bb str r3, [r7, #8] + 8004b06: 68bb ldr r3, [r7, #8] + 8004b08: 685b ldr r3, [r3, #4] + 8004b0a: 685a ldr r2, [r3, #4] + 8004b0c: 68bb ldr r3, [r7, #8] + 8004b0e: 605a str r2, [r3, #4] + 8004b10: 68bb ldr r3, [r7, #8] + 8004b12: 685a ldr r2, [r3, #4] + 8004b14: 68bb ldr r3, [r7, #8] + 8004b16: 3308 adds r3, #8 + 8004b18: 429a cmp r2, r3 + 8004b1a: d104 bne.n 8004b26 + 8004b1c: 68bb ldr r3, [r7, #8] + 8004b1e: 685b ldr r3, [r3, #4] + 8004b20: 685a ldr r2, [r3, #4] + 8004b22: 68bb ldr r3, [r7, #8] + 8004b24: 605a str r2, [r3, #4] + 8004b26: 68bb ldr r3, [r7, #8] + 8004b28: 685b ldr r3, [r3, #4] + 8004b2a: 68db ldr r3, [r3, #12] + 8004b2c: 4a0b ldr r2, [pc, #44] ; (8004b5c ) + 8004b2e: 6013 str r3, [r2, #0] + 8004b30: 4a08 ldr r2, [pc, #32] ; (8004b54 ) + 8004b32: 68fb ldr r3, [r7, #12] + 8004b34: 6013 str r3, [r2, #0] _impure_ptr = &( pxCurrentTCB->xNewLib_reent ); - 8003fba: 4b09 ldr r3, [pc, #36] ; (8003fe0 ) - 8003fbc: 681b ldr r3, [r3, #0] - 8003fbe: 3354 adds r3, #84 ; 0x54 - 8003fc0: 4a08 ldr r2, [pc, #32] ; (8003fe4 ) - 8003fc2: 6013 str r3, [r2, #0] + 8004b36: 4b09 ldr r3, [pc, #36] ; (8004b5c ) + 8004b38: 681b ldr r3, [r3, #0] + 8004b3a: 3354 adds r3, #84 ; 0x54 + 8004b3c: 4a08 ldr r2, [pc, #32] ; (8004b60 ) + 8004b3e: 6013 str r3, [r2, #0] } - 8003fc4: bf00 nop - 8003fc6: 3714 adds r7, #20 - 8003fc8: 46bd mov sp, r7 - 8003fca: f85d 7b04 ldr.w r7, [sp], #4 - 8003fce: 4770 bx lr - 8003fd0: 20000dbc .word 0x20000dbc - 8003fd4: 20000da8 .word 0x20000da8 - 8003fd8: 20000d9c .word 0x20000d9c - 8003fdc: 200008c4 .word 0x200008c4 - 8003fe0: 200008c0 .word 0x200008c0 - 8003fe4: 2000005c .word 0x2000005c + 8004b40: bf00 nop + 8004b42: 3714 adds r7, #20 + 8004b44: 46bd mov sp, r7 + 8004b46: f85d 7b04 ldr.w r7, [sp], #4 + 8004b4a: 4770 bx lr + 8004b4c: 20000e0c .word 0x20000e0c + 8004b50: 20000df8 .word 0x20000df8 + 8004b54: 20000dec .word 0x20000dec + 8004b58: 20000914 .word 0x20000914 + 8004b5c: 20000910 .word 0x20000910 + 8004b60: 2000005c .word 0x2000005c -08003fe8 : +08004b64 : /*-----------------------------------------------------------*/ void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) { - 8003fe8: b580 push {r7, lr} - 8003fea: b084 sub sp, #16 - 8003fec: af00 add r7, sp, #0 - 8003fee: 6078 str r0, [r7, #4] - 8003ff0: 6039 str r1, [r7, #0] + 8004b64: b580 push {r7, lr} + 8004b66: b084 sub sp, #16 + 8004b68: af00 add r7, sp, #0 + 8004b6a: 6078 str r0, [r7, #4] + 8004b6c: 6039 str r1, [r7, #0] configASSERT( pxEventList ); - 8003ff2: 687b ldr r3, [r7, #4] - 8003ff4: 2b00 cmp r3, #0 - 8003ff6: d10a bne.n 800400e + 8004b6e: 687b ldr r3, [r7, #4] + 8004b70: 2b00 cmp r3, #0 + 8004b72: d10a bne.n 8004b8a __asm volatile - 8003ff8: f04f 0350 mov.w r3, #80 ; 0x50 - 8003ffc: f383 8811 msr BASEPRI, r3 - 8004000: f3bf 8f6f isb sy - 8004004: f3bf 8f4f dsb sy - 8004008: 60fb str r3, [r7, #12] + 8004b74: f04f 0350 mov.w r3, #80 ; 0x50 + 8004b78: f383 8811 msr BASEPRI, r3 + 8004b7c: f3bf 8f6f isb sy + 8004b80: f3bf 8f4f dsb sy + 8004b84: 60fb str r3, [r7, #12] } - 800400a: bf00 nop - 800400c: e7fe b.n 800400c + 8004b86: bf00 nop + 8004b88: e7fe b.n 8004b88 /* Place the event list item of the TCB in the appropriate event list. This is placed in the list in priority order so the highest priority task is the first to be woken by the event. The queue that contains the event list is locked, preventing simultaneous access from interrupts. */ vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) ); - 800400e: 4b07 ldr r3, [pc, #28] ; (800402c ) - 8004010: 681b ldr r3, [r3, #0] - 8004012: 3318 adds r3, #24 - 8004014: 4619 mov r1, r3 - 8004016: 6878 ldr r0, [r7, #4] - 8004018: f7fe fe61 bl 8002cde + 8004b8a: 4b07 ldr r3, [pc, #28] ; (8004ba8 ) + 8004b8c: 681b ldr r3, [r3, #0] + 8004b8e: 3318 adds r3, #24 + 8004b90: 4619 mov r1, r3 + 8004b92: 6878 ldr r0, [r7, #4] + 8004b94: f7fe fe61 bl 800385a prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE ); - 800401c: 2101 movs r1, #1 - 800401e: 6838 ldr r0, [r7, #0] - 8004020: f000 fa80 bl 8004524 + 8004b98: 2101 movs r1, #1 + 8004b9a: 6838 ldr r0, [r7, #0] + 8004b9c: f000 fa80 bl 80050a0 } - 8004024: bf00 nop - 8004026: 3710 adds r7, #16 - 8004028: 46bd mov sp, r7 - 800402a: bd80 pop {r7, pc} - 800402c: 200008c0 .word 0x200008c0 + 8004ba0: bf00 nop + 8004ba2: 3710 adds r7, #16 + 8004ba4: 46bd mov sp, r7 + 8004ba6: bd80 pop {r7, pc} + 8004ba8: 20000910 .word 0x20000910 -08004030 : +08004bac : /*-----------------------------------------------------------*/ #if( configUSE_TIMERS == 1 ) void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) { - 8004030: b580 push {r7, lr} - 8004032: b086 sub sp, #24 - 8004034: af00 add r7, sp, #0 - 8004036: 60f8 str r0, [r7, #12] - 8004038: 60b9 str r1, [r7, #8] - 800403a: 607a str r2, [r7, #4] + 8004bac: b580 push {r7, lr} + 8004bae: b086 sub sp, #24 + 8004bb0: af00 add r7, sp, #0 + 8004bb2: 60f8 str r0, [r7, #12] + 8004bb4: 60b9 str r1, [r7, #8] + 8004bb6: 607a str r2, [r7, #4] configASSERT( pxEventList ); - 800403c: 68fb ldr r3, [r7, #12] - 800403e: 2b00 cmp r3, #0 - 8004040: d10a bne.n 8004058 + 8004bb8: 68fb ldr r3, [r7, #12] + 8004bba: 2b00 cmp r3, #0 + 8004bbc: d10a bne.n 8004bd4 __asm volatile - 8004042: f04f 0350 mov.w r3, #80 ; 0x50 - 8004046: f383 8811 msr BASEPRI, r3 - 800404a: f3bf 8f6f isb sy - 800404e: f3bf 8f4f dsb sy - 8004052: 617b str r3, [r7, #20] + 8004bbe: f04f 0350 mov.w r3, #80 ; 0x50 + 8004bc2: f383 8811 msr BASEPRI, r3 + 8004bc6: f3bf 8f6f isb sy + 8004bca: f3bf 8f4f dsb sy + 8004bce: 617b str r3, [r7, #20] } - 8004054: bf00 nop - 8004056: e7fe b.n 8004056 + 8004bd0: bf00 nop + 8004bd2: e7fe b.n 8004bd2 /* Place the event list item of the TCB in the appropriate event list. In this case it is assume that this is the only task that is going to be waiting on this event list, so the faster vListInsertEnd() function can be used in place of vListInsert. */ vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) ); - 8004058: 4b0a ldr r3, [pc, #40] ; (8004084 ) - 800405a: 681b ldr r3, [r3, #0] - 800405c: 3318 adds r3, #24 - 800405e: 4619 mov r1, r3 - 8004060: 68f8 ldr r0, [r7, #12] - 8004062: f7fe fe18 bl 8002c96 + 8004bd4: 4b0a ldr r3, [pc, #40] ; (8004c00 ) + 8004bd6: 681b ldr r3, [r3, #0] + 8004bd8: 3318 adds r3, #24 + 8004bda: 4619 mov r1, r3 + 8004bdc: 68f8 ldr r0, [r7, #12] + 8004bde: f7fe fe18 bl 8003812 /* If the task should block indefinitely then set the block time to a value that will be recognised as an indefinite delay inside the prvAddCurrentTaskToDelayedList() function. */ if( xWaitIndefinitely != pdFALSE ) - 8004066: 687b ldr r3, [r7, #4] - 8004068: 2b00 cmp r3, #0 - 800406a: d002 beq.n 8004072 + 8004be2: 687b ldr r3, [r7, #4] + 8004be4: 2b00 cmp r3, #0 + 8004be6: d002 beq.n 8004bee { xTicksToWait = portMAX_DELAY; - 800406c: f04f 33ff mov.w r3, #4294967295 - 8004070: 60bb str r3, [r7, #8] + 8004be8: f04f 33ff mov.w r3, #4294967295 + 8004bec: 60bb str r3, [r7, #8] } traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) ); prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely ); - 8004072: 6879 ldr r1, [r7, #4] - 8004074: 68b8 ldr r0, [r7, #8] - 8004076: f000 fa55 bl 8004524 + 8004bee: 6879 ldr r1, [r7, #4] + 8004bf0: 68b8 ldr r0, [r7, #8] + 8004bf2: f000 fa55 bl 80050a0 } - 800407a: bf00 nop - 800407c: 3718 adds r7, #24 - 800407e: 46bd mov sp, r7 - 8004080: bd80 pop {r7, pc} - 8004082: bf00 nop - 8004084: 200008c0 .word 0x200008c0 + 8004bf6: bf00 nop + 8004bf8: 3718 adds r7, #24 + 8004bfa: 46bd mov sp, r7 + 8004bfc: bd80 pop {r7, pc} + 8004bfe: bf00 nop + 8004c00: 20000910 .word 0x20000910 -08004088 : +08004c04 : #endif /* configUSE_TIMERS */ /*-----------------------------------------------------------*/ BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) { - 8004088: b580 push {r7, lr} - 800408a: b086 sub sp, #24 - 800408c: af00 add r7, sp, #0 - 800408e: 6078 str r0, [r7, #4] + 8004c04: b580 push {r7, lr} + 8004c06: b086 sub sp, #24 + 8004c08: af00 add r7, sp, #0 + 8004c0a: 6078 str r0, [r7, #4] get called - the lock count on the queue will get modified instead. This means exclusive access to the event list is guaranteed here. This function assumes that a check has already been made to ensure that pxEventList is not empty. */ pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8004090: 687b ldr r3, [r7, #4] - 8004092: 68db ldr r3, [r3, #12] - 8004094: 68db ldr r3, [r3, #12] - 8004096: 613b str r3, [r7, #16] + 8004c0c: 687b ldr r3, [r7, #4] + 8004c0e: 68db ldr r3, [r3, #12] + 8004c10: 68db ldr r3, [r3, #12] + 8004c12: 613b str r3, [r7, #16] configASSERT( pxUnblockedTCB ); - 8004098: 693b ldr r3, [r7, #16] - 800409a: 2b00 cmp r3, #0 - 800409c: d10a bne.n 80040b4 + 8004c14: 693b ldr r3, [r7, #16] + 8004c16: 2b00 cmp r3, #0 + 8004c18: d10a bne.n 8004c30 __asm volatile - 800409e: f04f 0350 mov.w r3, #80 ; 0x50 - 80040a2: f383 8811 msr BASEPRI, r3 - 80040a6: f3bf 8f6f isb sy - 80040aa: f3bf 8f4f dsb sy - 80040ae: 60fb str r3, [r7, #12] + 8004c1a: f04f 0350 mov.w r3, #80 ; 0x50 + 8004c1e: f383 8811 msr BASEPRI, r3 + 8004c22: f3bf 8f6f isb sy + 8004c26: f3bf 8f4f dsb sy + 8004c2a: 60fb str r3, [r7, #12] } - 80040b0: bf00 nop - 80040b2: e7fe b.n 80040b2 + 8004c2c: bf00 nop + 8004c2e: e7fe b.n 8004c2e ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) ); - 80040b4: 693b ldr r3, [r7, #16] - 80040b6: 3318 adds r3, #24 - 80040b8: 4618 mov r0, r3 - 80040ba: f7fe fe49 bl 8002d50 + 8004c30: 693b ldr r3, [r7, #16] + 8004c32: 3318 adds r3, #24 + 8004c34: 4618 mov r0, r3 + 8004c36: f7fe fe49 bl 80038cc if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) - 80040be: 4b1e ldr r3, [pc, #120] ; (8004138 ) - 80040c0: 681b ldr r3, [r3, #0] - 80040c2: 2b00 cmp r3, #0 - 80040c4: d11d bne.n 8004102 + 8004c3a: 4b1e ldr r3, [pc, #120] ; (8004cb4 ) + 8004c3c: 681b ldr r3, [r3, #0] + 8004c3e: 2b00 cmp r3, #0 + 8004c40: d11d bne.n 8004c7e { ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) ); - 80040c6: 693b ldr r3, [r7, #16] - 80040c8: 3304 adds r3, #4 - 80040ca: 4618 mov r0, r3 - 80040cc: f7fe fe40 bl 8002d50 + 8004c42: 693b ldr r3, [r7, #16] + 8004c44: 3304 adds r3, #4 + 8004c46: 4618 mov r0, r3 + 8004c48: f7fe fe40 bl 80038cc prvAddTaskToReadyList( pxUnblockedTCB ); - 80040d0: 693b ldr r3, [r7, #16] - 80040d2: 6ada ldr r2, [r3, #44] ; 0x2c - 80040d4: 4b19 ldr r3, [pc, #100] ; (800413c ) - 80040d6: 681b ldr r3, [r3, #0] - 80040d8: 429a cmp r2, r3 - 80040da: d903 bls.n 80040e4 - 80040dc: 693b ldr r3, [r7, #16] - 80040de: 6adb ldr r3, [r3, #44] ; 0x2c - 80040e0: 4a16 ldr r2, [pc, #88] ; (800413c ) - 80040e2: 6013 str r3, [r2, #0] - 80040e4: 693b ldr r3, [r7, #16] - 80040e6: 6ada ldr r2, [r3, #44] ; 0x2c - 80040e8: 4613 mov r3, r2 - 80040ea: 009b lsls r3, r3, #2 - 80040ec: 4413 add r3, r2 - 80040ee: 009b lsls r3, r3, #2 - 80040f0: 4a13 ldr r2, [pc, #76] ; (8004140 ) - 80040f2: 441a add r2, r3 - 80040f4: 693b ldr r3, [r7, #16] - 80040f6: 3304 adds r3, #4 - 80040f8: 4619 mov r1, r3 - 80040fa: 4610 mov r0, r2 - 80040fc: f7fe fdcb bl 8002c96 - 8004100: e005 b.n 800410e + 8004c4c: 693b ldr r3, [r7, #16] + 8004c4e: 6ada ldr r2, [r3, #44] ; 0x2c + 8004c50: 4b19 ldr r3, [pc, #100] ; (8004cb8 ) + 8004c52: 681b ldr r3, [r3, #0] + 8004c54: 429a cmp r2, r3 + 8004c56: d903 bls.n 8004c60 + 8004c58: 693b ldr r3, [r7, #16] + 8004c5a: 6adb ldr r3, [r3, #44] ; 0x2c + 8004c5c: 4a16 ldr r2, [pc, #88] ; (8004cb8 ) + 8004c5e: 6013 str r3, [r2, #0] + 8004c60: 693b ldr r3, [r7, #16] + 8004c62: 6ada ldr r2, [r3, #44] ; 0x2c + 8004c64: 4613 mov r3, r2 + 8004c66: 009b lsls r3, r3, #2 + 8004c68: 4413 add r3, r2 + 8004c6a: 009b lsls r3, r3, #2 + 8004c6c: 4a13 ldr r2, [pc, #76] ; (8004cbc ) + 8004c6e: 441a add r2, r3 + 8004c70: 693b ldr r3, [r7, #16] + 8004c72: 3304 adds r3, #4 + 8004c74: 4619 mov r1, r3 + 8004c76: 4610 mov r0, r2 + 8004c78: f7fe fdcb bl 8003812 + 8004c7c: e005 b.n 8004c8a } else { /* The delayed and ready lists cannot be accessed, so hold this task pending until the scheduler is resumed. */ vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) ); - 8004102: 693b ldr r3, [r7, #16] - 8004104: 3318 adds r3, #24 - 8004106: 4619 mov r1, r3 - 8004108: 480e ldr r0, [pc, #56] ; (8004144 ) - 800410a: f7fe fdc4 bl 8002c96 + 8004c7e: 693b ldr r3, [r7, #16] + 8004c80: 3318 adds r3, #24 + 8004c82: 4619 mov r1, r3 + 8004c84: 480e ldr r0, [pc, #56] ; (8004cc0 ) + 8004c86: f7fe fdc4 bl 8003812 } if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority ) - 800410e: 693b ldr r3, [r7, #16] - 8004110: 6ada ldr r2, [r3, #44] ; 0x2c - 8004112: 4b0d ldr r3, [pc, #52] ; (8004148 ) - 8004114: 681b ldr r3, [r3, #0] - 8004116: 6adb ldr r3, [r3, #44] ; 0x2c - 8004118: 429a cmp r2, r3 - 800411a: d905 bls.n 8004128 + 8004c8a: 693b ldr r3, [r7, #16] + 8004c8c: 6ada ldr r2, [r3, #44] ; 0x2c + 8004c8e: 4b0d ldr r3, [pc, #52] ; (8004cc4 ) + 8004c90: 681b ldr r3, [r3, #0] + 8004c92: 6adb ldr r3, [r3, #44] ; 0x2c + 8004c94: 429a cmp r2, r3 + 8004c96: d905 bls.n 8004ca4 { /* Return true if the task removed from the event list has a higher priority than the calling task. This allows the calling task to know if it should force a context switch now. */ xReturn = pdTRUE; - 800411c: 2301 movs r3, #1 - 800411e: 617b str r3, [r7, #20] + 8004c98: 2301 movs r3, #1 + 8004c9a: 617b str r3, [r7, #20] /* Mark that a yield is pending in case the user is not using the "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */ xYieldPending = pdTRUE; - 8004120: 4b0a ldr r3, [pc, #40] ; (800414c ) - 8004122: 2201 movs r2, #1 - 8004124: 601a str r2, [r3, #0] - 8004126: e001 b.n 800412c + 8004c9c: 4b0a ldr r3, [pc, #40] ; (8004cc8 ) + 8004c9e: 2201 movs r2, #1 + 8004ca0: 601a str r2, [r3, #0] + 8004ca2: e001 b.n 8004ca8 } else { xReturn = pdFALSE; - 8004128: 2300 movs r3, #0 - 800412a: 617b str r3, [r7, #20] + 8004ca4: 2300 movs r3, #0 + 8004ca6: 617b str r3, [r7, #20] } return xReturn; - 800412c: 697b ldr r3, [r7, #20] + 8004ca8: 697b ldr r3, [r7, #20] } - 800412e: 4618 mov r0, r3 - 8004130: 3718 adds r7, #24 - 8004132: 46bd mov sp, r7 - 8004134: bd80 pop {r7, pc} - 8004136: bf00 nop - 8004138: 20000dbc .word 0x20000dbc - 800413c: 20000d9c .word 0x20000d9c - 8004140: 200008c4 .word 0x200008c4 - 8004144: 20000d54 .word 0x20000d54 - 8004148: 200008c0 .word 0x200008c0 - 800414c: 20000da8 .word 0x20000da8 + 8004caa: 4618 mov r0, r3 + 8004cac: 3718 adds r7, #24 + 8004cae: 46bd mov sp, r7 + 8004cb0: bd80 pop {r7, pc} + 8004cb2: bf00 nop + 8004cb4: 20000e0c .word 0x20000e0c + 8004cb8: 20000dec .word 0x20000dec + 8004cbc: 20000914 .word 0x20000914 + 8004cc0: 20000da4 .word 0x20000da4 + 8004cc4: 20000910 .word 0x20000910 + 8004cc8: 20000df8 .word 0x20000df8 -08004150 : +08004ccc : taskEXIT_CRITICAL(); } /*-----------------------------------------------------------*/ void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) { - 8004150: b480 push {r7} - 8004152: b083 sub sp, #12 - 8004154: af00 add r7, sp, #0 - 8004156: 6078 str r0, [r7, #4] + 8004ccc: b480 push {r7} + 8004cce: b083 sub sp, #12 + 8004cd0: af00 add r7, sp, #0 + 8004cd2: 6078 str r0, [r7, #4] /* For internal use only as it does not use a critical section. */ pxTimeOut->xOverflowCount = xNumOfOverflows; - 8004158: 4b06 ldr r3, [pc, #24] ; (8004174 ) - 800415a: 681a ldr r2, [r3, #0] - 800415c: 687b ldr r3, [r7, #4] - 800415e: 601a str r2, [r3, #0] + 8004cd4: 4b06 ldr r3, [pc, #24] ; (8004cf0 ) + 8004cd6: 681a ldr r2, [r3, #0] + 8004cd8: 687b ldr r3, [r7, #4] + 8004cda: 601a str r2, [r3, #0] pxTimeOut->xTimeOnEntering = xTickCount; - 8004160: 4b05 ldr r3, [pc, #20] ; (8004178 ) - 8004162: 681a ldr r2, [r3, #0] - 8004164: 687b ldr r3, [r7, #4] - 8004166: 605a str r2, [r3, #4] + 8004cdc: 4b05 ldr r3, [pc, #20] ; (8004cf4 ) + 8004cde: 681a ldr r2, [r3, #0] + 8004ce0: 687b ldr r3, [r7, #4] + 8004ce2: 605a str r2, [r3, #4] } - 8004168: bf00 nop - 800416a: 370c adds r7, #12 - 800416c: 46bd mov sp, r7 - 800416e: f85d 7b04 ldr.w r7, [sp], #4 - 8004172: 4770 bx lr - 8004174: 20000dac .word 0x20000dac - 8004178: 20000d98 .word 0x20000d98 + 8004ce4: bf00 nop + 8004ce6: 370c adds r7, #12 + 8004ce8: 46bd mov sp, r7 + 8004cea: f85d 7b04 ldr.w r7, [sp], #4 + 8004cee: 4770 bx lr + 8004cf0: 20000dfc .word 0x20000dfc + 8004cf4: 20000de8 .word 0x20000de8 -0800417c : +08004cf8 : /*-----------------------------------------------------------*/ BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) { - 800417c: b580 push {r7, lr} - 800417e: b088 sub sp, #32 - 8004180: af00 add r7, sp, #0 - 8004182: 6078 str r0, [r7, #4] - 8004184: 6039 str r1, [r7, #0] + 8004cf8: b580 push {r7, lr} + 8004cfa: b088 sub sp, #32 + 8004cfc: af00 add r7, sp, #0 + 8004cfe: 6078 str r0, [r7, #4] + 8004d00: 6039 str r1, [r7, #0] BaseType_t xReturn; configASSERT( pxTimeOut ); - 8004186: 687b ldr r3, [r7, #4] - 8004188: 2b00 cmp r3, #0 - 800418a: d10a bne.n 80041a2 + 8004d02: 687b ldr r3, [r7, #4] + 8004d04: 2b00 cmp r3, #0 + 8004d06: d10a bne.n 8004d1e __asm volatile - 800418c: f04f 0350 mov.w r3, #80 ; 0x50 - 8004190: f383 8811 msr BASEPRI, r3 - 8004194: f3bf 8f6f isb sy - 8004198: f3bf 8f4f dsb sy - 800419c: 613b str r3, [r7, #16] + 8004d08: f04f 0350 mov.w r3, #80 ; 0x50 + 8004d0c: f383 8811 msr BASEPRI, r3 + 8004d10: f3bf 8f6f isb sy + 8004d14: f3bf 8f4f dsb sy + 8004d18: 613b str r3, [r7, #16] } - 800419e: bf00 nop - 80041a0: e7fe b.n 80041a0 + 8004d1a: bf00 nop + 8004d1c: e7fe b.n 8004d1c configASSERT( pxTicksToWait ); - 80041a2: 683b ldr r3, [r7, #0] - 80041a4: 2b00 cmp r3, #0 - 80041a6: d10a bne.n 80041be + 8004d1e: 683b ldr r3, [r7, #0] + 8004d20: 2b00 cmp r3, #0 + 8004d22: d10a bne.n 8004d3a __asm volatile - 80041a8: f04f 0350 mov.w r3, #80 ; 0x50 - 80041ac: f383 8811 msr BASEPRI, r3 - 80041b0: f3bf 8f6f isb sy - 80041b4: f3bf 8f4f dsb sy - 80041b8: 60fb str r3, [r7, #12] + 8004d24: f04f 0350 mov.w r3, #80 ; 0x50 + 8004d28: f383 8811 msr BASEPRI, r3 + 8004d2c: f3bf 8f6f isb sy + 8004d30: f3bf 8f4f dsb sy + 8004d34: 60fb str r3, [r7, #12] } - 80041ba: bf00 nop - 80041bc: e7fe b.n 80041bc + 8004d36: bf00 nop + 8004d38: e7fe b.n 8004d38 taskENTER_CRITICAL(); - 80041be: f000 fe81 bl 8004ec4 + 8004d3a: f000 fe83 bl 8005a44 { /* Minor optimisation. The tick count cannot change in this block. */ const TickType_t xConstTickCount = xTickCount; - 80041c2: 4b1d ldr r3, [pc, #116] ; (8004238 ) - 80041c4: 681b ldr r3, [r3, #0] - 80041c6: 61bb str r3, [r7, #24] + 8004d3e: 4b1d ldr r3, [pc, #116] ; (8004db4 ) + 8004d40: 681b ldr r3, [r3, #0] + 8004d42: 61bb str r3, [r7, #24] const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering; - 80041c8: 687b ldr r3, [r7, #4] - 80041ca: 685b ldr r3, [r3, #4] - 80041cc: 69ba ldr r2, [r7, #24] - 80041ce: 1ad3 subs r3, r2, r3 - 80041d0: 617b str r3, [r7, #20] + 8004d44: 687b ldr r3, [r7, #4] + 8004d46: 685b ldr r3, [r3, #4] + 8004d48: 69ba ldr r2, [r7, #24] + 8004d4a: 1ad3 subs r3, r2, r3 + 8004d4c: 617b str r3, [r7, #20] } else #endif #if ( INCLUDE_vTaskSuspend == 1 ) if( *pxTicksToWait == portMAX_DELAY ) - 80041d2: 683b ldr r3, [r7, #0] - 80041d4: 681b ldr r3, [r3, #0] - 80041d6: f1b3 3fff cmp.w r3, #4294967295 - 80041da: d102 bne.n 80041e2 + 8004d4e: 683b ldr r3, [r7, #0] + 8004d50: 681b ldr r3, [r3, #0] + 8004d52: f1b3 3fff cmp.w r3, #4294967295 + 8004d56: d102 bne.n 8004d5e { /* If INCLUDE_vTaskSuspend is set to 1 and the block time specified is the maximum block time then the task should block indefinitely, and therefore never time out. */ xReturn = pdFALSE; - 80041dc: 2300 movs r3, #0 - 80041de: 61fb str r3, [r7, #28] - 80041e0: e023 b.n 800422a + 8004d58: 2300 movs r3, #0 + 8004d5a: 61fb str r3, [r7, #28] + 8004d5c: e023 b.n 8004da6 } else #endif if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */ - 80041e2: 687b ldr r3, [r7, #4] - 80041e4: 681a ldr r2, [r3, #0] - 80041e6: 4b15 ldr r3, [pc, #84] ; (800423c ) - 80041e8: 681b ldr r3, [r3, #0] - 80041ea: 429a cmp r2, r3 - 80041ec: d007 beq.n 80041fe - 80041ee: 687b ldr r3, [r7, #4] - 80041f0: 685b ldr r3, [r3, #4] - 80041f2: 69ba ldr r2, [r7, #24] - 80041f4: 429a cmp r2, r3 - 80041f6: d302 bcc.n 80041fe + 8004d5e: 687b ldr r3, [r7, #4] + 8004d60: 681a ldr r2, [r3, #0] + 8004d62: 4b15 ldr r3, [pc, #84] ; (8004db8 ) + 8004d64: 681b ldr r3, [r3, #0] + 8004d66: 429a cmp r2, r3 + 8004d68: d007 beq.n 8004d7a + 8004d6a: 687b ldr r3, [r7, #4] + 8004d6c: 685b ldr r3, [r3, #4] + 8004d6e: 69ba ldr r2, [r7, #24] + 8004d70: 429a cmp r2, r3 + 8004d72: d302 bcc.n 8004d7a /* The tick count is greater than the time at which vTaskSetTimeout() was called, but has also overflowed since vTaskSetTimeOut() was called. It must have wrapped all the way around and gone past again. This passed since vTaskSetTimeout() was called. */ xReturn = pdTRUE; - 80041f8: 2301 movs r3, #1 - 80041fa: 61fb str r3, [r7, #28] - 80041fc: e015 b.n 800422a + 8004d74: 2301 movs r3, #1 + 8004d76: 61fb str r3, [r7, #28] + 8004d78: e015 b.n 8004da6 } else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */ - 80041fe: 683b ldr r3, [r7, #0] - 8004200: 681b ldr r3, [r3, #0] - 8004202: 697a ldr r2, [r7, #20] - 8004204: 429a cmp r2, r3 - 8004206: d20b bcs.n 8004220 + 8004d7a: 683b ldr r3, [r7, #0] + 8004d7c: 681b ldr r3, [r3, #0] + 8004d7e: 697a ldr r2, [r7, #20] + 8004d80: 429a cmp r2, r3 + 8004d82: d20b bcs.n 8004d9c { /* Not a genuine timeout. Adjust parameters for time remaining. */ *pxTicksToWait -= xElapsedTime; - 8004208: 683b ldr r3, [r7, #0] - 800420a: 681a ldr r2, [r3, #0] - 800420c: 697b ldr r3, [r7, #20] - 800420e: 1ad2 subs r2, r2, r3 - 8004210: 683b ldr r3, [r7, #0] - 8004212: 601a str r2, [r3, #0] + 8004d84: 683b ldr r3, [r7, #0] + 8004d86: 681a ldr r2, [r3, #0] + 8004d88: 697b ldr r3, [r7, #20] + 8004d8a: 1ad2 subs r2, r2, r3 + 8004d8c: 683b ldr r3, [r7, #0] + 8004d8e: 601a str r2, [r3, #0] vTaskInternalSetTimeOutState( pxTimeOut ); - 8004214: 6878 ldr r0, [r7, #4] - 8004216: f7ff ff9b bl 8004150 + 8004d90: 6878 ldr r0, [r7, #4] + 8004d92: f7ff ff9b bl 8004ccc xReturn = pdFALSE; - 800421a: 2300 movs r3, #0 - 800421c: 61fb str r3, [r7, #28] - 800421e: e004 b.n 800422a + 8004d96: 2300 movs r3, #0 + 8004d98: 61fb str r3, [r7, #28] + 8004d9a: e004 b.n 8004da6 } else { *pxTicksToWait = 0; - 8004220: 683b ldr r3, [r7, #0] - 8004222: 2200 movs r2, #0 - 8004224: 601a str r2, [r3, #0] + 8004d9c: 683b ldr r3, [r7, #0] + 8004d9e: 2200 movs r2, #0 + 8004da0: 601a str r2, [r3, #0] xReturn = pdTRUE; - 8004226: 2301 movs r3, #1 - 8004228: 61fb str r3, [r7, #28] + 8004da2: 2301 movs r3, #1 + 8004da4: 61fb str r3, [r7, #28] } } taskEXIT_CRITICAL(); - 800422a: f000 fe7b bl 8004f24 + 8004da6: f000 fe7d bl 8005aa4 return xReturn; - 800422e: 69fb ldr r3, [r7, #28] + 8004daa: 69fb ldr r3, [r7, #28] } - 8004230: 4618 mov r0, r3 - 8004232: 3720 adds r7, #32 - 8004234: 46bd mov sp, r7 - 8004236: bd80 pop {r7, pc} - 8004238: 20000d98 .word 0x20000d98 - 800423c: 20000dac .word 0x20000dac + 8004dac: 4618 mov r0, r3 + 8004dae: 3720 adds r7, #32 + 8004db0: 46bd mov sp, r7 + 8004db2: bd80 pop {r7, pc} + 8004db4: 20000de8 .word 0x20000de8 + 8004db8: 20000dfc .word 0x20000dfc -08004240 : +08004dbc : /*-----------------------------------------------------------*/ void vTaskMissedYield( void ) { - 8004240: b480 push {r7} - 8004242: af00 add r7, sp, #0 + 8004dbc: b480 push {r7} + 8004dbe: af00 add r7, sp, #0 xYieldPending = pdTRUE; - 8004244: 4b03 ldr r3, [pc, #12] ; (8004254 ) - 8004246: 2201 movs r2, #1 - 8004248: 601a str r2, [r3, #0] + 8004dc0: 4b03 ldr r3, [pc, #12] ; (8004dd0 ) + 8004dc2: 2201 movs r2, #1 + 8004dc4: 601a str r2, [r3, #0] } - 800424a: bf00 nop - 800424c: 46bd mov sp, r7 - 800424e: f85d 7b04 ldr.w r7, [sp], #4 - 8004252: 4770 bx lr - 8004254: 20000da8 .word 0x20000da8 + 8004dc6: bf00 nop + 8004dc8: 46bd mov sp, r7 + 8004dca: f85d 7b04 ldr.w r7, [sp], #4 + 8004dce: 4770 bx lr + 8004dd0: 20000df8 .word 0x20000df8 -08004258 : +08004dd4 : * * void prvIdleTask( void *pvParameters ); * */ static portTASK_FUNCTION( prvIdleTask, pvParameters ) { - 8004258: b580 push {r7, lr} - 800425a: b082 sub sp, #8 - 800425c: af00 add r7, sp, #0 - 800425e: 6078 str r0, [r7, #4] + 8004dd4: b580 push {r7, lr} + 8004dd6: b082 sub sp, #8 + 8004dd8: af00 add r7, sp, #0 + 8004dda: 6078 str r0, [r7, #4] for( ;; ) { /* See if any tasks have deleted themselves - if so then the idle task is responsible for freeing the deleted task's TCB and stack. */ prvCheckTasksWaitingTermination(); - 8004260: f000 f852 bl 8004308 + 8004ddc: f000 f852 bl 8004e84 A critical region is not required here as we are just reading from the list, and an occasional incorrect value will not matter. If the ready list at the idle priority contains more than one task then a task other than the idle task is ready to execute. */ if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 ) - 8004264: 4b06 ldr r3, [pc, #24] ; (8004280 ) - 8004266: 681b ldr r3, [r3, #0] - 8004268: 2b01 cmp r3, #1 - 800426a: d9f9 bls.n 8004260 + 8004de0: 4b06 ldr r3, [pc, #24] ; (8004dfc ) + 8004de2: 681b ldr r3, [r3, #0] + 8004de4: 2b01 cmp r3, #1 + 8004de6: d9f9 bls.n 8004ddc { taskYIELD(); - 800426c: 4b05 ldr r3, [pc, #20] ; (8004284 ) - 800426e: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 8004272: 601a str r2, [r3, #0] - 8004274: f3bf 8f4f dsb sy - 8004278: f3bf 8f6f isb sy + 8004de8: 4b05 ldr r3, [pc, #20] ; (8004e00 ) + 8004dea: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8004dee: 601a str r2, [r3, #0] + 8004df0: f3bf 8f4f dsb sy + 8004df4: f3bf 8f6f isb sy prvCheckTasksWaitingTermination(); - 800427c: e7f0 b.n 8004260 - 800427e: bf00 nop - 8004280: 200008c4 .word 0x200008c4 - 8004284: e000ed04 .word 0xe000ed04 + 8004df8: e7f0 b.n 8004ddc + 8004dfa: bf00 nop + 8004dfc: 20000914 .word 0x20000914 + 8004e00: e000ed04 .word 0xe000ed04 -08004288 : +08004e04 : #endif /* portUSING_MPU_WRAPPERS */ /*-----------------------------------------------------------*/ static void prvInitialiseTaskLists( void ) { - 8004288: b580 push {r7, lr} - 800428a: b082 sub sp, #8 - 800428c: af00 add r7, sp, #0 + 8004e04: b580 push {r7, lr} + 8004e06: b082 sub sp, #8 + 8004e08: af00 add r7, sp, #0 UBaseType_t uxPriority; for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) - 800428e: 2300 movs r3, #0 - 8004290: 607b str r3, [r7, #4] - 8004292: e00c b.n 80042ae + 8004e0a: 2300 movs r3, #0 + 8004e0c: 607b str r3, [r7, #4] + 8004e0e: e00c b.n 8004e2a { vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) ); - 8004294: 687a ldr r2, [r7, #4] - 8004296: 4613 mov r3, r2 - 8004298: 009b lsls r3, r3, #2 - 800429a: 4413 add r3, r2 - 800429c: 009b lsls r3, r3, #2 - 800429e: 4a12 ldr r2, [pc, #72] ; (80042e8 ) - 80042a0: 4413 add r3, r2 - 80042a2: 4618 mov r0, r3 - 80042a4: f7fe fcca bl 8002c3c + 8004e10: 687a ldr r2, [r7, #4] + 8004e12: 4613 mov r3, r2 + 8004e14: 009b lsls r3, r3, #2 + 8004e16: 4413 add r3, r2 + 8004e18: 009b lsls r3, r3, #2 + 8004e1a: 4a12 ldr r2, [pc, #72] ; (8004e64 ) + 8004e1c: 4413 add r3, r2 + 8004e1e: 4618 mov r0, r3 + 8004e20: f7fe fcca bl 80037b8 for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ ) - 80042a8: 687b ldr r3, [r7, #4] - 80042aa: 3301 adds r3, #1 - 80042ac: 607b str r3, [r7, #4] - 80042ae: 687b ldr r3, [r7, #4] - 80042b0: 2b37 cmp r3, #55 ; 0x37 - 80042b2: d9ef bls.n 8004294 + 8004e24: 687b ldr r3, [r7, #4] + 8004e26: 3301 adds r3, #1 + 8004e28: 607b str r3, [r7, #4] + 8004e2a: 687b ldr r3, [r7, #4] + 8004e2c: 2b37 cmp r3, #55 ; 0x37 + 8004e2e: d9ef bls.n 8004e10 } vListInitialise( &xDelayedTaskList1 ); - 80042b4: 480d ldr r0, [pc, #52] ; (80042ec ) - 80042b6: f7fe fcc1 bl 8002c3c + 8004e30: 480d ldr r0, [pc, #52] ; (8004e68 ) + 8004e32: f7fe fcc1 bl 80037b8 vListInitialise( &xDelayedTaskList2 ); - 80042ba: 480d ldr r0, [pc, #52] ; (80042f0 ) - 80042bc: f7fe fcbe bl 8002c3c + 8004e36: 480d ldr r0, [pc, #52] ; (8004e6c ) + 8004e38: f7fe fcbe bl 80037b8 vListInitialise( &xPendingReadyList ); - 80042c0: 480c ldr r0, [pc, #48] ; (80042f4 ) - 80042c2: f7fe fcbb bl 8002c3c + 8004e3c: 480c ldr r0, [pc, #48] ; (8004e70 ) + 8004e3e: f7fe fcbb bl 80037b8 #if ( INCLUDE_vTaskDelete == 1 ) { vListInitialise( &xTasksWaitingTermination ); - 80042c6: 480c ldr r0, [pc, #48] ; (80042f8 ) - 80042c8: f7fe fcb8 bl 8002c3c + 8004e42: 480c ldr r0, [pc, #48] ; (8004e74 ) + 8004e44: f7fe fcb8 bl 80037b8 } #endif /* INCLUDE_vTaskDelete */ #if ( INCLUDE_vTaskSuspend == 1 ) { vListInitialise( &xSuspendedTaskList ); - 80042cc: 480b ldr r0, [pc, #44] ; (80042fc ) - 80042ce: f7fe fcb5 bl 8002c3c + 8004e48: 480b ldr r0, [pc, #44] ; (8004e78 ) + 8004e4a: f7fe fcb5 bl 80037b8 } #endif /* INCLUDE_vTaskSuspend */ /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList using list2. */ pxDelayedTaskList = &xDelayedTaskList1; - 80042d2: 4b0b ldr r3, [pc, #44] ; (8004300 ) - 80042d4: 4a05 ldr r2, [pc, #20] ; (80042ec ) - 80042d6: 601a str r2, [r3, #0] + 8004e4e: 4b0b ldr r3, [pc, #44] ; (8004e7c ) + 8004e50: 4a05 ldr r2, [pc, #20] ; (8004e68 ) + 8004e52: 601a str r2, [r3, #0] pxOverflowDelayedTaskList = &xDelayedTaskList2; - 80042d8: 4b0a ldr r3, [pc, #40] ; (8004304 ) - 80042da: 4a05 ldr r2, [pc, #20] ; (80042f0 ) - 80042dc: 601a str r2, [r3, #0] + 8004e54: 4b0a ldr r3, [pc, #40] ; (8004e80 ) + 8004e56: 4a05 ldr r2, [pc, #20] ; (8004e6c ) + 8004e58: 601a str r2, [r3, #0] } - 80042de: bf00 nop - 80042e0: 3708 adds r7, #8 - 80042e2: 46bd mov sp, r7 - 80042e4: bd80 pop {r7, pc} - 80042e6: bf00 nop - 80042e8: 200008c4 .word 0x200008c4 - 80042ec: 20000d24 .word 0x20000d24 - 80042f0: 20000d38 .word 0x20000d38 - 80042f4: 20000d54 .word 0x20000d54 - 80042f8: 20000d68 .word 0x20000d68 - 80042fc: 20000d80 .word 0x20000d80 - 8004300: 20000d4c .word 0x20000d4c - 8004304: 20000d50 .word 0x20000d50 + 8004e5a: bf00 nop + 8004e5c: 3708 adds r7, #8 + 8004e5e: 46bd mov sp, r7 + 8004e60: bd80 pop {r7, pc} + 8004e62: bf00 nop + 8004e64: 20000914 .word 0x20000914 + 8004e68: 20000d74 .word 0x20000d74 + 8004e6c: 20000d88 .word 0x20000d88 + 8004e70: 20000da4 .word 0x20000da4 + 8004e74: 20000db8 .word 0x20000db8 + 8004e78: 20000dd0 .word 0x20000dd0 + 8004e7c: 20000d9c .word 0x20000d9c + 8004e80: 20000da0 .word 0x20000da0 -08004308 : +08004e84 : /*-----------------------------------------------------------*/ static void prvCheckTasksWaitingTermination( void ) { - 8004308: b580 push {r7, lr} - 800430a: b082 sub sp, #8 - 800430c: af00 add r7, sp, #0 + 8004e84: b580 push {r7, lr} + 8004e86: b082 sub sp, #8 + 8004e88: af00 add r7, sp, #0 { TCB_t *pxTCB; /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL() being called too often in the idle task. */ while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) - 800430e: e019 b.n 8004344 + 8004e8a: e019 b.n 8004ec0 { taskENTER_CRITICAL(); - 8004310: f000 fdd8 bl 8004ec4 + 8004e8c: f000 fdda bl 8005a44 { pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8004314: 4b10 ldr r3, [pc, #64] ; (8004358 ) - 8004316: 68db ldr r3, [r3, #12] - 8004318: 68db ldr r3, [r3, #12] - 800431a: 607b str r3, [r7, #4] + 8004e90: 4b10 ldr r3, [pc, #64] ; (8004ed4 ) + 8004e92: 68db ldr r3, [r3, #12] + 8004e94: 68db ldr r3, [r3, #12] + 8004e96: 607b str r3, [r7, #4] ( void ) uxListRemove( &( pxTCB->xStateListItem ) ); - 800431c: 687b ldr r3, [r7, #4] - 800431e: 3304 adds r3, #4 - 8004320: 4618 mov r0, r3 - 8004322: f7fe fd15 bl 8002d50 + 8004e98: 687b ldr r3, [r7, #4] + 8004e9a: 3304 adds r3, #4 + 8004e9c: 4618 mov r0, r3 + 8004e9e: f7fe fd15 bl 80038cc --uxCurrentNumberOfTasks; - 8004326: 4b0d ldr r3, [pc, #52] ; (800435c ) - 8004328: 681b ldr r3, [r3, #0] - 800432a: 3b01 subs r3, #1 - 800432c: 4a0b ldr r2, [pc, #44] ; (800435c ) - 800432e: 6013 str r3, [r2, #0] + 8004ea2: 4b0d ldr r3, [pc, #52] ; (8004ed8 ) + 8004ea4: 681b ldr r3, [r3, #0] + 8004ea6: 3b01 subs r3, #1 + 8004ea8: 4a0b ldr r2, [pc, #44] ; (8004ed8 ) + 8004eaa: 6013 str r3, [r2, #0] --uxDeletedTasksWaitingCleanUp; - 8004330: 4b0b ldr r3, [pc, #44] ; (8004360 ) - 8004332: 681b ldr r3, [r3, #0] - 8004334: 3b01 subs r3, #1 - 8004336: 4a0a ldr r2, [pc, #40] ; (8004360 ) - 8004338: 6013 str r3, [r2, #0] + 8004eac: 4b0b ldr r3, [pc, #44] ; (8004edc ) + 8004eae: 681b ldr r3, [r3, #0] + 8004eb0: 3b01 subs r3, #1 + 8004eb2: 4a0a ldr r2, [pc, #40] ; (8004edc ) + 8004eb4: 6013 str r3, [r2, #0] } taskEXIT_CRITICAL(); - 800433a: f000 fdf3 bl 8004f24 + 8004eb6: f000 fdf5 bl 8005aa4 prvDeleteTCB( pxTCB ); - 800433e: 6878 ldr r0, [r7, #4] - 8004340: f000 f810 bl 8004364 + 8004eba: 6878 ldr r0, [r7, #4] + 8004ebc: f000 f810 bl 8004ee0 while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U ) - 8004344: 4b06 ldr r3, [pc, #24] ; (8004360 ) - 8004346: 681b ldr r3, [r3, #0] - 8004348: 2b00 cmp r3, #0 - 800434a: d1e1 bne.n 8004310 + 8004ec0: 4b06 ldr r3, [pc, #24] ; (8004edc ) + 8004ec2: 681b ldr r3, [r3, #0] + 8004ec4: 2b00 cmp r3, #0 + 8004ec6: d1e1 bne.n 8004e8c } } #endif /* INCLUDE_vTaskDelete */ } - 800434c: bf00 nop - 800434e: bf00 nop - 8004350: 3708 adds r7, #8 - 8004352: 46bd mov sp, r7 - 8004354: bd80 pop {r7, pc} - 8004356: bf00 nop - 8004358: 20000d68 .word 0x20000d68 - 800435c: 20000d94 .word 0x20000d94 - 8004360: 20000d7c .word 0x20000d7c + 8004ec8: bf00 nop + 8004eca: bf00 nop + 8004ecc: 3708 adds r7, #8 + 8004ece: 46bd mov sp, r7 + 8004ed0: bd80 pop {r7, pc} + 8004ed2: bf00 nop + 8004ed4: 20000db8 .word 0x20000db8 + 8004ed8: 20000de4 .word 0x20000de4 + 8004edc: 20000dcc .word 0x20000dcc -08004364 : +08004ee0 : /*-----------------------------------------------------------*/ #if ( INCLUDE_vTaskDelete == 1 ) static void prvDeleteTCB( TCB_t *pxTCB ) { - 8004364: b580 push {r7, lr} - 8004366: b084 sub sp, #16 - 8004368: af00 add r7, sp, #0 - 800436a: 6078 str r0, [r7, #4] + 8004ee0: b580 push {r7, lr} + 8004ee2: b084 sub sp, #16 + 8004ee4: af00 add r7, sp, #0 + 8004ee6: 6078 str r0, [r7, #4] to the task to free any memory allocated at the application level. See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html for additional information. */ #if ( configUSE_NEWLIB_REENTRANT == 1 ) { _reclaim_reent( &( pxTCB->xNewLib_reent ) ); - 800436c: 687b ldr r3, [r7, #4] - 800436e: 3354 adds r3, #84 ; 0x54 - 8004370: 4618 mov r0, r3 - 8004372: f001 f8bb bl 80054ec <_reclaim_reent> + 8004ee8: 687b ldr r3, [r7, #4] + 8004eea: 3354 adds r3, #84 ; 0x54 + 8004eec: 4618 mov r0, r3 + 8004eee: f001 f8bd bl 800606c <_reclaim_reent> #elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ { /* The task could have been allocated statically or dynamically, so check what was statically allocated before trying to free the memory. */ if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB ) - 8004376: 687b ldr r3, [r7, #4] - 8004378: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5 - 800437c: 2b00 cmp r3, #0 - 800437e: d108 bne.n 8004392 + 8004ef2: 687b ldr r3, [r7, #4] + 8004ef4: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5 + 8004ef8: 2b00 cmp r3, #0 + 8004efa: d108 bne.n 8004f0e { /* Both the stack and TCB were allocated dynamically, so both must be freed. */ vPortFree( pxTCB->pxStack ); - 8004380: 687b ldr r3, [r7, #4] - 8004382: 6b1b ldr r3, [r3, #48] ; 0x30 - 8004384: 4618 mov r0, r3 - 8004386: f000 ff8b bl 80052a0 + 8004efc: 687b ldr r3, [r7, #4] + 8004efe: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004f00: 4618 mov r0, r3 + 8004f02: f000 ff8d bl 8005e20 vPortFree( pxTCB ); - 800438a: 6878 ldr r0, [r7, #4] - 800438c: f000 ff88 bl 80052a0 + 8004f06: 6878 ldr r0, [r7, #4] + 8004f08: f000 ff8a bl 8005e20 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); mtCOVERAGE_TEST_MARKER(); } } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ } - 8004390: e018 b.n 80043c4 + 8004f0c: e018 b.n 8004f40 else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY ) - 8004392: 687b ldr r3, [r7, #4] - 8004394: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5 - 8004398: 2b01 cmp r3, #1 - 800439a: d103 bne.n 80043a4 + 8004f0e: 687b ldr r3, [r7, #4] + 8004f10: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5 + 8004f14: 2b01 cmp r3, #1 + 8004f16: d103 bne.n 8004f20 vPortFree( pxTCB ); - 800439c: 6878 ldr r0, [r7, #4] - 800439e: f000 ff7f bl 80052a0 + 8004f18: 6878 ldr r0, [r7, #4] + 8004f1a: f000 ff81 bl 8005e20 } - 80043a2: e00f b.n 80043c4 + 8004f1e: e00f b.n 8004f40 configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB ); - 80043a4: 687b ldr r3, [r7, #4] - 80043a6: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5 - 80043aa: 2b02 cmp r3, #2 - 80043ac: d00a beq.n 80043c4 + 8004f20: 687b ldr r3, [r7, #4] + 8004f22: f893 30a5 ldrb.w r3, [r3, #165] ; 0xa5 + 8004f26: 2b02 cmp r3, #2 + 8004f28: d00a beq.n 8004f40 __asm volatile - 80043ae: f04f 0350 mov.w r3, #80 ; 0x50 - 80043b2: f383 8811 msr BASEPRI, r3 - 80043b6: f3bf 8f6f isb sy - 80043ba: f3bf 8f4f dsb sy - 80043be: 60fb str r3, [r7, #12] + 8004f2a: f04f 0350 mov.w r3, #80 ; 0x50 + 8004f2e: f383 8811 msr BASEPRI, r3 + 8004f32: f3bf 8f6f isb sy + 8004f36: f3bf 8f4f dsb sy + 8004f3a: 60fb str r3, [r7, #12] } - 80043c0: bf00 nop - 80043c2: e7fe b.n 80043c2 + 8004f3c: bf00 nop + 8004f3e: e7fe b.n 8004f3e } - 80043c4: bf00 nop - 80043c6: 3710 adds r7, #16 - 80043c8: 46bd mov sp, r7 - 80043ca: bd80 pop {r7, pc} + 8004f40: bf00 nop + 8004f42: 3710 adds r7, #16 + 8004f44: 46bd mov sp, r7 + 8004f46: bd80 pop {r7, pc} -080043cc : +08004f48 : #endif /* INCLUDE_vTaskDelete */ /*-----------------------------------------------------------*/ static void prvResetNextTaskUnblockTime( void ) { - 80043cc: b480 push {r7} - 80043ce: b083 sub sp, #12 - 80043d0: af00 add r7, sp, #0 + 8004f48: b480 push {r7} + 8004f4a: b083 sub sp, #12 + 8004f4c: af00 add r7, sp, #0 TCB_t *pxTCB; if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE ) - 80043d2: 4b0c ldr r3, [pc, #48] ; (8004404 ) - 80043d4: 681b ldr r3, [r3, #0] - 80043d6: 681b ldr r3, [r3, #0] - 80043d8: 2b00 cmp r3, #0 - 80043da: d104 bne.n 80043e6 + 8004f4e: 4b0c ldr r3, [pc, #48] ; (8004f80 ) + 8004f50: 681b ldr r3, [r3, #0] + 8004f52: 681b ldr r3, [r3, #0] + 8004f54: 2b00 cmp r3, #0 + 8004f56: d104 bne.n 8004f62 { /* The new current delayed list is empty. Set xNextTaskUnblockTime to the maximum possible value so it is extremely unlikely that the if( xTickCount >= xNextTaskUnblockTime ) test will pass until there is an item in the delayed list. */ xNextTaskUnblockTime = portMAX_DELAY; - 80043dc: 4b0a ldr r3, [pc, #40] ; (8004408 ) - 80043de: f04f 32ff mov.w r2, #4294967295 - 80043e2: 601a str r2, [r3, #0] + 8004f58: 4b0a ldr r3, [pc, #40] ; (8004f84 ) + 8004f5a: f04f 32ff mov.w r2, #4294967295 + 8004f5e: 601a str r2, [r3, #0] which the task at the head of the delayed list should be removed from the Blocked state. */ ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); } } - 80043e4: e008 b.n 80043f8 + 8004f60: e008 b.n 8004f74 ( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 80043e6: 4b07 ldr r3, [pc, #28] ; (8004404 ) - 80043e8: 681b ldr r3, [r3, #0] - 80043ea: 68db ldr r3, [r3, #12] - 80043ec: 68db ldr r3, [r3, #12] - 80043ee: 607b str r3, [r7, #4] + 8004f62: 4b07 ldr r3, [pc, #28] ; (8004f80 ) + 8004f64: 681b ldr r3, [r3, #0] + 8004f66: 68db ldr r3, [r3, #12] + 8004f68: 68db ldr r3, [r3, #12] + 8004f6a: 607b str r3, [r7, #4] xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) ); - 80043f0: 687b ldr r3, [r7, #4] - 80043f2: 685b ldr r3, [r3, #4] - 80043f4: 4a04 ldr r2, [pc, #16] ; (8004408 ) - 80043f6: 6013 str r3, [r2, #0] + 8004f6c: 687b ldr r3, [r7, #4] + 8004f6e: 685b ldr r3, [r3, #4] + 8004f70: 4a04 ldr r2, [pc, #16] ; (8004f84 ) + 8004f72: 6013 str r3, [r2, #0] } - 80043f8: bf00 nop - 80043fa: 370c adds r7, #12 - 80043fc: 46bd mov sp, r7 - 80043fe: f85d 7b04 ldr.w r7, [sp], #4 - 8004402: 4770 bx lr - 8004404: 20000d4c .word 0x20000d4c - 8004408: 20000db4 .word 0x20000db4 + 8004f74: bf00 nop + 8004f76: 370c adds r7, #12 + 8004f78: 46bd mov sp, r7 + 8004f7a: f85d 7b04 ldr.w r7, [sp], #4 + 8004f7e: 4770 bx lr + 8004f80: 20000d9c .word 0x20000d9c + 8004f84: 20000e04 .word 0x20000e04 -0800440c : +08004f88 : /*-----------------------------------------------------------*/ #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) BaseType_t xTaskGetSchedulerState( void ) { - 800440c: b480 push {r7} - 800440e: b083 sub sp, #12 - 8004410: af00 add r7, sp, #0 + 8004f88: b480 push {r7} + 8004f8a: b083 sub sp, #12 + 8004f8c: af00 add r7, sp, #0 BaseType_t xReturn; if( xSchedulerRunning == pdFALSE ) - 8004412: 4b0b ldr r3, [pc, #44] ; (8004440 ) - 8004414: 681b ldr r3, [r3, #0] - 8004416: 2b00 cmp r3, #0 - 8004418: d102 bne.n 8004420 + 8004f8e: 4b0b ldr r3, [pc, #44] ; (8004fbc ) + 8004f90: 681b ldr r3, [r3, #0] + 8004f92: 2b00 cmp r3, #0 + 8004f94: d102 bne.n 8004f9c { xReturn = taskSCHEDULER_NOT_STARTED; - 800441a: 2301 movs r3, #1 - 800441c: 607b str r3, [r7, #4] - 800441e: e008 b.n 8004432 + 8004f96: 2301 movs r3, #1 + 8004f98: 607b str r3, [r7, #4] + 8004f9a: e008 b.n 8004fae } else { if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE ) - 8004420: 4b08 ldr r3, [pc, #32] ; (8004444 ) - 8004422: 681b ldr r3, [r3, #0] - 8004424: 2b00 cmp r3, #0 - 8004426: d102 bne.n 800442e + 8004f9c: 4b08 ldr r3, [pc, #32] ; (8004fc0 ) + 8004f9e: 681b ldr r3, [r3, #0] + 8004fa0: 2b00 cmp r3, #0 + 8004fa2: d102 bne.n 8004faa { xReturn = taskSCHEDULER_RUNNING; - 8004428: 2302 movs r3, #2 - 800442a: 607b str r3, [r7, #4] - 800442c: e001 b.n 8004432 + 8004fa4: 2302 movs r3, #2 + 8004fa6: 607b str r3, [r7, #4] + 8004fa8: e001 b.n 8004fae } else { xReturn = taskSCHEDULER_SUSPENDED; - 800442e: 2300 movs r3, #0 - 8004430: 607b str r3, [r7, #4] + 8004faa: 2300 movs r3, #0 + 8004fac: 607b str r3, [r7, #4] } } return xReturn; - 8004432: 687b ldr r3, [r7, #4] + 8004fae: 687b ldr r3, [r7, #4] } - 8004434: 4618 mov r0, r3 - 8004436: 370c adds r7, #12 - 8004438: 46bd mov sp, r7 - 800443a: f85d 7b04 ldr.w r7, [sp], #4 - 800443e: 4770 bx lr - 8004440: 20000da0 .word 0x20000da0 - 8004444: 20000dbc .word 0x20000dbc + 8004fb0: 4618 mov r0, r3 + 8004fb2: 370c adds r7, #12 + 8004fb4: 46bd mov sp, r7 + 8004fb6: f85d 7b04 ldr.w r7, [sp], #4 + 8004fba: 4770 bx lr + 8004fbc: 20000df0 .word 0x20000df0 + 8004fc0: 20000e0c .word 0x20000e0c -08004448 : +08004fc4 : /*-----------------------------------------------------------*/ #if ( configUSE_MUTEXES == 1 ) BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) { - 8004448: b580 push {r7, lr} - 800444a: b086 sub sp, #24 - 800444c: af00 add r7, sp, #0 - 800444e: 6078 str r0, [r7, #4] + 8004fc4: b580 push {r7, lr} + 8004fc6: b086 sub sp, #24 + 8004fc8: af00 add r7, sp, #0 + 8004fca: 6078 str r0, [r7, #4] TCB_t * const pxTCB = pxMutexHolder; - 8004450: 687b ldr r3, [r7, #4] - 8004452: 613b str r3, [r7, #16] + 8004fcc: 687b ldr r3, [r7, #4] + 8004fce: 613b str r3, [r7, #16] BaseType_t xReturn = pdFALSE; - 8004454: 2300 movs r3, #0 - 8004456: 617b str r3, [r7, #20] + 8004fd0: 2300 movs r3, #0 + 8004fd2: 617b str r3, [r7, #20] if( pxMutexHolder != NULL ) - 8004458: 687b ldr r3, [r7, #4] - 800445a: 2b00 cmp r3, #0 - 800445c: d056 beq.n 800450c + 8004fd4: 687b ldr r3, [r7, #4] + 8004fd6: 2b00 cmp r3, #0 + 8004fd8: d056 beq.n 8005088 { /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. */ configASSERT( pxTCB == pxCurrentTCB ); - 800445e: 4b2e ldr r3, [pc, #184] ; (8004518 ) - 8004460: 681b ldr r3, [r3, #0] - 8004462: 693a ldr r2, [r7, #16] - 8004464: 429a cmp r2, r3 - 8004466: d00a beq.n 800447e + 8004fda: 4b2e ldr r3, [pc, #184] ; (8005094 ) + 8004fdc: 681b ldr r3, [r3, #0] + 8004fde: 693a ldr r2, [r7, #16] + 8004fe0: 429a cmp r2, r3 + 8004fe2: d00a beq.n 8004ffa __asm volatile - 8004468: f04f 0350 mov.w r3, #80 ; 0x50 - 800446c: f383 8811 msr BASEPRI, r3 - 8004470: f3bf 8f6f isb sy - 8004474: f3bf 8f4f dsb sy - 8004478: 60fb str r3, [r7, #12] + 8004fe4: f04f 0350 mov.w r3, #80 ; 0x50 + 8004fe8: f383 8811 msr BASEPRI, r3 + 8004fec: f3bf 8f6f isb sy + 8004ff0: f3bf 8f4f dsb sy + 8004ff4: 60fb str r3, [r7, #12] } - 800447a: bf00 nop - 800447c: e7fe b.n 800447c + 8004ff6: bf00 nop + 8004ff8: e7fe b.n 8004ff8 configASSERT( pxTCB->uxMutexesHeld ); - 800447e: 693b ldr r3, [r7, #16] - 8004480: 6d1b ldr r3, [r3, #80] ; 0x50 - 8004482: 2b00 cmp r3, #0 - 8004484: d10a bne.n 800449c + 8004ffa: 693b ldr r3, [r7, #16] + 8004ffc: 6d1b ldr r3, [r3, #80] ; 0x50 + 8004ffe: 2b00 cmp r3, #0 + 8005000: d10a bne.n 8005018 __asm volatile - 8004486: f04f 0350 mov.w r3, #80 ; 0x50 - 800448a: f383 8811 msr BASEPRI, r3 - 800448e: f3bf 8f6f isb sy - 8004492: f3bf 8f4f dsb sy - 8004496: 60bb str r3, [r7, #8] + 8005002: f04f 0350 mov.w r3, #80 ; 0x50 + 8005006: f383 8811 msr BASEPRI, r3 + 800500a: f3bf 8f6f isb sy + 800500e: f3bf 8f4f dsb sy + 8005012: 60bb str r3, [r7, #8] } - 8004498: bf00 nop - 800449a: e7fe b.n 800449a + 8005014: bf00 nop + 8005016: e7fe b.n 8005016 ( pxTCB->uxMutexesHeld )--; - 800449c: 693b ldr r3, [r7, #16] - 800449e: 6d1b ldr r3, [r3, #80] ; 0x50 - 80044a0: 1e5a subs r2, r3, #1 - 80044a2: 693b ldr r3, [r7, #16] - 80044a4: 651a str r2, [r3, #80] ; 0x50 + 8005018: 693b ldr r3, [r7, #16] + 800501a: 6d1b ldr r3, [r3, #80] ; 0x50 + 800501c: 1e5a subs r2, r3, #1 + 800501e: 693b ldr r3, [r7, #16] + 8005020: 651a str r2, [r3, #80] ; 0x50 /* Has the holder of the mutex inherited the priority of another task? */ if( pxTCB->uxPriority != pxTCB->uxBasePriority ) - 80044a6: 693b ldr r3, [r7, #16] - 80044a8: 6ada ldr r2, [r3, #44] ; 0x2c - 80044aa: 693b ldr r3, [r7, #16] - 80044ac: 6cdb ldr r3, [r3, #76] ; 0x4c - 80044ae: 429a cmp r2, r3 - 80044b0: d02c beq.n 800450c + 8005022: 693b ldr r3, [r7, #16] + 8005024: 6ada ldr r2, [r3, #44] ; 0x2c + 8005026: 693b ldr r3, [r7, #16] + 8005028: 6cdb ldr r3, [r3, #76] ; 0x4c + 800502a: 429a cmp r2, r3 + 800502c: d02c beq.n 8005088 { /* Only disinherit if no other mutexes are held. */ if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 ) - 80044b2: 693b ldr r3, [r7, #16] - 80044b4: 6d1b ldr r3, [r3, #80] ; 0x50 - 80044b6: 2b00 cmp r3, #0 - 80044b8: d128 bne.n 800450c + 800502e: 693b ldr r3, [r7, #16] + 8005030: 6d1b ldr r3, [r3, #80] ; 0x50 + 8005032: 2b00 cmp r3, #0 + 8005034: d128 bne.n 8005088 /* A task can only have an inherited priority if it holds the mutex. If the mutex is held by a task then it cannot be given from an interrupt, and if a mutex is given by the holding task then it must be the running state task. Remove the holding task from the ready/delayed list. */ if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) - 80044ba: 693b ldr r3, [r7, #16] - 80044bc: 3304 adds r3, #4 - 80044be: 4618 mov r0, r3 - 80044c0: f7fe fc46 bl 8002d50 + 8005036: 693b ldr r3, [r7, #16] + 8005038: 3304 adds r3, #4 + 800503a: 4618 mov r0, r3 + 800503c: f7fe fc46 bl 80038cc } /* Disinherit the priority before adding the task into the new ready list. */ traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority ); pxTCB->uxPriority = pxTCB->uxBasePriority; - 80044c4: 693b ldr r3, [r7, #16] - 80044c6: 6cda ldr r2, [r3, #76] ; 0x4c - 80044c8: 693b ldr r3, [r7, #16] - 80044ca: 62da str r2, [r3, #44] ; 0x2c + 8005040: 693b ldr r3, [r7, #16] + 8005042: 6cda ldr r2, [r3, #76] ; 0x4c + 8005044: 693b ldr r3, [r7, #16] + 8005046: 62da str r2, [r3, #44] ; 0x2c /* Reset the event list item value. It cannot be in use for any other purpose if this task is running, and it must be running to give back the mutex. */ listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - 80044cc: 693b ldr r3, [r7, #16] - 80044ce: 6adb ldr r3, [r3, #44] ; 0x2c - 80044d0: f1c3 0238 rsb r2, r3, #56 ; 0x38 - 80044d4: 693b ldr r3, [r7, #16] - 80044d6: 619a str r2, [r3, #24] + 8005048: 693b ldr r3, [r7, #16] + 800504a: 6adb ldr r3, [r3, #44] ; 0x2c + 800504c: f1c3 0238 rsb r2, r3, #56 ; 0x38 + 8005050: 693b ldr r3, [r7, #16] + 8005052: 619a str r2, [r3, #24] prvAddTaskToReadyList( pxTCB ); - 80044d8: 693b ldr r3, [r7, #16] - 80044da: 6ada ldr r2, [r3, #44] ; 0x2c - 80044dc: 4b0f ldr r3, [pc, #60] ; (800451c ) - 80044de: 681b ldr r3, [r3, #0] - 80044e0: 429a cmp r2, r3 - 80044e2: d903 bls.n 80044ec - 80044e4: 693b ldr r3, [r7, #16] - 80044e6: 6adb ldr r3, [r3, #44] ; 0x2c - 80044e8: 4a0c ldr r2, [pc, #48] ; (800451c ) - 80044ea: 6013 str r3, [r2, #0] - 80044ec: 693b ldr r3, [r7, #16] - 80044ee: 6ada ldr r2, [r3, #44] ; 0x2c - 80044f0: 4613 mov r3, r2 - 80044f2: 009b lsls r3, r3, #2 - 80044f4: 4413 add r3, r2 - 80044f6: 009b lsls r3, r3, #2 - 80044f8: 4a09 ldr r2, [pc, #36] ; (8004520 ) - 80044fa: 441a add r2, r3 - 80044fc: 693b ldr r3, [r7, #16] - 80044fe: 3304 adds r3, #4 - 8004500: 4619 mov r1, r3 - 8004502: 4610 mov r0, r2 - 8004504: f7fe fbc7 bl 8002c96 + 8005054: 693b ldr r3, [r7, #16] + 8005056: 6ada ldr r2, [r3, #44] ; 0x2c + 8005058: 4b0f ldr r3, [pc, #60] ; (8005098 ) + 800505a: 681b ldr r3, [r3, #0] + 800505c: 429a cmp r2, r3 + 800505e: d903 bls.n 8005068 + 8005060: 693b ldr r3, [r7, #16] + 8005062: 6adb ldr r3, [r3, #44] ; 0x2c + 8005064: 4a0c ldr r2, [pc, #48] ; (8005098 ) + 8005066: 6013 str r3, [r2, #0] + 8005068: 693b ldr r3, [r7, #16] + 800506a: 6ada ldr r2, [r3, #44] ; 0x2c + 800506c: 4613 mov r3, r2 + 800506e: 009b lsls r3, r3, #2 + 8005070: 4413 add r3, r2 + 8005072: 009b lsls r3, r3, #2 + 8005074: 4a09 ldr r2, [pc, #36] ; (800509c ) + 8005076: 441a add r2, r3 + 8005078: 693b ldr r3, [r7, #16] + 800507a: 3304 adds r3, #4 + 800507c: 4619 mov r1, r3 + 800507e: 4610 mov r0, r2 + 8005080: f7fe fbc7 bl 8003812 in an order different to that in which they were taken. If a context switch did not occur when the first mutex was returned, even if a task was waiting on it, then a context switch should occur when the last mutex is returned whether a task is waiting on it or not. */ xReturn = pdTRUE; - 8004508: 2301 movs r3, #1 - 800450a: 617b str r3, [r7, #20] + 8005084: 2301 movs r3, #1 + 8005086: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } return xReturn; - 800450c: 697b ldr r3, [r7, #20] + 8005088: 697b ldr r3, [r7, #20] } - 800450e: 4618 mov r0, r3 - 8004510: 3718 adds r7, #24 - 8004512: 46bd mov sp, r7 - 8004514: bd80 pop {r7, pc} - 8004516: bf00 nop - 8004518: 200008c0 .word 0x200008c0 - 800451c: 20000d9c .word 0x20000d9c - 8004520: 200008c4 .word 0x200008c4 + 800508a: 4618 mov r0, r3 + 800508c: 3718 adds r7, #24 + 800508e: 46bd mov sp, r7 + 8005090: bd80 pop {r7, pc} + 8005092: bf00 nop + 8005094: 20000910 .word 0x20000910 + 8005098: 20000dec .word 0x20000dec + 800509c: 20000914 .word 0x20000914 -08004524 : +080050a0 : #endif /*-----------------------------------------------------------*/ static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) { - 8004524: b580 push {r7, lr} - 8004526: b084 sub sp, #16 - 8004528: af00 add r7, sp, #0 - 800452a: 6078 str r0, [r7, #4] - 800452c: 6039 str r1, [r7, #0] + 80050a0: b580 push {r7, lr} + 80050a2: b084 sub sp, #16 + 80050a4: af00 add r7, sp, #0 + 80050a6: 6078 str r0, [r7, #4] + 80050a8: 6039 str r1, [r7, #0] TickType_t xTimeToWake; const TickType_t xConstTickCount = xTickCount; - 800452e: 4b21 ldr r3, [pc, #132] ; (80045b4 ) - 8004530: 681b ldr r3, [r3, #0] - 8004532: 60fb str r3, [r7, #12] + 80050aa: 4b21 ldr r3, [pc, #132] ; (8005130 ) + 80050ac: 681b ldr r3, [r3, #0] + 80050ae: 60fb str r3, [r7, #12] } #endif /* Remove the task from the ready list before adding it to the blocked list as the same list item is used for both lists. */ if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 ) - 8004534: 4b20 ldr r3, [pc, #128] ; (80045b8 ) - 8004536: 681b ldr r3, [r3, #0] - 8004538: 3304 adds r3, #4 - 800453a: 4618 mov r0, r3 - 800453c: f7fe fc08 bl 8002d50 + 80050b0: 4b20 ldr r3, [pc, #128] ; (8005134 ) + 80050b2: 681b ldr r3, [r3, #0] + 80050b4: 3304 adds r3, #4 + 80050b6: 4618 mov r0, r3 + 80050b8: f7fe fc08 bl 80038cc mtCOVERAGE_TEST_MARKER(); } #if ( INCLUDE_vTaskSuspend == 1 ) { if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) ) - 8004540: 687b ldr r3, [r7, #4] - 8004542: f1b3 3fff cmp.w r3, #4294967295 - 8004546: d10a bne.n 800455e - 8004548: 683b ldr r3, [r7, #0] - 800454a: 2b00 cmp r3, #0 - 800454c: d007 beq.n 800455e + 80050bc: 687b ldr r3, [r7, #4] + 80050be: f1b3 3fff cmp.w r3, #4294967295 + 80050c2: d10a bne.n 80050da + 80050c4: 683b ldr r3, [r7, #0] + 80050c6: 2b00 cmp r3, #0 + 80050c8: d007 beq.n 80050da { /* Add the task to the suspended task list instead of a delayed task list to ensure it is not woken by a timing event. It will block indefinitely. */ vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) ); - 800454e: 4b1a ldr r3, [pc, #104] ; (80045b8 ) - 8004550: 681b ldr r3, [r3, #0] - 8004552: 3304 adds r3, #4 - 8004554: 4619 mov r1, r3 - 8004556: 4819 ldr r0, [pc, #100] ; (80045bc ) - 8004558: f7fe fb9d bl 8002c96 + 80050ca: 4b1a ldr r3, [pc, #104] ; (8005134 ) + 80050cc: 681b ldr r3, [r3, #0] + 80050ce: 3304 adds r3, #4 + 80050d0: 4619 mov r1, r3 + 80050d2: 4819 ldr r0, [pc, #100] ; (8005138 ) + 80050d4: f7fe fb9d bl 8003812 /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */ ( void ) xCanBlockIndefinitely; } #endif /* INCLUDE_vTaskSuspend */ } - 800455c: e026 b.n 80045ac + 80050d8: e026 b.n 8005128 xTimeToWake = xConstTickCount + xTicksToWait; - 800455e: 68fa ldr r2, [r7, #12] - 8004560: 687b ldr r3, [r7, #4] - 8004562: 4413 add r3, r2 - 8004564: 60bb str r3, [r7, #8] + 80050da: 68fa ldr r2, [r7, #12] + 80050dc: 687b ldr r3, [r7, #4] + 80050de: 4413 add r3, r2 + 80050e0: 60bb str r3, [r7, #8] listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake ); - 8004566: 4b14 ldr r3, [pc, #80] ; (80045b8 ) - 8004568: 681b ldr r3, [r3, #0] - 800456a: 68ba ldr r2, [r7, #8] - 800456c: 605a str r2, [r3, #4] + 80050e2: 4b14 ldr r3, [pc, #80] ; (8005134 ) + 80050e4: 681b ldr r3, [r3, #0] + 80050e6: 68ba ldr r2, [r7, #8] + 80050e8: 605a str r2, [r3, #4] if( xTimeToWake < xConstTickCount ) - 800456e: 68ba ldr r2, [r7, #8] - 8004570: 68fb ldr r3, [r7, #12] - 8004572: 429a cmp r2, r3 - 8004574: d209 bcs.n 800458a + 80050ea: 68ba ldr r2, [r7, #8] + 80050ec: 68fb ldr r3, [r7, #12] + 80050ee: 429a cmp r2, r3 + 80050f0: d209 bcs.n 8005106 vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); - 8004576: 4b12 ldr r3, [pc, #72] ; (80045c0 ) - 8004578: 681a ldr r2, [r3, #0] - 800457a: 4b0f ldr r3, [pc, #60] ; (80045b8 ) - 800457c: 681b ldr r3, [r3, #0] - 800457e: 3304 adds r3, #4 - 8004580: 4619 mov r1, r3 - 8004582: 4610 mov r0, r2 - 8004584: f7fe fbab bl 8002cde + 80050f2: 4b12 ldr r3, [pc, #72] ; (800513c ) + 80050f4: 681a ldr r2, [r3, #0] + 80050f6: 4b0f ldr r3, [pc, #60] ; (8005134 ) + 80050f8: 681b ldr r3, [r3, #0] + 80050fa: 3304 adds r3, #4 + 80050fc: 4619 mov r1, r3 + 80050fe: 4610 mov r0, r2 + 8005100: f7fe fbab bl 800385a } - 8004588: e010 b.n 80045ac + 8005104: e010 b.n 8005128 vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) ); - 800458a: 4b0e ldr r3, [pc, #56] ; (80045c4 ) - 800458c: 681a ldr r2, [r3, #0] - 800458e: 4b0a ldr r3, [pc, #40] ; (80045b8 ) - 8004590: 681b ldr r3, [r3, #0] - 8004592: 3304 adds r3, #4 - 8004594: 4619 mov r1, r3 - 8004596: 4610 mov r0, r2 - 8004598: f7fe fba1 bl 8002cde + 8005106: 4b0e ldr r3, [pc, #56] ; (8005140 ) + 8005108: 681a ldr r2, [r3, #0] + 800510a: 4b0a ldr r3, [pc, #40] ; (8005134 ) + 800510c: 681b ldr r3, [r3, #0] + 800510e: 3304 adds r3, #4 + 8005110: 4619 mov r1, r3 + 8005112: 4610 mov r0, r2 + 8005114: f7fe fba1 bl 800385a if( xTimeToWake < xNextTaskUnblockTime ) - 800459c: 4b0a ldr r3, [pc, #40] ; (80045c8 ) - 800459e: 681b ldr r3, [r3, #0] - 80045a0: 68ba ldr r2, [r7, #8] - 80045a2: 429a cmp r2, r3 - 80045a4: d202 bcs.n 80045ac + 8005118: 4b0a ldr r3, [pc, #40] ; (8005144 ) + 800511a: 681b ldr r3, [r3, #0] + 800511c: 68ba ldr r2, [r7, #8] + 800511e: 429a cmp r2, r3 + 8005120: d202 bcs.n 8005128 xNextTaskUnblockTime = xTimeToWake; - 80045a6: 4a08 ldr r2, [pc, #32] ; (80045c8 ) - 80045a8: 68bb ldr r3, [r7, #8] - 80045aa: 6013 str r3, [r2, #0] + 8005122: 4a08 ldr r2, [pc, #32] ; (8005144 ) + 8005124: 68bb ldr r3, [r7, #8] + 8005126: 6013 str r3, [r2, #0] } - 80045ac: bf00 nop - 80045ae: 3710 adds r7, #16 - 80045b0: 46bd mov sp, r7 - 80045b2: bd80 pop {r7, pc} - 80045b4: 20000d98 .word 0x20000d98 - 80045b8: 200008c0 .word 0x200008c0 - 80045bc: 20000d80 .word 0x20000d80 - 80045c0: 20000d50 .word 0x20000d50 - 80045c4: 20000d4c .word 0x20000d4c - 80045c8: 20000db4 .word 0x20000db4 + 8005128: bf00 nop + 800512a: 3710 adds r7, #16 + 800512c: 46bd mov sp, r7 + 800512e: bd80 pop {r7, pc} + 8005130: 20000de8 .word 0x20000de8 + 8005134: 20000910 .word 0x20000910 + 8005138: 20000dd0 .word 0x20000dd0 + 800513c: 20000da0 .word 0x20000da0 + 8005140: 20000d9c .word 0x20000d9c + 8005144: 20000e04 .word 0x20000e04 -080045cc : +08005148 : TimerCallbackFunction_t pxCallbackFunction, Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*-----------------------------------------------------------*/ BaseType_t xTimerCreateTimerTask( void ) { - 80045cc: b580 push {r7, lr} - 80045ce: b08a sub sp, #40 ; 0x28 - 80045d0: af04 add r7, sp, #16 + 8005148: b580 push {r7, lr} + 800514a: b08a sub sp, #40 ; 0x28 + 800514c: af04 add r7, sp, #16 BaseType_t xReturn = pdFAIL; - 80045d2: 2300 movs r3, #0 - 80045d4: 617b str r3, [r7, #20] + 800514e: 2300 movs r3, #0 + 8005150: 617b str r3, [r7, #20] /* This function is called when the scheduler is started if configUSE_TIMERS is set to 1. Check that the infrastructure used by the timer service task has been created/initialised. If timers have already been created then the initialisation will already have been performed. */ prvCheckForValidListAndQueue(); - 80045d6: f000 fb07 bl 8004be8 + 8005152: f000 fb07 bl 8005764 if( xTimerQueue != NULL ) - 80045da: 4b1c ldr r3, [pc, #112] ; (800464c ) - 80045dc: 681b ldr r3, [r3, #0] - 80045de: 2b00 cmp r3, #0 - 80045e0: d021 beq.n 8004626 + 8005156: 4b1c ldr r3, [pc, #112] ; (80051c8 ) + 8005158: 681b ldr r3, [r3, #0] + 800515a: 2b00 cmp r3, #0 + 800515c: d021 beq.n 80051a2 { #if( configSUPPORT_STATIC_ALLOCATION == 1 ) { StaticTask_t *pxTimerTaskTCBBuffer = NULL; - 80045e2: 2300 movs r3, #0 - 80045e4: 60fb str r3, [r7, #12] + 800515e: 2300 movs r3, #0 + 8005160: 60fb str r3, [r7, #12] StackType_t *pxTimerTaskStackBuffer = NULL; - 80045e6: 2300 movs r3, #0 - 80045e8: 60bb str r3, [r7, #8] + 8005162: 2300 movs r3, #0 + 8005164: 60bb str r3, [r7, #8] uint32_t ulTimerTaskStackSize; vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize ); - 80045ea: 1d3a adds r2, r7, #4 - 80045ec: f107 0108 add.w r1, r7, #8 - 80045f0: f107 030c add.w r3, r7, #12 - 80045f4: 4618 mov r0, r3 - 80045f6: f7fe fb07 bl 8002c08 + 8005166: 1d3a adds r2, r7, #4 + 8005168: f107 0108 add.w r1, r7, #8 + 800516c: f107 030c add.w r3, r7, #12 + 8005170: 4618 mov r0, r3 + 8005172: f7fe fb07 bl 8003784 xTimerTaskHandle = xTaskCreateStatic( prvTimerTask, - 80045fa: 6879 ldr r1, [r7, #4] - 80045fc: 68bb ldr r3, [r7, #8] - 80045fe: 68fa ldr r2, [r7, #12] - 8004600: 9202 str r2, [sp, #8] - 8004602: 9301 str r3, [sp, #4] - 8004604: 2302 movs r3, #2 - 8004606: 9300 str r3, [sp, #0] - 8004608: 2300 movs r3, #0 - 800460a: 460a mov r2, r1 - 800460c: 4910 ldr r1, [pc, #64] ; (8004650 ) - 800460e: 4811 ldr r0, [pc, #68] ; (8004654 ) - 8004610: f7ff f8b4 bl 800377c - 8004614: 4603 mov r3, r0 - 8004616: 4a10 ldr r2, [pc, #64] ; (8004658 ) - 8004618: 6013 str r3, [r2, #0] + 8005176: 6879 ldr r1, [r7, #4] + 8005178: 68bb ldr r3, [r7, #8] + 800517a: 68fa ldr r2, [r7, #12] + 800517c: 9202 str r2, [sp, #8] + 800517e: 9301 str r3, [sp, #4] + 8005180: 2302 movs r3, #2 + 8005182: 9300 str r3, [sp, #0] + 8005184: 2300 movs r3, #0 + 8005186: 460a mov r2, r1 + 8005188: 4910 ldr r1, [pc, #64] ; (80051cc ) + 800518a: 4811 ldr r0, [pc, #68] ; (80051d0 ) + 800518c: f7ff f8b4 bl 80042f8 + 8005190: 4603 mov r3, r0 + 8005192: 4a10 ldr r2, [pc, #64] ; (80051d4 ) + 8005194: 6013 str r3, [r2, #0] NULL, ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT, pxTimerTaskStackBuffer, pxTimerTaskTCBBuffer ); if( xTimerTaskHandle != NULL ) - 800461a: 4b0f ldr r3, [pc, #60] ; (8004658 ) - 800461c: 681b ldr r3, [r3, #0] - 800461e: 2b00 cmp r3, #0 - 8004620: d001 beq.n 8004626 + 8005196: 4b0f ldr r3, [pc, #60] ; (80051d4 ) + 8005198: 681b ldr r3, [r3, #0] + 800519a: 2b00 cmp r3, #0 + 800519c: d001 beq.n 80051a2 { xReturn = pdPASS; - 8004622: 2301 movs r3, #1 - 8004624: 617b str r3, [r7, #20] + 800519e: 2301 movs r3, #1 + 80051a0: 617b str r3, [r7, #20] else { mtCOVERAGE_TEST_MARKER(); } configASSERT( xReturn ); - 8004626: 697b ldr r3, [r7, #20] - 8004628: 2b00 cmp r3, #0 - 800462a: d10a bne.n 8004642 + 80051a2: 697b ldr r3, [r7, #20] + 80051a4: 2b00 cmp r3, #0 + 80051a6: d10a bne.n 80051be __asm volatile - 800462c: f04f 0350 mov.w r3, #80 ; 0x50 - 8004630: f383 8811 msr BASEPRI, r3 - 8004634: f3bf 8f6f isb sy - 8004638: f3bf 8f4f dsb sy - 800463c: 613b str r3, [r7, #16] + 80051a8: f04f 0350 mov.w r3, #80 ; 0x50 + 80051ac: f383 8811 msr BASEPRI, r3 + 80051b0: f3bf 8f6f isb sy + 80051b4: f3bf 8f4f dsb sy + 80051b8: 613b str r3, [r7, #16] } - 800463e: bf00 nop - 8004640: e7fe b.n 8004640 + 80051ba: bf00 nop + 80051bc: e7fe b.n 80051bc return xReturn; - 8004642: 697b ldr r3, [r7, #20] + 80051be: 697b ldr r3, [r7, #20] } - 8004644: 4618 mov r0, r3 - 8004646: 3718 adds r7, #24 - 8004648: 46bd mov sp, r7 - 800464a: bd80 pop {r7, pc} - 800464c: 20000df0 .word 0x20000df0 - 8004650: 080056e8 .word 0x080056e8 - 8004654: 08004791 .word 0x08004791 - 8004658: 20000df4 .word 0x20000df4 + 80051c0: 4618 mov r0, r3 + 80051c2: 3718 adds r7, #24 + 80051c4: 46bd mov sp, r7 + 80051c6: bd80 pop {r7, pc} + 80051c8: 20000e40 .word 0x20000e40 + 80051cc: 08006284 .word 0x08006284 + 80051d0: 0800530d .word 0x0800530d + 80051d4: 20000e44 .word 0x20000e44 -0800465c : +080051d8 : } } /*-----------------------------------------------------------*/ BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) { - 800465c: b580 push {r7, lr} - 800465e: b08a sub sp, #40 ; 0x28 - 8004660: af00 add r7, sp, #0 - 8004662: 60f8 str r0, [r7, #12] - 8004664: 60b9 str r1, [r7, #8] - 8004666: 607a str r2, [r7, #4] - 8004668: 603b str r3, [r7, #0] + 80051d8: b580 push {r7, lr} + 80051da: b08a sub sp, #40 ; 0x28 + 80051dc: af00 add r7, sp, #0 + 80051de: 60f8 str r0, [r7, #12] + 80051e0: 60b9 str r1, [r7, #8] + 80051e2: 607a str r2, [r7, #4] + 80051e4: 603b str r3, [r7, #0] BaseType_t xReturn = pdFAIL; - 800466a: 2300 movs r3, #0 - 800466c: 627b str r3, [r7, #36] ; 0x24 + 80051e6: 2300 movs r3, #0 + 80051e8: 627b str r3, [r7, #36] ; 0x24 DaemonTaskMessage_t xMessage; configASSERT( xTimer ); - 800466e: 68fb ldr r3, [r7, #12] - 8004670: 2b00 cmp r3, #0 - 8004672: d10a bne.n 800468a + 80051ea: 68fb ldr r3, [r7, #12] + 80051ec: 2b00 cmp r3, #0 + 80051ee: d10a bne.n 8005206 __asm volatile - 8004674: f04f 0350 mov.w r3, #80 ; 0x50 - 8004678: f383 8811 msr BASEPRI, r3 - 800467c: f3bf 8f6f isb sy - 8004680: f3bf 8f4f dsb sy - 8004684: 623b str r3, [r7, #32] + 80051f0: f04f 0350 mov.w r3, #80 ; 0x50 + 80051f4: f383 8811 msr BASEPRI, r3 + 80051f8: f3bf 8f6f isb sy + 80051fc: f3bf 8f4f dsb sy + 8005200: 623b str r3, [r7, #32] } - 8004686: bf00 nop - 8004688: e7fe b.n 8004688 + 8005202: bf00 nop + 8005204: e7fe b.n 8005204 /* Send a message to the timer service task to perform a particular action on a particular timer definition. */ if( xTimerQueue != NULL ) - 800468a: 4b1a ldr r3, [pc, #104] ; (80046f4 ) - 800468c: 681b ldr r3, [r3, #0] - 800468e: 2b00 cmp r3, #0 - 8004690: d02a beq.n 80046e8 + 8005206: 4b1a ldr r3, [pc, #104] ; (8005270 ) + 8005208: 681b ldr r3, [r3, #0] + 800520a: 2b00 cmp r3, #0 + 800520c: d02a beq.n 8005264 { /* Send a command to the timer service task to start the xTimer timer. */ xMessage.xMessageID = xCommandID; - 8004692: 68bb ldr r3, [r7, #8] - 8004694: 613b str r3, [r7, #16] + 800520e: 68bb ldr r3, [r7, #8] + 8005210: 613b str r3, [r7, #16] xMessage.u.xTimerParameters.xMessageValue = xOptionalValue; - 8004696: 687b ldr r3, [r7, #4] - 8004698: 617b str r3, [r7, #20] + 8005212: 687b ldr r3, [r7, #4] + 8005214: 617b str r3, [r7, #20] xMessage.u.xTimerParameters.pxTimer = xTimer; - 800469a: 68fb ldr r3, [r7, #12] - 800469c: 61bb str r3, [r7, #24] + 8005216: 68fb ldr r3, [r7, #12] + 8005218: 61bb str r3, [r7, #24] if( xCommandID < tmrFIRST_FROM_ISR_COMMAND ) - 800469e: 68bb ldr r3, [r7, #8] - 80046a0: 2b05 cmp r3, #5 - 80046a2: dc18 bgt.n 80046d6 + 800521a: 68bb ldr r3, [r7, #8] + 800521c: 2b05 cmp r3, #5 + 800521e: dc18 bgt.n 8005252 { if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING ) - 80046a4: f7ff feb2 bl 800440c - 80046a8: 4603 mov r3, r0 - 80046aa: 2b02 cmp r3, #2 - 80046ac: d109 bne.n 80046c2 + 8005220: f7ff feb2 bl 8004f88 + 8005224: 4603 mov r3, r0 + 8005226: 2b02 cmp r3, #2 + 8005228: d109 bne.n 800523e { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait ); - 80046ae: 4b11 ldr r3, [pc, #68] ; (80046f4 ) - 80046b0: 6818 ldr r0, [r3, #0] - 80046b2: f107 0110 add.w r1, r7, #16 - 80046b6: 2300 movs r3, #0 - 80046b8: 6b3a ldr r2, [r7, #48] ; 0x30 - 80046ba: f7fe fc77 bl 8002fac - 80046be: 6278 str r0, [r7, #36] ; 0x24 - 80046c0: e012 b.n 80046e8 + 800522a: 4b11 ldr r3, [pc, #68] ; (8005270 ) + 800522c: 6818 ldr r0, [r3, #0] + 800522e: f107 0110 add.w r1, r7, #16 + 8005232: 2300 movs r3, #0 + 8005234: 6b3a ldr r2, [r7, #48] ; 0x30 + 8005236: f7fe fc77 bl 8003b28 + 800523a: 6278 str r0, [r7, #36] ; 0x24 + 800523c: e012 b.n 8005264 } else { xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY ); - 80046c2: 4b0c ldr r3, [pc, #48] ; (80046f4 ) - 80046c4: 6818 ldr r0, [r3, #0] - 80046c6: f107 0110 add.w r1, r7, #16 - 80046ca: 2300 movs r3, #0 - 80046cc: 2200 movs r2, #0 - 80046ce: f7fe fc6d bl 8002fac - 80046d2: 6278 str r0, [r7, #36] ; 0x24 - 80046d4: e008 b.n 80046e8 + 800523e: 4b0c ldr r3, [pc, #48] ; (8005270 ) + 8005240: 6818 ldr r0, [r3, #0] + 8005242: f107 0110 add.w r1, r7, #16 + 8005246: 2300 movs r3, #0 + 8005248: 2200 movs r2, #0 + 800524a: f7fe fc6d bl 8003b28 + 800524e: 6278 str r0, [r7, #36] ; 0x24 + 8005250: e008 b.n 8005264 } } else { xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken ); - 80046d6: 4b07 ldr r3, [pc, #28] ; (80046f4 ) - 80046d8: 6818 ldr r0, [r3, #0] - 80046da: f107 0110 add.w r1, r7, #16 - 80046de: 2300 movs r3, #0 - 80046e0: 683a ldr r2, [r7, #0] - 80046e2: f7fe fd61 bl 80031a8 - 80046e6: 6278 str r0, [r7, #36] ; 0x24 + 8005252: 4b07 ldr r3, [pc, #28] ; (8005270 ) + 8005254: 6818 ldr r0, [r3, #0] + 8005256: f107 0110 add.w r1, r7, #16 + 800525a: 2300 movs r3, #0 + 800525c: 683a ldr r2, [r7, #0] + 800525e: f7fe fd61 bl 8003d24 + 8005262: 6278 str r0, [r7, #36] ; 0x24 else { mtCOVERAGE_TEST_MARKER(); } return xReturn; - 80046e8: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005264: 6a7b ldr r3, [r7, #36] ; 0x24 } - 80046ea: 4618 mov r0, r3 - 80046ec: 3728 adds r7, #40 ; 0x28 - 80046ee: 46bd mov sp, r7 - 80046f0: bd80 pop {r7, pc} - 80046f2: bf00 nop - 80046f4: 20000df0 .word 0x20000df0 + 8005266: 4618 mov r0, r3 + 8005268: 3728 adds r7, #40 ; 0x28 + 800526a: 46bd mov sp, r7 + 800526c: bd80 pop {r7, pc} + 800526e: bf00 nop + 8005270: 20000e40 .word 0x20000e40 -080046f8 : +08005274 : return pxTimer->pcTimerName; } /*-----------------------------------------------------------*/ static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) { - 80046f8: b580 push {r7, lr} - 80046fa: b088 sub sp, #32 - 80046fc: af02 add r7, sp, #8 - 80046fe: 6078 str r0, [r7, #4] - 8004700: 6039 str r1, [r7, #0] + 8005274: b580 push {r7, lr} + 8005276: b088 sub sp, #32 + 8005278: af02 add r7, sp, #8 + 800527a: 6078 str r0, [r7, #4] + 800527c: 6039 str r1, [r7, #0] BaseType_t xResult; Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8004702: 4b22 ldr r3, [pc, #136] ; (800478c ) - 8004704: 681b ldr r3, [r3, #0] - 8004706: 68db ldr r3, [r3, #12] - 8004708: 68db ldr r3, [r3, #12] - 800470a: 617b str r3, [r7, #20] + 800527e: 4b22 ldr r3, [pc, #136] ; (8005308 ) + 8005280: 681b ldr r3, [r3, #0] + 8005282: 68db ldr r3, [r3, #12] + 8005284: 68db ldr r3, [r3, #12] + 8005286: 617b str r3, [r7, #20] /* Remove the timer from the list of active timers. A check has already been performed to ensure the list is not empty. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); - 800470c: 697b ldr r3, [r7, #20] - 800470e: 3304 adds r3, #4 - 8004710: 4618 mov r0, r3 - 8004712: f7fe fb1d bl 8002d50 + 8005288: 697b ldr r3, [r7, #20] + 800528a: 3304 adds r3, #4 + 800528c: 4618 mov r0, r3 + 800528e: f7fe fb1d bl 80038cc traceTIMER_EXPIRED( pxTimer ); /* If the timer is an auto-reload timer then calculate the next expiry time and re-insert the timer in the list of active timers. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) - 8004716: 697b ldr r3, [r7, #20] - 8004718: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 - 800471c: f003 0304 and.w r3, r3, #4 - 8004720: 2b00 cmp r3, #0 - 8004722: d022 beq.n 800476a + 8005292: 697b ldr r3, [r7, #20] + 8005294: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 8005298: f003 0304 and.w r3, r3, #4 + 800529c: 2b00 cmp r3, #0 + 800529e: d022 beq.n 80052e6 { /* The timer is inserted into a list using a time relative to anything other than the current time. It will therefore be inserted into the correct list relative to the time this task thinks it is now. */ if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE ) - 8004724: 697b ldr r3, [r7, #20] - 8004726: 699a ldr r2, [r3, #24] - 8004728: 687b ldr r3, [r7, #4] - 800472a: 18d1 adds r1, r2, r3 - 800472c: 687b ldr r3, [r7, #4] - 800472e: 683a ldr r2, [r7, #0] - 8004730: 6978 ldr r0, [r7, #20] - 8004732: f000 f8d1 bl 80048d8 - 8004736: 4603 mov r3, r0 - 8004738: 2b00 cmp r3, #0 - 800473a: d01f beq.n 800477c + 80052a0: 697b ldr r3, [r7, #20] + 80052a2: 699a ldr r2, [r3, #24] + 80052a4: 687b ldr r3, [r7, #4] + 80052a6: 18d1 adds r1, r2, r3 + 80052a8: 687b ldr r3, [r7, #4] + 80052aa: 683a ldr r2, [r7, #0] + 80052ac: 6978 ldr r0, [r7, #20] + 80052ae: f000 f8d1 bl 8005454 + 80052b2: 4603 mov r3, r0 + 80052b4: 2b00 cmp r3, #0 + 80052b6: d01f beq.n 80052f8 { /* The timer expired before it was added to the active timer list. Reload it now. */ xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); - 800473c: 2300 movs r3, #0 - 800473e: 9300 str r3, [sp, #0] - 8004740: 2300 movs r3, #0 - 8004742: 687a ldr r2, [r7, #4] - 8004744: 2100 movs r1, #0 - 8004746: 6978 ldr r0, [r7, #20] - 8004748: f7ff ff88 bl 800465c - 800474c: 6138 str r0, [r7, #16] + 80052b8: 2300 movs r3, #0 + 80052ba: 9300 str r3, [sp, #0] + 80052bc: 2300 movs r3, #0 + 80052be: 687a ldr r2, [r7, #4] + 80052c0: 2100 movs r1, #0 + 80052c2: 6978 ldr r0, [r7, #20] + 80052c4: f7ff ff88 bl 80051d8 + 80052c8: 6138 str r0, [r7, #16] configASSERT( xResult ); - 800474e: 693b ldr r3, [r7, #16] - 8004750: 2b00 cmp r3, #0 - 8004752: d113 bne.n 800477c + 80052ca: 693b ldr r3, [r7, #16] + 80052cc: 2b00 cmp r3, #0 + 80052ce: d113 bne.n 80052f8 __asm volatile - 8004754: f04f 0350 mov.w r3, #80 ; 0x50 - 8004758: f383 8811 msr BASEPRI, r3 - 800475c: f3bf 8f6f isb sy - 8004760: f3bf 8f4f dsb sy - 8004764: 60fb str r3, [r7, #12] + 80052d0: f04f 0350 mov.w r3, #80 ; 0x50 + 80052d4: f383 8811 msr BASEPRI, r3 + 80052d8: f3bf 8f6f isb sy + 80052dc: f3bf 8f4f dsb sy + 80052e0: 60fb str r3, [r7, #12] } - 8004766: bf00 nop - 8004768: e7fe b.n 8004768 + 80052e2: bf00 nop + 80052e4: e7fe b.n 80052e4 mtCOVERAGE_TEST_MARKER(); } } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; - 800476a: 697b ldr r3, [r7, #20] - 800476c: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 - 8004770: f023 0301 bic.w r3, r3, #1 - 8004774: b2da uxtb r2, r3 - 8004776: 697b ldr r3, [r7, #20] - 8004778: f883 2028 strb.w r2, [r3, #40] ; 0x28 + 80052e6: 697b ldr r3, [r7, #20] + 80052e8: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 80052ec: f023 0301 bic.w r3, r3, #1 + 80052f0: b2da uxtb r2, r3 + 80052f2: 697b ldr r3, [r7, #20] + 80052f4: f883 2028 strb.w r2, [r3, #40] ; 0x28 mtCOVERAGE_TEST_MARKER(); } /* Call the timer callback. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); - 800477c: 697b ldr r3, [r7, #20] - 800477e: 6a1b ldr r3, [r3, #32] - 8004780: 6978 ldr r0, [r7, #20] - 8004782: 4798 blx r3 + 80052f8: 697b ldr r3, [r7, #20] + 80052fa: 6a1b ldr r3, [r3, #32] + 80052fc: 6978 ldr r0, [r7, #20] + 80052fe: 4798 blx r3 } - 8004784: bf00 nop - 8004786: 3718 adds r7, #24 - 8004788: 46bd mov sp, r7 - 800478a: bd80 pop {r7, pc} - 800478c: 20000de8 .word 0x20000de8 + 8005300: bf00 nop + 8005302: 3718 adds r7, #24 + 8005304: 46bd mov sp, r7 + 8005306: bd80 pop {r7, pc} + 8005308: 20000e38 .word 0x20000e38 -08004790 : +0800530c : /*-----------------------------------------------------------*/ static portTASK_FUNCTION( prvTimerTask, pvParameters ) { - 8004790: b580 push {r7, lr} - 8004792: b084 sub sp, #16 - 8004794: af00 add r7, sp, #0 - 8004796: 6078 str r0, [r7, #4] + 800530c: b580 push {r7, lr} + 800530e: b084 sub sp, #16 + 8005310: af00 add r7, sp, #0 + 8005312: 6078 str r0, [r7, #4] for( ;; ) { /* Query the timers list to see if it contains any timers, and if so, obtain the time at which the next timer will expire. */ xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); - 8004798: f107 0308 add.w r3, r7, #8 - 800479c: 4618 mov r0, r3 - 800479e: f000 f857 bl 8004850 - 80047a2: 60f8 str r0, [r7, #12] + 8005314: f107 0308 add.w r3, r7, #8 + 8005318: 4618 mov r0, r3 + 800531a: f000 f857 bl 80053cc + 800531e: 60f8 str r0, [r7, #12] /* If a timer has expired, process it. Otherwise, block this task until either a timer does expire, or a command is received. */ prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty ); - 80047a4: 68bb ldr r3, [r7, #8] - 80047a6: 4619 mov r1, r3 - 80047a8: 68f8 ldr r0, [r7, #12] - 80047aa: f000 f803 bl 80047b4 + 8005320: 68bb ldr r3, [r7, #8] + 8005322: 4619 mov r1, r3 + 8005324: 68f8 ldr r0, [r7, #12] + 8005326: f000 f803 bl 8005330 /* Empty the command queue. */ prvProcessReceivedCommands(); - 80047ae: f000 f8d5 bl 800495c + 800532a: f000 f8d5 bl 80054d8 xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty ); - 80047b2: e7f1 b.n 8004798 + 800532e: e7f1 b.n 8005314 -080047b4 : +08005330 : } } /*-----------------------------------------------------------*/ static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) { - 80047b4: b580 push {r7, lr} - 80047b6: b084 sub sp, #16 - 80047b8: af00 add r7, sp, #0 - 80047ba: 6078 str r0, [r7, #4] - 80047bc: 6039 str r1, [r7, #0] + 8005330: b580 push {r7, lr} + 8005332: b084 sub sp, #16 + 8005334: af00 add r7, sp, #0 + 8005336: 6078 str r0, [r7, #4] + 8005338: 6039 str r1, [r7, #0] TickType_t xTimeNow; BaseType_t xTimerListsWereSwitched; vTaskSuspendAll(); - 80047be: f7ff fa39 bl 8003c34 + 800533a: f7ff fa39 bl 80047b0 /* Obtain the time now to make an assessment as to whether the timer has expired or not. If obtaining the time causes the lists to switch then don't process this timer as any timers that remained in the list when the lists were switched will have been processed within the prvSampleTimeNow() function. */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); - 80047c2: f107 0308 add.w r3, r7, #8 - 80047c6: 4618 mov r0, r3 - 80047c8: f000 f866 bl 8004898 - 80047cc: 60f8 str r0, [r7, #12] + 800533e: f107 0308 add.w r3, r7, #8 + 8005342: 4618 mov r0, r3 + 8005344: f000 f866 bl 8005414 + 8005348: 60f8 str r0, [r7, #12] if( xTimerListsWereSwitched == pdFALSE ) - 80047ce: 68bb ldr r3, [r7, #8] - 80047d0: 2b00 cmp r3, #0 - 80047d2: d130 bne.n 8004836 + 800534a: 68bb ldr r3, [r7, #8] + 800534c: 2b00 cmp r3, #0 + 800534e: d130 bne.n 80053b2 { /* The tick count has not overflowed, has the timer expired? */ if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) ) - 80047d4: 683b ldr r3, [r7, #0] - 80047d6: 2b00 cmp r3, #0 - 80047d8: d10a bne.n 80047f0 - 80047da: 687a ldr r2, [r7, #4] - 80047dc: 68fb ldr r3, [r7, #12] - 80047de: 429a cmp r2, r3 - 80047e0: d806 bhi.n 80047f0 + 8005350: 683b ldr r3, [r7, #0] + 8005352: 2b00 cmp r3, #0 + 8005354: d10a bne.n 800536c + 8005356: 687a ldr r2, [r7, #4] + 8005358: 68fb ldr r3, [r7, #12] + 800535a: 429a cmp r2, r3 + 800535c: d806 bhi.n 800536c { ( void ) xTaskResumeAll(); - 80047e2: f7ff fa35 bl 8003c50 + 800535e: f7ff fa35 bl 80047cc prvProcessExpiredTimer( xNextExpireTime, xTimeNow ); - 80047e6: 68f9 ldr r1, [r7, #12] - 80047e8: 6878 ldr r0, [r7, #4] - 80047ea: f7ff ff85 bl 80046f8 + 8005362: 68f9 ldr r1, [r7, #12] + 8005364: 6878 ldr r0, [r7, #4] + 8005366: f7ff ff85 bl 8005274 else { ( void ) xTaskResumeAll(); } } } - 80047ee: e024 b.n 800483a + 800536a: e024 b.n 80053b6 if( xListWasEmpty != pdFALSE ) - 80047f0: 683b ldr r3, [r7, #0] - 80047f2: 2b00 cmp r3, #0 - 80047f4: d008 beq.n 8004808 + 800536c: 683b ldr r3, [r7, #0] + 800536e: 2b00 cmp r3, #0 + 8005370: d008 beq.n 8005384 xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList ); - 80047f6: 4b13 ldr r3, [pc, #76] ; (8004844 ) - 80047f8: 681b ldr r3, [r3, #0] - 80047fa: 681b ldr r3, [r3, #0] - 80047fc: 2b00 cmp r3, #0 - 80047fe: d101 bne.n 8004804 - 8004800: 2301 movs r3, #1 - 8004802: e000 b.n 8004806 - 8004804: 2300 movs r3, #0 - 8004806: 603b str r3, [r7, #0] + 8005372: 4b13 ldr r3, [pc, #76] ; (80053c0 ) + 8005374: 681b ldr r3, [r3, #0] + 8005376: 681b ldr r3, [r3, #0] + 8005378: 2b00 cmp r3, #0 + 800537a: d101 bne.n 8005380 + 800537c: 2301 movs r3, #1 + 800537e: e000 b.n 8005382 + 8005380: 2300 movs r3, #0 + 8005382: 603b str r3, [r7, #0] vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty ); - 8004808: 4b0f ldr r3, [pc, #60] ; (8004848 ) - 800480a: 6818 ldr r0, [r3, #0] - 800480c: 687a ldr r2, [r7, #4] - 800480e: 68fb ldr r3, [r7, #12] - 8004810: 1ad3 subs r3, r2, r3 - 8004812: 683a ldr r2, [r7, #0] - 8004814: 4619 mov r1, r3 - 8004816: f7fe ff7d bl 8003714 + 8005384: 4b0f ldr r3, [pc, #60] ; (80053c4 ) + 8005386: 6818 ldr r0, [r3, #0] + 8005388: 687a ldr r2, [r7, #4] + 800538a: 68fb ldr r3, [r7, #12] + 800538c: 1ad3 subs r3, r2, r3 + 800538e: 683a ldr r2, [r7, #0] + 8005390: 4619 mov r1, r3 + 8005392: f7fe ff7d bl 8004290 if( xTaskResumeAll() == pdFALSE ) - 800481a: f7ff fa19 bl 8003c50 - 800481e: 4603 mov r3, r0 - 8004820: 2b00 cmp r3, #0 - 8004822: d10a bne.n 800483a + 8005396: f7ff fa19 bl 80047cc + 800539a: 4603 mov r3, r0 + 800539c: 2b00 cmp r3, #0 + 800539e: d10a bne.n 80053b6 portYIELD_WITHIN_API(); - 8004824: 4b09 ldr r3, [pc, #36] ; (800484c ) - 8004826: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 800482a: 601a str r2, [r3, #0] - 800482c: f3bf 8f4f dsb sy - 8004830: f3bf 8f6f isb sy + 80053a0: 4b09 ldr r3, [pc, #36] ; (80053c8 ) + 80053a2: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 80053a6: 601a str r2, [r3, #0] + 80053a8: f3bf 8f4f dsb sy + 80053ac: f3bf 8f6f isb sy } - 8004834: e001 b.n 800483a + 80053b0: e001 b.n 80053b6 ( void ) xTaskResumeAll(); - 8004836: f7ff fa0b bl 8003c50 + 80053b2: f7ff fa0b bl 80047cc } - 800483a: bf00 nop - 800483c: 3710 adds r7, #16 - 800483e: 46bd mov sp, r7 - 8004840: bd80 pop {r7, pc} - 8004842: bf00 nop - 8004844: 20000dec .word 0x20000dec - 8004848: 20000df0 .word 0x20000df0 - 800484c: e000ed04 .word 0xe000ed04 + 80053b6: bf00 nop + 80053b8: 3710 adds r7, #16 + 80053ba: 46bd mov sp, r7 + 80053bc: bd80 pop {r7, pc} + 80053be: bf00 nop + 80053c0: 20000e3c .word 0x20000e3c + 80053c4: 20000e40 .word 0x20000e40 + 80053c8: e000ed04 .word 0xe000ed04 -08004850 : +080053cc : /*-----------------------------------------------------------*/ static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) { - 8004850: b480 push {r7} - 8004852: b085 sub sp, #20 - 8004854: af00 add r7, sp, #0 - 8004856: 6078 str r0, [r7, #4] + 80053cc: b480 push {r7} + 80053ce: b085 sub sp, #20 + 80053d0: af00 add r7, sp, #0 + 80053d2: 6078 str r0, [r7, #4] the timer with the nearest expiry time will expire. If there are no active timers then just set the next expire time to 0. That will cause this task to unblock when the tick count overflows, at which point the timer lists will be switched and the next expiry time can be re-assessed. */ *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList ); - 8004858: 4b0e ldr r3, [pc, #56] ; (8004894 ) - 800485a: 681b ldr r3, [r3, #0] - 800485c: 681b ldr r3, [r3, #0] - 800485e: 2b00 cmp r3, #0 - 8004860: d101 bne.n 8004866 - 8004862: 2201 movs r2, #1 - 8004864: e000 b.n 8004868 - 8004866: 2200 movs r2, #0 - 8004868: 687b ldr r3, [r7, #4] - 800486a: 601a str r2, [r3, #0] + 80053d4: 4b0e ldr r3, [pc, #56] ; (8005410 ) + 80053d6: 681b ldr r3, [r3, #0] + 80053d8: 681b ldr r3, [r3, #0] + 80053da: 2b00 cmp r3, #0 + 80053dc: d101 bne.n 80053e2 + 80053de: 2201 movs r2, #1 + 80053e0: e000 b.n 80053e4 + 80053e2: 2200 movs r2, #0 + 80053e4: 687b ldr r3, [r7, #4] + 80053e6: 601a str r2, [r3, #0] if( *pxListWasEmpty == pdFALSE ) - 800486c: 687b ldr r3, [r7, #4] - 800486e: 681b ldr r3, [r3, #0] - 8004870: 2b00 cmp r3, #0 - 8004872: d105 bne.n 8004880 + 80053e8: 687b ldr r3, [r7, #4] + 80053ea: 681b ldr r3, [r3, #0] + 80053ec: 2b00 cmp r3, #0 + 80053ee: d105 bne.n 80053fc { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); - 8004874: 4b07 ldr r3, [pc, #28] ; (8004894 ) - 8004876: 681b ldr r3, [r3, #0] - 8004878: 68db ldr r3, [r3, #12] - 800487a: 681b ldr r3, [r3, #0] - 800487c: 60fb str r3, [r7, #12] - 800487e: e001 b.n 8004884 + 80053f0: 4b07 ldr r3, [pc, #28] ; (8005410 ) + 80053f2: 681b ldr r3, [r3, #0] + 80053f4: 68db ldr r3, [r3, #12] + 80053f6: 681b ldr r3, [r3, #0] + 80053f8: 60fb str r3, [r7, #12] + 80053fa: e001 b.n 8005400 } else { /* Ensure the task unblocks when the tick count rolls over. */ xNextExpireTime = ( TickType_t ) 0U; - 8004880: 2300 movs r3, #0 - 8004882: 60fb str r3, [r7, #12] + 80053fc: 2300 movs r3, #0 + 80053fe: 60fb str r3, [r7, #12] } return xNextExpireTime; - 8004884: 68fb ldr r3, [r7, #12] + 8005400: 68fb ldr r3, [r7, #12] } - 8004886: 4618 mov r0, r3 - 8004888: 3714 adds r7, #20 - 800488a: 46bd mov sp, r7 - 800488c: f85d 7b04 ldr.w r7, [sp], #4 - 8004890: 4770 bx lr - 8004892: bf00 nop - 8004894: 20000de8 .word 0x20000de8 + 8005402: 4618 mov r0, r3 + 8005404: 3714 adds r7, #20 + 8005406: 46bd mov sp, r7 + 8005408: f85d 7b04 ldr.w r7, [sp], #4 + 800540c: 4770 bx lr + 800540e: bf00 nop + 8005410: 20000e38 .word 0x20000e38 -08004898 : +08005414 : /*-----------------------------------------------------------*/ static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) { - 8004898: b580 push {r7, lr} - 800489a: b084 sub sp, #16 - 800489c: af00 add r7, sp, #0 - 800489e: 6078 str r0, [r7, #4] + 8005414: b580 push {r7, lr} + 8005416: b084 sub sp, #16 + 8005418: af00 add r7, sp, #0 + 800541a: 6078 str r0, [r7, #4] TickType_t xTimeNow; PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */ xTimeNow = xTaskGetTickCount(); - 80048a0: f7ff fa74 bl 8003d8c - 80048a4: 60f8 str r0, [r7, #12] + 800541c: f7ff fa74 bl 8004908 + 8005420: 60f8 str r0, [r7, #12] if( xTimeNow < xLastTime ) - 80048a6: 4b0b ldr r3, [pc, #44] ; (80048d4 ) - 80048a8: 681b ldr r3, [r3, #0] - 80048aa: 68fa ldr r2, [r7, #12] - 80048ac: 429a cmp r2, r3 - 80048ae: d205 bcs.n 80048bc + 8005422: 4b0b ldr r3, [pc, #44] ; (8005450 ) + 8005424: 681b ldr r3, [r3, #0] + 8005426: 68fa ldr r2, [r7, #12] + 8005428: 429a cmp r2, r3 + 800542a: d205 bcs.n 8005438 { prvSwitchTimerLists(); - 80048b0: f000 f936 bl 8004b20 + 800542c: f000 f936 bl 800569c *pxTimerListsWereSwitched = pdTRUE; - 80048b4: 687b ldr r3, [r7, #4] - 80048b6: 2201 movs r2, #1 - 80048b8: 601a str r2, [r3, #0] - 80048ba: e002 b.n 80048c2 + 8005430: 687b ldr r3, [r7, #4] + 8005432: 2201 movs r2, #1 + 8005434: 601a str r2, [r3, #0] + 8005436: e002 b.n 800543e } else { *pxTimerListsWereSwitched = pdFALSE; - 80048bc: 687b ldr r3, [r7, #4] - 80048be: 2200 movs r2, #0 - 80048c0: 601a str r2, [r3, #0] + 8005438: 687b ldr r3, [r7, #4] + 800543a: 2200 movs r2, #0 + 800543c: 601a str r2, [r3, #0] } xLastTime = xTimeNow; - 80048c2: 4a04 ldr r2, [pc, #16] ; (80048d4 ) - 80048c4: 68fb ldr r3, [r7, #12] - 80048c6: 6013 str r3, [r2, #0] + 800543e: 4a04 ldr r2, [pc, #16] ; (8005450 ) + 8005440: 68fb ldr r3, [r7, #12] + 8005442: 6013 str r3, [r2, #0] return xTimeNow; - 80048c8: 68fb ldr r3, [r7, #12] + 8005444: 68fb ldr r3, [r7, #12] } - 80048ca: 4618 mov r0, r3 - 80048cc: 3710 adds r7, #16 - 80048ce: 46bd mov sp, r7 - 80048d0: bd80 pop {r7, pc} - 80048d2: bf00 nop - 80048d4: 20000df8 .word 0x20000df8 + 8005446: 4618 mov r0, r3 + 8005448: 3710 adds r7, #16 + 800544a: 46bd mov sp, r7 + 800544c: bd80 pop {r7, pc} + 800544e: bf00 nop + 8005450: 20000e48 .word 0x20000e48 -080048d8 : +08005454 : /*-----------------------------------------------------------*/ static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) { - 80048d8: b580 push {r7, lr} - 80048da: b086 sub sp, #24 - 80048dc: af00 add r7, sp, #0 - 80048de: 60f8 str r0, [r7, #12] - 80048e0: 60b9 str r1, [r7, #8] - 80048e2: 607a str r2, [r7, #4] - 80048e4: 603b str r3, [r7, #0] + 8005454: b580 push {r7, lr} + 8005456: b086 sub sp, #24 + 8005458: af00 add r7, sp, #0 + 800545a: 60f8 str r0, [r7, #12] + 800545c: 60b9 str r1, [r7, #8] + 800545e: 607a str r2, [r7, #4] + 8005460: 603b str r3, [r7, #0] BaseType_t xProcessTimerNow = pdFALSE; - 80048e6: 2300 movs r3, #0 - 80048e8: 617b str r3, [r7, #20] + 8005462: 2300 movs r3, #0 + 8005464: 617b str r3, [r7, #20] listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime ); - 80048ea: 68fb ldr r3, [r7, #12] - 80048ec: 68ba ldr r2, [r7, #8] - 80048ee: 605a str r2, [r3, #4] + 8005466: 68fb ldr r3, [r7, #12] + 8005468: 68ba ldr r2, [r7, #8] + 800546a: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); - 80048f0: 68fb ldr r3, [r7, #12] - 80048f2: 68fa ldr r2, [r7, #12] - 80048f4: 611a str r2, [r3, #16] + 800546c: 68fb ldr r3, [r7, #12] + 800546e: 68fa ldr r2, [r7, #12] + 8005470: 611a str r2, [r3, #16] if( xNextExpiryTime <= xTimeNow ) - 80048f6: 68ba ldr r2, [r7, #8] - 80048f8: 687b ldr r3, [r7, #4] - 80048fa: 429a cmp r2, r3 - 80048fc: d812 bhi.n 8004924 + 8005472: 68ba ldr r2, [r7, #8] + 8005474: 687b ldr r3, [r7, #4] + 8005476: 429a cmp r2, r3 + 8005478: d812 bhi.n 80054a0 { /* Has the expiry time elapsed between the command to start/reset a timer was issued, and the time the command was processed? */ if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */ - 80048fe: 687a ldr r2, [r7, #4] - 8004900: 683b ldr r3, [r7, #0] - 8004902: 1ad2 subs r2, r2, r3 - 8004904: 68fb ldr r3, [r7, #12] - 8004906: 699b ldr r3, [r3, #24] - 8004908: 429a cmp r2, r3 - 800490a: d302 bcc.n 8004912 + 800547a: 687a ldr r2, [r7, #4] + 800547c: 683b ldr r3, [r7, #0] + 800547e: 1ad2 subs r2, r2, r3 + 8005480: 68fb ldr r3, [r7, #12] + 8005482: 699b ldr r3, [r3, #24] + 8005484: 429a cmp r2, r3 + 8005486: d302 bcc.n 800548e { /* The time between a command being issued and the command being processed actually exceeds the timers period. */ xProcessTimerNow = pdTRUE; - 800490c: 2301 movs r3, #1 - 800490e: 617b str r3, [r7, #20] - 8004910: e01b b.n 800494a + 8005488: 2301 movs r3, #1 + 800548a: 617b str r3, [r7, #20] + 800548c: e01b b.n 80054c6 } else { vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) ); - 8004912: 4b10 ldr r3, [pc, #64] ; (8004954 ) - 8004914: 681a ldr r2, [r3, #0] - 8004916: 68fb ldr r3, [r7, #12] - 8004918: 3304 adds r3, #4 - 800491a: 4619 mov r1, r3 - 800491c: 4610 mov r0, r2 - 800491e: f7fe f9de bl 8002cde - 8004922: e012 b.n 800494a + 800548e: 4b10 ldr r3, [pc, #64] ; (80054d0 ) + 8005490: 681a ldr r2, [r3, #0] + 8005492: 68fb ldr r3, [r7, #12] + 8005494: 3304 adds r3, #4 + 8005496: 4619 mov r1, r3 + 8005498: 4610 mov r0, r2 + 800549a: f7fe f9de bl 800385a + 800549e: e012 b.n 80054c6 } } else { if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) ) - 8004924: 687a ldr r2, [r7, #4] - 8004926: 683b ldr r3, [r7, #0] - 8004928: 429a cmp r2, r3 - 800492a: d206 bcs.n 800493a - 800492c: 68ba ldr r2, [r7, #8] - 800492e: 683b ldr r3, [r7, #0] - 8004930: 429a cmp r2, r3 - 8004932: d302 bcc.n 800493a + 80054a0: 687a ldr r2, [r7, #4] + 80054a2: 683b ldr r3, [r7, #0] + 80054a4: 429a cmp r2, r3 + 80054a6: d206 bcs.n 80054b6 + 80054a8: 68ba ldr r2, [r7, #8] + 80054aa: 683b ldr r3, [r7, #0] + 80054ac: 429a cmp r2, r3 + 80054ae: d302 bcc.n 80054b6 { /* If, since the command was issued, the tick count has overflowed but the expiry time has not, then the timer must have already passed its expiry time and should be processed immediately. */ xProcessTimerNow = pdTRUE; - 8004934: 2301 movs r3, #1 - 8004936: 617b str r3, [r7, #20] - 8004938: e007 b.n 800494a + 80054b0: 2301 movs r3, #1 + 80054b2: 617b str r3, [r7, #20] + 80054b4: e007 b.n 80054c6 } else { vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); - 800493a: 4b07 ldr r3, [pc, #28] ; (8004958 ) - 800493c: 681a ldr r2, [r3, #0] - 800493e: 68fb ldr r3, [r7, #12] - 8004940: 3304 adds r3, #4 - 8004942: 4619 mov r1, r3 - 8004944: 4610 mov r0, r2 - 8004946: f7fe f9ca bl 8002cde + 80054b6: 4b07 ldr r3, [pc, #28] ; (80054d4 ) + 80054b8: 681a ldr r2, [r3, #0] + 80054ba: 68fb ldr r3, [r7, #12] + 80054bc: 3304 adds r3, #4 + 80054be: 4619 mov r1, r3 + 80054c0: 4610 mov r0, r2 + 80054c2: f7fe f9ca bl 800385a } } return xProcessTimerNow; - 800494a: 697b ldr r3, [r7, #20] + 80054c6: 697b ldr r3, [r7, #20] } - 800494c: 4618 mov r0, r3 - 800494e: 3718 adds r7, #24 - 8004950: 46bd mov sp, r7 - 8004952: bd80 pop {r7, pc} - 8004954: 20000dec .word 0x20000dec - 8004958: 20000de8 .word 0x20000de8 + 80054c8: 4618 mov r0, r3 + 80054ca: 3718 adds r7, #24 + 80054cc: 46bd mov sp, r7 + 80054ce: bd80 pop {r7, pc} + 80054d0: 20000e3c .word 0x20000e3c + 80054d4: 20000e38 .word 0x20000e38 -0800495c : +080054d8 : /*-----------------------------------------------------------*/ static void prvProcessReceivedCommands( void ) { - 800495c: b580 push {r7, lr} - 800495e: b08e sub sp, #56 ; 0x38 - 8004960: af02 add r7, sp, #8 + 80054d8: b580 push {r7, lr} + 80054da: b08e sub sp, #56 ; 0x38 + 80054dc: af02 add r7, sp, #8 DaemonTaskMessage_t xMessage; Timer_t *pxTimer; BaseType_t xTimerListsWereSwitched, xResult; TickType_t xTimeNow; while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ - 8004962: e0ca b.n 8004afa + 80054de: e0ca b.n 8005676 { #if ( INCLUDE_xTimerPendFunctionCall == 1 ) { /* Negative commands are pended function calls rather than timer commands. */ if( xMessage.xMessageID < ( BaseType_t ) 0 ) - 8004964: 687b ldr r3, [r7, #4] - 8004966: 2b00 cmp r3, #0 - 8004968: da18 bge.n 800499c + 80054e0: 687b ldr r3, [r7, #4] + 80054e2: 2b00 cmp r3, #0 + 80054e4: da18 bge.n 8005518 { const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters ); - 800496a: 1d3b adds r3, r7, #4 - 800496c: 3304 adds r3, #4 - 800496e: 62fb str r3, [r7, #44] ; 0x2c + 80054e6: 1d3b adds r3, r7, #4 + 80054e8: 3304 adds r3, #4 + 80054ea: 62fb str r3, [r7, #44] ; 0x2c /* The timer uses the xCallbackParameters member to request a callback be executed. Check the callback is not NULL. */ configASSERT( pxCallback ); - 8004970: 6afb ldr r3, [r7, #44] ; 0x2c - 8004972: 2b00 cmp r3, #0 - 8004974: d10a bne.n 800498c + 80054ec: 6afb ldr r3, [r7, #44] ; 0x2c + 80054ee: 2b00 cmp r3, #0 + 80054f0: d10a bne.n 8005508 __asm volatile - 8004976: f04f 0350 mov.w r3, #80 ; 0x50 - 800497a: f383 8811 msr BASEPRI, r3 - 800497e: f3bf 8f6f isb sy - 8004982: f3bf 8f4f dsb sy - 8004986: 61fb str r3, [r7, #28] + 80054f2: f04f 0350 mov.w r3, #80 ; 0x50 + 80054f6: f383 8811 msr BASEPRI, r3 + 80054fa: f3bf 8f6f isb sy + 80054fe: f3bf 8f4f dsb sy + 8005502: 61fb str r3, [r7, #28] } - 8004988: bf00 nop - 800498a: e7fe b.n 800498a + 8005504: bf00 nop + 8005506: e7fe b.n 8005506 /* Call the function. */ pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 ); - 800498c: 6afb ldr r3, [r7, #44] ; 0x2c - 800498e: 681b ldr r3, [r3, #0] - 8004990: 6afa ldr r2, [r7, #44] ; 0x2c - 8004992: 6850 ldr r0, [r2, #4] - 8004994: 6afa ldr r2, [r7, #44] ; 0x2c - 8004996: 6892 ldr r2, [r2, #8] - 8004998: 4611 mov r1, r2 - 800499a: 4798 blx r3 + 8005508: 6afb ldr r3, [r7, #44] ; 0x2c + 800550a: 681b ldr r3, [r3, #0] + 800550c: 6afa ldr r2, [r7, #44] ; 0x2c + 800550e: 6850 ldr r0, [r2, #4] + 8005510: 6afa ldr r2, [r7, #44] ; 0x2c + 8005512: 6892 ldr r2, [r2, #8] + 8005514: 4611 mov r1, r2 + 8005516: 4798 blx r3 } #endif /* INCLUDE_xTimerPendFunctionCall */ /* Commands that are positive are timer commands rather than pended function calls. */ if( xMessage.xMessageID >= ( BaseType_t ) 0 ) - 800499c: 687b ldr r3, [r7, #4] - 800499e: 2b00 cmp r3, #0 - 80049a0: f2c0 80ab blt.w 8004afa + 8005518: 687b ldr r3, [r7, #4] + 800551a: 2b00 cmp r3, #0 + 800551c: f2c0 80ab blt.w 8005676 { /* The messages uses the xTimerParameters member to work on a software timer. */ pxTimer = xMessage.u.xTimerParameters.pxTimer; - 80049a4: 68fb ldr r3, [r7, #12] - 80049a6: 62bb str r3, [r7, #40] ; 0x28 + 8005520: 68fb ldr r3, [r7, #12] + 8005522: 62bb str r3, [r7, #40] ; 0x28 if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */ - 80049a8: 6abb ldr r3, [r7, #40] ; 0x28 - 80049aa: 695b ldr r3, [r3, #20] - 80049ac: 2b00 cmp r3, #0 - 80049ae: d004 beq.n 80049ba + 8005524: 6abb ldr r3, [r7, #40] ; 0x28 + 8005526: 695b ldr r3, [r3, #20] + 8005528: 2b00 cmp r3, #0 + 800552a: d004 beq.n 8005536 { /* The timer is in a list, remove it. */ ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); - 80049b0: 6abb ldr r3, [r7, #40] ; 0x28 - 80049b2: 3304 adds r3, #4 - 80049b4: 4618 mov r0, r3 - 80049b6: f7fe f9cb bl 8002d50 + 800552c: 6abb ldr r3, [r7, #40] ; 0x28 + 800552e: 3304 adds r3, #4 + 8005530: 4618 mov r0, r3 + 8005532: f7fe f9cb bl 80038cc it must be present in the function call. prvSampleTimeNow() must be called after the message is received from xTimerQueue so there is no possibility of a higher priority task adding a message to the message queue with a time that is ahead of the timer daemon task (because it pre-empted the timer daemon task after the xTimeNow value was set). */ xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched ); - 80049ba: 463b mov r3, r7 - 80049bc: 4618 mov r0, r3 - 80049be: f7ff ff6b bl 8004898 - 80049c2: 6278 str r0, [r7, #36] ; 0x24 + 8005536: 463b mov r3, r7 + 8005538: 4618 mov r0, r3 + 800553a: f7ff ff6b bl 8005414 + 800553e: 6278 str r0, [r7, #36] ; 0x24 switch( xMessage.xMessageID ) - 80049c4: 687b ldr r3, [r7, #4] - 80049c6: 2b09 cmp r3, #9 - 80049c8: f200 8096 bhi.w 8004af8 - 80049cc: a201 add r2, pc, #4 ; (adr r2, 80049d4 ) - 80049ce: f852 f023 ldr.w pc, [r2, r3, lsl #2] - 80049d2: bf00 nop - 80049d4: 080049fd .word 0x080049fd - 80049d8: 080049fd .word 0x080049fd - 80049dc: 080049fd .word 0x080049fd - 80049e0: 08004a71 .word 0x08004a71 - 80049e4: 08004a85 .word 0x08004a85 - 80049e8: 08004acf .word 0x08004acf - 80049ec: 080049fd .word 0x080049fd - 80049f0: 080049fd .word 0x080049fd - 80049f4: 08004a71 .word 0x08004a71 - 80049f8: 08004a85 .word 0x08004a85 + 8005540: 687b ldr r3, [r7, #4] + 8005542: 2b09 cmp r3, #9 + 8005544: f200 8096 bhi.w 8005674 + 8005548: a201 add r2, pc, #4 ; (adr r2, 8005550 ) + 800554a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800554e: bf00 nop + 8005550: 08005579 .word 0x08005579 + 8005554: 08005579 .word 0x08005579 + 8005558: 08005579 .word 0x08005579 + 800555c: 080055ed .word 0x080055ed + 8005560: 08005601 .word 0x08005601 + 8005564: 0800564b .word 0x0800564b + 8005568: 08005579 .word 0x08005579 + 800556c: 08005579 .word 0x08005579 + 8005570: 080055ed .word 0x080055ed + 8005574: 08005601 .word 0x08005601 case tmrCOMMAND_START_FROM_ISR : case tmrCOMMAND_RESET : case tmrCOMMAND_RESET_FROM_ISR : case tmrCOMMAND_START_DONT_TRACE : /* Start or restart a timer. */ pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; - 80049fc: 6abb ldr r3, [r7, #40] ; 0x28 - 80049fe: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 - 8004a02: f043 0301 orr.w r3, r3, #1 - 8004a06: b2da uxtb r2, r3 - 8004a08: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a0a: f883 2028 strb.w r2, [r3, #40] ; 0x28 + 8005578: 6abb ldr r3, [r7, #40] ; 0x28 + 800557a: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 800557e: f043 0301 orr.w r3, r3, #1 + 8005582: b2da uxtb r2, r3 + 8005584: 6abb ldr r3, [r7, #40] ; 0x28 + 8005586: f883 2028 strb.w r2, [r3, #40] ; 0x28 if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE ) - 8004a0e: 68ba ldr r2, [r7, #8] - 8004a10: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a12: 699b ldr r3, [r3, #24] - 8004a14: 18d1 adds r1, r2, r3 - 8004a16: 68bb ldr r3, [r7, #8] - 8004a18: 6a7a ldr r2, [r7, #36] ; 0x24 - 8004a1a: 6ab8 ldr r0, [r7, #40] ; 0x28 - 8004a1c: f7ff ff5c bl 80048d8 - 8004a20: 4603 mov r3, r0 - 8004a22: 2b00 cmp r3, #0 - 8004a24: d069 beq.n 8004afa + 800558a: 68ba ldr r2, [r7, #8] + 800558c: 6abb ldr r3, [r7, #40] ; 0x28 + 800558e: 699b ldr r3, [r3, #24] + 8005590: 18d1 adds r1, r2, r3 + 8005592: 68bb ldr r3, [r7, #8] + 8005594: 6a7a ldr r2, [r7, #36] ; 0x24 + 8005596: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8005598: f7ff ff5c bl 8005454 + 800559c: 4603 mov r3, r0 + 800559e: 2b00 cmp r3, #0 + 80055a0: d069 beq.n 8005676 { /* The timer expired before it was added to the active timer list. Process it now. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); - 8004a26: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a28: 6a1b ldr r3, [r3, #32] - 8004a2a: 6ab8 ldr r0, [r7, #40] ; 0x28 - 8004a2c: 4798 blx r3 + 80055a2: 6abb ldr r3, [r7, #40] ; 0x28 + 80055a4: 6a1b ldr r3, [r3, #32] + 80055a6: 6ab8 ldr r0, [r7, #40] ; 0x28 + 80055a8: 4798 blx r3 traceTIMER_EXPIRED( pxTimer ); if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) - 8004a2e: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a30: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 - 8004a34: f003 0304 and.w r3, r3, #4 - 8004a38: 2b00 cmp r3, #0 - 8004a3a: d05e beq.n 8004afa + 80055aa: 6abb ldr r3, [r7, #40] ; 0x28 + 80055ac: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 80055b0: f003 0304 and.w r3, r3, #4 + 80055b4: 2b00 cmp r3, #0 + 80055b6: d05e beq.n 8005676 { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY ); - 8004a3c: 68ba ldr r2, [r7, #8] - 8004a3e: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a40: 699b ldr r3, [r3, #24] - 8004a42: 441a add r2, r3 - 8004a44: 2300 movs r3, #0 - 8004a46: 9300 str r3, [sp, #0] - 8004a48: 2300 movs r3, #0 - 8004a4a: 2100 movs r1, #0 - 8004a4c: 6ab8 ldr r0, [r7, #40] ; 0x28 - 8004a4e: f7ff fe05 bl 800465c - 8004a52: 6238 str r0, [r7, #32] + 80055b8: 68ba ldr r2, [r7, #8] + 80055ba: 6abb ldr r3, [r7, #40] ; 0x28 + 80055bc: 699b ldr r3, [r3, #24] + 80055be: 441a add r2, r3 + 80055c0: 2300 movs r3, #0 + 80055c2: 9300 str r3, [sp, #0] + 80055c4: 2300 movs r3, #0 + 80055c6: 2100 movs r1, #0 + 80055c8: 6ab8 ldr r0, [r7, #40] ; 0x28 + 80055ca: f7ff fe05 bl 80051d8 + 80055ce: 6238 str r0, [r7, #32] configASSERT( xResult ); - 8004a54: 6a3b ldr r3, [r7, #32] - 8004a56: 2b00 cmp r3, #0 - 8004a58: d14f bne.n 8004afa + 80055d0: 6a3b ldr r3, [r7, #32] + 80055d2: 2b00 cmp r3, #0 + 80055d4: d14f bne.n 8005676 __asm volatile - 8004a5a: f04f 0350 mov.w r3, #80 ; 0x50 - 8004a5e: f383 8811 msr BASEPRI, r3 - 8004a62: f3bf 8f6f isb sy - 8004a66: f3bf 8f4f dsb sy - 8004a6a: 61bb str r3, [r7, #24] + 80055d6: f04f 0350 mov.w r3, #80 ; 0x50 + 80055da: f383 8811 msr BASEPRI, r3 + 80055de: f3bf 8f6f isb sy + 80055e2: f3bf 8f4f dsb sy + 80055e6: 61bb str r3, [r7, #24] } - 8004a6c: bf00 nop - 8004a6e: e7fe b.n 8004a6e + 80055e8: bf00 nop + 80055ea: e7fe b.n 80055ea break; case tmrCOMMAND_STOP : case tmrCOMMAND_STOP_FROM_ISR : /* The timer has already been removed from the active list. */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; - 8004a70: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a72: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 - 8004a76: f023 0301 bic.w r3, r3, #1 - 8004a7a: b2da uxtb r2, r3 - 8004a7c: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a7e: f883 2028 strb.w r2, [r3, #40] ; 0x28 + 80055ec: 6abb ldr r3, [r7, #40] ; 0x28 + 80055ee: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 80055f2: f023 0301 bic.w r3, r3, #1 + 80055f6: b2da uxtb r2, r3 + 80055f8: 6abb ldr r3, [r7, #40] ; 0x28 + 80055fa: f883 2028 strb.w r2, [r3, #40] ; 0x28 break; - 8004a82: e03a b.n 8004afa + 80055fe: e03a b.n 8005676 case tmrCOMMAND_CHANGE_PERIOD : case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR : pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE; - 8004a84: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a86: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 - 8004a8a: f043 0301 orr.w r3, r3, #1 - 8004a8e: b2da uxtb r2, r3 - 8004a90: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a92: f883 2028 strb.w r2, [r3, #40] ; 0x28 + 8005600: 6abb ldr r3, [r7, #40] ; 0x28 + 8005602: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 8005606: f043 0301 orr.w r3, r3, #1 + 800560a: b2da uxtb r2, r3 + 800560c: 6abb ldr r3, [r7, #40] ; 0x28 + 800560e: f883 2028 strb.w r2, [r3, #40] ; 0x28 pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue; - 8004a96: 68ba ldr r2, [r7, #8] - 8004a98: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a9a: 619a str r2, [r3, #24] + 8005612: 68ba ldr r2, [r7, #8] + 8005614: 6abb ldr r3, [r7, #40] ; 0x28 + 8005616: 619a str r2, [r3, #24] configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) ); - 8004a9c: 6abb ldr r3, [r7, #40] ; 0x28 - 8004a9e: 699b ldr r3, [r3, #24] - 8004aa0: 2b00 cmp r3, #0 - 8004aa2: d10a bne.n 8004aba + 8005618: 6abb ldr r3, [r7, #40] ; 0x28 + 800561a: 699b ldr r3, [r3, #24] + 800561c: 2b00 cmp r3, #0 + 800561e: d10a bne.n 8005636 __asm volatile - 8004aa4: f04f 0350 mov.w r3, #80 ; 0x50 - 8004aa8: f383 8811 msr BASEPRI, r3 - 8004aac: f3bf 8f6f isb sy - 8004ab0: f3bf 8f4f dsb sy - 8004ab4: 617b str r3, [r7, #20] + 8005620: f04f 0350 mov.w r3, #80 ; 0x50 + 8005624: f383 8811 msr BASEPRI, r3 + 8005628: f3bf 8f6f isb sy + 800562c: f3bf 8f4f dsb sy + 8005630: 617b str r3, [r7, #20] } - 8004ab6: bf00 nop - 8004ab8: e7fe b.n 8004ab8 + 8005632: bf00 nop + 8005634: e7fe b.n 8005634 be longer or shorter than the old one. The command time is therefore set to the current time, and as the period cannot be zero the next expiry time can only be in the future, meaning (unlike for the xTimerStart() case above) there is no fail case that needs to be handled here. */ ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow ); - 8004aba: 6abb ldr r3, [r7, #40] ; 0x28 - 8004abc: 699a ldr r2, [r3, #24] - 8004abe: 6a7b ldr r3, [r7, #36] ; 0x24 - 8004ac0: 18d1 adds r1, r2, r3 - 8004ac2: 6a7b ldr r3, [r7, #36] ; 0x24 - 8004ac4: 6a7a ldr r2, [r7, #36] ; 0x24 - 8004ac6: 6ab8 ldr r0, [r7, #40] ; 0x28 - 8004ac8: f7ff ff06 bl 80048d8 + 8005636: 6abb ldr r3, [r7, #40] ; 0x28 + 8005638: 699a ldr r2, [r3, #24] + 800563a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800563c: 18d1 adds r1, r2, r3 + 800563e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005640: 6a7a ldr r2, [r7, #36] ; 0x24 + 8005642: 6ab8 ldr r0, [r7, #40] ; 0x28 + 8005644: f7ff ff06 bl 8005454 break; - 8004acc: e015 b.n 8004afa + 8005648: e015 b.n 8005676 #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) { /* The timer has already been removed from the active list, just free up the memory if the memory was dynamically allocated. */ if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 ) - 8004ace: 6abb ldr r3, [r7, #40] ; 0x28 - 8004ad0: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 - 8004ad4: f003 0302 and.w r3, r3, #2 - 8004ad8: 2b00 cmp r3, #0 - 8004ada: d103 bne.n 8004ae4 + 800564a: 6abb ldr r3, [r7, #40] ; 0x28 + 800564c: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 8005650: f003 0302 and.w r3, r3, #2 + 8005654: 2b00 cmp r3, #0 + 8005656: d103 bne.n 8005660 { vPortFree( pxTimer ); - 8004adc: 6ab8 ldr r0, [r7, #40] ; 0x28 - 8004ade: f000 fbdf bl 80052a0 - 8004ae2: e00a b.n 8004afa + 8005658: 6ab8 ldr r0, [r7, #40] ; 0x28 + 800565a: f000 fbe1 bl 8005e20 + 800565e: e00a b.n 8005676 } else { pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; - 8004ae4: 6abb ldr r3, [r7, #40] ; 0x28 - 8004ae6: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 - 8004aea: f023 0301 bic.w r3, r3, #1 - 8004aee: b2da uxtb r2, r3 - 8004af0: 6abb ldr r3, [r7, #40] ; 0x28 - 8004af2: f883 2028 strb.w r2, [r3, #40] ; 0x28 + 8005660: 6abb ldr r3, [r7, #40] ; 0x28 + 8005662: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 8005666: f023 0301 bic.w r3, r3, #1 + 800566a: b2da uxtb r2, r3 + 800566c: 6abb ldr r3, [r7, #40] ; 0x28 + 800566e: f883 2028 strb.w r2, [r3, #40] ; 0x28 no need to free the memory - just mark the timer as "not active". */ pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE; } #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ break; - 8004af6: e000 b.n 8004afa + 8005672: e000 b.n 8005676 default : /* Don't expect to get here. */ break; - 8004af8: bf00 nop + 8005674: bf00 nop while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */ - 8004afa: 4b08 ldr r3, [pc, #32] ; (8004b1c ) - 8004afc: 681b ldr r3, [r3, #0] - 8004afe: 1d39 adds r1, r7, #4 - 8004b00: 2200 movs r2, #0 - 8004b02: 4618 mov r0, r3 - 8004b04: f7fe fbec bl 80032e0 - 8004b08: 4603 mov r3, r0 - 8004b0a: 2b00 cmp r3, #0 - 8004b0c: f47f af2a bne.w 8004964 + 8005676: 4b08 ldr r3, [pc, #32] ; (8005698 ) + 8005678: 681b ldr r3, [r3, #0] + 800567a: 1d39 adds r1, r7, #4 + 800567c: 2200 movs r2, #0 + 800567e: 4618 mov r0, r3 + 8005680: f7fe fbec bl 8003e5c + 8005684: 4603 mov r3, r0 + 8005686: 2b00 cmp r3, #0 + 8005688: f47f af2a bne.w 80054e0 } } } } - 8004b10: bf00 nop - 8004b12: bf00 nop - 8004b14: 3730 adds r7, #48 ; 0x30 - 8004b16: 46bd mov sp, r7 - 8004b18: bd80 pop {r7, pc} - 8004b1a: bf00 nop - 8004b1c: 20000df0 .word 0x20000df0 + 800568c: bf00 nop + 800568e: bf00 nop + 8005690: 3730 adds r7, #48 ; 0x30 + 8005692: 46bd mov sp, r7 + 8005694: bd80 pop {r7, pc} + 8005696: bf00 nop + 8005698: 20000e40 .word 0x20000e40 -08004b20 : +0800569c : /*-----------------------------------------------------------*/ static void prvSwitchTimerLists( void ) { - 8004b20: b580 push {r7, lr} - 8004b22: b088 sub sp, #32 - 8004b24: af02 add r7, sp, #8 + 800569c: b580 push {r7, lr} + 800569e: b088 sub sp, #32 + 80056a0: af02 add r7, sp, #8 /* The tick count has overflowed. The timer lists must be switched. If there are any timers still referenced from the current timer list then they must have expired and should be processed before the lists are switched. */ while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) - 8004b26: e048 b.n 8004bba + 80056a2: e048 b.n 8005736 { xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList ); - 8004b28: 4b2d ldr r3, [pc, #180] ; (8004be0 ) - 8004b2a: 681b ldr r3, [r3, #0] - 8004b2c: 68db ldr r3, [r3, #12] - 8004b2e: 681b ldr r3, [r3, #0] - 8004b30: 613b str r3, [r7, #16] + 80056a4: 4b2d ldr r3, [pc, #180] ; (800575c ) + 80056a6: 681b ldr r3, [r3, #0] + 80056a8: 68db ldr r3, [r3, #12] + 80056aa: 681b ldr r3, [r3, #0] + 80056ac: 613b str r3, [r7, #16] /* Remove the timer from the list. */ pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too. Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */ - 8004b32: 4b2b ldr r3, [pc, #172] ; (8004be0 ) - 8004b34: 681b ldr r3, [r3, #0] - 8004b36: 68db ldr r3, [r3, #12] - 8004b38: 68db ldr r3, [r3, #12] - 8004b3a: 60fb str r3, [r7, #12] + 80056ae: 4b2b ldr r3, [pc, #172] ; (800575c ) + 80056b0: 681b ldr r3, [r3, #0] + 80056b2: 68db ldr r3, [r3, #12] + 80056b4: 68db ldr r3, [r3, #12] + 80056b6: 60fb str r3, [r7, #12] ( void ) uxListRemove( &( pxTimer->xTimerListItem ) ); - 8004b3c: 68fb ldr r3, [r7, #12] - 8004b3e: 3304 adds r3, #4 - 8004b40: 4618 mov r0, r3 - 8004b42: f7fe f905 bl 8002d50 + 80056b8: 68fb ldr r3, [r7, #12] + 80056ba: 3304 adds r3, #4 + 80056bc: 4618 mov r0, r3 + 80056be: f7fe f905 bl 80038cc traceTIMER_EXPIRED( pxTimer ); /* Execute its callback, then send a command to restart the timer if it is an auto-reload timer. It cannot be restarted here as the lists have not yet been switched. */ pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer ); - 8004b46: 68fb ldr r3, [r7, #12] - 8004b48: 6a1b ldr r3, [r3, #32] - 8004b4a: 68f8 ldr r0, [r7, #12] - 8004b4c: 4798 blx r3 + 80056c2: 68fb ldr r3, [r7, #12] + 80056c4: 6a1b ldr r3, [r3, #32] + 80056c6: 68f8 ldr r0, [r7, #12] + 80056c8: 4798 blx r3 if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 ) - 8004b4e: 68fb ldr r3, [r7, #12] - 8004b50: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 - 8004b54: f003 0304 and.w r3, r3, #4 - 8004b58: 2b00 cmp r3, #0 - 8004b5a: d02e beq.n 8004bba + 80056ca: 68fb ldr r3, [r7, #12] + 80056cc: f893 3028 ldrb.w r3, [r3, #40] ; 0x28 + 80056d0: f003 0304 and.w r3, r3, #4 + 80056d4: 2b00 cmp r3, #0 + 80056d6: d02e beq.n 8005736 the timer going into the same timer list then it has already expired and the timer should be re-inserted into the current list so it is processed again within this loop. Otherwise a command should be sent to restart the timer to ensure it is only inserted into a list after the lists have been swapped. */ xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ); - 8004b5c: 68fb ldr r3, [r7, #12] - 8004b5e: 699b ldr r3, [r3, #24] - 8004b60: 693a ldr r2, [r7, #16] - 8004b62: 4413 add r3, r2 - 8004b64: 60bb str r3, [r7, #8] + 80056d8: 68fb ldr r3, [r7, #12] + 80056da: 699b ldr r3, [r3, #24] + 80056dc: 693a ldr r2, [r7, #16] + 80056de: 4413 add r3, r2 + 80056e0: 60bb str r3, [r7, #8] if( xReloadTime > xNextExpireTime ) - 8004b66: 68ba ldr r2, [r7, #8] - 8004b68: 693b ldr r3, [r7, #16] - 8004b6a: 429a cmp r2, r3 - 8004b6c: d90e bls.n 8004b8c + 80056e2: 68ba ldr r2, [r7, #8] + 80056e4: 693b ldr r3, [r7, #16] + 80056e6: 429a cmp r2, r3 + 80056e8: d90e bls.n 8005708 { listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime ); - 8004b6e: 68fb ldr r3, [r7, #12] - 8004b70: 68ba ldr r2, [r7, #8] - 8004b72: 605a str r2, [r3, #4] + 80056ea: 68fb ldr r3, [r7, #12] + 80056ec: 68ba ldr r2, [r7, #8] + 80056ee: 605a str r2, [r3, #4] listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer ); - 8004b74: 68fb ldr r3, [r7, #12] - 8004b76: 68fa ldr r2, [r7, #12] - 8004b78: 611a str r2, [r3, #16] + 80056f0: 68fb ldr r3, [r7, #12] + 80056f2: 68fa ldr r2, [r7, #12] + 80056f4: 611a str r2, [r3, #16] vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) ); - 8004b7a: 4b19 ldr r3, [pc, #100] ; (8004be0 ) - 8004b7c: 681a ldr r2, [r3, #0] - 8004b7e: 68fb ldr r3, [r7, #12] - 8004b80: 3304 adds r3, #4 - 8004b82: 4619 mov r1, r3 - 8004b84: 4610 mov r0, r2 - 8004b86: f7fe f8aa bl 8002cde - 8004b8a: e016 b.n 8004bba + 80056f6: 4b19 ldr r3, [pc, #100] ; (800575c ) + 80056f8: 681a ldr r2, [r3, #0] + 80056fa: 68fb ldr r3, [r7, #12] + 80056fc: 3304 adds r3, #4 + 80056fe: 4619 mov r1, r3 + 8005700: 4610 mov r0, r2 + 8005702: f7fe f8aa bl 800385a + 8005706: e016 b.n 8005736 } else { xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY ); - 8004b8c: 2300 movs r3, #0 - 8004b8e: 9300 str r3, [sp, #0] - 8004b90: 2300 movs r3, #0 - 8004b92: 693a ldr r2, [r7, #16] - 8004b94: 2100 movs r1, #0 - 8004b96: 68f8 ldr r0, [r7, #12] - 8004b98: f7ff fd60 bl 800465c - 8004b9c: 6078 str r0, [r7, #4] + 8005708: 2300 movs r3, #0 + 800570a: 9300 str r3, [sp, #0] + 800570c: 2300 movs r3, #0 + 800570e: 693a ldr r2, [r7, #16] + 8005710: 2100 movs r1, #0 + 8005712: 68f8 ldr r0, [r7, #12] + 8005714: f7ff fd60 bl 80051d8 + 8005718: 6078 str r0, [r7, #4] configASSERT( xResult ); - 8004b9e: 687b ldr r3, [r7, #4] - 8004ba0: 2b00 cmp r3, #0 - 8004ba2: d10a bne.n 8004bba + 800571a: 687b ldr r3, [r7, #4] + 800571c: 2b00 cmp r3, #0 + 800571e: d10a bne.n 8005736 __asm volatile - 8004ba4: f04f 0350 mov.w r3, #80 ; 0x50 - 8004ba8: f383 8811 msr BASEPRI, r3 - 8004bac: f3bf 8f6f isb sy - 8004bb0: f3bf 8f4f dsb sy - 8004bb4: 603b str r3, [r7, #0] + 8005720: f04f 0350 mov.w r3, #80 ; 0x50 + 8005724: f383 8811 msr BASEPRI, r3 + 8005728: f3bf 8f6f isb sy + 800572c: f3bf 8f4f dsb sy + 8005730: 603b str r3, [r7, #0] } - 8004bb6: bf00 nop - 8004bb8: e7fe b.n 8004bb8 + 8005732: bf00 nop + 8005734: e7fe b.n 8005734 while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE ) - 8004bba: 4b09 ldr r3, [pc, #36] ; (8004be0 ) - 8004bbc: 681b ldr r3, [r3, #0] - 8004bbe: 681b ldr r3, [r3, #0] - 8004bc0: 2b00 cmp r3, #0 - 8004bc2: d1b1 bne.n 8004b28 + 8005736: 4b09 ldr r3, [pc, #36] ; (800575c ) + 8005738: 681b ldr r3, [r3, #0] + 800573a: 681b ldr r3, [r3, #0] + 800573c: 2b00 cmp r3, #0 + 800573e: d1b1 bne.n 80056a4 { mtCOVERAGE_TEST_MARKER(); } } pxTemp = pxCurrentTimerList; - 8004bc4: 4b06 ldr r3, [pc, #24] ; (8004be0 ) - 8004bc6: 681b ldr r3, [r3, #0] - 8004bc8: 617b str r3, [r7, #20] + 8005740: 4b06 ldr r3, [pc, #24] ; (800575c ) + 8005742: 681b ldr r3, [r3, #0] + 8005744: 617b str r3, [r7, #20] pxCurrentTimerList = pxOverflowTimerList; - 8004bca: 4b06 ldr r3, [pc, #24] ; (8004be4 ) - 8004bcc: 681b ldr r3, [r3, #0] - 8004bce: 4a04 ldr r2, [pc, #16] ; (8004be0 ) - 8004bd0: 6013 str r3, [r2, #0] + 8005746: 4b06 ldr r3, [pc, #24] ; (8005760 ) + 8005748: 681b ldr r3, [r3, #0] + 800574a: 4a04 ldr r2, [pc, #16] ; (800575c ) + 800574c: 6013 str r3, [r2, #0] pxOverflowTimerList = pxTemp; - 8004bd2: 4a04 ldr r2, [pc, #16] ; (8004be4 ) - 8004bd4: 697b ldr r3, [r7, #20] - 8004bd6: 6013 str r3, [r2, #0] + 800574e: 4a04 ldr r2, [pc, #16] ; (8005760 ) + 8005750: 697b ldr r3, [r7, #20] + 8005752: 6013 str r3, [r2, #0] } - 8004bd8: bf00 nop - 8004bda: 3718 adds r7, #24 - 8004bdc: 46bd mov sp, r7 - 8004bde: bd80 pop {r7, pc} - 8004be0: 20000de8 .word 0x20000de8 - 8004be4: 20000dec .word 0x20000dec + 8005754: bf00 nop + 8005756: 3718 adds r7, #24 + 8005758: 46bd mov sp, r7 + 800575a: bd80 pop {r7, pc} + 800575c: 20000e38 .word 0x20000e38 + 8005760: 20000e3c .word 0x20000e3c -08004be8 : +08005764 : /*-----------------------------------------------------------*/ static void prvCheckForValidListAndQueue( void ) { - 8004be8: b580 push {r7, lr} - 8004bea: b082 sub sp, #8 - 8004bec: af02 add r7, sp, #8 + 8005764: b580 push {r7, lr} + 8005766: b082 sub sp, #8 + 8005768: af02 add r7, sp, #8 /* Check that the list from which active timers are referenced, and the queue used to communicate with the timer service, have been initialised. */ taskENTER_CRITICAL(); - 8004bee: f000 f969 bl 8004ec4 + 800576a: f000 f96b bl 8005a44 { if( xTimerQueue == NULL ) - 8004bf2: 4b15 ldr r3, [pc, #84] ; (8004c48 ) - 8004bf4: 681b ldr r3, [r3, #0] - 8004bf6: 2b00 cmp r3, #0 - 8004bf8: d120 bne.n 8004c3c + 800576e: 4b15 ldr r3, [pc, #84] ; (80057c4 ) + 8005770: 681b ldr r3, [r3, #0] + 8005772: 2b00 cmp r3, #0 + 8005774: d120 bne.n 80057b8 { vListInitialise( &xActiveTimerList1 ); - 8004bfa: 4814 ldr r0, [pc, #80] ; (8004c4c ) - 8004bfc: f7fe f81e bl 8002c3c + 8005776: 4814 ldr r0, [pc, #80] ; (80057c8 ) + 8005778: f7fe f81e bl 80037b8 vListInitialise( &xActiveTimerList2 ); - 8004c00: 4813 ldr r0, [pc, #76] ; (8004c50 ) - 8004c02: f7fe f81b bl 8002c3c + 800577c: 4813 ldr r0, [pc, #76] ; (80057cc ) + 800577e: f7fe f81b bl 80037b8 pxCurrentTimerList = &xActiveTimerList1; - 8004c06: 4b13 ldr r3, [pc, #76] ; (8004c54 ) - 8004c08: 4a10 ldr r2, [pc, #64] ; (8004c4c ) - 8004c0a: 601a str r2, [r3, #0] + 8005782: 4b13 ldr r3, [pc, #76] ; (80057d0 ) + 8005784: 4a10 ldr r2, [pc, #64] ; (80057c8 ) + 8005786: 601a str r2, [r3, #0] pxOverflowTimerList = &xActiveTimerList2; - 8004c0c: 4b12 ldr r3, [pc, #72] ; (8004c58 ) - 8004c0e: 4a10 ldr r2, [pc, #64] ; (8004c50 ) - 8004c10: 601a str r2, [r3, #0] + 8005788: 4b12 ldr r3, [pc, #72] ; (80057d4 ) + 800578a: 4a10 ldr r2, [pc, #64] ; (80057cc ) + 800578c: 601a str r2, [r3, #0] /* The timer queue is allocated statically in case configSUPPORT_DYNAMIC_ALLOCATION is 0. */ static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */ xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue ); - 8004c12: 2300 movs r3, #0 - 8004c14: 9300 str r3, [sp, #0] - 8004c16: 4b11 ldr r3, [pc, #68] ; (8004c5c ) - 8004c18: 4a11 ldr r2, [pc, #68] ; (8004c60 ) - 8004c1a: 2110 movs r1, #16 - 8004c1c: 200a movs r0, #10 - 8004c1e: f7fe f929 bl 8002e74 - 8004c22: 4603 mov r3, r0 - 8004c24: 4a08 ldr r2, [pc, #32] ; (8004c48 ) - 8004c26: 6013 str r3, [r2, #0] + 800578e: 2300 movs r3, #0 + 8005790: 9300 str r3, [sp, #0] + 8005792: 4b11 ldr r3, [pc, #68] ; (80057d8 ) + 8005794: 4a11 ldr r2, [pc, #68] ; (80057dc ) + 8005796: 2110 movs r1, #16 + 8005798: 200a movs r0, #10 + 800579a: f7fe f929 bl 80039f0 + 800579e: 4603 mov r3, r0 + 80057a0: 4a08 ldr r2, [pc, #32] ; (80057c4 ) + 80057a2: 6013 str r3, [r2, #0] } #endif #if ( configQUEUE_REGISTRY_SIZE > 0 ) { if( xTimerQueue != NULL ) - 8004c28: 4b07 ldr r3, [pc, #28] ; (8004c48 ) - 8004c2a: 681b ldr r3, [r3, #0] - 8004c2c: 2b00 cmp r3, #0 - 8004c2e: d005 beq.n 8004c3c + 80057a4: 4b07 ldr r3, [pc, #28] ; (80057c4 ) + 80057a6: 681b ldr r3, [r3, #0] + 80057a8: 2b00 cmp r3, #0 + 80057aa: d005 beq.n 80057b8 { vQueueAddToRegistry( xTimerQueue, "TmrQ" ); - 8004c30: 4b05 ldr r3, [pc, #20] ; (8004c48 ) - 8004c32: 681b ldr r3, [r3, #0] - 8004c34: 490b ldr r1, [pc, #44] ; (8004c64 ) - 8004c36: 4618 mov r0, r3 - 8004c38: f7fe fd42 bl 80036c0 + 80057ac: 4b05 ldr r3, [pc, #20] ; (80057c4 ) + 80057ae: 681b ldr r3, [r3, #0] + 80057b0: 490b ldr r1, [pc, #44] ; (80057e0 ) + 80057b2: 4618 mov r0, r3 + 80057b4: f7fe fd42 bl 800423c else { mtCOVERAGE_TEST_MARKER(); } } taskEXIT_CRITICAL(); - 8004c3c: f000 f972 bl 8004f24 + 80057b8: f000 f974 bl 8005aa4 } - 8004c40: bf00 nop - 8004c42: 46bd mov sp, r7 - 8004c44: bd80 pop {r7, pc} - 8004c46: bf00 nop - 8004c48: 20000df0 .word 0x20000df0 - 8004c4c: 20000dc0 .word 0x20000dc0 - 8004c50: 20000dd4 .word 0x20000dd4 - 8004c54: 20000de8 .word 0x20000de8 - 8004c58: 20000dec .word 0x20000dec - 8004c5c: 20000e9c .word 0x20000e9c - 8004c60: 20000dfc .word 0x20000dfc - 8004c64: 080056f0 .word 0x080056f0 + 80057bc: bf00 nop + 80057be: 46bd mov sp, r7 + 80057c0: bd80 pop {r7, pc} + 80057c2: bf00 nop + 80057c4: 20000e40 .word 0x20000e40 + 80057c8: 20000e10 .word 0x20000e10 + 80057cc: 20000e24 .word 0x20000e24 + 80057d0: 20000e38 .word 0x20000e38 + 80057d4: 20000e3c .word 0x20000e3c + 80057d8: 20000eec .word 0x20000eec + 80057dc: 20000e4c .word 0x20000e4c + 80057e0: 0800628c .word 0x0800628c -08004c68 : +080057e4 : /* * See header file for description. */ StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) { - 8004c68: b480 push {r7} - 8004c6a: b085 sub sp, #20 - 8004c6c: af00 add r7, sp, #0 - 8004c6e: 60f8 str r0, [r7, #12] - 8004c70: 60b9 str r1, [r7, #8] - 8004c72: 607a str r2, [r7, #4] + 80057e4: b480 push {r7} + 80057e6: b085 sub sp, #20 + 80057e8: af00 add r7, sp, #0 + 80057ea: 60f8 str r0, [r7, #12] + 80057ec: 60b9 str r1, [r7, #8] + 80057ee: 607a str r2, [r7, #4] /* Simulate the stack frame as it would be created by a context switch interrupt. */ /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts, and to ensure alignment. */ pxTopOfStack--; - 8004c74: 68fb ldr r3, [r7, #12] - 8004c76: 3b04 subs r3, #4 - 8004c78: 60fb str r3, [r7, #12] + 80057f0: 68fb ldr r3, [r7, #12] + 80057f2: 3b04 subs r3, #4 + 80057f4: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_XPSR; /* xPSR */ - 8004c7a: 68fb ldr r3, [r7, #12] - 8004c7c: f04f 7280 mov.w r2, #16777216 ; 0x1000000 - 8004c80: 601a str r2, [r3, #0] + 80057f6: 68fb ldr r3, [r7, #12] + 80057f8: f04f 7280 mov.w r2, #16777216 ; 0x1000000 + 80057fc: 601a str r2, [r3, #0] pxTopOfStack--; - 8004c82: 68fb ldr r3, [r7, #12] - 8004c84: 3b04 subs r3, #4 - 8004c86: 60fb str r3, [r7, #12] + 80057fe: 68fb ldr r3, [r7, #12] + 8005800: 3b04 subs r3, #4 + 8005802: 60fb str r3, [r7, #12] *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */ - 8004c88: 68bb ldr r3, [r7, #8] - 8004c8a: f023 0201 bic.w r2, r3, #1 - 8004c8e: 68fb ldr r3, [r7, #12] - 8004c90: 601a str r2, [r3, #0] + 8005804: 68bb ldr r3, [r7, #8] + 8005806: f023 0201 bic.w r2, r3, #1 + 800580a: 68fb ldr r3, [r7, #12] + 800580c: 601a str r2, [r3, #0] pxTopOfStack--; - 8004c92: 68fb ldr r3, [r7, #12] - 8004c94: 3b04 subs r3, #4 - 8004c96: 60fb str r3, [r7, #12] + 800580e: 68fb ldr r3, [r7, #12] + 8005810: 3b04 subs r3, #4 + 8005812: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */ - 8004c98: 4a0c ldr r2, [pc, #48] ; (8004ccc ) - 8004c9a: 68fb ldr r3, [r7, #12] - 8004c9c: 601a str r2, [r3, #0] + 8005814: 4a0c ldr r2, [pc, #48] ; (8005848 ) + 8005816: 68fb ldr r3, [r7, #12] + 8005818: 601a str r2, [r3, #0] /* Save code space by skipping register initialisation. */ pxTopOfStack -= 5; /* R12, R3, R2 and R1. */ - 8004c9e: 68fb ldr r3, [r7, #12] - 8004ca0: 3b14 subs r3, #20 - 8004ca2: 60fb str r3, [r7, #12] + 800581a: 68fb ldr r3, [r7, #12] + 800581c: 3b14 subs r3, #20 + 800581e: 60fb str r3, [r7, #12] *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */ - 8004ca4: 687a ldr r2, [r7, #4] - 8004ca6: 68fb ldr r3, [r7, #12] - 8004ca8: 601a str r2, [r3, #0] + 8005820: 687a ldr r2, [r7, #4] + 8005822: 68fb ldr r3, [r7, #12] + 8005824: 601a str r2, [r3, #0] /* A save method is being used that requires each task to maintain its own exec return value. */ pxTopOfStack--; - 8004caa: 68fb ldr r3, [r7, #12] - 8004cac: 3b04 subs r3, #4 - 8004cae: 60fb str r3, [r7, #12] + 8005826: 68fb ldr r3, [r7, #12] + 8005828: 3b04 subs r3, #4 + 800582a: 60fb str r3, [r7, #12] *pxTopOfStack = portINITIAL_EXC_RETURN; - 8004cb0: 68fb ldr r3, [r7, #12] - 8004cb2: f06f 0202 mvn.w r2, #2 - 8004cb6: 601a str r2, [r3, #0] + 800582c: 68fb ldr r3, [r7, #12] + 800582e: f06f 0202 mvn.w r2, #2 + 8005832: 601a str r2, [r3, #0] pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */ - 8004cb8: 68fb ldr r3, [r7, #12] - 8004cba: 3b20 subs r3, #32 - 8004cbc: 60fb str r3, [r7, #12] + 8005834: 68fb ldr r3, [r7, #12] + 8005836: 3b20 subs r3, #32 + 8005838: 60fb str r3, [r7, #12] return pxTopOfStack; - 8004cbe: 68fb ldr r3, [r7, #12] + 800583a: 68fb ldr r3, [r7, #12] } - 8004cc0: 4618 mov r0, r3 - 8004cc2: 3714 adds r7, #20 - 8004cc4: 46bd mov sp, r7 - 8004cc6: f85d 7b04 ldr.w r7, [sp], #4 - 8004cca: 4770 bx lr - 8004ccc: 08004cd1 .word 0x08004cd1 + 800583c: 4618 mov r0, r3 + 800583e: 3714 adds r7, #20 + 8005840: 46bd mov sp, r7 + 8005842: f85d 7b04 ldr.w r7, [sp], #4 + 8005846: 4770 bx lr + 8005848: 0800584d .word 0x0800584d -08004cd0 : +0800584c : /*-----------------------------------------------------------*/ static void prvTaskExitError( void ) { - 8004cd0: b480 push {r7} - 8004cd2: b085 sub sp, #20 - 8004cd4: af00 add r7, sp, #0 + 800584c: b480 push {r7} + 800584e: b085 sub sp, #20 + 8005850: af00 add r7, sp, #0 volatile uint32_t ulDummy = 0; - 8004cd6: 2300 movs r3, #0 - 8004cd8: 607b str r3, [r7, #4] + 8005852: 2300 movs r3, #0 + 8005854: 607b str r3, [r7, #4] its caller as there is nothing to return to. If a task wants to exit it should instead call vTaskDelete( NULL ). Artificially force an assert() to be triggered if configASSERT() is defined, then stop here so application writers can catch the error. */ configASSERT( uxCriticalNesting == ~0UL ); - 8004cda: 4b12 ldr r3, [pc, #72] ; (8004d24 ) - 8004cdc: 681b ldr r3, [r3, #0] - 8004cde: f1b3 3fff cmp.w r3, #4294967295 - 8004ce2: d00a beq.n 8004cfa + 8005856: 4b12 ldr r3, [pc, #72] ; (80058a0 ) + 8005858: 681b ldr r3, [r3, #0] + 800585a: f1b3 3fff cmp.w r3, #4294967295 + 800585e: d00a beq.n 8005876 __asm volatile - 8004ce4: f04f 0350 mov.w r3, #80 ; 0x50 - 8004ce8: f383 8811 msr BASEPRI, r3 - 8004cec: f3bf 8f6f isb sy - 8004cf0: f3bf 8f4f dsb sy - 8004cf4: 60fb str r3, [r7, #12] + 8005860: f04f 0350 mov.w r3, #80 ; 0x50 + 8005864: f383 8811 msr BASEPRI, r3 + 8005868: f3bf 8f6f isb sy + 800586c: f3bf 8f4f dsb sy + 8005870: 60fb str r3, [r7, #12] } - 8004cf6: bf00 nop - 8004cf8: e7fe b.n 8004cf8 + 8005872: bf00 nop + 8005874: e7fe b.n 8005874 __asm volatile - 8004cfa: f04f 0350 mov.w r3, #80 ; 0x50 - 8004cfe: f383 8811 msr BASEPRI, r3 - 8004d02: f3bf 8f6f isb sy - 8004d06: f3bf 8f4f dsb sy - 8004d0a: 60bb str r3, [r7, #8] + 8005876: f04f 0350 mov.w r3, #80 ; 0x50 + 800587a: f383 8811 msr BASEPRI, r3 + 800587e: f3bf 8f6f isb sy + 8005882: f3bf 8f4f dsb sy + 8005886: 60bb str r3, [r7, #8] } - 8004d0c: bf00 nop + 8005888: bf00 nop portDISABLE_INTERRUPTS(); while( ulDummy == 0 ) - 8004d0e: bf00 nop - 8004d10: 687b ldr r3, [r7, #4] - 8004d12: 2b00 cmp r3, #0 - 8004d14: d0fc beq.n 8004d10 + 800588a: bf00 nop + 800588c: 687b ldr r3, [r7, #4] + 800588e: 2b00 cmp r3, #0 + 8005890: d0fc beq.n 800588c about code appearing after this function is called - making ulDummy volatile makes the compiler think the function could return and therefore not output an 'unreachable code' warning for code that appears after it. */ } } - 8004d16: bf00 nop - 8004d18: bf00 nop - 8004d1a: 3714 adds r7, #20 - 8004d1c: 46bd mov sp, r7 - 8004d1e: f85d 7b04 ldr.w r7, [sp], #4 - 8004d22: 4770 bx lr - 8004d24: 2000000c .word 0x2000000c + 8005892: bf00 nop + 8005894: bf00 nop + 8005896: 3714 adds r7, #20 + 8005898: 46bd mov sp, r7 + 800589a: f85d 7b04 ldr.w r7, [sp], #4 + 800589e: 4770 bx lr + 80058a0: 2000000c .word 0x2000000c ... -08004d30 : +080058b0 : /*-----------------------------------------------------------*/ void vPortSVCHandler( void ) { __asm volatile ( - 8004d30: 4b07 ldr r3, [pc, #28] ; (8004d50 ) - 8004d32: 6819 ldr r1, [r3, #0] - 8004d34: 6808 ldr r0, [r1, #0] - 8004d36: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8004d3a: f380 8809 msr PSP, r0 - 8004d3e: f3bf 8f6f isb sy - 8004d42: f04f 0000 mov.w r0, #0 - 8004d46: f380 8811 msr BASEPRI, r0 - 8004d4a: 4770 bx lr - 8004d4c: f3af 8000 nop.w + 80058b0: 4b07 ldr r3, [pc, #28] ; (80058d0 ) + 80058b2: 6819 ldr r1, [r3, #0] + 80058b4: 6808 ldr r0, [r1, #0] + 80058b6: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 80058ba: f380 8809 msr PSP, r0 + 80058be: f3bf 8f6f isb sy + 80058c2: f04f 0000 mov.w r0, #0 + 80058c6: f380 8811 msr BASEPRI, r0 + 80058ca: 4770 bx lr + 80058cc: f3af 8000 nop.w -08004d50 : - 8004d50: 200008c0 .word 0x200008c0 +080058d0 : + 80058d0: 20000910 .word 0x20000910 " bx r14 \n" " \n" " .align 4 \n" "pxCurrentTCBConst2: .word pxCurrentTCB \n" ); } - 8004d54: bf00 nop - 8004d56: bf00 nop + 80058d4: bf00 nop + 80058d6: bf00 nop -08004d58 : +080058d8 : { /* Start the first task. This also clears the bit that indicates the FPU is in use in case the FPU was used before the scheduler was started - which would otherwise result in the unnecessary leaving of space in the SVC stack for lazy saving of FPU registers. */ __asm volatile( - 8004d58: 4808 ldr r0, [pc, #32] ; (8004d7c ) - 8004d5a: 6800 ldr r0, [r0, #0] - 8004d5c: 6800 ldr r0, [r0, #0] - 8004d5e: f380 8808 msr MSP, r0 - 8004d62: f04f 0000 mov.w r0, #0 - 8004d66: f380 8814 msr CONTROL, r0 - 8004d6a: b662 cpsie i - 8004d6c: b661 cpsie f - 8004d6e: f3bf 8f4f dsb sy - 8004d72: f3bf 8f6f isb sy - 8004d76: df00 svc 0 - 8004d78: bf00 nop + 80058d8: 4808 ldr r0, [pc, #32] ; (80058fc ) + 80058da: 6800 ldr r0, [r0, #0] + 80058dc: 6800 ldr r0, [r0, #0] + 80058de: f380 8808 msr MSP, r0 + 80058e2: f04f 0000 mov.w r0, #0 + 80058e6: f380 8814 msr CONTROL, r0 + 80058ea: b662 cpsie i + 80058ec: b661 cpsie f + 80058ee: f3bf 8f4f dsb sy + 80058f2: f3bf 8f6f isb sy + 80058f6: df00 svc 0 + 80058f8: bf00 nop " dsb \n" " isb \n" " svc 0 \n" /* System call to start first task. */ " nop \n" ); } - 8004d7a: bf00 nop - 8004d7c: e000ed08 .word 0xe000ed08 + 80058fa: bf00 nop + 80058fc: e000ed08 .word 0xe000ed08 -08004d80 : +08005900 : /* * See header file for description. */ BaseType_t xPortStartScheduler( void ) { - 8004d80: b580 push {r7, lr} - 8004d82: b086 sub sp, #24 - 8004d84: af00 add r7, sp, #0 + 8005900: b580 push {r7, lr} + 8005902: b086 sub sp, #24 + 8005904: af00 add r7, sp, #0 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY ); /* This port can be used on all revisions of the Cortex-M7 core other than the r0p1 parts. r0p1 parts should use the port from the /source/portable/GCC/ARM_CM7/r0p1 directory. */ configASSERT( portCPUID != portCORTEX_M7_r0p1_ID ); - 8004d86: 4b46 ldr r3, [pc, #280] ; (8004ea0 ) - 8004d88: 681b ldr r3, [r3, #0] - 8004d8a: 4a46 ldr r2, [pc, #280] ; (8004ea4 ) - 8004d8c: 4293 cmp r3, r2 - 8004d8e: d10a bne.n 8004da6 + 8005906: 4b46 ldr r3, [pc, #280] ; (8005a20 ) + 8005908: 681b ldr r3, [r3, #0] + 800590a: 4a46 ldr r2, [pc, #280] ; (8005a24 ) + 800590c: 4293 cmp r3, r2 + 800590e: d10a bne.n 8005926 __asm volatile - 8004d90: f04f 0350 mov.w r3, #80 ; 0x50 - 8004d94: f383 8811 msr BASEPRI, r3 - 8004d98: f3bf 8f6f isb sy - 8004d9c: f3bf 8f4f dsb sy - 8004da0: 613b str r3, [r7, #16] + 8005910: f04f 0350 mov.w r3, #80 ; 0x50 + 8005914: f383 8811 msr BASEPRI, r3 + 8005918: f3bf 8f6f isb sy + 800591c: f3bf 8f4f dsb sy + 8005920: 613b str r3, [r7, #16] } - 8004da2: bf00 nop - 8004da4: e7fe b.n 8004da4 + 8005922: bf00 nop + 8005924: e7fe b.n 8005924 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID ); - 8004da6: 4b3e ldr r3, [pc, #248] ; (8004ea0 ) - 8004da8: 681b ldr r3, [r3, #0] - 8004daa: 4a3f ldr r2, [pc, #252] ; (8004ea8 ) - 8004dac: 4293 cmp r3, r2 - 8004dae: d10a bne.n 8004dc6 + 8005926: 4b3e ldr r3, [pc, #248] ; (8005a20 ) + 8005928: 681b ldr r3, [r3, #0] + 800592a: 4a3f ldr r2, [pc, #252] ; (8005a28 ) + 800592c: 4293 cmp r3, r2 + 800592e: d10a bne.n 8005946 __asm volatile - 8004db0: f04f 0350 mov.w r3, #80 ; 0x50 - 8004db4: f383 8811 msr BASEPRI, r3 - 8004db8: f3bf 8f6f isb sy - 8004dbc: f3bf 8f4f dsb sy - 8004dc0: 60fb str r3, [r7, #12] + 8005930: f04f 0350 mov.w r3, #80 ; 0x50 + 8005934: f383 8811 msr BASEPRI, r3 + 8005938: f3bf 8f6f isb sy + 800593c: f3bf 8f4f dsb sy + 8005940: 60fb str r3, [r7, #12] } - 8004dc2: bf00 nop - 8004dc4: e7fe b.n 8004dc4 + 8005942: bf00 nop + 8005944: e7fe b.n 8005944 #if( configASSERT_DEFINED == 1 ) { volatile uint32_t ulOriginalPriority; volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER ); - 8004dc6: 4b39 ldr r3, [pc, #228] ; (8004eac ) - 8004dc8: 617b str r3, [r7, #20] + 8005946: 4b39 ldr r3, [pc, #228] ; (8005a2c ) + 8005948: 617b str r3, [r7, #20] functions can be called. ISR safe functions are those that end in "FromISR". FreeRTOS maintains separate thread and ISR API functions to ensure interrupt entry is as fast and simple as possible. Save the interrupt priority value that is about to be clobbered. */ ulOriginalPriority = *pucFirstUserPriorityRegister; - 8004dca: 697b ldr r3, [r7, #20] - 8004dcc: 781b ldrb r3, [r3, #0] - 8004dce: b2db uxtb r3, r3 - 8004dd0: 607b str r3, [r7, #4] + 800594a: 697b ldr r3, [r7, #20] + 800594c: 781b ldrb r3, [r3, #0] + 800594e: b2db uxtb r3, r3 + 8005950: 607b str r3, [r7, #4] /* Determine the number of priority bits available. First write to all possible bits. */ *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE; - 8004dd2: 697b ldr r3, [r7, #20] - 8004dd4: 22ff movs r2, #255 ; 0xff - 8004dd6: 701a strb r2, [r3, #0] + 8005952: 697b ldr r3, [r7, #20] + 8005954: 22ff movs r2, #255 ; 0xff + 8005956: 701a strb r2, [r3, #0] /* Read the value back to see how many bits stuck. */ ucMaxPriorityValue = *pucFirstUserPriorityRegister; - 8004dd8: 697b ldr r3, [r7, #20] - 8004dda: 781b ldrb r3, [r3, #0] - 8004ddc: b2db uxtb r3, r3 - 8004dde: 70fb strb r3, [r7, #3] + 8005958: 697b ldr r3, [r7, #20] + 800595a: 781b ldrb r3, [r3, #0] + 800595c: b2db uxtb r3, r3 + 800595e: 70fb strb r3, [r7, #3] /* Use the same mask on the maximum system call priority. */ ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue; - 8004de0: 78fb ldrb r3, [r7, #3] - 8004de2: b2db uxtb r3, r3 - 8004de4: f003 0350 and.w r3, r3, #80 ; 0x50 - 8004de8: b2da uxtb r2, r3 - 8004dea: 4b31 ldr r3, [pc, #196] ; (8004eb0 ) - 8004dec: 701a strb r2, [r3, #0] + 8005960: 78fb ldrb r3, [r7, #3] + 8005962: b2db uxtb r3, r3 + 8005964: f003 0350 and.w r3, r3, #80 ; 0x50 + 8005968: b2da uxtb r2, r3 + 800596a: 4b31 ldr r3, [pc, #196] ; (8005a30 ) + 800596c: 701a strb r2, [r3, #0] /* Calculate the maximum acceptable priority group value for the number of bits read back. */ ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS; - 8004dee: 4b31 ldr r3, [pc, #196] ; (8004eb4 ) - 8004df0: 2207 movs r2, #7 - 8004df2: 601a str r2, [r3, #0] + 800596e: 4b31 ldr r3, [pc, #196] ; (8005a34 ) + 8005970: 2207 movs r2, #7 + 8005972: 601a str r2, [r3, #0] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - 8004df4: e009 b.n 8004e0a + 8005974: e009 b.n 800598a { ulMaxPRIGROUPValue--; - 8004df6: 4b2f ldr r3, [pc, #188] ; (8004eb4 ) - 8004df8: 681b ldr r3, [r3, #0] - 8004dfa: 3b01 subs r3, #1 - 8004dfc: 4a2d ldr r2, [pc, #180] ; (8004eb4 ) - 8004dfe: 6013 str r3, [r2, #0] + 8005976: 4b2f ldr r3, [pc, #188] ; (8005a34 ) + 8005978: 681b ldr r3, [r3, #0] + 800597a: 3b01 subs r3, #1 + 800597c: 4a2d ldr r2, [pc, #180] ; (8005a34 ) + 800597e: 6013 str r3, [r2, #0] ucMaxPriorityValue <<= ( uint8_t ) 0x01; - 8004e00: 78fb ldrb r3, [r7, #3] - 8004e02: b2db uxtb r3, r3 - 8004e04: 005b lsls r3, r3, #1 - 8004e06: b2db uxtb r3, r3 - 8004e08: 70fb strb r3, [r7, #3] + 8005980: 78fb ldrb r3, [r7, #3] + 8005982: b2db uxtb r3, r3 + 8005984: 005b lsls r3, r3, #1 + 8005986: b2db uxtb r3, r3 + 8005988: 70fb strb r3, [r7, #3] while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE ) - 8004e0a: 78fb ldrb r3, [r7, #3] - 8004e0c: b2db uxtb r3, r3 - 8004e0e: f003 0380 and.w r3, r3, #128 ; 0x80 - 8004e12: 2b80 cmp r3, #128 ; 0x80 - 8004e14: d0ef beq.n 8004df6 + 800598a: 78fb ldrb r3, [r7, #3] + 800598c: b2db uxtb r3, r3 + 800598e: f003 0380 and.w r3, r3, #128 ; 0x80 + 8005992: 2b80 cmp r3, #128 ; 0x80 + 8005994: d0ef beq.n 8005976 #ifdef configPRIO_BITS { /* Check the FreeRTOS configuration that defines the number of priority bits matches the number of priority bits actually queried from the hardware. */ configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS ); - 8004e16: 4b27 ldr r3, [pc, #156] ; (8004eb4 ) - 8004e18: 681b ldr r3, [r3, #0] - 8004e1a: f1c3 0307 rsb r3, r3, #7 - 8004e1e: 2b04 cmp r3, #4 - 8004e20: d00a beq.n 8004e38 + 8005996: 4b27 ldr r3, [pc, #156] ; (8005a34 ) + 8005998: 681b ldr r3, [r3, #0] + 800599a: f1c3 0307 rsb r3, r3, #7 + 800599e: 2b04 cmp r3, #4 + 80059a0: d00a beq.n 80059b8 __asm volatile - 8004e22: f04f 0350 mov.w r3, #80 ; 0x50 - 8004e26: f383 8811 msr BASEPRI, r3 - 8004e2a: f3bf 8f6f isb sy - 8004e2e: f3bf 8f4f dsb sy - 8004e32: 60bb str r3, [r7, #8] + 80059a2: f04f 0350 mov.w r3, #80 ; 0x50 + 80059a6: f383 8811 msr BASEPRI, r3 + 80059aa: f3bf 8f6f isb sy + 80059ae: f3bf 8f4f dsb sy + 80059b2: 60bb str r3, [r7, #8] } - 8004e34: bf00 nop - 8004e36: e7fe b.n 8004e36 + 80059b4: bf00 nop + 80059b6: e7fe b.n 80059b6 } #endif /* Shift the priority group value back to its position within the AIRCR register. */ ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT; - 8004e38: 4b1e ldr r3, [pc, #120] ; (8004eb4 ) - 8004e3a: 681b ldr r3, [r3, #0] - 8004e3c: 021b lsls r3, r3, #8 - 8004e3e: 4a1d ldr r2, [pc, #116] ; (8004eb4 ) - 8004e40: 6013 str r3, [r2, #0] + 80059b8: 4b1e ldr r3, [pc, #120] ; (8005a34 ) + 80059ba: 681b ldr r3, [r3, #0] + 80059bc: 021b lsls r3, r3, #8 + 80059be: 4a1d ldr r2, [pc, #116] ; (8005a34 ) + 80059c0: 6013 str r3, [r2, #0] ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK; - 8004e42: 4b1c ldr r3, [pc, #112] ; (8004eb4 ) - 8004e44: 681b ldr r3, [r3, #0] - 8004e46: f403 63e0 and.w r3, r3, #1792 ; 0x700 - 8004e4a: 4a1a ldr r2, [pc, #104] ; (8004eb4 ) - 8004e4c: 6013 str r3, [r2, #0] + 80059c2: 4b1c ldr r3, [pc, #112] ; (8005a34 ) + 80059c4: 681b ldr r3, [r3, #0] + 80059c6: f403 63e0 and.w r3, r3, #1792 ; 0x700 + 80059ca: 4a1a ldr r2, [pc, #104] ; (8005a34 ) + 80059cc: 6013 str r3, [r2, #0] /* Restore the clobbered interrupt priority register to its original value. */ *pucFirstUserPriorityRegister = ulOriginalPriority; - 8004e4e: 687b ldr r3, [r7, #4] - 8004e50: b2da uxtb r2, r3 - 8004e52: 697b ldr r3, [r7, #20] - 8004e54: 701a strb r2, [r3, #0] + 80059ce: 687b ldr r3, [r7, #4] + 80059d0: b2da uxtb r2, r3 + 80059d2: 697b ldr r3, [r7, #20] + 80059d4: 701a strb r2, [r3, #0] } #endif /* conifgASSERT_DEFINED */ /* Make PendSV and SysTick the lowest priority interrupts. */ portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI; - 8004e56: 4b18 ldr r3, [pc, #96] ; (8004eb8 ) - 8004e58: 681b ldr r3, [r3, #0] - 8004e5a: 4a17 ldr r2, [pc, #92] ; (8004eb8 ) - 8004e5c: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 - 8004e60: 6013 str r3, [r2, #0] + 80059d6: 4b18 ldr r3, [pc, #96] ; (8005a38 ) + 80059d8: 681b ldr r3, [r3, #0] + 80059da: 4a17 ldr r2, [pc, #92] ; (8005a38 ) + 80059dc: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 + 80059e0: 6013 str r3, [r2, #0] portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI; - 8004e62: 4b15 ldr r3, [pc, #84] ; (8004eb8 ) - 8004e64: 681b ldr r3, [r3, #0] - 8004e66: 4a14 ldr r2, [pc, #80] ; (8004eb8 ) - 8004e68: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000 - 8004e6c: 6013 str r3, [r2, #0] + 80059e2: 4b15 ldr r3, [pc, #84] ; (8005a38 ) + 80059e4: 681b ldr r3, [r3, #0] + 80059e6: 4a14 ldr r2, [pc, #80] ; (8005a38 ) + 80059e8: f043 4370 orr.w r3, r3, #4026531840 ; 0xf0000000 + 80059ec: 6013 str r3, [r2, #0] /* Start the timer that generates the tick ISR. Interrupts are disabled here already. */ vPortSetupTimerInterrupt(); - 8004e6e: f000 f8dd bl 800502c + 80059ee: f000 f8dd bl 8005bac /* Initialise the critical nesting count ready for the first task. */ uxCriticalNesting = 0; - 8004e72: 4b12 ldr r3, [pc, #72] ; (8004ebc ) - 8004e74: 2200 movs r2, #0 - 8004e76: 601a str r2, [r3, #0] + 80059f2: 4b12 ldr r3, [pc, #72] ; (8005a3c ) + 80059f4: 2200 movs r2, #0 + 80059f6: 601a str r2, [r3, #0] /* Ensure the VFP is enabled - it should be anyway. */ vPortEnableVFP(); - 8004e78: f000 f8fc bl 8005074 + 80059f8: f000 f8fc bl 8005bf4 /* Lazy save always. */ *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS; - 8004e7c: 4b10 ldr r3, [pc, #64] ; (8004ec0 ) - 8004e7e: 681b ldr r3, [r3, #0] - 8004e80: 4a0f ldr r2, [pc, #60] ; (8004ec0 ) - 8004e82: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000 - 8004e86: 6013 str r3, [r2, #0] + 80059fc: 4b10 ldr r3, [pc, #64] ; (8005a40 ) + 80059fe: 681b ldr r3, [r3, #0] + 8005a00: 4a0f ldr r2, [pc, #60] ; (8005a40 ) + 8005a02: f043 4340 orr.w r3, r3, #3221225472 ; 0xc0000000 + 8005a06: 6013 str r3, [r2, #0] /* Start the first task. */ prvPortStartFirstTask(); - 8004e88: f7ff ff66 bl 8004d58 + 8005a08: f7ff ff66 bl 80058d8 exit error function to prevent compiler warnings about a static function not being called in the case that the application writer overrides this functionality by defining configTASK_RETURN_ADDRESS. Call vTaskSwitchContext() so link time optimisation does not remove the symbol. */ vTaskSwitchContext(); - 8004e8c: f7ff f848 bl 8003f20 + 8005a0c: f7ff f846 bl 8004a9c prvTaskExitError(); - 8004e90: f7ff ff1e bl 8004cd0 + 8005a10: f7ff ff1c bl 800584c /* Should not get here! */ return 0; - 8004e94: 2300 movs r3, #0 + 8005a14: 2300 movs r3, #0 } - 8004e96: 4618 mov r0, r3 - 8004e98: 3718 adds r7, #24 - 8004e9a: 46bd mov sp, r7 - 8004e9c: bd80 pop {r7, pc} - 8004e9e: bf00 nop - 8004ea0: e000ed00 .word 0xe000ed00 - 8004ea4: 410fc271 .word 0x410fc271 - 8004ea8: 410fc270 .word 0x410fc270 - 8004eac: e000e400 .word 0xe000e400 - 8004eb0: 20000eec .word 0x20000eec - 8004eb4: 20000ef0 .word 0x20000ef0 - 8004eb8: e000ed20 .word 0xe000ed20 - 8004ebc: 2000000c .word 0x2000000c - 8004ec0: e000ef34 .word 0xe000ef34 + 8005a16: 4618 mov r0, r3 + 8005a18: 3718 adds r7, #24 + 8005a1a: 46bd mov sp, r7 + 8005a1c: bd80 pop {r7, pc} + 8005a1e: bf00 nop + 8005a20: e000ed00 .word 0xe000ed00 + 8005a24: 410fc271 .word 0x410fc271 + 8005a28: 410fc270 .word 0x410fc270 + 8005a2c: e000e400 .word 0xe000e400 + 8005a30: 20000f3c .word 0x20000f3c + 8005a34: 20000f40 .word 0x20000f40 + 8005a38: e000ed20 .word 0xe000ed20 + 8005a3c: 2000000c .word 0x2000000c + 8005a40: e000ef34 .word 0xe000ef34 -08004ec4 : +08005a44 : configASSERT( uxCriticalNesting == 1000UL ); } /*-----------------------------------------------------------*/ void vPortEnterCritical( void ) { - 8004ec4: b480 push {r7} - 8004ec6: b083 sub sp, #12 - 8004ec8: af00 add r7, sp, #0 + 8005a44: b480 push {r7} + 8005a46: b083 sub sp, #12 + 8005a48: af00 add r7, sp, #0 __asm volatile - 8004eca: f04f 0350 mov.w r3, #80 ; 0x50 - 8004ece: f383 8811 msr BASEPRI, r3 - 8004ed2: f3bf 8f6f isb sy - 8004ed6: f3bf 8f4f dsb sy - 8004eda: 607b str r3, [r7, #4] + 8005a4a: f04f 0350 mov.w r3, #80 ; 0x50 + 8005a4e: f383 8811 msr BASEPRI, r3 + 8005a52: f3bf 8f6f isb sy + 8005a56: f3bf 8f4f dsb sy + 8005a5a: 607b str r3, [r7, #4] } - 8004edc: bf00 nop + 8005a5c: bf00 nop portDISABLE_INTERRUPTS(); uxCriticalNesting++; - 8004ede: 4b0f ldr r3, [pc, #60] ; (8004f1c ) - 8004ee0: 681b ldr r3, [r3, #0] - 8004ee2: 3301 adds r3, #1 - 8004ee4: 4a0d ldr r2, [pc, #52] ; (8004f1c ) - 8004ee6: 6013 str r3, [r2, #0] + 8005a5e: 4b0f ldr r3, [pc, #60] ; (8005a9c ) + 8005a60: 681b ldr r3, [r3, #0] + 8005a62: 3301 adds r3, #1 + 8005a64: 4a0d ldr r2, [pc, #52] ; (8005a9c ) + 8005a66: 6013 str r3, [r2, #0] /* This is not the interrupt safe version of the enter critical function so assert() if it is being called from an interrupt context. Only API functions that end in "FromISR" can be used in an interrupt. Only assert if the critical nesting count is 1 to protect against recursive calls if the assert function also uses a critical section. */ if( uxCriticalNesting == 1 ) - 8004ee8: 4b0c ldr r3, [pc, #48] ; (8004f1c ) - 8004eea: 681b ldr r3, [r3, #0] - 8004eec: 2b01 cmp r3, #1 - 8004eee: d10f bne.n 8004f10 + 8005a68: 4b0c ldr r3, [pc, #48] ; (8005a9c ) + 8005a6a: 681b ldr r3, [r3, #0] + 8005a6c: 2b01 cmp r3, #1 + 8005a6e: d10f bne.n 8005a90 { configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 ); - 8004ef0: 4b0b ldr r3, [pc, #44] ; (8004f20 ) - 8004ef2: 681b ldr r3, [r3, #0] - 8004ef4: b2db uxtb r3, r3 - 8004ef6: 2b00 cmp r3, #0 - 8004ef8: d00a beq.n 8004f10 + 8005a70: 4b0b ldr r3, [pc, #44] ; (8005aa0 ) + 8005a72: 681b ldr r3, [r3, #0] + 8005a74: b2db uxtb r3, r3 + 8005a76: 2b00 cmp r3, #0 + 8005a78: d00a beq.n 8005a90 __asm volatile - 8004efa: f04f 0350 mov.w r3, #80 ; 0x50 - 8004efe: f383 8811 msr BASEPRI, r3 - 8004f02: f3bf 8f6f isb sy - 8004f06: f3bf 8f4f dsb sy - 8004f0a: 603b str r3, [r7, #0] + 8005a7a: f04f 0350 mov.w r3, #80 ; 0x50 + 8005a7e: f383 8811 msr BASEPRI, r3 + 8005a82: f3bf 8f6f isb sy + 8005a86: f3bf 8f4f dsb sy + 8005a8a: 603b str r3, [r7, #0] } - 8004f0c: bf00 nop - 8004f0e: e7fe b.n 8004f0e + 8005a8c: bf00 nop + 8005a8e: e7fe b.n 8005a8e } } - 8004f10: bf00 nop - 8004f12: 370c adds r7, #12 - 8004f14: 46bd mov sp, r7 - 8004f16: f85d 7b04 ldr.w r7, [sp], #4 - 8004f1a: 4770 bx lr - 8004f1c: 2000000c .word 0x2000000c - 8004f20: e000ed04 .word 0xe000ed04 + 8005a90: bf00 nop + 8005a92: 370c adds r7, #12 + 8005a94: 46bd mov sp, r7 + 8005a96: f85d 7b04 ldr.w r7, [sp], #4 + 8005a9a: 4770 bx lr + 8005a9c: 2000000c .word 0x2000000c + 8005aa0: e000ed04 .word 0xe000ed04 -08004f24 : +08005aa4 : /*-----------------------------------------------------------*/ void vPortExitCritical( void ) { - 8004f24: b480 push {r7} - 8004f26: b083 sub sp, #12 - 8004f28: af00 add r7, sp, #0 + 8005aa4: b480 push {r7} + 8005aa6: b083 sub sp, #12 + 8005aa8: af00 add r7, sp, #0 configASSERT( uxCriticalNesting ); - 8004f2a: 4b12 ldr r3, [pc, #72] ; (8004f74 ) - 8004f2c: 681b ldr r3, [r3, #0] - 8004f2e: 2b00 cmp r3, #0 - 8004f30: d10a bne.n 8004f48 + 8005aaa: 4b12 ldr r3, [pc, #72] ; (8005af4 ) + 8005aac: 681b ldr r3, [r3, #0] + 8005aae: 2b00 cmp r3, #0 + 8005ab0: d10a bne.n 8005ac8 __asm volatile - 8004f32: f04f 0350 mov.w r3, #80 ; 0x50 - 8004f36: f383 8811 msr BASEPRI, r3 - 8004f3a: f3bf 8f6f isb sy - 8004f3e: f3bf 8f4f dsb sy - 8004f42: 607b str r3, [r7, #4] + 8005ab2: f04f 0350 mov.w r3, #80 ; 0x50 + 8005ab6: f383 8811 msr BASEPRI, r3 + 8005aba: f3bf 8f6f isb sy + 8005abe: f3bf 8f4f dsb sy + 8005ac2: 607b str r3, [r7, #4] } - 8004f44: bf00 nop - 8004f46: e7fe b.n 8004f46 + 8005ac4: bf00 nop + 8005ac6: e7fe b.n 8005ac6 uxCriticalNesting--; - 8004f48: 4b0a ldr r3, [pc, #40] ; (8004f74 ) - 8004f4a: 681b ldr r3, [r3, #0] - 8004f4c: 3b01 subs r3, #1 - 8004f4e: 4a09 ldr r2, [pc, #36] ; (8004f74 ) - 8004f50: 6013 str r3, [r2, #0] + 8005ac8: 4b0a ldr r3, [pc, #40] ; (8005af4 ) + 8005aca: 681b ldr r3, [r3, #0] + 8005acc: 3b01 subs r3, #1 + 8005ace: 4a09 ldr r2, [pc, #36] ; (8005af4 ) + 8005ad0: 6013 str r3, [r2, #0] if( uxCriticalNesting == 0 ) - 8004f52: 4b08 ldr r3, [pc, #32] ; (8004f74 ) - 8004f54: 681b ldr r3, [r3, #0] - 8004f56: 2b00 cmp r3, #0 - 8004f58: d105 bne.n 8004f66 - 8004f5a: 2300 movs r3, #0 - 8004f5c: 603b str r3, [r7, #0] + 8005ad2: 4b08 ldr r3, [pc, #32] ; (8005af4 ) + 8005ad4: 681b ldr r3, [r3, #0] + 8005ad6: 2b00 cmp r3, #0 + 8005ad8: d105 bne.n 8005ae6 + 8005ada: 2300 movs r3, #0 + 8005adc: 603b str r3, [r7, #0] __asm volatile - 8004f5e: 683b ldr r3, [r7, #0] - 8004f60: f383 8811 msr BASEPRI, r3 + 8005ade: 683b ldr r3, [r7, #0] + 8005ae0: f383 8811 msr BASEPRI, r3 } - 8004f64: bf00 nop + 8005ae4: bf00 nop { portENABLE_INTERRUPTS(); } } - 8004f66: bf00 nop - 8004f68: 370c adds r7, #12 - 8004f6a: 46bd mov sp, r7 - 8004f6c: f85d 7b04 ldr.w r7, [sp], #4 - 8004f70: 4770 bx lr - 8004f72: bf00 nop - 8004f74: 2000000c .word 0x2000000c + 8005ae6: bf00 nop + 8005ae8: 370c adds r7, #12 + 8005aea: 46bd mov sp, r7 + 8005aec: f85d 7b04 ldr.w r7, [sp], #4 + 8005af0: 4770 bx lr + 8005af2: bf00 nop + 8005af4: 2000000c .word 0x2000000c ... -08004f80 : +08005b00 : void xPortPendSVHandler( void ) { /* This is a naked function. */ __asm volatile - 8004f80: f3ef 8009 mrs r0, PSP - 8004f84: f3bf 8f6f isb sy - 8004f88: 4b15 ldr r3, [pc, #84] ; (8004fe0 ) - 8004f8a: 681a ldr r2, [r3, #0] - 8004f8c: f01e 0f10 tst.w lr, #16 - 8004f90: bf08 it eq - 8004f92: ed20 8a10 vstmdbeq r0!, {s16-s31} - 8004f96: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8004f9a: 6010 str r0, [r2, #0] - 8004f9c: e92d 0009 stmdb sp!, {r0, r3} - 8004fa0: f04f 0050 mov.w r0, #80 ; 0x50 - 8004fa4: f380 8811 msr BASEPRI, r0 - 8004fa8: f3bf 8f4f dsb sy - 8004fac: f3bf 8f6f isb sy - 8004fb0: f7fe ffb6 bl 8003f20 - 8004fb4: f04f 0000 mov.w r0, #0 - 8004fb8: f380 8811 msr BASEPRI, r0 - 8004fbc: bc09 pop {r0, r3} - 8004fbe: 6819 ldr r1, [r3, #0] - 8004fc0: 6808 ldr r0, [r1, #0] - 8004fc2: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} - 8004fc6: f01e 0f10 tst.w lr, #16 - 8004fca: bf08 it eq - 8004fcc: ecb0 8a10 vldmiaeq r0!, {s16-s31} - 8004fd0: f380 8809 msr PSP, r0 - 8004fd4: f3bf 8f6f isb sy - 8004fd8: 4770 bx lr - 8004fda: bf00 nop - 8004fdc: f3af 8000 nop.w + 8005b00: f3ef 8009 mrs r0, PSP + 8005b04: f3bf 8f6f isb sy + 8005b08: 4b15 ldr r3, [pc, #84] ; (8005b60 ) + 8005b0a: 681a ldr r2, [r3, #0] + 8005b0c: f01e 0f10 tst.w lr, #16 + 8005b10: bf08 it eq + 8005b12: ed20 8a10 vstmdbeq r0!, {s16-s31} + 8005b16: e920 4ff0 stmdb r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8005b1a: 6010 str r0, [r2, #0] + 8005b1c: e92d 0009 stmdb sp!, {r0, r3} + 8005b20: f04f 0050 mov.w r0, #80 ; 0x50 + 8005b24: f380 8811 msr BASEPRI, r0 + 8005b28: f3bf 8f4f dsb sy + 8005b2c: f3bf 8f6f isb sy + 8005b30: f7fe ffb4 bl 8004a9c + 8005b34: f04f 0000 mov.w r0, #0 + 8005b38: f380 8811 msr BASEPRI, r0 + 8005b3c: bc09 pop {r0, r3} + 8005b3e: 6819 ldr r1, [r3, #0] + 8005b40: 6808 ldr r0, [r1, #0] + 8005b42: e8b0 4ff0 ldmia.w r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8005b46: f01e 0f10 tst.w lr, #16 + 8005b4a: bf08 it eq + 8005b4c: ecb0 8a10 vldmiaeq r0!, {s16-s31} + 8005b50: f380 8809 msr PSP, r0 + 8005b54: f3bf 8f6f isb sy + 8005b58: 4770 bx lr + 8005b5a: bf00 nop + 8005b5c: f3af 8000 nop.w -08004fe0 : - 8004fe0: 200008c0 .word 0x200008c0 +08005b60 : + 8005b60: 20000910 .word 0x20000910 " \n" " .align 4 \n" "pxCurrentTCBConst: .word pxCurrentTCB \n" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) ); } - 8004fe4: bf00 nop - 8004fe6: bf00 nop + 8005b64: bf00 nop + 8005b66: bf00 nop -08004fe8 : +08005b68 : /*-----------------------------------------------------------*/ void xPortSysTickHandler( void ) { - 8004fe8: b580 push {r7, lr} - 8004fea: b082 sub sp, #8 - 8004fec: af00 add r7, sp, #0 + 8005b68: b580 push {r7, lr} + 8005b6a: b082 sub sp, #8 + 8005b6c: af00 add r7, sp, #0 __asm volatile - 8004fee: f04f 0350 mov.w r3, #80 ; 0x50 - 8004ff2: f383 8811 msr BASEPRI, r3 - 8004ff6: f3bf 8f6f isb sy - 8004ffa: f3bf 8f4f dsb sy - 8004ffe: 607b str r3, [r7, #4] + 8005b6e: f04f 0350 mov.w r3, #80 ; 0x50 + 8005b72: f383 8811 msr BASEPRI, r3 + 8005b76: f3bf 8f6f isb sy + 8005b7a: f3bf 8f4f dsb sy + 8005b7e: 607b str r3, [r7, #4] } - 8005000: bf00 nop + 8005b80: bf00 nop save and then restore the interrupt mask value as its value is already known. */ portDISABLE_INTERRUPTS(); { /* Increment the RTOS tick. */ if( xTaskIncrementTick() != pdFALSE ) - 8005002: f7fe fed3 bl 8003dac - 8005006: 4603 mov r3, r0 - 8005008: 2b00 cmp r3, #0 - 800500a: d003 beq.n 8005014 + 8005b82: f7fe fed1 bl 8004928 + 8005b86: 4603 mov r3, r0 + 8005b88: 2b00 cmp r3, #0 + 8005b8a: d003 beq.n 8005b94 { /* A context switch is required. Context switching is performed in the PendSV interrupt. Pend the PendSV interrupt. */ portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; - 800500c: 4b06 ldr r3, [pc, #24] ; (8005028 ) - 800500e: f04f 5280 mov.w r2, #268435456 ; 0x10000000 - 8005012: 601a str r2, [r3, #0] - 8005014: 2300 movs r3, #0 - 8005016: 603b str r3, [r7, #0] + 8005b8c: 4b06 ldr r3, [pc, #24] ; (8005ba8 ) + 8005b8e: f04f 5280 mov.w r2, #268435456 ; 0x10000000 + 8005b92: 601a str r2, [r3, #0] + 8005b94: 2300 movs r3, #0 + 8005b96: 603b str r3, [r7, #0] __asm volatile - 8005018: 683b ldr r3, [r7, #0] - 800501a: f383 8811 msr BASEPRI, r3 + 8005b98: 683b ldr r3, [r7, #0] + 8005b9a: f383 8811 msr BASEPRI, r3 } - 800501e: bf00 nop + 8005b9e: bf00 nop } } portENABLE_INTERRUPTS(); } - 8005020: bf00 nop - 8005022: 3708 adds r7, #8 - 8005024: 46bd mov sp, r7 - 8005026: bd80 pop {r7, pc} - 8005028: e000ed04 .word 0xe000ed04 + 8005ba0: bf00 nop + 8005ba2: 3708 adds r7, #8 + 8005ba4: 46bd mov sp, r7 + 8005ba6: bd80 pop {r7, pc} + 8005ba8: e000ed04 .word 0xe000ed04 -0800502c : +08005bac : /* * Setup the systick timer to generate the tick interrupts at the required * frequency. */ __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) { - 800502c: b480 push {r7} - 800502e: af00 add r7, sp, #0 + 8005bac: b480 push {r7} + 8005bae: af00 add r7, sp, #0 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ ); } #endif /* configUSE_TICKLESS_IDLE */ /* Stop and clear the SysTick. */ portNVIC_SYSTICK_CTRL_REG = 0UL; - 8005030: 4b0b ldr r3, [pc, #44] ; (8005060 ) - 8005032: 2200 movs r2, #0 - 8005034: 601a str r2, [r3, #0] + 8005bb0: 4b0b ldr r3, [pc, #44] ; (8005be0 ) + 8005bb2: 2200 movs r2, #0 + 8005bb4: 601a str r2, [r3, #0] portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL; - 8005036: 4b0b ldr r3, [pc, #44] ; (8005064 ) - 8005038: 2200 movs r2, #0 - 800503a: 601a str r2, [r3, #0] + 8005bb6: 4b0b ldr r3, [pc, #44] ; (8005be4 ) + 8005bb8: 2200 movs r2, #0 + 8005bba: 601a str r2, [r3, #0] /* Configure SysTick to interrupt at the requested rate. */ portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL; - 800503c: 4b0a ldr r3, [pc, #40] ; (8005068 ) - 800503e: 681b ldr r3, [r3, #0] - 8005040: 4a0a ldr r2, [pc, #40] ; (800506c ) - 8005042: fba2 2303 umull r2, r3, r2, r3 - 8005046: 099b lsrs r3, r3, #6 - 8005048: 4a09 ldr r2, [pc, #36] ; (8005070 ) - 800504a: 3b01 subs r3, #1 - 800504c: 6013 str r3, [r2, #0] + 8005bbc: 4b0a ldr r3, [pc, #40] ; (8005be8 ) + 8005bbe: 681b ldr r3, [r3, #0] + 8005bc0: 4a0a ldr r2, [pc, #40] ; (8005bec ) + 8005bc2: fba2 2303 umull r2, r3, r2, r3 + 8005bc6: 099b lsrs r3, r3, #6 + 8005bc8: 4a09 ldr r2, [pc, #36] ; (8005bf0 ) + 8005bca: 3b01 subs r3, #1 + 8005bcc: 6013 str r3, [r2, #0] portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT ); - 800504e: 4b04 ldr r3, [pc, #16] ; (8005060 ) - 8005050: 2207 movs r2, #7 - 8005052: 601a str r2, [r3, #0] + 8005bce: 4b04 ldr r3, [pc, #16] ; (8005be0 ) + 8005bd0: 2207 movs r2, #7 + 8005bd2: 601a str r2, [r3, #0] } - 8005054: bf00 nop - 8005056: 46bd mov sp, r7 - 8005058: f85d 7b04 ldr.w r7, [sp], #4 - 800505c: 4770 bx lr - 800505e: bf00 nop - 8005060: e000e010 .word 0xe000e010 - 8005064: e000e018 .word 0xe000e018 - 8005068: 20000000 .word 0x20000000 - 800506c: 10624dd3 .word 0x10624dd3 - 8005070: e000e014 .word 0xe000e014 + 8005bd4: bf00 nop + 8005bd6: 46bd mov sp, r7 + 8005bd8: f85d 7b04 ldr.w r7, [sp], #4 + 8005bdc: 4770 bx lr + 8005bde: bf00 nop + 8005be0: e000e010 .word 0xe000e010 + 8005be4: e000e018 .word 0xe000e018 + 8005be8: 20000000 .word 0x20000000 + 8005bec: 10624dd3 .word 0x10624dd3 + 8005bf0: e000e014 .word 0xe000e014 -08005074 : +08005bf4 : /*-----------------------------------------------------------*/ /* This is a naked function. */ static void vPortEnableVFP( void ) { __asm volatile - 8005074: f8df 000c ldr.w r0, [pc, #12] ; 8005084 - 8005078: 6801 ldr r1, [r0, #0] - 800507a: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 - 800507e: 6001 str r1, [r0, #0] - 8005080: 4770 bx lr + 8005bf4: f8df 000c ldr.w r0, [pc, #12] ; 8005c04 + 8005bf8: 6801 ldr r1, [r0, #0] + 8005bfa: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 + 8005bfe: 6001 str r1, [r0, #0] + 8005c00: 4770 bx lr " \n" " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */ " str r1, [r0] \n" " bx r14 " ); } - 8005082: bf00 nop - 8005084: e000ed88 .word 0xe000ed88 + 8005c02: bf00 nop + 8005c04: e000ed88 .word 0xe000ed88 -08005088 : +08005c08 : /*-----------------------------------------------------------*/ #if( configASSERT_DEFINED == 1 ) void vPortValidateInterruptPriority( void ) { - 8005088: b480 push {r7} - 800508a: b085 sub sp, #20 - 800508c: af00 add r7, sp, #0 + 8005c08: b480 push {r7} + 8005c0a: b085 sub sp, #20 + 8005c0c: af00 add r7, sp, #0 uint32_t ulCurrentInterrupt; uint8_t ucCurrentPriority; /* Obtain the number of the currently executing interrupt. */ __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" ); - 800508e: f3ef 8305 mrs r3, IPSR - 8005092: 60fb str r3, [r7, #12] + 8005c0e: f3ef 8305 mrs r3, IPSR + 8005c12: 60fb str r3, [r7, #12] /* Is the interrupt number a user defined interrupt? */ if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER ) - 8005094: 68fb ldr r3, [r7, #12] - 8005096: 2b0f cmp r3, #15 - 8005098: d914 bls.n 80050c4 + 8005c14: 68fb ldr r3, [r7, #12] + 8005c16: 2b0f cmp r3, #15 + 8005c18: d914 bls.n 8005c44 { /* Look up the interrupt's priority. */ ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ]; - 800509a: 4a17 ldr r2, [pc, #92] ; (80050f8 ) - 800509c: 68fb ldr r3, [r7, #12] - 800509e: 4413 add r3, r2 - 80050a0: 781b ldrb r3, [r3, #0] - 80050a2: 72fb strb r3, [r7, #11] + 8005c1a: 4a17 ldr r2, [pc, #92] ; (8005c78 ) + 8005c1c: 68fb ldr r3, [r7, #12] + 8005c1e: 4413 add r3, r2 + 8005c20: 781b ldrb r3, [r3, #0] + 8005c22: 72fb strb r3, [r7, #11] interrupt entry is as fast and simple as possible. The following links provide detailed information: http://www.freertos.org/RTOS-Cortex-M3-M4.html http://www.freertos.org/FAQHelp.html */ configASSERT( ucCurrentPriority >= ucMaxSysCallPriority ); - 80050a4: 4b15 ldr r3, [pc, #84] ; (80050fc ) - 80050a6: 781b ldrb r3, [r3, #0] - 80050a8: 7afa ldrb r2, [r7, #11] - 80050aa: 429a cmp r2, r3 - 80050ac: d20a bcs.n 80050c4 + 8005c24: 4b15 ldr r3, [pc, #84] ; (8005c7c ) + 8005c26: 781b ldrb r3, [r3, #0] + 8005c28: 7afa ldrb r2, [r7, #11] + 8005c2a: 429a cmp r2, r3 + 8005c2c: d20a bcs.n 8005c44 __asm volatile - 80050ae: f04f 0350 mov.w r3, #80 ; 0x50 - 80050b2: f383 8811 msr BASEPRI, r3 - 80050b6: f3bf 8f6f isb sy - 80050ba: f3bf 8f4f dsb sy - 80050be: 607b str r3, [r7, #4] + 8005c2e: f04f 0350 mov.w r3, #80 ; 0x50 + 8005c32: f383 8811 msr BASEPRI, r3 + 8005c36: f3bf 8f6f isb sy + 8005c3a: f3bf 8f4f dsb sy + 8005c3e: 607b str r3, [r7, #4] } - 80050c0: bf00 nop - 80050c2: e7fe b.n 80050c2 + 8005c40: bf00 nop + 8005c42: e7fe b.n 8005c42 configuration then the correct setting can be achieved on all Cortex-M devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the scheduler. Note however that some vendor specific peripheral libraries assume a non-zero priority group setting, in which cases using a value of zero will result in unpredictable behaviour. */ configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue ); - 80050c4: 4b0e ldr r3, [pc, #56] ; (8005100 ) - 80050c6: 681b ldr r3, [r3, #0] - 80050c8: f403 62e0 and.w r2, r3, #1792 ; 0x700 - 80050cc: 4b0d ldr r3, [pc, #52] ; (8005104 ) - 80050ce: 681b ldr r3, [r3, #0] - 80050d0: 429a cmp r2, r3 - 80050d2: d90a bls.n 80050ea + 8005c44: 4b0e ldr r3, [pc, #56] ; (8005c80 ) + 8005c46: 681b ldr r3, [r3, #0] + 8005c48: f403 62e0 and.w r2, r3, #1792 ; 0x700 + 8005c4c: 4b0d ldr r3, [pc, #52] ; (8005c84 ) + 8005c4e: 681b ldr r3, [r3, #0] + 8005c50: 429a cmp r2, r3 + 8005c52: d90a bls.n 8005c6a __asm volatile - 80050d4: f04f 0350 mov.w r3, #80 ; 0x50 - 80050d8: f383 8811 msr BASEPRI, r3 - 80050dc: f3bf 8f6f isb sy - 80050e0: f3bf 8f4f dsb sy - 80050e4: 603b str r3, [r7, #0] + 8005c54: f04f 0350 mov.w r3, #80 ; 0x50 + 8005c58: f383 8811 msr BASEPRI, r3 + 8005c5c: f3bf 8f6f isb sy + 8005c60: f3bf 8f4f dsb sy + 8005c64: 603b str r3, [r7, #0] } - 80050e6: bf00 nop - 80050e8: e7fe b.n 80050e8 + 8005c66: bf00 nop + 8005c68: e7fe b.n 8005c68 } - 80050ea: bf00 nop - 80050ec: 3714 adds r7, #20 - 80050ee: 46bd mov sp, r7 - 80050f0: f85d 7b04 ldr.w r7, [sp], #4 - 80050f4: 4770 bx lr - 80050f6: bf00 nop - 80050f8: e000e3f0 .word 0xe000e3f0 - 80050fc: 20000eec .word 0x20000eec - 8005100: e000ed0c .word 0xe000ed0c - 8005104: 20000ef0 .word 0x20000ef0 + 8005c6a: bf00 nop + 8005c6c: 3714 adds r7, #20 + 8005c6e: 46bd mov sp, r7 + 8005c70: f85d 7b04 ldr.w r7, [sp], #4 + 8005c74: 4770 bx lr + 8005c76: bf00 nop + 8005c78: e000e3f0 .word 0xe000e3f0 + 8005c7c: 20000f3c .word 0x20000f3c + 8005c80: e000ed0c .word 0xe000ed0c + 8005c84: 20000f40 .word 0x20000f40 -08005108 : +08005c88 : static size_t xBlockAllocatedBit = 0; /*-----------------------------------------------------------*/ void *pvPortMalloc( size_t xWantedSize ) { - 8005108: b580 push {r7, lr} - 800510a: b08a sub sp, #40 ; 0x28 - 800510c: af00 add r7, sp, #0 - 800510e: 6078 str r0, [r7, #4] + 8005c88: b580 push {r7, lr} + 8005c8a: b08a sub sp, #40 ; 0x28 + 8005c8c: af00 add r7, sp, #0 + 8005c8e: 6078 str r0, [r7, #4] BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink; void *pvReturn = NULL; - 8005110: 2300 movs r3, #0 - 8005112: 61fb str r3, [r7, #28] + 8005c90: 2300 movs r3, #0 + 8005c92: 61fb str r3, [r7, #28] vTaskSuspendAll(); - 8005114: f7fe fd8e bl 8003c34 + 8005c94: f7fe fd8c bl 80047b0 { /* If this is the first call to malloc then the heap will require initialisation to setup the list of free blocks. */ if( pxEnd == NULL ) - 8005118: 4b5b ldr r3, [pc, #364] ; (8005288 ) - 800511a: 681b ldr r3, [r3, #0] - 800511c: 2b00 cmp r3, #0 - 800511e: d101 bne.n 8005124 + 8005c98: 4b5b ldr r3, [pc, #364] ; (8005e08 ) + 8005c9a: 681b ldr r3, [r3, #0] + 8005c9c: 2b00 cmp r3, #0 + 8005c9e: d101 bne.n 8005ca4 { prvHeapInit(); - 8005120: f000 f920 bl 8005364 + 8005ca0: f000 f920 bl 8005ee4 /* Check the requested block size is not so large that the top bit is set. The top bit of the block size member of the BlockLink_t structure is used to determine who owns the block - the application or the kernel, so it must be free. */ if( ( xWantedSize & xBlockAllocatedBit ) == 0 ) - 8005124: 4b59 ldr r3, [pc, #356] ; (800528c ) - 8005126: 681a ldr r2, [r3, #0] - 8005128: 687b ldr r3, [r7, #4] - 800512a: 4013 ands r3, r2 - 800512c: 2b00 cmp r3, #0 - 800512e: f040 8093 bne.w 8005258 + 8005ca4: 4b59 ldr r3, [pc, #356] ; (8005e0c ) + 8005ca6: 681a ldr r2, [r3, #0] + 8005ca8: 687b ldr r3, [r7, #4] + 8005caa: 4013 ands r3, r2 + 8005cac: 2b00 cmp r3, #0 + 8005cae: f040 8093 bne.w 8005dd8 { /* The wanted size is increased so it can contain a BlockLink_t structure in addition to the requested amount of bytes. */ if( xWantedSize > 0 ) - 8005132: 687b ldr r3, [r7, #4] - 8005134: 2b00 cmp r3, #0 - 8005136: d01d beq.n 8005174 + 8005cb2: 687b ldr r3, [r7, #4] + 8005cb4: 2b00 cmp r3, #0 + 8005cb6: d01d beq.n 8005cf4 { xWantedSize += xHeapStructSize; - 8005138: 2208 movs r2, #8 - 800513a: 687b ldr r3, [r7, #4] - 800513c: 4413 add r3, r2 - 800513e: 607b str r3, [r7, #4] + 8005cb8: 2208 movs r2, #8 + 8005cba: 687b ldr r3, [r7, #4] + 8005cbc: 4413 add r3, r2 + 8005cbe: 607b str r3, [r7, #4] /* Ensure that blocks are always aligned to the required number of bytes. */ if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 ) - 8005140: 687b ldr r3, [r7, #4] - 8005142: f003 0307 and.w r3, r3, #7 - 8005146: 2b00 cmp r3, #0 - 8005148: d014 beq.n 8005174 + 8005cc0: 687b ldr r3, [r7, #4] + 8005cc2: f003 0307 and.w r3, r3, #7 + 8005cc6: 2b00 cmp r3, #0 + 8005cc8: d014 beq.n 8005cf4 { /* Byte alignment required. */ xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ); - 800514a: 687b ldr r3, [r7, #4] - 800514c: f023 0307 bic.w r3, r3, #7 - 8005150: 3308 adds r3, #8 - 8005152: 607b str r3, [r7, #4] + 8005cca: 687b ldr r3, [r7, #4] + 8005ccc: f023 0307 bic.w r3, r3, #7 + 8005cd0: 3308 adds r3, #8 + 8005cd2: 607b str r3, [r7, #4] configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 ); - 8005154: 687b ldr r3, [r7, #4] - 8005156: f003 0307 and.w r3, r3, #7 - 800515a: 2b00 cmp r3, #0 - 800515c: d00a beq.n 8005174 + 8005cd4: 687b ldr r3, [r7, #4] + 8005cd6: f003 0307 and.w r3, r3, #7 + 8005cda: 2b00 cmp r3, #0 + 8005cdc: d00a beq.n 8005cf4 __asm volatile - 800515e: f04f 0350 mov.w r3, #80 ; 0x50 - 8005162: f383 8811 msr BASEPRI, r3 - 8005166: f3bf 8f6f isb sy - 800516a: f3bf 8f4f dsb sy - 800516e: 617b str r3, [r7, #20] + 8005cde: f04f 0350 mov.w r3, #80 ; 0x50 + 8005ce2: f383 8811 msr BASEPRI, r3 + 8005ce6: f3bf 8f6f isb sy + 8005cea: f3bf 8f4f dsb sy + 8005cee: 617b str r3, [r7, #20] } - 8005170: bf00 nop - 8005172: e7fe b.n 8005172 + 8005cf0: bf00 nop + 8005cf2: e7fe b.n 8005cf2 else { mtCOVERAGE_TEST_MARKER(); } if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) ) - 8005174: 687b ldr r3, [r7, #4] - 8005176: 2b00 cmp r3, #0 - 8005178: d06e beq.n 8005258 - 800517a: 4b45 ldr r3, [pc, #276] ; (8005290 ) - 800517c: 681b ldr r3, [r3, #0] - 800517e: 687a ldr r2, [r7, #4] - 8005180: 429a cmp r2, r3 - 8005182: d869 bhi.n 8005258 + 8005cf4: 687b ldr r3, [r7, #4] + 8005cf6: 2b00 cmp r3, #0 + 8005cf8: d06e beq.n 8005dd8 + 8005cfa: 4b45 ldr r3, [pc, #276] ; (8005e10 ) + 8005cfc: 681b ldr r3, [r3, #0] + 8005cfe: 687a ldr r2, [r7, #4] + 8005d00: 429a cmp r2, r3 + 8005d02: d869 bhi.n 8005dd8 { /* Traverse the list from the start (lowest address) block until one of adequate size is found. */ pxPreviousBlock = &xStart; - 8005184: 4b43 ldr r3, [pc, #268] ; (8005294 ) - 8005186: 623b str r3, [r7, #32] + 8005d04: 4b43 ldr r3, [pc, #268] ; (8005e14 ) + 8005d06: 623b str r3, [r7, #32] pxBlock = xStart.pxNextFreeBlock; - 8005188: 4b42 ldr r3, [pc, #264] ; (8005294 ) - 800518a: 681b ldr r3, [r3, #0] - 800518c: 627b str r3, [r7, #36] ; 0x24 + 8005d08: 4b42 ldr r3, [pc, #264] ; (8005e14 ) + 8005d0a: 681b ldr r3, [r3, #0] + 8005d0c: 627b str r3, [r7, #36] ; 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) - 800518e: e004 b.n 800519a + 8005d0e: e004 b.n 8005d1a { pxPreviousBlock = pxBlock; - 8005190: 6a7b ldr r3, [r7, #36] ; 0x24 - 8005192: 623b str r3, [r7, #32] + 8005d10: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d12: 623b str r3, [r7, #32] pxBlock = pxBlock->pxNextFreeBlock; - 8005194: 6a7b ldr r3, [r7, #36] ; 0x24 - 8005196: 681b ldr r3, [r3, #0] - 8005198: 627b str r3, [r7, #36] ; 0x24 + 8005d14: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d16: 681b ldr r3, [r3, #0] + 8005d18: 627b str r3, [r7, #36] ; 0x24 while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) ) - 800519a: 6a7b ldr r3, [r7, #36] ; 0x24 - 800519c: 685b ldr r3, [r3, #4] - 800519e: 687a ldr r2, [r7, #4] - 80051a0: 429a cmp r2, r3 - 80051a2: d903 bls.n 80051ac - 80051a4: 6a7b ldr r3, [r7, #36] ; 0x24 - 80051a6: 681b ldr r3, [r3, #0] - 80051a8: 2b00 cmp r3, #0 - 80051aa: d1f1 bne.n 8005190 + 8005d1a: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d1c: 685b ldr r3, [r3, #4] + 8005d1e: 687a ldr r2, [r7, #4] + 8005d20: 429a cmp r2, r3 + 8005d22: d903 bls.n 8005d2c + 8005d24: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d26: 681b ldr r3, [r3, #0] + 8005d28: 2b00 cmp r3, #0 + 8005d2a: d1f1 bne.n 8005d10 } /* If the end marker was reached then a block of adequate size was not found. */ if( pxBlock != pxEnd ) - 80051ac: 4b36 ldr r3, [pc, #216] ; (8005288 ) - 80051ae: 681b ldr r3, [r3, #0] - 80051b0: 6a7a ldr r2, [r7, #36] ; 0x24 - 80051b2: 429a cmp r2, r3 - 80051b4: d050 beq.n 8005258 + 8005d2c: 4b36 ldr r3, [pc, #216] ; (8005e08 ) + 8005d2e: 681b ldr r3, [r3, #0] + 8005d30: 6a7a ldr r2, [r7, #36] ; 0x24 + 8005d32: 429a cmp r2, r3 + 8005d34: d050 beq.n 8005dd8 { /* Return the memory space pointed to - jumping over the BlockLink_t structure at its start. */ pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize ); - 80051b6: 6a3b ldr r3, [r7, #32] - 80051b8: 681b ldr r3, [r3, #0] - 80051ba: 2208 movs r2, #8 - 80051bc: 4413 add r3, r2 - 80051be: 61fb str r3, [r7, #28] + 8005d36: 6a3b ldr r3, [r7, #32] + 8005d38: 681b ldr r3, [r3, #0] + 8005d3a: 2208 movs r2, #8 + 8005d3c: 4413 add r3, r2 + 8005d3e: 61fb str r3, [r7, #28] /* This block is being returned for use so must be taken out of the list of free blocks. */ pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock; - 80051c0: 6a7b ldr r3, [r7, #36] ; 0x24 - 80051c2: 681a ldr r2, [r3, #0] - 80051c4: 6a3b ldr r3, [r7, #32] - 80051c6: 601a str r2, [r3, #0] + 8005d40: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d42: 681a ldr r2, [r3, #0] + 8005d44: 6a3b ldr r3, [r7, #32] + 8005d46: 601a str r2, [r3, #0] /* If the block is larger than required it can be split into two. */ if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE ) - 80051c8: 6a7b ldr r3, [r7, #36] ; 0x24 - 80051ca: 685a ldr r2, [r3, #4] - 80051cc: 687b ldr r3, [r7, #4] - 80051ce: 1ad2 subs r2, r2, r3 - 80051d0: 2308 movs r3, #8 - 80051d2: 005b lsls r3, r3, #1 - 80051d4: 429a cmp r2, r3 - 80051d6: d91f bls.n 8005218 + 8005d48: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d4a: 685a ldr r2, [r3, #4] + 8005d4c: 687b ldr r3, [r7, #4] + 8005d4e: 1ad2 subs r2, r2, r3 + 8005d50: 2308 movs r3, #8 + 8005d52: 005b lsls r3, r3, #1 + 8005d54: 429a cmp r2, r3 + 8005d56: d91f bls.n 8005d98 { /* This block is to be split into two. Create a new block following the number of bytes requested. The void cast is used to prevent byte alignment warnings from the compiler. */ pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize ); - 80051d8: 6a7a ldr r2, [r7, #36] ; 0x24 - 80051da: 687b ldr r3, [r7, #4] - 80051dc: 4413 add r3, r2 - 80051de: 61bb str r3, [r7, #24] + 8005d58: 6a7a ldr r2, [r7, #36] ; 0x24 + 8005d5a: 687b ldr r3, [r7, #4] + 8005d5c: 4413 add r3, r2 + 8005d5e: 61bb str r3, [r7, #24] configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 ); - 80051e0: 69bb ldr r3, [r7, #24] - 80051e2: f003 0307 and.w r3, r3, #7 - 80051e6: 2b00 cmp r3, #0 - 80051e8: d00a beq.n 8005200 + 8005d60: 69bb ldr r3, [r7, #24] + 8005d62: f003 0307 and.w r3, r3, #7 + 8005d66: 2b00 cmp r3, #0 + 8005d68: d00a beq.n 8005d80 __asm volatile - 80051ea: f04f 0350 mov.w r3, #80 ; 0x50 - 80051ee: f383 8811 msr BASEPRI, r3 - 80051f2: f3bf 8f6f isb sy - 80051f6: f3bf 8f4f dsb sy - 80051fa: 613b str r3, [r7, #16] + 8005d6a: f04f 0350 mov.w r3, #80 ; 0x50 + 8005d6e: f383 8811 msr BASEPRI, r3 + 8005d72: f3bf 8f6f isb sy + 8005d76: f3bf 8f4f dsb sy + 8005d7a: 613b str r3, [r7, #16] } - 80051fc: bf00 nop - 80051fe: e7fe b.n 80051fe + 8005d7c: bf00 nop + 8005d7e: e7fe b.n 8005d7e /* Calculate the sizes of two blocks split from the single block. */ pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize; - 8005200: 6a7b ldr r3, [r7, #36] ; 0x24 - 8005202: 685a ldr r2, [r3, #4] - 8005204: 687b ldr r3, [r7, #4] - 8005206: 1ad2 subs r2, r2, r3 - 8005208: 69bb ldr r3, [r7, #24] - 800520a: 605a str r2, [r3, #4] + 8005d80: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d82: 685a ldr r2, [r3, #4] + 8005d84: 687b ldr r3, [r7, #4] + 8005d86: 1ad2 subs r2, r2, r3 + 8005d88: 69bb ldr r3, [r7, #24] + 8005d8a: 605a str r2, [r3, #4] pxBlock->xBlockSize = xWantedSize; - 800520c: 6a7b ldr r3, [r7, #36] ; 0x24 - 800520e: 687a ldr r2, [r7, #4] - 8005210: 605a str r2, [r3, #4] + 8005d8c: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d8e: 687a ldr r2, [r7, #4] + 8005d90: 605a str r2, [r3, #4] /* Insert the new block into the list of free blocks. */ prvInsertBlockIntoFreeList( pxNewBlockLink ); - 8005212: 69b8 ldr r0, [r7, #24] - 8005214: f000 f908 bl 8005428 + 8005d92: 69b8 ldr r0, [r7, #24] + 8005d94: f000 f908 bl 8005fa8 else { mtCOVERAGE_TEST_MARKER(); } xFreeBytesRemaining -= pxBlock->xBlockSize; - 8005218: 4b1d ldr r3, [pc, #116] ; (8005290 ) - 800521a: 681a ldr r2, [r3, #0] - 800521c: 6a7b ldr r3, [r7, #36] ; 0x24 - 800521e: 685b ldr r3, [r3, #4] - 8005220: 1ad3 subs r3, r2, r3 - 8005222: 4a1b ldr r2, [pc, #108] ; (8005290 ) - 8005224: 6013 str r3, [r2, #0] + 8005d98: 4b1d ldr r3, [pc, #116] ; (8005e10 ) + 8005d9a: 681a ldr r2, [r3, #0] + 8005d9c: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d9e: 685b ldr r3, [r3, #4] + 8005da0: 1ad3 subs r3, r2, r3 + 8005da2: 4a1b ldr r2, [pc, #108] ; (8005e10 ) + 8005da4: 6013 str r3, [r2, #0] if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining ) - 8005226: 4b1a ldr r3, [pc, #104] ; (8005290 ) - 8005228: 681a ldr r2, [r3, #0] - 800522a: 4b1b ldr r3, [pc, #108] ; (8005298 ) - 800522c: 681b ldr r3, [r3, #0] - 800522e: 429a cmp r2, r3 - 8005230: d203 bcs.n 800523a + 8005da6: 4b1a ldr r3, [pc, #104] ; (8005e10 ) + 8005da8: 681a ldr r2, [r3, #0] + 8005daa: 4b1b ldr r3, [pc, #108] ; (8005e18 ) + 8005dac: 681b ldr r3, [r3, #0] + 8005dae: 429a cmp r2, r3 + 8005db0: d203 bcs.n 8005dba { xMinimumEverFreeBytesRemaining = xFreeBytesRemaining; - 8005232: 4b17 ldr r3, [pc, #92] ; (8005290 ) - 8005234: 681b ldr r3, [r3, #0] - 8005236: 4a18 ldr r2, [pc, #96] ; (8005298 ) - 8005238: 6013 str r3, [r2, #0] + 8005db2: 4b17 ldr r3, [pc, #92] ; (8005e10 ) + 8005db4: 681b ldr r3, [r3, #0] + 8005db6: 4a18 ldr r2, [pc, #96] ; (8005e18 ) + 8005db8: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } /* The block is being returned - it is allocated and owned by the application and has no "next" block. */ pxBlock->xBlockSize |= xBlockAllocatedBit; - 800523a: 6a7b ldr r3, [r7, #36] ; 0x24 - 800523c: 685a ldr r2, [r3, #4] - 800523e: 4b13 ldr r3, [pc, #76] ; (800528c ) - 8005240: 681b ldr r3, [r3, #0] - 8005242: 431a orrs r2, r3 - 8005244: 6a7b ldr r3, [r7, #36] ; 0x24 - 8005246: 605a str r2, [r3, #4] + 8005dba: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005dbc: 685a ldr r2, [r3, #4] + 8005dbe: 4b13 ldr r3, [pc, #76] ; (8005e0c ) + 8005dc0: 681b ldr r3, [r3, #0] + 8005dc2: 431a orrs r2, r3 + 8005dc4: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005dc6: 605a str r2, [r3, #4] pxBlock->pxNextFreeBlock = NULL; - 8005248: 6a7b ldr r3, [r7, #36] ; 0x24 - 800524a: 2200 movs r2, #0 - 800524c: 601a str r2, [r3, #0] + 8005dc8: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005dca: 2200 movs r2, #0 + 8005dcc: 601a str r2, [r3, #0] xNumberOfSuccessfulAllocations++; - 800524e: 4b13 ldr r3, [pc, #76] ; (800529c ) - 8005250: 681b ldr r3, [r3, #0] - 8005252: 3301 adds r3, #1 - 8005254: 4a11 ldr r2, [pc, #68] ; (800529c ) - 8005256: 6013 str r3, [r2, #0] + 8005dce: 4b13 ldr r3, [pc, #76] ; (8005e1c ) + 8005dd0: 681b ldr r3, [r3, #0] + 8005dd2: 3301 adds r3, #1 + 8005dd4: 4a11 ldr r2, [pc, #68] ; (8005e1c ) + 8005dd6: 6013 str r3, [r2, #0] mtCOVERAGE_TEST_MARKER(); } traceMALLOC( pvReturn, xWantedSize ); } ( void ) xTaskResumeAll(); - 8005258: f7fe fcfa bl 8003c50 + 8005dd8: f7fe fcf8 bl 80047cc mtCOVERAGE_TEST_MARKER(); } } #endif configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 ); - 800525c: 69fb ldr r3, [r7, #28] - 800525e: f003 0307 and.w r3, r3, #7 - 8005262: 2b00 cmp r3, #0 - 8005264: d00a beq.n 800527c + 8005ddc: 69fb ldr r3, [r7, #28] + 8005dde: f003 0307 and.w r3, r3, #7 + 8005de2: 2b00 cmp r3, #0 + 8005de4: d00a beq.n 8005dfc __asm volatile - 8005266: f04f 0350 mov.w r3, #80 ; 0x50 - 800526a: f383 8811 msr BASEPRI, r3 - 800526e: f3bf 8f6f isb sy - 8005272: f3bf 8f4f dsb sy - 8005276: 60fb str r3, [r7, #12] + 8005de6: f04f 0350 mov.w r3, #80 ; 0x50 + 8005dea: f383 8811 msr BASEPRI, r3 + 8005dee: f3bf 8f6f isb sy + 8005df2: f3bf 8f4f dsb sy + 8005df6: 60fb str r3, [r7, #12] } - 8005278: bf00 nop - 800527a: e7fe b.n 800527a + 8005df8: bf00 nop + 8005dfa: e7fe b.n 8005dfa return pvReturn; - 800527c: 69fb ldr r3, [r7, #28] + 8005dfc: 69fb ldr r3, [r7, #28] } - 800527e: 4618 mov r0, r3 - 8005280: 3728 adds r7, #40 ; 0x28 - 8005282: 46bd mov sp, r7 - 8005284: bd80 pop {r7, pc} - 8005286: bf00 nop - 8005288: 20004afc .word 0x20004afc - 800528c: 20004b10 .word 0x20004b10 - 8005290: 20004b00 .word 0x20004b00 - 8005294: 20004af4 .word 0x20004af4 - 8005298: 20004b04 .word 0x20004b04 - 800529c: 20004b08 .word 0x20004b08 + 8005dfe: 4618 mov r0, r3 + 8005e00: 3728 adds r7, #40 ; 0x28 + 8005e02: 46bd mov sp, r7 + 8005e04: bd80 pop {r7, pc} + 8005e06: bf00 nop + 8005e08: 20004b4c .word 0x20004b4c + 8005e0c: 20004b60 .word 0x20004b60 + 8005e10: 20004b50 .word 0x20004b50 + 8005e14: 20004b44 .word 0x20004b44 + 8005e18: 20004b54 .word 0x20004b54 + 8005e1c: 20004b58 .word 0x20004b58 -080052a0 : +08005e20 : /*-----------------------------------------------------------*/ void vPortFree( void *pv ) { - 80052a0: b580 push {r7, lr} - 80052a2: b086 sub sp, #24 - 80052a4: af00 add r7, sp, #0 - 80052a6: 6078 str r0, [r7, #4] + 8005e20: b580 push {r7, lr} + 8005e22: b086 sub sp, #24 + 8005e24: af00 add r7, sp, #0 + 8005e26: 6078 str r0, [r7, #4] uint8_t *puc = ( uint8_t * ) pv; - 80052a8: 687b ldr r3, [r7, #4] - 80052aa: 617b str r3, [r7, #20] + 8005e28: 687b ldr r3, [r7, #4] + 8005e2a: 617b str r3, [r7, #20] BlockLink_t *pxLink; if( pv != NULL ) - 80052ac: 687b ldr r3, [r7, #4] - 80052ae: 2b00 cmp r3, #0 - 80052b0: d04d beq.n 800534e + 8005e2c: 687b ldr r3, [r7, #4] + 8005e2e: 2b00 cmp r3, #0 + 8005e30: d04d beq.n 8005ece { /* The memory being freed will have an BlockLink_t structure immediately before it. */ puc -= xHeapStructSize; - 80052b2: 2308 movs r3, #8 - 80052b4: 425b negs r3, r3 - 80052b6: 697a ldr r2, [r7, #20] - 80052b8: 4413 add r3, r2 - 80052ba: 617b str r3, [r7, #20] + 8005e32: 2308 movs r3, #8 + 8005e34: 425b negs r3, r3 + 8005e36: 697a ldr r2, [r7, #20] + 8005e38: 4413 add r3, r2 + 8005e3a: 617b str r3, [r7, #20] /* This casting is to keep the compiler from issuing warnings. */ pxLink = ( void * ) puc; - 80052bc: 697b ldr r3, [r7, #20] - 80052be: 613b str r3, [r7, #16] + 8005e3c: 697b ldr r3, [r7, #20] + 8005e3e: 613b str r3, [r7, #16] /* Check the block is actually allocated. */ configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ); - 80052c0: 693b ldr r3, [r7, #16] - 80052c2: 685a ldr r2, [r3, #4] - 80052c4: 4b24 ldr r3, [pc, #144] ; (8005358 ) - 80052c6: 681b ldr r3, [r3, #0] - 80052c8: 4013 ands r3, r2 - 80052ca: 2b00 cmp r3, #0 - 80052cc: d10a bne.n 80052e4 + 8005e40: 693b ldr r3, [r7, #16] + 8005e42: 685a ldr r2, [r3, #4] + 8005e44: 4b24 ldr r3, [pc, #144] ; (8005ed8 ) + 8005e46: 681b ldr r3, [r3, #0] + 8005e48: 4013 ands r3, r2 + 8005e4a: 2b00 cmp r3, #0 + 8005e4c: d10a bne.n 8005e64 __asm volatile - 80052ce: f04f 0350 mov.w r3, #80 ; 0x50 - 80052d2: f383 8811 msr BASEPRI, r3 - 80052d6: f3bf 8f6f isb sy - 80052da: f3bf 8f4f dsb sy - 80052de: 60fb str r3, [r7, #12] + 8005e4e: f04f 0350 mov.w r3, #80 ; 0x50 + 8005e52: f383 8811 msr BASEPRI, r3 + 8005e56: f3bf 8f6f isb sy + 8005e5a: f3bf 8f4f dsb sy + 8005e5e: 60fb str r3, [r7, #12] } - 80052e0: bf00 nop - 80052e2: e7fe b.n 80052e2 + 8005e60: bf00 nop + 8005e62: e7fe b.n 8005e62 configASSERT( pxLink->pxNextFreeBlock == NULL ); - 80052e4: 693b ldr r3, [r7, #16] - 80052e6: 681b ldr r3, [r3, #0] - 80052e8: 2b00 cmp r3, #0 - 80052ea: d00a beq.n 8005302 + 8005e64: 693b ldr r3, [r7, #16] + 8005e66: 681b ldr r3, [r3, #0] + 8005e68: 2b00 cmp r3, #0 + 8005e6a: d00a beq.n 8005e82 __asm volatile - 80052ec: f04f 0350 mov.w r3, #80 ; 0x50 - 80052f0: f383 8811 msr BASEPRI, r3 - 80052f4: f3bf 8f6f isb sy - 80052f8: f3bf 8f4f dsb sy - 80052fc: 60bb str r3, [r7, #8] + 8005e6c: f04f 0350 mov.w r3, #80 ; 0x50 + 8005e70: f383 8811 msr BASEPRI, r3 + 8005e74: f3bf 8f6f isb sy + 8005e78: f3bf 8f4f dsb sy + 8005e7c: 60bb str r3, [r7, #8] } - 80052fe: bf00 nop - 8005300: e7fe b.n 8005300 + 8005e7e: bf00 nop + 8005e80: e7fe b.n 8005e80 if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 ) - 8005302: 693b ldr r3, [r7, #16] - 8005304: 685a ldr r2, [r3, #4] - 8005306: 4b14 ldr r3, [pc, #80] ; (8005358 ) - 8005308: 681b ldr r3, [r3, #0] - 800530a: 4013 ands r3, r2 - 800530c: 2b00 cmp r3, #0 - 800530e: d01e beq.n 800534e + 8005e82: 693b ldr r3, [r7, #16] + 8005e84: 685a ldr r2, [r3, #4] + 8005e86: 4b14 ldr r3, [pc, #80] ; (8005ed8 ) + 8005e88: 681b ldr r3, [r3, #0] + 8005e8a: 4013 ands r3, r2 + 8005e8c: 2b00 cmp r3, #0 + 8005e8e: d01e beq.n 8005ece { if( pxLink->pxNextFreeBlock == NULL ) - 8005310: 693b ldr r3, [r7, #16] - 8005312: 681b ldr r3, [r3, #0] - 8005314: 2b00 cmp r3, #0 - 8005316: d11a bne.n 800534e + 8005e90: 693b ldr r3, [r7, #16] + 8005e92: 681b ldr r3, [r3, #0] + 8005e94: 2b00 cmp r3, #0 + 8005e96: d11a bne.n 8005ece { /* The block is being returned to the heap - it is no longer allocated. */ pxLink->xBlockSize &= ~xBlockAllocatedBit; - 8005318: 693b ldr r3, [r7, #16] - 800531a: 685a ldr r2, [r3, #4] - 800531c: 4b0e ldr r3, [pc, #56] ; (8005358 ) - 800531e: 681b ldr r3, [r3, #0] - 8005320: 43db mvns r3, r3 - 8005322: 401a ands r2, r3 - 8005324: 693b ldr r3, [r7, #16] - 8005326: 605a str r2, [r3, #4] + 8005e98: 693b ldr r3, [r7, #16] + 8005e9a: 685a ldr r2, [r3, #4] + 8005e9c: 4b0e ldr r3, [pc, #56] ; (8005ed8 ) + 8005e9e: 681b ldr r3, [r3, #0] + 8005ea0: 43db mvns r3, r3 + 8005ea2: 401a ands r2, r3 + 8005ea4: 693b ldr r3, [r7, #16] + 8005ea6: 605a str r2, [r3, #4] vTaskSuspendAll(); - 8005328: f7fe fc84 bl 8003c34 + 8005ea8: f7fe fc82 bl 80047b0 { /* Add this block to the list of free blocks. */ xFreeBytesRemaining += pxLink->xBlockSize; - 800532c: 693b ldr r3, [r7, #16] - 800532e: 685a ldr r2, [r3, #4] - 8005330: 4b0a ldr r3, [pc, #40] ; (800535c ) - 8005332: 681b ldr r3, [r3, #0] - 8005334: 4413 add r3, r2 - 8005336: 4a09 ldr r2, [pc, #36] ; (800535c ) - 8005338: 6013 str r3, [r2, #0] + 8005eac: 693b ldr r3, [r7, #16] + 8005eae: 685a ldr r2, [r3, #4] + 8005eb0: 4b0a ldr r3, [pc, #40] ; (8005edc ) + 8005eb2: 681b ldr r3, [r3, #0] + 8005eb4: 4413 add r3, r2 + 8005eb6: 4a09 ldr r2, [pc, #36] ; (8005edc ) + 8005eb8: 6013 str r3, [r2, #0] traceFREE( pv, pxLink->xBlockSize ); prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) ); - 800533a: 6938 ldr r0, [r7, #16] - 800533c: f000 f874 bl 8005428 + 8005eba: 6938 ldr r0, [r7, #16] + 8005ebc: f000 f874 bl 8005fa8 xNumberOfSuccessfulFrees++; - 8005340: 4b07 ldr r3, [pc, #28] ; (8005360 ) - 8005342: 681b ldr r3, [r3, #0] - 8005344: 3301 adds r3, #1 - 8005346: 4a06 ldr r2, [pc, #24] ; (8005360 ) - 8005348: 6013 str r3, [r2, #0] + 8005ec0: 4b07 ldr r3, [pc, #28] ; (8005ee0 ) + 8005ec2: 681b ldr r3, [r3, #0] + 8005ec4: 3301 adds r3, #1 + 8005ec6: 4a06 ldr r2, [pc, #24] ; (8005ee0 ) + 8005ec8: 6013 str r3, [r2, #0] } ( void ) xTaskResumeAll(); - 800534a: f7fe fc81 bl 8003c50 + 8005eca: f7fe fc7f bl 80047cc else { mtCOVERAGE_TEST_MARKER(); } } } - 800534e: bf00 nop - 8005350: 3718 adds r7, #24 - 8005352: 46bd mov sp, r7 - 8005354: bd80 pop {r7, pc} - 8005356: bf00 nop - 8005358: 20004b10 .word 0x20004b10 - 800535c: 20004b00 .word 0x20004b00 - 8005360: 20004b0c .word 0x20004b0c + 8005ece: bf00 nop + 8005ed0: 3718 adds r7, #24 + 8005ed2: 46bd mov sp, r7 + 8005ed4: bd80 pop {r7, pc} + 8005ed6: bf00 nop + 8005ed8: 20004b60 .word 0x20004b60 + 8005edc: 20004b50 .word 0x20004b50 + 8005ee0: 20004b5c .word 0x20004b5c -08005364 : +08005ee4 : /* This just exists to keep the linker quiet. */ } /*-----------------------------------------------------------*/ static void prvHeapInit( void ) { - 8005364: b480 push {r7} - 8005366: b085 sub sp, #20 - 8005368: af00 add r7, sp, #0 + 8005ee4: b480 push {r7} + 8005ee6: b085 sub sp, #20 + 8005ee8: af00 add r7, sp, #0 BlockLink_t *pxFirstFreeBlock; uint8_t *pucAlignedHeap; size_t uxAddress; size_t xTotalHeapSize = configTOTAL_HEAP_SIZE; - 800536a: f44f 5370 mov.w r3, #15360 ; 0x3c00 - 800536e: 60bb str r3, [r7, #8] + 8005eea: f44f 5370 mov.w r3, #15360 ; 0x3c00 + 8005eee: 60bb str r3, [r7, #8] /* Ensure the heap starts on a correctly aligned boundary. */ uxAddress = ( size_t ) ucHeap; - 8005370: 4b27 ldr r3, [pc, #156] ; (8005410 ) - 8005372: 60fb str r3, [r7, #12] + 8005ef0: 4b27 ldr r3, [pc, #156] ; (8005f90 ) + 8005ef2: 60fb str r3, [r7, #12] if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 ) - 8005374: 68fb ldr r3, [r7, #12] - 8005376: f003 0307 and.w r3, r3, #7 - 800537a: 2b00 cmp r3, #0 - 800537c: d00c beq.n 8005398 + 8005ef4: 68fb ldr r3, [r7, #12] + 8005ef6: f003 0307 and.w r3, r3, #7 + 8005efa: 2b00 cmp r3, #0 + 8005efc: d00c beq.n 8005f18 { uxAddress += ( portBYTE_ALIGNMENT - 1 ); - 800537e: 68fb ldr r3, [r7, #12] - 8005380: 3307 adds r3, #7 - 8005382: 60fb str r3, [r7, #12] + 8005efe: 68fb ldr r3, [r7, #12] + 8005f00: 3307 adds r3, #7 + 8005f02: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); - 8005384: 68fb ldr r3, [r7, #12] - 8005386: f023 0307 bic.w r3, r3, #7 - 800538a: 60fb str r3, [r7, #12] + 8005f04: 68fb ldr r3, [r7, #12] + 8005f06: f023 0307 bic.w r3, r3, #7 + 8005f0a: 60fb str r3, [r7, #12] xTotalHeapSize -= uxAddress - ( size_t ) ucHeap; - 800538c: 68ba ldr r2, [r7, #8] - 800538e: 68fb ldr r3, [r7, #12] - 8005390: 1ad3 subs r3, r2, r3 - 8005392: 4a1f ldr r2, [pc, #124] ; (8005410 ) - 8005394: 4413 add r3, r2 - 8005396: 60bb str r3, [r7, #8] + 8005f0c: 68ba ldr r2, [r7, #8] + 8005f0e: 68fb ldr r3, [r7, #12] + 8005f10: 1ad3 subs r3, r2, r3 + 8005f12: 4a1f ldr r2, [pc, #124] ; (8005f90 ) + 8005f14: 4413 add r3, r2 + 8005f16: 60bb str r3, [r7, #8] } pucAlignedHeap = ( uint8_t * ) uxAddress; - 8005398: 68fb ldr r3, [r7, #12] - 800539a: 607b str r3, [r7, #4] + 8005f18: 68fb ldr r3, [r7, #12] + 8005f1a: 607b str r3, [r7, #4] /* xStart is used to hold a pointer to the first item in the list of free blocks. The void cast is used to prevent compiler warnings. */ xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap; - 800539c: 4a1d ldr r2, [pc, #116] ; (8005414 ) - 800539e: 687b ldr r3, [r7, #4] - 80053a0: 6013 str r3, [r2, #0] + 8005f1c: 4a1d ldr r2, [pc, #116] ; (8005f94 ) + 8005f1e: 687b ldr r3, [r7, #4] + 8005f20: 6013 str r3, [r2, #0] xStart.xBlockSize = ( size_t ) 0; - 80053a2: 4b1c ldr r3, [pc, #112] ; (8005414 ) - 80053a4: 2200 movs r2, #0 - 80053a6: 605a str r2, [r3, #4] + 8005f22: 4b1c ldr r3, [pc, #112] ; (8005f94 ) + 8005f24: 2200 movs r2, #0 + 8005f26: 605a str r2, [r3, #4] /* pxEnd is used to mark the end of the list of free blocks and is inserted at the end of the heap space. */ uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize; - 80053a8: 687b ldr r3, [r7, #4] - 80053aa: 68ba ldr r2, [r7, #8] - 80053ac: 4413 add r3, r2 - 80053ae: 60fb str r3, [r7, #12] + 8005f28: 687b ldr r3, [r7, #4] + 8005f2a: 68ba ldr r2, [r7, #8] + 8005f2c: 4413 add r3, r2 + 8005f2e: 60fb str r3, [r7, #12] uxAddress -= xHeapStructSize; - 80053b0: 2208 movs r2, #8 - 80053b2: 68fb ldr r3, [r7, #12] - 80053b4: 1a9b subs r3, r3, r2 - 80053b6: 60fb str r3, [r7, #12] + 8005f30: 2208 movs r2, #8 + 8005f32: 68fb ldr r3, [r7, #12] + 8005f34: 1a9b subs r3, r3, r2 + 8005f36: 60fb str r3, [r7, #12] uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK ); - 80053b8: 68fb ldr r3, [r7, #12] - 80053ba: f023 0307 bic.w r3, r3, #7 - 80053be: 60fb str r3, [r7, #12] + 8005f38: 68fb ldr r3, [r7, #12] + 8005f3a: f023 0307 bic.w r3, r3, #7 + 8005f3e: 60fb str r3, [r7, #12] pxEnd = ( void * ) uxAddress; - 80053c0: 68fb ldr r3, [r7, #12] - 80053c2: 4a15 ldr r2, [pc, #84] ; (8005418 ) - 80053c4: 6013 str r3, [r2, #0] + 8005f40: 68fb ldr r3, [r7, #12] + 8005f42: 4a15 ldr r2, [pc, #84] ; (8005f98 ) + 8005f44: 6013 str r3, [r2, #0] pxEnd->xBlockSize = 0; - 80053c6: 4b14 ldr r3, [pc, #80] ; (8005418 ) - 80053c8: 681b ldr r3, [r3, #0] - 80053ca: 2200 movs r2, #0 - 80053cc: 605a str r2, [r3, #4] + 8005f46: 4b14 ldr r3, [pc, #80] ; (8005f98 ) + 8005f48: 681b ldr r3, [r3, #0] + 8005f4a: 2200 movs r2, #0 + 8005f4c: 605a str r2, [r3, #4] pxEnd->pxNextFreeBlock = NULL; - 80053ce: 4b12 ldr r3, [pc, #72] ; (8005418 ) - 80053d0: 681b ldr r3, [r3, #0] - 80053d2: 2200 movs r2, #0 - 80053d4: 601a str r2, [r3, #0] + 8005f4e: 4b12 ldr r3, [pc, #72] ; (8005f98 ) + 8005f50: 681b ldr r3, [r3, #0] + 8005f52: 2200 movs r2, #0 + 8005f54: 601a str r2, [r3, #0] /* To start with there is a single free block that is sized to take up the entire heap space, minus the space taken by pxEnd. */ pxFirstFreeBlock = ( void * ) pucAlignedHeap; - 80053d6: 687b ldr r3, [r7, #4] - 80053d8: 603b str r3, [r7, #0] + 8005f56: 687b ldr r3, [r7, #4] + 8005f58: 603b str r3, [r7, #0] pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock; - 80053da: 683b ldr r3, [r7, #0] - 80053dc: 68fa ldr r2, [r7, #12] - 80053de: 1ad2 subs r2, r2, r3 - 80053e0: 683b ldr r3, [r7, #0] - 80053e2: 605a str r2, [r3, #4] + 8005f5a: 683b ldr r3, [r7, #0] + 8005f5c: 68fa ldr r2, [r7, #12] + 8005f5e: 1ad2 subs r2, r2, r3 + 8005f60: 683b ldr r3, [r7, #0] + 8005f62: 605a str r2, [r3, #4] pxFirstFreeBlock->pxNextFreeBlock = pxEnd; - 80053e4: 4b0c ldr r3, [pc, #48] ; (8005418 ) - 80053e6: 681a ldr r2, [r3, #0] - 80053e8: 683b ldr r3, [r7, #0] - 80053ea: 601a str r2, [r3, #0] + 8005f64: 4b0c ldr r3, [pc, #48] ; (8005f98 ) + 8005f66: 681a ldr r2, [r3, #0] + 8005f68: 683b ldr r3, [r7, #0] + 8005f6a: 601a str r2, [r3, #0] /* Only one block exists - and it covers the entire usable heap space. */ xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - 80053ec: 683b ldr r3, [r7, #0] - 80053ee: 685b ldr r3, [r3, #4] - 80053f0: 4a0a ldr r2, [pc, #40] ; (800541c ) - 80053f2: 6013 str r3, [r2, #0] + 8005f6c: 683b ldr r3, [r7, #0] + 8005f6e: 685b ldr r3, [r3, #4] + 8005f70: 4a0a ldr r2, [pc, #40] ; (8005f9c ) + 8005f72: 6013 str r3, [r2, #0] xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize; - 80053f4: 683b ldr r3, [r7, #0] - 80053f6: 685b ldr r3, [r3, #4] - 80053f8: 4a09 ldr r2, [pc, #36] ; (8005420 ) - 80053fa: 6013 str r3, [r2, #0] + 8005f74: 683b ldr r3, [r7, #0] + 8005f76: 685b ldr r3, [r3, #4] + 8005f78: 4a09 ldr r2, [pc, #36] ; (8005fa0 ) + 8005f7a: 6013 str r3, [r2, #0] /* Work out the position of the top bit in a size_t variable. */ xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 ); - 80053fc: 4b09 ldr r3, [pc, #36] ; (8005424 ) - 80053fe: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 - 8005402: 601a str r2, [r3, #0] + 8005f7c: 4b09 ldr r3, [pc, #36] ; (8005fa4 ) + 8005f7e: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 + 8005f82: 601a str r2, [r3, #0] } - 8005404: bf00 nop - 8005406: 3714 adds r7, #20 - 8005408: 46bd mov sp, r7 - 800540a: f85d 7b04 ldr.w r7, [sp], #4 - 800540e: 4770 bx lr - 8005410: 20000ef4 .word 0x20000ef4 - 8005414: 20004af4 .word 0x20004af4 - 8005418: 20004afc .word 0x20004afc - 800541c: 20004b04 .word 0x20004b04 - 8005420: 20004b00 .word 0x20004b00 - 8005424: 20004b10 .word 0x20004b10 + 8005f84: bf00 nop + 8005f86: 3714 adds r7, #20 + 8005f88: 46bd mov sp, r7 + 8005f8a: f85d 7b04 ldr.w r7, [sp], #4 + 8005f8e: 4770 bx lr + 8005f90: 20000f44 .word 0x20000f44 + 8005f94: 20004b44 .word 0x20004b44 + 8005f98: 20004b4c .word 0x20004b4c + 8005f9c: 20004b54 .word 0x20004b54 + 8005fa0: 20004b50 .word 0x20004b50 + 8005fa4: 20004b60 .word 0x20004b60 -08005428 : +08005fa8 : /*-----------------------------------------------------------*/ static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert ) { - 8005428: b480 push {r7} - 800542a: b085 sub sp, #20 - 800542c: af00 add r7, sp, #0 - 800542e: 6078 str r0, [r7, #4] + 8005fa8: b480 push {r7} + 8005faa: b085 sub sp, #20 + 8005fac: af00 add r7, sp, #0 + 8005fae: 6078 str r0, [r7, #4] BlockLink_t *pxIterator; uint8_t *puc; /* Iterate through the list until a block is found that has a higher address than the block being inserted. */ for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock ) - 8005430: 4b28 ldr r3, [pc, #160] ; (80054d4 ) - 8005432: 60fb str r3, [r7, #12] - 8005434: e002 b.n 800543c - 8005436: 68fb ldr r3, [r7, #12] - 8005438: 681b ldr r3, [r3, #0] - 800543a: 60fb str r3, [r7, #12] - 800543c: 68fb ldr r3, [r7, #12] - 800543e: 681b ldr r3, [r3, #0] - 8005440: 687a ldr r2, [r7, #4] - 8005442: 429a cmp r2, r3 - 8005444: d8f7 bhi.n 8005436 + 8005fb0: 4b28 ldr r3, [pc, #160] ; (8006054 ) + 8005fb2: 60fb str r3, [r7, #12] + 8005fb4: e002 b.n 8005fbc + 8005fb6: 68fb ldr r3, [r7, #12] + 8005fb8: 681b ldr r3, [r3, #0] + 8005fba: 60fb str r3, [r7, #12] + 8005fbc: 68fb ldr r3, [r7, #12] + 8005fbe: 681b ldr r3, [r3, #0] + 8005fc0: 687a ldr r2, [r7, #4] + 8005fc2: 429a cmp r2, r3 + 8005fc4: d8f7 bhi.n 8005fb6 /* Nothing to do here, just iterate to the right position. */ } /* Do the block being inserted, and the block it is being inserted after make a contiguous block of memory? */ puc = ( uint8_t * ) pxIterator; - 8005446: 68fb ldr r3, [r7, #12] - 8005448: 60bb str r3, [r7, #8] + 8005fc6: 68fb ldr r3, [r7, #12] + 8005fc8: 60bb str r3, [r7, #8] if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert ) - 800544a: 68fb ldr r3, [r7, #12] - 800544c: 685b ldr r3, [r3, #4] - 800544e: 68ba ldr r2, [r7, #8] - 8005450: 4413 add r3, r2 - 8005452: 687a ldr r2, [r7, #4] - 8005454: 429a cmp r2, r3 - 8005456: d108 bne.n 800546a + 8005fca: 68fb ldr r3, [r7, #12] + 8005fcc: 685b ldr r3, [r3, #4] + 8005fce: 68ba ldr r2, [r7, #8] + 8005fd0: 4413 add r3, r2 + 8005fd2: 687a ldr r2, [r7, #4] + 8005fd4: 429a cmp r2, r3 + 8005fd6: d108 bne.n 8005fea { pxIterator->xBlockSize += pxBlockToInsert->xBlockSize; - 8005458: 68fb ldr r3, [r7, #12] - 800545a: 685a ldr r2, [r3, #4] - 800545c: 687b ldr r3, [r7, #4] - 800545e: 685b ldr r3, [r3, #4] - 8005460: 441a add r2, r3 - 8005462: 68fb ldr r3, [r7, #12] - 8005464: 605a str r2, [r3, #4] + 8005fd8: 68fb ldr r3, [r7, #12] + 8005fda: 685a ldr r2, [r3, #4] + 8005fdc: 687b ldr r3, [r7, #4] + 8005fde: 685b ldr r3, [r3, #4] + 8005fe0: 441a add r2, r3 + 8005fe2: 68fb ldr r3, [r7, #12] + 8005fe4: 605a str r2, [r3, #4] pxBlockToInsert = pxIterator; - 8005466: 68fb ldr r3, [r7, #12] - 8005468: 607b str r3, [r7, #4] + 8005fe6: 68fb ldr r3, [r7, #12] + 8005fe8: 607b str r3, [r7, #4] mtCOVERAGE_TEST_MARKER(); } /* Do the block being inserted, and the block it is being inserted before make a contiguous block of memory? */ puc = ( uint8_t * ) pxBlockToInsert; - 800546a: 687b ldr r3, [r7, #4] - 800546c: 60bb str r3, [r7, #8] + 8005fea: 687b ldr r3, [r7, #4] + 8005fec: 60bb str r3, [r7, #8] if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock ) - 800546e: 687b ldr r3, [r7, #4] - 8005470: 685b ldr r3, [r3, #4] - 8005472: 68ba ldr r2, [r7, #8] - 8005474: 441a add r2, r3 - 8005476: 68fb ldr r3, [r7, #12] - 8005478: 681b ldr r3, [r3, #0] - 800547a: 429a cmp r2, r3 - 800547c: d118 bne.n 80054b0 + 8005fee: 687b ldr r3, [r7, #4] + 8005ff0: 685b ldr r3, [r3, #4] + 8005ff2: 68ba ldr r2, [r7, #8] + 8005ff4: 441a add r2, r3 + 8005ff6: 68fb ldr r3, [r7, #12] + 8005ff8: 681b ldr r3, [r3, #0] + 8005ffa: 429a cmp r2, r3 + 8005ffc: d118 bne.n 8006030 { if( pxIterator->pxNextFreeBlock != pxEnd ) - 800547e: 68fb ldr r3, [r7, #12] - 8005480: 681a ldr r2, [r3, #0] - 8005482: 4b15 ldr r3, [pc, #84] ; (80054d8 ) - 8005484: 681b ldr r3, [r3, #0] - 8005486: 429a cmp r2, r3 - 8005488: d00d beq.n 80054a6 + 8005ffe: 68fb ldr r3, [r7, #12] + 8006000: 681a ldr r2, [r3, #0] + 8006002: 4b15 ldr r3, [pc, #84] ; (8006058 ) + 8006004: 681b ldr r3, [r3, #0] + 8006006: 429a cmp r2, r3 + 8006008: d00d beq.n 8006026 { /* Form one big block from the two blocks. */ pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize; - 800548a: 687b ldr r3, [r7, #4] - 800548c: 685a ldr r2, [r3, #4] - 800548e: 68fb ldr r3, [r7, #12] - 8005490: 681b ldr r3, [r3, #0] - 8005492: 685b ldr r3, [r3, #4] - 8005494: 441a add r2, r3 - 8005496: 687b ldr r3, [r7, #4] - 8005498: 605a str r2, [r3, #4] + 800600a: 687b ldr r3, [r7, #4] + 800600c: 685a ldr r2, [r3, #4] + 800600e: 68fb ldr r3, [r7, #12] + 8006010: 681b ldr r3, [r3, #0] + 8006012: 685b ldr r3, [r3, #4] + 8006014: 441a add r2, r3 + 8006016: 687b ldr r3, [r7, #4] + 8006018: 605a str r2, [r3, #4] pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock; - 800549a: 68fb ldr r3, [r7, #12] - 800549c: 681b ldr r3, [r3, #0] - 800549e: 681a ldr r2, [r3, #0] - 80054a0: 687b ldr r3, [r7, #4] - 80054a2: 601a str r2, [r3, #0] - 80054a4: e008 b.n 80054b8 + 800601a: 68fb ldr r3, [r7, #12] + 800601c: 681b ldr r3, [r3, #0] + 800601e: 681a ldr r2, [r3, #0] + 8006020: 687b ldr r3, [r7, #4] + 8006022: 601a str r2, [r3, #0] + 8006024: e008 b.n 8006038 } else { pxBlockToInsert->pxNextFreeBlock = pxEnd; - 80054a6: 4b0c ldr r3, [pc, #48] ; (80054d8 ) - 80054a8: 681a ldr r2, [r3, #0] - 80054aa: 687b ldr r3, [r7, #4] - 80054ac: 601a str r2, [r3, #0] - 80054ae: e003 b.n 80054b8 + 8006026: 4b0c ldr r3, [pc, #48] ; (8006058 ) + 8006028: 681a ldr r2, [r3, #0] + 800602a: 687b ldr r3, [r7, #4] + 800602c: 601a str r2, [r3, #0] + 800602e: e003 b.n 8006038 } } else { pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock; - 80054b0: 68fb ldr r3, [r7, #12] - 80054b2: 681a ldr r2, [r3, #0] - 80054b4: 687b ldr r3, [r7, #4] - 80054b6: 601a str r2, [r3, #0] + 8006030: 68fb ldr r3, [r7, #12] + 8006032: 681a ldr r2, [r3, #0] + 8006034: 687b ldr r3, [r7, #4] + 8006036: 601a str r2, [r3, #0] /* If the block being inserted plugged a gab, so was merged with the block before and the block after, then it's pxNextFreeBlock pointer will have already been set, and should not be set here as that would make it point to itself. */ if( pxIterator != pxBlockToInsert ) - 80054b8: 68fa ldr r2, [r7, #12] - 80054ba: 687b ldr r3, [r7, #4] - 80054bc: 429a cmp r2, r3 - 80054be: d002 beq.n 80054c6 + 8006038: 68fa ldr r2, [r7, #12] + 800603a: 687b ldr r3, [r7, #4] + 800603c: 429a cmp r2, r3 + 800603e: d002 beq.n 8006046 { pxIterator->pxNextFreeBlock = pxBlockToInsert; - 80054c0: 68fb ldr r3, [r7, #12] - 80054c2: 687a ldr r2, [r7, #4] - 80054c4: 601a str r2, [r3, #0] + 8006040: 68fb ldr r3, [r7, #12] + 8006042: 687a ldr r2, [r7, #4] + 8006044: 601a str r2, [r3, #0] } else { mtCOVERAGE_TEST_MARKER(); } } - 80054c6: bf00 nop - 80054c8: 3714 adds r7, #20 - 80054ca: 46bd mov sp, r7 - 80054cc: f85d 7b04 ldr.w r7, [sp], #4 - 80054d0: 4770 bx lr - 80054d2: bf00 nop - 80054d4: 20004af4 .word 0x20004af4 - 80054d8: 20004afc .word 0x20004afc + 8006046: bf00 nop + 8006048: 3714 adds r7, #20 + 800604a: 46bd mov sp, r7 + 800604c: f85d 7b04 ldr.w r7, [sp], #4 + 8006050: 4770 bx lr + 8006052: bf00 nop + 8006054: 20004b44 .word 0x20004b44 + 8006058: 20004b4c .word 0x20004b4c -080054dc : - 80054dc: 4402 add r2, r0 - 80054de: 4603 mov r3, r0 - 80054e0: 4293 cmp r3, r2 - 80054e2: d100 bne.n 80054e6 - 80054e4: 4770 bx lr - 80054e6: f803 1b01 strb.w r1, [r3], #1 - 80054ea: e7f9 b.n 80054e0 +0800605c : + 800605c: 4402 add r2, r0 + 800605e: 4603 mov r3, r0 + 8006060: 4293 cmp r3, r2 + 8006062: d100 bne.n 8006066 + 8006064: 4770 bx lr + 8006066: f803 1b01 strb.w r1, [r3], #1 + 800606a: e7f9 b.n 8006060 -080054ec <_reclaim_reent>: - 80054ec: 4b29 ldr r3, [pc, #164] ; (8005594 <_reclaim_reent+0xa8>) - 80054ee: 681b ldr r3, [r3, #0] - 80054f0: 4283 cmp r3, r0 - 80054f2: b570 push {r4, r5, r6, lr} - 80054f4: 4604 mov r4, r0 - 80054f6: d04b beq.n 8005590 <_reclaim_reent+0xa4> - 80054f8: 69c3 ldr r3, [r0, #28] - 80054fa: b143 cbz r3, 800550e <_reclaim_reent+0x22> - 80054fc: 68db ldr r3, [r3, #12] - 80054fe: 2b00 cmp r3, #0 - 8005500: d144 bne.n 800558c <_reclaim_reent+0xa0> - 8005502: 69e3 ldr r3, [r4, #28] - 8005504: 6819 ldr r1, [r3, #0] - 8005506: b111 cbz r1, 800550e <_reclaim_reent+0x22> - 8005508: 4620 mov r0, r4 - 800550a: f000 f879 bl 8005600 <_free_r> - 800550e: 6961 ldr r1, [r4, #20] - 8005510: b111 cbz r1, 8005518 <_reclaim_reent+0x2c> - 8005512: 4620 mov r0, r4 - 8005514: f000 f874 bl 8005600 <_free_r> - 8005518: 69e1 ldr r1, [r4, #28] - 800551a: b111 cbz r1, 8005522 <_reclaim_reent+0x36> - 800551c: 4620 mov r0, r4 - 800551e: f000 f86f bl 8005600 <_free_r> - 8005522: 6b21 ldr r1, [r4, #48] ; 0x30 - 8005524: b111 cbz r1, 800552c <_reclaim_reent+0x40> - 8005526: 4620 mov r0, r4 - 8005528: f000 f86a bl 8005600 <_free_r> - 800552c: 6b61 ldr r1, [r4, #52] ; 0x34 - 800552e: b111 cbz r1, 8005536 <_reclaim_reent+0x4a> - 8005530: 4620 mov r0, r4 - 8005532: f000 f865 bl 8005600 <_free_r> - 8005536: 6ba1 ldr r1, [r4, #56] ; 0x38 - 8005538: b111 cbz r1, 8005540 <_reclaim_reent+0x54> - 800553a: 4620 mov r0, r4 - 800553c: f000 f860 bl 8005600 <_free_r> - 8005540: 6ca1 ldr r1, [r4, #72] ; 0x48 - 8005542: b111 cbz r1, 800554a <_reclaim_reent+0x5e> - 8005544: 4620 mov r0, r4 - 8005546: f000 f85b bl 8005600 <_free_r> - 800554a: 6c61 ldr r1, [r4, #68] ; 0x44 - 800554c: b111 cbz r1, 8005554 <_reclaim_reent+0x68> - 800554e: 4620 mov r0, r4 - 8005550: f000 f856 bl 8005600 <_free_r> - 8005554: 6ae1 ldr r1, [r4, #44] ; 0x2c - 8005556: b111 cbz r1, 800555e <_reclaim_reent+0x72> - 8005558: 4620 mov r0, r4 - 800555a: f000 f851 bl 8005600 <_free_r> - 800555e: 6a23 ldr r3, [r4, #32] - 8005560: b1b3 cbz r3, 8005590 <_reclaim_reent+0xa4> - 8005562: 4620 mov r0, r4 - 8005564: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} - 8005568: 4718 bx r3 - 800556a: 5949 ldr r1, [r1, r5] - 800556c: b941 cbnz r1, 8005580 <_reclaim_reent+0x94> - 800556e: 3504 adds r5, #4 - 8005570: 69e3 ldr r3, [r4, #28] - 8005572: 2d80 cmp r5, #128 ; 0x80 - 8005574: 68d9 ldr r1, [r3, #12] - 8005576: d1f8 bne.n 800556a <_reclaim_reent+0x7e> - 8005578: 4620 mov r0, r4 - 800557a: f000 f841 bl 8005600 <_free_r> - 800557e: e7c0 b.n 8005502 <_reclaim_reent+0x16> - 8005580: 680e ldr r6, [r1, #0] - 8005582: 4620 mov r0, r4 - 8005584: f000 f83c bl 8005600 <_free_r> - 8005588: 4631 mov r1, r6 - 800558a: e7ef b.n 800556c <_reclaim_reent+0x80> - 800558c: 2500 movs r5, #0 - 800558e: e7ef b.n 8005570 <_reclaim_reent+0x84> - 8005590: bd70 pop {r4, r5, r6, pc} - 8005592: bf00 nop - 8005594: 2000005c .word 0x2000005c +0800606c <_reclaim_reent>: + 800606c: 4b29 ldr r3, [pc, #164] ; (8006114 <_reclaim_reent+0xa8>) + 800606e: 681b ldr r3, [r3, #0] + 8006070: 4283 cmp r3, r0 + 8006072: b570 push {r4, r5, r6, lr} + 8006074: 4604 mov r4, r0 + 8006076: d04b beq.n 8006110 <_reclaim_reent+0xa4> + 8006078: 69c3 ldr r3, [r0, #28] + 800607a: b143 cbz r3, 800608e <_reclaim_reent+0x22> + 800607c: 68db ldr r3, [r3, #12] + 800607e: 2b00 cmp r3, #0 + 8006080: d144 bne.n 800610c <_reclaim_reent+0xa0> + 8006082: 69e3 ldr r3, [r4, #28] + 8006084: 6819 ldr r1, [r3, #0] + 8006086: b111 cbz r1, 800608e <_reclaim_reent+0x22> + 8006088: 4620 mov r0, r4 + 800608a: f000 f879 bl 8006180 <_free_r> + 800608e: 6961 ldr r1, [r4, #20] + 8006090: b111 cbz r1, 8006098 <_reclaim_reent+0x2c> + 8006092: 4620 mov r0, r4 + 8006094: f000 f874 bl 8006180 <_free_r> + 8006098: 69e1 ldr r1, [r4, #28] + 800609a: b111 cbz r1, 80060a2 <_reclaim_reent+0x36> + 800609c: 4620 mov r0, r4 + 800609e: f000 f86f bl 8006180 <_free_r> + 80060a2: 6b21 ldr r1, [r4, #48] ; 0x30 + 80060a4: b111 cbz r1, 80060ac <_reclaim_reent+0x40> + 80060a6: 4620 mov r0, r4 + 80060a8: f000 f86a bl 8006180 <_free_r> + 80060ac: 6b61 ldr r1, [r4, #52] ; 0x34 + 80060ae: b111 cbz r1, 80060b6 <_reclaim_reent+0x4a> + 80060b0: 4620 mov r0, r4 + 80060b2: f000 f865 bl 8006180 <_free_r> + 80060b6: 6ba1 ldr r1, [r4, #56] ; 0x38 + 80060b8: b111 cbz r1, 80060c0 <_reclaim_reent+0x54> + 80060ba: 4620 mov r0, r4 + 80060bc: f000 f860 bl 8006180 <_free_r> + 80060c0: 6ca1 ldr r1, [r4, #72] ; 0x48 + 80060c2: b111 cbz r1, 80060ca <_reclaim_reent+0x5e> + 80060c4: 4620 mov r0, r4 + 80060c6: f000 f85b bl 8006180 <_free_r> + 80060ca: 6c61 ldr r1, [r4, #68] ; 0x44 + 80060cc: b111 cbz r1, 80060d4 <_reclaim_reent+0x68> + 80060ce: 4620 mov r0, r4 + 80060d0: f000 f856 bl 8006180 <_free_r> + 80060d4: 6ae1 ldr r1, [r4, #44] ; 0x2c + 80060d6: b111 cbz r1, 80060de <_reclaim_reent+0x72> + 80060d8: 4620 mov r0, r4 + 80060da: f000 f851 bl 8006180 <_free_r> + 80060de: 6a23 ldr r3, [r4, #32] + 80060e0: b1b3 cbz r3, 8006110 <_reclaim_reent+0xa4> + 80060e2: 4620 mov r0, r4 + 80060e4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + 80060e8: 4718 bx r3 + 80060ea: 5949 ldr r1, [r1, r5] + 80060ec: b941 cbnz r1, 8006100 <_reclaim_reent+0x94> + 80060ee: 3504 adds r5, #4 + 80060f0: 69e3 ldr r3, [r4, #28] + 80060f2: 2d80 cmp r5, #128 ; 0x80 + 80060f4: 68d9 ldr r1, [r3, #12] + 80060f6: d1f8 bne.n 80060ea <_reclaim_reent+0x7e> + 80060f8: 4620 mov r0, r4 + 80060fa: f000 f841 bl 8006180 <_free_r> + 80060fe: e7c0 b.n 8006082 <_reclaim_reent+0x16> + 8006100: 680e ldr r6, [r1, #0] + 8006102: 4620 mov r0, r4 + 8006104: f000 f83c bl 8006180 <_free_r> + 8006108: 4631 mov r1, r6 + 800610a: e7ef b.n 80060ec <_reclaim_reent+0x80> + 800610c: 2500 movs r5, #0 + 800610e: e7ef b.n 80060f0 <_reclaim_reent+0x84> + 8006110: bd70 pop {r4, r5, r6, pc} + 8006112: bf00 nop + 8006114: 2000005c .word 0x2000005c -08005598 <__libc_init_array>: - 8005598: b570 push {r4, r5, r6, lr} - 800559a: 4d0d ldr r5, [pc, #52] ; (80055d0 <__libc_init_array+0x38>) - 800559c: 4c0d ldr r4, [pc, #52] ; (80055d4 <__libc_init_array+0x3c>) - 800559e: 1b64 subs r4, r4, r5 - 80055a0: 10a4 asrs r4, r4, #2 - 80055a2: 2600 movs r6, #0 - 80055a4: 42a6 cmp r6, r4 - 80055a6: d109 bne.n 80055bc <__libc_init_array+0x24> - 80055a8: 4d0b ldr r5, [pc, #44] ; (80055d8 <__libc_init_array+0x40>) - 80055aa: 4c0c ldr r4, [pc, #48] ; (80055dc <__libc_init_array+0x44>) - 80055ac: f000 f880 bl 80056b0 <_init> - 80055b0: 1b64 subs r4, r4, r5 - 80055b2: 10a4 asrs r4, r4, #2 - 80055b4: 2600 movs r6, #0 - 80055b6: 42a6 cmp r6, r4 - 80055b8: d105 bne.n 80055c6 <__libc_init_array+0x2e> - 80055ba: bd70 pop {r4, r5, r6, pc} - 80055bc: f855 3b04 ldr.w r3, [r5], #4 - 80055c0: 4798 blx r3 - 80055c2: 3601 adds r6, #1 - 80055c4: e7ee b.n 80055a4 <__libc_init_array+0xc> - 80055c6: f855 3b04 ldr.w r3, [r5], #4 - 80055ca: 4798 blx r3 - 80055cc: 3601 adds r6, #1 - 80055ce: e7f2 b.n 80055b6 <__libc_init_array+0x1e> - 80055d0: 08005760 .word 0x08005760 - 80055d4: 08005760 .word 0x08005760 - 80055d8: 08005760 .word 0x08005760 - 80055dc: 08005764 .word 0x08005764 +08006118 <__libc_init_array>: + 8006118: b570 push {r4, r5, r6, lr} + 800611a: 4d0d ldr r5, [pc, #52] ; (8006150 <__libc_init_array+0x38>) + 800611c: 4c0d ldr r4, [pc, #52] ; (8006154 <__libc_init_array+0x3c>) + 800611e: 1b64 subs r4, r4, r5 + 8006120: 10a4 asrs r4, r4, #2 + 8006122: 2600 movs r6, #0 + 8006124: 42a6 cmp r6, r4 + 8006126: d109 bne.n 800613c <__libc_init_array+0x24> + 8006128: 4d0b ldr r5, [pc, #44] ; (8006158 <__libc_init_array+0x40>) + 800612a: 4c0c ldr r4, [pc, #48] ; (800615c <__libc_init_array+0x44>) + 800612c: f000 f880 bl 8006230 <_init> + 8006130: 1b64 subs r4, r4, r5 + 8006132: 10a4 asrs r4, r4, #2 + 8006134: 2600 movs r6, #0 + 8006136: 42a6 cmp r6, r4 + 8006138: d105 bne.n 8006146 <__libc_init_array+0x2e> + 800613a: bd70 pop {r4, r5, r6, pc} + 800613c: f855 3b04 ldr.w r3, [r5], #4 + 8006140: 4798 blx r3 + 8006142: 3601 adds r6, #1 + 8006144: e7ee b.n 8006124 <__libc_init_array+0xc> + 8006146: f855 3b04 ldr.w r3, [r5], #4 + 800614a: 4798 blx r3 + 800614c: 3601 adds r6, #1 + 800614e: e7f2 b.n 8006136 <__libc_init_array+0x1e> + 8006150: 08006344 .word 0x08006344 + 8006154: 08006344 .word 0x08006344 + 8006158: 08006344 .word 0x08006344 + 800615c: 08006348 .word 0x08006348 -080055e0 <__retarget_lock_acquire_recursive>: - 80055e0: 4770 bx lr +08006160 <__retarget_lock_acquire_recursive>: + 8006160: 4770 bx lr -080055e2 <__retarget_lock_release_recursive>: - 80055e2: 4770 bx lr +08006162 <__retarget_lock_release_recursive>: + 8006162: 4770 bx lr -080055e4 : - 80055e4: 440a add r2, r1 - 80055e6: 4291 cmp r1, r2 - 80055e8: f100 33ff add.w r3, r0, #4294967295 - 80055ec: d100 bne.n 80055f0 - 80055ee: 4770 bx lr - 80055f0: b510 push {r4, lr} - 80055f2: f811 4b01 ldrb.w r4, [r1], #1 - 80055f6: f803 4f01 strb.w r4, [r3, #1]! - 80055fa: 4291 cmp r1, r2 - 80055fc: d1f9 bne.n 80055f2 - 80055fe: bd10 pop {r4, pc} +08006164 : + 8006164: 440a add r2, r1 + 8006166: 4291 cmp r1, r2 + 8006168: f100 33ff add.w r3, r0, #4294967295 + 800616c: d100 bne.n 8006170 + 800616e: 4770 bx lr + 8006170: b510 push {r4, lr} + 8006172: f811 4b01 ldrb.w r4, [r1], #1 + 8006176: f803 4f01 strb.w r4, [r3, #1]! + 800617a: 4291 cmp r1, r2 + 800617c: d1f9 bne.n 8006172 + 800617e: bd10 pop {r4, pc} -08005600 <_free_r>: - 8005600: b537 push {r0, r1, r2, r4, r5, lr} - 8005602: 2900 cmp r1, #0 - 8005604: d044 beq.n 8005690 <_free_r+0x90> - 8005606: f851 3c04 ldr.w r3, [r1, #-4] - 800560a: 9001 str r0, [sp, #4] - 800560c: 2b00 cmp r3, #0 - 800560e: f1a1 0404 sub.w r4, r1, #4 - 8005612: bfb8 it lt - 8005614: 18e4 addlt r4, r4, r3 - 8005616: f000 f83f bl 8005698 <__malloc_lock> - 800561a: 4a1e ldr r2, [pc, #120] ; (8005694 <_free_r+0x94>) - 800561c: 9801 ldr r0, [sp, #4] - 800561e: 6813 ldr r3, [r2, #0] - 8005620: b933 cbnz r3, 8005630 <_free_r+0x30> - 8005622: 6063 str r3, [r4, #4] - 8005624: 6014 str r4, [r2, #0] - 8005626: b003 add sp, #12 - 8005628: e8bd 4030 ldmia.w sp!, {r4, r5, lr} - 800562c: f000 b83a b.w 80056a4 <__malloc_unlock> - 8005630: 42a3 cmp r3, r4 - 8005632: d908 bls.n 8005646 <_free_r+0x46> - 8005634: 6825 ldr r5, [r4, #0] - 8005636: 1961 adds r1, r4, r5 - 8005638: 428b cmp r3, r1 - 800563a: bf01 itttt eq - 800563c: 6819 ldreq r1, [r3, #0] - 800563e: 685b ldreq r3, [r3, #4] - 8005640: 1949 addeq r1, r1, r5 - 8005642: 6021 streq r1, [r4, #0] - 8005644: e7ed b.n 8005622 <_free_r+0x22> - 8005646: 461a mov r2, r3 - 8005648: 685b ldr r3, [r3, #4] - 800564a: b10b cbz r3, 8005650 <_free_r+0x50> - 800564c: 42a3 cmp r3, r4 - 800564e: d9fa bls.n 8005646 <_free_r+0x46> - 8005650: 6811 ldr r1, [r2, #0] - 8005652: 1855 adds r5, r2, r1 - 8005654: 42a5 cmp r5, r4 - 8005656: d10b bne.n 8005670 <_free_r+0x70> - 8005658: 6824 ldr r4, [r4, #0] - 800565a: 4421 add r1, r4 - 800565c: 1854 adds r4, r2, r1 - 800565e: 42a3 cmp r3, r4 - 8005660: 6011 str r1, [r2, #0] - 8005662: d1e0 bne.n 8005626 <_free_r+0x26> - 8005664: 681c ldr r4, [r3, #0] - 8005666: 685b ldr r3, [r3, #4] - 8005668: 6053 str r3, [r2, #4] - 800566a: 440c add r4, r1 - 800566c: 6014 str r4, [r2, #0] - 800566e: e7da b.n 8005626 <_free_r+0x26> - 8005670: d902 bls.n 8005678 <_free_r+0x78> - 8005672: 230c movs r3, #12 - 8005674: 6003 str r3, [r0, #0] - 8005676: e7d6 b.n 8005626 <_free_r+0x26> - 8005678: 6825 ldr r5, [r4, #0] - 800567a: 1961 adds r1, r4, r5 - 800567c: 428b cmp r3, r1 - 800567e: bf04 itt eq - 8005680: 6819 ldreq r1, [r3, #0] - 8005682: 685b ldreq r3, [r3, #4] - 8005684: 6063 str r3, [r4, #4] - 8005686: bf04 itt eq - 8005688: 1949 addeq r1, r1, r5 - 800568a: 6021 streq r1, [r4, #0] - 800568c: 6054 str r4, [r2, #4] - 800568e: e7ca b.n 8005626 <_free_r+0x26> - 8005690: b003 add sp, #12 - 8005692: bd30 pop {r4, r5, pc} - 8005694: 20004c50 .word 0x20004c50 +08006180 <_free_r>: + 8006180: b537 push {r0, r1, r2, r4, r5, lr} + 8006182: 2900 cmp r1, #0 + 8006184: d044 beq.n 8006210 <_free_r+0x90> + 8006186: f851 3c04 ldr.w r3, [r1, #-4] + 800618a: 9001 str r0, [sp, #4] + 800618c: 2b00 cmp r3, #0 + 800618e: f1a1 0404 sub.w r4, r1, #4 + 8006192: bfb8 it lt + 8006194: 18e4 addlt r4, r4, r3 + 8006196: f000 f83f bl 8006218 <__malloc_lock> + 800619a: 4a1e ldr r2, [pc, #120] ; (8006214 <_free_r+0x94>) + 800619c: 9801 ldr r0, [sp, #4] + 800619e: 6813 ldr r3, [r2, #0] + 80061a0: b933 cbnz r3, 80061b0 <_free_r+0x30> + 80061a2: 6063 str r3, [r4, #4] + 80061a4: 6014 str r4, [r2, #0] + 80061a6: b003 add sp, #12 + 80061a8: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + 80061ac: f000 b83a b.w 8006224 <__malloc_unlock> + 80061b0: 42a3 cmp r3, r4 + 80061b2: d908 bls.n 80061c6 <_free_r+0x46> + 80061b4: 6825 ldr r5, [r4, #0] + 80061b6: 1961 adds r1, r4, r5 + 80061b8: 428b cmp r3, r1 + 80061ba: bf01 itttt eq + 80061bc: 6819 ldreq r1, [r3, #0] + 80061be: 685b ldreq r3, [r3, #4] + 80061c0: 1949 addeq r1, r1, r5 + 80061c2: 6021 streq r1, [r4, #0] + 80061c4: e7ed b.n 80061a2 <_free_r+0x22> + 80061c6: 461a mov r2, r3 + 80061c8: 685b ldr r3, [r3, #4] + 80061ca: b10b cbz r3, 80061d0 <_free_r+0x50> + 80061cc: 42a3 cmp r3, r4 + 80061ce: d9fa bls.n 80061c6 <_free_r+0x46> + 80061d0: 6811 ldr r1, [r2, #0] + 80061d2: 1855 adds r5, r2, r1 + 80061d4: 42a5 cmp r5, r4 + 80061d6: d10b bne.n 80061f0 <_free_r+0x70> + 80061d8: 6824 ldr r4, [r4, #0] + 80061da: 4421 add r1, r4 + 80061dc: 1854 adds r4, r2, r1 + 80061de: 42a3 cmp r3, r4 + 80061e0: 6011 str r1, [r2, #0] + 80061e2: d1e0 bne.n 80061a6 <_free_r+0x26> + 80061e4: 681c ldr r4, [r3, #0] + 80061e6: 685b ldr r3, [r3, #4] + 80061e8: 6053 str r3, [r2, #4] + 80061ea: 440c add r4, r1 + 80061ec: 6014 str r4, [r2, #0] + 80061ee: e7da b.n 80061a6 <_free_r+0x26> + 80061f0: d902 bls.n 80061f8 <_free_r+0x78> + 80061f2: 230c movs r3, #12 + 80061f4: 6003 str r3, [r0, #0] + 80061f6: e7d6 b.n 80061a6 <_free_r+0x26> + 80061f8: 6825 ldr r5, [r4, #0] + 80061fa: 1961 adds r1, r4, r5 + 80061fc: 428b cmp r3, r1 + 80061fe: bf04 itt eq + 8006200: 6819 ldreq r1, [r3, #0] + 8006202: 685b ldreq r3, [r3, #4] + 8006204: 6063 str r3, [r4, #4] + 8006206: bf04 itt eq + 8006208: 1949 addeq r1, r1, r5 + 800620a: 6021 streq r1, [r4, #0] + 800620c: 6054 str r4, [r2, #4] + 800620e: e7ca b.n 80061a6 <_free_r+0x26> + 8006210: b003 add sp, #12 + 8006212: bd30 pop {r4, r5, pc} + 8006214: 20004ca0 .word 0x20004ca0 -08005698 <__malloc_lock>: - 8005698: 4801 ldr r0, [pc, #4] ; (80056a0 <__malloc_lock+0x8>) - 800569a: f7ff bfa1 b.w 80055e0 <__retarget_lock_acquire_recursive> - 800569e: bf00 nop - 80056a0: 20004c4c .word 0x20004c4c +08006218 <__malloc_lock>: + 8006218: 4801 ldr r0, [pc, #4] ; (8006220 <__malloc_lock+0x8>) + 800621a: f7ff bfa1 b.w 8006160 <__retarget_lock_acquire_recursive> + 800621e: bf00 nop + 8006220: 20004c9c .word 0x20004c9c -080056a4 <__malloc_unlock>: - 80056a4: 4801 ldr r0, [pc, #4] ; (80056ac <__malloc_unlock+0x8>) - 80056a6: f7ff bf9c b.w 80055e2 <__retarget_lock_release_recursive> - 80056aa: bf00 nop - 80056ac: 20004c4c .word 0x20004c4c +08006224 <__malloc_unlock>: + 8006224: 4801 ldr r0, [pc, #4] ; (800622c <__malloc_unlock+0x8>) + 8006226: f7ff bf9c b.w 8006162 <__retarget_lock_release_recursive> + 800622a: bf00 nop + 800622c: 20004c9c .word 0x20004c9c -080056b0 <_init>: - 80056b0: b5f8 push {r3, r4, r5, r6, r7, lr} - 80056b2: bf00 nop - 80056b4: bcf8 pop {r3, r4, r5, r6, r7} - 80056b6: bc08 pop {r3} - 80056b8: 469e mov lr, r3 - 80056ba: 4770 bx lr +08006230 <_init>: + 8006230: b5f8 push {r3, r4, r5, r6, r7, lr} + 8006232: bf00 nop + 8006234: bcf8 pop {r3, r4, r5, r6, r7} + 8006236: bc08 pop {r3} + 8006238: 469e mov lr, r3 + 800623a: 4770 bx lr -080056bc <_fini>: - 80056bc: b5f8 push {r3, r4, r5, r6, r7, lr} - 80056be: bf00 nop - 80056c0: bcf8 pop {r3, r4, r5, r6, r7} - 80056c2: bc08 pop {r3} - 80056c4: 469e mov lr, r3 - 80056c6: 4770 bx lr +0800623c <_fini>: + 800623c: b5f8 push {r3, r4, r5, r6, r7, lr} + 800623e: bf00 nop + 8006240: bcf8 pop {r3, r4, r5, r6, r7} + 8006242: bc08 pop {r3} + 8006244: 469e mov lr, r3 + 8006246: 4770 bx lr diff --git a/access_control_stm32/Debug/access_control_stm32.map b/access_control_stm32/Debug/access_control_stm32.map index 691ad26..e7d59a0 100644 --- a/access_control_stm32/Debug/access_control_stm32.map +++ b/access_control_stm32/Debug/access_control_stm32.map @@ -131,6 +131,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Core/Src/freertos.o .group 0x0000000000000000 0xc ./Core/Src/freertos.o .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o + .group 0x0000000000000000 0xc ./Core/Src/freertos.o .text 0x0000000000000000 0x0 ./Core/Src/freertos.o .data 0x0000000000000000 0x0 ./Core/Src/freertos.o .bss 0x0000000000000000 0x0 ./Core/Src/freertos.o @@ -138,7 +142,7 @@ Discarded input sections .debug_abbrev 0x0000000000000000 0x28 ./Core/Src/freertos.o .debug_aranges 0x0000000000000000 0x18 ./Core/Src/freertos.o - .debug_macro 0x0000000000000000 0x2e2 ./Core/Src/freertos.o + .debug_macro 0x0000000000000000 0x30a ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x174 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x22 ./Core/Src/freertos.o @@ -169,7 +173,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x4bf ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0xb5 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0xaa ./Core/Src/freertos.o - .debug_macro 0x0000000000000000 0x29b ./Core/Src/freertos.o + .debug_macro 0x0000000000000000 0x2a1 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x28 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x1c ./Core/Src/freertos.o @@ -190,6 +194,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x5f ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x236 ./Core/Src/freertos.o + .debug_macro 0x0000000000000000 0x9e1 ./Core/Src/freertos.o + .debug_macro 0x0000000000000000 0x38b ./Core/Src/freertos.o + .debug_macro 0x0000000000000000 0x17d ./Core/Src/freertos.o + .debug_macro 0x0000000000000000 0xf9 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x132 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x264 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/freertos.o @@ -201,8 +209,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x295 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x126 ./Core/Src/freertos.o .debug_macro 0x0000000000000000 0x70 ./Core/Src/freertos.o - .debug_line 0x0000000000000000 0x957 ./Core/Src/freertos.o - .debug_str 0x0000000000000000 0x8c3f8 ./Core/Src/freertos.o + .debug_line 0x0000000000000000 0x99e ./Core/Src/freertos.o + .debug_str 0x0000000000000000 0x97c4a ./Core/Src/freertos.o .comment 0x0000000000000000 0x44 ./Core/Src/freertos.o .ARM.attributes 0x0000000000000000 0x34 ./Core/Src/freertos.o @@ -280,11 +288,17 @@ Discarded input sections .group 0x0000000000000000 0xc ./Core/Src/main.o .group 0x0000000000000000 0xc ./Core/Src/main.o .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o + .group 0x0000000000000000 0xc ./Core/Src/main.o .text 0x0000000000000000 0x0 ./Core/Src/main.o .data 0x0000000000000000 0x0 ./Core/Src/main.o .bss 0x0000000000000000 0x0 ./Core/Src/main.o + .data.flag_uart_cmd + 0x0000000000000000 0x4 ./Core/Src/main.o .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/main.o - .debug_macro 0x0000000000000000 0x29b ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x2a1 ./Core/Src/main.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/main.o .debug_macro 0x0000000000000000 0x28 ./Core/Src/main.o .debug_macro 0x0000000000000000 0x22 ./Core/Src/main.o @@ -312,6 +326,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Core/Src/main.o .debug_macro 0x0000000000000000 0x5f ./Core/Src/main.o .debug_macro 0x0000000000000000 0x236 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x9e1 ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x38b ./Core/Src/main.o + .debug_macro 0x0000000000000000 0x17d ./Core/Src/main.o + .debug_macro 0x0000000000000000 0xf9 ./Core/Src/main.o .debug_macro 0x0000000000000000 0x132 ./Core/Src/main.o .debug_macro 0x0000000000000000 0x264 ./Core/Src/main.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/main.o @@ -384,13 +402,19 @@ Discarded input sections .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_msp.o .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_msp.o .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_msp.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_msp.o .text 0x0000000000000000 0x0 ./Core/Src/stm32f4xx_hal_msp.o .data 0x0000000000000000 0x0 ./Core/Src/stm32f4xx_hal_msp.o .bss 0x0000000000000000 0x0 ./Core/Src/stm32f4xx_hal_msp.o + .text.HAL_ADC_MspDeInit + 0x0000000000000000 0x40 ./Core/Src/stm32f4xx_hal_msp.o .text.HAL_UART_MspDeInit 0x0000000000000000 0x3c ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/stm32f4xx_hal_msp.o - .debug_macro 0x0000000000000000 0x29b ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x2a1 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x0000000000000000 0x22 ./Core/Src/stm32f4xx_hal_msp.o @@ -418,6 +442,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x0000000000000000 0x5f ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x0000000000000000 0x236 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x9e1 ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x38b ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0x17d ./Core/Src/stm32f4xx_hal_msp.o + .debug_macro 0x0000000000000000 0xf9 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x0000000000000000 0x132 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x0000000000000000 0x264 ./Core/Src/stm32f4xx_hal_msp.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32f4xx_hal_msp.o @@ -468,6 +496,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_hal_timebase_tim.o .text 0x0000000000000000 0x0 ./Core/Src/stm32f4xx_hal_timebase_tim.o .data 0x0000000000000000 0x0 ./Core/Src/stm32f4xx_hal_timebase_tim.o .bss 0x0000000000000000 0x0 ./Core/Src/stm32f4xx_hal_timebase_tim.o @@ -476,7 +508,7 @@ Discarded input sections .text.HAL_ResumeTick 0x0000000000000000 0x24 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/stm32f4xx_hal_timebase_tim.o - .debug_macro 0x0000000000000000 0x29b ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x2a1 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x0000000000000000 0x22 ./Core/Src/stm32f4xx_hal_timebase_tim.o @@ -504,6 +536,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x0000000000000000 0x5f ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x0000000000000000 0x236 ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x9e1 ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x38b ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0x17d ./Core/Src/stm32f4xx_hal_timebase_tim.o + .debug_macro 0x0000000000000000 0xf9 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x0000000000000000 0x132 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x0000000000000000 0x264 ./Core/Src/stm32f4xx_hal_timebase_tim.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32f4xx_hal_timebase_tim.o @@ -554,11 +590,15 @@ Discarded input sections .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_it.o .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_it.o .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_it.o + .group 0x0000000000000000 0xc ./Core/Src/stm32f4xx_it.o .text 0x0000000000000000 0x0 ./Core/Src/stm32f4xx_it.o .data 0x0000000000000000 0x0 ./Core/Src/stm32f4xx_it.o .bss 0x0000000000000000 0x0 ./Core/Src/stm32f4xx_it.o .debug_macro 0x0000000000000000 0xaa8 ./Core/Src/stm32f4xx_it.o - .debug_macro 0x0000000000000000 0x29b ./Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x2a1 ./Core/Src/stm32f4xx_it.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32f4xx_it.o .debug_macro 0x0000000000000000 0x28 ./Core/Src/stm32f4xx_it.o .debug_macro 0x0000000000000000 0x22 ./Core/Src/stm32f4xx_it.o @@ -586,6 +626,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Core/Src/stm32f4xx_it.o .debug_macro 0x0000000000000000 0x5f ./Core/Src/stm32f4xx_it.o .debug_macro 0x0000000000000000 0x236 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x9e1 ./Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x38b ./Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0x17d ./Core/Src/stm32f4xx_it.o + .debug_macro 0x0000000000000000 0xf9 ./Core/Src/stm32f4xx_it.o .debug_macro 0x0000000000000000 0x132 ./Core/Src/stm32f4xx_it.o .debug_macro 0x0000000000000000 0x264 ./Core/Src/stm32f4xx_it.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/stm32f4xx_it.o @@ -834,6 +878,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Core/Src/system_stm32f4xx.o .group 0x0000000000000000 0xc ./Core/Src/system_stm32f4xx.o .group 0x0000000000000000 0xc ./Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32f4xx.o + .group 0x0000000000000000 0xc ./Core/Src/system_stm32f4xx.o .text 0x0000000000000000 0x0 ./Core/Src/system_stm32f4xx.o .data 0x0000000000000000 0x0 ./Core/Src/system_stm32f4xx.o .bss 0x0000000000000000 0x0 ./Core/Src/system_stm32f4xx.o @@ -855,7 +903,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x11f ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0xb953 ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0x6d ./Core/Src/system_stm32f4xx.o - .debug_macro 0x0000000000000000 0x29b ./Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x2a1 ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0x367e ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0x174 ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0x5c ./Core/Src/system_stm32f4xx.o @@ -868,6 +916,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0x5f ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0x236 ./Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x9e1 ./Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x38b ./Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0x17d ./Core/Src/system_stm32f4xx.o + .debug_macro 0x0000000000000000 0xf9 ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0x132 ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0x264 ./Core/Src/system_stm32f4xx.o .debug_macro 0x0000000000000000 0x2e ./Core/Src/system_stm32f4xx.o @@ -920,6 +972,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o @@ -972,7 +1028,7 @@ Discarded input sections .text.HAL_GetUIDw2 0x0000000000000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o @@ -1000,6 +1056,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o @@ -1010,6 +1070,252 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o + .group 0x0000000000000000 0xc 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./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x11a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x85 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x89 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x8e6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o @@ -1101,7 +1407,7 @@ Discarded input sections .text.HAL_SYSTICK_Callback 0x0000000000000000 0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o @@ -1129,6 +1435,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o @@ -1178,6 +1488,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o @@ -1219,9 +1533,9 @@ Discarded input sections 0x0000000000000000 0x90 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_rnglists 0x0000000000000000 0x70 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_macro 0x0000000000000000 0x1d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x1fc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o @@ -1249,6 +1563,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o @@ -1259,8 +1577,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_line 0x0000000000000000 0xf92 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o - .debug_str 0x0000000000000000 0x86f23 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_line 0x0000000000000000 0xfd9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o + .debug_str 0x0000000000000000 0x92775 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .debug_frame 0x0000000000000000 0x250 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o .ARM.attributes @@ -1304,6 +1622,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o @@ -1321,9 +1643,9 @@ Discarded input sections 0x0000000000000000 0x38 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_rnglists 0x0000000000000000 0x27 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o - .debug_macro 0x0000000000000000 0x1ce ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x1f6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o @@ -1351,6 +1673,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o @@ -1361,8 +1687,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o - .debug_line 0x0000000000000000 0x13c1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o - .debug_str 0x0000000000000000 0x86cdd ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_line 0x0000000000000000 0x1408 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o + .debug_str 0x0000000000000000 0x9252f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .debug_frame 0x0000000000000000 0xac ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o .ARM.attributes @@ -1406,6 +1732,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o @@ -1433,9 +1763,9 @@ Discarded input sections 0x0000000000000000 0x60 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_rnglists 0x0000000000000000 0x46 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o - .debug_macro 0x0000000000000000 0x1ce ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x1f6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o @@ -1463,6 +1793,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o @@ -1473,8 +1807,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o - .debug_line 0x0000000000000000 0xa1d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o - .debug_str 0x0000000000000000 0x86b75 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_line 0x0000000000000000 0xa64 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o + .debug_str 0x0000000000000000 0x923c7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .debug_frame 0x0000000000000000 0x174 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_exti.o .ARM.attributes @@ -1518,6 +1852,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o @@ -1562,9 +1900,9 @@ Discarded input sections 0x0000000000000000 0xa0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_rnglists 0x0000000000000000 0x78 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o - .debug_macro 0x0000000000000000 0x1d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x1fc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o @@ -1592,6 +1930,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o @@ -1602,8 +1944,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o - .debug_line 0x0000000000000000 0xacd ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o - .debug_str 0x0000000000000000 0x86cf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_line 0x0000000000000000 0xb14 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o + .debug_str 0x0000000000000000 0x9254b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .debug_frame 0x0000000000000000 0x274 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash.o .ARM.attributes @@ -1647,6 +1989,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o @@ -1700,9 +2046,9 @@ Discarded input sections 0x0000000000000000 0xc8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_rnglists 0x0000000000000000 0x96 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x1d4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x1fc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o @@ -1730,6 +2076,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o @@ -1740,8 +2090,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o - .debug_line 0x0000000000000000 0xbd2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o - .debug_str 0x0000000000000000 0x86e1c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_line 0x0000000000000000 0xc19 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o + .debug_str 0x0000000000000000 0x9266e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .debug_frame 0x0000000000000000 0x334 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ex.o .ARM.attributes @@ -1785,6 +2135,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o @@ -1795,9 +2149,9 @@ Discarded input sections 0x0000000000000000 0x38 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_rnglists 0x0000000000000000 0x25 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x1ce ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x1f6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o @@ -1825,6 +2179,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o @@ -1835,8 +2193,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o - .debug_line 0x0000000000000000 0x789 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o - .debug_str 0x0000000000000000 0x86b43 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_line 0x0000000000000000 0x7d0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o + .debug_str 0x0000000000000000 0x92395 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .debug_frame 0x0000000000000000 0xb0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_flash_ramfunc.o .ARM.attributes @@ -1880,6 +2238,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o @@ -1894,7 +2256,7 @@ Discarded input sections .text.HAL_GPIO_EXTI_Callback 0x0000000000000000 0x16 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o @@ -1922,6 +2284,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o @@ -1971,6 +2337,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o @@ -2014,9 +2384,9 @@ Discarded input sections 0x0000000000000000 0xa0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_rnglists 0x0000000000000000 0x74 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x1e6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x20e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o @@ -2044,6 +2414,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o @@ -2054,8 +2428,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o - .debug_line 0x0000000000000000 0x93a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o - .debug_str 0x0000000000000000 0x86d51 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_line 0x0000000000000000 0x981 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o + .debug_str 0x0000000000000000 0x925a3 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .debug_frame 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.o .ARM.attributes @@ -2099,6 +2473,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o @@ -2128,9 +2506,9 @@ Discarded input sections 0x0000000000000000 0x68 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_rnglists 0x0000000000000000 0x4a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x1e6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x20e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o @@ -2158,6 +2536,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o @@ -2168,8 +2550,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o - .debug_line 0x0000000000000000 0x8e8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o - .debug_str 0x0000000000000000 0x86ccc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_line 0x0000000000000000 0x92f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o + .debug_str 0x0000000000000000 0x9251e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .debug_frame 0x0000000000000000 0x15c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr_ex.o .ARM.attributes @@ -2213,6 +2595,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o @@ -2231,7 +2617,7 @@ Discarded input sections .text.HAL_RCC_CSSCallback 0x0000000000000000 0xe ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o @@ -2259,6 +2645,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o @@ -2308,6 +2698,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o @@ -2331,9 +2725,9 @@ Discarded input sections 0x0000000000000000 0x50 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_rnglists 0x0000000000000000 0x3c ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x1ce ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x1f6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o @@ -2361,6 +2755,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o @@ -2371,8 +2769,8 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o - .debug_line 0x0000000000000000 0xa88 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o - .debug_str 0x0000000000000000 0x86ca3 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_line 0x0000000000000000 0xacf ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o + .debug_str 0x0000000000000000 0x924f5 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .debug_frame 0x0000000000000000 0x118 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o .ARM.attributes @@ -2416,6 +2814,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o @@ -2640,7 +3042,7 @@ Discarded input sections .text.TIM_CCxChannelCmd 0x0000000000000000 0x4a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o @@ -2668,6 +3070,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o @@ -2717,6 +3123,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o @@ -2801,7 +3211,7 @@ Discarded input sections .text.TIM_CCxNChannelCmd 0x0000000000000000 0x4a ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o @@ -2829,6 +3239,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o @@ -2878,6 +3292,10 @@ Discarded input sections .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o @@ -2994,7 +3412,7 @@ Discarded input sections .text.UART_Receive_IT 0x0000000000000000 0x176 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o - .debug_macro 0x0000000000000000 0x29b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x2a1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x28 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o @@ -3022,6 +3440,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x5f ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x236 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x9e1 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x38b ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0x17d ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .debug_macro 0x0000000000000000 0xf9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x132 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x264 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x2e ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o @@ -3032,6 +3454,25 @@ Discarded input sections .debug_macro 0x0000000000000000 0x47 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x295 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .debug_macro 0x0000000000000000 0x126 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + .group 0x0000000000000000 0xc ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .text 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .data 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .bss 0x0000000000000000 0x0 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .debug_info 0x0000000000000000 0x22 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .debug_abbrev 0x0000000000000000 0x12 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .debug_aranges + 0x0000000000000000 0x18 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .debug_macro 0x0000000000000000 0x11 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .debug_macro 0x0000000000000000 0xaa8 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .debug_line 0x0000000000000000 0x57 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .debug_str 0x0000000000000000 0x2dda ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .comment 0x0000000000000000 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .ARM.attributes + 0x0000000000000000 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .group 0x0000000000000000 0xc ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o @@ -3164,7 +3605,6 @@ Discarded input sections 0x0000000000000000 0x42 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osThreadFlagsWait 0x0000000000000000 0x102 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .text.osDelay 0x0000000000000000 0x36 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.osDelayUntil 0x0000000000000000 0x5a ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .text.TimerCallback @@ -3295,7 +3735,7 @@ Discarded input sections .debug_macro 0x0000000000000000 0x11f ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0xb953 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0x6d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o - .debug_macro 0x0000000000000000 0x29b ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x2a1 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0x367e ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0x447 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0x9fe ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o @@ -3306,6 +3746,10 @@ Discarded input sections .debug_macro 0x0000000000000000 0x287 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0x5f ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0x236 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x9e1 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x38b ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0x17d ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + .debug_macro 0x0000000000000000 0xf9 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0x132 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0x264 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .debug_macro 0x0000000000000000 0x2e ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o @@ -4475,6 +4919,8 @@ LOAD ./Core/Src/sysmem.o LOAD ./Core/Src/system_stm32f4xx.o LOAD ./Core/Startup/startup_stm32f411retx.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o @@ -4490,6 +4936,7 @@ LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc_ex.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o +LOAD ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o LOAD ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o LOAD ./Middlewares/Third_Party/FreeRTOS/Source/croutine.o LOAD ./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o @@ -4531,7 +4978,7 @@ LOAD C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x0000000008000000 g_pfnVectors 0x0000000008000198 . = ALIGN (0x4) -.text 0x00000000080001a0 0x5528 +.text 0x00000000080001a0 0x60a8 0x00000000080001a0 . = ALIGN (0x4) *(.text) .text 0x00000000080001a0 0x40 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtbegin.o @@ -4543,556 +4990,610 @@ LOAD C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext 0x00000000080004d8 __aeabi_idiv0 0x00000000080004d8 __aeabi_ldiv0 *(.text*) - .text.main 0x00000000080004dc 0x64 ./Core/Src/main.o - 0x00000000080004dc main + .text.HAL_ADC_ConvCpltCallback + 0x00000000080004dc 0x40 ./Core/Src/main.o + 0x00000000080004dc HAL_ADC_ConvCpltCallback + .text.main 0x000000000800051c 0xa0 ./Core/Src/main.o + 0x000000000800051c main .text.SystemClock_Config - 0x0000000008000540 0xd4 ./Core/Src/main.o - 0x0000000008000540 SystemClock_Config + 0x00000000080005bc 0xd4 ./Core/Src/main.o + 0x00000000080005bc SystemClock_Config + .text.MX_ADC1_Init + 0x0000000008000690 0xa4 ./Core/Src/main.o .text.MX_USART2_UART_Init - 0x0000000008000614 0x54 ./Core/Src/main.o + 0x0000000008000734 0x54 ./Core/Src/main.o .text.MX_GPIO_Init - 0x0000000008000668 0xf8 ./Core/Src/main.o + 0x0000000008000788 0xf8 ./Core/Src/main.o .text.StartMainTask - 0x0000000008000760 0xf4 ./Core/Src/main.o - 0x0000000008000760 StartMainTask + 0x0000000008000880 0x120 ./Core/Src/main.o + 0x0000000008000880 StartMainTask .text.startDoorHandleTask - 0x0000000008000854 0x17c ./Core/Src/main.o - 0x0000000008000854 startDoorHandleTask + 0x00000000080009a0 0x17c ./Core/Src/main.o + 0x00000000080009a0 startDoorHandleTask + .text.StartStateSendTask + 0x0000000008000b1c 0x58 ./Core/Src/main.o + 0x0000000008000b1c StartStateSendTask + .text.StartADCReqTask + 0x0000000008000b74 0x1c ./Core/Src/main.o + 0x0000000008000b74 StartADCReqTask .text.HAL_TIM_PeriodElapsedCallback - 0x00000000080009d0 0x24 ./Core/Src/main.o - 0x00000000080009d0 HAL_TIM_PeriodElapsedCallback + 0x0000000008000b90 0x24 ./Core/Src/main.o + 0x0000000008000b90 HAL_TIM_PeriodElapsedCallback .text.Error_Handler - 0x00000000080009f4 0xa ./Core/Src/main.o - 0x00000000080009f4 Error_Handler - *fill* 0x00000000080009fe 0x2 + 0x0000000008000bb4 0xa ./Core/Src/main.o + 0x0000000008000bb4 Error_Handler + *fill* 0x0000000008000bbe 0x2 .text.HAL_MspInit - 0x0000000008000a00 0x58 ./Core/Src/stm32f4xx_hal_msp.o - 0x0000000008000a00 HAL_MspInit + 0x0000000008000bc0 0x58 ./Core/Src/stm32f4xx_hal_msp.o + 0x0000000008000bc0 HAL_MspInit + .text.HAL_ADC_MspInit + 0x0000000008000c18 0x98 ./Core/Src/stm32f4xx_hal_msp.o + 0x0000000008000c18 HAL_ADC_MspInit .text.HAL_UART_MspInit - 0x0000000008000a58 0x90 ./Core/Src/stm32f4xx_hal_msp.o - 0x0000000008000a58 HAL_UART_MspInit + 0x0000000008000cb0 0x90 ./Core/Src/stm32f4xx_hal_msp.o + 0x0000000008000cb0 HAL_UART_MspInit .text.HAL_InitTick - 0x0000000008000ae8 0xe4 ./Core/Src/stm32f4xx_hal_timebase_tim.o - 0x0000000008000ae8 HAL_InitTick + 0x0000000008000d40 0xe4 ./Core/Src/stm32f4xx_hal_timebase_tim.o + 0x0000000008000d40 HAL_InitTick .text.NMI_Handler - 0x0000000008000bcc 0x6 ./Core/Src/stm32f4xx_it.o - 0x0000000008000bcc NMI_Handler + 0x0000000008000e24 0x6 ./Core/Src/stm32f4xx_it.o + 0x0000000008000e24 NMI_Handler .text.HardFault_Handler - 0x0000000008000bd2 0x6 ./Core/Src/stm32f4xx_it.o - 0x0000000008000bd2 HardFault_Handler + 0x0000000008000e2a 0x6 ./Core/Src/stm32f4xx_it.o + 0x0000000008000e2a HardFault_Handler .text.MemManage_Handler - 0x0000000008000bd8 0x6 ./Core/Src/stm32f4xx_it.o - 0x0000000008000bd8 MemManage_Handler + 0x0000000008000e30 0x6 ./Core/Src/stm32f4xx_it.o + 0x0000000008000e30 MemManage_Handler .text.BusFault_Handler - 0x0000000008000bde 0x6 ./Core/Src/stm32f4xx_it.o - 0x0000000008000bde BusFault_Handler + 0x0000000008000e36 0x6 ./Core/Src/stm32f4xx_it.o + 0x0000000008000e36 BusFault_Handler .text.UsageFault_Handler - 0x0000000008000be4 0x6 ./Core/Src/stm32f4xx_it.o - 0x0000000008000be4 UsageFault_Handler + 0x0000000008000e3c 0x6 ./Core/Src/stm32f4xx_it.o + 0x0000000008000e3c UsageFault_Handler .text.DebugMon_Handler - 0x0000000008000bea 0xe ./Core/Src/stm32f4xx_it.o - 0x0000000008000bea DebugMon_Handler + 0x0000000008000e42 0xe ./Core/Src/stm32f4xx_it.o + 0x0000000008000e42 DebugMon_Handler + .text.ADC_IRQHandler + 0x0000000008000e50 0x14 ./Core/Src/stm32f4xx_it.o + 0x0000000008000e50 ADC_IRQHandler .text.TIM1_UP_TIM10_IRQHandler - 0x0000000008000bf8 0x14 ./Core/Src/stm32f4xx_it.o - 0x0000000008000bf8 TIM1_UP_TIM10_IRQHandler + 0x0000000008000e64 0x14 ./Core/Src/stm32f4xx_it.o + 0x0000000008000e64 TIM1_UP_TIM10_IRQHandler .text.SystemInit - 0x0000000008000c0c 0x24 ./Core/Src/system_stm32f4xx.o - 0x0000000008000c0c SystemInit + 0x0000000008000e78 0x24 ./Core/Src/system_stm32f4xx.o + 0x0000000008000e78 SystemInit .text.Reset_Handler - 0x0000000008000c30 0x50 ./Core/Startup/startup_stm32f411retx.o - 0x0000000008000c30 Reset_Handler + 0x0000000008000e9c 0x50 ./Core/Startup/startup_stm32f411retx.o + 0x0000000008000e9c Reset_Handler .text.Default_Handler - 0x0000000008000c80 0x2 ./Core/Startup/startup_stm32f411retx.o - 0x0000000008000c80 RTC_Alarm_IRQHandler - 0x0000000008000c80 EXTI2_IRQHandler - 0x0000000008000c80 SPI4_IRQHandler - 0x0000000008000c80 TIM1_CC_IRQHandler - 0x0000000008000c80 DMA2_Stream5_IRQHandler - 0x0000000008000c80 DMA1_Stream5_IRQHandler - 0x0000000008000c80 PVD_IRQHandler - 0x0000000008000c80 SDIO_IRQHandler - 0x0000000008000c80 TAMP_STAMP_IRQHandler - 0x0000000008000c80 EXTI3_IRQHandler - 0x0000000008000c80 I2C3_ER_IRQHandler - 0x0000000008000c80 EXTI0_IRQHandler - 0x0000000008000c80 I2C2_EV_IRQHandler - 0x0000000008000c80 DMA1_Stream2_IRQHandler - 0x0000000008000c80 FPU_IRQHandler - 0x0000000008000c80 DMA2_Stream2_IRQHandler - 0x0000000008000c80 SPI1_IRQHandler - 0x0000000008000c80 TIM1_BRK_TIM9_IRQHandler - 0x0000000008000c80 DMA2_Stream3_IRQHandler - 0x0000000008000c80 USART6_IRQHandler - 0x0000000008000c80 DMA2_Stream0_IRQHandler - 0x0000000008000c80 TIM4_IRQHandler - 0x0000000008000c80 I2C1_EV_IRQHandler - 0x0000000008000c80 DMA1_Stream6_IRQHandler - 0x0000000008000c80 DMA1_Stream1_IRQHandler - 0x0000000008000c80 TIM3_IRQHandler - 0x0000000008000c80 RCC_IRQHandler - 0x0000000008000c80 Default_Handler - 0x0000000008000c80 EXTI15_10_IRQHandler - 0x0000000008000c80 ADC_IRQHandler - 0x0000000008000c80 DMA1_Stream7_IRQHandler - 0x0000000008000c80 SPI5_IRQHandler - 0x0000000008000c80 TIM5_IRQHandler - 0x0000000008000c80 DMA2_Stream7_IRQHandler - 0x0000000008000c80 I2C3_EV_IRQHandler - 0x0000000008000c80 EXTI9_5_IRQHandler - 0x0000000008000c80 RTC_WKUP_IRQHandler - 0x0000000008000c80 SPI2_IRQHandler - 0x0000000008000c80 DMA1_Stream0_IRQHandler - 0x0000000008000c80 EXTI4_IRQHandler - 0x0000000008000c80 WWDG_IRQHandler - 0x0000000008000c80 TIM2_IRQHandler - 0x0000000008000c80 OTG_FS_WKUP_IRQHandler - 0x0000000008000c80 TIM1_TRG_COM_TIM11_IRQHandler - 0x0000000008000c80 EXTI1_IRQHandler - 0x0000000008000c80 USART2_IRQHandler - 0x0000000008000c80 I2C2_ER_IRQHandler - 0x0000000008000c80 DMA2_Stream1_IRQHandler - 0x0000000008000c80 FLASH_IRQHandler - 0x0000000008000c80 DMA2_Stream4_IRQHandler - 0x0000000008000c80 USART1_IRQHandler - 0x0000000008000c80 OTG_FS_IRQHandler - 0x0000000008000c80 SPI3_IRQHandler - 0x0000000008000c80 DMA1_Stream4_IRQHandler - 0x0000000008000c80 I2C1_ER_IRQHandler - 0x0000000008000c80 DMA2_Stream6_IRQHandler - 0x0000000008000c80 DMA1_Stream3_IRQHandler - *fill* 0x0000000008000c82 0x2 + 0x0000000008000eec 0x2 ./Core/Startup/startup_stm32f411retx.o + 0x0000000008000eec RTC_Alarm_IRQHandler + 0x0000000008000eec EXTI2_IRQHandler + 0x0000000008000eec SPI4_IRQHandler + 0x0000000008000eec TIM1_CC_IRQHandler + 0x0000000008000eec DMA2_Stream5_IRQHandler + 0x0000000008000eec DMA1_Stream5_IRQHandler + 0x0000000008000eec PVD_IRQHandler + 0x0000000008000eec SDIO_IRQHandler + 0x0000000008000eec TAMP_STAMP_IRQHandler + 0x0000000008000eec EXTI3_IRQHandler + 0x0000000008000eec I2C3_ER_IRQHandler + 0x0000000008000eec EXTI0_IRQHandler + 0x0000000008000eec I2C2_EV_IRQHandler + 0x0000000008000eec DMA1_Stream2_IRQHandler + 0x0000000008000eec FPU_IRQHandler + 0x0000000008000eec DMA2_Stream2_IRQHandler + 0x0000000008000eec SPI1_IRQHandler + 0x0000000008000eec TIM1_BRK_TIM9_IRQHandler + 0x0000000008000eec DMA2_Stream3_IRQHandler + 0x0000000008000eec USART6_IRQHandler + 0x0000000008000eec DMA2_Stream0_IRQHandler + 0x0000000008000eec TIM4_IRQHandler + 0x0000000008000eec I2C1_EV_IRQHandler + 0x0000000008000eec DMA1_Stream6_IRQHandler + 0x0000000008000eec DMA1_Stream1_IRQHandler + 0x0000000008000eec TIM3_IRQHandler + 0x0000000008000eec RCC_IRQHandler + 0x0000000008000eec Default_Handler + 0x0000000008000eec EXTI15_10_IRQHandler + 0x0000000008000eec DMA1_Stream7_IRQHandler + 0x0000000008000eec SPI5_IRQHandler + 0x0000000008000eec TIM5_IRQHandler + 0x0000000008000eec DMA2_Stream7_IRQHandler + 0x0000000008000eec I2C3_EV_IRQHandler + 0x0000000008000eec EXTI9_5_IRQHandler + 0x0000000008000eec RTC_WKUP_IRQHandler + 0x0000000008000eec SPI2_IRQHandler + 0x0000000008000eec DMA1_Stream0_IRQHandler + 0x0000000008000eec EXTI4_IRQHandler + 0x0000000008000eec WWDG_IRQHandler + 0x0000000008000eec TIM2_IRQHandler + 0x0000000008000eec OTG_FS_WKUP_IRQHandler + 0x0000000008000eec TIM1_TRG_COM_TIM11_IRQHandler + 0x0000000008000eec EXTI1_IRQHandler + 0x0000000008000eec USART2_IRQHandler + 0x0000000008000eec I2C2_ER_IRQHandler + 0x0000000008000eec DMA2_Stream1_IRQHandler + 0x0000000008000eec FLASH_IRQHandler + 0x0000000008000eec DMA2_Stream4_IRQHandler + 0x0000000008000eec USART1_IRQHandler + 0x0000000008000eec OTG_FS_IRQHandler + 0x0000000008000eec SPI3_IRQHandler + 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0x0000000008005758 __exidx_start = . +.ARM 0x000000000800633c 0x8 + 0x000000000800633c . = ALIGN (0x4) + 0x000000000800633c __exidx_start = . *(.ARM.exidx*) - .ARM.exidx 0x0000000008005758 0x8 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o) - 0x0000000008005760 __exidx_end = . - 0x0000000008005760 . = ALIGN (0x4) + .ARM.exidx 0x000000000800633c 0x8 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o) + 0x0000000008006344 __exidx_end = . + 0x0000000008006344 . = ALIGN (0x4) -.rel.dyn 0x0000000008005760 0x0 - .rel.iplt 0x0000000008005760 0x0 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0x0000000020004b44 0x8 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + .bss.pxEnd 0x0000000020004b4c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o .bss.xFreeBytesRemaining - 0x0000000020004b00 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0x0000000020004b50 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o .bss.xMinimumEverFreeBytesRemaining - 0x0000000020004b04 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0x0000000020004b54 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o .bss.xNumberOfSuccessfulAllocations - 0x0000000020004b08 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0x0000000020004b58 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o .bss.xNumberOfSuccessfulFrees - 0x0000000020004b0c 0x4 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0x0000000020004b5c 0x4 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C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o) - 0x0000000020004c4c __lock___malloc_recursive_mutex - *fill* 0x0000000020004c4d 0x3 + 0x0000000020004c9c 0x1 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-lock.o) + 0x0000000020004c9c __lock___malloc_recursive_mutex + *fill* 0x0000000020004c9d 0x3 .bss.__malloc_free_list - 0x0000000020004c50 0x4 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o) - 0x0000000020004c50 __malloc_free_list + 0x0000000020004ca0 0x4 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-mallocr.o) + 0x0000000020004ca0 __malloc_free_list *(COMMON) - 0x0000000020004c54 . = ALIGN (0x4) - 0x0000000020004c54 _ebss = . - 0x0000000020004c54 __bss_end__ = _ebss + 0x0000000020004ca4 . = ALIGN (0x4) + 0x0000000020004ca4 _ebss = . + 0x0000000020004ca4 __bss_end__ = _ebss ._user_heap_stack - 0x0000000020004c54 0x3004 load address 0x00000000080057c8 - 0x0000000020004c58 . = ALIGN (0x8) - *fill* 0x0000000020004c54 0x4 + 0x0000000020004ca4 0x3004 load address 0x00000000080063ac + 0x0000000020004ca8 . = ALIGN (0x8) + *fill* 0x0000000020004ca4 0x4 [!provide] PROVIDE (end = .) - 0x0000000020004c58 PROVIDE (_end = .) - 0x0000000020005c58 . = (. + _Min_Heap_Size) - *fill* 0x0000000020004c58 0x1000 - 0x0000000020007c58 . = (. + _Min_Stack_Size) - *fill* 0x0000000020005c58 0x2000 - 0x0000000020007c58 . = ALIGN (0x8) + 0x0000000020004ca8 PROVIDE (_end = .) + 0x0000000020005ca8 . = (. + _Min_Heap_Size) + *fill* 0x0000000020004ca8 0x1000 + 0x0000000020007ca8 . = (. + _Min_Stack_Size) + *fill* 0x0000000020005ca8 0x2000 + 0x0000000020007ca8 . = ALIGN (0x8) /DISCARD/ libc.a(*) @@ -5313,59 +5826,63 @@ LOAD C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .ARM.attributes 0x0000000000000177 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o .ARM.attributes - 0x00000000000001ab 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o + 0x00000000000001ab 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o .ARM.attributes - 0x00000000000001df 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o + 0x00000000000001df 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o .ARM.attributes - 0x0000000000000213 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o + 0x0000000000000213 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .ARM.attributes - 0x0000000000000247 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o + 0x0000000000000247 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .ARM.attributes - 0x000000000000027b 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o + 0x000000000000027b 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o .ARM.attributes - 0x00000000000002af 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o + 0x00000000000002af 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o .ARM.attributes - 0x00000000000002e3 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o + 0x00000000000002e3 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o .ARM.attributes - 0x0000000000000317 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/list.o + 0x0000000000000317 0x34 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o .ARM.attributes - 0x000000000000034b 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o + 0x000000000000034b 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o .ARM.attributes - 0x000000000000037f 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o + 0x000000000000037f 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/list.o .ARM.attributes - 0x00000000000003b3 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o + 0x00000000000003b3 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/queue.o .ARM.attributes - 0x00000000000003e7 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o + 0x00000000000003e7 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/tasks.o .ARM.attributes - 0x000000000000041b 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o + 0x000000000000041b 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/timers.o .ARM.attributes - 0x000000000000044f 0x34 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) + 0x000000000000044f 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o .ARM.attributes - 0x0000000000000483 0x34 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o) + 0x0000000000000483 0x34 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o .ARM.attributes - 0x00000000000004b7 0x34 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o) + 0x00000000000004b7 0x34 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-findfp.o) .ARM.attributes - 0x00000000000004eb 0x34 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-impure.o) + 0x00000000000004eb 0x34 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-memset.o) .ARM.attributes - 0x000000000000051f 0x34 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-init.o) + 0x000000000000051f 0x34 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc_nano.a(libc_a-reent.o) .ARM.attributes - 0x0000000000000553 0x34 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C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x000000000000072f 0x1e C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard/crtn.o OUTPUT(access_control_stm32.elf elf32-littlearm) LOAD linker stubs LOAD C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m+fp/hard\libc.a @@ -5381,6 +5898,8 @@ LOAD C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .comment 0x0000000000000043 0x44 ./Core/Src/stm32f4xx_it.o .comment 0x0000000000000043 0x44 ./Core/Src/system_stm32f4xx.o .comment 0x0000000000000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o + .comment 0x0000000000000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o + .comment 0x0000000000000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o .comment 0x0000000000000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o .comment 0x0000000000000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o .comment 0x0000000000000043 0x44 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o @@ -5395,276 +5914,298 @@ LOAD C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext .comment 0x0000000000000043 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.o .comment 0x0000000000000043 0x44 ./Middlewares/Third_Party/FreeRTOS/Source/portable/MemMang/heap_4.o -.debug_info 0x0000000000000000 0x175bc - .debug_info 0x0000000000000000 0x1418 ./Core/Src/main.o - .debug_info 0x0000000000001418 0xabb ./Core/Src/stm32f4xx_hal_msp.o - .debug_info 0x0000000000001ed3 0xb75 ./Core/Src/stm32f4xx_hal_timebase_tim.o - .debug_info 0x0000000000002a48 0x6a4 ./Core/Src/stm32f4xx_it.o - .debug_info 0x00000000000030ec 0x53e ./Core/Src/system_stm32f4xx.o - .debug_info 0x000000000000362a 0x23 ./Core/Startup/startup_stm32f411retx.o - .debug_info 0x000000000000364d 0x8c4 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o - .debug_info 0x0000000000003f11 0xcb6 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o - .debug_info 0x0000000000004bc7 0x6f9 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_gpio.o - .debug_info 0x00000000000052c0 0x8f2 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_rcc.o - .debug_info 0x0000000000005bb2 0x2941 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o - .debug_info 0x00000000000084f3 0x14a7 ./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o - .debug_info 0x000000000000999a 0x2fbf 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C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_aeabi_uldivmod.o) + .debug_frame 0x0000000000005ca4 0x34 C:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.0.202305231506/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/thumb/v7e-m+fp/hard\libgcc.a(_udivmoddi4.o) .debug_line_str 0x0000000000000000 0x59 diff --git a/access_control_stm32/Debug/objects.list b/access_control_stm32/Debug/objects.list index 39bb8f1..43a2e0e 100644 --- a/access_control_stm32/Debug/objects.list +++ b/access_control_stm32/Debug/objects.list @@ -8,6 +8,8 @@ "./Core/Src/system_stm32f4xx.o" "./Core/Startup/startup_stm32f411retx.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_cortex.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_dma_ex.o" @@ -23,6 +25,7 @@ "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_tim_ex.o" "./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_uart.o" +"./Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.o" "./Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS_V2/cmsis_os2.o" "./Middlewares/Third_Party/FreeRTOS/Source/croutine.o" "./Middlewares/Third_Party/FreeRTOS/Source/event_groups.o" diff --git a/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h new file mode 100644 index 0000000..ce95f08 --- /dev/null +++ b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc.h @@ -0,0 +1,898 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_adc.h + * @author MCD Application Team + * @brief Header file containing functions prototypes of ADC HAL library. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_ADC_H +#define __STM32F4xx_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/* Include low level driver */ +#include "stm32f4xx_ll_adc.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief Structure definition of ADC and regular group initialization + * @note Parameters of this structure are shared within 2 scopes: + * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. + * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. + * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group. + * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going. + * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed + * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). + */ +typedef struct +{ + uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for + all the ADCs. + This parameter can be a value of @ref ADC_ClockPrescaler */ + uint32_t Resolution; /*!< Configures the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting) + or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3). + This parameter can be a value of @ref ADC_Data_align */ + uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups. + This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. + If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). + Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). + If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank). + Scan direction is upward: from rank1 to rank 'n'. + This parameter can be set to ENABLE or DISABLE */ + uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence. + This parameter can be a value of @ref ADC_EOCSelection. + Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence. + Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT) + or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion. + Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()). + If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */ + FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group, + after the selected trigger occurred (software start or external trigger). + This parameter can be set to ENABLE or DISABLE. */ + uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer. + To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 16. */ + FunctionalState DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. */ + uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided. + If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ + uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group. + If set to ADC_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge by default. + This parameter can be a value of @ref ADC_External_trigger_Source_Regular */ + uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group. + If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. + This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ + FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). + This parameter can be set to ENABLE or DISABLE. */ +}ADC_InitTypeDef; + + + +/** + * @brief Structure definition of ADC channel for regular group + * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. + * ADC can be either disabled or enabled without conversion on going on regular group. + */ +typedef struct +{ + uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_channels */ + uint32_t Rank; /*!< Specifies the rank in the regular group sequencer. + This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ +}ADC_ChannelConfTypeDef; + +/** + * @brief ADC Configuration multi-mode structure definition + */ +typedef struct +{ + uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. + This parameter can be a value of @ref ADC_analog_watchdog_selection */ + uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a 12-bit value. */ + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. + This parameter must be a 12-bit value. */ + uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. + This parameter has an effect only if watchdog mode is configured on single channel + This parameter can be a value of @ref ADC_channels */ + FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured + is interrupt mode or in polling mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ +}ADC_AnalogWDGConfTypeDef; + +/** + * @brief HAL ADC state machine: ADC states definition (bitfields) + */ +/* States of ADC global scope */ +#define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ +#define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ +#define HAL_ADC_STATE_BUSY_INTERNAL 0x00000002U /*!< ADC is busy to internal process (initialization, calibration) */ +#define HAL_ADC_STATE_TIMEOUT 0x00000004U /*!< TimeOut occurrence */ + +/* States of ADC errors */ +#define HAL_ADC_STATE_ERROR_INTERNAL 0x00000010U /*!< Internal error occurrence */ +#define HAL_ADC_STATE_ERROR_CONFIG 0x00000020U /*!< Configuration error occurrence */ +#define HAL_ADC_STATE_ERROR_DMA 0x00000040U /*!< DMA error occurrence */ + +/* States of ADC group regular */ +#define HAL_ADC_STATE_REG_BUSY 0x00000100U /*!< A conversion on group regular is ongoing or can occur (either by continuous mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_REG_EOC 0x00000200U /*!< Conversion data available on group regular */ +#define HAL_ADC_STATE_REG_OVR 0x00000400U /*!< Overrun occurrence */ + +/* States of ADC group injected */ +#define HAL_ADC_STATE_INJ_BUSY 0x00001000U /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode, + external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ +#define HAL_ADC_STATE_INJ_EOC 0x00002000U /*!< Conversion data available on group injected */ + +/* States of ADC analog watchdogs */ +#define HAL_ADC_STATE_AWD1 0x00010000U /*!< Out-of-window occurrence of analog watchdog 1 */ +#define HAL_ADC_STATE_AWD2 0x00020000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 2 */ +#define HAL_ADC_STATE_AWD3 0x00040000U /*!< Not available on STM32F4 device: Out-of-window occurrence of analog watchdog 3 */ + +/* States of ADC multi-mode */ +#define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */ + + +/** + * @brief ADC handle Structure definition + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +typedef struct __ADC_HandleTypeDef +#else +typedef struct +#endif +{ + ADC_TypeDef *Instance; /*!< Register base address */ + + ADC_InitTypeDef Init; /*!< ADC required parameters */ + + __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */ + + DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ + + HAL_LockTypeDef Lock; /*!< ADC locking object */ + + __IO uint32_t State; /*!< ADC communication state */ + + __IO uint32_t ErrorCode; /*!< ADC Error code */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ + void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ + void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ + void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ + void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ + void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ + void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +}ADC_HandleTypeDef; + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ADC Callback ID enumeration definition + */ +typedef enum +{ + HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ + HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ + HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ + HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ + HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ + HAL_ADC_MSPINIT_CB_ID = 0x05U, /*!< ADC Msp Init callback ID */ + HAL_ADC_MSPDEINIT_CB_ID = 0x06U /*!< ADC Msp DeInit callback ID */ +} HAL_ADC_CallbackIDTypeDef; + +/** + * @brief HAL ADC Callback pointer definition + */ +typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_Error_Code ADC Error Code + * @{ + */ +#define HAL_ADC_ERROR_NONE 0x00U /*!< No error */ +#define HAL_ADC_ERROR_INTERNAL 0x01U /*!< ADC IP internal error: if problem of clocking, + enable/disable, erroneous state */ +#define HAL_ADC_ERROR_OVR 0x02U /*!< Overrun error */ +#define HAL_ADC_ERROR_DMA 0x04U /*!< DMA transfer error */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + + +/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler + * @{ + */ +#define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) +#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) +#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) +/** + * @} + */ + +/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases + * @{ + */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U +#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) +#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) +#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) +#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) +#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) +/** + * @} + */ + +/** @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12B 0x00000000U +#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) +#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) +#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular + * @{ + */ +#define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U +#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) +#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) +/** + * @} + */ + +/** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular + * @{ + */ +/* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */ +/* compatibility with other STM32 devices. */ +#define ADC_EXTERNALTRIGCONV_T1_CC1 0x00000000U +#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0) +#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1) +#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T2_CC3 ((uint32_t)ADC_CR2_EXTSEL_2) +#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) +#define ADC_EXTERNALTRIGCONV_T3_CC1 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T3_TRGO ((uint32_t)ADC_CR2_EXTSEL_3) +#define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T5_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1)) +#define ADC_EXTERNALTRIGCONV_T5_CC2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T5_CC3 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2)) +#define ADC_EXTERNALTRIGCONV_T8_CC1 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0)) +#define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1)) +#define ADC_EXTERNALTRIGCONV_Ext_IT11 ((uint32_t)ADC_CR2_EXTSEL) +#define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U) +/** + * @} + */ + +/** @defgroup ADC_Data_align ADC Data Align + * @{ + */ +#define ADC_DATAALIGN_RIGHT 0x00000000U +#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) +/** + * @} + */ + +/** @defgroup ADC_channels ADC Common Channels + * @{ + */ +#define ADC_CHANNEL_0 0x00000000U +#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) +#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2) +#define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) +#define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3) +#define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1)) +#define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2)) +#define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1)) +#define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4) +#define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) +#define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) + +#define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) +#define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) +/** + * @} + */ + +/** @defgroup ADC_sampling_times ADC Sampling Times + * @{ + */ +#define ADC_SAMPLETIME_3CYCLES 0x00000000U +#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) +#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) +#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)) +#define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2) +#define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)) +#define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)) +#define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) +/** + * @} + */ + + /** @defgroup ADC_EOCSelection ADC EOC Selection + * @{ + */ +#define ADC_EOC_SEQ_CONV 0x00000000U +#define ADC_EOC_SINGLE_CONV 0x00000001U +#define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */ +/** + * @} + */ + +/** @defgroup ADC_Event_type ADC Event Type + * @{ + */ +#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) +#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection + * @{ + */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN) +#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN) +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) +#define ADC_ANALOGWATCHDOG_NONE 0x00000000U +/** + * @} + */ + +/** @defgroup ADC_interrupts_definition ADC Interrupts Definition + * @{ + */ +#define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) +#define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) +#define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) +#define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) +/** + * @} + */ + +/** @defgroup ADC_flags_definition ADC Flags Definition + * @{ + */ +#define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) +#define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) +#define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) +#define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT) +#define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT) +#define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) +/** + * @} + */ + +/** @defgroup ADC_channels_type ADC Channels Type + * @{ + */ +#define ADC_ALL_CHANNELS 0x00000001U +#define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */ +#define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @brief Reset ADC handle state + * @param __HANDLE__ ADC handle + * @retval None + */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ + ((__HANDLE__)->State = HAL_ADC_STATE_RESET) +#endif + +/** + * @brief Enable the ADC peripheral. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) + +/** + * @brief Disable the ADC peripheral. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) + +/** + * @brief Enable the ADC end of conversion interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC Interrupt. + * @retval None + */ +#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) + +/** + * @brief Disable the ADC end of conversion interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC interrupt. + * @retval None + */ +#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) + +/** @brief Check if the specified ADC interrupt source is enabled or disabled. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ specifies the ADC interrupt source to check. + * @retval The new state of __IT__ (TRUE or FALSE). + */ +#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clear the ADC's pending flags. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. + * @retval None + */ +#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) + +/** + * @brief Get the selected ADC's flag status. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. + * @retval None + */ +#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) + +/** + * @} + */ + +/* Include ADC HAL Extension module */ +#include "stm32f4xx_hal_adc_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/* Callbacks Register/UnRegister functions ***********************************/ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); + +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); + +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); + +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); + +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); + +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); + +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +/** + * @} + */ + +/** @addtogroup ADC_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions ***************************************************/ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_Private_Constants ADC Private Constants + * @{ + */ +/* Delay for ADC stabilization time. */ +/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */ +/* Unit: us */ +#define ADC_STAB_DELAY_US 3U +/* Delay for temperature sensor stabilization time. */ +/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ +/* Unit: us */ +#define ADC_TEMPSENSOR_DELAY_US 10U +/** + * @} + */ + +/* Private macro ------------------------------------------------------------*/ + +/** @defgroup ADC_Private_Macros ADC Private Macros + * @{ + */ +/* Macro reserved for internal HAL driver usage, not intended to be used in + code of final user */ + +/** + * @brief Verification of ADC state: enabled or disabled + * @param __HANDLE__ ADC handle + * @retval SET (ADC enabled) or RESET (ADC disabled) + */ +#define ADC_IS_ENABLE(__HANDLE__) \ + ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \ + ) ? SET : RESET) + +/** + * @brief Test if conversion trigger of regular group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + +/** + * @brief Test if conversion trigger of injected group is software start + * or external trigger. + * @param __HANDLE__ ADC handle + * @retval SET (software start) or RESET (external trigger) + */ +#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ + (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET) + +/** + * @brief Simultaneously clears and sets specific bits of the handle State + * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), + * the first parameter is the ADC handle State, the second parameter is the + * bit field to clear, the third and last parameter is the bit field to set. + * @retval None + */ +#define ADC_STATE_CLR_SET MODIFY_REG + +/** + * @brief Clear ADC error code (set it to error code: "no error") + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_CLEAR_ERRORCODE(__HANDLE__) \ + ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) + + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV8)) +#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B)) +#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) +#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T1_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC2) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T5_CC3) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_CC1) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \ + ((REGTRIG) == ADC_EXTERNALTRIGCONV_Ext_IT11)|| \ + ((REGTRIG) == ADC_SOFTWARE_START)) +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT)) +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_3CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_15CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_28CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_56CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_84CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_112CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_144CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_480CYCLES)) +#define IS_ADC_EOCSelection(EOCSelection) (((EOCSelection) == ADC_EOC_SINGLE_CONV) || \ + ((EOCSelection) == ADC_EOC_SEQ_CONV) || \ + ((EOCSelection) == ADC_EOC_SINGLE_SEQ_CONV)) +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ + ((EVENT) == ADC_OVR_EVENT)) +#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \ + ((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)) +#define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \ + ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \ + ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS)) +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFFU) + +#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 16U)) +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= (16U))) +#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) +#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ + ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= 0x0FFFU)) || \ + (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= 0x03FFU)) || \ + (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= 0x00FFU)) || \ + (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= 0x003FU))) + +/** + * @brief Set ADC Regular channel sequence length. + * @param _NbrOfConversion_ Regular channel sequence length. + * @retval None + */ +#define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) + +/** + * @brief Set the ADC's sample time for channel numbers between 10 and 18. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. + * @retval None + */ +#define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) + +/** + * @brief Set the ADC's sample time for channel numbers between 0 and 9. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. + * @retval None + */ +#define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) + +/** + * @brief Set the selected regular channel rank for rank between 1 and 6. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @retval None + */ +#define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) + +/** + * @brief Set the selected regular channel rank for rank between 7 and 12. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @retval None + */ +#define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) + +/** + * @brief Set the selected regular channel rank for rank between 13 and 16. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @retval None + */ +#define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) + +/** + * @brief Enable ADC continuous conversion mode. + * @param _CONTINUOUS_MODE_ Continuous mode. + * @retval None + */ +#define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) + +/** + * @brief Configures the number of discontinuous conversions for the regular group channels. + * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. + * @retval None + */ +#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos) + +/** + * @brief Enable ADC scan mode. + * @param _SCANCONV_MODE_ Scan conversion mode. + * @retval None + */ +#define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) + +/** + * @brief Enable the ADC end of conversion selection. + * @param _EOCSelection_MODE_ End of conversion selection mode. + * @retval None + */ +#define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) + +/** + * @brief Enable the ADC DMA continuous request. + * @param _DMAContReq_MODE_ DMA continuous request mode. + * @retval None + */ +#define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) + +/** + * @brief Return resolution bits in CR1 register. + * @param __HANDLE__ ADC handle + * @retval None + */ +#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup ADC_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_ADC_H */ + + diff --git a/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h new file mode 100644 index 0000000..515435f --- /dev/null +++ b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_adc_ex.h @@ -0,0 +1,407 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_adc_ex.h + * @author MCD Application Team + * @brief Header file of ADC HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_ADC_EX_H +#define __STM32F4xx_ADC_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup ADCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Types ADC Exported Types + * @{ + */ + +/** + * @brief ADC Configuration injected Channel structure definition + * @note Parameters of this structure are shared within 2 scopes: + * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset + * - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, + * AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv. + * @note The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters: ADC disabled + * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. + * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. + */ +typedef struct +{ + uint32_t InjectedChannel; /*!< Selection of ADC channel to configure + This parameter can be a value of @ref ADC_channels + Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */ + uint32_t InjectedRank; /*!< Rank in the injected group sequencer + This parameter must be a value of @ref ADCEx_injected_rank + Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */ + uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups. + If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting. + Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), + sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) + Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ + uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only). + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), + this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. + To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 4. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). + Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. + Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one + This parameter can be set to ENABLE or DISABLE. + Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) + Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) + Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. + To maintain JAUTO always enabled, DMA must be configured in circular mode. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled. + If set to external trigger source, triggering is on event rising edge. + This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected + Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly) + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ + uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. + This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. + If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + configure a channel on injected group can impact the configuration of other channels previously set. */ +}ADC_InjectionConfTypeDef; + +/** + * @brief ADC Configuration multi-mode structure definition + */ +typedef struct +{ + uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. + This parameter can be a value of @ref ADCEx_Common_mode */ + uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. + This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ + uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. + This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ +}ADC_MultiModeTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADCEx_Common_mode ADC Common Mode + * @{ + */ +#define ADC_MODE_INDEPENDENT 0x00000000U +#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) +#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) +#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) +#define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) +#define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) +#define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1)) +#define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1)) +#define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)) +#define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) +/** + * @} + */ + +/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode + * @{ + */ +#define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */ +#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ +#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ +#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected + * @{ + */ +#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U +#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) +#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) +#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) +/** + * @} + */ + +/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected + * @{ + */ +#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U +#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0) +#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1) +#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2) +#define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) +#define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3) +#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1)) +#define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2)) +#define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0)) +#define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1)) +#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL) +#define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U) +/** + * @} + */ + +/** @defgroup ADCEx_injected_rank ADC Injected Rank + * @{ + */ +#define ADC_INJECTED_RANK_1 0x00000001U +#define ADC_INJECTED_RANK_2 0x00000002U +#define ADC_INJECTED_RANK_3 0x00000003U +#define ADC_INJECTED_RANK_4 0x00000004U +/** + * @} + */ + +/** @defgroup ADCEx_channels ADC Specific Channels + * @{ + */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ + defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ + defined(STM32F412Cx) +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx || + STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) +#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_Exported_Macros ADC Exported Macros + * @{ + */ +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +/** + * @brief Disable internal path of ADC channel Vbat + * @note Use case of this macro: + * On devices STM32F42x and STM32F43x, ADC internal channels + * Vbat and VrefInt share the same internal path, only + * one of them can be enabled.This macro is to be used when ADC + * channels Vbat and VrefInt are selected, and must be called + * before starting conversion of ADC channel VrefInt in order + * to disable ADC channel Vbat. + * @retval None + */ +#define __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() (ADC->CCR &= ~(ADC_CCR_VBATE)) +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADCEx_Exported_Functions + * @{ + */ + +/** @addtogroup ADCEx_Exported_Functions_Group1 + * @{ + */ + +/* I/O operation functions ******************************************************/ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); + +/* Peripheral Control functions *************************************************/ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); + +/** + * @} + */ + +/** + * @} + */ +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Constants ADC Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Macros ADC Private Macros + * @{ + */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ + defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ + defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ + defined(STM32F412Cx) +#define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18) +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || + STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ + +#if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \ + defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \ + defined(STM32F469xx) || defined(STM32F479xx) +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)) +#endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ + ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ + ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ + ((MODE) == ADC_DUALMODE_INJECSIMULT) || \ + ((MODE) == ADC_DUALMODE_REGSIMULT) || \ + ((MODE) == ADC_DUALMODE_INTERL) || \ + ((MODE) == ADC_DUALMODE_ALTERTRIG) || \ + ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \ + ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \ + ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \ + ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \ + ((MODE) == ADC_TRIPLEMODE_INTERL) || \ + ((MODE) == ADC_TRIPLEMODE_ALTERTRIG)) +#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \ + ((MODE) == ADC_DMAACCESSMODE_1) || \ + ((MODE) == ADC_DMAACCESSMODE_2) || \ + ((MODE) == ADC_DMAACCESSMODE_3)) +#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING)) +#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \ + ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15)|| \ + ((INJTRIG) == ADC_INJECTED_SOFTWARE_START)) +#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 1U) && ((LENGTH) <= 4U)) +#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 1U) && ((RANK) <= 4U)) + +/** + * @brief Set the selected injected Channel rank. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @param _JSQR_JL_ Sequence length. + * @retval None + */ +#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_)))) + +/** + * @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1 + * if available (ADC2, ADC3 availability depends on STM32 product) + * @param __HANDLE__ ADC handle + * @retval Common control register ADC123 or ADC1 + */ +#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define ADC_COMMON_REGISTER(__HANDLE__) ADC123_COMMON +#else +#define ADC_COMMON_REGISTER(__HANDLE__) ADC1_COMMON +#endif /* STM32F405xx || STM32F407xx || STM32F415xx || STM32F417xx || STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup ADCEx_Private_Functions ADC Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__STM32F4xx_ADC_EX_H */ + + diff --git a/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h new file mode 100644 index 0000000..49fee97 --- /dev/null +++ b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_ll_adc.h @@ -0,0 +1,4779 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_adc.h + * @author MCD Application Team + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_LL_ADC_H +#define __STM32F4xx_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx.h" + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) || defined (ADC3) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular sequencer: */ +/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ +/* - sequencer register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group regular sequencer configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SQR1_REGOFFSET 0x00000000UL +#define ADC_SQR2_REGOFFSET 0x00000100UL +#define ADC_SQR3_REGOFFSET 0x00000200UL +#define ADC_SQR4_REGOFFSET 0x00000300UL + +#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET) +#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Definition of ADC group regular sequencer bits information to be inserted */ +/* into ADC group regular sequencer ranks literals definition. */ +#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */ +#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */ +#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */ +#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */ +#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */ +#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */ +#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */ +#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */ +#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */ +#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */ +#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */ +#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */ +#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */ +#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */ +#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */ +#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */ + +/* Internal mask for ADC group injected sequencer: */ +/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ +/* - data register offset */ +/* - offset register offset */ +/* - sequencer rank bits position into the selected register */ + +/* Internal register offset for ADC group injected data register */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JDR1_REGOFFSET 0x00000000UL +#define ADC_JDR2_REGOFFSET 0x00000100UL +#define ADC_JDR3_REGOFFSET 0x00000200UL +#define ADC_JDR4_REGOFFSET 0x00000300UL + +/* Internal register offset for ADC group injected offset configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_JOFR1_REGOFFSET 0x00000000UL +#define ADC_JOFR2_REGOFFSET 0x00001000UL +#define ADC_JOFR3_REGOFFSET 0x00002000UL +#define ADC_JOFR4_REGOFFSET 0x00003000UL + +#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET) +#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET) +#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) + +/* Internal mask for ADC group regular trigger: */ +/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ +/* - regular trigger source */ +/* - regular trigger edge */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4UL * 0UL)) | \ + ((ADC_CR2_EXTSEL) >> (4UL * 1UL)) | \ + ((ADC_CR2_EXTSEL) >> (4UL * 2UL)) | \ + ((ADC_CR2_EXTSEL) >> (4UL * 3UL))) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4UL * 0UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL))) + +/* Definition of ADC group regular trigger bits information. */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */ + + + +/* Internal mask for ADC group injected trigger: */ +/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ +/* - injected trigger source */ +/* - injected trigger edge */ +#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4UL * 0UL)) | \ + ((ADC_CR2_JEXTSEL) >> (4UL * 1UL)) | \ + ((ADC_CR2_JEXTSEL) >> (4UL * 2UL)) | \ + ((ADC_CR2_JEXTSEL) >> (4UL * 3UL))) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4UL * 0UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \ + ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL))) + +/* Definition of ADC group injected trigger bits information. */ +#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */ +#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */ + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +/* - channel sampling time defined by SMPRx register offset */ +/* and SMPx bits positions into SMPRx register */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH) +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000UL /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000UL /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */ +#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) + +/* Internal register offset for ADC channel sampling time configuration */ +/* (offset placed into a spare area of literal definition) */ +#define ADC_SMPR1_REGOFFSET 0x00000000UL +#define ADC_SMPR2_REGOFFSET 0x02000000UL +#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET) + +#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000UL +#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */ + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER 0x00000000UL +#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 ) +#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 ) +#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 ) +#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 ) +#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0) +#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 ) + +/* Definition of channels sampling time information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */ +#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */ +#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */ +#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */ +#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */ +#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */ +#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */ +#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */ +#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */ +#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */ +#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */ +#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */ +#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */ +#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */ +#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */ +#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */ +#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */ +#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */ +#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */ + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* (concatenation of multiple bits used in different analog watchdogs, */ +/* (feature of several watchdogs not available on all STM32 families)). */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC groups regular and-or injected). */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET 0x00000000UL + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000UL +#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001UL +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET) + +/* ADC registers bits positions */ +#define ADC_CR1_RES_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */ +#define ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ + +/* ADC internal channels related definitions */ +/* Internal voltage reference VrefInt */ +#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ +/* Temperature sensor */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Macros ADC Private Macros + * @{ + */ + +/** + * @brief Driver macro reserved for internal use: isolate bits with the + * selected mask and shift them to the register LSB + * (shift mask on register position bit 0). + * @param __BITS__ Bits in register 32 bits + * @param __MASK__ Mask in register 32 bits + * @retval Bits in register 32 bits + */ +#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \ + (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) + +/** + * @brief Driver macro reserved for internal use: set a pointer to + * a register from a register basis from which an offset + * is applied. + * @param __REG__ Register basis from which the offset is applied. + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). + * @retval Pointer to register address + */ +#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ + ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC common parameters + * and multimode + * (all ADC instances belonging to the same ADC common instance). + * @note The setting of these parameters by function @ref LL_ADC_CommonInit() + * is conditioned to ADC instances state (all ADC instances + * sharing the same ADC common instance): + * All ADC instances sharing the same ADC common instance must be + * disabled. + */ +typedef struct +{ + uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ + +#if defined(ADC_MULTIMODE_SUPPORT) + uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). + This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ + + uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. + This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ + + uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. + This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ +#endif /* ADC_MULTIMODE_SUPPORT */ + +} LL_ADC_CommonInitTypeDef; + +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 families). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t Resolution; /*!< Set ADC resolution. + This parameter can be a value of @ref ADC_LL_EC_RESOLUTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ + + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ + + uint32_t SequencersScanMode; /*!< Set ADC scan selection. + This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this STM32 series, setting of external trigger edge is performed + using function @ref LL_ADC_REG_StartConversionExtTrig(). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ + + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_INJ_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line). + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE + @note On this STM32 series, setting of external trigger edge is performed + using function @ref LL_ADC_INJ_StartConversionExtTrig(). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ + + uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH + @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE + @note This parameter has an effect only if group injected sequencer is enabled + (scan length of 2 ranks or more). + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ + + uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. + This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO + Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. + + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ + +} LL_ADC_INJ_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ +#define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */ +#define LL_ADC_FLAG_EOCS ADC_SR_EOC /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_OVR ADC_SR_OVR /*!< ADC flag ADC group regular overrun */ +#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */ +#define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ +#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */ +#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */ +#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2 /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3 /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1 /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */ +#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2 /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */ +#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3 /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ +#define LL_ADC_IT_EOCS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ +#define LL_ADC_IT_OVR ADC_CR1_OVRIE /*!< ADC interruption ADC group regular overrun */ +#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ +#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000UL /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +#if defined(ADC_MULTIMODE_SUPPORT) +#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001UL /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source + * @{ + */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000UL /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 ) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE 0x00000000UL /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */ +#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE) /*!< ADC measurement path to internal channel Vbat */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B 0x00000000UL /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0) /*!< ADC resolution 10 bits */ +#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 ) /*!< ADC resolution 8 bits */ +#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000UL /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection + * @{ + */ +#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/ +#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR 0x00000001UL /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_INJECTED 0x00000002UL /*!< ADC group injected (not available on all STM32 devices)*/ +#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003UL /*!< ADC both groups regular and injected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ +#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ +#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +#define LL_ADC_REG_TRIG_SOFTWARE 0x00000000UL /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode +* @{ +*/ +#define LL_ADC_REG_CONV_SINGLE 0x00000000UL /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000UL /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions) + * @{ + */ +#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000UL /*!< ADC flag EOC (end of unitary conversion) selected */ +#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ +#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */ +#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks + * @{ + */ +#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ +#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */ +#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */ +#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */ +#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */ +#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */ +#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */ +#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */ +#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source + * @{ + */ +#define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000UL /*!< ADC group injected conversion trigger internal: SW start. */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge + * @{ + */ +#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */ +#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 ) /*!< ADC group injected conversion trigger polarity set to falling edge */ +#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode +* @{ +*/ +#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ +#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ +/** + * @} + */ + + +/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length + * @{ + */ +#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000UL /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */ +#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000UL /*!< ADC group injected sequencer discontinuous mode disable */ +#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks + * @{ + */ +#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001UL) /*!< ADC group injected sequencer rank 1 */ +#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002UL) /*!< ADC group injected sequencer rank 2 */ +#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003UL) /*!< ADC group injected sequencer rank 3 */ +#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004UL) /*!< ADC group injected sequencer rank 4 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000UL /*!< Sampling time 3 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0) /*!< Sampling time 15 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1) /*!< Sampling time 28 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0) /*!< Sampling time 56 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2) /*!< Sampling time 84 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0) /*!< Sampling time 112 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1) /*!< Sampling time 144 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10) /*!< Sampling time 480 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE 0x00000000UL /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ +#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */ +#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */ +#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */ +#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */ +#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */ +#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ +#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ +#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ +#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ +#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */ +/** + * @} + */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode + * @{ + */ +#define LL_ADC_MULTI_INDEPENDENT 0x00000000UL /*!< ADC dual mode disabled (ADC independent mode) */ +#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: group regular simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */ +#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ +#if defined(ADC3) +#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */ +#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */ +#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */ +#define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 ) /*!< ADC triple mode enabled: group regular simultaneous */ +#define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */ +#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ +#endif +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER Multimode - DMA transfer + * @{ + */ +#define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000UL /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */ +#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */ +#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_1 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases + * @{ + */ +#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000UL /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/ +#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */ +#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave + * @{ + */ +#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */ +#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV ) /*!< In multimode, selection among several ADC instances: ADC slave */ +#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */ +/** + * @} + */ + +#endif /* ADC_MULTIMODE_SUPPORT */ + + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC IP HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* STM32 series: */ +/* - ADC enable time: maximum delay is 2us */ +/* (refer to device datasheet, parameter "tSTAB") */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + +/* Delay for internal voltage reference stabilization time. */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10UL) /*!< Delay for internal voltage reference stabilization time */ + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Value between Min_Data=0 and Max_Data=18 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) <= 9UL) \ + ? ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR2_REGOFFSET | (((uint32_t) (3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + : \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_SMPR1_REGOFFSET | (((uint32_t) (3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \ + ) \ + ) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1. + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \ + ) +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD1, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @arg @ref LL_ADC_GROUP_INJECTED + * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ + (((__GROUP__) == LL_ADC_GROUP_REGULAR) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + : \ + ((__GROUP__) == LL_ADC_GROUP_INJECTED) \ + ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \ + : \ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \ + ) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL ))) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL ))) + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Helper macro to get the ADC multimode conversion data of ADC master + * or ADC slave from raw value with both ADC conversion data concatenated. + * @note This macro is intended to be used when multimode transfer by DMA + * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). + * In this case the transferred data need to processed with this macro + * to separate the conversion data of ADC master and ADC slave. + * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ + (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST) +#endif + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC123_COMMON) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC12_COMMON) +#else +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC1_COMMON) +#endif + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#if defined(ADC1) && defined(ADC2) && defined(ADC3) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) | \ + LL_ADC_IsEnabled(ADC3) ) +#elif defined(ADC1) && defined(ADC2) +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1) | \ + LL_ADC_IsEnabled(ADC2) ) +#else +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + (LL_ADC_IsEnabled(ADC1)) +#endif + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ + (((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)) \ + ) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ + __ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + ) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this STM32 series, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ + / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B)) + +/* Note: On device STM32F4x9, calibration parameter TS_CAL2 is not available. */ +/* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/ +/* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */ +#if !defined(STM32F469) && !defined(STM32F479xx) && !defined(STM32F429xx) && !defined(STM32F439xx) +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this STM32 series, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) +#endif + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). + * On STM32F4, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). + * On STM32F4, refer to device datasheet parameter "V25". + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + ((( ( \ + (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000) \ + - \ + (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000) \ + ) \ + ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (__TEMPSENSOR_CALX_TEMP__) \ + ) + +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @rmtoll DR RDATA LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_MST LL_ADC_DMA_GetRegAddr\n + * CDR RDATA_SLV LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) + * + * (1) Available on devices with several ADC instances. + * @retval ADC register address + */ +#if defined(ADC_MULTIMODE_SUPPORT) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + uint32_t data_reg_addr = 0UL; + + if (Register == LL_ADC_DMA_REG_REGULAR_DATA) + { + /* Retrieve address of register DR */ + data_reg_addr = (uint32_t)&(ADCx->DR); + } + else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ + { + /* Retrieve address of register CDR */ + data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); + } + + return data_reg_addr; +} +#else +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + /* Retrieve address of register DR */ + return (uint32_t)&(ADCx->DR); +} +#endif + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR ADCPRE LL_ADC_SetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param CommonClock This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock); +} + +/** + * @brief Get parameter common to several ADC: Clock source and prescaler. + * @rmtoll CCR ADCPRE LL_ADC_GetCommonClock + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE)); +} + +/** + * @brief Set parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @rmtoll CCR TSVREFE LL_ADC_SetCommonPathInternalCh\n + * CCR VBATE LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR TSVREFE LL_ADC_GetCommonPathInternalCh\n + * CCR VBATE LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @arg @ref LL_ADC_PATH_INTERNAL_VBAT + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR1 RES LL_ADC_SetResolution + * @param ADCx ADC instance + * @param Resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution); +} + +/** + * @brief Get ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR1 RES LL_ADC_GetResolution + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES)); +} + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN)); +} + +/** + * @brief Set ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode + * @param ADCx ADC instance + * @param ScanMode This parameter can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode); +} + +/** + * @brief Get ADC sequencers scan mode, for all ADC groups + * (group regular, group injected). + * @note According to sequencers scan mode : + * - If disabled: ADC conversion is performed in unitary conversion + * mode (one channel converted, that defined in rank 1). + * Configuration of sequencers of all ADC groups + * (sequencer scan length, ...) is discarded: equivalent to + * scan length of 1 rank. + * - If enabled: ADC conversions are performed in sequence conversions + * mode, according to configuration of sequencers of + * each ADC group (sequencer scan length, ...). + * Refer to function @ref LL_ADC_REG_SetSequencerLength() + * and to function @ref LL_ADC_INJ_SetSequencerLength(). + * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_SEQ_SCAN_ENABLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 series, setting of external trigger edge is performed + * using function @ref LL_ADC_REG_StartConversionExtTrig(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n + * CR2 EXTEN LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 series, ADC group regular external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_REG_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n + * CR2 EXTEN LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH2 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +{ + uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ + uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + + /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN) + ); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CR2 EXTEN LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN)); +} + +/** + * @brief Get ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @note On this STM32 series, setting of external trigger edge is performed + * using function @ref LL_ADC_REG_StartConversionExtTrig(). + * @rmtoll CR2 EXTEN LL_ADC_REG_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN)); +} + + +/** + * @brief Set ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 series, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks); +} + +/** + * @brief Get ADC group regular sequencer length and scan direction. + * @note Description of ADC group regular sequencer features: + * - For devices with sequencer fully configurable + * (function "LL_ADC_REG_SetSequencerRanks()" available): + * sequencer length and each rank affectation to a channel + * are configurable. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerRanks()". + * - For devices with sequencer not fully configurable + * (function "LL_ADC_REG_SetSequencerChannels()" available): + * sequencer length and each rank affectation to a channel + * are defined by channel number. + * This function retrieves: + * - Sequence length: Number of ranks in the scan sequence is + * defined by number of channels set in the sequence, + * rank of each channel is fixed by channel HW number. + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from lowest channel number to + * highest channel number). + * Sequencer ranks are selected using + * function "LL_ADC_REG_SetSequencerChannels()". + * @note On this STM32 series, group regular sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS + * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note It is not possible to enable both ADC auto-injected mode + * and ADC group regular sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n + * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS + * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM)); +} + +/** + * @brief Set ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note This function performs configuration of: + * - Channels ordering into each rank of scan sequence: + * whatever channel can be placed into whatever rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register and register position depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on the selected + * scan sequence rank. + * @note On this STM32 series, ADC group regular sequencer is + * fully configurable: sequencer length and each rank + * affectation to a channel are configurable. + * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n + * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n + * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n + * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_RANK_1 + * @arg @ref LL_ADC_REG_RANK_2 + * @arg @ref LL_ADC_REG_RANK_3 + * @arg @ref LL_ADC_REG_RANK_4 + * @arg @ref LL_ADC_REG_RANK_5 + * @arg @ref LL_ADC_REG_RANK_6 + * @arg @ref LL_ADC_REG_RANK_7 + * @arg @ref LL_ADC_REG_RANK_8 + * @arg @ref LL_ADC_REG_RANK_9 + * @arg @ref LL_ADC_REG_RANK_10 + * @arg @ref LL_ADC_REG_RANK_11 + * @arg @ref LL_ADC_REG_RANK_12 + * @arg @ref LL_ADC_REG_RANK_13 + * @arg @ref LL_ADC_REG_RANK_14 + * @arg @ref LL_ADC_REG_RANK_15 + * @arg @ref LL_ADC_REG_RANK_16 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); + + return (uint32_t) (READ_BIT(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ); +} + +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT)); +} + +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note For devices with several ADC instances: ADC multimode DMA + * settings are available using function @ref LL_ADC_SetMultiDMATransfer(). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer\n + * CR2 DDS LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note For devices with several ADC instances: ADC multimode DMA + * settings are available using function @ref LL_ADC_GetMultiDMATransfer(). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer\n + * CR2 DDS LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS)); +} + +/** + * @brief Specify which ADC flag between EOC (end of unitary conversion) + * or EOS (end of sequence conversions) is used to indicate + * the end of conversion. + * @note This feature is aimed to be set when using ADC with + * programming model by polling or interruption + * (programming model by DMA usually uses DMA interruptions + * to indicate end of conversion and data transfer). + * @note For ADC group injected, end of conversion (flag&IT) is raised + * only at the end of the sequence. + * @rmtoll CR2 EOCS LL_ADC_REG_SetFlagEndOfConversion + * @param ADCx ADC instance + * @param EocSelection This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV + * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection) +{ + MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection); +} + +/** + * @brief Get which ADC flag between EOC (end of unitary conversion) + * or EOS (end of sequence conversions) is used to indicate + * the end of conversion. + * @rmtoll CR2 EOCS LL_ADC_REG_GetFlagEndOfConversion + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV + * @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Set ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this STM32 series, setting of external trigger edge is performed + * using function @ref LL_ADC_INJ_StartConversionExtTrig(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n + * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ +/* Note: On this STM32 series, ADC group injected external trigger edge */ +/* is used to perform a ADC conversion start. */ +/* This function does not set external trigger edge. */ +/* This feature is set using function */ +/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ + MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); +} + +/** + * @brief Get ADC group injected conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group injected trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") + * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n + * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH1 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH3 + * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 + * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) +{ + uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ + uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); + + /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL) + | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN) + ); +} + +/** + * @brief Get ADC group injected conversion trigger source internal (SW start) + or external + * @note In case of group injected trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_INJ_GetTriggerSource. + * @rmtoll CR2 JEXTEN LL_ADC_INJ_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN)); +} + +/** + * @brief Get ADC group injected conversion trigger polarity. + * Applicable only for trigger source set to external trigger. + * @rmtoll CR2 JEXTEN LL_ADC_INJ_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN)); +} + +/** + * @brief Set ADC group injected sequencer length and scan direction. + * @note This function performs configuration of: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 series, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength + * @param ADCx ADC instance + * @param SequencerNbRanks This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) +{ + MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks); +} + +/** + * @brief Get ADC group injected sequencer length and scan direction. + * @note This function retrieves: + * - Sequence length: Number of ranks in the scan sequence. + * - Sequence direction: Unless specified in parameters, sequencer + * scan direction is forward (from rank 1 to rank n). + * @note On this STM32 series, group injected sequencer configuration + * is conditioned to ADC instance sequencer mode. + * If ADC instance sequencer mode is disabled, sequencers of + * all groups (group regular, group injected) can be configured + * but their execution is disabled (limited to rank 1). + * Refer to function @ref LL_ADC_SetSequencersScanMode(). + * @note Sequencer disabled is equivalent to sequencer of 1 rank: + * ADC conversion on only 1 channel. + * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS + * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL)); +} + +/** + * @brief Set ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group injected sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN)); +} + +/** + * @brief Set ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this STM32 series, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) +{ + /* Set bits with content of parameter "Channel" with bits position */ + /* in register depending on parameter "Rank". */ + /* Parameters "Rank" and "Channel" are used with masks because containing */ + /* other bits reserved for other purpose. */ + uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL; + + MODIFY_REG(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))), + (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))); +} + +/** + * @brief Get ADC group injected sequence: channel on the selected + * sequence rank. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n + * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +{ + uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL; + + return (uint32_t)(READ_BIT(ADCx->JSQR, + ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))) + >> (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))) + ); +} + +/** + * @brief Set ADC group injected conversion trigger: + * independent or from ADC group regular. + * @note This mode can be used to extend number of data registers + * updated after one ADC conversion trigger and with data + * permanently kept (not erased by successive conversions of scan of + * ADC sequencer ranks), up to 5 data registers: + * 1 data register on ADC group regular, 4 data registers + * on ADC group injected. + * @note If ADC group injected injected trigger source is set to an + * external trigger, this feature must be must be set to + * independent trigger. + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only + * from ADC group regular. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto + * @param ADCx ADC instance + * @param TrigAuto This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto) +{ + MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto); +} + +/** + * @brief Get ADC group injected conversion trigger: + * independent or from ADC group regular. + * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT + * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO)); +} + +/** + * @brief Set ADC group injected offset. + * @note It sets: + * - ADC group injected rank to which the offset programmed + * will be applied + * - Offset level (offset to be subtracted from the raw + * converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @note Offset cannot be enabled or disabled. + * To emulate offset disabled, set an offset value equal to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_JOFR1_JOFFSET1, + OffsetLevel); +} + +/** + * @brief Get ADC group injected offset. + * @note It gives offset level (offset to be subtracted from the raw converted data). + * Caution: Offset format is dependent to ADC resolution: + * offset has to be left-aligned on bit 11, the LSB (right bits) + * are set to 0. + * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n + * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n + * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n + * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JOFR1_JOFFSET1) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels + * @{ + */ + +/** + * @brief Set sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @rmtoll SMPR1 SMP18 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime) +{ + /* Set bits with content of parameter "SamplingTime" with bits position */ + /* in register and register position depending on parameter "Channel". */ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + MODIFY_REG(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), + SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); +} + +/** + * @brief Get sampling time of the selected ADC channel + * Unit: ADC clock cycles. + * @note On this device, sampling time is on channel scope: independently + * of channel mapped on ADC group regular or injected. + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this STM32 series. + * @rmtoll SMPR1 SMP18 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n + * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n + * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime + * @param ADCx ADC instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_13 + * @arg @ref LL_ADC_CHANNEL_14 + * @arg @ref LL_ADC_CHANNEL_15 + * @arg @ref LL_ADC_CHANNEL_16 + * @arg @ref LL_ADC_CHANNEL_17 + * @arg @ref LL_ADC_CHANNEL_18 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) + * @arg @ref LL_ADC_CHANNEL_VBAT (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES + * @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) + >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel or all channels, + * on ADC groups regular and-or injected. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)(2) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) + * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) + * + * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n + * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) +{ + MODIFY_REG(ADCx->CR1, + (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH), + AWDChannelGroup); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n + * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG + * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG + * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG + * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG + * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG + * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG + * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG + * @arg @ref LL_ADC_AWD_CHANNEL_18_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH))); +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this STM32 series, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD1): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC groups regular and-or injected. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n + * LTR LT LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + MODIFY_REG(*preg, + ADC_HTR_HT, + AWDThresholdValue); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high or + * threshold low. + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n + * LTR LT LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF +*/ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); + + return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode + * @{ + */ + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Set ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CCR MULTI LL_ADC_SetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param Multimode This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode); +} + +/** + * @brief Get ADC multimode configuration to operate in independent mode + * or multimode (for devices with several ADC instances). + * @note If multimode configuration: the selected ADC instance is + * either master or slave depending on hardware. + * Refer to reference manual. + * @rmtoll CCR MULTI LL_ADC_GetMultimode + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_INDEPENDENT + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL + * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT + * @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL + * @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI)); +} + +/** + * @brief Set ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @rmtoll CCR MDMA LL_ADC_SetMultiDMATransfer\n + * CCR DDS LL_ADC_SetMultiDMATransfer + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiDMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer); +} + +/** + * @brief Get ADC multimode conversion data transfer: no transfer + * or transfer by DMA. + * @note If ADC multimode transfer by DMA is not selected: + * each ADC uses its own DMA channel, with its individual + * DMA transfer settings. + * If ADC multimode transfer by DMA is selected: + * One DMA channel is used for both ADC (DMA of ADC master) + * Specifies the DMA requests mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note How to retrieve multimode conversion data: + * Whatever multimode transfer by DMA setting: using function + * @ref LL_ADC_REG_ReadMultiConversionData32(). + * If ADC multimode transfer by DMA is selected: conversion data + * is a raw data with ADC master and slave concatenated. + * A macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * @rmtoll CCR MDMA LL_ADC_GetMultiDMATransfer\n + * CCR DDS LL_ADC_GetMultiDMATransfer + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2 + * @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3 + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS)); +} + +/** + * @brief Set ADC multimode delay between 2 sampling phases. + * @note The sampling delay range depends on ADC resolution: + * - ADC resolution 12 bits can have maximum delay of 12 cycles. + * - ADC resolution 10 bits can have maximum delay of 10 cycles. + * - ADC resolution 8 bits can have maximum delay of 8 cycles. + * - ADC resolution 6 bits can have maximum delay of 6 cycles. + * @rmtoll CCR DELAY LL_ADC_SetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param MultiTwoSamplingDelay This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay); +} + +/** + * @brief Get ADC multimode delay between 2 sampling phases. + * @rmtoll CCR DELAY LL_ADC_GetMultiTwoSamplingDelay + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES + * @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES + */ +__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY)); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Enable the selected ADC instance. + * @note On this STM32 series, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @rmtoll CR2 ADON LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Disable the selected ADC instance. + * @rmtoll CR2 ADON LL_ADC_Disable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON); +} + +/** + * @brief Get the selected ADC instance enable state. + * @rmtoll CR2 ADON LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this STM32 series, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_REG_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_SWSTART); +} + +/** + * @brief Start ADC group regular conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 series, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_REG_StartConversionSWStart(). + * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group regular conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 series, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 EXTEN LL_ADC_REG_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData10 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData8 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData6 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get ADC multimode conversion data of ADC master, ADC slave + * or raw data with ADC master and slave concatenated. + * @note If raw data with ADC master and slave concatenated is retrieved, + * a macro is available to get the conversion data of + * ADC master or ADC slave: see helper macro + * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(). + * (however this macro is mainly intended for multimode + * transfer by DMA, because this function can do the same + * by getting multimode conversion data of ADC master or ADC slave + * separately). + * @rmtoll CDR DATA1 LL_ADC_REG_ReadMultiConversionData32\n + * CDR DATA2 LL_ADC_REG_ReadMultiConversionData32 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ConversionData This parameter can be one of the following values: + * @arg @ref LL_ADC_MULTI_MASTER + * @arg @ref LL_ADC_MULTI_SLAVE + * @arg @ref LL_ADC_MULTI_MASTER_SLAVE + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR, + ADC_DR_ADC2DATA) + >> POSITION_VAL(ConversionData) + ); +} +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected + * @{ + */ + +/** + * @brief Start ADC group injected conversion. + * @note On this STM32 series, this function is relevant only for + * internal trigger (SW start), not for external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * start must be performed using function + * @ref LL_ADC_INJ_StartConversionExtTrig(). + * (if external trigger edge would have been set during ADC other + * settings, ADC conversion would start at trigger event + * as soon as ADC is enabled). + * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART); +} + +/** + * @brief Start ADC group injected conversion from external trigger. + * @note ADC conversion will start at next trigger event (on the selected + * trigger edge) following the ADC start conversion command. + * @note On this STM32 series, this function is relevant for + * ADC conversion start from external trigger. + * If internal trigger (SW start) is needed, perform ADC conversion + * start using function @ref LL_ADC_INJ_StartConversionSWStart(). + * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING + * @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING + * @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + SET_BIT(ADCx->CR2, ExternalTriggerEdge); +} + +/** + * @brief Stop ADC group injected conversion from external trigger. + * @note No more ADC conversion will start at next trigger event + * following the ADC stop conversion command. + * If a conversion is on-going, it will be completed. + * @note On this STM32 series, there is no specific command + * to stop a conversion on-going or to stop ADC converting + * in continuous mode. These actions can be performed + * using function @ref LL_ADC_Disable(). + * @rmtoll CR2 JEXTEN LL_ADC_INJ_StopConversionExtTrig + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData32 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint32_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData12 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData10\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData10 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint16_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData8\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData8 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint8_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @brief Get ADC group injected conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_INJ_ReadConversionData32. + * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR2 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR3 JDATA LL_ADC_INJ_ReadConversionData6\n + * JDR4 JDATA LL_ADC_INJ_ReadConversionData6 + * @param ADCx ADC instance + * @param Rank This parameter can be one of the following values: + * @arg @ref LL_ADC_INJ_RANK_1 + * @arg @ref LL_ADC_INJ_RANK_2 + * @arg @ref LL_ADC_INJ_RANK_3 + * @arg @ref LL_ADC_INJ_RANK_4 + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) +{ + __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); + + return (uint8_t)(READ_BIT(*preg, + ADC_JDR1_JDATA) + ); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOCS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); +} + +/** + * @brief Get flag ADC group regular overrun. + * @rmtoll SR OVR LL_ADC_IsActiveFlag_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); +} + + +/** + * @brief Get flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)); +} + +/** + * @brief Clear flag ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll SR EOC LL_ADC_ClearFlag_EOCS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS); +} + +/** + * @brief Clear flag ADC group regular overrun. + * @rmtoll SR OVR LL_ADC_ClearFlag_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR); +} + + +/** + * @brief Clear flag ADC group injected end of sequence conversions. + * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1); +} + +#if defined(ADC_MULTIMODE_SUPPORT) +/** + * @brief Get flag multimode ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration, of the ADC master. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CSR EOC1 LL_ADC_IsActiveFlag_MST_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_MST) == (LL_ADC_FLAG_EOCS_MST)); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration, of the ADC slave 1. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CSR EOC2 LL_ADC_IsActiveFlag_SLV1_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1)); +} + +/** + * @brief Get flag multimode ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration, of the ADC slave 2. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CSR EOC3 LL_ADC_IsActiveFlag_SLV2_EOCS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2)); +} +/** + * @brief Get flag multimode ADC group regular overrun of the ADC master. + * @rmtoll CSR OVR1 LL_ADC_IsActiveFlag_MST_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC slave 1. + * @rmtoll CSR OVR2 LL_ADC_IsActiveFlag_SLV1_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1)); +} + +/** + * @brief Get flag multimode ADC group regular overrun of the ADC slave 2. + * @rmtoll CSR OVR3 LL_ADC_IsActiveFlag_SLV2_OVR + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2)); +} + + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. + * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1)); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1. + * @rmtoll CSR JEOC2 LL_ADC_IsActiveFlag_SLV1_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2)); +} + +/** + * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2. + * @rmtoll CSR JEOC3 LL_ADC_IsActiveFlag_SLV2_JEOS + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3)); +} + +/** + * @brief Get flag multimode ADC analog watchdog 1 of the ADC master. + * @rmtoll CSR AWD1 LL_ADC_IsActiveFlag_MST_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave 1. + * @rmtoll CSR AWD2 LL_ADC_IsActiveFlag_SLV1_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1)); +} + +/** + * @brief Get flag multimode analog watchdog 1 of the ADC slave 2. + * @rmtoll CSR AWD3 LL_ADC_IsActiveFlag_SLV2_AWD1 + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); +} + +#endif /* ADC_MULTIMODE_SUPPORT */ + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ + +/** + * @brief Enable interruption ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOCS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS); +} + +/** + * @brief Enable ADC group regular interruption overrun. + * @rmtoll CR1 OVRIE LL_ADC_EnableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_OVR); +} + + +/** + * @brief Enable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOCS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS); +} + +/** + * @brief Disable interruption ADC group regular overrun. + * @rmtoll CR1 OVRIE LL_ADC_DisableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR); +} + + +/** + * @brief Disable interruption ADC group injected end of sequence conversions. + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1); +} + +/** + * @brief Get state of interruption ADC group regular end of unitary conversion + * or end of sequence conversions, depending on + * ADC configuration. + * @note To configure flag of end of conversion, + * use function @ref LL_ADC_REG_SetFlagEndOfConversion(). + * (0: interrupt disabled, 1: interrupt enabled) + * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOCS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS)); +} + +/** + * @brief Get state of interruption ADC group regular overrun + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 OVRIE LL_ADC_IsEnabledIT_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); +} + + +/** + * @brief Get state of interruption ADC group injected end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx) +{ + /* Note: on this STM32 series, there is no flag ADC group injected */ + /* end of unitary conversion. */ + /* Flag noted as "JEOC" is corresponding to flag "JEOS" */ + /* in other STM32 families). */ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1 + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); + +/* De-initialization of ADC instance, ADC group regular and ADC group injected */ +/* (availability of ADC group injected depends on STM32 families) */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); + +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); + +/* Initialization of some features of ADC instance and ADC group injected */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_LL_ADC_H */ + diff --git a/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c new file mode 100644 index 0000000..9c2ba28 --- /dev/null +++ b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc.c @@ -0,0 +1,2110 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_adc.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Converter (ADC) peripheral: + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### ADC Peripheral features ##### + ============================================================================== + [..] + (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. + (#) Interrupt generation at the end of conversion, end of injected conversion, + and in case of analog watchdog or overrun events + (#) Single and continuous conversion modes. + (#) Scan mode for automatic conversion of channel 0 to channel x. + (#) Data alignment with in-built data coherency. + (#) Channel-wise programmable sampling time. + (#) External trigger option with configurable polarity for both regular and + injected conversion. + (#) Dual/Triple mode (on devices with 2 ADCs or more). + (#) Configurable DMA data storage in Dual/Triple ADC mode. + (#) Configurable delay between conversions in Dual/Triple interleaved mode. + (#) ADC conversion type (refer to the datasheets). + (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + slower speed. + (#) ADC input range: VREF(minus) = VIN = VREF(plus). + (#) DMA request generation during regular channel conversion. + + + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): + (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() + (##) ADC pins configuration + (+++) Enable the clock for the ADC GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE() + (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() + (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) + (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() + (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA streams stream for managing data + transfer from peripheral to memory (output stream) + (+++) Associate the initialized DMA handle to the CRYP DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA Streams. The output stream should have higher + priority than the input stream. + + *** Configuration of ADC, groups regular/injected, channels parameters *** + ============================================================================== + [..] + (#) Configure the ADC parameters (resolution, data alignment, ...) + and regular group parameters (conversion trigger, sequencer, ...) + using function HAL_ADC_Init(). + + (#) Configure the channels for regular group parameters (channel number, + channel rank into sequencer, ..., into regular group) + using function HAL_ADC_ConfigChannel(). + + (#) Optionally, configure the injected group parameters (conversion trigger, + sequencer, ..., of injected group) + and the channels for injected group parameters (channel number, + channel rank into sequencer, ..., into injected group) + using function HAL_ADCEx_InjectedConfigChannel(). + + (#) Optionally, configure the analog watchdog parameters (channels + monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). + + (#) Optionally, for devices with several ADC instances: configure the + multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). + + *** Execution of ADC conversions *** + ============================================================================== + [..] + (#) ADC driver can be used among three modes: polling, interruption, + transfer by DMA. + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the ADC peripheral using HAL_ADC_Start() + (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage + user can specify the value of timeout according to his end application + (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. + (+) Stop the ADC peripheral using HAL_ADC_Stop() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the ADC peripheral using HAL_ADC_Start_IT() + (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine + (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ErrorCallback + (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ErrorCallback + (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() + + *** ADC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in ADC HAL driver. + + (+) __HAL_ADC_ENABLE : Enable the ADC peripheral + (+) __HAL_ADC_DISABLE : Disable the ADC peripheral + (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt + (+) __HAL_ADC_DISABLE_IT: Disable the ADC end of conversion interrupt + (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled + (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags + (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status + (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register + + [..] + (@) You can refer to the ADC HAL driver header file for more useful macros + + *** Deinitialization of ADC *** + ============================================================================== + [..] + (#) Disable the ADC interface + (++) ADC clock can be hard reset and disabled at RCC top level. + (++) Hard reset of ADC peripherals + using macro __HAL_RCC_ADC_FORCE_RESET(), __HAL_RCC_ADC_RELEASE_RESET(). + (++) ADC clock disable using the equivalent macro/functions as configuration step. + (+++) Example: + Into HAL_ADC_MspDeInit() (recommended code location) or with + other device clock parameters configuration: + (+++) HAL_RCC_GetOscConfig(&RCC_OscInitStructure); + (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI; + (+++) RCC_OscInitStructure.HSIState = RCC_HSI_OFF; (if not used for system clock) + (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); + + (#) ADC pins configuration + (++) Disable the clock for the ADC GPIOs using macro __HAL_RCC_GPIOx_CLK_DISABLE() + + (#) Optionally, in case of usage of ADC with interruptions: + (++) Disable the NVIC for ADC using function HAL_NVIC_DisableIRQ(ADCx_IRQn) + + (#) Optionally, in case of usage of DMA: + (++) Deinitialize the DMA using function HAL_DMA_DeInit(). + (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) + *** Callback registration *** + ============================================================================== + [..] + + The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, + allows the user to configure dynamically the driver callbacks. + Use Functions HAL_ADC_RegisterCallback() + to register an interrupt callback. + [..] + + Function HAL_ADC_RegisterCallback() allows to register following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + [..] + + Use function HAL_ADC_UnRegisterCallback to reset a callback to the default + weak function. + [..] + + HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) ConvCpltCallback : ADC conversion complete callback + (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback + (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback + (+) ErrorCallback : ADC error callback + (+) InjectedConvCpltCallback : ADC group injected conversion complete callback + (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback + (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback + (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback + (+) EndOfSamplingCallback : ADC end of sampling callback + (+) MspInitCallback : ADC Msp Init callback + (+) MspDeInitCallback : ADC Msp DeInit callback + [..] + + By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when + these callbacks are null (not registered beforehand). + [..] + + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. + [..] + + Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. + Exception done MspInit/MspDeInit functions that can be registered/unregistered + in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + [..] + + Then, the user first registers the MspInit/MspDeInit user callbacks + using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + or HAL_ADC_Init() function. + [..] + + When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup ADC ADC + * @brief ADC driver modules + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup ADC_Private_Functions + * @{ + */ +/* Private function prototypes -----------------------------------------------*/ +static void ADC_Init(ADC_HandleTypeDef* hadc); +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_DMAError(DMA_HandleTypeDef *hdma); +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the ADC. + (+) De-initialize the ADC. + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct and initializes the ADC MSP. + * + * @note This function is used to configure the global features of the ADC ( + * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, + * the rest of the configuration parameters are specific to the regular + * channels group (scan mode activation, continuous mode activation, + * External trigger source and edge, DMA continuous request after the + * last transfer and End of conversion selection). + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); + assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ScanConvMode)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG(hadc->Init.ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); + assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); + + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + } + + if(hadc->State == HAL_ADC_STATE_RESET) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + /* Init the ADC Callback settings */ + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ + hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ + if (hadc->MspInitCallback == NULL) + { + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + } + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Initialize ADC error code */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; + } + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_BUSY_INTERNAL); + + /* Set ADC parameters */ + ADC_Init(hadc); + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_READY); + } + else + { + tmp_hal_status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check ADC handle */ + if(hadc == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } + + /* DeInit the low level hardware: RCC clock, NVIC */ + hadc->MspDeInitCallback(hadc); +#else + /* DeInit the low level hardware: RCC clock, NVIC */ + HAL_ADC_MspDeInit(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + + /* Set ADC state */ + hadc->State = HAL_ADC_STATE_RESET; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ADC Callback + * To be used instead of the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = pCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = pCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = pCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = pCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = pCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = pCallback; + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister a ADC Callback + * ADC callback is redirected to the weak predefined callback + * @param hadc Pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID + * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID + * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID + * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID + * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID + * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID + * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) + { + switch (CallbackID) + { + case HAL_ADC_CONVERSION_COMPLETE_CB_ID : + hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; + break; + + case HAL_ADC_CONVERSION_HALF_CB_ID : + hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; + break; + + case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : + hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; + break; + + case HAL_ADC_ERROR_CB_ID : + hadc->ErrorCallback = HAL_ADC_ErrorCallback; + break; + + case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : + hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; + break; + + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if (HAL_ADC_STATE_RESET == hadc->State) + { + switch (CallbackID) + { + case HAL_ADC_MSPINIT_CB_ID : + hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ + break; + + case HAL_ADC_MSPDEINIT_CB_ID : + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + break; + + default : + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Update the error code */ + hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; + + /* Return error status */ + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + +/** + * @brief Initializes the ADC MSP. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes the ADC MSP. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_MspDeInit could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of regular channel. + (+) Stop conversion of regular channel. + (+) Start conversion of regular channel and enable interrupt. + (+) Stop conversion of regular channel and disable interrupt. + (+) Start conversion of regular channel and enable DMA transfer. + (+) Stop conversion of regular channel and disable DMA transfer. + (+) Handle ADC interrupt request. + +@endverbatim + * @{ + */ + +/** + * @brief Enables ADC and starts conversion of the regular channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0U; + ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(counter != 0U) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + { +#if defined(ADC2) && defined(ADC3) + if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + { +#endif /* ADC2 || ADC3 */ + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } +#if defined(ADC2) && defined(ADC3) + } +#endif /* ADC2 || ADC3 */ + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables ADC and stop conversion of regular channels. + * + * @note Caution: This function will stop also injected channels. + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Poll for regular conversion complete + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function. + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and polling for end of each conversion. */ + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && + HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of conversion flag */ + while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + { + /* Check if timeout is disabled (set to infinite wait) */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F4, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Poll for conversion event + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param EventType the ADC event type. + * This parameter can be one of the following values: + * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. + * @arg ADC_OVR_EVENT: ADC Overrun event. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + assert_param(IS_ADC_EVENT_TYPE(EventType)); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check selected event flag */ + while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + { + /* Update ADC state machine to timeout */ + SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_TIMEOUT; + } + } + } + } + + /* Analog watchdog (level out of window) event */ + if(EventType == ADC_AWD_EVENT) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Clear ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + } + /* Overrun event */ + else + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } + + /* Return ADC state */ + return HAL_OK; +} + + +/** + * @brief Enables the interrupt and starts ADC conversion of regular channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0U; + ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(counter != 0U) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Enable end of conversion interrupt for regular group */ + __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + { +#if defined(ADC2) && defined(ADC3) + if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + { +#endif /* ADC2 || ADC3 */ + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } +#if defined(ADC2) && defined(ADC3) + } +#endif /* ADC2 || ADC3 */ + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables the interrupt and stop ADC conversion of regular channels. + * + * @note Caution: This function will stop also injected channels. + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable ADC end of conversion interrupt for regular group */ + __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Handles ADC interrupt request + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +{ + uint32_t tmp1 = 0U, tmp2 = 0U; + + uint32_t tmp_sr = hadc->Instance->SR; + uint32_t tmp_cr1 = hadc->Instance->CR1; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); + assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); + + tmp1 = tmp_sr & ADC_FLAG_EOC; + tmp2 = tmp_cr1 & ADC_IT_EOC; + /* Check End of conversion flag for regular channels */ + if(tmp1 && tmp2) + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + } + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F4, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear regular group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); + } + + tmp1 = tmp_sr & ADC_FLAG_JEOC; + tmp2 = tmp_cr1 & ADC_IT_JEOC; + /* Check End of conversion flag for injected channels */ + if(tmp1 && tmp2) + { + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + } + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, scan sequence on going or by automatic injected */ + /* conversion from group regular (same conditions as group regular */ + /* interruption disabling above). */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + { + /* Disable ADC end of single conversion interrupt on group injected */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->InjectedConvCpltCallback(hadc); +#else + HAL_ADCEx_InjectedConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); + } + + tmp1 = tmp_sr & ADC_FLAG_AWD; + tmp2 = tmp_cr1 & ADC_IT_AWD; + /* Check Analog watchdog flag */ + if(tmp1 && tmp2) + { + if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) + { + /* Set ADC state */ + SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); + + /* Level out of window callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->LevelOutOfWindowCallback(hadc); +#else + HAL_ADC_LevelOutOfWindowCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear the ADC analog watchdog flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); + } + } + + tmp1 = tmp_sr & ADC_FLAG_OVR; + tmp2 = tmp_cr1 & ADC_IT_OVR; + /* Check Overrun flag */ + if(tmp1 && tmp2) + { + /* Note: On STM32F4, ADC overrun can be set through other parameters */ + /* refer to description of parameter "EOCSelection" for more */ + /* details. */ + + /* Set ADC error code to overrun */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); + + /* Clear ADC overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Clear the Overrun flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); + } +} + +/** + * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + __IO uint32_t counter = 0U; + ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(counter != 0U) + { + counter--; + } + } + + /* Check ADC DMA Mode */ + /* - disable the DMA Mode if it is already enabled */ + if((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA) + { + CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable ADC DMA mode */ + hadc->Instance->CR2 |= ADC_CR2_DMA; + + /* Start the DMA channel */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + { +#if defined(ADC2) && defined(ADC3) + if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + { +#endif /* ADC2 || ADC3 */ + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } +#if defined(ADC2) && defined(ADC3) + } +#endif /* ADC2 || ADC3 */ + } + else + { + /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ + if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable the selected ADC DMA mode */ + hadc->Instance->CR2 &= ~ADC_CR2_DMA; + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) + { + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Check if DMA channel effectively disabled */ + if (tmp_hal_status != HAL_OK) + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); + } + } + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Gets the converted value from data register of regular channel. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval Converted value + */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) +{ + /* Return the selected ADC converted value */ + return hadc->Instance->DR; +} + +/** + * @brief Regular conversion complete callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ConvCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Regular conversion half DMA transfer callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ConvHalfCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Analog watchdog callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file + */ +} + +/** + * @brief Error ADC callback. + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". + * - If needed, restart a new ADC conversion using function + * "HAL_ADC_Start_DMA()" + * (this function is also clearing overrun flag) + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure regular channels. + (+) Configure injected channels. + (+) Configure multimode. + (+) Configure the analog watch dog. + +@endverbatim + * @{ + */ + + /** + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param sConfig ADC configuration structure. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +{ + __IO uint32_t counter = 0U; + ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_ADC_CHANNEL(sConfig->Channel)); + assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (sConfig->Channel > ADC_CHANNEL_9) + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); + + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Clear the old sample time */ + hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); + + /* Set the new sample time */ + hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); + } + + /* For Rank 1 to 6 */ + if (sConfig->Rank < 7U) + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); + } + /* For Rank 7 to 12 */ + else if (sConfig->Rank < 13U) + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); + } + /* For Rank 13 to 16 */ + else + { + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); + } + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */ + if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) + { + /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/ + if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT) + { + tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE; + } + /* Enable the VBAT channel*/ + tmpADC_Common->CCR |= ADC_CCR_VBATE; + } + + /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or + Channel_17 is selected for VREFINT enable TSVREFE */ + if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) + { + /* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/ + if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT) + { + tmpADC_Common->CCR &= ~ADC_CCR_VBATE; + } + /* Enable the Temperature sensor and VREFINT channel*/ + tmpADC_Common->CCR |= ADC_CCR_TSVREFE; + + if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) + { + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); + while(counter != 0U) + { + counter--; + } + } + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the analog watchdog. + * @note Analog watchdog thresholds can be modified while ADC conversion + * is on going. + * In this case, some constraints must be taken into account: + * The programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure + * that contains the configuration information of ADC analog watchdog. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ +#ifdef USE_FULL_ASSERT + uint32_t tmp = 0U; +#endif /* USE_FULL_ASSERT */ + + /* Check the parameters */ + assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + +#ifdef USE_FULL_ASSERT + tmp = ADC_GET_RESOLUTION(hadc); + assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); +#endif /* USE_FULL_ASSERT */ + + /* Process locked */ + __HAL_LOCK(hadc); + + if(AnalogWDGConfig->ITMode == ENABLE) + { + /* Enable the ADC Analog watchdog interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); + } + else + { + /* Disable the ADC Analog watchdog interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); + } + + /* Clear AWDEN, JAWDEN and AWDSGL bits */ + hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); + + /* Set the analog watchdog enable mode */ + hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; + + /* Set the high threshold */ + hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; + + /* Set the low threshold */ + hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; + + /* Clear the Analog watchdog channel select bits */ + hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; + + /* Set the Analog watchdog channel */ + hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions + * @brief ADC Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State and errors functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Check the ADC state + (+) Check the ADC Error + +@endverbatim + * @{ + */ + +/** + * @brief return the ADC state + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL state + */ +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +{ + /* Return ADC state */ + return hadc->State; +} + +/** + * @brief Return the ADC error code + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval ADC Error Code + */ +uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) +{ + return hadc->ErrorCode; +} + +/** + * @} + */ + +/** @addtogroup ADC_Private_Functions + * @{ + */ + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct without initializing the ADC MSP. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +static void ADC_Init(ADC_HandleTypeDef* hadc) +{ + ADC_Common_TypeDef *tmpADC_Common; + + /* Set ADC parameters */ + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* Set the ADC clock prescaler */ + tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE); + tmpADC_Common->CCR |= hadc->Init.ClockPrescaler; + + /* Set ADC scan mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); + hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); + + /* Set ADC resolution */ + hadc->Instance->CR1 &= ~(ADC_CR1_RES); + hadc->Instance->CR1 |= hadc->Init.Resolution; + + /* Set ADC data alignment */ + hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); + hadc->Instance->CR2 |= hadc->Init.DataAlign; + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + { + /* Select external trigger to start conversion */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; + + /* Select external trigger polarity */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); + hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); + } + + /* Enable or disable ADC continuous conversion mode */ + hadc->Instance->CR2 &= ~(ADC_CR2_CONT); + hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); + + if(hadc->Init.DiscontinuousConvMode != DISABLE) + { + assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); + + /* Enable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; + + /* Set the number of channels to be converted in discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); + hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); + } + else + { + /* Disable the selected ADC regular discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); + } + + /* Set ADC number of conversion */ + hadc->Instance->SQR1 &= ~(ADC_SQR1_L); + hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); + + /* Enable or disable ADC DMA continuous request */ + hadc->Instance->CR2 &= ~(ADC_CR2_DDS); + hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests); + + /* Enable or disable ADC end of conversion selection */ + hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); + hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); +} + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F4, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvCpltCallback(hadc); +#else + HAL_ADC_ConvCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else /* DMA and-or internal error occurred */ + { + if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) + { + /* Call HAL ADC Error Callback function */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Half conversion callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ConvHalfCpltCallback(hadc); +#else + HAL_ADC_ConvHalfCpltCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_DMAError(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hadc->State= HAL_ADC_STATE_ERROR_DMA; + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + /* Error callback */ +#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) + hadc->ErrorCallback(hadc); +#else + HAL_ADC_ErrorCallback(hadc); +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c new file mode 100644 index 0000000..c971e22 --- /dev/null +++ b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_adc_ex.c @@ -0,0 +1,1112 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_adc_ex.c + * @author MCD Application Team + * @brief This file provides firmware functions to manage the following + * functionalities of the ADC extension peripheral: + * + Extended features functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): + (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() + (##) ADC pins configuration + (+++) Enable the clock for the ADC GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE() + (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() + (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) + (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() + (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() + (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() + (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) + (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() + (+++) Configure and enable two DMA streams stream for managing data + transfer from peripheral to memory (output stream) + (+++) Associate the initialized DMA handle to the ADC DMA handle + using __HAL_LINKDMA() + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the two DMA Streams. The output stream should have higher + priority than the input stream. + (#) Configure the ADC Prescaler, conversion resolution and data alignment + using the HAL_ADC_Init() function. + + (#) Configure the ADC Injected channels group features, use HAL_ADC_Init() + and HAL_ADC_ConfigChannel() functions. + + (#) Three operation modes are available within this driver: + + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() + (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage + user can specify the value of timeout according to his end application + (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function. + (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop() + + *** Interrupt mode IO operation *** + =================================== + [..] + (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() + (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine + (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback + (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback + (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() + + *** Multi mode ADCs Regular channels configuration *** + ====================================================== + [..] + (+) Select the Multi mode ADC regular channels features (dual or triple mode) + and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. + (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function. + + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup ADCEx ADCEx + * @brief ADC Extended driver modules + * @{ + */ + +#ifdef HAL_ADC_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup ADCEx_Private_Functions + * @{ + */ +/* Private function prototypes -----------------------------------------------*/ +static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma); +static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADCEx_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Start conversion of injected channel. + (+) Stop conversion of injected channel. + (+) Start multimode and enable DMA transfer. + (+) Stop multimode and disable DMA transfer. + (+) Get result of injected channel conversion. + (+) Get result of multimode conversion. + (+) Configure injected channels. + (+) Configure multimode. + +@endverbatim + * @{ + */ + +/** + * @brief Enables the selected ADC software start conversion of the injected channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0U; + uint32_t tmp1 = 0U, tmp2 = 0U; + ADC_Common_TypeDef *tmpADC_Common; + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(counter != 0U) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + else + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if((hadc->Instance == ADC1) && tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables the interrupt and starts ADC conversion of injected channels. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +{ + __IO uint32_t counter = 0U; + uint32_t tmp1 = 0U, tmp2 = 0U; + ADC_Common_TypeDef *tmpADC_Common; + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Enable the ADC peripheral */ + + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for ADC stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(counter != 0U) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to injected group conversion results */ + /* - Set state bitfield related to injected operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, + HAL_ADC_STATE_INJ_BUSY); + + /* Check if a regular conversion is ongoing */ + /* Note: On this device, there is no ADC error code fields related to */ + /* conversions on group injected only. In case of conversion on */ + /* going on group regular, no error code is reset. */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Clear injected group conversion flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Enable end of conversion interrupt for injected channels */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* Check if Multimode enabled */ + if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if(tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + else + { + tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); + tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); + if((hadc->Instance == ADC1) && tmp1 && tmp2) + { + /* Enable the selected ADC software conversion for injected group */ + hadc->Instance->CR2 |= ADC_CR2_JSWSTART; + } + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop conversion of injected channels. Disable ADC peripheral if + * no regular conversion is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @note In case of auto-injection mode, HAL_ADC_Stop must be used. + * @param hadc ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Poll for injected conversion complete + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param Timeout Timeout value in millisecond. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +{ + uint32_t tickstart = 0U; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check End of conversion flag */ + while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + { + /* Check for the Timeout */ + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + { + /* New check to avoid false timeout detection in case of preemption */ + if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + { + hadc->State= HAL_ADC_STATE_TIMEOUT; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + return HAL_TIMEOUT; + } + } + } + } + + /* Clear injected group conversion flag */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); + + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); + + /* Determine whether any further conversion upcoming on group injected */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F4, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + { + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Return ADC state */ + return HAL_OK; +} + +/** + * @brief Stop conversion of injected channels, disable interruption of + * end-of-conversion. Disable ADC peripheral if no regular conversion + * is on going. + * @note If ADC must be disabled and if conversion is on going on + * regular group, function HAL_ADC_Stop must be used to stop both + * injected and regular groups, and disable the ADC. + * @note If injected group mode auto-injection is enabled, + * function HAL_ADC_Stop must be used. + * @param hadc ADC handle + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion and disable ADC peripheral */ + /* Conditioned to: */ + /* - No conversion on the other group (regular group) is intended to */ + /* continue (injected and regular groups stop conversion and ADC disable */ + /* are common) */ + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + { + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable ADC end of conversion interrupt for injected channels */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + + tmp_hal_status = HAL_ERROR; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Gets the converted value from data register of injected channel. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param InjectedRank the ADC injected rank. + * This parameter can be one of the following values: + * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected + * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected + * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected + * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected + * @retval None + */ +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +{ + __IO uint32_t tmp = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); + + /* Clear injected group conversion flag to have similar behaviour as */ + /* regular group: reading data register also clears end of conversion flag. */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); + + /* Return the selected ADC converted value */ + switch(InjectedRank) + { + case ADC_INJECTED_RANK_4: + { + tmp = hadc->Instance->JDR4; + } + break; + case ADC_INJECTED_RANK_3: + { + tmp = hadc->Instance->JDR3; + } + break; + case ADC_INJECTED_RANK_2: + { + tmp = hadc->Instance->JDR2; + } + break; + case ADC_INJECTED_RANK_1: + { + tmp = hadc->Instance->JDR1; + } + break; + default: + break; + } + return tmp; +} + +/** + * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral + * + * @note Caution: This function must be used only with the ADC master. + * + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. + * @param Length The length of data to be transferred from ADC peripheral to memory. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +{ + __IO uint32_t counter = 0U; + ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Check if ADC peripheral is disabled in order to enable it and wait during + Tstab time the ADC's stabilization */ + if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { + /* Enable the Peripheral */ + __HAL_ADC_ENABLE(hadc); + + /* Delay for temperature sensor stabilization time */ + /* Compute number of CPU cycles to wait for */ + counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); + while(counter != 0U) + { + counter--; + } + } + + /* Start conversion if ADC is effectively enabled */ + if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Set ADC state */ + /* - Clear state bitfield related to regular group conversion results */ + /* - Set state bitfield related to regular group operation */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, + HAL_ADC_STATE_REG_BUSY); + + /* If conversions on group regular are also triggering group injected, */ + /* update ADC state. */ + if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) + { + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + } + + /* State machine update: Check if an injected conversion is ongoing */ + if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + /* Reset ADC error code fields related to conversions on group regular */ + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + } + else + { + /* Reset ADC all error code fields */ + ADC_CLEAR_ERRORCODE(hadc); + } + + /* Process unlocked */ + /* Unlock before starting ADC conversions: in case of potential */ + /* interruption, to let the process to ADC IRQ Handler. */ + __HAL_UNLOCK(hadc); + + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ + /* start (in case of SW start): */ + + /* Clear regular group conversion flag and overrun flag */ + /* (To ensure of no unknown state from potential previous ADC operations) */ + __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + if (hadc->Init.DMAContinuousRequests != DISABLE) + { + /* Enable the selected ADC DMA request after last transfer */ + tmpADC_Common->CCR |= ADC_CCR_DDS; + } + else + { + /* Disable the selected ADC EOC rising on each regular channel conversion */ + tmpADC_Common->CCR &= ~ADC_CCR_DDS; + } + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); + + /* if no external trigger present enable software conversion of regular channels */ + if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + { + /* Enable the selected ADC software conversion for regular group */ + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + } + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC IP internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + } + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) +{ + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Stop potential conversion on going, on regular and injected groups */ + /* Disable ADC peripheral */ + __HAL_ADC_DISABLE(hadc); + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* Check if ADC is effectively disabled */ + if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + { + /* Disable the selected ADC DMA mode for multimode */ + tmpADC_Common->CCR &= ~ADC_CCR_DDS; + + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ + /* DMA transfer is on going) */ + tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); + + /* Disable ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); + + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, + HAL_ADC_STATE_READY); + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return tmp_hal_status; +} + +/** + * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results + * data in the selected multi mode. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval The converted data value. + */ +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) +{ + ADC_Common_TypeDef *tmpADC_Common; + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* Return the multi mode conversion value */ + return tmpADC_Common->CDR; +} + +/** + * @brief Injected conversion complete callback in non blocking mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @retval None + */ +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hadc); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param sConfigInjected ADC configuration structure for injected channel. + * @retval None + */ +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +{ + +#ifdef USE_FULL_ASSERT + uint32_t tmp = 0U; + +#endif /* USE_FULL_ASSERT */ + + ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); + assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); + assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); + assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); + assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); + assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); + +#ifdef USE_FULL_ASSERT + tmp = ADC_GET_RESOLUTION(hadc); + assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); +#endif /* USE_FULL_ASSERT */ + + if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); + } + + /* Process locked */ + __HAL_LOCK(hadc); + + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ + if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) + { + /* Clear the old sample time */ + hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); + + /* Set the new sample time */ + hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); + } + else /* ADC_Channel include in ADC_Channel_[0..9] */ + { + /* Clear the old sample time */ + hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); + + /* Set the new sample time */ + hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); + } + + /*---------------------------- ADCx JSQR Configuration -----------------*/ + hadc->Instance->JSQR &= ~(ADC_JSQR_JL); + hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); + + /* Rank configuration */ + + /* Clear the old SQx bits for the selected rank */ + hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + + /* Set the SQx bits for the selected rank */ + hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { + /* Select external trigger to start conversion */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; + + /* Select external trigger polarity */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; + } + else + { + /* Reset the external trigger */ + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + } + + if (sConfigInjected->AutoInjectedConv != DISABLE) + { + /* Enable the selected ADC automatic injected group conversion */ + hadc->Instance->CR1 |= ADC_CR1_JAUTO; + } + else + { + /* Disable the selected ADC automatic injected group conversion */ + hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); + } + + if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) + { + /* Enable the selected ADC injected discontinuous mode */ + hadc->Instance->CR1 |= ADC_CR1_JDISCEN; + } + else + { + /* Disable the selected ADC injected discontinuous mode */ + hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); + } + + switch(sConfigInjected->InjectedRank) + { + case 1U: + /* Set injected channel 1 offset */ + hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); + hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; + break; + case 2U: + /* Set injected channel 2 offset */ + hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); + hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; + break; + case 3U: + /* Set injected channel 3 offset */ + hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); + hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; + break; + default: + /* Set injected channel 4 offset */ + hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); + hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; + break; + } + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* if ADC1 Channel_18 is selected enable VBAT Channel */ + if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) + { + /* Enable the VBAT channel*/ + tmpADC_Common->CCR |= ADC_CCR_VBATE; + } + + /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ + if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) + { + /* Enable the TSVREFE channel*/ + tmpADC_Common->CCR |= ADC_CCR_TSVREFE; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Configures the ADC multi-mode + * @param hadc pointer to a ADC_HandleTypeDef structure that contains + * the configuration information for the specified ADC. + * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains + * the configuration information for multimode. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +{ + + ADC_Common_TypeDef *tmpADC_Common; + + /* Check the parameters */ + assert_param(IS_ADC_MODE(multimode->Mode)); + assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); + assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); + + /* Process locked */ + __HAL_LOCK(hadc); + + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); + + /* Set ADC mode */ + tmpADC_Common->CCR &= ~(ADC_CCR_MULTI); + tmpADC_Common->CCR |= multimode->Mode; + + /* Set the ADC DMA access mode */ + tmpADC_Common->CCR &= ~(ADC_CCR_DMA); + tmpADC_Common->CCR |= multimode->DMAAccessMode; + + /* Set delay between two sampling phases */ + tmpADC_Common->CCR &= ~(ADC_CCR_DELAY); + tmpADC_Common->CCR |= multimode->TwoSamplingDelay; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** + * @brief DMA transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) +{ + /* Retrieve ADC handle corresponding to current DMA handle */ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Update state machine on conversion status if not in error state */ + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) + { + /* Update ADC state machine */ + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + + /* Determine whether any further conversion upcoming on group regular */ + /* by external trigger, continuous mode or scan sequence on going. */ + /* Note: On STM32F4, there is no independent flag of end of sequence. */ + /* The test of scan sequence on going is done either with scan */ + /* sequence disabled or with end of conversion flag set to */ + /* of end of sequence. */ + if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + { + /* Disable ADC end of single conversion interrupt on group regular */ + /* Note: Overrun interrupt was enabled with EOC interrupt in */ + /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ + /* by overrun IRQ process below. */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + + /* Set ADC state */ + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) + { + SET_BIT(hadc->State, HAL_ADC_STATE_READY); + } + } + + /* Conversion complete callback */ + HAL_ADC_ConvCpltCallback(hadc); + } + else + { + /* Call DMA error callback */ + hadc->DMA_Handle->XferErrorCallback(hdma); + } +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); +} + +/** + * @brief DMA error callback + * @param hdma pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) +{ + ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hadc->State= HAL_ADC_STATE_ERROR_DMA; + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + HAL_ADC_ErrorCallback(hadc); +} + +/** + * @} + */ + +#endif /* HAL_ADC_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c new file mode 100644 index 0000000..5f880ff --- /dev/null +++ b/access_control_stm32/Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_ll_adc.c @@ -0,0 +1,922 @@ +/** + ****************************************************************************** + * @file stm32f4xx_ll_adc.c + * @author MCD Application Team + * @brief ADC LL module driver + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_ll_adc.h" +#include "stm32f4xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT + #include "stm32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup STM32F4xx_LL_Driver + * @{ + */ + +#if defined (ADC1) || defined (ADC2) || defined (ADC3) + +/** @addtogroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup ADC_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* common to several ADC instances. */ +#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ + ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC instance. */ +#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ + ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ + ) + +#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ + ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ + ) + +#define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ + ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ + || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ + ) + +#define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ + ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ + || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group regular */ +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH2) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_CH3) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ + ) +#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ + ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ + ) + +#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ + ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ + ) + +#define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ + ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ + || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ + ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ + || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ + ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group injected */ +#define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ + ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH3) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \ + || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ + ) + +#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ + ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ + || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ + || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ + ) + +#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ + ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ + || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ + ) + +#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ + ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ + || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ + ) + +#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ + ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ + || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ + ) + +#if defined(ADC_MULTIMODE_SUPPORT) +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* multimode. */ +#if defined(ADC3) +#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ + ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \ + ) +#else +#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \ + ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \ + || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \ + ) +#endif + +#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \ + ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \ + || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \ + ) + +#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \ + ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \ + || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \ + ) + +#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \ + ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \ + || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \ + ) + +#endif /* ADC_MULTIMODE_SUPPORT */ +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of all ADC instances belonging to + * the same ADC common instance to their default reset values. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + + + /* Force reset of ADC clock (core clock) */ + LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); + + /* Release reset of ADC clock (core clock) */ + LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); + + return SUCCESS; +} + +/** + * @brief Initialize some features of ADC common parameters + * (all ADC instances belonging to the same ADC common instance) + * and multimode (for devices with several ADC instances available). + * @note The setting of ADC common parameters is conditioned to + * ADC instances state: + * All ADC instances belonging to the same ADC common instance + * must be disabled. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are initialized + * - ERROR: ADC common registers are not initialized + */ +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); + +#if defined(ADC_MULTIMODE_SUPPORT) + assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); + if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + { + assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); + assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); + } +#endif /* ADC_MULTIMODE_SUPPORT */ + + /* Note: Hardware constraint (refer to description of functions */ + /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */ + /* On this STM32 series, setting of these features is conditioned to */ + /* ADC state: */ + /* All ADC instances of the ADC common group must be disabled. */ + if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - common to several ADC */ + /* (all ADC instances belonging to the same ADC common instance) */ + /* - Set ADC clock (conversion clock) */ + /* - multimode (if several ADC instances available on the */ + /* selected device) */ + /* - Set ADC multimode configuration */ + /* - Set ADC multimode DMA transfer */ + /* - Set ADC multimode: delay between 2 sampling phases */ +#if defined(ADC_MULTIMODE_SUPPORT) + if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + { + MODIFY_REG(ADCxy_COMMON->CCR, + ADC_CCR_ADCPRE + | ADC_CCR_MULTI + | ADC_CCR_DMA + | ADC_CCR_DDS + | ADC_CCR_DELAY + , + ADC_CommonInitStruct->CommonClock + | ADC_CommonInitStruct->Multimode + | ADC_CommonInitStruct->MultiDMATransfer + | ADC_CommonInitStruct->MultiTwoSamplingDelay + ); + } + else + { + MODIFY_REG(ADCxy_COMMON->CCR, + ADC_CCR_ADCPRE + | ADC_CCR_MULTI + | ADC_CCR_DMA + | ADC_CCR_DDS + | ADC_CCR_DELAY + , + ADC_CommonInitStruct->CommonClock + | LL_ADC_MULTI_INDEPENDENT + ); + } +#else + LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); +#endif + } + else + { + /* Initialization error: One or several ADC instances belonging to */ + /* the same ADC common instance are not disabled. */ + status = ERROR; + } + + return status; +} + +/** + * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. + * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) +{ + /* Set ADC_CommonInitStruct fields to default values */ + /* Set fields of ADC common */ + /* (all ADC instances belonging to the same ADC common instance) */ + ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + +#if defined(ADC_MULTIMODE_SUPPORT) + /* Set fields of ADC multimode */ + ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; + ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; + ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; +#endif /* ADC_MULTIMODE_SUPPORT */ +} + +/** + * @brief De-initialize registers of the selected ADC instance + * to their default reset values. + * @note To reset all ADC instances quickly (perform a hard reset), + * use function @ref LL_ADC_CommonDeInit(). + * @param ADCx ADC instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are de-initialized + * - ERROR: ADC registers are not de-initialized + */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + /* Disable ADC instance if not already disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 1UL) + { + /* Set ADC group regular trigger source to SW start to ensure to not */ + /* have an external trigger event occurring during the conversion stop */ + /* ADC disable process. */ + LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); + + /* Set ADC group injected trigger source to SW start to ensure to not */ + /* have an external trigger event occurring during the conversion stop */ + /* ADC disable process. */ + LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); + + /* Disable the ADC instance */ + LL_ADC_Disable(ADCx); + } + + /* Check whether ADC state is compliant with expected state */ + /* (hardware requirements of bits state to reset registers below) */ + if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) + { + /* ========== Reset ADC registers ========== */ + /* Reset register SR */ + CLEAR_BIT(ADCx->SR, + ( LL_ADC_FLAG_STRT + | LL_ADC_FLAG_JSTRT + | LL_ADC_FLAG_EOCS + | LL_ADC_FLAG_OVR + | LL_ADC_FLAG_JEOS + | LL_ADC_FLAG_AWD1 ) + ); + + /* Reset register CR1 */ + CLEAR_BIT(ADCx->CR1, + ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN + | ADC_CR1_JAWDEN + | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN + | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN + | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE + | ADC_CR1_AWDCH ) + ); + + /* Reset register CR2 */ + CLEAR_BIT(ADCx->CR2, + ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL + | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL + | ADC_CR2_ALIGN | ADC_CR2_EOCS + | ADC_CR2_DDS | ADC_CR2_DMA + | ADC_CR2_CONT | ADC_CR2_ADON ) + ); + + /* Reset register SMPR1 */ + CLEAR_BIT(ADCx->SMPR1, + ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 + | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 + | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) + ); + + /* Reset register SMPR2 */ + CLEAR_BIT(ADCx->SMPR2, + ( ADC_SMPR2_SMP9 + | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 + | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 + | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) + ); + + /* Reset register JOFR1 */ + CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); + /* Reset register JOFR2 */ + CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); + /* Reset register JOFR3 */ + CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); + /* Reset register JOFR4 */ + CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); + + /* Reset register HTR */ + SET_BIT(ADCx->HTR, ADC_HTR_HT); + /* Reset register LTR */ + CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); + + /* Reset register SQR1 */ + CLEAR_BIT(ADCx->SQR1, + ( ADC_SQR1_L + | ADC_SQR1_SQ16 + | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) + ); + + /* Reset register SQR2 */ + CLEAR_BIT(ADCx->SQR2, + ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 + | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) + ); + + /* Reset register SQR3 */ + CLEAR_BIT(ADCx->SQR3, + ( ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 + | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) + ); + + /* Reset register JSQR */ + CLEAR_BIT(ADCx->JSQR, + ( ADC_JSQR_JL + | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) + ); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ + /* bits in access mode read only, no direct reset applicable */ + + /* Reset register CCR */ + CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); + } + + return status; +} + +/** + * @brief Initialize some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Affects both group regular and group injected (availability + * of ADC group injected depends on STM32 families). + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, some other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular or group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); + assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC instance */ + /* - Set ADC data resolution */ + /* - Set ADC conversion data alignment */ + MODIFY_REG(ADCx->CR1, + ADC_CR1_RES + | ADC_CR1_SCAN + , + ADC_InitStruct->Resolution + | ADC_InitStruct->SequencersScanMode + ); + + MODIFY_REG(ADCx->CR2, + ADC_CR2_ALIGN + , + ADC_InitStruct->DataAlignment + ); + + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_InitTypeDef field to default value. + * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) +{ + /* Set ADC_InitStruct fields to default values */ + /* Set fields of ADC instance */ + ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + + /* Enable scan mode to have a generic behavior with ADC of other */ + /* STM32 families, without this setting available: */ + /* ADC group regular sequencer and ADC group injected sequencer depend */ + /* only of their own configuration. */ + ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; + +} + +/** + * @brief Initialize some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular or group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); + if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + } + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); + + /* ADC group regular continuous mode and discontinuous mode */ + /* can not be enabled simultenaeously */ + assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) + || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group regular */ + /* - Set ADC group regular trigger source */ + /* - Set ADC group regular sequencer length */ + /* - Set ADC group regular sequencer discontinuous mode */ + /* - Set ADC group regular continuous mode */ + /* - Set ADC group regular conversion data transfer: no transfer or */ + /* transfer by DMA, and DMA requests mode */ + /* Note: On this STM32 series, ADC trigger edge is set when starting */ + /* ADC conversion. */ + /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ + if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_DISCEN + | ADC_CR1_DISCNUM + , + ADC_REG_InitStruct->SequencerDiscont + ); + } + else + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_DISCEN + | ADC_CR1_DISCNUM + , + LL_ADC_REG_SEQ_DISCONT_DISABLE + ); + } + + MODIFY_REG(ADCx->CR2, + ADC_CR2_EXTSEL + | ADC_CR2_EXTEN + | ADC_CR2_CONT + | ADC_CR2_DMA + | ADC_CR2_DDS + , + (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) + | ADC_REG_InitStruct->ContinuousMode + | ADC_REG_InitStruct->DMATransfer + ); + + /* Set ADC group regular sequencer length and scan direction */ + /* Note: Hardware constraint (refer to description of this function): */ + /* Note: If ADC instance feature scan mode is disabled */ + /* (refer to ADC instance initialization structure */ + /* parameter @ref SequencersScanMode */ + /* or function @ref LL_ADC_SetSequencersScanMode() ), */ + /* this parameter is discarded. */ + LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + /* Set ADC_REG_InitStruct fields to default values */ + /* Set fields of ADC group regular */ + /* Note: On this STM32 series, ADC trigger edge is set when starting */ + /* ADC conversion. */ + /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ + ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; + ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; + ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; +} + +/** + * @brief Initialize some features of ADC group injected. + * @note These parameters have an impact on ADC scope: ADC group injected. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "INJ"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all STM32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group injected sequencer: + * map channel on the selected sequencer rank. + * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); + if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + { + assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); + } + assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0UL) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group injected */ + /* - Set ADC group injected trigger source */ + /* - Set ADC group injected sequencer length */ + /* - Set ADC group injected sequencer discontinuous mode */ + /* - Set ADC group injected conversion trigger: independent or */ + /* from ADC group regular */ + /* Note: On this STM32 series, ADC trigger edge is set when starting */ + /* ADC conversion. */ + /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ + if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_JDISCEN + | ADC_CR1_JAUTO + , + ADC_INJ_InitStruct->SequencerDiscont + | ADC_INJ_InitStruct->TrigAuto + ); + } + else + { + MODIFY_REG(ADCx->CR1, + ADC_CR1_JDISCEN + | ADC_CR1_JAUTO + , + LL_ADC_REG_SEQ_DISCONT_DISABLE + | ADC_INJ_InitStruct->TrigAuto + ); + } + + MODIFY_REG(ADCx->CR2, + ADC_CR2_JEXTSEL + | ADC_CR2_JEXTEN + , + (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) + ); + + /* Note: Hardware constraint (refer to description of this function): */ + /* Note: If ADC instance feature scan mode is disabled */ + /* (refer to ADC instance initialization structure */ + /* parameter @ref SequencersScanMode */ + /* or function @ref LL_ADC_SetSequencersScanMode() ), */ + /* this parameter is discarded. */ + LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. + * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) +{ + /* Set ADC_INJ_InitStruct fields to default values */ + /* Set fields of ADC group injected */ + ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; + ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; + ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; + ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 || ADC2 || ADC3 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + diff --git a/access_control_stm32/access_control_stm32.ioc b/access_control_stm32/access_control_stm32.ioc index d00997f..5e4b480 100644 --- a/access_control_stm32/access_control_stm32.ioc +++ b/access_control_stm32/access_control_stm32.ioc @@ -1,45 +1,55 @@ #MicroXplorer Configuration settings - do not modify +ADC1.Channel-1\#ChannelRegularConversion=ADC_CHANNEL_1 +ADC1.ContinuousConvMode=DISABLE +ADC1.IPParameters=Rank-1\#ChannelRegularConversion,master,Channel-1\#ChannelRegularConversion,SamplingTime-1\#ChannelRegularConversion,NbrOfConversionFlag,ContinuousConvMode +ADC1.NbrOfConversionFlag=1 +ADC1.Rank-1\#ChannelRegularConversion=1 +ADC1.SamplingTime-1\#ChannelRegularConversion=ADC_SAMPLETIME_3CYCLES +ADC1.master=1 CAD.formats= CAD.pinconfig= CAD.provider= FREERTOS.FootprintOK=true FREERTOS.IPParameters=Tasks01,configUSE_NEWLIB_REENTRANT,FootprintOK -FREERTOS.Tasks01=mainTask,24,128,StartMainTask,Default,NULL,Dynamic,NULL,NULL;doorHandler,8,128,startDoorHandleTask,Default,NULL,Dynamic,NULL,NULL +FREERTOS.Tasks01=mainTask,24,128,StartMainTask,Default,NULL,Dynamic,NULL,NULL;doorHandler,40,128,startDoorHandleTask,Default,NULL,Dynamic,NULL,NULL;StateSendTask,8,128,StartStateSendTask,Default,NULL,Dynamic,NULL,NULL;ADCReqTask,8,128,StartADCReqTask,Default,NULL,Dynamic,NULL,NULL FREERTOS.configUSE_NEWLIB_REENTRANT=1 File.Version=6 GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false Mcu.CPN=STM32F411RET6 Mcu.Family=STM32F4 -Mcu.IP0=FREERTOS -Mcu.IP1=NVIC -Mcu.IP2=RCC -Mcu.IP3=SYS -Mcu.IP4=USART2 -Mcu.IPNb=5 +Mcu.IP0=ADC1 +Mcu.IP1=FREERTOS +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SYS +Mcu.IP5=USART2 +Mcu.IPNb=6 Mcu.Name=STM32F411R(C-E)Tx Mcu.Package=LQFP64 Mcu.Pin0=PC13-ANTI_TAMP Mcu.Pin1=PC14-OSC32_IN -Mcu.Pin10=PA13 -Mcu.Pin11=PA14 -Mcu.Pin12=PB3 -Mcu.Pin13=VP_FREERTOS_VS_CMSIS_V2 -Mcu.Pin14=VP_SYS_VS_tim1 +Mcu.Pin10=PA9 +Mcu.Pin11=PA13 +Mcu.Pin12=PA14 +Mcu.Pin13=PB3 +Mcu.Pin14=VP_FREERTOS_VS_CMSIS_V2 +Mcu.Pin15=VP_SYS_VS_tim1 Mcu.Pin2=PC15-OSC32_OUT Mcu.Pin3=PH0 - OSC_IN Mcu.Pin4=PH1 - OSC_OUT -Mcu.Pin5=PA2 -Mcu.Pin6=PA3 -Mcu.Pin7=PA5 -Mcu.Pin8=PA7 -Mcu.Pin9=PA9 -Mcu.PinsNb=15 +Mcu.Pin5=PA1 +Mcu.Pin6=PA2 +Mcu.Pin7=PA3 +Mcu.Pin8=PA5 +Mcu.Pin9=PA7 +Mcu.PinsNb=16 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F411RETx MxCube.Version=6.9.1 MxDb.Version=DB.6.0.91 +NVIC.ADC_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false\:false NVIC.ForceEnableDMAVector=true @@ -57,6 +67,8 @@ NVIC.TIM1_UP_TIM10_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:tru NVIC.TimeBase=TIM1_UP_TIM10_IRQn NVIC.TimeBaseIP=TIM1 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:false\:false +PA1.Locked=true +PA1.Signal=ADCx_IN1 PA13.GPIOParameters=GPIO_Label PA13.GPIO_Label=TMS PA13.Locked=true @@ -142,7 +154,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART2_UART_Init-USART2-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART2_UART_Init-USART2-false-HAL-true,4-MX_ADC1_Init-ADC1-false-HAL-true RCC.48MHZClocksFreq_Value=84000000 RCC.AHBFreq_Value=84000000 RCC.APB1CLKDivider=RCC_HCLK_DIV2 @@ -175,6 +187,8 @@ RCC.VCOInputFreq_Value=1000000 RCC.VCOInputMFreq_Value=1000000 RCC.VCOOutputFreq_Value=336000000 RCC.VcooutputI2S=96000000 +SH.ADCx_IN1.0=ADC1_IN1,IN1 +SH.ADCx_IN1.ConfNb=1 SH.GPXTI13.0=GPIO_EXTI13 SH.GPXTI13.ConfNb=1 USART2.BaudRate=9600