
access_control_stm32.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   00000198  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         000060d8  080001a0  080001a0  000101a0  2**4
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       000000f4  08006278  08006278  00016278  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  0800636c  0800636c  00020060  2**0
                  CONTENTS
  4 .ARM          00000008  0800636c  0800636c  0001636c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  5 .preinit_array 00000000  08006374  08006374  00020060  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08006374  08006374  00016374  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  08006378  08006378  00016378  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         00000060  20000000  0800637c  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00004c44  20000060  080063dc  00020060  2**2
                  ALLOC
 10 ._user_heap_stack 00003004  20004ca4  080063dc  00024ca4  2**0
                  ALLOC
 11 .ARM.attributes 00000030  00000000  00000000  00020060  2**0
                  CONTENTS, READONLY
 12 .comment      00000043  00000000  00000000  00020090  2**0
                  CONTENTS, READONLY
 13 .debug_info   000197ff  00000000  00000000  000200d3  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_abbrev 000035e1  00000000  00000000  000398d2  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_aranges 00001540  00000000  00000000  0003ceb8  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_rnglists 00001092  00000000  00000000  0003e3f8  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_macro  00003b4c  00000000  00000000  0003f48a  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_line   00017e7d  00000000  00000000  00042fd6  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .debug_str    000a45a6  00000000  00000000  0005ae53  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 20 .debug_frame  00005cd8  00000000  00000000  000ff3fc  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 21 .debug_line_str 00000059  00000000  00000000  001050d4  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

080001a0 <__do_global_dtors_aux>:
 80001a0:	b510      	push	{r4, lr}
 80001a2:	4c05      	ldr	r4, [pc, #20]	; (80001b8 <__do_global_dtors_aux+0x18>)
 80001a4:	7823      	ldrb	r3, [r4, #0]
 80001a6:	b933      	cbnz	r3, 80001b6 <__do_global_dtors_aux+0x16>
 80001a8:	4b04      	ldr	r3, [pc, #16]	; (80001bc <__do_global_dtors_aux+0x1c>)
 80001aa:	b113      	cbz	r3, 80001b2 <__do_global_dtors_aux+0x12>
 80001ac:	4804      	ldr	r0, [pc, #16]	; (80001c0 <__do_global_dtors_aux+0x20>)
 80001ae:	f3af 8000 	nop.w
 80001b2:	2301      	movs	r3, #1
 80001b4:	7023      	strb	r3, [r4, #0]
 80001b6:	bd10      	pop	{r4, pc}
 80001b8:	20000060 	.word	0x20000060
 80001bc:	00000000 	.word	0x00000000
 80001c0:	08006260 	.word	0x08006260

080001c4 <frame_dummy>:
 80001c4:	b508      	push	{r3, lr}
 80001c6:	4b03      	ldr	r3, [pc, #12]	; (80001d4 <frame_dummy+0x10>)
 80001c8:	b11b      	cbz	r3, 80001d2 <frame_dummy+0xe>
 80001ca:	4903      	ldr	r1, [pc, #12]	; (80001d8 <frame_dummy+0x14>)
 80001cc:	4803      	ldr	r0, [pc, #12]	; (80001dc <frame_dummy+0x18>)
 80001ce:	f3af 8000 	nop.w
 80001d2:	bd08      	pop	{r3, pc}
 80001d4:	00000000 	.word	0x00000000
 80001d8:	20000064 	.word	0x20000064
 80001dc:	08006260 	.word	0x08006260

080001e0 <__aeabi_uldivmod>:
 80001e0:	b953      	cbnz	r3, 80001f8 <__aeabi_uldivmod+0x18>
 80001e2:	b94a      	cbnz	r2, 80001f8 <__aeabi_uldivmod+0x18>
 80001e4:	2900      	cmp	r1, #0
 80001e6:	bf08      	it	eq
 80001e8:	2800      	cmpeq	r0, #0
 80001ea:	bf1c      	itt	ne
 80001ec:	f04f 31ff 	movne.w	r1, #4294967295
 80001f0:	f04f 30ff 	movne.w	r0, #4294967295
 80001f4:	f000 b970 	b.w	80004d8 <__aeabi_idiv0>
 80001f8:	f1ad 0c08 	sub.w	ip, sp, #8
 80001fc:	e96d ce04 	strd	ip, lr, [sp, #-16]!
 8000200:	f000 f806 	bl	8000210 <__udivmoddi4>
 8000204:	f8dd e004 	ldr.w	lr, [sp, #4]
 8000208:	e9dd 2302 	ldrd	r2, r3, [sp, #8]
 800020c:	b004      	add	sp, #16
 800020e:	4770      	bx	lr

08000210 <__udivmoddi4>:
 8000210:	e92d 47f0 	stmdb	sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
 8000214:	9e08      	ldr	r6, [sp, #32]
 8000216:	460d      	mov	r5, r1
 8000218:	4604      	mov	r4, r0
 800021a:	460f      	mov	r7, r1
 800021c:	2b00      	cmp	r3, #0
 800021e:	d14a      	bne.n	80002b6 <__udivmoddi4+0xa6>
 8000220:	428a      	cmp	r2, r1
 8000222:	4694      	mov	ip, r2
 8000224:	d965      	bls.n	80002f2 <__udivmoddi4+0xe2>
 8000226:	fab2 f382 	clz	r3, r2
 800022a:	b143      	cbz	r3, 800023e <__udivmoddi4+0x2e>
 800022c:	fa02 fc03 	lsl.w	ip, r2, r3
 8000230:	f1c3 0220 	rsb	r2, r3, #32
 8000234:	409f      	lsls	r7, r3
 8000236:	fa20 f202 	lsr.w	r2, r0, r2
 800023a:	4317      	orrs	r7, r2
 800023c:	409c      	lsls	r4, r3
 800023e:	ea4f 4e1c 	mov.w	lr, ip, lsr #16
 8000242:	fa1f f58c 	uxth.w	r5, ip
 8000246:	fbb7 f1fe 	udiv	r1, r7, lr
 800024a:	0c22      	lsrs	r2, r4, #16
 800024c:	fb0e 7711 	mls	r7, lr, r1, r7
 8000250:	ea42 4207 	orr.w	r2, r2, r7, lsl #16
 8000254:	fb01 f005 	mul.w	r0, r1, r5
 8000258:	4290      	cmp	r0, r2
 800025a:	d90a      	bls.n	8000272 <__udivmoddi4+0x62>
 800025c:	eb1c 0202 	adds.w	r2, ip, r2
 8000260:	f101 37ff 	add.w	r7, r1, #4294967295
 8000264:	f080 811c 	bcs.w	80004a0 <__udivmoddi4+0x290>
 8000268:	4290      	cmp	r0, r2
 800026a:	f240 8119 	bls.w	80004a0 <__udivmoddi4+0x290>
 800026e:	3902      	subs	r1, #2
 8000270:	4462      	add	r2, ip
 8000272:	1a12      	subs	r2, r2, r0
 8000274:	b2a4      	uxth	r4, r4
 8000276:	fbb2 f0fe 	udiv	r0, r2, lr
 800027a:	fb0e 2210 	mls	r2, lr, r0, r2
 800027e:	ea44 4402 	orr.w	r4, r4, r2, lsl #16
 8000282:	fb00 f505 	mul.w	r5, r0, r5
 8000286:	42a5      	cmp	r5, r4
 8000288:	d90a      	bls.n	80002a0 <__udivmoddi4+0x90>
 800028a:	eb1c 0404 	adds.w	r4, ip, r4
 800028e:	f100 32ff 	add.w	r2, r0, #4294967295
 8000292:	f080 8107 	bcs.w	80004a4 <__udivmoddi4+0x294>
 8000296:	42a5      	cmp	r5, r4
 8000298:	f240 8104 	bls.w	80004a4 <__udivmoddi4+0x294>
 800029c:	4464      	add	r4, ip
 800029e:	3802      	subs	r0, #2
 80002a0:	ea40 4001 	orr.w	r0, r0, r1, lsl #16
 80002a4:	1b64      	subs	r4, r4, r5
 80002a6:	2100      	movs	r1, #0
 80002a8:	b11e      	cbz	r6, 80002b2 <__udivmoddi4+0xa2>
 80002aa:	40dc      	lsrs	r4, r3
 80002ac:	2300      	movs	r3, #0
 80002ae:	e9c6 4300 	strd	r4, r3, [r6]
 80002b2:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002b6:	428b      	cmp	r3, r1
 80002b8:	d908      	bls.n	80002cc <__udivmoddi4+0xbc>
 80002ba:	2e00      	cmp	r6, #0
 80002bc:	f000 80ed 	beq.w	800049a <__udivmoddi4+0x28a>
 80002c0:	2100      	movs	r1, #0
 80002c2:	e9c6 0500 	strd	r0, r5, [r6]
 80002c6:	4608      	mov	r0, r1
 80002c8:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 80002cc:	fab3 f183 	clz	r1, r3
 80002d0:	2900      	cmp	r1, #0
 80002d2:	d149      	bne.n	8000368 <__udivmoddi4+0x158>
 80002d4:	42ab      	cmp	r3, r5
 80002d6:	d302      	bcc.n	80002de <__udivmoddi4+0xce>
 80002d8:	4282      	cmp	r2, r0
 80002da:	f200 80f8 	bhi.w	80004ce <__udivmoddi4+0x2be>
 80002de:	1a84      	subs	r4, r0, r2
 80002e0:	eb65 0203 	sbc.w	r2, r5, r3
 80002e4:	2001      	movs	r0, #1
 80002e6:	4617      	mov	r7, r2
 80002e8:	2e00      	cmp	r6, #0
 80002ea:	d0e2      	beq.n	80002b2 <__udivmoddi4+0xa2>
 80002ec:	e9c6 4700 	strd	r4, r7, [r6]
 80002f0:	e7df      	b.n	80002b2 <__udivmoddi4+0xa2>
 80002f2:	b902      	cbnz	r2, 80002f6 <__udivmoddi4+0xe6>
 80002f4:	deff      	udf	#255	; 0xff
 80002f6:	fab2 f382 	clz	r3, r2
 80002fa:	2b00      	cmp	r3, #0
 80002fc:	f040 8090 	bne.w	8000420 <__udivmoddi4+0x210>
 8000300:	1a8a      	subs	r2, r1, r2
 8000302:	ea4f 471c 	mov.w	r7, ip, lsr #16
 8000306:	fa1f fe8c 	uxth.w	lr, ip
 800030a:	2101      	movs	r1, #1
 800030c:	fbb2 f5f7 	udiv	r5, r2, r7
 8000310:	fb07 2015 	mls	r0, r7, r5, r2
 8000314:	0c22      	lsrs	r2, r4, #16
 8000316:	ea42 4200 	orr.w	r2, r2, r0, lsl #16
 800031a:	fb0e f005 	mul.w	r0, lr, r5
 800031e:	4290      	cmp	r0, r2
 8000320:	d908      	bls.n	8000334 <__udivmoddi4+0x124>
 8000322:	eb1c 0202 	adds.w	r2, ip, r2
 8000326:	f105 38ff 	add.w	r8, r5, #4294967295
 800032a:	d202      	bcs.n	8000332 <__udivmoddi4+0x122>
 800032c:	4290      	cmp	r0, r2
 800032e:	f200 80cb 	bhi.w	80004c8 <__udivmoddi4+0x2b8>
 8000332:	4645      	mov	r5, r8
 8000334:	1a12      	subs	r2, r2, r0
 8000336:	b2a4      	uxth	r4, r4
 8000338:	fbb2 f0f7 	udiv	r0, r2, r7
 800033c:	fb07 2210 	mls	r2, r7, r0, r2
 8000340:	ea44 4402 	orr.w	r4, r4, r2, lsl #16
 8000344:	fb0e fe00 	mul.w	lr, lr, r0
 8000348:	45a6      	cmp	lr, r4
 800034a:	d908      	bls.n	800035e <__udivmoddi4+0x14e>
 800034c:	eb1c 0404 	adds.w	r4, ip, r4
 8000350:	f100 32ff 	add.w	r2, r0, #4294967295
 8000354:	d202      	bcs.n	800035c <__udivmoddi4+0x14c>
 8000356:	45a6      	cmp	lr, r4
 8000358:	f200 80bb 	bhi.w	80004d2 <__udivmoddi4+0x2c2>
 800035c:	4610      	mov	r0, r2
 800035e:	eba4 040e 	sub.w	r4, r4, lr
 8000362:	ea40 4005 	orr.w	r0, r0, r5, lsl #16
 8000366:	e79f      	b.n	80002a8 <__udivmoddi4+0x98>
 8000368:	f1c1 0720 	rsb	r7, r1, #32
 800036c:	408b      	lsls	r3, r1
 800036e:	fa22 fc07 	lsr.w	ip, r2, r7
 8000372:	ea4c 0c03 	orr.w	ip, ip, r3
 8000376:	fa05 f401 	lsl.w	r4, r5, r1
 800037a:	fa20 f307 	lsr.w	r3, r0, r7
 800037e:	40fd      	lsrs	r5, r7
 8000380:	ea4f 491c 	mov.w	r9, ip, lsr #16
 8000384:	4323      	orrs	r3, r4
 8000386:	fbb5 f8f9 	udiv	r8, r5, r9
 800038a:	fa1f fe8c 	uxth.w	lr, ip
 800038e:	fb09 5518 	mls	r5, r9, r8, r5
 8000392:	0c1c      	lsrs	r4, r3, #16
 8000394:	ea44 4405 	orr.w	r4, r4, r5, lsl #16
 8000398:	fb08 f50e 	mul.w	r5, r8, lr
 800039c:	42a5      	cmp	r5, r4
 800039e:	fa02 f201 	lsl.w	r2, r2, r1
 80003a2:	fa00 f001 	lsl.w	r0, r0, r1
 80003a6:	d90b      	bls.n	80003c0 <__udivmoddi4+0x1b0>
 80003a8:	eb1c 0404 	adds.w	r4, ip, r4
 80003ac:	f108 3aff 	add.w	sl, r8, #4294967295
 80003b0:	f080 8088 	bcs.w	80004c4 <__udivmoddi4+0x2b4>
 80003b4:	42a5      	cmp	r5, r4
 80003b6:	f240 8085 	bls.w	80004c4 <__udivmoddi4+0x2b4>
 80003ba:	f1a8 0802 	sub.w	r8, r8, #2
 80003be:	4464      	add	r4, ip
 80003c0:	1b64      	subs	r4, r4, r5
 80003c2:	b29d      	uxth	r5, r3
 80003c4:	fbb4 f3f9 	udiv	r3, r4, r9
 80003c8:	fb09 4413 	mls	r4, r9, r3, r4
 80003cc:	ea45 4404 	orr.w	r4, r5, r4, lsl #16
 80003d0:	fb03 fe0e 	mul.w	lr, r3, lr
 80003d4:	45a6      	cmp	lr, r4
 80003d6:	d908      	bls.n	80003ea <__udivmoddi4+0x1da>
 80003d8:	eb1c 0404 	adds.w	r4, ip, r4
 80003dc:	f103 35ff 	add.w	r5, r3, #4294967295
 80003e0:	d26c      	bcs.n	80004bc <__udivmoddi4+0x2ac>
 80003e2:	45a6      	cmp	lr, r4
 80003e4:	d96a      	bls.n	80004bc <__udivmoddi4+0x2ac>
 80003e6:	3b02      	subs	r3, #2
 80003e8:	4464      	add	r4, ip
 80003ea:	ea43 4308 	orr.w	r3, r3, r8, lsl #16
 80003ee:	fba3 9502 	umull	r9, r5, r3, r2
 80003f2:	eba4 040e 	sub.w	r4, r4, lr
 80003f6:	42ac      	cmp	r4, r5
 80003f8:	46c8      	mov	r8, r9
 80003fa:	46ae      	mov	lr, r5
 80003fc:	d356      	bcc.n	80004ac <__udivmoddi4+0x29c>
 80003fe:	d053      	beq.n	80004a8 <__udivmoddi4+0x298>
 8000400:	b156      	cbz	r6, 8000418 <__udivmoddi4+0x208>
 8000402:	ebb0 0208 	subs.w	r2, r0, r8
 8000406:	eb64 040e 	sbc.w	r4, r4, lr
 800040a:	fa04 f707 	lsl.w	r7, r4, r7
 800040e:	40ca      	lsrs	r2, r1
 8000410:	40cc      	lsrs	r4, r1
 8000412:	4317      	orrs	r7, r2
 8000414:	e9c6 7400 	strd	r7, r4, [r6]
 8000418:	4618      	mov	r0, r3
 800041a:	2100      	movs	r1, #0
 800041c:	e8bd 87f0 	ldmia.w	sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
 8000420:	f1c3 0120 	rsb	r1, r3, #32
 8000424:	fa02 fc03 	lsl.w	ip, r2, r3
 8000428:	fa20 f201 	lsr.w	r2, r0, r1
 800042c:	fa25 f101 	lsr.w	r1, r5, r1
 8000430:	409d      	lsls	r5, r3
 8000432:	432a      	orrs	r2, r5
 8000434:	ea4f 471c 	mov.w	r7, ip, lsr #16
 8000438:	fa1f fe8c 	uxth.w	lr, ip
 800043c:	fbb1 f0f7 	udiv	r0, r1, r7
 8000440:	fb07 1510 	mls	r5, r7, r0, r1
 8000444:	0c11      	lsrs	r1, r2, #16
 8000446:	ea41 4105 	orr.w	r1, r1, r5, lsl #16
 800044a:	fb00 f50e 	mul.w	r5, r0, lr
 800044e:	428d      	cmp	r5, r1
 8000450:	fa04 f403 	lsl.w	r4, r4, r3
 8000454:	d908      	bls.n	8000468 <__udivmoddi4+0x258>
 8000456:	eb1c 0101 	adds.w	r1, ip, r1
 800045a:	f100 38ff 	add.w	r8, r0, #4294967295
 800045e:	d22f      	bcs.n	80004c0 <__udivmoddi4+0x2b0>
 8000460:	428d      	cmp	r5, r1
 8000462:	d92d      	bls.n	80004c0 <__udivmoddi4+0x2b0>
 8000464:	3802      	subs	r0, #2
 8000466:	4461      	add	r1, ip
 8000468:	1b49      	subs	r1, r1, r5
 800046a:	b292      	uxth	r2, r2
 800046c:	fbb1 f5f7 	udiv	r5, r1, r7
 8000470:	fb07 1115 	mls	r1, r7, r5, r1
 8000474:	ea42 4201 	orr.w	r2, r2, r1, lsl #16
 8000478:	fb05 f10e 	mul.w	r1, r5, lr
 800047c:	4291      	cmp	r1, r2
 800047e:	d908      	bls.n	8000492 <__udivmoddi4+0x282>
 8000480:	eb1c 0202 	adds.w	r2, ip, r2
 8000484:	f105 38ff 	add.w	r8, r5, #4294967295
 8000488:	d216      	bcs.n	80004b8 <__udivmoddi4+0x2a8>
 800048a:	4291      	cmp	r1, r2
 800048c:	d914      	bls.n	80004b8 <__udivmoddi4+0x2a8>
 800048e:	3d02      	subs	r5, #2
 8000490:	4462      	add	r2, ip
 8000492:	1a52      	subs	r2, r2, r1
 8000494:	ea45 4100 	orr.w	r1, r5, r0, lsl #16
 8000498:	e738      	b.n	800030c <__udivmoddi4+0xfc>
 800049a:	4631      	mov	r1, r6
 800049c:	4630      	mov	r0, r6
 800049e:	e708      	b.n	80002b2 <__udivmoddi4+0xa2>
 80004a0:	4639      	mov	r1, r7
 80004a2:	e6e6      	b.n	8000272 <__udivmoddi4+0x62>
 80004a4:	4610      	mov	r0, r2
 80004a6:	e6fb      	b.n	80002a0 <__udivmoddi4+0x90>
 80004a8:	4548      	cmp	r0, r9
 80004aa:	d2a9      	bcs.n	8000400 <__udivmoddi4+0x1f0>
 80004ac:	ebb9 0802 	subs.w	r8, r9, r2
 80004b0:	eb65 0e0c 	sbc.w	lr, r5, ip
 80004b4:	3b01      	subs	r3, #1
 80004b6:	e7a3      	b.n	8000400 <__udivmoddi4+0x1f0>
 80004b8:	4645      	mov	r5, r8
 80004ba:	e7ea      	b.n	8000492 <__udivmoddi4+0x282>
 80004bc:	462b      	mov	r3, r5
 80004be:	e794      	b.n	80003ea <__udivmoddi4+0x1da>
 80004c0:	4640      	mov	r0, r8
 80004c2:	e7d1      	b.n	8000468 <__udivmoddi4+0x258>
 80004c4:	46d0      	mov	r8, sl
 80004c6:	e77b      	b.n	80003c0 <__udivmoddi4+0x1b0>
 80004c8:	3d02      	subs	r5, #2
 80004ca:	4462      	add	r2, ip
 80004cc:	e732      	b.n	8000334 <__udivmoddi4+0x124>
 80004ce:	4608      	mov	r0, r1
 80004d0:	e70a      	b.n	80002e8 <__udivmoddi4+0xd8>
 80004d2:	4464      	add	r4, ip
 80004d4:	3802      	subs	r0, #2
 80004d6:	e742      	b.n	800035e <__udivmoddi4+0x14e>

080004d8 <__aeabi_idiv0>:
 80004d8:	4770      	bx	lr
 80004da:	bf00      	nop

080004dc <HAL_ADC_ConvCpltCallback>:

/* USER CODE END PFP */

/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) {
 80004dc:	b580      	push	{r7, lr}
 80004de:	b082      	sub	sp, #8
 80004e0:	af00      	add	r7, sp, #0
 80004e2:	6078      	str	r0, [r7, #4]
	adc_val = HAL_ADC_GetValue(&hadc1);
 80004e4:	480a      	ldr	r0, [pc, #40]	; (8000510 <HAL_ADC_ConvCpltCallback+0x34>)
 80004e6:	f000 ff75 	bl	80013d4 <HAL_ADC_GetValue>
 80004ea:	4603      	mov	r3, r0
 80004ec:	b29a      	uxth	r2, r3
 80004ee:	4b09      	ldr	r3, [pc, #36]	; (8000514 <HAL_ADC_ConvCpltCallback+0x38>)
 80004f0:	801a      	strh	r2, [r3, #0]
	scan_active = adc_val < 1000;
 80004f2:	4b08      	ldr	r3, [pc, #32]	; (8000514 <HAL_ADC_ConvCpltCallback+0x38>)
 80004f4:	881b      	ldrh	r3, [r3, #0]
 80004f6:	f240 32e7 	movw	r2, #999	; 0x3e7
 80004fa:	4293      	cmp	r3, r2
 80004fc:	bf94      	ite	ls
 80004fe:	2301      	movls	r3, #1
 8000500:	2300      	movhi	r3, #0
 8000502:	b2da      	uxtb	r2, r3
 8000504:	4b04      	ldr	r3, [pc, #16]	; (8000518 <HAL_ADC_ConvCpltCallback+0x3c>)
 8000506:	701a      	strb	r2, [r3, #0]
}
 8000508:	bf00      	nop
 800050a:	3708      	adds	r7, #8
 800050c:	46bd      	mov	sp, r7
 800050e:	bd80      	pop	{r7, pc}
 8000510:	2000007c 	.word	0x2000007c
 8000514:	2000012e 	.word	0x2000012e
 8000518:	2000012d 	.word	0x2000012d

0800051c <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 800051c:	b580      	push	{r7, lr}
 800051e:	af00      	add	r7, sp, #0
  /* USER CODE END 1 */

  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000520:	f000 fd04 	bl	8000f2c <HAL_Init>
  /* USER CODE BEGIN Init */

  /* USER CODE END Init */

  /* Configure the system clock */
  SystemClock_Config();
 8000524:	f000 f84a 	bl	80005bc <SystemClock_Config>
  /* USER CODE BEGIN SysInit */

  /* USER CODE END SysInit */

  /* Initialize all configured peripherals */
  MX_GPIO_Init();
 8000528:	f000 f92e 	bl	8000788 <MX_GPIO_Init>
  MX_USART2_UART_Init();
 800052c:	f000 f902 	bl	8000734 <MX_USART2_UART_Init>
  MX_ADC1_Init();
 8000530:	f000 f8ae 	bl	8000690 <MX_ADC1_Init>
  /* USER CODE BEGIN 2 */
	memset(uart_buffer, 0, 10);
 8000534:	220a      	movs	r2, #10
 8000536:	2100      	movs	r1, #0
 8000538:	4813      	ldr	r0, [pc, #76]	; (8000588 <main+0x6c>)
 800053a:	f005 fda7 	bl	800608c <memset>
  /* USER CODE END 2 */

  /* Init scheduler */
  osKernelInitialize();
 800053e:	f003 f82d 	bl	800359c <osKernelInitialize>
	/* add queues, ... */
  /* USER CODE END RTOS_QUEUES */

  /* Create the thread(s) */
  /* creation of mainTask */
  mainTaskHandle = osThreadNew(StartMainTask, NULL, &mainTask_attributes);
 8000542:	4a12      	ldr	r2, [pc, #72]	; (800058c <main+0x70>)
 8000544:	2100      	movs	r1, #0
 8000546:	4812      	ldr	r0, [pc, #72]	; (8000590 <main+0x74>)
 8000548:	f003 f872 	bl	8003630 <osThreadNew>
 800054c:	4603      	mov	r3, r0
 800054e:	4a11      	ldr	r2, [pc, #68]	; (8000594 <main+0x78>)
 8000550:	6013      	str	r3, [r2, #0]

  /* creation of doorHandler */
  doorHandlerHandle = osThreadNew(startDoorHandleTask, NULL, &doorHandler_attributes);
 8000552:	4a11      	ldr	r2, [pc, #68]	; (8000598 <main+0x7c>)
 8000554:	2100      	movs	r1, #0
 8000556:	4811      	ldr	r0, [pc, #68]	; (800059c <main+0x80>)
 8000558:	f003 f86a 	bl	8003630 <osThreadNew>
 800055c:	4603      	mov	r3, r0
 800055e:	4a10      	ldr	r2, [pc, #64]	; (80005a0 <main+0x84>)
 8000560:	6013      	str	r3, [r2, #0]

  /* creation of StateSendTask */
  StateSendTaskHandle = osThreadNew(StartStateSendTask, NULL, &StateSendTask_attributes);
 8000562:	4a10      	ldr	r2, [pc, #64]	; (80005a4 <main+0x88>)
 8000564:	2100      	movs	r1, #0
 8000566:	4810      	ldr	r0, [pc, #64]	; (80005a8 <main+0x8c>)
 8000568:	f003 f862 	bl	8003630 <osThreadNew>
 800056c:	4603      	mov	r3, r0
 800056e:	4a0f      	ldr	r2, [pc, #60]	; (80005ac <main+0x90>)
 8000570:	6013      	str	r3, [r2, #0]

  /* creation of ADCReqTask */
  ADCReqTaskHandle = osThreadNew(StartADCReqTask, NULL, &ADCReqTask_attributes);
 8000572:	4a0f      	ldr	r2, [pc, #60]	; (80005b0 <main+0x94>)
 8000574:	2100      	movs	r1, #0
 8000576:	480f      	ldr	r0, [pc, #60]	; (80005b4 <main+0x98>)
 8000578:	f003 f85a 	bl	8003630 <osThreadNew>
 800057c:	4603      	mov	r3, r0
 800057e:	4a0e      	ldr	r2, [pc, #56]	; (80005b8 <main+0x9c>)
 8000580:	6013      	str	r3, [r2, #0]
  /* USER CODE BEGIN RTOS_EVENTS */
	/* add events, ... */
  /* USER CODE END RTOS_EVENTS */

  /* Start scheduler */
  osKernelStart();
 8000582:	f003 f82f 	bl	80035e4 <osKernelStart>

  /* We should never get here as control is now taken by the scheduler */
  /* Infinite loop */
  /* USER CODE BEGIN WHILE */
	while (1) {
 8000586:	e7fe      	b.n	8000586 <main+0x6a>
 8000588:	20000118 	.word	0x20000118
 800058c:	080062c4 	.word	0x080062c4
 8000590:	080008a9 	.word	0x080008a9
 8000594:	20000108 	.word	0x20000108
 8000598:	080062e8 	.word	0x080062e8
 800059c:	080009c9 	.word	0x080009c9
 80005a0:	2000010c 	.word	0x2000010c
 80005a4:	0800630c 	.word	0x0800630c
 80005a8:	08000b59 	.word	0x08000b59
 80005ac:	20000110 	.word	0x20000110
 80005b0:	08006330 	.word	0x08006330
 80005b4:	08000bb1 	.word	0x08000bb1
 80005b8:	20000114 	.word	0x20000114

080005bc <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 80005bc:	b580      	push	{r7, lr}
 80005be:	b094      	sub	sp, #80	; 0x50
 80005c0:	af00      	add	r7, sp, #0
  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 80005c2:	f107 0320 	add.w	r3, r7, #32
 80005c6:	2230      	movs	r2, #48	; 0x30
 80005c8:	2100      	movs	r1, #0
 80005ca:	4618      	mov	r0, r3
 80005cc:	f005 fd5e 	bl	800608c <memset>
  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 80005d0:	f107 030c 	add.w	r3, r7, #12
 80005d4:	2200      	movs	r2, #0
 80005d6:	601a      	str	r2, [r3, #0]
 80005d8:	605a      	str	r2, [r3, #4]
 80005da:	609a      	str	r2, [r3, #8]
 80005dc:	60da      	str	r2, [r3, #12]
 80005de:	611a      	str	r2, [r3, #16]

  /** Configure the main internal regulator output voltage
  */
  __HAL_RCC_PWR_CLK_ENABLE();
 80005e0:	2300      	movs	r3, #0
 80005e2:	60bb      	str	r3, [r7, #8]
 80005e4:	4b28      	ldr	r3, [pc, #160]	; (8000688 <SystemClock_Config+0xcc>)
 80005e6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80005e8:	4a27      	ldr	r2, [pc, #156]	; (8000688 <SystemClock_Config+0xcc>)
 80005ea:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80005ee:	6413      	str	r3, [r2, #64]	; 0x40
 80005f0:	4b25      	ldr	r3, [pc, #148]	; (8000688 <SystemClock_Config+0xcc>)
 80005f2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80005f4:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80005f8:	60bb      	str	r3, [r7, #8]
 80005fa:	68bb      	ldr	r3, [r7, #8]
  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 80005fc:	2300      	movs	r3, #0
 80005fe:	607b      	str	r3, [r7, #4]
 8000600:	4b22      	ldr	r3, [pc, #136]	; (800068c <SystemClock_Config+0xd0>)
 8000602:	681b      	ldr	r3, [r3, #0]
 8000604:	4a21      	ldr	r2, [pc, #132]	; (800068c <SystemClock_Config+0xd0>)
 8000606:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
 800060a:	6013      	str	r3, [r2, #0]
 800060c:	4b1f      	ldr	r3, [pc, #124]	; (800068c <SystemClock_Config+0xd0>)
 800060e:	681b      	ldr	r3, [r3, #0]
 8000610:	f403 4340 	and.w	r3, r3, #49152	; 0xc000
 8000614:	607b      	str	r3, [r7, #4]
 8000616:	687b      	ldr	r3, [r7, #4]

  /** Initializes the RCC Oscillators according to the specified parameters
  * in the RCC_OscInitTypeDef structure.
  */
  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
 8000618:	2302      	movs	r3, #2
 800061a:	623b      	str	r3, [r7, #32]
  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 800061c:	2301      	movs	r3, #1
 800061e:	62fb      	str	r3, [r7, #44]	; 0x2c
  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
 8000620:	2310      	movs	r3, #16
 8000622:	633b      	str	r3, [r7, #48]	; 0x30
  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 8000624:	2302      	movs	r3, #2
 8000626:	63bb      	str	r3, [r7, #56]	; 0x38
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
 8000628:	2300      	movs	r3, #0
 800062a:	63fb      	str	r3, [r7, #60]	; 0x3c
  RCC_OscInitStruct.PLL.PLLM = 16;
 800062c:	2310      	movs	r3, #16
 800062e:	643b      	str	r3, [r7, #64]	; 0x40
  RCC_OscInitStruct.PLL.PLLN = 336;
 8000630:	f44f 73a8 	mov.w	r3, #336	; 0x150
 8000634:	647b      	str	r3, [r7, #68]	; 0x44
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4;
 8000636:	2304      	movs	r3, #4
 8000638:	64bb      	str	r3, [r7, #72]	; 0x48
  RCC_OscInitStruct.PLL.PLLQ = 4;
 800063a:	2304      	movs	r3, #4
 800063c:	64fb      	str	r3, [r7, #76]	; 0x4c
  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800063e:	f107 0320 	add.w	r3, r7, #32
 8000642:	4618      	mov	r0, r3
 8000644:	f001 fbb8 	bl	8001db8 <HAL_RCC_OscConfig>
 8000648:	4603      	mov	r3, r0
 800064a:	2b00      	cmp	r3, #0
 800064c:	d001      	beq.n	8000652 <SystemClock_Config+0x96>
  {
    Error_Handler();
 800064e:	f000 facf 	bl	8000bf0 <Error_Handler>
  }

  /** Initializes the CPU, AHB and APB buses clocks
  */
  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 8000652:	230f      	movs	r3, #15
 8000654:	60fb      	str	r3, [r7, #12]
                              |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 8000656:	2302      	movs	r3, #2
 8000658:	613b      	str	r3, [r7, #16]
  RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 800065a:	2300      	movs	r3, #0
 800065c:	617b      	str	r3, [r7, #20]
  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 800065e:	f44f 5380 	mov.w	r3, #4096	; 0x1000
 8000662:	61bb      	str	r3, [r7, #24]
  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 8000664:	2300      	movs	r3, #0
 8000666:	61fb      	str	r3, [r7, #28]

  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 8000668:	f107 030c 	add.w	r3, r7, #12
 800066c:	2102      	movs	r1, #2
 800066e:	4618      	mov	r0, r3
 8000670:	f001 fe1a 	bl	80022a8 <HAL_RCC_ClockConfig>
 8000674:	4603      	mov	r3, r0
 8000676:	2b00      	cmp	r3, #0
 8000678:	d001      	beq.n	800067e <SystemClock_Config+0xc2>
  {
    Error_Handler();
 800067a:	f000 fab9 	bl	8000bf0 <Error_Handler>
  }
}
 800067e:	bf00      	nop
 8000680:	3750      	adds	r7, #80	; 0x50
 8000682:	46bd      	mov	sp, r7
 8000684:	bd80      	pop	{r7, pc}
 8000686:	bf00      	nop
 8000688:	40023800 	.word	0x40023800
 800068c:	40007000 	.word	0x40007000

08000690 <MX_ADC1_Init>:
  * @brief ADC1 Initialization Function
  * @param None
  * @retval None
  */
static void MX_ADC1_Init(void)
{
 8000690:	b580      	push	{r7, lr}
 8000692:	b084      	sub	sp, #16
 8000694:	af00      	add	r7, sp, #0

  /* USER CODE BEGIN ADC1_Init 0 */

  /* USER CODE END ADC1_Init 0 */

  ADC_ChannelConfTypeDef sConfig = {0};
 8000696:	463b      	mov	r3, r7
 8000698:	2200      	movs	r2, #0
 800069a:	601a      	str	r2, [r3, #0]
 800069c:	605a      	str	r2, [r3, #4]
 800069e:	609a      	str	r2, [r3, #8]
 80006a0:	60da      	str	r2, [r3, #12]

  /* USER CODE END ADC1_Init 1 */

  /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
  */
  hadc1.Instance = ADC1;
 80006a2:	4b21      	ldr	r3, [pc, #132]	; (8000728 <MX_ADC1_Init+0x98>)
 80006a4:	4a21      	ldr	r2, [pc, #132]	; (800072c <MX_ADC1_Init+0x9c>)
 80006a6:	601a      	str	r2, [r3, #0]
  hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
 80006a8:	4b1f      	ldr	r3, [pc, #124]	; (8000728 <MX_ADC1_Init+0x98>)
 80006aa:	f44f 3280 	mov.w	r2, #65536	; 0x10000
 80006ae:	605a      	str	r2, [r3, #4]
  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
 80006b0:	4b1d      	ldr	r3, [pc, #116]	; (8000728 <MX_ADC1_Init+0x98>)
 80006b2:	2200      	movs	r2, #0
 80006b4:	609a      	str	r2, [r3, #8]
  hadc1.Init.ScanConvMode = DISABLE;
 80006b6:	4b1c      	ldr	r3, [pc, #112]	; (8000728 <MX_ADC1_Init+0x98>)
 80006b8:	2200      	movs	r2, #0
 80006ba:	611a      	str	r2, [r3, #16]
  hadc1.Init.ContinuousConvMode = DISABLE;
 80006bc:	4b1a      	ldr	r3, [pc, #104]	; (8000728 <MX_ADC1_Init+0x98>)
 80006be:	2200      	movs	r2, #0
 80006c0:	761a      	strb	r2, [r3, #24]
  hadc1.Init.DiscontinuousConvMode = DISABLE;
 80006c2:	4b19      	ldr	r3, [pc, #100]	; (8000728 <MX_ADC1_Init+0x98>)
 80006c4:	2200      	movs	r2, #0
 80006c6:	f883 2020 	strb.w	r2, [r3, #32]
  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
 80006ca:	4b17      	ldr	r3, [pc, #92]	; (8000728 <MX_ADC1_Init+0x98>)
 80006cc:	2200      	movs	r2, #0
 80006ce:	62da      	str	r2, [r3, #44]	; 0x2c
  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
 80006d0:	4b15      	ldr	r3, [pc, #84]	; (8000728 <MX_ADC1_Init+0x98>)
 80006d2:	4a17      	ldr	r2, [pc, #92]	; (8000730 <MX_ADC1_Init+0xa0>)
 80006d4:	629a      	str	r2, [r3, #40]	; 0x28
  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
 80006d6:	4b14      	ldr	r3, [pc, #80]	; (8000728 <MX_ADC1_Init+0x98>)
 80006d8:	2200      	movs	r2, #0
 80006da:	60da      	str	r2, [r3, #12]
  hadc1.Init.NbrOfConversion = 1;
 80006dc:	4b12      	ldr	r3, [pc, #72]	; (8000728 <MX_ADC1_Init+0x98>)
 80006de:	2201      	movs	r2, #1
 80006e0:	61da      	str	r2, [r3, #28]
  hadc1.Init.DMAContinuousRequests = DISABLE;
 80006e2:	4b11      	ldr	r3, [pc, #68]	; (8000728 <MX_ADC1_Init+0x98>)
 80006e4:	2200      	movs	r2, #0
 80006e6:	f883 2030 	strb.w	r2, [r3, #48]	; 0x30
  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
 80006ea:	4b0f      	ldr	r3, [pc, #60]	; (8000728 <MX_ADC1_Init+0x98>)
 80006ec:	2201      	movs	r2, #1
 80006ee:	615a      	str	r2, [r3, #20]
  if (HAL_ADC_Init(&hadc1) != HAL_OK)
 80006f0:	480d      	ldr	r0, [pc, #52]	; (8000728 <MX_ADC1_Init+0x98>)
 80006f2:	f000 fc5d 	bl	8000fb0 <HAL_ADC_Init>
 80006f6:	4603      	mov	r3, r0
 80006f8:	2b00      	cmp	r3, #0
 80006fa:	d001      	beq.n	8000700 <MX_ADC1_Init+0x70>
  {
    Error_Handler();
 80006fc:	f000 fa78 	bl	8000bf0 <Error_Handler>
  }

  /** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
  */
  sConfig.Channel = ADC_CHANNEL_1;
 8000700:	2301      	movs	r3, #1
 8000702:	603b      	str	r3, [r7, #0]
  sConfig.Rank = 1;
 8000704:	2301      	movs	r3, #1
 8000706:	607b      	str	r3, [r7, #4]
  sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
 8000708:	2300      	movs	r3, #0
 800070a:	60bb      	str	r3, [r7, #8]
  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
 800070c:	463b      	mov	r3, r7
 800070e:	4619      	mov	r1, r3
 8000710:	4805      	ldr	r0, [pc, #20]	; (8000728 <MX_ADC1_Init+0x98>)
 8000712:	f000 fe81 	bl	8001418 <HAL_ADC_ConfigChannel>
 8000716:	4603      	mov	r3, r0
 8000718:	2b00      	cmp	r3, #0
 800071a:	d001      	beq.n	8000720 <MX_ADC1_Init+0x90>
  {
    Error_Handler();
 800071c:	f000 fa68 	bl	8000bf0 <Error_Handler>
  }
  /* USER CODE BEGIN ADC1_Init 2 */

  /* USER CODE END ADC1_Init 2 */

}
 8000720:	bf00      	nop
 8000722:	3710      	adds	r7, #16
 8000724:	46bd      	mov	sp, r7
 8000726:	bd80      	pop	{r7, pc}
 8000728:	2000007c 	.word	0x2000007c
 800072c:	40012000 	.word	0x40012000
 8000730:	0f000001 	.word	0x0f000001

08000734 <MX_USART2_UART_Init>:
  * @brief USART2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_USART2_UART_Init(void)
{
 8000734:	b580      	push	{r7, lr}
 8000736:	af00      	add	r7, sp, #0
  /* USER CODE END USART2_Init 0 */

  /* USER CODE BEGIN USART2_Init 1 */

  /* USER CODE END USART2_Init 1 */
  huart2.Instance = USART2;
 8000738:	4b11      	ldr	r3, [pc, #68]	; (8000780 <MX_USART2_UART_Init+0x4c>)
 800073a:	4a12      	ldr	r2, [pc, #72]	; (8000784 <MX_USART2_UART_Init+0x50>)
 800073c:	601a      	str	r2, [r3, #0]
  huart2.Init.BaudRate = 9600;
 800073e:	4b10      	ldr	r3, [pc, #64]	; (8000780 <MX_USART2_UART_Init+0x4c>)
 8000740:	f44f 5216 	mov.w	r2, #9600	; 0x2580
 8000744:	605a      	str	r2, [r3, #4]
  huart2.Init.WordLength = UART_WORDLENGTH_8B;
 8000746:	4b0e      	ldr	r3, [pc, #56]	; (8000780 <MX_USART2_UART_Init+0x4c>)
 8000748:	2200      	movs	r2, #0
 800074a:	609a      	str	r2, [r3, #8]
  huart2.Init.StopBits = UART_STOPBITS_1;
 800074c:	4b0c      	ldr	r3, [pc, #48]	; (8000780 <MX_USART2_UART_Init+0x4c>)
 800074e:	2200      	movs	r2, #0
 8000750:	60da      	str	r2, [r3, #12]
  huart2.Init.Parity = UART_PARITY_NONE;
 8000752:	4b0b      	ldr	r3, [pc, #44]	; (8000780 <MX_USART2_UART_Init+0x4c>)
 8000754:	2200      	movs	r2, #0
 8000756:	611a      	str	r2, [r3, #16]
  huart2.Init.Mode = UART_MODE_TX_RX;
 8000758:	4b09      	ldr	r3, [pc, #36]	; (8000780 <MX_USART2_UART_Init+0x4c>)
 800075a:	220c      	movs	r2, #12
 800075c:	615a      	str	r2, [r3, #20]
  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
 800075e:	4b08      	ldr	r3, [pc, #32]	; (8000780 <MX_USART2_UART_Init+0x4c>)
 8000760:	2200      	movs	r2, #0
 8000762:	619a      	str	r2, [r3, #24]
  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
 8000764:	4b06      	ldr	r3, [pc, #24]	; (8000780 <MX_USART2_UART_Init+0x4c>)
 8000766:	2200      	movs	r2, #0
 8000768:	61da      	str	r2, [r3, #28]
  if (HAL_UART_Init(&huart2) != HAL_OK)
 800076a:	4805      	ldr	r0, [pc, #20]	; (8000780 <MX_USART2_UART_Init+0x4c>)
 800076c:	f002 fa6e 	bl	8002c4c <HAL_UART_Init>
 8000770:	4603      	mov	r3, r0
 8000772:	2b00      	cmp	r3, #0
 8000774:	d001      	beq.n	800077a <MX_USART2_UART_Init+0x46>
  {
    Error_Handler();
 8000776:	f000 fa3b 	bl	8000bf0 <Error_Handler>
  }
  /* USER CODE BEGIN USART2_Init 2 */

  /* USER CODE END USART2_Init 2 */

}
 800077a:	bf00      	nop
 800077c:	bd80      	pop	{r7, pc}
 800077e:	bf00      	nop
 8000780:	200000c4 	.word	0x200000c4
 8000784:	40004400 	.word	0x40004400

08000788 <MX_GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void MX_GPIO_Init(void)
{
 8000788:	b580      	push	{r7, lr}
 800078a:	b08a      	sub	sp, #40	; 0x28
 800078c:	af00      	add	r7, sp, #0
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 800078e:	f107 0314 	add.w	r3, r7, #20
 8000792:	2200      	movs	r2, #0
 8000794:	601a      	str	r2, [r3, #0]
 8000796:	605a      	str	r2, [r3, #4]
 8000798:	609a      	str	r2, [r3, #8]
 800079a:	60da      	str	r2, [r3, #12]
 800079c:	611a      	str	r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOC_CLK_ENABLE();
 800079e:	2300      	movs	r3, #0
 80007a0:	613b      	str	r3, [r7, #16]
 80007a2:	4b3e      	ldr	r3, [pc, #248]	; (800089c <MX_GPIO_Init+0x114>)
 80007a4:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80007a6:	4a3d      	ldr	r2, [pc, #244]	; (800089c <MX_GPIO_Init+0x114>)
 80007a8:	f043 0304 	orr.w	r3, r3, #4
 80007ac:	6313      	str	r3, [r2, #48]	; 0x30
 80007ae:	4b3b      	ldr	r3, [pc, #236]	; (800089c <MX_GPIO_Init+0x114>)
 80007b0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80007b2:	f003 0304 	and.w	r3, r3, #4
 80007b6:	613b      	str	r3, [r7, #16]
 80007b8:	693b      	ldr	r3, [r7, #16]
  __HAL_RCC_GPIOH_CLK_ENABLE();
 80007ba:	2300      	movs	r3, #0
 80007bc:	60fb      	str	r3, [r7, #12]
 80007be:	4b37      	ldr	r3, [pc, #220]	; (800089c <MX_GPIO_Init+0x114>)
 80007c0:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80007c2:	4a36      	ldr	r2, [pc, #216]	; (800089c <MX_GPIO_Init+0x114>)
 80007c4:	f043 0380 	orr.w	r3, r3, #128	; 0x80
 80007c8:	6313      	str	r3, [r2, #48]	; 0x30
 80007ca:	4b34      	ldr	r3, [pc, #208]	; (800089c <MX_GPIO_Init+0x114>)
 80007cc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80007ce:	f003 0380 	and.w	r3, r3, #128	; 0x80
 80007d2:	60fb      	str	r3, [r7, #12]
 80007d4:	68fb      	ldr	r3, [r7, #12]
  __HAL_RCC_GPIOA_CLK_ENABLE();
 80007d6:	2300      	movs	r3, #0
 80007d8:	60bb      	str	r3, [r7, #8]
 80007da:	4b30      	ldr	r3, [pc, #192]	; (800089c <MX_GPIO_Init+0x114>)
 80007dc:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80007de:	4a2f      	ldr	r2, [pc, #188]	; (800089c <MX_GPIO_Init+0x114>)
 80007e0:	f043 0301 	orr.w	r3, r3, #1
 80007e4:	6313      	str	r3, [r2, #48]	; 0x30
 80007e6:	4b2d      	ldr	r3, [pc, #180]	; (800089c <MX_GPIO_Init+0x114>)
 80007e8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80007ea:	f003 0301 	and.w	r3, r3, #1
 80007ee:	60bb      	str	r3, [r7, #8]
 80007f0:	68bb      	ldr	r3, [r7, #8]
  __HAL_RCC_GPIOB_CLK_ENABLE();
 80007f2:	2300      	movs	r3, #0
 80007f4:	607b      	str	r3, [r7, #4]
 80007f6:	4b29      	ldr	r3, [pc, #164]	; (800089c <MX_GPIO_Init+0x114>)
 80007f8:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 80007fa:	4a28      	ldr	r2, [pc, #160]	; (800089c <MX_GPIO_Init+0x114>)
 80007fc:	f043 0302 	orr.w	r3, r3, #2
 8000800:	6313      	str	r3, [r2, #48]	; 0x30
 8000802:	4b26      	ldr	r3, [pc, #152]	; (800089c <MX_GPIO_Init+0x114>)
 8000804:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000806:	f003 0302 	and.w	r3, r3, #2
 800080a:	607b      	str	r3, [r7, #4]
 800080c:	687b      	ldr	r3, [r7, #4]

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(ALARM_GPIO_Port, ALARM_Pin, GPIO_PIN_RESET);
 800080e:	2200      	movs	r2, #0
 8000810:	2101      	movs	r1, #1
 8000812:	4823      	ldr	r0, [pc, #140]	; (80008a0 <MX_GPIO_Init+0x118>)
 8000814:	f001 fab6 	bl	8001d84 <HAL_GPIO_WritePin>

  /*Configure GPIO pin Output Level */
  HAL_GPIO_WritePin(GPIOA, LD2_Pin|Door_Lock_Pin, GPIO_PIN_RESET);
 8000818:	2200      	movs	r2, #0
 800081a:	f44f 7108 	mov.w	r1, #544	; 0x220
 800081e:	4821      	ldr	r0, [pc, #132]	; (80008a4 <MX_GPIO_Init+0x11c>)
 8000820:	f001 fab0 	bl	8001d84 <HAL_GPIO_WritePin>

  /*Configure GPIO pin : B1_Pin */
  GPIO_InitStruct.Pin = B1_Pin;
 8000824:	f44f 5300 	mov.w	r3, #8192	; 0x2000
 8000828:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
 800082a:	f44f 1304 	mov.w	r3, #2162688	; 0x210000
 800082e:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000830:	2300      	movs	r3, #0
 8000832:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct);
 8000834:	f107 0314 	add.w	r3, r7, #20
 8000838:	4619      	mov	r1, r3
 800083a:	4819      	ldr	r0, [pc, #100]	; (80008a0 <MX_GPIO_Init+0x118>)
 800083c:	f001 f906 	bl	8001a4c <HAL_GPIO_Init>

  /*Configure GPIO pin : ALARM_Pin */
  GPIO_InitStruct.Pin = ALARM_Pin;
 8000840:	2301      	movs	r3, #1
 8000842:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000844:	2301      	movs	r3, #1
 8000846:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000848:	2300      	movs	r3, #0
 800084a:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 800084c:	2300      	movs	r3, #0
 800084e:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(ALARM_GPIO_Port, &GPIO_InitStruct);
 8000850:	f107 0314 	add.w	r3, r7, #20
 8000854:	4619      	mov	r1, r3
 8000856:	4812      	ldr	r0, [pc, #72]	; (80008a0 <MX_GPIO_Init+0x118>)
 8000858:	f001 f8f8 	bl	8001a4c <HAL_GPIO_Init>

  /*Configure GPIO pins : LD2_Pin Door_Lock_Pin */
  GPIO_InitStruct.Pin = LD2_Pin|Door_Lock_Pin;
 800085c:	f44f 7308 	mov.w	r3, #544	; 0x220
 8000860:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
 8000862:	2301      	movs	r3, #1
 8000864:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000866:	2300      	movs	r3, #0
 8000868:	61fb      	str	r3, [r7, #28]
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
 800086a:	2300      	movs	r3, #0
 800086c:	623b      	str	r3, [r7, #32]
  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 800086e:	f107 0314 	add.w	r3, r7, #20
 8000872:	4619      	mov	r1, r3
 8000874:	480b      	ldr	r0, [pc, #44]	; (80008a4 <MX_GPIO_Init+0x11c>)
 8000876:	f001 f8e9 	bl	8001a4c <HAL_GPIO_Init>

  /*Configure GPIO pin : Door_Sensor_Pin */
  GPIO_InitStruct.Pin = Door_Sensor_Pin;
 800087a:	2380      	movs	r3, #128	; 0x80
 800087c:	617b      	str	r3, [r7, #20]
  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
 800087e:	2300      	movs	r3, #0
 8000880:	61bb      	str	r3, [r7, #24]
  GPIO_InitStruct.Pull = GPIO_PULLUP;
 8000882:	2301      	movs	r3, #1
 8000884:	61fb      	str	r3, [r7, #28]
  HAL_GPIO_Init(Door_Sensor_GPIO_Port, &GPIO_InitStruct);
 8000886:	f107 0314 	add.w	r3, r7, #20
 800088a:	4619      	mov	r1, r3
 800088c:	4805      	ldr	r0, [pc, #20]	; (80008a4 <MX_GPIO_Init+0x11c>)
 800088e:	f001 f8dd 	bl	8001a4c <HAL_GPIO_Init>

/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
 8000892:	bf00      	nop
 8000894:	3728      	adds	r7, #40	; 0x28
 8000896:	46bd      	mov	sp, r7
 8000898:	bd80      	pop	{r7, pc}
 800089a:	bf00      	nop
 800089c:	40023800 	.word	0x40023800
 80008a0:	40020800 	.word	0x40020800
 80008a4:	40020000 	.word	0x40020000

080008a8 <StartMainTask>:
 * @param  argument: Not used
 * @retval None
 */
/* USER CODE END Header_StartMainTask */
void StartMainTask(void *argument)
{
 80008a8:	b580      	push	{r7, lr}
 80008aa:	b084      	sub	sp, #16
 80008ac:	af00      	add	r7, sp, #0
 80008ae:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN 5 */
	memset(uart_buffer, 0, 10);
 80008b0:	220a      	movs	r2, #10
 80008b2:	2100      	movs	r1, #0
 80008b4:	483d      	ldr	r0, [pc, #244]	; (80009ac <StartMainTask+0x104>)
 80008b6:	f005 fbe9 	bl	800608c <memset>

	/* Infinite loop */
	/* USER CODE BEGIN WHILE */
	while (1) {

		if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 100)
 80008ba:	4b3d      	ldr	r3, [pc, #244]	; (80009b0 <StartMainTask+0x108>)
 80008bc:	781b      	ldrb	r3, [r3, #0]
 80008be:	461a      	mov	r2, r3
 80008c0:	4b3a      	ldr	r3, [pc, #232]	; (80009ac <StartMainTask+0x104>)
 80008c2:	18d1      	adds	r1, r2, r3
 80008c4:	2364      	movs	r3, #100	; 0x64
 80008c6:	2201      	movs	r2, #1
 80008c8:	483a      	ldr	r0, [pc, #232]	; (80009b4 <StartMainTask+0x10c>)
 80008ca:	f002 fa9e 	bl	8002e0a <HAL_UART_Receive>
 80008ce:	4603      	mov	r3, r0
 80008d0:	2b00      	cmp	r3, #0
 80008d2:	d166      	bne.n	80009a2 <StartMainTask+0xfa>
				== HAL_OK) {
			uart_index++;
 80008d4:	4b36      	ldr	r3, [pc, #216]	; (80009b0 <StartMainTask+0x108>)
 80008d6:	781b      	ldrb	r3, [r3, #0]
 80008d8:	3301      	adds	r3, #1
 80008da:	b2da      	uxtb	r2, r3
 80008dc:	4b34      	ldr	r3, [pc, #208]	; (80009b0 <StartMainTask+0x108>)
 80008de:	701a      	strb	r2, [r3, #0]
			if (uart_buffer[uart_index - 1] == 0xFF) {
 80008e0:	4b33      	ldr	r3, [pc, #204]	; (80009b0 <StartMainTask+0x108>)
 80008e2:	781b      	ldrb	r3, [r3, #0]
 80008e4:	3b01      	subs	r3, #1
 80008e6:	4a31      	ldr	r2, [pc, #196]	; (80009ac <StartMainTask+0x104>)
 80008e8:	5cd3      	ldrb	r3, [r2, r3]
 80008ea:	2bff      	cmp	r3, #255	; 0xff
 80008ec:	d14d      	bne.n	800098a <StartMainTask+0xe2>
				if (uart_index > 1) {
 80008ee:	4b30      	ldr	r3, [pc, #192]	; (80009b0 <StartMainTask+0x108>)
 80008f0:	781b      	ldrb	r3, [r3, #0]
 80008f2:	2b01      	cmp	r3, #1
 80008f4:	d940      	bls.n	8000978 <StartMainTask+0xd0>
					// Command Internal LED
					if (uart_buffer[0] == 0x00) {
 80008f6:	4b2d      	ldr	r3, [pc, #180]	; (80009ac <StartMainTask+0x104>)
 80008f8:	781b      	ldrb	r3, [r3, #0]
 80008fa:	2b00      	cmp	r3, #0
 80008fc:	d107      	bne.n	800090e <StartMainTask+0x66>
						HAL_GPIO_WritePin(GPIOA, GPIO_PIN_5, uart_buffer[1]);
 80008fe:	4b2b      	ldr	r3, [pc, #172]	; (80009ac <StartMainTask+0x104>)
 8000900:	785b      	ldrb	r3, [r3, #1]
 8000902:	461a      	mov	r2, r3
 8000904:	2120      	movs	r1, #32
 8000906:	482c      	ldr	r0, [pc, #176]	; (80009b8 <StartMainTask+0x110>)
 8000908:	f001 fa3c 	bl	8001d84 <HAL_GPIO_WritePin>
 800090c:	e034      	b.n	8000978 <StartMainTask+0xd0>
					}
					// Get Current Door State
					else if (uart_buffer[0] == 0x01) {
 800090e:	4b27      	ldr	r3, [pc, #156]	; (80009ac <StartMainTask+0x104>)
 8000910:	781b      	ldrb	r3, [r3, #0]
 8000912:	2b01      	cmp	r3, #1
 8000914:	d10f      	bne.n	8000936 <StartMainTask+0x8e>
						uint8_t payload[3] = { 0x01, door_state, 0xFF };
 8000916:	2301      	movs	r3, #1
 8000918:	733b      	strb	r3, [r7, #12]
 800091a:	4b28      	ldr	r3, [pc, #160]	; (80009bc <StartMainTask+0x114>)
 800091c:	781b      	ldrb	r3, [r3, #0]
 800091e:	737b      	strb	r3, [r7, #13]
 8000920:	23ff      	movs	r3, #255	; 0xff
 8000922:	73bb      	strb	r3, [r7, #14]
						HAL_UART_Transmit(&huart2, payload, 3, 1500);
 8000924:	f107 010c 	add.w	r1, r7, #12
 8000928:	f240 53dc 	movw	r3, #1500	; 0x5dc
 800092c:	2203      	movs	r2, #3
 800092e:	4821      	ldr	r0, [pc, #132]	; (80009b4 <StartMainTask+0x10c>)
 8000930:	f002 f9d9 	bl	8002ce6 <HAL_UART_Transmit>
 8000934:	e020      	b.n	8000978 <StartMainTask+0xd0>
					}
					// Set Door Lock State
					else if (uart_buffer[0] == 0x02) {
 8000936:	4b1d      	ldr	r3, [pc, #116]	; (80009ac <StartMainTask+0x104>)
 8000938:	781b      	ldrb	r3, [r3, #0]
 800093a:	2b02      	cmp	r3, #2
 800093c:	d109      	bne.n	8000952 <StartMainTask+0xaa>
						door_lock_state_command = uart_buffer[1];
 800093e:	4b1b      	ldr	r3, [pc, #108]	; (80009ac <StartMainTask+0x104>)
 8000940:	785b      	ldrb	r3, [r3, #1]
 8000942:	2b00      	cmp	r3, #0
 8000944:	bf14      	ite	ne
 8000946:	2301      	movne	r3, #1
 8000948:	2300      	moveq	r3, #0
 800094a:	b2da      	uxtb	r2, r3
 800094c:	4b1c      	ldr	r3, [pc, #112]	; (80009c0 <StartMainTask+0x118>)
 800094e:	701a      	strb	r2, [r3, #0]
 8000950:	e012      	b.n	8000978 <StartMainTask+0xd0>
						// Get Current Scan Active State
					} else if (uart_buffer[0] == 0x03) {
 8000952:	4b16      	ldr	r3, [pc, #88]	; (80009ac <StartMainTask+0x104>)
 8000954:	781b      	ldrb	r3, [r3, #0]
 8000956:	2b03      	cmp	r3, #3
 8000958:	d10e      	bne.n	8000978 <StartMainTask+0xd0>
						uint8_t payload[3] = { 0x02, scan_active, 0xFF };
 800095a:	2302      	movs	r3, #2
 800095c:	723b      	strb	r3, [r7, #8]
 800095e:	4b19      	ldr	r3, [pc, #100]	; (80009c4 <StartMainTask+0x11c>)
 8000960:	781b      	ldrb	r3, [r3, #0]
 8000962:	727b      	strb	r3, [r7, #9]
 8000964:	23ff      	movs	r3, #255	; 0xff
 8000966:	72bb      	strb	r3, [r7, #10]
						HAL_UART_Transmit(&huart2, payload, 3, 1500);
 8000968:	f107 0108 	add.w	r1, r7, #8
 800096c:	f240 53dc 	movw	r3, #1500	; 0x5dc
 8000970:	2203      	movs	r2, #3
 8000972:	4810      	ldr	r0, [pc, #64]	; (80009b4 <StartMainTask+0x10c>)
 8000974:	f002 f9b7 	bl	8002ce6 <HAL_UART_Transmit>
					}
				}
				uart_index = 0;
 8000978:	4b0d      	ldr	r3, [pc, #52]	; (80009b0 <StartMainTask+0x108>)
 800097a:	2200      	movs	r2, #0
 800097c:	701a      	strb	r2, [r3, #0]
				memset(uart_buffer, 0, 10);
 800097e:	220a      	movs	r2, #10
 8000980:	2100      	movs	r1, #0
 8000982:	480a      	ldr	r0, [pc, #40]	; (80009ac <StartMainTask+0x104>)
 8000984:	f005 fb82 	bl	800608c <memset>
 8000988:	e00b      	b.n	80009a2 <StartMainTask+0xfa>
			} else if (uart_index > sizeof(uart_buffer) - 1) {
 800098a:	4b09      	ldr	r3, [pc, #36]	; (80009b0 <StartMainTask+0x108>)
 800098c:	781b      	ldrb	r3, [r3, #0]
 800098e:	2b09      	cmp	r3, #9
 8000990:	d907      	bls.n	80009a2 <StartMainTask+0xfa>
				memset(uart_buffer, 0, 10);
 8000992:	220a      	movs	r2, #10
 8000994:	2100      	movs	r1, #0
 8000996:	4805      	ldr	r0, [pc, #20]	; (80009ac <StartMainTask+0x104>)
 8000998:	f005 fb78 	bl	800608c <memset>
				uart_index = 0;
 800099c:	4b04      	ldr	r3, [pc, #16]	; (80009b0 <StartMainTask+0x108>)
 800099e:	2200      	movs	r2, #0
 80009a0:	701a      	strb	r2, [r3, #0]
			}
		}
		vTaskDelay(1);
 80009a2:	2001      	movs	r0, #1
 80009a4:	f003 fe7e 	bl	80046a4 <vTaskDelay>
		if (HAL_UART_Receive(&huart2, uart_buffer + uart_index, 1, 100)
 80009a8:	e787      	b.n	80008ba <StartMainTask+0x12>
 80009aa:	bf00      	nop
 80009ac:	20000118 	.word	0x20000118
 80009b0:	20000122 	.word	0x20000122
 80009b4:	200000c4 	.word	0x200000c4
 80009b8:	40020000 	.word	0x40020000
 80009bc:	20000128 	.word	0x20000128
 80009c0:	2000012a 	.word	0x2000012a
 80009c4:	2000012d 	.word	0x2000012d

080009c8 <startDoorHandleTask>:
 * @param argument: Not used
 * @retval None
 */
/* USER CODE END Header_startDoorHandleTask */
void startDoorHandleTask(void *argument)
{
 80009c8:	b580      	push	{r7, lr}
 80009ca:	b082      	sub	sp, #8
 80009cc:	af00      	add	r7, sp, #0
 80009ce:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN startDoorHandleTask */
	/* Infinite loop */
	HAL_GPIO_WritePin(DOOR_LOCK_BANK, DOOR_LOCK_PIN, 1);
 80009d0:	2201      	movs	r2, #1
 80009d2:	f44f 7100 	mov.w	r1, #512	; 0x200
 80009d6:	4858      	ldr	r0, [pc, #352]	; (8000b38 <startDoorHandleTask+0x170>)
 80009d8:	f001 f9d4 	bl	8001d84 <HAL_GPIO_WritePin>
	for (;;) {
		door_state = !HAL_GPIO_ReadPin(DOOR_SENSOR_BANK, DOOR_SENSOR_PIN);
 80009dc:	2180      	movs	r1, #128	; 0x80
 80009de:	4856      	ldr	r0, [pc, #344]	; (8000b38 <startDoorHandleTask+0x170>)
 80009e0:	f001 f9b8 	bl	8001d54 <HAL_GPIO_ReadPin>
 80009e4:	4603      	mov	r3, r0
 80009e6:	2b00      	cmp	r3, #0
 80009e8:	bf0c      	ite	eq
 80009ea:	2301      	moveq	r3, #1
 80009ec:	2300      	movne	r3, #0
 80009ee:	b2da      	uxtb	r2, r3
 80009f0:	4b52      	ldr	r3, [pc, #328]	; (8000b3c <startDoorHandleTask+0x174>)
 80009f2:	701a      	strb	r2, [r3, #0]
		if (door_lock_state != door_lock_state_command) {
 80009f4:	4b52      	ldr	r3, [pc, #328]	; (8000b40 <startDoorHandleTask+0x178>)
 80009f6:	781a      	ldrb	r2, [r3, #0]
 80009f8:	4b52      	ldr	r3, [pc, #328]	; (8000b44 <startDoorHandleTask+0x17c>)
 80009fa:	781b      	ldrb	r3, [r3, #0]
 80009fc:	429a      	cmp	r2, r3
 80009fe:	d062      	beq.n	8000ac6 <startDoorHandleTask+0xfe>
			if (door_lock_state_command == DOOR_LOCK_LOCKED) {
 8000a00:	4b50      	ldr	r3, [pc, #320]	; (8000b44 <startDoorHandleTask+0x17c>)
 8000a02:	781b      	ldrb	r3, [r3, #0]
 8000a04:	2b00      	cmp	r3, #0
 8000a06:	d04b      	beq.n	8000aa0 <startDoorHandleTask+0xd8>
				if (door_state == DOOR_STATE_CLOSED) {
 8000a08:	4b4c      	ldr	r3, [pc, #304]	; (8000b3c <startDoorHandleTask+0x174>)
 8000a0a:	781b      	ldrb	r3, [r3, #0]
 8000a0c:	2b00      	cmp	r3, #0
 8000a0e:	d010      	beq.n	8000a32 <startDoorHandleTask+0x6a>
					osDelay(500);
 8000a10:	f44f 70fa 	mov.w	r0, #500	; 0x1f4
 8000a14:	f002 fe9e 	bl	8003754 <osDelay>
					HAL_GPIO_WritePin(DOOR_LOCK_BANK, DOOR_LOCK_PIN, 1);
 8000a18:	2201      	movs	r2, #1
 8000a1a:	f44f 7100 	mov.w	r1, #512	; 0x200
 8000a1e:	4846      	ldr	r0, [pc, #280]	; (8000b38 <startDoorHandleTask+0x170>)
 8000a20:	f001 f9b0 	bl	8001d84 <HAL_GPIO_WritePin>
					door_lock_state = DOOR_LOCK_LOCKED;
 8000a24:	4b46      	ldr	r3, [pc, #280]	; (8000b40 <startDoorHandleTask+0x178>)
 8000a26:	2201      	movs	r2, #1
 8000a28:	701a      	strb	r2, [r3, #0]
					door_lock_waiting = false;
 8000a2a:	4b47      	ldr	r3, [pc, #284]	; (8000b48 <startDoorHandleTask+0x180>)
 8000a2c:	2200      	movs	r2, #0
 8000a2e:	701a      	strb	r2, [r3, #0]
 8000a30:	e049      	b.n	8000ac6 <startDoorHandleTask+0xfe>
				} else {
					if (!door_lock_waiting) {
 8000a32:	4b45      	ldr	r3, [pc, #276]	; (8000b48 <startDoorHandleTask+0x180>)
 8000a34:	781b      	ldrb	r3, [r3, #0]
 8000a36:	f083 0301 	eor.w	r3, r3, #1
 8000a3a:	b2db      	uxtb	r3, r3
 8000a3c:	2b00      	cmp	r3, #0
 8000a3e:	d008      	beq.n	8000a52 <startDoorHandleTask+0x8a>
						door_lock_command_time = HAL_GetTick();
 8000a40:	f000 faaa 	bl	8000f98 <HAL_GetTick>
 8000a44:	4603      	mov	r3, r0
 8000a46:	4a41      	ldr	r2, [pc, #260]	; (8000b4c <startDoorHandleTask+0x184>)
 8000a48:	6013      	str	r3, [r2, #0]
						door_lock_waiting = true;
 8000a4a:	4b3f      	ldr	r3, [pc, #252]	; (8000b48 <startDoorHandleTask+0x180>)
 8000a4c:	2201      	movs	r2, #1
 8000a4e:	701a      	strb	r2, [r3, #0]
 8000a50:	e039      	b.n	8000ac6 <startDoorHandleTask+0xfe>
					} else {
						if (door_state == DOOR_STATE_OPEN) {
 8000a52:	4b3a      	ldr	r3, [pc, #232]	; (8000b3c <startDoorHandleTask+0x174>)
 8000a54:	781b      	ldrb	r3, [r3, #0]
 8000a56:	f083 0301 	eor.w	r3, r3, #1
 8000a5a:	b2db      	uxtb	r3, r3
 8000a5c:	2b00      	cmp	r3, #0
 8000a5e:	d012      	beq.n	8000a86 <startDoorHandleTask+0xbe>
							if (HAL_GetTick()
 8000a60:	f000 fa9a 	bl	8000f98 <HAL_GetTick>
 8000a64:	4602      	mov	r2, r0
									- door_lock_command_time>DOOR_ERROR_ALARM_DELAY) {
 8000a66:	4b39      	ldr	r3, [pc, #228]	; (8000b4c <startDoorHandleTask+0x184>)
 8000a68:	681b      	ldr	r3, [r3, #0]
 8000a6a:	1ad3      	subs	r3, r2, r3
							if (HAL_GetTick()
 8000a6c:	f242 7210 	movw	r2, #10000	; 0x2710
 8000a70:	4293      	cmp	r3, r2
 8000a72:	d928      	bls.n	8000ac6 <startDoorHandleTask+0xfe>
								alarm_active = true;
 8000a74:	4b36      	ldr	r3, [pc, #216]	; (8000b50 <startDoorHandleTask+0x188>)
 8000a76:	2201      	movs	r2, #1
 8000a78:	701a      	strb	r2, [r3, #0]
								HAL_GPIO_WritePin(ALARM_BANK, ALARM_PIN, 1);
 8000a7a:	2201      	movs	r2, #1
 8000a7c:	2101      	movs	r1, #1
 8000a7e:	4835      	ldr	r0, [pc, #212]	; (8000b54 <startDoorHandleTask+0x18c>)
 8000a80:	f001 f980 	bl	8001d84 <HAL_GPIO_WritePin>
 8000a84:	e01f      	b.n	8000ac6 <startDoorHandleTask+0xfe>
							}
						} else {
							HAL_GPIO_WritePin(DOOR_LOCK_BANK, DOOR_LOCK_PIN, 1);
 8000a86:	2201      	movs	r2, #1
 8000a88:	f44f 7100 	mov.w	r1, #512	; 0x200
 8000a8c:	482a      	ldr	r0, [pc, #168]	; (8000b38 <startDoorHandleTask+0x170>)
 8000a8e:	f001 f979 	bl	8001d84 <HAL_GPIO_WritePin>
							door_lock_waiting = false;
 8000a92:	4b2d      	ldr	r3, [pc, #180]	; (8000b48 <startDoorHandleTask+0x180>)
 8000a94:	2200      	movs	r2, #0
 8000a96:	701a      	strb	r2, [r3, #0]
							door_lock_state = DOOR_LOCK_LOCKED;
 8000a98:	4b29      	ldr	r3, [pc, #164]	; (8000b40 <startDoorHandleTask+0x178>)
 8000a9a:	2201      	movs	r2, #1
 8000a9c:	701a      	strb	r2, [r3, #0]
 8000a9e:	e012      	b.n	8000ac6 <startDoorHandleTask+0xfe>
						}
					}
				}
			} else if (door_lock_state_command == DOOR_LOCK_UNLOCKED) {
 8000aa0:	4b28      	ldr	r3, [pc, #160]	; (8000b44 <startDoorHandleTask+0x17c>)
 8000aa2:	781b      	ldrb	r3, [r3, #0]
 8000aa4:	f083 0301 	eor.w	r3, r3, #1
 8000aa8:	b2db      	uxtb	r3, r3
 8000aaa:	2b00      	cmp	r3, #0
 8000aac:	d00b      	beq.n	8000ac6 <startDoorHandleTask+0xfe>
				HAL_GPIO_WritePin(DOOR_LOCK_BANK, DOOR_LOCK_PIN, 0);
 8000aae:	2200      	movs	r2, #0
 8000ab0:	f44f 7100 	mov.w	r1, #512	; 0x200
 8000ab4:	4820      	ldr	r0, [pc, #128]	; (8000b38 <startDoorHandleTask+0x170>)
 8000ab6:	f001 f965 	bl	8001d84 <HAL_GPIO_WritePin>
				door_lock_state = DOOR_LOCK_UNLOCKED;
 8000aba:	4b21      	ldr	r3, [pc, #132]	; (8000b40 <startDoorHandleTask+0x178>)
 8000abc:	2200      	movs	r2, #0
 8000abe:	701a      	strb	r2, [r3, #0]
				door_lock_waiting = false;
 8000ac0:	4b21      	ldr	r3, [pc, #132]	; (8000b48 <startDoorHandleTask+0x180>)
 8000ac2:	2200      	movs	r2, #0
 8000ac4:	701a      	strb	r2, [r3, #0]
			}
		}
		if (!door_lock_state_command && door_lock_waiting) {
 8000ac6:	4b1f      	ldr	r3, [pc, #124]	; (8000b44 <startDoorHandleTask+0x17c>)
 8000ac8:	781b      	ldrb	r3, [r3, #0]
 8000aca:	f083 0301 	eor.w	r3, r3, #1
 8000ace:	b2db      	uxtb	r3, r3
 8000ad0:	2b00      	cmp	r3, #0
 8000ad2:	d006      	beq.n	8000ae2 <startDoorHandleTask+0x11a>
 8000ad4:	4b1c      	ldr	r3, [pc, #112]	; (8000b48 <startDoorHandleTask+0x180>)
 8000ad6:	781b      	ldrb	r3, [r3, #0]
 8000ad8:	2b00      	cmp	r3, #0
 8000ada:	d002      	beq.n	8000ae2 <startDoorHandleTask+0x11a>
			door_lock_waiting = false;
 8000adc:	4b1a      	ldr	r3, [pc, #104]	; (8000b48 <startDoorHandleTask+0x180>)
 8000ade:	2200      	movs	r2, #0
 8000ae0:	701a      	strb	r2, [r3, #0]
		}
		if (alarm_active && !door_lock_state_command) {
 8000ae2:	4b1b      	ldr	r3, [pc, #108]	; (8000b50 <startDoorHandleTask+0x188>)
 8000ae4:	781b      	ldrb	r3, [r3, #0]
 8000ae6:	2b00      	cmp	r3, #0
 8000ae8:	d00e      	beq.n	8000b08 <startDoorHandleTask+0x140>
 8000aea:	4b16      	ldr	r3, [pc, #88]	; (8000b44 <startDoorHandleTask+0x17c>)
 8000aec:	781b      	ldrb	r3, [r3, #0]
 8000aee:	f083 0301 	eor.w	r3, r3, #1
 8000af2:	b2db      	uxtb	r3, r3
 8000af4:	2b00      	cmp	r3, #0
 8000af6:	d007      	beq.n	8000b08 <startDoorHandleTask+0x140>
			HAL_GPIO_WritePin(ALARM_BANK, ALARM_PIN, 0);
 8000af8:	2200      	movs	r2, #0
 8000afa:	2101      	movs	r1, #1
 8000afc:	4815      	ldr	r0, [pc, #84]	; (8000b54 <startDoorHandleTask+0x18c>)
 8000afe:	f001 f941 	bl	8001d84 <HAL_GPIO_WritePin>
			alarm_active = false;
 8000b02:	4b13      	ldr	r3, [pc, #76]	; (8000b50 <startDoorHandleTask+0x188>)
 8000b04:	2200      	movs	r2, #0
 8000b06:	701a      	strb	r2, [r3, #0]
		}
		if (!door_state && door_lock_state) {
 8000b08:	4b0c      	ldr	r3, [pc, #48]	; (8000b3c <startDoorHandleTask+0x174>)
 8000b0a:	781b      	ldrb	r3, [r3, #0]
 8000b0c:	f083 0301 	eor.w	r3, r3, #1
 8000b10:	b2db      	uxtb	r3, r3
 8000b12:	2b00      	cmp	r3, #0
 8000b14:	d00b      	beq.n	8000b2e <startDoorHandleTask+0x166>
 8000b16:	4b0a      	ldr	r3, [pc, #40]	; (8000b40 <startDoorHandleTask+0x178>)
 8000b18:	781b      	ldrb	r3, [r3, #0]
 8000b1a:	2b00      	cmp	r3, #0
 8000b1c:	d007      	beq.n	8000b2e <startDoorHandleTask+0x166>
			HAL_GPIO_WritePin(ALARM_BANK, ALARM_PIN, 1);
 8000b1e:	2201      	movs	r2, #1
 8000b20:	2101      	movs	r1, #1
 8000b22:	480c      	ldr	r0, [pc, #48]	; (8000b54 <startDoorHandleTask+0x18c>)
 8000b24:	f001 f92e 	bl	8001d84 <HAL_GPIO_WritePin>
			alarm_active = true;
 8000b28:	4b09      	ldr	r3, [pc, #36]	; (8000b50 <startDoorHandleTask+0x188>)
 8000b2a:	2201      	movs	r2, #1
 8000b2c:	701a      	strb	r2, [r3, #0]
		}
		vTaskDelay(50);
 8000b2e:	2032      	movs	r0, #50	; 0x32
 8000b30:	f003 fdb8 	bl	80046a4 <vTaskDelay>
		door_state = !HAL_GPIO_ReadPin(DOOR_SENSOR_BANK, DOOR_SENSOR_PIN);
 8000b34:	e752      	b.n	80009dc <startDoorHandleTask+0x14>
 8000b36:	bf00      	nop
 8000b38:	40020000 	.word	0x40020000
 8000b3c:	20000128 	.word	0x20000128
 8000b40:	20000129 	.word	0x20000129
 8000b44:	2000012a 	.word	0x2000012a
 8000b48:	2000012b 	.word	0x2000012b
 8000b4c:	20000124 	.word	0x20000124
 8000b50:	2000012c 	.word	0x2000012c
 8000b54:	40020800 	.word	0x40020800

08000b58 <StartStateSendTask>:
 * @param argument: Not used
 * @retval None
 */
/* USER CODE END Header_StartStateSendTask */
void StartStateSendTask(void *argument)
{
 8000b58:	b580      	push	{r7, lr}
 8000b5a:	b084      	sub	sp, #16
 8000b5c:	af00      	add	r7, sp, #0
 8000b5e:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN StartStateSendTask */
	/* Infinite loop */
	for (;;) {
		uint8_t payload1[3] = { 0x01, door_state, 0xFF };
 8000b60:	2301      	movs	r3, #1
 8000b62:	733b      	strb	r3, [r7, #12]
 8000b64:	4b0f      	ldr	r3, [pc, #60]	; (8000ba4 <StartStateSendTask+0x4c>)
 8000b66:	781b      	ldrb	r3, [r3, #0]
 8000b68:	737b      	strb	r3, [r7, #13]
 8000b6a:	23ff      	movs	r3, #255	; 0xff
 8000b6c:	73bb      	strb	r3, [r7, #14]
		HAL_UART_Transmit(&huart2, payload1, 3, 1000);
 8000b6e:	f107 010c 	add.w	r1, r7, #12
 8000b72:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8000b76:	2203      	movs	r2, #3
 8000b78:	480b      	ldr	r0, [pc, #44]	; (8000ba8 <StartStateSendTask+0x50>)
 8000b7a:	f002 f8b4 	bl	8002ce6 <HAL_UART_Transmit>
		uint8_t payload2[3] = { 0x02, scan_active, 0xFF };
 8000b7e:	2302      	movs	r3, #2
 8000b80:	723b      	strb	r3, [r7, #8]
 8000b82:	4b0a      	ldr	r3, [pc, #40]	; (8000bac <StartStateSendTask+0x54>)
 8000b84:	781b      	ldrb	r3, [r3, #0]
 8000b86:	727b      	strb	r3, [r7, #9]
 8000b88:	23ff      	movs	r3, #255	; 0xff
 8000b8a:	72bb      	strb	r3, [r7, #10]
		HAL_UART_Transmit(&huart2, payload2, 3, 1000);
 8000b8c:	f107 0108 	add.w	r1, r7, #8
 8000b90:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8000b94:	2203      	movs	r2, #3
 8000b96:	4804      	ldr	r0, [pc, #16]	; (8000ba8 <StartStateSendTask+0x50>)
 8000b98:	f002 f8a5 	bl	8002ce6 <HAL_UART_Transmit>
		osDelay(200);
 8000b9c:	20c8      	movs	r0, #200	; 0xc8
 8000b9e:	f002 fdd9 	bl	8003754 <osDelay>
	for (;;) {
 8000ba2:	e7dd      	b.n	8000b60 <StartStateSendTask+0x8>
 8000ba4:	20000128 	.word	0x20000128
 8000ba8:	200000c4 	.word	0x200000c4
 8000bac:	2000012d 	.word	0x2000012d

08000bb0 <StartADCReqTask>:
* @param argument: Not used
* @retval None
*/
/* USER CODE END Header_StartADCReqTask */
void StartADCReqTask(void *argument)
{
 8000bb0:	b580      	push	{r7, lr}
 8000bb2:	b082      	sub	sp, #8
 8000bb4:	af00      	add	r7, sp, #0
 8000bb6:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN StartADCReqTask */
  /* Infinite loop */
  for(;;)
  {
	HAL_ADC_Start_IT(&hadc1);
 8000bb8:	4803      	ldr	r0, [pc, #12]	; (8000bc8 <StartADCReqTask+0x18>)
 8000bba:	f000 fa3d 	bl	8001038 <HAL_ADC_Start_IT>
    osDelay(500);
 8000bbe:	f44f 70fa 	mov.w	r0, #500	; 0x1f4
 8000bc2:	f002 fdc7 	bl	8003754 <osDelay>
	HAL_ADC_Start_IT(&hadc1);
 8000bc6:	e7f7      	b.n	8000bb8 <StartADCReqTask+0x8>
 8000bc8:	2000007c 	.word	0x2000007c

08000bcc <HAL_TIM_PeriodElapsedCallback>:
  * a global variable "uwTick" used as application time base.
  * @param  htim : TIM handle
  * @retval None
  */
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
 8000bcc:	b580      	push	{r7, lr}
 8000bce:	b082      	sub	sp, #8
 8000bd0:	af00      	add	r7, sp, #0
 8000bd2:	6078      	str	r0, [r7, #4]
  /* USER CODE BEGIN Callback 0 */

  /* USER CODE END Callback 0 */
  if (htim->Instance == TIM1) {
 8000bd4:	687b      	ldr	r3, [r7, #4]
 8000bd6:	681b      	ldr	r3, [r3, #0]
 8000bd8:	4a04      	ldr	r2, [pc, #16]	; (8000bec <HAL_TIM_PeriodElapsedCallback+0x20>)
 8000bda:	4293      	cmp	r3, r2
 8000bdc:	d101      	bne.n	8000be2 <HAL_TIM_PeriodElapsedCallback+0x16>
    HAL_IncTick();
 8000bde:	f000 f9c7 	bl	8000f70 <HAL_IncTick>
  }
  /* USER CODE BEGIN Callback 1 */

  /* USER CODE END Callback 1 */
}
 8000be2:	bf00      	nop
 8000be4:	3708      	adds	r7, #8
 8000be6:	46bd      	mov	sp, r7
 8000be8:	bd80      	pop	{r7, pc}
 8000bea:	bf00      	nop
 8000bec:	40010000 	.word	0x40010000

08000bf0 <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 8000bf0:	b480      	push	{r7}
 8000bf2:	af00      	add	r7, sp, #0
  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
           Can only be executed in Privileged modes.
 */
__STATIC_FORCEINLINE void __disable_irq(void)
{
  __ASM volatile ("cpsid i" : : : "memory");
 8000bf4:	b672      	cpsid	i
}
 8000bf6:	bf00      	nop
  /* USER CODE BEGIN Error_Handler_Debug */
	/* User can add his own implementation to report the HAL error return state */
	__disable_irq();
	while (1) {
 8000bf8:	e7fe      	b.n	8000bf8 <Error_Handler+0x8>
	...

08000bfc <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8000bfc:	b580      	push	{r7, lr}
 8000bfe:	b082      	sub	sp, #8
 8000c00:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_SYSCFG_CLK_ENABLE();
 8000c02:	2300      	movs	r3, #0
 8000c04:	607b      	str	r3, [r7, #4]
 8000c06:	4b12      	ldr	r3, [pc, #72]	; (8000c50 <HAL_MspInit+0x54>)
 8000c08:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000c0a:	4a11      	ldr	r2, [pc, #68]	; (8000c50 <HAL_MspInit+0x54>)
 8000c0c:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 8000c10:	6453      	str	r3, [r2, #68]	; 0x44
 8000c12:	4b0f      	ldr	r3, [pc, #60]	; (8000c50 <HAL_MspInit+0x54>)
 8000c14:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000c16:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 8000c1a:	607b      	str	r3, [r7, #4]
 8000c1c:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 8000c1e:	2300      	movs	r3, #0
 8000c20:	603b      	str	r3, [r7, #0]
 8000c22:	4b0b      	ldr	r3, [pc, #44]	; (8000c50 <HAL_MspInit+0x54>)
 8000c24:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000c26:	4a0a      	ldr	r2, [pc, #40]	; (8000c50 <HAL_MspInit+0x54>)
 8000c28:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8000c2c:	6413      	str	r3, [r2, #64]	; 0x40
 8000c2e:	4b08      	ldr	r3, [pc, #32]	; (8000c50 <HAL_MspInit+0x54>)
 8000c30:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000c32:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000c36:	603b      	str	r3, [r7, #0]
 8000c38:	683b      	ldr	r3, [r7, #0]

  /* System interrupt init*/
  /* PendSV_IRQn interrupt configuration */
  HAL_NVIC_SetPriority(PendSV_IRQn, 15, 0);
 8000c3a:	2200      	movs	r2, #0
 8000c3c:	210f      	movs	r1, #15
 8000c3e:	f06f 0001 	mvn.w	r0, #1
 8000c42:	f000 fed9 	bl	80019f8 <HAL_NVIC_SetPriority>

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8000c46:	bf00      	nop
 8000c48:	3708      	adds	r7, #8
 8000c4a:	46bd      	mov	sp, r7
 8000c4c:	bd80      	pop	{r7, pc}
 8000c4e:	bf00      	nop
 8000c50:	40023800 	.word	0x40023800

08000c54 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
 8000c54:	b580      	push	{r7, lr}
 8000c56:	b08a      	sub	sp, #40	; 0x28
 8000c58:	af00      	add	r7, sp, #0
 8000c5a:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000c5c:	f107 0314 	add.w	r3, r7, #20
 8000c60:	2200      	movs	r2, #0
 8000c62:	601a      	str	r2, [r3, #0]
 8000c64:	605a      	str	r2, [r3, #4]
 8000c66:	609a      	str	r2, [r3, #8]
 8000c68:	60da      	str	r2, [r3, #12]
 8000c6a:	611a      	str	r2, [r3, #16]
  if(hadc->Instance==ADC1)
 8000c6c:	687b      	ldr	r3, [r7, #4]
 8000c6e:	681b      	ldr	r3, [r3, #0]
 8000c70:	4a1b      	ldr	r2, [pc, #108]	; (8000ce0 <HAL_ADC_MspInit+0x8c>)
 8000c72:	4293      	cmp	r3, r2
 8000c74:	d12f      	bne.n	8000cd6 <HAL_ADC_MspInit+0x82>
  {
  /* USER CODE BEGIN ADC1_MspInit 0 */

  /* USER CODE END ADC1_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_ADC1_CLK_ENABLE();
 8000c76:	2300      	movs	r3, #0
 8000c78:	613b      	str	r3, [r7, #16]
 8000c7a:	4b1a      	ldr	r3, [pc, #104]	; (8000ce4 <HAL_ADC_MspInit+0x90>)
 8000c7c:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000c7e:	4a19      	ldr	r2, [pc, #100]	; (8000ce4 <HAL_ADC_MspInit+0x90>)
 8000c80:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8000c84:	6453      	str	r3, [r2, #68]	; 0x44
 8000c86:	4b17      	ldr	r3, [pc, #92]	; (8000ce4 <HAL_ADC_MspInit+0x90>)
 8000c88:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000c8a:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8000c8e:	613b      	str	r3, [r7, #16]
 8000c90:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8000c92:	2300      	movs	r3, #0
 8000c94:	60fb      	str	r3, [r7, #12]
 8000c96:	4b13      	ldr	r3, [pc, #76]	; (8000ce4 <HAL_ADC_MspInit+0x90>)
 8000c98:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000c9a:	4a12      	ldr	r2, [pc, #72]	; (8000ce4 <HAL_ADC_MspInit+0x90>)
 8000c9c:	f043 0301 	orr.w	r3, r3, #1
 8000ca0:	6313      	str	r3, [r2, #48]	; 0x30
 8000ca2:	4b10      	ldr	r3, [pc, #64]	; (8000ce4 <HAL_ADC_MspInit+0x90>)
 8000ca4:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000ca6:	f003 0301 	and.w	r3, r3, #1
 8000caa:	60fb      	str	r3, [r7, #12]
 8000cac:	68fb      	ldr	r3, [r7, #12]
    /**ADC1 GPIO Configuration
    PA1     ------> ADC1_IN1
    */
    GPIO_InitStruct.Pin = GPIO_PIN_1;
 8000cae:	2302      	movs	r3, #2
 8000cb0:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
 8000cb2:	2303      	movs	r3, #3
 8000cb4:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000cb6:	2300      	movs	r3, #0
 8000cb8:	61fb      	str	r3, [r7, #28]
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000cba:	f107 0314 	add.w	r3, r7, #20
 8000cbe:	4619      	mov	r1, r3
 8000cc0:	4809      	ldr	r0, [pc, #36]	; (8000ce8 <HAL_ADC_MspInit+0x94>)
 8000cc2:	f000 fec3 	bl	8001a4c <HAL_GPIO_Init>

    /* ADC1 interrupt Init */
    HAL_NVIC_SetPriority(ADC_IRQn, 5, 0);
 8000cc6:	2200      	movs	r2, #0
 8000cc8:	2105      	movs	r1, #5
 8000cca:	2012      	movs	r0, #18
 8000ccc:	f000 fe94 	bl	80019f8 <HAL_NVIC_SetPriority>
    HAL_NVIC_EnableIRQ(ADC_IRQn);
 8000cd0:	2012      	movs	r0, #18
 8000cd2:	f000 fead 	bl	8001a30 <HAL_NVIC_EnableIRQ>
  /* USER CODE BEGIN ADC1_MspInit 1 */

  /* USER CODE END ADC1_MspInit 1 */
  }

}
 8000cd6:	bf00      	nop
 8000cd8:	3728      	adds	r7, #40	; 0x28
 8000cda:	46bd      	mov	sp, r7
 8000cdc:	bd80      	pop	{r7, pc}
 8000cde:	bf00      	nop
 8000ce0:	40012000 	.word	0x40012000
 8000ce4:	40023800 	.word	0x40023800
 8000ce8:	40020000 	.word	0x40020000

08000cec <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
 8000cec:	b580      	push	{r7, lr}
 8000cee:	b08a      	sub	sp, #40	; 0x28
 8000cf0:	af00      	add	r7, sp, #0
 8000cf2:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000cf4:	f107 0314 	add.w	r3, r7, #20
 8000cf8:	2200      	movs	r2, #0
 8000cfa:	601a      	str	r2, [r3, #0]
 8000cfc:	605a      	str	r2, [r3, #4]
 8000cfe:	609a      	str	r2, [r3, #8]
 8000d00:	60da      	str	r2, [r3, #12]
 8000d02:	611a      	str	r2, [r3, #16]
  if(huart->Instance==USART2)
 8000d04:	687b      	ldr	r3, [r7, #4]
 8000d06:	681b      	ldr	r3, [r3, #0]
 8000d08:	4a19      	ldr	r2, [pc, #100]	; (8000d70 <HAL_UART_MspInit+0x84>)
 8000d0a:	4293      	cmp	r3, r2
 8000d0c:	d12b      	bne.n	8000d66 <HAL_UART_MspInit+0x7a>
  {
  /* USER CODE BEGIN USART2_MspInit 0 */

  /* USER CODE END USART2_MspInit 0 */
    /* Peripheral clock enable */
    __HAL_RCC_USART2_CLK_ENABLE();
 8000d0e:	2300      	movs	r3, #0
 8000d10:	613b      	str	r3, [r7, #16]
 8000d12:	4b18      	ldr	r3, [pc, #96]	; (8000d74 <HAL_UART_MspInit+0x88>)
 8000d14:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000d16:	4a17      	ldr	r2, [pc, #92]	; (8000d74 <HAL_UART_MspInit+0x88>)
 8000d18:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8000d1c:	6413      	str	r3, [r2, #64]	; 0x40
 8000d1e:	4b15      	ldr	r3, [pc, #84]	; (8000d74 <HAL_UART_MspInit+0x88>)
 8000d20:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000d22:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8000d26:	613b      	str	r3, [r7, #16]
 8000d28:	693b      	ldr	r3, [r7, #16]

    __HAL_RCC_GPIOA_CLK_ENABLE();
 8000d2a:	2300      	movs	r3, #0
 8000d2c:	60fb      	str	r3, [r7, #12]
 8000d2e:	4b11      	ldr	r3, [pc, #68]	; (8000d74 <HAL_UART_MspInit+0x88>)
 8000d30:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000d32:	4a10      	ldr	r2, [pc, #64]	; (8000d74 <HAL_UART_MspInit+0x88>)
 8000d34:	f043 0301 	orr.w	r3, r3, #1
 8000d38:	6313      	str	r3, [r2, #48]	; 0x30
 8000d3a:	4b0e      	ldr	r3, [pc, #56]	; (8000d74 <HAL_UART_MspInit+0x88>)
 8000d3c:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8000d3e:	f003 0301 	and.w	r3, r3, #1
 8000d42:	60fb      	str	r3, [r7, #12]
 8000d44:	68fb      	ldr	r3, [r7, #12]
    /**USART2 GPIO Configuration
    PA2     ------> USART2_TX
    PA3     ------> USART2_RX
    */
    GPIO_InitStruct.Pin = USART_TX_Pin|USART_RX_Pin;
 8000d46:	230c      	movs	r3, #12
 8000d48:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
 8000d4a:	2302      	movs	r3, #2
 8000d4c:	61bb      	str	r3, [r7, #24]
    GPIO_InitStruct.Pull = GPIO_NOPULL;
 8000d4e:	2300      	movs	r3, #0
 8000d50:	61fb      	str	r3, [r7, #28]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
 8000d52:	2303      	movs	r3, #3
 8000d54:	623b      	str	r3, [r7, #32]
    GPIO_InitStruct.Alternate = GPIO_AF7_USART2;
 8000d56:	2307      	movs	r3, #7
 8000d58:	627b      	str	r3, [r7, #36]	; 0x24
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
 8000d5a:	f107 0314 	add.w	r3, r7, #20
 8000d5e:	4619      	mov	r1, r3
 8000d60:	4805      	ldr	r0, [pc, #20]	; (8000d78 <HAL_UART_MspInit+0x8c>)
 8000d62:	f000 fe73 	bl	8001a4c <HAL_GPIO_Init>
  /* USER CODE BEGIN USART2_MspInit 1 */

  /* USER CODE END USART2_MspInit 1 */
  }

}
 8000d66:	bf00      	nop
 8000d68:	3728      	adds	r7, #40	; 0x28
 8000d6a:	46bd      	mov	sp, r7
 8000d6c:	bd80      	pop	{r7, pc}
 8000d6e:	bf00      	nop
 8000d70:	40004400 	.word	0x40004400
 8000d74:	40023800 	.word	0x40023800
 8000d78:	40020000 	.word	0x40020000

08000d7c <HAL_InitTick>:
  *         reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
  * @param  TickPriority: Tick interrupt priority.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8000d7c:	b580      	push	{r7, lr}
 8000d7e:	b08c      	sub	sp, #48	; 0x30
 8000d80:	af00      	add	r7, sp, #0
 8000d82:	6078      	str	r0, [r7, #4]
  RCC_ClkInitTypeDef    clkconfig;
  uint32_t              uwTimclock = 0U;
 8000d84:	2300      	movs	r3, #0
 8000d86:	62bb      	str	r3, [r7, #40]	; 0x28

  uint32_t              uwPrescalerValue = 0U;
 8000d88:	2300      	movs	r3, #0
 8000d8a:	627b      	str	r3, [r7, #36]	; 0x24
  uint32_t              pFLatency;
  HAL_StatusTypeDef     status;

  /* Enable TIM1 clock */
  __HAL_RCC_TIM1_CLK_ENABLE();
 8000d8c:	2300      	movs	r3, #0
 8000d8e:	60bb      	str	r3, [r7, #8]
 8000d90:	4b2e      	ldr	r3, [pc, #184]	; (8000e4c <HAL_InitTick+0xd0>)
 8000d92:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000d94:	4a2d      	ldr	r2, [pc, #180]	; (8000e4c <HAL_InitTick+0xd0>)
 8000d96:	f043 0301 	orr.w	r3, r3, #1
 8000d9a:	6453      	str	r3, [r2, #68]	; 0x44
 8000d9c:	4b2b      	ldr	r3, [pc, #172]	; (8000e4c <HAL_InitTick+0xd0>)
 8000d9e:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8000da0:	f003 0301 	and.w	r3, r3, #1
 8000da4:	60bb      	str	r3, [r7, #8]
 8000da6:	68bb      	ldr	r3, [r7, #8]

  /* Get clock configuration */
  HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
 8000da8:	f107 020c 	add.w	r2, r7, #12
 8000dac:	f107 0310 	add.w	r3, r7, #16
 8000db0:	4611      	mov	r1, r2
 8000db2:	4618      	mov	r0, r3
 8000db4:	f001 fc98 	bl	80026e8 <HAL_RCC_GetClockConfig>

  /* Compute TIM1 clock */
      uwTimclock = HAL_RCC_GetPCLK2Freq();
 8000db8:	f001 fc82 	bl	80026c0 <HAL_RCC_GetPCLK2Freq>
 8000dbc:	62b8      	str	r0, [r7, #40]	; 0x28

  /* Compute the prescaler value to have TIM1 counter clock equal to 1MHz */
  uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
 8000dbe:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8000dc0:	4a23      	ldr	r2, [pc, #140]	; (8000e50 <HAL_InitTick+0xd4>)
 8000dc2:	fba2 2303 	umull	r2, r3, r2, r3
 8000dc6:	0c9b      	lsrs	r3, r3, #18
 8000dc8:	3b01      	subs	r3, #1
 8000dca:	627b      	str	r3, [r7, #36]	; 0x24

  /* Initialize TIM1 */
  htim1.Instance = TIM1;
 8000dcc:	4b21      	ldr	r3, [pc, #132]	; (8000e54 <HAL_InitTick+0xd8>)
 8000dce:	4a22      	ldr	r2, [pc, #136]	; (8000e58 <HAL_InitTick+0xdc>)
 8000dd0:	601a      	str	r2, [r3, #0]
  + Period = [(TIM1CLK/1000) - 1]. to have a (1/1000) s time base.
  + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
  + ClockDivision = 0
  + Counter direction = Up
  */
  htim1.Init.Period = (1000000U / 1000U) - 1U;
 8000dd2:	4b20      	ldr	r3, [pc, #128]	; (8000e54 <HAL_InitTick+0xd8>)
 8000dd4:	f240 32e7 	movw	r2, #999	; 0x3e7
 8000dd8:	60da      	str	r2, [r3, #12]
  htim1.Init.Prescaler = uwPrescalerValue;
 8000dda:	4a1e      	ldr	r2, [pc, #120]	; (8000e54 <HAL_InitTick+0xd8>)
 8000ddc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8000dde:	6053      	str	r3, [r2, #4]
  htim1.Init.ClockDivision = 0;
 8000de0:	4b1c      	ldr	r3, [pc, #112]	; (8000e54 <HAL_InitTick+0xd8>)
 8000de2:	2200      	movs	r2, #0
 8000de4:	611a      	str	r2, [r3, #16]
  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
 8000de6:	4b1b      	ldr	r3, [pc, #108]	; (8000e54 <HAL_InitTick+0xd8>)
 8000de8:	2200      	movs	r2, #0
 8000dea:	609a      	str	r2, [r3, #8]
  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
 8000dec:	4b19      	ldr	r3, [pc, #100]	; (8000e54 <HAL_InitTick+0xd8>)
 8000dee:	2200      	movs	r2, #0
 8000df0:	619a      	str	r2, [r3, #24]

  status = HAL_TIM_Base_Init(&htim1);
 8000df2:	4818      	ldr	r0, [pc, #96]	; (8000e54 <HAL_InitTick+0xd8>)
 8000df4:	f001 fcaa 	bl	800274c <HAL_TIM_Base_Init>
 8000df8:	4603      	mov	r3, r0
 8000dfa:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
  if (status == HAL_OK)
 8000dfe:	f897 302f 	ldrb.w	r3, [r7, #47]	; 0x2f
 8000e02:	2b00      	cmp	r3, #0
 8000e04:	d11b      	bne.n	8000e3e <HAL_InitTick+0xc2>
  {
    /* Start the TIM time Base generation in interrupt mode */
    status = HAL_TIM_Base_Start_IT(&htim1);
 8000e06:	4813      	ldr	r0, [pc, #76]	; (8000e54 <HAL_InitTick+0xd8>)
 8000e08:	f001 fcfa 	bl	8002800 <HAL_TIM_Base_Start_IT>
 8000e0c:	4603      	mov	r3, r0
 8000e0e:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
    if (status == HAL_OK)
 8000e12:	f897 302f 	ldrb.w	r3, [r7, #47]	; 0x2f
 8000e16:	2b00      	cmp	r3, #0
 8000e18:	d111      	bne.n	8000e3e <HAL_InitTick+0xc2>
    {
    /* Enable the TIM1 global Interrupt */
        HAL_NVIC_EnableIRQ(TIM1_UP_TIM10_IRQn);
 8000e1a:	2019      	movs	r0, #25
 8000e1c:	f000 fe08 	bl	8001a30 <HAL_NVIC_EnableIRQ>
      /* Configure the SysTick IRQ priority */
      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8000e20:	687b      	ldr	r3, [r7, #4]
 8000e22:	2b0f      	cmp	r3, #15
 8000e24:	d808      	bhi.n	8000e38 <HAL_InitTick+0xbc>
      {
        /* Configure the TIM IRQ priority */
        HAL_NVIC_SetPriority(TIM1_UP_TIM10_IRQn, TickPriority, 0U);
 8000e26:	2200      	movs	r2, #0
 8000e28:	6879      	ldr	r1, [r7, #4]
 8000e2a:	2019      	movs	r0, #25
 8000e2c:	f000 fde4 	bl	80019f8 <HAL_NVIC_SetPriority>
        uwTickPrio = TickPriority;
 8000e30:	4a0a      	ldr	r2, [pc, #40]	; (8000e5c <HAL_InitTick+0xe0>)
 8000e32:	687b      	ldr	r3, [r7, #4]
 8000e34:	6013      	str	r3, [r2, #0]
 8000e36:	e002      	b.n	8000e3e <HAL_InitTick+0xc2>
      }
      else
      {
        status = HAL_ERROR;
 8000e38:	2301      	movs	r3, #1
 8000e3a:	f887 302f 	strb.w	r3, [r7, #47]	; 0x2f
      }
    }
  }

 /* Return function status */
  return status;
 8000e3e:	f897 302f 	ldrb.w	r3, [r7, #47]	; 0x2f
}
 8000e42:	4618      	mov	r0, r3
 8000e44:	3730      	adds	r7, #48	; 0x30
 8000e46:	46bd      	mov	sp, r7
 8000e48:	bd80      	pop	{r7, pc}
 8000e4a:	bf00      	nop
 8000e4c:	40023800 	.word	0x40023800
 8000e50:	431bde83 	.word	0x431bde83
 8000e54:	20000130 	.word	0x20000130
 8000e58:	40010000 	.word	0x40010000
 8000e5c:	20000004 	.word	0x20000004

08000e60 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 8000e60:	b480      	push	{r7}
 8000e62:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 8000e64:	e7fe      	b.n	8000e64 <NMI_Handler+0x4>

08000e66 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8000e66:	b480      	push	{r7}
 8000e68:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8000e6a:	e7fe      	b.n	8000e6a <HardFault_Handler+0x4>

08000e6c <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8000e6c:	b480      	push	{r7}
 8000e6e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8000e70:	e7fe      	b.n	8000e70 <MemManage_Handler+0x4>

08000e72 <BusFault_Handler>:

/**
  * @brief This function handles Pre-fetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8000e72:	b480      	push	{r7}
 8000e74:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8000e76:	e7fe      	b.n	8000e76 <BusFault_Handler+0x4>

08000e78 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8000e78:	b480      	push	{r7}
 8000e7a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8000e7c:	e7fe      	b.n	8000e7c <UsageFault_Handler+0x4>

08000e7e <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8000e7e:	b480      	push	{r7}
 8000e80:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8000e82:	bf00      	nop
 8000e84:	46bd      	mov	sp, r7
 8000e86:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000e8a:	4770      	bx	lr

08000e8c <ADC_IRQHandler>:

/**
  * @brief This function handles ADC1 global interrupt.
  */
void ADC_IRQHandler(void)
{
 8000e8c:	b580      	push	{r7, lr}
 8000e8e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN ADC_IRQn 0 */

  /* USER CODE END ADC_IRQn 0 */
  HAL_ADC_IRQHandler(&hadc1);
 8000e90:	4802      	ldr	r0, [pc, #8]	; (8000e9c <ADC_IRQHandler+0x10>)
 8000e92:	f000 f98f 	bl	80011b4 <HAL_ADC_IRQHandler>
  /* USER CODE BEGIN ADC_IRQn 1 */

  /* USER CODE END ADC_IRQn 1 */
}
 8000e96:	bf00      	nop
 8000e98:	bd80      	pop	{r7, pc}
 8000e9a:	bf00      	nop
 8000e9c:	2000007c 	.word	0x2000007c

08000ea0 <TIM1_UP_TIM10_IRQHandler>:

/**
  * @brief This function handles TIM1 update interrupt and TIM10 global interrupt.
  */
void TIM1_UP_TIM10_IRQHandler(void)
{
 8000ea0:	b580      	push	{r7, lr}
 8000ea2:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 0 */

  /* USER CODE END TIM1_UP_TIM10_IRQn 0 */
  HAL_TIM_IRQHandler(&htim1);
 8000ea4:	4802      	ldr	r0, [pc, #8]	; (8000eb0 <TIM1_UP_TIM10_IRQHandler+0x10>)
 8000ea6:	f001 fd0d 	bl	80028c4 <HAL_TIM_IRQHandler>
  /* USER CODE BEGIN TIM1_UP_TIM10_IRQn 1 */

  /* USER CODE END TIM1_UP_TIM10_IRQn 1 */
}
 8000eaa:	bf00      	nop
 8000eac:	bd80      	pop	{r7, pc}
 8000eae:	bf00      	nop
 8000eb0:	20000130 	.word	0x20000130

08000eb4 <SystemInit>:
  *         configuration.
  * @param  None
  * @retval None
  */
void SystemInit(void)
{
 8000eb4:	b480      	push	{r7}
 8000eb6:	af00      	add	r7, sp, #0
  /* FPU settings ------------------------------------------------------------*/
  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 8000eb8:	4b06      	ldr	r3, [pc, #24]	; (8000ed4 <SystemInit+0x20>)
 8000eba:	f8d3 3088 	ldr.w	r3, [r3, #136]	; 0x88
 8000ebe:	4a05      	ldr	r2, [pc, #20]	; (8000ed4 <SystemInit+0x20>)
 8000ec0:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
 8000ec4:	f8c2 3088 	str.w	r3, [r2, #136]	; 0x88

  /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
 8000ec8:	bf00      	nop
 8000eca:	46bd      	mov	sp, r7
 8000ecc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000ed0:	4770      	bx	lr
 8000ed2:	bf00      	nop
 8000ed4:	e000ed00 	.word	0xe000ed00

08000ed8 <Reset_Handler>:

    .section  .text.Reset_Handler
  .weak  Reset_Handler
  .type  Reset_Handler, %function
Reset_Handler:  
  ldr   sp, =_estack    		 /* set stack pointer */
 8000ed8:	f8df d034 	ldr.w	sp, [pc, #52]	; 8000f10 <LoopFillZerobss+0x12>

/* Copy the data segment initializers from flash to SRAM */  
  ldr r0, =_sdata
 8000edc:	480d      	ldr	r0, [pc, #52]	; (8000f14 <LoopFillZerobss+0x16>)
  ldr r1, =_edata
 8000ede:	490e      	ldr	r1, [pc, #56]	; (8000f18 <LoopFillZerobss+0x1a>)
  ldr r2, =_sidata
 8000ee0:	4a0e      	ldr	r2, [pc, #56]	; (8000f1c <LoopFillZerobss+0x1e>)
  movs r3, #0
 8000ee2:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8000ee4:	e002      	b.n	8000eec <LoopCopyDataInit>

08000ee6 <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 8000ee6:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 8000ee8:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 8000eea:	3304      	adds	r3, #4

08000eec <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8000eec:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8000eee:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8000ef0:	d3f9      	bcc.n	8000ee6 <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 8000ef2:	4a0b      	ldr	r2, [pc, #44]	; (8000f20 <LoopFillZerobss+0x22>)
  ldr r4, =_ebss
 8000ef4:	4c0b      	ldr	r4, [pc, #44]	; (8000f24 <LoopFillZerobss+0x26>)
  movs r3, #0
 8000ef6:	2300      	movs	r3, #0
  b LoopFillZerobss
 8000ef8:	e001      	b.n	8000efe <LoopFillZerobss>

08000efa <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 8000efa:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8000efc:	3204      	adds	r2, #4

08000efe <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8000efe:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8000f00:	d3fb      	bcc.n	8000efa <FillZerobss>

/* Call the clock system initialization function.*/
  bl  SystemInit   
 8000f02:	f7ff ffd7 	bl	8000eb4 <SystemInit>
/* Call static constructors */
    bl __libc_init_array
 8000f06:	f005 f91f 	bl	8006148 <__libc_init_array>
/* Call the application's entry point.*/
  bl  main
 8000f0a:	f7ff fb07 	bl	800051c <main>
  bx  lr    
 8000f0e:	4770      	bx	lr
  ldr   sp, =_estack    		 /* set stack pointer */
 8000f10:	20020000 	.word	0x20020000
  ldr r0, =_sdata
 8000f14:	20000000 	.word	0x20000000
  ldr r1, =_edata
 8000f18:	20000060 	.word	0x20000060
  ldr r2, =_sidata
 8000f1c:	0800637c 	.word	0x0800637c
  ldr r2, =_sbss
 8000f20:	20000060 	.word	0x20000060
  ldr r4, =_ebss
 8000f24:	20004ca4 	.word	0x20004ca4

08000f28 <DMA1_Stream0_IRQHandler>:
 * @retval None       
*/
    .section  .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b  Infinite_Loop
 8000f28:	e7fe      	b.n	8000f28 <DMA1_Stream0_IRQHandler>
	...

08000f2c <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 8000f2c:	b580      	push	{r7, lr}
 8000f2e:	af00      	add	r7, sp, #0
  /* Configure Flash prefetch, Instruction cache, Data cache */ 
#if (INSTRUCTION_CACHE_ENABLE != 0U)
  __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
 8000f30:	4b0e      	ldr	r3, [pc, #56]	; (8000f6c <HAL_Init+0x40>)
 8000f32:	681b      	ldr	r3, [r3, #0]
 8000f34:	4a0d      	ldr	r2, [pc, #52]	; (8000f6c <HAL_Init+0x40>)
 8000f36:	f443 7300 	orr.w	r3, r3, #512	; 0x200
 8000f3a:	6013      	str	r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */

#if (DATA_CACHE_ENABLE != 0U)
  __HAL_FLASH_DATA_CACHE_ENABLE();
 8000f3c:	4b0b      	ldr	r3, [pc, #44]	; (8000f6c <HAL_Init+0x40>)
 8000f3e:	681b      	ldr	r3, [r3, #0]
 8000f40:	4a0a      	ldr	r2, [pc, #40]	; (8000f6c <HAL_Init+0x40>)
 8000f42:	f443 6380 	orr.w	r3, r3, #1024	; 0x400
 8000f46:	6013      	str	r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */

#if (PREFETCH_ENABLE != 0U)
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000f48:	4b08      	ldr	r3, [pc, #32]	; (8000f6c <HAL_Init+0x40>)
 8000f4a:	681b      	ldr	r3, [r3, #0]
 8000f4c:	4a07      	ldr	r2, [pc, #28]	; (8000f6c <HAL_Init+0x40>)
 8000f4e:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8000f52:	6013      	str	r3, [r2, #0]
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8000f54:	2003      	movs	r0, #3
 8000f56:	f000 fd44 	bl	80019e2 <HAL_NVIC_SetPriorityGrouping>

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  HAL_InitTick(TICK_INT_PRIORITY);
 8000f5a:	200f      	movs	r0, #15
 8000f5c:	f7ff ff0e 	bl	8000d7c <HAL_InitTick>

  /* Init the low level hardware */
  HAL_MspInit();
 8000f60:	f7ff fe4c 	bl	8000bfc <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 8000f64:	2300      	movs	r3, #0
}
 8000f66:	4618      	mov	r0, r3
 8000f68:	bd80      	pop	{r7, pc}
 8000f6a:	bf00      	nop
 8000f6c:	40023c00 	.word	0x40023c00

08000f70 <HAL_IncTick>:
 * @note This function is declared as __weak to be overwritten in case of other 
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8000f70:	b480      	push	{r7}
 8000f72:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 8000f74:	4b06      	ldr	r3, [pc, #24]	; (8000f90 <HAL_IncTick+0x20>)
 8000f76:	781b      	ldrb	r3, [r3, #0]
 8000f78:	461a      	mov	r2, r3
 8000f7a:	4b06      	ldr	r3, [pc, #24]	; (8000f94 <HAL_IncTick+0x24>)
 8000f7c:	681b      	ldr	r3, [r3, #0]
 8000f7e:	4413      	add	r3, r2
 8000f80:	4a04      	ldr	r2, [pc, #16]	; (8000f94 <HAL_IncTick+0x24>)
 8000f82:	6013      	str	r3, [r2, #0]
}
 8000f84:	bf00      	nop
 8000f86:	46bd      	mov	sp, r7
 8000f88:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000f8c:	4770      	bx	lr
 8000f8e:	bf00      	nop
 8000f90:	20000008 	.word	0x20000008
 8000f94:	20000178 	.word	0x20000178

08000f98 <HAL_GetTick>:
  * @note This function is declared as __weak to be overwritten in case of other 
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8000f98:	b480      	push	{r7}
 8000f9a:	af00      	add	r7, sp, #0
  return uwTick;
 8000f9c:	4b03      	ldr	r3, [pc, #12]	; (8000fac <HAL_GetTick+0x14>)
 8000f9e:	681b      	ldr	r3, [r3, #0]
}
 8000fa0:	4618      	mov	r0, r3
 8000fa2:	46bd      	mov	sp, r7
 8000fa4:	f85d 7b04 	ldr.w	r7, [sp], #4
 8000fa8:	4770      	bx	lr
 8000faa:	bf00      	nop
 8000fac:	20000178 	.word	0x20000178

08000fb0 <HAL_ADC_Init>:
  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
  *         the configuration information for the specified ADC.  
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
{
 8000fb0:	b580      	push	{r7, lr}
 8000fb2:	b084      	sub	sp, #16
 8000fb4:	af00      	add	r7, sp, #0
 8000fb6:	6078      	str	r0, [r7, #4]
  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
 8000fb8:	2300      	movs	r3, #0
 8000fba:	73fb      	strb	r3, [r7, #15]
  
  /* Check ADC handle */
  if(hadc == NULL)
 8000fbc:	687b      	ldr	r3, [r7, #4]
 8000fbe:	2b00      	cmp	r3, #0
 8000fc0:	d101      	bne.n	8000fc6 <HAL_ADC_Init+0x16>
  {
    return HAL_ERROR;
 8000fc2:	2301      	movs	r3, #1
 8000fc4:	e033      	b.n	800102e <HAL_ADC_Init+0x7e>
  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
  {
    assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
  }
  
  if(hadc->State == HAL_ADC_STATE_RESET)
 8000fc6:	687b      	ldr	r3, [r7, #4]
 8000fc8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000fca:	2b00      	cmp	r3, #0
 8000fcc:	d109      	bne.n	8000fe2 <HAL_ADC_Init+0x32>

    /* Init the low level hardware */
    hadc->MspInitCallback(hadc);
#else
    /* Init the low level hardware */
    HAL_ADC_MspInit(hadc);
 8000fce:	6878      	ldr	r0, [r7, #4]
 8000fd0:	f7ff fe40 	bl	8000c54 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */

    /* Initialize ADC error code */
    ADC_CLEAR_ERRORCODE(hadc);
 8000fd4:	687b      	ldr	r3, [r7, #4]
 8000fd6:	2200      	movs	r2, #0
 8000fd8:	645a      	str	r2, [r3, #68]	; 0x44
    
    /* Allocate lock resource and initialize it */
    hadc->Lock = HAL_UNLOCKED;
 8000fda:	687b      	ldr	r3, [r7, #4]
 8000fdc:	2200      	movs	r2, #0
 8000fde:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
  }
  
  /* Configuration of ADC parameters if previous preliminary actions are      */ 
  /* correctly completed.                                                     */
  if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 8000fe2:	687b      	ldr	r3, [r7, #4]
 8000fe4:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000fe6:	f003 0310 	and.w	r3, r3, #16
 8000fea:	2b00      	cmp	r3, #0
 8000fec:	d118      	bne.n	8001020 <HAL_ADC_Init+0x70>
  {
    /* Set ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 8000fee:	687b      	ldr	r3, [r7, #4]
 8000ff0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8000ff2:	f423 5388 	bic.w	r3, r3, #4352	; 0x1100
 8000ff6:	f023 0302 	bic.w	r3, r3, #2
 8000ffa:	f043 0202 	orr.w	r2, r3, #2
 8000ffe:	687b      	ldr	r3, [r7, #4]
 8001000:	641a      	str	r2, [r3, #64]	; 0x40
                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
                      HAL_ADC_STATE_BUSY_INTERNAL);
    
    /* Set ADC parameters */
    ADC_Init(hadc);
 8001002:	6878      	ldr	r0, [r7, #4]
 8001004:	f000 fb3a 	bl	800167c <ADC_Init>
    
    /* Set ADC error code to none */
    ADC_CLEAR_ERRORCODE(hadc);
 8001008:	687b      	ldr	r3, [r7, #4]
 800100a:	2200      	movs	r2, #0
 800100c:	645a      	str	r2, [r3, #68]	; 0x44
    
    /* Set the ADC state */
    ADC_STATE_CLR_SET(hadc->State,
 800100e:	687b      	ldr	r3, [r7, #4]
 8001010:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001012:	f023 0303 	bic.w	r3, r3, #3
 8001016:	f043 0201 	orr.w	r2, r3, #1
 800101a:	687b      	ldr	r3, [r7, #4]
 800101c:	641a      	str	r2, [r3, #64]	; 0x40
 800101e:	e001      	b.n	8001024 <HAL_ADC_Init+0x74>
                      HAL_ADC_STATE_BUSY_INTERNAL,
                      HAL_ADC_STATE_READY);
  }
  else
  {
    tmp_hal_status = HAL_ERROR;
 8001020:	2301      	movs	r3, #1
 8001022:	73fb      	strb	r3, [r7, #15]
  }
  
  /* Release Lock */
  __HAL_UNLOCK(hadc);
 8001024:	687b      	ldr	r3, [r7, #4]
 8001026:	2200      	movs	r2, #0
 8001028:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

  /* Return function status */
  return tmp_hal_status;
 800102c:	7bfb      	ldrb	r3, [r7, #15]
}
 800102e:	4618      	mov	r0, r3
 8001030:	3710      	adds	r7, #16
 8001032:	46bd      	mov	sp, r7
 8001034:	bd80      	pop	{r7, pc}
	...

08001038 <HAL_ADC_Start_IT>:
  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
  *         the configuration information for the specified ADC.
  * @retval HAL status.
  */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
{
 8001038:	b480      	push	{r7}
 800103a:	b085      	sub	sp, #20
 800103c:	af00      	add	r7, sp, #0
 800103e:	6078      	str	r0, [r7, #4]
  __IO uint32_t counter = 0U;
 8001040:	2300      	movs	r3, #0
 8001042:	60bb      	str	r3, [r7, #8]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 
  
  /* Process locked */
  __HAL_LOCK(hadc);
 8001044:	687b      	ldr	r3, [r7, #4]
 8001046:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 800104a:	2b01      	cmp	r3, #1
 800104c:	d101      	bne.n	8001052 <HAL_ADC_Start_IT+0x1a>
 800104e:	2302      	movs	r3, #2
 8001050:	e0a1      	b.n	8001196 <HAL_ADC_Start_IT+0x15e>
 8001052:	687b      	ldr	r3, [r7, #4]
 8001054:	2201      	movs	r2, #1
 8001056:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
  
  /* Enable the ADC peripheral */
  /* Check if ADC peripheral is disabled in order to enable it and wait during 
  Tstab time the ADC's stabilization */
  if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON)
 800105a:	687b      	ldr	r3, [r7, #4]
 800105c:	681b      	ldr	r3, [r3, #0]
 800105e:	689b      	ldr	r3, [r3, #8]
 8001060:	f003 0301 	and.w	r3, r3, #1
 8001064:	2b01      	cmp	r3, #1
 8001066:	d018      	beq.n	800109a <HAL_ADC_Start_IT+0x62>
  {  
    /* Enable the Peripheral */
    __HAL_ADC_ENABLE(hadc);
 8001068:	687b      	ldr	r3, [r7, #4]
 800106a:	681b      	ldr	r3, [r3, #0]
 800106c:	689a      	ldr	r2, [r3, #8]
 800106e:	687b      	ldr	r3, [r7, #4]
 8001070:	681b      	ldr	r3, [r3, #0]
 8001072:	f042 0201 	orr.w	r2, r2, #1
 8001076:	609a      	str	r2, [r3, #8]
    
    /* Delay for ADC stabilization time */
    /* Compute number of CPU cycles to wait for */
    counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U));
 8001078:	4b4a      	ldr	r3, [pc, #296]	; (80011a4 <HAL_ADC_Start_IT+0x16c>)
 800107a:	681b      	ldr	r3, [r3, #0]
 800107c:	4a4a      	ldr	r2, [pc, #296]	; (80011a8 <HAL_ADC_Start_IT+0x170>)
 800107e:	fba2 2303 	umull	r2, r3, r2, r3
 8001082:	0c9a      	lsrs	r2, r3, #18
 8001084:	4613      	mov	r3, r2
 8001086:	005b      	lsls	r3, r3, #1
 8001088:	4413      	add	r3, r2
 800108a:	60bb      	str	r3, [r7, #8]
    while(counter != 0U)
 800108c:	e002      	b.n	8001094 <HAL_ADC_Start_IT+0x5c>
    {
      counter--;
 800108e:	68bb      	ldr	r3, [r7, #8]
 8001090:	3b01      	subs	r3, #1
 8001092:	60bb      	str	r3, [r7, #8]
    while(counter != 0U)
 8001094:	68bb      	ldr	r3, [r7, #8]
 8001096:	2b00      	cmp	r3, #0
 8001098:	d1f9      	bne.n	800108e <HAL_ADC_Start_IT+0x56>
    }
  }
  
  /* Start conversion if ADC is effectively enabled */
  if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON))
 800109a:	687b      	ldr	r3, [r7, #4]
 800109c:	681b      	ldr	r3, [r3, #0]
 800109e:	689b      	ldr	r3, [r3, #8]
 80010a0:	f003 0301 	and.w	r3, r3, #1
 80010a4:	2b01      	cmp	r3, #1
 80010a6:	d169      	bne.n	800117c <HAL_ADC_Start_IT+0x144>
  {
    /* Set ADC state                                                          */
    /* - Clear state bitfield related to regular group conversion results     */
    /* - Set state bitfield related to regular group operation                */
    ADC_STATE_CLR_SET(hadc->State,
 80010a8:	687b      	ldr	r3, [r7, #4]
 80010aa:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80010ac:	f423 63e0 	bic.w	r3, r3, #1792	; 0x700
 80010b0:	f023 0301 	bic.w	r3, r3, #1
 80010b4:	f443 7280 	orr.w	r2, r3, #256	; 0x100
 80010b8:	687b      	ldr	r3, [r7, #4]
 80010ba:	641a      	str	r2, [r3, #64]	; 0x40
                      HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR,
                      HAL_ADC_STATE_REG_BUSY);
    
    /* If conversions on group regular are also triggering group injected,    */
    /* update ADC state.                                                      */
    if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
 80010bc:	687b      	ldr	r3, [r7, #4]
 80010be:	681b      	ldr	r3, [r3, #0]
 80010c0:	685b      	ldr	r3, [r3, #4]
 80010c2:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 80010c6:	2b00      	cmp	r3, #0
 80010c8:	d007      	beq.n	80010da <HAL_ADC_Start_IT+0xa2>
    {
      ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);  
 80010ca:	687b      	ldr	r3, [r7, #4]
 80010cc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80010ce:	f423 5340 	bic.w	r3, r3, #12288	; 0x3000
 80010d2:	f443 5280 	orr.w	r2, r3, #4096	; 0x1000
 80010d6:	687b      	ldr	r3, [r7, #4]
 80010d8:	641a      	str	r2, [r3, #64]	; 0x40
    }
    
    /* State machine update: Check if an injected conversion is ongoing */
    if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 80010da:	687b      	ldr	r3, [r7, #4]
 80010dc:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80010de:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 80010e2:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 80010e6:	d106      	bne.n	80010f6 <HAL_ADC_Start_IT+0xbe>
    {
      /* Reset ADC error code fields related to conversions on group regular */
      CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));         
 80010e8:	687b      	ldr	r3, [r7, #4]
 80010ea:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80010ec:	f023 0206 	bic.w	r2, r3, #6
 80010f0:	687b      	ldr	r3, [r7, #4]
 80010f2:	645a      	str	r2, [r3, #68]	; 0x44
 80010f4:	e002      	b.n	80010fc <HAL_ADC_Start_IT+0xc4>
    }
    else
    {
      /* Reset ADC all error code fields */
      ADC_CLEAR_ERRORCODE(hadc);
 80010f6:	687b      	ldr	r3, [r7, #4]
 80010f8:	2200      	movs	r2, #0
 80010fa:	645a      	str	r2, [r3, #68]	; 0x44
    }

    /* Process unlocked */
    /* Unlock before starting ADC conversions: in case of potential           */
    /* interruption, to let the process to ADC IRQ Handler.                   */
    __HAL_UNLOCK(hadc);
 80010fc:	687b      	ldr	r3, [r7, #4]
 80010fe:	2200      	movs	r2, #0
 8001100:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Pointer to the common control register to which is belonging hadc    */
    /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
    /* control register)                                                    */
    tmpADC_Common = ADC_COMMON_REGISTER(hadc);
 8001104:	4b29      	ldr	r3, [pc, #164]	; (80011ac <HAL_ADC_Start_IT+0x174>)
 8001106:	60fb      	str	r3, [r7, #12]

    /* Clear regular group conversion flag and overrun flag */
    /* (To ensure of no unknown state from potential previous ADC operations) */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
 8001108:	687b      	ldr	r3, [r7, #4]
 800110a:	681b      	ldr	r3, [r3, #0]
 800110c:	f06f 0222 	mvn.w	r2, #34	; 0x22
 8001110:	601a      	str	r2, [r3, #0]
    
    /* Enable end of conversion interrupt for regular group */
    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
 8001112:	687b      	ldr	r3, [r7, #4]
 8001114:	681b      	ldr	r3, [r3, #0]
 8001116:	685b      	ldr	r3, [r3, #4]
 8001118:	687a      	ldr	r2, [r7, #4]
 800111a:	6812      	ldr	r2, [r2, #0]
 800111c:	f043 6380 	orr.w	r3, r3, #67108864	; 0x4000000
 8001120:	f043 0320 	orr.w	r3, r3, #32
 8001124:	6053      	str	r3, [r2, #4]
    
    /* Check if Multimode enabled */
    if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI))
 8001126:	68fb      	ldr	r3, [r7, #12]
 8001128:	685b      	ldr	r3, [r3, #4]
 800112a:	f003 031f 	and.w	r3, r3, #31
 800112e:	2b00      	cmp	r3, #0
 8001130:	d10f      	bne.n	8001152 <HAL_ADC_Start_IT+0x11a>
      if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \
                                  || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4)))
      {
#endif /* ADC2 || ADC3 */
        /* if no external trigger present enable software conversion of regular channels */
        if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 
 8001132:	687b      	ldr	r3, [r7, #4]
 8001134:	681b      	ldr	r3, [r3, #0]
 8001136:	689b      	ldr	r3, [r3, #8]
 8001138:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
 800113c:	2b00      	cmp	r3, #0
 800113e:	d129      	bne.n	8001194 <HAL_ADC_Start_IT+0x15c>
        {
          /* Enable the selected ADC software conversion for regular group */
          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
 8001140:	687b      	ldr	r3, [r7, #4]
 8001142:	681b      	ldr	r3, [r3, #0]
 8001144:	689a      	ldr	r2, [r3, #8]
 8001146:	687b      	ldr	r3, [r7, #4]
 8001148:	681b      	ldr	r3, [r3, #0]
 800114a:	f042 4280 	orr.w	r2, r2, #1073741824	; 0x40000000
 800114e:	609a      	str	r2, [r3, #8]
 8001150:	e020      	b.n	8001194 <HAL_ADC_Start_IT+0x15c>
#endif /* ADC2 || ADC3 */
    }
    else
    {
      /* if instance of handle correspond to ADC1 and  no external trigger present enable software conversion of regular channels */
      if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET))
 8001152:	687b      	ldr	r3, [r7, #4]
 8001154:	681b      	ldr	r3, [r3, #0]
 8001156:	4a16      	ldr	r2, [pc, #88]	; (80011b0 <HAL_ADC_Start_IT+0x178>)
 8001158:	4293      	cmp	r3, r2
 800115a:	d11b      	bne.n	8001194 <HAL_ADC_Start_IT+0x15c>
 800115c:	687b      	ldr	r3, [r7, #4]
 800115e:	681b      	ldr	r3, [r3, #0]
 8001160:	689b      	ldr	r3, [r3, #8]
 8001162:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
 8001166:	2b00      	cmp	r3, #0
 8001168:	d114      	bne.n	8001194 <HAL_ADC_Start_IT+0x15c>
      {
        /* Enable the selected ADC software conversion for regular group */
          hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART;
 800116a:	687b      	ldr	r3, [r7, #4]
 800116c:	681b      	ldr	r3, [r3, #0]
 800116e:	689a      	ldr	r2, [r3, #8]
 8001170:	687b      	ldr	r3, [r7, #4]
 8001172:	681b      	ldr	r3, [r3, #0]
 8001174:	f042 4280 	orr.w	r2, r2, #1073741824	; 0x40000000
 8001178:	609a      	str	r2, [r3, #8]
 800117a:	e00b      	b.n	8001194 <HAL_ADC_Start_IT+0x15c>
    }
  }
  else
  {
    /* Update ADC state machine to error */
    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
 800117c:	687b      	ldr	r3, [r7, #4]
 800117e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001180:	f043 0210 	orr.w	r2, r3, #16
 8001184:	687b      	ldr	r3, [r7, #4]
 8001186:	641a      	str	r2, [r3, #64]	; 0x40

    /* Set ADC error code to ADC IP internal error */
    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
 8001188:	687b      	ldr	r3, [r7, #4]
 800118a:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 800118c:	f043 0201 	orr.w	r2, r3, #1
 8001190:	687b      	ldr	r3, [r7, #4]
 8001192:	645a      	str	r2, [r3, #68]	; 0x44
  }
  
  /* Return function status */
  return HAL_OK;
 8001194:	2300      	movs	r3, #0
}
 8001196:	4618      	mov	r0, r3
 8001198:	3714      	adds	r7, #20
 800119a:	46bd      	mov	sp, r7
 800119c:	f85d 7b04 	ldr.w	r7, [sp], #4
 80011a0:	4770      	bx	lr
 80011a2:	bf00      	nop
 80011a4:	20000000 	.word	0x20000000
 80011a8:	431bde83 	.word	0x431bde83
 80011ac:	40012300 	.word	0x40012300
 80011b0:	40012000 	.word	0x40012000

080011b4 <HAL_ADC_IRQHandler>:
  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
  *         the configuration information for the specified ADC.
  * @retval None
  */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
{
 80011b4:	b580      	push	{r7, lr}
 80011b6:	b086      	sub	sp, #24
 80011b8:	af00      	add	r7, sp, #0
 80011ba:	6078      	str	r0, [r7, #4]
  uint32_t tmp1 = 0U, tmp2 = 0U;
 80011bc:	2300      	movs	r3, #0
 80011be:	617b      	str	r3, [r7, #20]
 80011c0:	2300      	movs	r3, #0
 80011c2:	613b      	str	r3, [r7, #16]
  
  uint32_t tmp_sr = hadc->Instance->SR;
 80011c4:	687b      	ldr	r3, [r7, #4]
 80011c6:	681b      	ldr	r3, [r3, #0]
 80011c8:	681b      	ldr	r3, [r3, #0]
 80011ca:	60fb      	str	r3, [r7, #12]
  uint32_t tmp_cr1 = hadc->Instance->CR1;
 80011cc:	687b      	ldr	r3, [r7, #4]
 80011ce:	681b      	ldr	r3, [r3, #0]
 80011d0:	685b      	ldr	r3, [r3, #4]
 80011d2:	60bb      	str	r3, [r7, #8]
  /* Check the parameters */
  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
  assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
  assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
  
  tmp1 = tmp_sr & ADC_FLAG_EOC;
 80011d4:	68fb      	ldr	r3, [r7, #12]
 80011d6:	f003 0302 	and.w	r3, r3, #2
 80011da:	617b      	str	r3, [r7, #20]
  tmp2 = tmp_cr1 & ADC_IT_EOC;
 80011dc:	68bb      	ldr	r3, [r7, #8]
 80011de:	f003 0320 	and.w	r3, r3, #32
 80011e2:	613b      	str	r3, [r7, #16]
  /* Check End of conversion flag for regular channels */
  if(tmp1 && tmp2)
 80011e4:	697b      	ldr	r3, [r7, #20]
 80011e6:	2b00      	cmp	r3, #0
 80011e8:	d049      	beq.n	800127e <HAL_ADC_IRQHandler+0xca>
 80011ea:	693b      	ldr	r3, [r7, #16]
 80011ec:	2b00      	cmp	r3, #0
 80011ee:	d046      	beq.n	800127e <HAL_ADC_IRQHandler+0xca>
  {
    /* Update state machine on conversion status if not in error state */
    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 80011f0:	687b      	ldr	r3, [r7, #4]
 80011f2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80011f4:	f003 0310 	and.w	r3, r3, #16
 80011f8:	2b00      	cmp	r3, #0
 80011fa:	d105      	bne.n	8001208 <HAL_ADC_IRQHandler+0x54>
    {
      /* Set ADC state */
      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 
 80011fc:	687b      	ldr	r3, [r7, #4]
 80011fe:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001200:	f443 7200 	orr.w	r2, r3, #512	; 0x200
 8001204:	687b      	ldr	r3, [r7, #4]
 8001206:	641a      	str	r2, [r3, #64]	; 0x40
    /* by external trigger, continuous mode or scan sequence on going.      */
    /* Note: On STM32F4, there is no independent flag of end of sequence.   */
    /*       The test of scan sequence on going is done either with scan    */
    /*       sequence disabled or with end of conversion flag set to        */
    /*       of end of sequence.                                            */
    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
 8001208:	687b      	ldr	r3, [r7, #4]
 800120a:	681b      	ldr	r3, [r3, #0]
 800120c:	689b      	ldr	r3, [r3, #8]
 800120e:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
 8001212:	2b00      	cmp	r3, #0
 8001214:	d12b      	bne.n	800126e <HAL_ADC_IRQHandler+0xba>
       (hadc->Init.ContinuousConvMode == DISABLE)            &&
 8001216:	687b      	ldr	r3, [r7, #4]
 8001218:	7e1b      	ldrb	r3, [r3, #24]
    if(ADC_IS_SOFTWARE_START_REGULAR(hadc)                   &&
 800121a:	2b00      	cmp	r3, #0
 800121c:	d127      	bne.n	800126e <HAL_ADC_IRQHandler+0xba>
       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
 800121e:	687b      	ldr	r3, [r7, #4]
 8001220:	681b      	ldr	r3, [r3, #0]
 8001222:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8001224:	f403 0370 	and.w	r3, r3, #15728640	; 0xf00000
       (hadc->Init.ContinuousConvMode == DISABLE)            &&
 8001228:	2b00      	cmp	r3, #0
 800122a:	d006      	beq.n	800123a <HAL_ADC_IRQHandler+0x86>
        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)  )   )
 800122c:	687b      	ldr	r3, [r7, #4]
 800122e:	681b      	ldr	r3, [r3, #0]
 8001230:	689b      	ldr	r3, [r3, #8]
 8001232:	f403 6380 	and.w	r3, r3, #1024	; 0x400
       (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 
 8001236:	2b00      	cmp	r3, #0
 8001238:	d119      	bne.n	800126e <HAL_ADC_IRQHandler+0xba>
    {
      /* Disable ADC end of single conversion interrupt on group regular */
      /* Note: Overrun interrupt was enabled with EOC interrupt in          */
      /* HAL_ADC_Start_IT(), but is not disabled here because can be used   */
      /* by overrun IRQ process below.                                      */
      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
 800123a:	687b      	ldr	r3, [r7, #4]
 800123c:	681b      	ldr	r3, [r3, #0]
 800123e:	685a      	ldr	r2, [r3, #4]
 8001240:	687b      	ldr	r3, [r7, #4]
 8001242:	681b      	ldr	r3, [r3, #0]
 8001244:	f022 0220 	bic.w	r2, r2, #32
 8001248:	605a      	str	r2, [r3, #4]
      
      /* Set ADC state */
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
 800124a:	687b      	ldr	r3, [r7, #4]
 800124c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800124e:	f423 7280 	bic.w	r2, r3, #256	; 0x100
 8001252:	687b      	ldr	r3, [r7, #4]
 8001254:	641a      	str	r2, [r3, #64]	; 0x40
      
      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
 8001256:	687b      	ldr	r3, [r7, #4]
 8001258:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800125a:	f403 5380 	and.w	r3, r3, #4096	; 0x1000
 800125e:	2b00      	cmp	r3, #0
 8001260:	d105      	bne.n	800126e <HAL_ADC_IRQHandler+0xba>
      {
        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8001262:	687b      	ldr	r3, [r7, #4]
 8001264:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001266:	f043 0201 	orr.w	r2, r3, #1
 800126a:	687b      	ldr	r3, [r7, #4]
 800126c:	641a      	str	r2, [r3, #64]	; 0x40
    
    /* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
    hadc->ConvCpltCallback(hadc);
#else
    HAL_ADC_ConvCpltCallback(hadc);
 800126e:	6878      	ldr	r0, [r7, #4]
 8001270:	f7ff f934 	bl	80004dc <HAL_ADC_ConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
    
    /* Clear regular group conversion flag */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
 8001274:	687b      	ldr	r3, [r7, #4]
 8001276:	681b      	ldr	r3, [r3, #0]
 8001278:	f06f 0212 	mvn.w	r2, #18
 800127c:	601a      	str	r2, [r3, #0]
  }
  
  tmp1 = tmp_sr & ADC_FLAG_JEOC;
 800127e:	68fb      	ldr	r3, [r7, #12]
 8001280:	f003 0304 	and.w	r3, r3, #4
 8001284:	617b      	str	r3, [r7, #20]
  tmp2 = tmp_cr1 & ADC_IT_JEOC;
 8001286:	68bb      	ldr	r3, [r7, #8]
 8001288:	f003 0380 	and.w	r3, r3, #128	; 0x80
 800128c:	613b      	str	r3, [r7, #16]
  /* Check End of conversion flag for injected channels */
  if(tmp1 && tmp2)
 800128e:	697b      	ldr	r3, [r7, #20]
 8001290:	2b00      	cmp	r3, #0
 8001292:	d057      	beq.n	8001344 <HAL_ADC_IRQHandler+0x190>
 8001294:	693b      	ldr	r3, [r7, #16]
 8001296:	2b00      	cmp	r3, #0
 8001298:	d054      	beq.n	8001344 <HAL_ADC_IRQHandler+0x190>
  {
    /* Update state machine on conversion status if not in error state */
    if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
 800129a:	687b      	ldr	r3, [r7, #4]
 800129c:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800129e:	f003 0310 	and.w	r3, r3, #16
 80012a2:	2b00      	cmp	r3, #0
 80012a4:	d105      	bne.n	80012b2 <HAL_ADC_IRQHandler+0xfe>
    {
      /* Set ADC state */
      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
 80012a6:	687b      	ldr	r3, [r7, #4]
 80012a8:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80012aa:	f443 5200 	orr.w	r2, r3, #8192	; 0x2000
 80012ae:	687b      	ldr	r3, [r7, #4]
 80012b0:	641a      	str	r2, [r3, #64]	; 0x40

    /* Determine whether any further conversion upcoming on group injected  */
    /* by external trigger, scan sequence on going or by automatic injected */
    /* conversion from group regular (same conditions as group regular      */
    /* interruption disabling above).                                       */
    if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
 80012b2:	687b      	ldr	r3, [r7, #4]
 80012b4:	681b      	ldr	r3, [r3, #0]
 80012b6:	689b      	ldr	r3, [r3, #8]
 80012b8:	f403 1340 	and.w	r3, r3, #3145728	; 0x300000
 80012bc:	2b00      	cmp	r3, #0
 80012be:	d139      	bne.n	8001334 <HAL_ADC_IRQHandler+0x180>
       (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
 80012c0:	687b      	ldr	r3, [r7, #4]
 80012c2:	681b      	ldr	r3, [r3, #0]
 80012c4:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 80012c6:	f403 1340 	and.w	r3, r3, #3145728	; 0x300000
    if(ADC_IS_SOFTWARE_START_INJECTED(hadc)                    &&
 80012ca:	2b00      	cmp	r3, #0
 80012cc:	d006      	beq.n	80012dc <HAL_ADC_IRQHandler+0x128>
        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
 80012ce:	687b      	ldr	r3, [r7, #4]
 80012d0:	681b      	ldr	r3, [r3, #0]
 80012d2:	689b      	ldr	r3, [r3, #8]
 80012d4:	f403 6380 	and.w	r3, r3, #1024	; 0x400
       (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL)  ||
 80012d8:	2b00      	cmp	r3, #0
 80012da:	d12b      	bne.n	8001334 <HAL_ADC_IRQHandler+0x180>
       (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
 80012dc:	687b      	ldr	r3, [r7, #4]
 80012de:	681b      	ldr	r3, [r3, #0]
 80012e0:	685b      	ldr	r3, [r3, #4]
 80012e2:	f403 6380 	and.w	r3, r3, #1024	; 0x400
        HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)    ) &&
 80012e6:	2b00      	cmp	r3, #0
 80012e8:	d124      	bne.n	8001334 <HAL_ADC_IRQHandler+0x180>
        (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
 80012ea:	687b      	ldr	r3, [r7, #4]
 80012ec:	681b      	ldr	r3, [r3, #0]
 80012ee:	689b      	ldr	r3, [r3, #8]
 80012f0:	f003 5340 	and.w	r3, r3, #805306368	; 0x30000000
       (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
 80012f4:	2b00      	cmp	r3, #0
 80012f6:	d11d      	bne.n	8001334 <HAL_ADC_IRQHandler+0x180>
        (hadc->Init.ContinuousConvMode == DISABLE)   )       )   )
 80012f8:	687b      	ldr	r3, [r7, #4]
 80012fa:	7e1b      	ldrb	r3, [r3, #24]
        (ADC_IS_SOFTWARE_START_REGULAR(hadc)       &&
 80012fc:	2b00      	cmp	r3, #0
 80012fe:	d119      	bne.n	8001334 <HAL_ADC_IRQHandler+0x180>
    {
      /* Disable ADC end of single conversion interrupt on group injected */
      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
 8001300:	687b      	ldr	r3, [r7, #4]
 8001302:	681b      	ldr	r3, [r3, #0]
 8001304:	685a      	ldr	r2, [r3, #4]
 8001306:	687b      	ldr	r3, [r7, #4]
 8001308:	681b      	ldr	r3, [r3, #0]
 800130a:	f022 0280 	bic.w	r2, r2, #128	; 0x80
 800130e:	605a      	str	r2, [r3, #4]
      
      /* Set ADC state */
      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);   
 8001310:	687b      	ldr	r3, [r7, #4]
 8001312:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001314:	f423 5280 	bic.w	r2, r3, #4096	; 0x1000
 8001318:	687b      	ldr	r3, [r7, #4]
 800131a:	641a      	str	r2, [r3, #64]	; 0x40

      if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
 800131c:	687b      	ldr	r3, [r7, #4]
 800131e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001320:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8001324:	2b00      	cmp	r3, #0
 8001326:	d105      	bne.n	8001334 <HAL_ADC_IRQHandler+0x180>
      { 
        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
 8001328:	687b      	ldr	r3, [r7, #4]
 800132a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800132c:	f043 0201 	orr.w	r2, r3, #1
 8001330:	687b      	ldr	r3, [r7, #4]
 8001332:	641a      	str	r2, [r3, #64]	; 0x40
    /* Conversion complete callback */ 
    /* Conversion complete callback */ 
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->InjectedConvCpltCallback(hadc);
#else
      HAL_ADCEx_InjectedConvCpltCallback(hadc);
 8001334:	6878      	ldr	r0, [r7, #4]
 8001336:	f000 fa9d 	bl	8001874 <HAL_ADCEx_InjectedConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
    
    /* Clear injected group conversion flag */
    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
 800133a:	687b      	ldr	r3, [r7, #4]
 800133c:	681b      	ldr	r3, [r3, #0]
 800133e:	f06f 020c 	mvn.w	r2, #12
 8001342:	601a      	str	r2, [r3, #0]
  }
  
  tmp1 = tmp_sr & ADC_FLAG_AWD;
 8001344:	68fb      	ldr	r3, [r7, #12]
 8001346:	f003 0301 	and.w	r3, r3, #1
 800134a:	617b      	str	r3, [r7, #20]
  tmp2 = tmp_cr1 & ADC_IT_AWD;
 800134c:	68bb      	ldr	r3, [r7, #8]
 800134e:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8001352:	613b      	str	r3, [r7, #16]
  /* Check Analog watchdog flag */
  if(tmp1 && tmp2)
 8001354:	697b      	ldr	r3, [r7, #20]
 8001356:	2b00      	cmp	r3, #0
 8001358:	d017      	beq.n	800138a <HAL_ADC_IRQHandler+0x1d6>
 800135a:	693b      	ldr	r3, [r7, #16]
 800135c:	2b00      	cmp	r3, #0
 800135e:	d014      	beq.n	800138a <HAL_ADC_IRQHandler+0x1d6>
  {
    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
 8001360:	687b      	ldr	r3, [r7, #4]
 8001362:	681b      	ldr	r3, [r3, #0]
 8001364:	681b      	ldr	r3, [r3, #0]
 8001366:	f003 0301 	and.w	r3, r3, #1
 800136a:	2b01      	cmp	r3, #1
 800136c:	d10d      	bne.n	800138a <HAL_ADC_IRQHandler+0x1d6>
    {
      /* Set ADC state */
      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
 800136e:	687b      	ldr	r3, [r7, #4]
 8001370:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001372:	f443 3280 	orr.w	r2, r3, #65536	; 0x10000
 8001376:	687b      	ldr	r3, [r7, #4]
 8001378:	641a      	str	r2, [r3, #64]	; 0x40
      
      /* Level out of window callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->LevelOutOfWindowCallback(hadc);
#else
      HAL_ADC_LevelOutOfWindowCallback(hadc);
 800137a:	6878      	ldr	r0, [r7, #4]
 800137c:	f000 f837 	bl	80013ee <HAL_ADC_LevelOutOfWindowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
      
      /* Clear the ADC analog watchdog flag */
      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
 8001380:	687b      	ldr	r3, [r7, #4]
 8001382:	681b      	ldr	r3, [r3, #0]
 8001384:	f06f 0201 	mvn.w	r2, #1
 8001388:	601a      	str	r2, [r3, #0]
    }
  }
  
  tmp1 = tmp_sr & ADC_FLAG_OVR;
 800138a:	68fb      	ldr	r3, [r7, #12]
 800138c:	f003 0320 	and.w	r3, r3, #32
 8001390:	617b      	str	r3, [r7, #20]
  tmp2 = tmp_cr1 & ADC_IT_OVR;
 8001392:	68bb      	ldr	r3, [r7, #8]
 8001394:	f003 6380 	and.w	r3, r3, #67108864	; 0x4000000
 8001398:	613b      	str	r3, [r7, #16]
  /* Check Overrun flag */
  if(tmp1 && tmp2)
 800139a:	697b      	ldr	r3, [r7, #20]
 800139c:	2b00      	cmp	r3, #0
 800139e:	d015      	beq.n	80013cc <HAL_ADC_IRQHandler+0x218>
 80013a0:	693b      	ldr	r3, [r7, #16]
 80013a2:	2b00      	cmp	r3, #0
 80013a4:	d012      	beq.n	80013cc <HAL_ADC_IRQHandler+0x218>
    /* Note: On STM32F4, ADC overrun can be set through other parameters    */
    /*       refer to description of parameter "EOCSelection" for more      */
    /*       details.                                                       */
    
    /* Set ADC error code to overrun */
    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
 80013a6:	687b      	ldr	r3, [r7, #4]
 80013a8:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 80013aa:	f043 0202 	orr.w	r2, r3, #2
 80013ae:	687b      	ldr	r3, [r7, #4]
 80013b0:	645a      	str	r2, [r3, #68]	; 0x44
    
    /* Clear ADC overrun flag */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
 80013b2:	687b      	ldr	r3, [r7, #4]
 80013b4:	681b      	ldr	r3, [r3, #0]
 80013b6:	f06f 0220 	mvn.w	r2, #32
 80013ba:	601a      	str	r2, [r3, #0]
    
    /* Error callback */ 
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
      hadc->ErrorCallback(hadc);
#else
      HAL_ADC_ErrorCallback(hadc);
 80013bc:	6878      	ldr	r0, [r7, #4]
 80013be:	f000 f820 	bl	8001402 <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
    
    /* Clear the Overrun flag */
    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
 80013c2:	687b      	ldr	r3, [r7, #4]
 80013c4:	681b      	ldr	r3, [r3, #0]
 80013c6:	f06f 0220 	mvn.w	r2, #32
 80013ca:	601a      	str	r2, [r3, #0]
  }
}
 80013cc:	bf00      	nop
 80013ce:	3718      	adds	r7, #24
 80013d0:	46bd      	mov	sp, r7
 80013d2:	bd80      	pop	{r7, pc}

080013d4 <HAL_ADC_GetValue>:
  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
  *         the configuration information for the specified ADC.
  * @retval Converted value
  */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
{       
 80013d4:	b480      	push	{r7}
 80013d6:	b083      	sub	sp, #12
 80013d8:	af00      	add	r7, sp, #0
 80013da:	6078      	str	r0, [r7, #4]
  /* Return the selected ADC converted value */ 
  return hadc->Instance->DR;
 80013dc:	687b      	ldr	r3, [r7, #4]
 80013de:	681b      	ldr	r3, [r3, #0]
 80013e0:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
}
 80013e2:	4618      	mov	r0, r3
 80013e4:	370c      	adds	r7, #12
 80013e6:	46bd      	mov	sp, r7
 80013e8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80013ec:	4770      	bx	lr

080013ee <HAL_ADC_LevelOutOfWindowCallback>:
  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
  *         the configuration information for the specified ADC.
  * @retval None
  */
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
{
 80013ee:	b480      	push	{r7}
 80013f0:	b083      	sub	sp, #12
 80013f2:	af00      	add	r7, sp, #0
 80013f4:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
   */
}
 80013f6:	bf00      	nop
 80013f8:	370c      	adds	r7, #12
 80013fa:	46bd      	mov	sp, r7
 80013fc:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001400:	4770      	bx	lr

08001402 <HAL_ADC_ErrorCallback>:
  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
  *         the configuration information for the specified ADC.
  * @retval None
  */
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
 8001402:	b480      	push	{r7}
 8001404:	b083      	sub	sp, #12
 8001406:	af00      	add	r7, sp, #0
 8001408:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_ADC_ErrorCallback could be implemented in the user file
   */
}
 800140a:	bf00      	nop
 800140c:	370c      	adds	r7, #12
 800140e:	46bd      	mov	sp, r7
 8001410:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001414:	4770      	bx	lr
	...

08001418 <HAL_ADC_ConfigChannel>:
  *         the configuration information for the specified ADC.
  * @param  sConfig ADC configuration structure. 
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
{
 8001418:	b480      	push	{r7}
 800141a:	b085      	sub	sp, #20
 800141c:	af00      	add	r7, sp, #0
 800141e:	6078      	str	r0, [r7, #4]
 8001420:	6039      	str	r1, [r7, #0]
  __IO uint32_t counter = 0U;
 8001422:	2300      	movs	r3, #0
 8001424:	60bb      	str	r3, [r7, #8]
  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
  
  /* Process locked */
  __HAL_LOCK(hadc);
 8001426:	687b      	ldr	r3, [r7, #4]
 8001428:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 800142c:	2b01      	cmp	r3, #1
 800142e:	d101      	bne.n	8001434 <HAL_ADC_ConfigChannel+0x1c>
 8001430:	2302      	movs	r3, #2
 8001432:	e113      	b.n	800165c <HAL_ADC_ConfigChannel+0x244>
 8001434:	687b      	ldr	r3, [r7, #4]
 8001436:	2201      	movs	r2, #1
 8001438:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
    
  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
  if (sConfig->Channel > ADC_CHANNEL_9)
 800143c:	683b      	ldr	r3, [r7, #0]
 800143e:	681b      	ldr	r3, [r3, #0]
 8001440:	2b09      	cmp	r3, #9
 8001442:	d925      	bls.n	8001490 <HAL_ADC_ConfigChannel+0x78>
  {
    /* Clear the old sample time */
    hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
 8001444:	687b      	ldr	r3, [r7, #4]
 8001446:	681b      	ldr	r3, [r3, #0]
 8001448:	68d9      	ldr	r1, [r3, #12]
 800144a:	683b      	ldr	r3, [r7, #0]
 800144c:	681b      	ldr	r3, [r3, #0]
 800144e:	b29b      	uxth	r3, r3
 8001450:	461a      	mov	r2, r3
 8001452:	4613      	mov	r3, r2
 8001454:	005b      	lsls	r3, r3, #1
 8001456:	4413      	add	r3, r2
 8001458:	3b1e      	subs	r3, #30
 800145a:	2207      	movs	r2, #7
 800145c:	fa02 f303 	lsl.w	r3, r2, r3
 8001460:	43da      	mvns	r2, r3
 8001462:	687b      	ldr	r3, [r7, #4]
 8001464:	681b      	ldr	r3, [r3, #0]
 8001466:	400a      	ands	r2, r1
 8001468:	60da      	str	r2, [r3, #12]
    
    /* Set the new sample time */
    hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
 800146a:	687b      	ldr	r3, [r7, #4]
 800146c:	681b      	ldr	r3, [r3, #0]
 800146e:	68d9      	ldr	r1, [r3, #12]
 8001470:	683b      	ldr	r3, [r7, #0]
 8001472:	689a      	ldr	r2, [r3, #8]
 8001474:	683b      	ldr	r3, [r7, #0]
 8001476:	681b      	ldr	r3, [r3, #0]
 8001478:	b29b      	uxth	r3, r3
 800147a:	4618      	mov	r0, r3
 800147c:	4603      	mov	r3, r0
 800147e:	005b      	lsls	r3, r3, #1
 8001480:	4403      	add	r3, r0
 8001482:	3b1e      	subs	r3, #30
 8001484:	409a      	lsls	r2, r3
 8001486:	687b      	ldr	r3, [r7, #4]
 8001488:	681b      	ldr	r3, [r3, #0]
 800148a:	430a      	orrs	r2, r1
 800148c:	60da      	str	r2, [r3, #12]
 800148e:	e022      	b.n	80014d6 <HAL_ADC_ConfigChannel+0xbe>
  }
  else /* ADC_Channel include in ADC_Channel_[0..9] */
  {
    /* Clear the old sample time */
    hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
 8001490:	687b      	ldr	r3, [r7, #4]
 8001492:	681b      	ldr	r3, [r3, #0]
 8001494:	6919      	ldr	r1, [r3, #16]
 8001496:	683b      	ldr	r3, [r7, #0]
 8001498:	681b      	ldr	r3, [r3, #0]
 800149a:	b29b      	uxth	r3, r3
 800149c:	461a      	mov	r2, r3
 800149e:	4613      	mov	r3, r2
 80014a0:	005b      	lsls	r3, r3, #1
 80014a2:	4413      	add	r3, r2
 80014a4:	2207      	movs	r2, #7
 80014a6:	fa02 f303 	lsl.w	r3, r2, r3
 80014aa:	43da      	mvns	r2, r3
 80014ac:	687b      	ldr	r3, [r7, #4]
 80014ae:	681b      	ldr	r3, [r3, #0]
 80014b0:	400a      	ands	r2, r1
 80014b2:	611a      	str	r2, [r3, #16]
    
    /* Set the new sample time */
    hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
 80014b4:	687b      	ldr	r3, [r7, #4]
 80014b6:	681b      	ldr	r3, [r3, #0]
 80014b8:	6919      	ldr	r1, [r3, #16]
 80014ba:	683b      	ldr	r3, [r7, #0]
 80014bc:	689a      	ldr	r2, [r3, #8]
 80014be:	683b      	ldr	r3, [r7, #0]
 80014c0:	681b      	ldr	r3, [r3, #0]
 80014c2:	b29b      	uxth	r3, r3
 80014c4:	4618      	mov	r0, r3
 80014c6:	4603      	mov	r3, r0
 80014c8:	005b      	lsls	r3, r3, #1
 80014ca:	4403      	add	r3, r0
 80014cc:	409a      	lsls	r2, r3
 80014ce:	687b      	ldr	r3, [r7, #4]
 80014d0:	681b      	ldr	r3, [r3, #0]
 80014d2:	430a      	orrs	r2, r1
 80014d4:	611a      	str	r2, [r3, #16]
  }
  
  /* For Rank 1 to 6 */
  if (sConfig->Rank < 7U)
 80014d6:	683b      	ldr	r3, [r7, #0]
 80014d8:	685b      	ldr	r3, [r3, #4]
 80014da:	2b06      	cmp	r3, #6
 80014dc:	d824      	bhi.n	8001528 <HAL_ADC_ConfigChannel+0x110>
  {
    /* Clear the old SQx bits for the selected rank */
    hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
 80014de:	687b      	ldr	r3, [r7, #4]
 80014e0:	681b      	ldr	r3, [r3, #0]
 80014e2:	6b59      	ldr	r1, [r3, #52]	; 0x34
 80014e4:	683b      	ldr	r3, [r7, #0]
 80014e6:	685a      	ldr	r2, [r3, #4]
 80014e8:	4613      	mov	r3, r2
 80014ea:	009b      	lsls	r3, r3, #2
 80014ec:	4413      	add	r3, r2
 80014ee:	3b05      	subs	r3, #5
 80014f0:	221f      	movs	r2, #31
 80014f2:	fa02 f303 	lsl.w	r3, r2, r3
 80014f6:	43da      	mvns	r2, r3
 80014f8:	687b      	ldr	r3, [r7, #4]
 80014fa:	681b      	ldr	r3, [r3, #0]
 80014fc:	400a      	ands	r2, r1
 80014fe:	635a      	str	r2, [r3, #52]	; 0x34
    
    /* Set the SQx bits for the selected rank */
    hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
 8001500:	687b      	ldr	r3, [r7, #4]
 8001502:	681b      	ldr	r3, [r3, #0]
 8001504:	6b59      	ldr	r1, [r3, #52]	; 0x34
 8001506:	683b      	ldr	r3, [r7, #0]
 8001508:	681b      	ldr	r3, [r3, #0]
 800150a:	b29b      	uxth	r3, r3
 800150c:	4618      	mov	r0, r3
 800150e:	683b      	ldr	r3, [r7, #0]
 8001510:	685a      	ldr	r2, [r3, #4]
 8001512:	4613      	mov	r3, r2
 8001514:	009b      	lsls	r3, r3, #2
 8001516:	4413      	add	r3, r2
 8001518:	3b05      	subs	r3, #5
 800151a:	fa00 f203 	lsl.w	r2, r0, r3
 800151e:	687b      	ldr	r3, [r7, #4]
 8001520:	681b      	ldr	r3, [r3, #0]
 8001522:	430a      	orrs	r2, r1
 8001524:	635a      	str	r2, [r3, #52]	; 0x34
 8001526:	e04c      	b.n	80015c2 <HAL_ADC_ConfigChannel+0x1aa>
  }
  /* For Rank 7 to 12 */
  else if (sConfig->Rank < 13U)
 8001528:	683b      	ldr	r3, [r7, #0]
 800152a:	685b      	ldr	r3, [r3, #4]
 800152c:	2b0c      	cmp	r3, #12
 800152e:	d824      	bhi.n	800157a <HAL_ADC_ConfigChannel+0x162>
  {
    /* Clear the old SQx bits for the selected rank */
    hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
 8001530:	687b      	ldr	r3, [r7, #4]
 8001532:	681b      	ldr	r3, [r3, #0]
 8001534:	6b19      	ldr	r1, [r3, #48]	; 0x30
 8001536:	683b      	ldr	r3, [r7, #0]
 8001538:	685a      	ldr	r2, [r3, #4]
 800153a:	4613      	mov	r3, r2
 800153c:	009b      	lsls	r3, r3, #2
 800153e:	4413      	add	r3, r2
 8001540:	3b23      	subs	r3, #35	; 0x23
 8001542:	221f      	movs	r2, #31
 8001544:	fa02 f303 	lsl.w	r3, r2, r3
 8001548:	43da      	mvns	r2, r3
 800154a:	687b      	ldr	r3, [r7, #4]
 800154c:	681b      	ldr	r3, [r3, #0]
 800154e:	400a      	ands	r2, r1
 8001550:	631a      	str	r2, [r3, #48]	; 0x30
    
    /* Set the SQx bits for the selected rank */
    hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
 8001552:	687b      	ldr	r3, [r7, #4]
 8001554:	681b      	ldr	r3, [r3, #0]
 8001556:	6b19      	ldr	r1, [r3, #48]	; 0x30
 8001558:	683b      	ldr	r3, [r7, #0]
 800155a:	681b      	ldr	r3, [r3, #0]
 800155c:	b29b      	uxth	r3, r3
 800155e:	4618      	mov	r0, r3
 8001560:	683b      	ldr	r3, [r7, #0]
 8001562:	685a      	ldr	r2, [r3, #4]
 8001564:	4613      	mov	r3, r2
 8001566:	009b      	lsls	r3, r3, #2
 8001568:	4413      	add	r3, r2
 800156a:	3b23      	subs	r3, #35	; 0x23
 800156c:	fa00 f203 	lsl.w	r2, r0, r3
 8001570:	687b      	ldr	r3, [r7, #4]
 8001572:	681b      	ldr	r3, [r3, #0]
 8001574:	430a      	orrs	r2, r1
 8001576:	631a      	str	r2, [r3, #48]	; 0x30
 8001578:	e023      	b.n	80015c2 <HAL_ADC_ConfigChannel+0x1aa>
  }
  /* For Rank 13 to 16 */
  else
  {
    /* Clear the old SQx bits for the selected rank */
    hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
 800157a:	687b      	ldr	r3, [r7, #4]
 800157c:	681b      	ldr	r3, [r3, #0]
 800157e:	6ad9      	ldr	r1, [r3, #44]	; 0x2c
 8001580:	683b      	ldr	r3, [r7, #0]
 8001582:	685a      	ldr	r2, [r3, #4]
 8001584:	4613      	mov	r3, r2
 8001586:	009b      	lsls	r3, r3, #2
 8001588:	4413      	add	r3, r2
 800158a:	3b41      	subs	r3, #65	; 0x41
 800158c:	221f      	movs	r2, #31
 800158e:	fa02 f303 	lsl.w	r3, r2, r3
 8001592:	43da      	mvns	r2, r3
 8001594:	687b      	ldr	r3, [r7, #4]
 8001596:	681b      	ldr	r3, [r3, #0]
 8001598:	400a      	ands	r2, r1
 800159a:	62da      	str	r2, [r3, #44]	; 0x2c
    
    /* Set the SQx bits for the selected rank */
    hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
 800159c:	687b      	ldr	r3, [r7, #4]
 800159e:	681b      	ldr	r3, [r3, #0]
 80015a0:	6ad9      	ldr	r1, [r3, #44]	; 0x2c
 80015a2:	683b      	ldr	r3, [r7, #0]
 80015a4:	681b      	ldr	r3, [r3, #0]
 80015a6:	b29b      	uxth	r3, r3
 80015a8:	4618      	mov	r0, r3
 80015aa:	683b      	ldr	r3, [r7, #0]
 80015ac:	685a      	ldr	r2, [r3, #4]
 80015ae:	4613      	mov	r3, r2
 80015b0:	009b      	lsls	r3, r3, #2
 80015b2:	4413      	add	r3, r2
 80015b4:	3b41      	subs	r3, #65	; 0x41
 80015b6:	fa00 f203 	lsl.w	r2, r0, r3
 80015ba:	687b      	ldr	r3, [r7, #4]
 80015bc:	681b      	ldr	r3, [r3, #0]
 80015be:	430a      	orrs	r2, r1
 80015c0:	62da      	str	r2, [r3, #44]	; 0x2c
  }

    /* Pointer to the common control register to which is belonging hadc    */
    /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
    /* control register)                                                    */
    tmpADC_Common = ADC_COMMON_REGISTER(hadc);
 80015c2:	4b29      	ldr	r3, [pc, #164]	; (8001668 <HAL_ADC_ConfigChannel+0x250>)
 80015c4:	60fb      	str	r3, [r7, #12]

  /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */
  if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
 80015c6:	687b      	ldr	r3, [r7, #4]
 80015c8:	681b      	ldr	r3, [r3, #0]
 80015ca:	4a28      	ldr	r2, [pc, #160]	; (800166c <HAL_ADC_ConfigChannel+0x254>)
 80015cc:	4293      	cmp	r3, r2
 80015ce:	d10f      	bne.n	80015f0 <HAL_ADC_ConfigChannel+0x1d8>
 80015d0:	683b      	ldr	r3, [r7, #0]
 80015d2:	681b      	ldr	r3, [r3, #0]
 80015d4:	2b12      	cmp	r3, #18
 80015d6:	d10b      	bne.n	80015f0 <HAL_ADC_ConfigChannel+0x1d8>
  {
    /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/    
    if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
    {
      tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;
 80015d8:	68fb      	ldr	r3, [r7, #12]
 80015da:	685b      	ldr	r3, [r3, #4]
 80015dc:	f423 0200 	bic.w	r2, r3, #8388608	; 0x800000
 80015e0:	68fb      	ldr	r3, [r7, #12]
 80015e2:	605a      	str	r2, [r3, #4]
    }
    /* Enable the VBAT channel*/
    tmpADC_Common->CCR |= ADC_CCR_VBATE;
 80015e4:	68fb      	ldr	r3, [r7, #12]
 80015e6:	685b      	ldr	r3, [r3, #4]
 80015e8:	f443 0280 	orr.w	r2, r3, #4194304	; 0x400000
 80015ec:	68fb      	ldr	r3, [r7, #12]
 80015ee:	605a      	str	r2, [r3, #4]
  }
  
  /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or 
     Channel_17 is selected for VREFINT enable TSVREFE */
  if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
 80015f0:	687b      	ldr	r3, [r7, #4]
 80015f2:	681b      	ldr	r3, [r3, #0]
 80015f4:	4a1d      	ldr	r2, [pc, #116]	; (800166c <HAL_ADC_ConfigChannel+0x254>)
 80015f6:	4293      	cmp	r3, r2
 80015f8:	d12b      	bne.n	8001652 <HAL_ADC_ConfigChannel+0x23a>
 80015fa:	683b      	ldr	r3, [r7, #0]
 80015fc:	681b      	ldr	r3, [r3, #0]
 80015fe:	4a1c      	ldr	r2, [pc, #112]	; (8001670 <HAL_ADC_ConfigChannel+0x258>)
 8001600:	4293      	cmp	r3, r2
 8001602:	d003      	beq.n	800160c <HAL_ADC_ConfigChannel+0x1f4>
 8001604:	683b      	ldr	r3, [r7, #0]
 8001606:	681b      	ldr	r3, [r3, #0]
 8001608:	2b11      	cmp	r3, #17
 800160a:	d122      	bne.n	8001652 <HAL_ADC_ConfigChannel+0x23a>
  {
    /* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
    if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
    {
      tmpADC_Common->CCR &= ~ADC_CCR_VBATE;
 800160c:	68fb      	ldr	r3, [r7, #12]
 800160e:	685b      	ldr	r3, [r3, #4]
 8001610:	f423 0280 	bic.w	r2, r3, #4194304	; 0x400000
 8001614:	68fb      	ldr	r3, [r7, #12]
 8001616:	605a      	str	r2, [r3, #4]
    }
    /* Enable the Temperature sensor and VREFINT channel*/
    tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
 8001618:	68fb      	ldr	r3, [r7, #12]
 800161a:	685b      	ldr	r3, [r3, #4]
 800161c:	f443 0200 	orr.w	r2, r3, #8388608	; 0x800000
 8001620:	68fb      	ldr	r3, [r7, #12]
 8001622:	605a      	str	r2, [r3, #4]
    
    if(sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
 8001624:	683b      	ldr	r3, [r7, #0]
 8001626:	681b      	ldr	r3, [r3, #0]
 8001628:	4a11      	ldr	r2, [pc, #68]	; (8001670 <HAL_ADC_ConfigChannel+0x258>)
 800162a:	4293      	cmp	r3, r2
 800162c:	d111      	bne.n	8001652 <HAL_ADC_ConfigChannel+0x23a>
    {
      /* Delay for temperature sensor stabilization time */
      /* Compute number of CPU cycles to wait for */
      counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
 800162e:	4b11      	ldr	r3, [pc, #68]	; (8001674 <HAL_ADC_ConfigChannel+0x25c>)
 8001630:	681b      	ldr	r3, [r3, #0]
 8001632:	4a11      	ldr	r2, [pc, #68]	; (8001678 <HAL_ADC_ConfigChannel+0x260>)
 8001634:	fba2 2303 	umull	r2, r3, r2, r3
 8001638:	0c9a      	lsrs	r2, r3, #18
 800163a:	4613      	mov	r3, r2
 800163c:	009b      	lsls	r3, r3, #2
 800163e:	4413      	add	r3, r2
 8001640:	005b      	lsls	r3, r3, #1
 8001642:	60bb      	str	r3, [r7, #8]
      while(counter != 0U)
 8001644:	e002      	b.n	800164c <HAL_ADC_ConfigChannel+0x234>
      {
        counter--;
 8001646:	68bb      	ldr	r3, [r7, #8]
 8001648:	3b01      	subs	r3, #1
 800164a:	60bb      	str	r3, [r7, #8]
      while(counter != 0U)
 800164c:	68bb      	ldr	r3, [r7, #8]
 800164e:	2b00      	cmp	r3, #0
 8001650:	d1f9      	bne.n	8001646 <HAL_ADC_ConfigChannel+0x22e>
      }
    }
  }
  
  /* Process unlocked */
  __HAL_UNLOCK(hadc);
 8001652:	687b      	ldr	r3, [r7, #4]
 8001654:	2200      	movs	r2, #0
 8001656:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
  
  /* Return function status */
  return HAL_OK;
 800165a:	2300      	movs	r3, #0
}
 800165c:	4618      	mov	r0, r3
 800165e:	3714      	adds	r7, #20
 8001660:	46bd      	mov	sp, r7
 8001662:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001666:	4770      	bx	lr
 8001668:	40012300 	.word	0x40012300
 800166c:	40012000 	.word	0x40012000
 8001670:	10000012 	.word	0x10000012
 8001674:	20000000 	.word	0x20000000
 8001678:	431bde83 	.word	0x431bde83

0800167c <ADC_Init>:
  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
  *         the configuration information for the specified ADC.  
  * @retval None
  */
static void ADC_Init(ADC_HandleTypeDef* hadc)
{
 800167c:	b480      	push	{r7}
 800167e:	b085      	sub	sp, #20
 8001680:	af00      	add	r7, sp, #0
 8001682:	6078      	str	r0, [r7, #4]
  
  /* Set ADC parameters */
  /* Pointer to the common control register to which is belonging hadc    */
  /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
  /* control register)                                                    */
  tmpADC_Common = ADC_COMMON_REGISTER(hadc);
 8001684:	4b79      	ldr	r3, [pc, #484]	; (800186c <ADC_Init+0x1f0>)
 8001686:	60fb      	str	r3, [r7, #12]
  
  /* Set the ADC clock prescaler */
  tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
 8001688:	68fb      	ldr	r3, [r7, #12]
 800168a:	685b      	ldr	r3, [r3, #4]
 800168c:	f423 3240 	bic.w	r2, r3, #196608	; 0x30000
 8001690:	68fb      	ldr	r3, [r7, #12]
 8001692:	605a      	str	r2, [r3, #4]
  tmpADC_Common->CCR |=  hadc->Init.ClockPrescaler;
 8001694:	68fb      	ldr	r3, [r7, #12]
 8001696:	685a      	ldr	r2, [r3, #4]
 8001698:	687b      	ldr	r3, [r7, #4]
 800169a:	685b      	ldr	r3, [r3, #4]
 800169c:	431a      	orrs	r2, r3
 800169e:	68fb      	ldr	r3, [r7, #12]
 80016a0:	605a      	str	r2, [r3, #4]
  
  /* Set ADC scan mode */
  hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
 80016a2:	687b      	ldr	r3, [r7, #4]
 80016a4:	681b      	ldr	r3, [r3, #0]
 80016a6:	685a      	ldr	r2, [r3, #4]
 80016a8:	687b      	ldr	r3, [r7, #4]
 80016aa:	681b      	ldr	r3, [r3, #0]
 80016ac:	f422 7280 	bic.w	r2, r2, #256	; 0x100
 80016b0:	605a      	str	r2, [r3, #4]
  hadc->Instance->CR1 |=  ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
 80016b2:	687b      	ldr	r3, [r7, #4]
 80016b4:	681b      	ldr	r3, [r3, #0]
 80016b6:	6859      	ldr	r1, [r3, #4]
 80016b8:	687b      	ldr	r3, [r7, #4]
 80016ba:	691b      	ldr	r3, [r3, #16]
 80016bc:	021a      	lsls	r2, r3, #8
 80016be:	687b      	ldr	r3, [r7, #4]
 80016c0:	681b      	ldr	r3, [r3, #0]
 80016c2:	430a      	orrs	r2, r1
 80016c4:	605a      	str	r2, [r3, #4]
  
  /* Set ADC resolution */
  hadc->Instance->CR1 &= ~(ADC_CR1_RES);
 80016c6:	687b      	ldr	r3, [r7, #4]
 80016c8:	681b      	ldr	r3, [r3, #0]
 80016ca:	685a      	ldr	r2, [r3, #4]
 80016cc:	687b      	ldr	r3, [r7, #4]
 80016ce:	681b      	ldr	r3, [r3, #0]
 80016d0:	f022 7240 	bic.w	r2, r2, #50331648	; 0x3000000
 80016d4:	605a      	str	r2, [r3, #4]
  hadc->Instance->CR1 |=  hadc->Init.Resolution;
 80016d6:	687b      	ldr	r3, [r7, #4]
 80016d8:	681b      	ldr	r3, [r3, #0]
 80016da:	6859      	ldr	r1, [r3, #4]
 80016dc:	687b      	ldr	r3, [r7, #4]
 80016de:	689a      	ldr	r2, [r3, #8]
 80016e0:	687b      	ldr	r3, [r7, #4]
 80016e2:	681b      	ldr	r3, [r3, #0]
 80016e4:	430a      	orrs	r2, r1
 80016e6:	605a      	str	r2, [r3, #4]
  
  /* Set ADC data alignment */
  hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
 80016e8:	687b      	ldr	r3, [r7, #4]
 80016ea:	681b      	ldr	r3, [r3, #0]
 80016ec:	689a      	ldr	r2, [r3, #8]
 80016ee:	687b      	ldr	r3, [r7, #4]
 80016f0:	681b      	ldr	r3, [r3, #0]
 80016f2:	f422 6200 	bic.w	r2, r2, #2048	; 0x800
 80016f6:	609a      	str	r2, [r3, #8]
  hadc->Instance->CR2 |= hadc->Init.DataAlign;
 80016f8:	687b      	ldr	r3, [r7, #4]
 80016fa:	681b      	ldr	r3, [r3, #0]
 80016fc:	6899      	ldr	r1, [r3, #8]
 80016fe:	687b      	ldr	r3, [r7, #4]
 8001700:	68da      	ldr	r2, [r3, #12]
 8001702:	687b      	ldr	r3, [r7, #4]
 8001704:	681b      	ldr	r3, [r3, #0]
 8001706:	430a      	orrs	r2, r1
 8001708:	609a      	str	r2, [r3, #8]
  /* Enable external trigger if trigger selection is different of software  */
  /* start.                                                                 */
  /* Note: This configuration keeps the hardware feature of parameter       */
  /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
  /*       software start.                                                  */
  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
 800170a:	687b      	ldr	r3, [r7, #4]
 800170c:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800170e:	4a58      	ldr	r2, [pc, #352]	; (8001870 <ADC_Init+0x1f4>)
 8001710:	4293      	cmp	r3, r2
 8001712:	d022      	beq.n	800175a <ADC_Init+0xde>
  {
    /* Select external trigger to start conversion */
    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
 8001714:	687b      	ldr	r3, [r7, #4]
 8001716:	681b      	ldr	r3, [r3, #0]
 8001718:	689a      	ldr	r2, [r3, #8]
 800171a:	687b      	ldr	r3, [r7, #4]
 800171c:	681b      	ldr	r3, [r3, #0]
 800171e:	f022 6270 	bic.w	r2, r2, #251658240	; 0xf000000
 8001722:	609a      	str	r2, [r3, #8]
    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
 8001724:	687b      	ldr	r3, [r7, #4]
 8001726:	681b      	ldr	r3, [r3, #0]
 8001728:	6899      	ldr	r1, [r3, #8]
 800172a:	687b      	ldr	r3, [r7, #4]
 800172c:	6a9a      	ldr	r2, [r3, #40]	; 0x28
 800172e:	687b      	ldr	r3, [r7, #4]
 8001730:	681b      	ldr	r3, [r3, #0]
 8001732:	430a      	orrs	r2, r1
 8001734:	609a      	str	r2, [r3, #8]
    
    /* Select external trigger polarity */
    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
 8001736:	687b      	ldr	r3, [r7, #4]
 8001738:	681b      	ldr	r3, [r3, #0]
 800173a:	689a      	ldr	r2, [r3, #8]
 800173c:	687b      	ldr	r3, [r7, #4]
 800173e:	681b      	ldr	r3, [r3, #0]
 8001740:	f022 5240 	bic.w	r2, r2, #805306368	; 0x30000000
 8001744:	609a      	str	r2, [r3, #8]
    hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
 8001746:	687b      	ldr	r3, [r7, #4]
 8001748:	681b      	ldr	r3, [r3, #0]
 800174a:	6899      	ldr	r1, [r3, #8]
 800174c:	687b      	ldr	r3, [r7, #4]
 800174e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8001750:	687b      	ldr	r3, [r7, #4]
 8001752:	681b      	ldr	r3, [r3, #0]
 8001754:	430a      	orrs	r2, r1
 8001756:	609a      	str	r2, [r3, #8]
 8001758:	e00f      	b.n	800177a <ADC_Init+0xfe>
  }
  else
  {
    /* Reset the external trigger */
    hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
 800175a:	687b      	ldr	r3, [r7, #4]
 800175c:	681b      	ldr	r3, [r3, #0]
 800175e:	689a      	ldr	r2, [r3, #8]
 8001760:	687b      	ldr	r3, [r7, #4]
 8001762:	681b      	ldr	r3, [r3, #0]
 8001764:	f022 6270 	bic.w	r2, r2, #251658240	; 0xf000000
 8001768:	609a      	str	r2, [r3, #8]
    hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
 800176a:	687b      	ldr	r3, [r7, #4]
 800176c:	681b      	ldr	r3, [r3, #0]
 800176e:	689a      	ldr	r2, [r3, #8]
 8001770:	687b      	ldr	r3, [r7, #4]
 8001772:	681b      	ldr	r3, [r3, #0]
 8001774:	f022 5240 	bic.w	r2, r2, #805306368	; 0x30000000
 8001778:	609a      	str	r2, [r3, #8]
  }
  
  /* Enable or disable ADC continuous conversion mode */
  hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
 800177a:	687b      	ldr	r3, [r7, #4]
 800177c:	681b      	ldr	r3, [r3, #0]
 800177e:	689a      	ldr	r2, [r3, #8]
 8001780:	687b      	ldr	r3, [r7, #4]
 8001782:	681b      	ldr	r3, [r3, #0]
 8001784:	f022 0202 	bic.w	r2, r2, #2
 8001788:	609a      	str	r2, [r3, #8]
  hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
 800178a:	687b      	ldr	r3, [r7, #4]
 800178c:	681b      	ldr	r3, [r3, #0]
 800178e:	6899      	ldr	r1, [r3, #8]
 8001790:	687b      	ldr	r3, [r7, #4]
 8001792:	7e1b      	ldrb	r3, [r3, #24]
 8001794:	005a      	lsls	r2, r3, #1
 8001796:	687b      	ldr	r3, [r7, #4]
 8001798:	681b      	ldr	r3, [r3, #0]
 800179a:	430a      	orrs	r2, r1
 800179c:	609a      	str	r2, [r3, #8]
  
  if(hadc->Init.DiscontinuousConvMode != DISABLE)
 800179e:	687b      	ldr	r3, [r7, #4]
 80017a0:	f893 3020 	ldrb.w	r3, [r3, #32]
 80017a4:	2b00      	cmp	r3, #0
 80017a6:	d01b      	beq.n	80017e0 <ADC_Init+0x164>
  {
    assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
  
    /* Enable the selected ADC regular discontinuous mode */
    hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
 80017a8:	687b      	ldr	r3, [r7, #4]
 80017aa:	681b      	ldr	r3, [r3, #0]
 80017ac:	685a      	ldr	r2, [r3, #4]
 80017ae:	687b      	ldr	r3, [r7, #4]
 80017b0:	681b      	ldr	r3, [r3, #0]
 80017b2:	f442 6200 	orr.w	r2, r2, #2048	; 0x800
 80017b6:	605a      	str	r2, [r3, #4]
    
    /* Set the number of channels to be converted in discontinuous mode */
    hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
 80017b8:	687b      	ldr	r3, [r7, #4]
 80017ba:	681b      	ldr	r3, [r3, #0]
 80017bc:	685a      	ldr	r2, [r3, #4]
 80017be:	687b      	ldr	r3, [r7, #4]
 80017c0:	681b      	ldr	r3, [r3, #0]
 80017c2:	f422 4260 	bic.w	r2, r2, #57344	; 0xe000
 80017c6:	605a      	str	r2, [r3, #4]
    hadc->Instance->CR1 |=  ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
 80017c8:	687b      	ldr	r3, [r7, #4]
 80017ca:	681b      	ldr	r3, [r3, #0]
 80017cc:	6859      	ldr	r1, [r3, #4]
 80017ce:	687b      	ldr	r3, [r7, #4]
 80017d0:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80017d2:	3b01      	subs	r3, #1
 80017d4:	035a      	lsls	r2, r3, #13
 80017d6:	687b      	ldr	r3, [r7, #4]
 80017d8:	681b      	ldr	r3, [r3, #0]
 80017da:	430a      	orrs	r2, r1
 80017dc:	605a      	str	r2, [r3, #4]
 80017de:	e007      	b.n	80017f0 <ADC_Init+0x174>
  }
  else
  {
    /* Disable the selected ADC regular discontinuous mode */
    hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
 80017e0:	687b      	ldr	r3, [r7, #4]
 80017e2:	681b      	ldr	r3, [r3, #0]
 80017e4:	685a      	ldr	r2, [r3, #4]
 80017e6:	687b      	ldr	r3, [r7, #4]
 80017e8:	681b      	ldr	r3, [r3, #0]
 80017ea:	f422 6200 	bic.w	r2, r2, #2048	; 0x800
 80017ee:	605a      	str	r2, [r3, #4]
  }
  
  /* Set ADC number of conversion */
  hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
 80017f0:	687b      	ldr	r3, [r7, #4]
 80017f2:	681b      	ldr	r3, [r3, #0]
 80017f4:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80017f6:	687b      	ldr	r3, [r7, #4]
 80017f8:	681b      	ldr	r3, [r3, #0]
 80017fa:	f422 0270 	bic.w	r2, r2, #15728640	; 0xf00000
 80017fe:	62da      	str	r2, [r3, #44]	; 0x2c
  hadc->Instance->SQR1 |=  ADC_SQR1(hadc->Init.NbrOfConversion);
 8001800:	687b      	ldr	r3, [r7, #4]
 8001802:	681b      	ldr	r3, [r3, #0]
 8001804:	6ad9      	ldr	r1, [r3, #44]	; 0x2c
 8001806:	687b      	ldr	r3, [r7, #4]
 8001808:	69db      	ldr	r3, [r3, #28]
 800180a:	3b01      	subs	r3, #1
 800180c:	051a      	lsls	r2, r3, #20
 800180e:	687b      	ldr	r3, [r7, #4]
 8001810:	681b      	ldr	r3, [r3, #0]
 8001812:	430a      	orrs	r2, r1
 8001814:	62da      	str	r2, [r3, #44]	; 0x2c
  
  /* Enable or disable ADC DMA continuous request */
  hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
 8001816:	687b      	ldr	r3, [r7, #4]
 8001818:	681b      	ldr	r3, [r3, #0]
 800181a:	689a      	ldr	r2, [r3, #8]
 800181c:	687b      	ldr	r3, [r7, #4]
 800181e:	681b      	ldr	r3, [r3, #0]
 8001820:	f422 7200 	bic.w	r2, r2, #512	; 0x200
 8001824:	609a      	str	r2, [r3, #8]
  hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
 8001826:	687b      	ldr	r3, [r7, #4]
 8001828:	681b      	ldr	r3, [r3, #0]
 800182a:	6899      	ldr	r1, [r3, #8]
 800182c:	687b      	ldr	r3, [r7, #4]
 800182e:	f893 3030 	ldrb.w	r3, [r3, #48]	; 0x30
 8001832:	025a      	lsls	r2, r3, #9
 8001834:	687b      	ldr	r3, [r7, #4]
 8001836:	681b      	ldr	r3, [r3, #0]
 8001838:	430a      	orrs	r2, r1
 800183a:	609a      	str	r2, [r3, #8]
  
  /* Enable or disable ADC end of conversion selection */
  hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
 800183c:	687b      	ldr	r3, [r7, #4]
 800183e:	681b      	ldr	r3, [r3, #0]
 8001840:	689a      	ldr	r2, [r3, #8]
 8001842:	687b      	ldr	r3, [r7, #4]
 8001844:	681b      	ldr	r3, [r3, #0]
 8001846:	f422 6280 	bic.w	r2, r2, #1024	; 0x400
 800184a:	609a      	str	r2, [r3, #8]
  hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
 800184c:	687b      	ldr	r3, [r7, #4]
 800184e:	681b      	ldr	r3, [r3, #0]
 8001850:	6899      	ldr	r1, [r3, #8]
 8001852:	687b      	ldr	r3, [r7, #4]
 8001854:	695b      	ldr	r3, [r3, #20]
 8001856:	029a      	lsls	r2, r3, #10
 8001858:	687b      	ldr	r3, [r7, #4]
 800185a:	681b      	ldr	r3, [r3, #0]
 800185c:	430a      	orrs	r2, r1
 800185e:	609a      	str	r2, [r3, #8]
}
 8001860:	bf00      	nop
 8001862:	3714      	adds	r7, #20
 8001864:	46bd      	mov	sp, r7
 8001866:	f85d 7b04 	ldr.w	r7, [sp], #4
 800186a:	4770      	bx	lr
 800186c:	40012300 	.word	0x40012300
 8001870:	0f000001 	.word	0x0f000001

08001874 <HAL_ADCEx_InjectedConvCpltCallback>:
  * @param  hadc pointer to a ADC_HandleTypeDef structure that contains
  *         the configuration information for the specified ADC.
  * @retval None
  */
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
{
 8001874:	b480      	push	{r7}
 8001876:	b083      	sub	sp, #12
 8001878:	af00      	add	r7, sp, #0
 800187a:	6078      	str	r0, [r7, #4]
  /* Prevent unused argument(s) compilation warning */
  UNUSED(hadc);
  /* NOTE : This function Should not be modified, when the callback is needed,
            the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
   */
}
 800187c:	bf00      	nop
 800187e:	370c      	adds	r7, #12
 8001880:	46bd      	mov	sp, r7
 8001882:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001886:	4770      	bx	lr

08001888 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8001888:	b480      	push	{r7}
 800188a:	b085      	sub	sp, #20
 800188c:	af00      	add	r7, sp, #0
 800188e:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8001890:	687b      	ldr	r3, [r7, #4]
 8001892:	f003 0307 	and.w	r3, r3, #7
 8001896:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8001898:	4b0c      	ldr	r3, [pc, #48]	; (80018cc <__NVIC_SetPriorityGrouping+0x44>)
 800189a:	68db      	ldr	r3, [r3, #12]
 800189c:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 800189e:	68ba      	ldr	r2, [r7, #8]
 80018a0:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
 80018a4:	4013      	ands	r3, r2
 80018a6:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
 80018a8:	68fb      	ldr	r3, [r7, #12]
 80018aa:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 80018ac:	68bb      	ldr	r3, [r7, #8]
 80018ae:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 80018b0:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 80018b4:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 80018b8:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 80018ba:	4a04      	ldr	r2, [pc, #16]	; (80018cc <__NVIC_SetPriorityGrouping+0x44>)
 80018bc:	68bb      	ldr	r3, [r7, #8]
 80018be:	60d3      	str	r3, [r2, #12]
}
 80018c0:	bf00      	nop
 80018c2:	3714      	adds	r7, #20
 80018c4:	46bd      	mov	sp, r7
 80018c6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80018ca:	4770      	bx	lr
 80018cc:	e000ed00 	.word	0xe000ed00

080018d0 <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 80018d0:	b480      	push	{r7}
 80018d2:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 80018d4:	4b04      	ldr	r3, [pc, #16]	; (80018e8 <__NVIC_GetPriorityGrouping+0x18>)
 80018d6:	68db      	ldr	r3, [r3, #12]
 80018d8:	0a1b      	lsrs	r3, r3, #8
 80018da:	f003 0307 	and.w	r3, r3, #7
}
 80018de:	4618      	mov	r0, r3
 80018e0:	46bd      	mov	sp, r7
 80018e2:	f85d 7b04 	ldr.w	r7, [sp], #4
 80018e6:	4770      	bx	lr
 80018e8:	e000ed00 	.word	0xe000ed00

080018ec <__NVIC_EnableIRQ>:
  \details Enables a device specific interrupt in the NVIC interrupt controller.
  \param [in]      IRQn  Device specific interrupt number.
  \note    IRQn must not be negative.
 */
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
 80018ec:	b480      	push	{r7}
 80018ee:	b083      	sub	sp, #12
 80018f0:	af00      	add	r7, sp, #0
 80018f2:	4603      	mov	r3, r0
 80018f4:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 80018f6:	f997 3007 	ldrsb.w	r3, [r7, #7]
 80018fa:	2b00      	cmp	r3, #0
 80018fc:	db0b      	blt.n	8001916 <__NVIC_EnableIRQ+0x2a>
  {
    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
 80018fe:	79fb      	ldrb	r3, [r7, #7]
 8001900:	f003 021f 	and.w	r2, r3, #31
 8001904:	4907      	ldr	r1, [pc, #28]	; (8001924 <__NVIC_EnableIRQ+0x38>)
 8001906:	f997 3007 	ldrsb.w	r3, [r7, #7]
 800190a:	095b      	lsrs	r3, r3, #5
 800190c:	2001      	movs	r0, #1
 800190e:	fa00 f202 	lsl.w	r2, r0, r2
 8001912:	f841 2023 	str.w	r2, [r1, r3, lsl #2]
  }
}
 8001916:	bf00      	nop
 8001918:	370c      	adds	r7, #12
 800191a:	46bd      	mov	sp, r7
 800191c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001920:	4770      	bx	lr
 8001922:	bf00      	nop
 8001924:	e000e100 	.word	0xe000e100

08001928 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8001928:	b480      	push	{r7}
 800192a:	b083      	sub	sp, #12
 800192c:	af00      	add	r7, sp, #0
 800192e:	4603      	mov	r3, r0
 8001930:	6039      	str	r1, [r7, #0]
 8001932:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8001934:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001938:	2b00      	cmp	r3, #0
 800193a:	db0a      	blt.n	8001952 <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800193c:	683b      	ldr	r3, [r7, #0]
 800193e:	b2da      	uxtb	r2, r3
 8001940:	490c      	ldr	r1, [pc, #48]	; (8001974 <__NVIC_SetPriority+0x4c>)
 8001942:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001946:	0112      	lsls	r2, r2, #4
 8001948:	b2d2      	uxtb	r2, r2
 800194a:	440b      	add	r3, r1
 800194c:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 8001950:	e00a      	b.n	8001968 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8001952:	683b      	ldr	r3, [r7, #0]
 8001954:	b2da      	uxtb	r2, r3
 8001956:	4908      	ldr	r1, [pc, #32]	; (8001978 <__NVIC_SetPriority+0x50>)
 8001958:	79fb      	ldrb	r3, [r7, #7]
 800195a:	f003 030f 	and.w	r3, r3, #15
 800195e:	3b04      	subs	r3, #4
 8001960:	0112      	lsls	r2, r2, #4
 8001962:	b2d2      	uxtb	r2, r2
 8001964:	440b      	add	r3, r1
 8001966:	761a      	strb	r2, [r3, #24]
}
 8001968:	bf00      	nop
 800196a:	370c      	adds	r7, #12
 800196c:	46bd      	mov	sp, r7
 800196e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001972:	4770      	bx	lr
 8001974:	e000e100 	.word	0xe000e100
 8001978:	e000ed00 	.word	0xe000ed00

0800197c <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 800197c:	b480      	push	{r7}
 800197e:	b089      	sub	sp, #36	; 0x24
 8001980:	af00      	add	r7, sp, #0
 8001982:	60f8      	str	r0, [r7, #12]
 8001984:	60b9      	str	r1, [r7, #8]
 8001986:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8001988:	68fb      	ldr	r3, [r7, #12]
 800198a:	f003 0307 	and.w	r3, r3, #7
 800198e:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8001990:	69fb      	ldr	r3, [r7, #28]
 8001992:	f1c3 0307 	rsb	r3, r3, #7
 8001996:	2b04      	cmp	r3, #4
 8001998:	bf28      	it	cs
 800199a:	2304      	movcs	r3, #4
 800199c:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 800199e:	69fb      	ldr	r3, [r7, #28]
 80019a0:	3304      	adds	r3, #4
 80019a2:	2b06      	cmp	r3, #6
 80019a4:	d902      	bls.n	80019ac <NVIC_EncodePriority+0x30>
 80019a6:	69fb      	ldr	r3, [r7, #28]
 80019a8:	3b03      	subs	r3, #3
 80019aa:	e000      	b.n	80019ae <NVIC_EncodePriority+0x32>
 80019ac:	2300      	movs	r3, #0
 80019ae:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80019b0:	f04f 32ff 	mov.w	r2, #4294967295
 80019b4:	69bb      	ldr	r3, [r7, #24]
 80019b6:	fa02 f303 	lsl.w	r3, r2, r3
 80019ba:	43da      	mvns	r2, r3
 80019bc:	68bb      	ldr	r3, [r7, #8]
 80019be:	401a      	ands	r2, r3
 80019c0:	697b      	ldr	r3, [r7, #20]
 80019c2:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 80019c4:	f04f 31ff 	mov.w	r1, #4294967295
 80019c8:	697b      	ldr	r3, [r7, #20]
 80019ca:	fa01 f303 	lsl.w	r3, r1, r3
 80019ce:	43d9      	mvns	r1, r3
 80019d0:	687b      	ldr	r3, [r7, #4]
 80019d2:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 80019d4:	4313      	orrs	r3, r2
         );
}
 80019d6:	4618      	mov	r0, r3
 80019d8:	3724      	adds	r7, #36	; 0x24
 80019da:	46bd      	mov	sp, r7
 80019dc:	f85d 7b04 	ldr.w	r7, [sp], #4
 80019e0:	4770      	bx	lr

080019e2 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 80019e2:	b580      	push	{r7, lr}
 80019e4:	b082      	sub	sp, #8
 80019e6:	af00      	add	r7, sp, #0
 80019e8:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 80019ea:	6878      	ldr	r0, [r7, #4]
 80019ec:	f7ff ff4c 	bl	8001888 <__NVIC_SetPriorityGrouping>
}
 80019f0:	bf00      	nop
 80019f2:	3708      	adds	r7, #8
 80019f4:	46bd      	mov	sp, r7
 80019f6:	bd80      	pop	{r7, pc}

080019f8 <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 80019f8:	b580      	push	{r7, lr}
 80019fa:	b086      	sub	sp, #24
 80019fc:	af00      	add	r7, sp, #0
 80019fe:	4603      	mov	r3, r0
 8001a00:	60b9      	str	r1, [r7, #8]
 8001a02:	607a      	str	r2, [r7, #4]
 8001a04:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00U;
 8001a06:	2300      	movs	r3, #0
 8001a08:	617b      	str	r3, [r7, #20]
  
  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  
  prioritygroup = NVIC_GetPriorityGrouping();
 8001a0a:	f7ff ff61 	bl	80018d0 <__NVIC_GetPriorityGrouping>
 8001a0e:	6178      	str	r0, [r7, #20]
  
  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 8001a10:	687a      	ldr	r2, [r7, #4]
 8001a12:	68b9      	ldr	r1, [r7, #8]
 8001a14:	6978      	ldr	r0, [r7, #20]
 8001a16:	f7ff ffb1 	bl	800197c <NVIC_EncodePriority>
 8001a1a:	4602      	mov	r2, r0
 8001a1c:	f997 300f 	ldrsb.w	r3, [r7, #15]
 8001a20:	4611      	mov	r1, r2
 8001a22:	4618      	mov	r0, r3
 8001a24:	f7ff ff80 	bl	8001928 <__NVIC_SetPriority>
}
 8001a28:	bf00      	nop
 8001a2a:	3718      	adds	r7, #24
 8001a2c:	46bd      	mov	sp, r7
 8001a2e:	bd80      	pop	{r7, pc}

08001a30 <HAL_NVIC_EnableIRQ>:
  *         This parameter can be an enumerator of IRQn_Type enumeration
  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
  * @retval None
  */
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
 8001a30:	b580      	push	{r7, lr}
 8001a32:	b082      	sub	sp, #8
 8001a34:	af00      	add	r7, sp, #0
 8001a36:	4603      	mov	r3, r0
 8001a38:	71fb      	strb	r3, [r7, #7]
  /* Check the parameters */
  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
  
  /* Enable interrupt */
  NVIC_EnableIRQ(IRQn);
 8001a3a:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8001a3e:	4618      	mov	r0, r3
 8001a40:	f7ff ff54 	bl	80018ec <__NVIC_EnableIRQ>
}
 8001a44:	bf00      	nop
 8001a46:	3708      	adds	r7, #8
 8001a48:	46bd      	mov	sp, r7
 8001a4a:	bd80      	pop	{r7, pc}

08001a4c <HAL_GPIO_Init>:
  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 8001a4c:	b480      	push	{r7}
 8001a4e:	b089      	sub	sp, #36	; 0x24
 8001a50:	af00      	add	r7, sp, #0
 8001a52:	6078      	str	r0, [r7, #4]
 8001a54:	6039      	str	r1, [r7, #0]
  uint32_t position;
  uint32_t ioposition = 0x00U;
 8001a56:	2300      	movs	r3, #0
 8001a58:	617b      	str	r3, [r7, #20]
  uint32_t iocurrent = 0x00U;
 8001a5a:	2300      	movs	r3, #0
 8001a5c:	613b      	str	r3, [r7, #16]
  uint32_t temp = 0x00U;
 8001a5e:	2300      	movs	r3, #0
 8001a60:	61bb      	str	r3, [r7, #24]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  for(position = 0U; position < GPIO_NUMBER; position++)
 8001a62:	2300      	movs	r3, #0
 8001a64:	61fb      	str	r3, [r7, #28]
 8001a66:	e159      	b.n	8001d1c <HAL_GPIO_Init+0x2d0>
  {
    /* Get the IO position */
    ioposition = 0x01U << position;
 8001a68:	2201      	movs	r2, #1
 8001a6a:	69fb      	ldr	r3, [r7, #28]
 8001a6c:	fa02 f303 	lsl.w	r3, r2, r3
 8001a70:	617b      	str	r3, [r7, #20]
    /* Get the current IO position */
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 8001a72:	683b      	ldr	r3, [r7, #0]
 8001a74:	681b      	ldr	r3, [r3, #0]
 8001a76:	697a      	ldr	r2, [r7, #20]
 8001a78:	4013      	ands	r3, r2
 8001a7a:	613b      	str	r3, [r7, #16]

    if(iocurrent == ioposition)
 8001a7c:	693a      	ldr	r2, [r7, #16]
 8001a7e:	697b      	ldr	r3, [r7, #20]
 8001a80:	429a      	cmp	r2, r3
 8001a82:	f040 8148 	bne.w	8001d16 <HAL_GPIO_Init+0x2ca>
    {
      /*--------------------- GPIO Mode Configuration ------------------------*/
      /* In case of Output or Alternate function mode selection */
      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
 8001a86:	683b      	ldr	r3, [r7, #0]
 8001a88:	685b      	ldr	r3, [r3, #4]
 8001a8a:	f003 0303 	and.w	r3, r3, #3
 8001a8e:	2b01      	cmp	r3, #1
 8001a90:	d005      	beq.n	8001a9e <HAL_GPIO_Init+0x52>
          (GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8001a92:	683b      	ldr	r3, [r7, #0]
 8001a94:	685b      	ldr	r3, [r3, #4]
 8001a96:	f003 0303 	and.w	r3, r3, #3
      if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
 8001a9a:	2b02      	cmp	r3, #2
 8001a9c:	d130      	bne.n	8001b00 <HAL_GPIO_Init+0xb4>
      {
        /* Check the Speed parameter */
        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
        /* Configure the IO Speed */
        temp = GPIOx->OSPEEDR; 
 8001a9e:	687b      	ldr	r3, [r7, #4]
 8001aa0:	689b      	ldr	r3, [r3, #8]
 8001aa2:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
 8001aa4:	69fb      	ldr	r3, [r7, #28]
 8001aa6:	005b      	lsls	r3, r3, #1
 8001aa8:	2203      	movs	r2, #3
 8001aaa:	fa02 f303 	lsl.w	r3, r2, r3
 8001aae:	43db      	mvns	r3, r3
 8001ab0:	69ba      	ldr	r2, [r7, #24]
 8001ab2:	4013      	ands	r3, r2
 8001ab4:	61bb      	str	r3, [r7, #24]
        temp |= (GPIO_Init->Speed << (position * 2U));
 8001ab6:	683b      	ldr	r3, [r7, #0]
 8001ab8:	68da      	ldr	r2, [r3, #12]
 8001aba:	69fb      	ldr	r3, [r7, #28]
 8001abc:	005b      	lsls	r3, r3, #1
 8001abe:	fa02 f303 	lsl.w	r3, r2, r3
 8001ac2:	69ba      	ldr	r2, [r7, #24]
 8001ac4:	4313      	orrs	r3, r2
 8001ac6:	61bb      	str	r3, [r7, #24]
        GPIOx->OSPEEDR = temp;
 8001ac8:	687b      	ldr	r3, [r7, #4]
 8001aca:	69ba      	ldr	r2, [r7, #24]
 8001acc:	609a      	str	r2, [r3, #8]

        /* Configure the IO Output Type */
        temp = GPIOx->OTYPER;
 8001ace:	687b      	ldr	r3, [r7, #4]
 8001ad0:	685b      	ldr	r3, [r3, #4]
 8001ad2:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_OTYPER_OT_0 << position) ;
 8001ad4:	2201      	movs	r2, #1
 8001ad6:	69fb      	ldr	r3, [r7, #28]
 8001ad8:	fa02 f303 	lsl.w	r3, r2, r3
 8001adc:	43db      	mvns	r3, r3
 8001ade:	69ba      	ldr	r2, [r7, #24]
 8001ae0:	4013      	ands	r3, r2
 8001ae2:	61bb      	str	r3, [r7, #24]
        temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
 8001ae4:	683b      	ldr	r3, [r7, #0]
 8001ae6:	685b      	ldr	r3, [r3, #4]
 8001ae8:	091b      	lsrs	r3, r3, #4
 8001aea:	f003 0201 	and.w	r2, r3, #1
 8001aee:	69fb      	ldr	r3, [r7, #28]
 8001af0:	fa02 f303 	lsl.w	r3, r2, r3
 8001af4:	69ba      	ldr	r2, [r7, #24]
 8001af6:	4313      	orrs	r3, r2
 8001af8:	61bb      	str	r3, [r7, #24]
        GPIOx->OTYPER = temp;
 8001afa:	687b      	ldr	r3, [r7, #4]
 8001afc:	69ba      	ldr	r2, [r7, #24]
 8001afe:	605a      	str	r2, [r3, #4]
       }

      if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
 8001b00:	683b      	ldr	r3, [r7, #0]
 8001b02:	685b      	ldr	r3, [r3, #4]
 8001b04:	f003 0303 	and.w	r3, r3, #3
 8001b08:	2b03      	cmp	r3, #3
 8001b0a:	d017      	beq.n	8001b3c <HAL_GPIO_Init+0xf0>
      {
        /* Check the parameters */
        assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
        
        /* Activate the Pull-up or Pull down resistor for the current IO */
        temp = GPIOx->PUPDR;
 8001b0c:	687b      	ldr	r3, [r7, #4]
 8001b0e:	68db      	ldr	r3, [r3, #12]
 8001b10:	61bb      	str	r3, [r7, #24]
        temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
 8001b12:	69fb      	ldr	r3, [r7, #28]
 8001b14:	005b      	lsls	r3, r3, #1
 8001b16:	2203      	movs	r2, #3
 8001b18:	fa02 f303 	lsl.w	r3, r2, r3
 8001b1c:	43db      	mvns	r3, r3
 8001b1e:	69ba      	ldr	r2, [r7, #24]
 8001b20:	4013      	ands	r3, r2
 8001b22:	61bb      	str	r3, [r7, #24]
        temp |= ((GPIO_Init->Pull) << (position * 2U));
 8001b24:	683b      	ldr	r3, [r7, #0]
 8001b26:	689a      	ldr	r2, [r3, #8]
 8001b28:	69fb      	ldr	r3, [r7, #28]
 8001b2a:	005b      	lsls	r3, r3, #1
 8001b2c:	fa02 f303 	lsl.w	r3, r2, r3
 8001b30:	69ba      	ldr	r2, [r7, #24]
 8001b32:	4313      	orrs	r3, r2
 8001b34:	61bb      	str	r3, [r7, #24]
        GPIOx->PUPDR = temp;
 8001b36:	687b      	ldr	r3, [r7, #4]
 8001b38:	69ba      	ldr	r2, [r7, #24]
 8001b3a:	60da      	str	r2, [r3, #12]
      }

      /* In case of Alternate function mode selection */
      if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
 8001b3c:	683b      	ldr	r3, [r7, #0]
 8001b3e:	685b      	ldr	r3, [r3, #4]
 8001b40:	f003 0303 	and.w	r3, r3, #3
 8001b44:	2b02      	cmp	r3, #2
 8001b46:	d123      	bne.n	8001b90 <HAL_GPIO_Init+0x144>
      {
        /* Check the Alternate function parameter */
        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
        /* Configure Alternate function mapped with the current IO */
        temp = GPIOx->AFR[position >> 3U];
 8001b48:	69fb      	ldr	r3, [r7, #28]
 8001b4a:	08da      	lsrs	r2, r3, #3
 8001b4c:	687b      	ldr	r3, [r7, #4]
 8001b4e:	3208      	adds	r2, #8
 8001b50:	f853 3022 	ldr.w	r3, [r3, r2, lsl #2]
 8001b54:	61bb      	str	r3, [r7, #24]
        temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
 8001b56:	69fb      	ldr	r3, [r7, #28]
 8001b58:	f003 0307 	and.w	r3, r3, #7
 8001b5c:	009b      	lsls	r3, r3, #2
 8001b5e:	220f      	movs	r2, #15
 8001b60:	fa02 f303 	lsl.w	r3, r2, r3
 8001b64:	43db      	mvns	r3, r3
 8001b66:	69ba      	ldr	r2, [r7, #24]
 8001b68:	4013      	ands	r3, r2
 8001b6a:	61bb      	str	r3, [r7, #24]
        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
 8001b6c:	683b      	ldr	r3, [r7, #0]
 8001b6e:	691a      	ldr	r2, [r3, #16]
 8001b70:	69fb      	ldr	r3, [r7, #28]
 8001b72:	f003 0307 	and.w	r3, r3, #7
 8001b76:	009b      	lsls	r3, r3, #2
 8001b78:	fa02 f303 	lsl.w	r3, r2, r3
 8001b7c:	69ba      	ldr	r2, [r7, #24]
 8001b7e:	4313      	orrs	r3, r2
 8001b80:	61bb      	str	r3, [r7, #24]
        GPIOx->AFR[position >> 3U] = temp;
 8001b82:	69fb      	ldr	r3, [r7, #28]
 8001b84:	08da      	lsrs	r2, r3, #3
 8001b86:	687b      	ldr	r3, [r7, #4]
 8001b88:	3208      	adds	r2, #8
 8001b8a:	69b9      	ldr	r1, [r7, #24]
 8001b8c:	f843 1022 	str.w	r1, [r3, r2, lsl #2]
      }

      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
      temp = GPIOx->MODER;
 8001b90:	687b      	ldr	r3, [r7, #4]
 8001b92:	681b      	ldr	r3, [r3, #0]
 8001b94:	61bb      	str	r3, [r7, #24]
      temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
 8001b96:	69fb      	ldr	r3, [r7, #28]
 8001b98:	005b      	lsls	r3, r3, #1
 8001b9a:	2203      	movs	r2, #3
 8001b9c:	fa02 f303 	lsl.w	r3, r2, r3
 8001ba0:	43db      	mvns	r3, r3
 8001ba2:	69ba      	ldr	r2, [r7, #24]
 8001ba4:	4013      	ands	r3, r2
 8001ba6:	61bb      	str	r3, [r7, #24]
      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
 8001ba8:	683b      	ldr	r3, [r7, #0]
 8001baa:	685b      	ldr	r3, [r3, #4]
 8001bac:	f003 0203 	and.w	r2, r3, #3
 8001bb0:	69fb      	ldr	r3, [r7, #28]
 8001bb2:	005b      	lsls	r3, r3, #1
 8001bb4:	fa02 f303 	lsl.w	r3, r2, r3
 8001bb8:	69ba      	ldr	r2, [r7, #24]
 8001bba:	4313      	orrs	r3, r2
 8001bbc:	61bb      	str	r3, [r7, #24]
      GPIOx->MODER = temp;
 8001bbe:	687b      	ldr	r3, [r7, #4]
 8001bc0:	69ba      	ldr	r2, [r7, #24]
 8001bc2:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
 8001bc4:	683b      	ldr	r3, [r7, #0]
 8001bc6:	685b      	ldr	r3, [r3, #4]
 8001bc8:	f403 3340 	and.w	r3, r3, #196608	; 0x30000
 8001bcc:	2b00      	cmp	r3, #0
 8001bce:	f000 80a2 	beq.w	8001d16 <HAL_GPIO_Init+0x2ca>
      {
        /* Enable SYSCFG Clock */
        __HAL_RCC_SYSCFG_CLK_ENABLE();
 8001bd2:	2300      	movs	r3, #0
 8001bd4:	60fb      	str	r3, [r7, #12]
 8001bd6:	4b57      	ldr	r3, [pc, #348]	; (8001d34 <HAL_GPIO_Init+0x2e8>)
 8001bd8:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8001bda:	4a56      	ldr	r2, [pc, #344]	; (8001d34 <HAL_GPIO_Init+0x2e8>)
 8001bdc:	f443 4380 	orr.w	r3, r3, #16384	; 0x4000
 8001be0:	6453      	str	r3, [r2, #68]	; 0x44
 8001be2:	4b54      	ldr	r3, [pc, #336]	; (8001d34 <HAL_GPIO_Init+0x2e8>)
 8001be4:	6c5b      	ldr	r3, [r3, #68]	; 0x44
 8001be6:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 8001bea:	60fb      	str	r3, [r7, #12]
 8001bec:	68fb      	ldr	r3, [r7, #12]

        temp = SYSCFG->EXTICR[position >> 2U];
 8001bee:	4a52      	ldr	r2, [pc, #328]	; (8001d38 <HAL_GPIO_Init+0x2ec>)
 8001bf0:	69fb      	ldr	r3, [r7, #28]
 8001bf2:	089b      	lsrs	r3, r3, #2
 8001bf4:	3302      	adds	r3, #2
 8001bf6:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8001bfa:	61bb      	str	r3, [r7, #24]
        temp &= ~(0x0FU << (4U * (position & 0x03U)));
 8001bfc:	69fb      	ldr	r3, [r7, #28]
 8001bfe:	f003 0303 	and.w	r3, r3, #3
 8001c02:	009b      	lsls	r3, r3, #2
 8001c04:	220f      	movs	r2, #15
 8001c06:	fa02 f303 	lsl.w	r3, r2, r3
 8001c0a:	43db      	mvns	r3, r3
 8001c0c:	69ba      	ldr	r2, [r7, #24]
 8001c0e:	4013      	ands	r3, r2
 8001c10:	61bb      	str	r3, [r7, #24]
        temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
 8001c12:	687b      	ldr	r3, [r7, #4]
 8001c14:	4a49      	ldr	r2, [pc, #292]	; (8001d3c <HAL_GPIO_Init+0x2f0>)
 8001c16:	4293      	cmp	r3, r2
 8001c18:	d019      	beq.n	8001c4e <HAL_GPIO_Init+0x202>
 8001c1a:	687b      	ldr	r3, [r7, #4]
 8001c1c:	4a48      	ldr	r2, [pc, #288]	; (8001d40 <HAL_GPIO_Init+0x2f4>)
 8001c1e:	4293      	cmp	r3, r2
 8001c20:	d013      	beq.n	8001c4a <HAL_GPIO_Init+0x1fe>
 8001c22:	687b      	ldr	r3, [r7, #4]
 8001c24:	4a47      	ldr	r2, [pc, #284]	; (8001d44 <HAL_GPIO_Init+0x2f8>)
 8001c26:	4293      	cmp	r3, r2
 8001c28:	d00d      	beq.n	8001c46 <HAL_GPIO_Init+0x1fa>
 8001c2a:	687b      	ldr	r3, [r7, #4]
 8001c2c:	4a46      	ldr	r2, [pc, #280]	; (8001d48 <HAL_GPIO_Init+0x2fc>)
 8001c2e:	4293      	cmp	r3, r2
 8001c30:	d007      	beq.n	8001c42 <HAL_GPIO_Init+0x1f6>
 8001c32:	687b      	ldr	r3, [r7, #4]
 8001c34:	4a45      	ldr	r2, [pc, #276]	; (8001d4c <HAL_GPIO_Init+0x300>)
 8001c36:	4293      	cmp	r3, r2
 8001c38:	d101      	bne.n	8001c3e <HAL_GPIO_Init+0x1f2>
 8001c3a:	2304      	movs	r3, #4
 8001c3c:	e008      	b.n	8001c50 <HAL_GPIO_Init+0x204>
 8001c3e:	2307      	movs	r3, #7
 8001c40:	e006      	b.n	8001c50 <HAL_GPIO_Init+0x204>
 8001c42:	2303      	movs	r3, #3
 8001c44:	e004      	b.n	8001c50 <HAL_GPIO_Init+0x204>
 8001c46:	2302      	movs	r3, #2
 8001c48:	e002      	b.n	8001c50 <HAL_GPIO_Init+0x204>
 8001c4a:	2301      	movs	r3, #1
 8001c4c:	e000      	b.n	8001c50 <HAL_GPIO_Init+0x204>
 8001c4e:	2300      	movs	r3, #0
 8001c50:	69fa      	ldr	r2, [r7, #28]
 8001c52:	f002 0203 	and.w	r2, r2, #3
 8001c56:	0092      	lsls	r2, r2, #2
 8001c58:	4093      	lsls	r3, r2
 8001c5a:	69ba      	ldr	r2, [r7, #24]
 8001c5c:	4313      	orrs	r3, r2
 8001c5e:	61bb      	str	r3, [r7, #24]
        SYSCFG->EXTICR[position >> 2U] = temp;
 8001c60:	4935      	ldr	r1, [pc, #212]	; (8001d38 <HAL_GPIO_Init+0x2ec>)
 8001c62:	69fb      	ldr	r3, [r7, #28]
 8001c64:	089b      	lsrs	r3, r3, #2
 8001c66:	3302      	adds	r3, #2
 8001c68:	69ba      	ldr	r2, [r7, #24]
 8001c6a:	f841 2023 	str.w	r2, [r1, r3, lsl #2]

        /* Clear Rising Falling edge configuration */
        temp = EXTI->RTSR;
 8001c6e:	4b38      	ldr	r3, [pc, #224]	; (8001d50 <HAL_GPIO_Init+0x304>)
 8001c70:	689b      	ldr	r3, [r3, #8]
 8001c72:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8001c74:	693b      	ldr	r3, [r7, #16]
 8001c76:	43db      	mvns	r3, r3
 8001c78:	69ba      	ldr	r2, [r7, #24]
 8001c7a:	4013      	ands	r3, r2
 8001c7c:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
 8001c7e:	683b      	ldr	r3, [r7, #0]
 8001c80:	685b      	ldr	r3, [r3, #4]
 8001c82:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
 8001c86:	2b00      	cmp	r3, #0
 8001c88:	d003      	beq.n	8001c92 <HAL_GPIO_Init+0x246>
        {
          temp |= iocurrent;
 8001c8a:	69ba      	ldr	r2, [r7, #24]
 8001c8c:	693b      	ldr	r3, [r7, #16]
 8001c8e:	4313      	orrs	r3, r2
 8001c90:	61bb      	str	r3, [r7, #24]
        }
        EXTI->RTSR = temp;
 8001c92:	4a2f      	ldr	r2, [pc, #188]	; (8001d50 <HAL_GPIO_Init+0x304>)
 8001c94:	69bb      	ldr	r3, [r7, #24]
 8001c96:	6093      	str	r3, [r2, #8]

        temp = EXTI->FTSR;
 8001c98:	4b2d      	ldr	r3, [pc, #180]	; (8001d50 <HAL_GPIO_Init+0x304>)
 8001c9a:	68db      	ldr	r3, [r3, #12]
 8001c9c:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8001c9e:	693b      	ldr	r3, [r7, #16]
 8001ca0:	43db      	mvns	r3, r3
 8001ca2:	69ba      	ldr	r2, [r7, #24]
 8001ca4:	4013      	ands	r3, r2
 8001ca6:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
 8001ca8:	683b      	ldr	r3, [r7, #0]
 8001caa:	685b      	ldr	r3, [r3, #4]
 8001cac:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 8001cb0:	2b00      	cmp	r3, #0
 8001cb2:	d003      	beq.n	8001cbc <HAL_GPIO_Init+0x270>
        {
          temp |= iocurrent;
 8001cb4:	69ba      	ldr	r2, [r7, #24]
 8001cb6:	693b      	ldr	r3, [r7, #16]
 8001cb8:	4313      	orrs	r3, r2
 8001cba:	61bb      	str	r3, [r7, #24]
        }
        EXTI->FTSR = temp;
 8001cbc:	4a24      	ldr	r2, [pc, #144]	; (8001d50 <HAL_GPIO_Init+0x304>)
 8001cbe:	69bb      	ldr	r3, [r7, #24]
 8001cc0:	60d3      	str	r3, [r2, #12]

        temp = EXTI->EMR;
 8001cc2:	4b23      	ldr	r3, [pc, #140]	; (8001d50 <HAL_GPIO_Init+0x304>)
 8001cc4:	685b      	ldr	r3, [r3, #4]
 8001cc6:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8001cc8:	693b      	ldr	r3, [r7, #16]
 8001cca:	43db      	mvns	r3, r3
 8001ccc:	69ba      	ldr	r2, [r7, #24]
 8001cce:	4013      	ands	r3, r2
 8001cd0:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
 8001cd2:	683b      	ldr	r3, [r7, #0]
 8001cd4:	685b      	ldr	r3, [r3, #4]
 8001cd6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001cda:	2b00      	cmp	r3, #0
 8001cdc:	d003      	beq.n	8001ce6 <HAL_GPIO_Init+0x29a>
        {
          temp |= iocurrent;
 8001cde:	69ba      	ldr	r2, [r7, #24]
 8001ce0:	693b      	ldr	r3, [r7, #16]
 8001ce2:	4313      	orrs	r3, r2
 8001ce4:	61bb      	str	r3, [r7, #24]
        }
        EXTI->EMR = temp;
 8001ce6:	4a1a      	ldr	r2, [pc, #104]	; (8001d50 <HAL_GPIO_Init+0x304>)
 8001ce8:	69bb      	ldr	r3, [r7, #24]
 8001cea:	6053      	str	r3, [r2, #4]

        /* Clear EXTI line configuration */
        temp = EXTI->IMR;
 8001cec:	4b18      	ldr	r3, [pc, #96]	; (8001d50 <HAL_GPIO_Init+0x304>)
 8001cee:	681b      	ldr	r3, [r3, #0]
 8001cf0:	61bb      	str	r3, [r7, #24]
        temp &= ~((uint32_t)iocurrent);
 8001cf2:	693b      	ldr	r3, [r7, #16]
 8001cf4:	43db      	mvns	r3, r3
 8001cf6:	69ba      	ldr	r2, [r7, #24]
 8001cf8:	4013      	ands	r3, r2
 8001cfa:	61bb      	str	r3, [r7, #24]
        if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
 8001cfc:	683b      	ldr	r3, [r7, #0]
 8001cfe:	685b      	ldr	r3, [r3, #4]
 8001d00:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8001d04:	2b00      	cmp	r3, #0
 8001d06:	d003      	beq.n	8001d10 <HAL_GPIO_Init+0x2c4>
        {
          temp |= iocurrent;
 8001d08:	69ba      	ldr	r2, [r7, #24]
 8001d0a:	693b      	ldr	r3, [r7, #16]
 8001d0c:	4313      	orrs	r3, r2
 8001d0e:	61bb      	str	r3, [r7, #24]
        }
        EXTI->IMR = temp;
 8001d10:	4a0f      	ldr	r2, [pc, #60]	; (8001d50 <HAL_GPIO_Init+0x304>)
 8001d12:	69bb      	ldr	r3, [r7, #24]
 8001d14:	6013      	str	r3, [r2, #0]
  for(position = 0U; position < GPIO_NUMBER; position++)
 8001d16:	69fb      	ldr	r3, [r7, #28]
 8001d18:	3301      	adds	r3, #1
 8001d1a:	61fb      	str	r3, [r7, #28]
 8001d1c:	69fb      	ldr	r3, [r7, #28]
 8001d1e:	2b0f      	cmp	r3, #15
 8001d20:	f67f aea2 	bls.w	8001a68 <HAL_GPIO_Init+0x1c>
      }
    }
  }
}
 8001d24:	bf00      	nop
 8001d26:	bf00      	nop
 8001d28:	3724      	adds	r7, #36	; 0x24
 8001d2a:	46bd      	mov	sp, r7
 8001d2c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001d30:	4770      	bx	lr
 8001d32:	bf00      	nop
 8001d34:	40023800 	.word	0x40023800
 8001d38:	40013800 	.word	0x40013800
 8001d3c:	40020000 	.word	0x40020000
 8001d40:	40020400 	.word	0x40020400
 8001d44:	40020800 	.word	0x40020800
 8001d48:	40020c00 	.word	0x40020c00
 8001d4c:	40021000 	.word	0x40021000
 8001d50:	40013c00 	.word	0x40013c00

08001d54 <HAL_GPIO_ReadPin>:
  * @param  GPIO_Pin specifies the port bit to read.
  *         This parameter can be GPIO_PIN_x where x can be (0..15).
  * @retval The input port pin value.
  */
GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
 8001d54:	b480      	push	{r7}
 8001d56:	b085      	sub	sp, #20
 8001d58:	af00      	add	r7, sp, #0
 8001d5a:	6078      	str	r0, [r7, #4]
 8001d5c:	460b      	mov	r3, r1
 8001d5e:	807b      	strh	r3, [r7, #2]
  GPIO_PinState bitstatus;

  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));

  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
 8001d60:	687b      	ldr	r3, [r7, #4]
 8001d62:	691a      	ldr	r2, [r3, #16]
 8001d64:	887b      	ldrh	r3, [r7, #2]
 8001d66:	4013      	ands	r3, r2
 8001d68:	2b00      	cmp	r3, #0
 8001d6a:	d002      	beq.n	8001d72 <HAL_GPIO_ReadPin+0x1e>
  {
    bitstatus = GPIO_PIN_SET;
 8001d6c:	2301      	movs	r3, #1
 8001d6e:	73fb      	strb	r3, [r7, #15]
 8001d70:	e001      	b.n	8001d76 <HAL_GPIO_ReadPin+0x22>
  }
  else
  {
    bitstatus = GPIO_PIN_RESET;
 8001d72:	2300      	movs	r3, #0
 8001d74:	73fb      	strb	r3, [r7, #15]
  }
  return bitstatus;
 8001d76:	7bfb      	ldrb	r3, [r7, #15]
}
 8001d78:	4618      	mov	r0, r3
 8001d7a:	3714      	adds	r7, #20
 8001d7c:	46bd      	mov	sp, r7
 8001d7e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001d82:	4770      	bx	lr

08001d84 <HAL_GPIO_WritePin>:
  *            @arg GPIO_PIN_RESET: to clear the port pin
  *            @arg GPIO_PIN_SET: to set the port pin
  * @retval None
  */
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
 8001d84:	b480      	push	{r7}
 8001d86:	b083      	sub	sp, #12
 8001d88:	af00      	add	r7, sp, #0
 8001d8a:	6078      	str	r0, [r7, #4]
 8001d8c:	460b      	mov	r3, r1
 8001d8e:	807b      	strh	r3, [r7, #2]
 8001d90:	4613      	mov	r3, r2
 8001d92:	707b      	strb	r3, [r7, #1]
  /* Check the parameters */
  assert_param(IS_GPIO_PIN(GPIO_Pin));
  assert_param(IS_GPIO_PIN_ACTION(PinState));

  if(PinState != GPIO_PIN_RESET)
 8001d94:	787b      	ldrb	r3, [r7, #1]
 8001d96:	2b00      	cmp	r3, #0
 8001d98:	d003      	beq.n	8001da2 <HAL_GPIO_WritePin+0x1e>
  {
    GPIOx->BSRR = GPIO_Pin;
 8001d9a:	887a      	ldrh	r2, [r7, #2]
 8001d9c:	687b      	ldr	r3, [r7, #4]
 8001d9e:	619a      	str	r2, [r3, #24]
  }
  else
  {
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
  }
}
 8001da0:	e003      	b.n	8001daa <HAL_GPIO_WritePin+0x26>
    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
 8001da2:	887b      	ldrh	r3, [r7, #2]
 8001da4:	041a      	lsls	r2, r3, #16
 8001da6:	687b      	ldr	r3, [r7, #4]
 8001da8:	619a      	str	r2, [r3, #24]
}
 8001daa:	bf00      	nop
 8001dac:	370c      	adds	r7, #12
 8001dae:	46bd      	mov	sp, r7
 8001db0:	f85d 7b04 	ldr.w	r7, [sp], #4
 8001db4:	4770      	bx	lr
	...

08001db8 <HAL_RCC_OscConfig>:
  *         supported by this API. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8001db8:	b580      	push	{r7, lr}
 8001dba:	b086      	sub	sp, #24
 8001dbc:	af00      	add	r7, sp, #0
 8001dbe:	6078      	str	r0, [r7, #4]
  uint32_t tickstart, pll_config;

  /* Check Null pointer */
  if(RCC_OscInitStruct == NULL)
 8001dc0:	687b      	ldr	r3, [r7, #4]
 8001dc2:	2b00      	cmp	r3, #0
 8001dc4:	d101      	bne.n	8001dca <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 8001dc6:	2301      	movs	r3, #1
 8001dc8:	e267      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
  }

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
  /*------------------------------- HSE Configuration ------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8001dca:	687b      	ldr	r3, [r7, #4]
 8001dcc:	681b      	ldr	r3, [r3, #0]
 8001dce:	f003 0301 	and.w	r3, r3, #1
 8001dd2:	2b00      	cmp	r3, #0
 8001dd4:	d075      	beq.n	8001ec2 <HAL_RCC_OscConfig+0x10a>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
    /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
 8001dd6:	4b88      	ldr	r3, [pc, #544]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001dd8:	689b      	ldr	r3, [r3, #8]
 8001dda:	f003 030c 	and.w	r3, r3, #12
 8001dde:	2b04      	cmp	r3, #4
 8001de0:	d00c      	beq.n	8001dfc <HAL_RCC_OscConfig+0x44>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 8001de2:	4b85      	ldr	r3, [pc, #532]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001de4:	689b      	ldr	r3, [r3, #8]
 8001de6:	f003 030c 	and.w	r3, r3, #12
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
 8001dea:	2b08      	cmp	r3, #8
 8001dec:	d112      	bne.n	8001e14 <HAL_RCC_OscConfig+0x5c>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
 8001dee:	4b82      	ldr	r3, [pc, #520]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001df0:	685b      	ldr	r3, [r3, #4]
 8001df2:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 8001df6:	f5b3 0f80 	cmp.w	r3, #4194304	; 0x400000
 8001dfa:	d10b      	bne.n	8001e14 <HAL_RCC_OscConfig+0x5c>
    {
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8001dfc:	4b7e      	ldr	r3, [pc, #504]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001dfe:	681b      	ldr	r3, [r3, #0]
 8001e00:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001e04:	2b00      	cmp	r3, #0
 8001e06:	d05b      	beq.n	8001ec0 <HAL_RCC_OscConfig+0x108>
 8001e08:	687b      	ldr	r3, [r7, #4]
 8001e0a:	685b      	ldr	r3, [r3, #4]
 8001e0c:	2b00      	cmp	r3, #0
 8001e0e:	d157      	bne.n	8001ec0 <HAL_RCC_OscConfig+0x108>
      {
        return HAL_ERROR;
 8001e10:	2301      	movs	r3, #1
 8001e12:	e242      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8001e14:	687b      	ldr	r3, [r7, #4]
 8001e16:	685b      	ldr	r3, [r3, #4]
 8001e18:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8001e1c:	d106      	bne.n	8001e2c <HAL_RCC_OscConfig+0x74>
 8001e1e:	4b76      	ldr	r3, [pc, #472]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e20:	681b      	ldr	r3, [r3, #0]
 8001e22:	4a75      	ldr	r2, [pc, #468]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e24:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8001e28:	6013      	str	r3, [r2, #0]
 8001e2a:	e01d      	b.n	8001e68 <HAL_RCC_OscConfig+0xb0>
 8001e2c:	687b      	ldr	r3, [r7, #4]
 8001e2e:	685b      	ldr	r3, [r3, #4]
 8001e30:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8001e34:	d10c      	bne.n	8001e50 <HAL_RCC_OscConfig+0x98>
 8001e36:	4b70      	ldr	r3, [pc, #448]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e38:	681b      	ldr	r3, [r3, #0]
 8001e3a:	4a6f      	ldr	r2, [pc, #444]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e3c:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8001e40:	6013      	str	r3, [r2, #0]
 8001e42:	4b6d      	ldr	r3, [pc, #436]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e44:	681b      	ldr	r3, [r3, #0]
 8001e46:	4a6c      	ldr	r2, [pc, #432]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e48:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8001e4c:	6013      	str	r3, [r2, #0]
 8001e4e:	e00b      	b.n	8001e68 <HAL_RCC_OscConfig+0xb0>
 8001e50:	4b69      	ldr	r3, [pc, #420]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e52:	681b      	ldr	r3, [r3, #0]
 8001e54:	4a68      	ldr	r2, [pc, #416]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e56:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8001e5a:	6013      	str	r3, [r2, #0]
 8001e5c:	4b66      	ldr	r3, [pc, #408]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e5e:	681b      	ldr	r3, [r3, #0]
 8001e60:	4a65      	ldr	r2, [pc, #404]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e62:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8001e66:	6013      	str	r3, [r2, #0]

      /* Check the HSE State */
      if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
 8001e68:	687b      	ldr	r3, [r7, #4]
 8001e6a:	685b      	ldr	r3, [r3, #4]
 8001e6c:	2b00      	cmp	r3, #0
 8001e6e:	d013      	beq.n	8001e98 <HAL_RCC_OscConfig+0xe0>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001e70:	f7ff f892 	bl	8000f98 <HAL_GetTick>
 8001e74:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8001e76:	e008      	b.n	8001e8a <HAL_RCC_OscConfig+0xd2>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8001e78:	f7ff f88e 	bl	8000f98 <HAL_GetTick>
 8001e7c:	4602      	mov	r2, r0
 8001e7e:	693b      	ldr	r3, [r7, #16]
 8001e80:	1ad3      	subs	r3, r2, r3
 8001e82:	2b64      	cmp	r3, #100	; 0x64
 8001e84:	d901      	bls.n	8001e8a <HAL_RCC_OscConfig+0xd2>
          {
            return HAL_TIMEOUT;
 8001e86:	2303      	movs	r3, #3
 8001e88:	e207      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8001e8a:	4b5b      	ldr	r3, [pc, #364]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001e8c:	681b      	ldr	r3, [r3, #0]
 8001e8e:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001e92:	2b00      	cmp	r3, #0
 8001e94:	d0f0      	beq.n	8001e78 <HAL_RCC_OscConfig+0xc0>
 8001e96:	e014      	b.n	8001ec2 <HAL_RCC_OscConfig+0x10a>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8001e98:	f7ff f87e 	bl	8000f98 <HAL_GetTick>
 8001e9c:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is bypassed or disabled */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8001e9e:	e008      	b.n	8001eb2 <HAL_RCC_OscConfig+0xfa>
        {
          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
 8001ea0:	f7ff f87a 	bl	8000f98 <HAL_GetTick>
 8001ea4:	4602      	mov	r2, r0
 8001ea6:	693b      	ldr	r3, [r7, #16]
 8001ea8:	1ad3      	subs	r3, r2, r3
 8001eaa:	2b64      	cmp	r3, #100	; 0x64
 8001eac:	d901      	bls.n	8001eb2 <HAL_RCC_OscConfig+0xfa>
          {
            return HAL_TIMEOUT;
 8001eae:	2303      	movs	r3, #3
 8001eb0:	e1f3      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8001eb2:	4b51      	ldr	r3, [pc, #324]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001eb4:	681b      	ldr	r3, [r3, #0]
 8001eb6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001eba:	2b00      	cmp	r3, #0
 8001ebc:	d1f0      	bne.n	8001ea0 <HAL_RCC_OscConfig+0xe8>
 8001ebe:	e000      	b.n	8001ec2 <HAL_RCC_OscConfig+0x10a>
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8001ec0:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8001ec2:	687b      	ldr	r3, [r7, #4]
 8001ec4:	681b      	ldr	r3, [r3, #0]
 8001ec6:	f003 0302 	and.w	r3, r3, #2
 8001eca:	2b00      	cmp	r3, #0
 8001ecc:	d063      	beq.n	8001f96 <HAL_RCC_OscConfig+0x1de>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
 8001ece:	4b4a      	ldr	r3, [pc, #296]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001ed0:	689b      	ldr	r3, [r3, #8]
 8001ed2:	f003 030c 	and.w	r3, r3, #12
 8001ed6:	2b00      	cmp	r3, #0
 8001ed8:	d00b      	beq.n	8001ef2 <HAL_RCC_OscConfig+0x13a>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 8001eda:	4b47      	ldr	r3, [pc, #284]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001edc:	689b      	ldr	r3, [r3, #8]
 8001ede:	f003 030c 	and.w	r3, r3, #12
    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
 8001ee2:	2b08      	cmp	r3, #8
 8001ee4:	d11c      	bne.n	8001f20 <HAL_RCC_OscConfig+0x168>
      ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
 8001ee6:	4b44      	ldr	r3, [pc, #272]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001ee8:	685b      	ldr	r3, [r3, #4]
 8001eea:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 8001eee:	2b00      	cmp	r3, #0
 8001ef0:	d116      	bne.n	8001f20 <HAL_RCC_OscConfig+0x168>
    {
      /* When HSI is used as system clock it will not disabled */
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8001ef2:	4b41      	ldr	r3, [pc, #260]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001ef4:	681b      	ldr	r3, [r3, #0]
 8001ef6:	f003 0302 	and.w	r3, r3, #2
 8001efa:	2b00      	cmp	r3, #0
 8001efc:	d005      	beq.n	8001f0a <HAL_RCC_OscConfig+0x152>
 8001efe:	687b      	ldr	r3, [r7, #4]
 8001f00:	68db      	ldr	r3, [r3, #12]
 8001f02:	2b01      	cmp	r3, #1
 8001f04:	d001      	beq.n	8001f0a <HAL_RCC_OscConfig+0x152>
      {
        return HAL_ERROR;
 8001f06:	2301      	movs	r3, #1
 8001f08:	e1c7      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8001f0a:	4b3b      	ldr	r3, [pc, #236]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001f0c:	681b      	ldr	r3, [r3, #0]
 8001f0e:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 8001f12:	687b      	ldr	r3, [r7, #4]
 8001f14:	691b      	ldr	r3, [r3, #16]
 8001f16:	00db      	lsls	r3, r3, #3
 8001f18:	4937      	ldr	r1, [pc, #220]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001f1a:	4313      	orrs	r3, r2
 8001f1c:	600b      	str	r3, [r1, #0]
      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8001f1e:	e03a      	b.n	8001f96 <HAL_RCC_OscConfig+0x1de>
      }
    }
    else
    {
      /* Check the HSI State */
      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
 8001f20:	687b      	ldr	r3, [r7, #4]
 8001f22:	68db      	ldr	r3, [r3, #12]
 8001f24:	2b00      	cmp	r3, #0
 8001f26:	d020      	beq.n	8001f6a <HAL_RCC_OscConfig+0x1b2>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 8001f28:	4b34      	ldr	r3, [pc, #208]	; (8001ffc <HAL_RCC_OscConfig+0x244>)
 8001f2a:	2201      	movs	r2, #1
 8001f2c:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001f2e:	f7ff f833 	bl	8000f98 <HAL_GetTick>
 8001f32:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8001f34:	e008      	b.n	8001f48 <HAL_RCC_OscConfig+0x190>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8001f36:	f7ff f82f 	bl	8000f98 <HAL_GetTick>
 8001f3a:	4602      	mov	r2, r0
 8001f3c:	693b      	ldr	r3, [r7, #16]
 8001f3e:	1ad3      	subs	r3, r2, r3
 8001f40:	2b02      	cmp	r3, #2
 8001f42:	d901      	bls.n	8001f48 <HAL_RCC_OscConfig+0x190>
          {
            return HAL_TIMEOUT;
 8001f44:	2303      	movs	r3, #3
 8001f46:	e1a8      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8001f48:	4b2b      	ldr	r3, [pc, #172]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001f4a:	681b      	ldr	r3, [r3, #0]
 8001f4c:	f003 0302 	and.w	r3, r3, #2
 8001f50:	2b00      	cmp	r3, #0
 8001f52:	d0f0      	beq.n	8001f36 <HAL_RCC_OscConfig+0x17e>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 8001f54:	4b28      	ldr	r3, [pc, #160]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001f56:	681b      	ldr	r3, [r3, #0]
 8001f58:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 8001f5c:	687b      	ldr	r3, [r7, #4]
 8001f5e:	691b      	ldr	r3, [r3, #16]
 8001f60:	00db      	lsls	r3, r3, #3
 8001f62:	4925      	ldr	r1, [pc, #148]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001f64:	4313      	orrs	r3, r2
 8001f66:	600b      	str	r3, [r1, #0]
 8001f68:	e015      	b.n	8001f96 <HAL_RCC_OscConfig+0x1de>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 8001f6a:	4b24      	ldr	r3, [pc, #144]	; (8001ffc <HAL_RCC_OscConfig+0x244>)
 8001f6c:	2200      	movs	r2, #0
 8001f6e:	601a      	str	r2, [r3, #0]

        /* Get Start Tick*/
        tickstart = HAL_GetTick();
 8001f70:	f7ff f812 	bl	8000f98 <HAL_GetTick>
 8001f74:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8001f76:	e008      	b.n	8001f8a <HAL_RCC_OscConfig+0x1d2>
        {
          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
 8001f78:	f7ff f80e 	bl	8000f98 <HAL_GetTick>
 8001f7c:	4602      	mov	r2, r0
 8001f7e:	693b      	ldr	r3, [r7, #16]
 8001f80:	1ad3      	subs	r3, r2, r3
 8001f82:	2b02      	cmp	r3, #2
 8001f84:	d901      	bls.n	8001f8a <HAL_RCC_OscConfig+0x1d2>
          {
            return HAL_TIMEOUT;
 8001f86:	2303      	movs	r3, #3
 8001f88:	e187      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 8001f8a:	4b1b      	ldr	r3, [pc, #108]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001f8c:	681b      	ldr	r3, [r3, #0]
 8001f8e:	f003 0302 	and.w	r3, r3, #2
 8001f92:	2b00      	cmp	r3, #0
 8001f94:	d1f0      	bne.n	8001f78 <HAL_RCC_OscConfig+0x1c0>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 8001f96:	687b      	ldr	r3, [r7, #4]
 8001f98:	681b      	ldr	r3, [r3, #0]
 8001f9a:	f003 0308 	and.w	r3, r3, #8
 8001f9e:	2b00      	cmp	r3, #0
 8001fa0:	d036      	beq.n	8002010 <HAL_RCC_OscConfig+0x258>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
 8001fa2:	687b      	ldr	r3, [r7, #4]
 8001fa4:	695b      	ldr	r3, [r3, #20]
 8001fa6:	2b00      	cmp	r3, #0
 8001fa8:	d016      	beq.n	8001fd8 <HAL_RCC_OscConfig+0x220>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 8001faa:	4b15      	ldr	r3, [pc, #84]	; (8002000 <HAL_RCC_OscConfig+0x248>)
 8001fac:	2201      	movs	r2, #1
 8001fae:	601a      	str	r2, [r3, #0]

      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 8001fb0:	f7fe fff2 	bl	8000f98 <HAL_GetTick>
 8001fb4:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8001fb6:	e008      	b.n	8001fca <HAL_RCC_OscConfig+0x212>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8001fb8:	f7fe ffee 	bl	8000f98 <HAL_GetTick>
 8001fbc:	4602      	mov	r2, r0
 8001fbe:	693b      	ldr	r3, [r7, #16]
 8001fc0:	1ad3      	subs	r3, r2, r3
 8001fc2:	2b02      	cmp	r3, #2
 8001fc4:	d901      	bls.n	8001fca <HAL_RCC_OscConfig+0x212>
        {
          return HAL_TIMEOUT;
 8001fc6:	2303      	movs	r3, #3
 8001fc8:	e167      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 8001fca:	4b0b      	ldr	r3, [pc, #44]	; (8001ff8 <HAL_RCC_OscConfig+0x240>)
 8001fcc:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 8001fce:	f003 0302 	and.w	r3, r3, #2
 8001fd2:	2b00      	cmp	r3, #0
 8001fd4:	d0f0      	beq.n	8001fb8 <HAL_RCC_OscConfig+0x200>
 8001fd6:	e01b      	b.n	8002010 <HAL_RCC_OscConfig+0x258>
      }
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8001fd8:	4b09      	ldr	r3, [pc, #36]	; (8002000 <HAL_RCC_OscConfig+0x248>)
 8001fda:	2200      	movs	r2, #0
 8001fdc:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8001fde:	f7fe ffdb 	bl	8000f98 <HAL_GetTick>
 8001fe2:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8001fe4:	e00e      	b.n	8002004 <HAL_RCC_OscConfig+0x24c>
      {
        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
 8001fe6:	f7fe ffd7 	bl	8000f98 <HAL_GetTick>
 8001fea:	4602      	mov	r2, r0
 8001fec:	693b      	ldr	r3, [r7, #16]
 8001fee:	1ad3      	subs	r3, r2, r3
 8001ff0:	2b02      	cmp	r3, #2
 8001ff2:	d907      	bls.n	8002004 <HAL_RCC_OscConfig+0x24c>
        {
          return HAL_TIMEOUT;
 8001ff4:	2303      	movs	r3, #3
 8001ff6:	e150      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
 8001ff8:	40023800 	.word	0x40023800
 8001ffc:	42470000 	.word	0x42470000
 8002000:	42470e80 	.word	0x42470e80
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 8002004:	4b88      	ldr	r3, [pc, #544]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002006:	6f5b      	ldr	r3, [r3, #116]	; 0x74
 8002008:	f003 0302 	and.w	r3, r3, #2
 800200c:	2b00      	cmp	r3, #0
 800200e:	d1ea      	bne.n	8001fe6 <HAL_RCC_OscConfig+0x22e>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 8002010:	687b      	ldr	r3, [r7, #4]
 8002012:	681b      	ldr	r3, [r3, #0]
 8002014:	f003 0304 	and.w	r3, r3, #4
 8002018:	2b00      	cmp	r3, #0
 800201a:	f000 8097 	beq.w	800214c <HAL_RCC_OscConfig+0x394>
  {
    FlagStatus       pwrclkchanged = RESET;
 800201e:	2300      	movs	r3, #0
 8002020:	75fb      	strb	r3, [r7, #23]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if(__HAL_RCC_PWR_IS_CLK_DISABLED())
 8002022:	4b81      	ldr	r3, [pc, #516]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002024:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002026:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 800202a:	2b00      	cmp	r3, #0
 800202c:	d10f      	bne.n	800204e <HAL_RCC_OscConfig+0x296>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 800202e:	2300      	movs	r3, #0
 8002030:	60bb      	str	r3, [r7, #8]
 8002032:	4b7d      	ldr	r3, [pc, #500]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002034:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002036:	4a7c      	ldr	r2, [pc, #496]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002038:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 800203c:	6413      	str	r3, [r2, #64]	; 0x40
 800203e:	4b7a      	ldr	r3, [pc, #488]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002040:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002042:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8002046:	60bb      	str	r3, [r7, #8]
 8002048:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 800204a:	2301      	movs	r3, #1
 800204c:	75fb      	strb	r3, [r7, #23]
    }

    if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 800204e:	4b77      	ldr	r3, [pc, #476]	; (800222c <HAL_RCC_OscConfig+0x474>)
 8002050:	681b      	ldr	r3, [r3, #0]
 8002052:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8002056:	2b00      	cmp	r3, #0
 8002058:	d118      	bne.n	800208c <HAL_RCC_OscConfig+0x2d4>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 800205a:	4b74      	ldr	r3, [pc, #464]	; (800222c <HAL_RCC_OscConfig+0x474>)
 800205c:	681b      	ldr	r3, [r3, #0]
 800205e:	4a73      	ldr	r2, [pc, #460]	; (800222c <HAL_RCC_OscConfig+0x474>)
 8002060:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 8002064:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 8002066:	f7fe ff97 	bl	8000f98 <HAL_GetTick>
 800206a:	6138      	str	r0, [r7, #16]

      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 800206c:	e008      	b.n	8002080 <HAL_RCC_OscConfig+0x2c8>
      {
        if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 800206e:	f7fe ff93 	bl	8000f98 <HAL_GetTick>
 8002072:	4602      	mov	r2, r0
 8002074:	693b      	ldr	r3, [r7, #16]
 8002076:	1ad3      	subs	r3, r2, r3
 8002078:	2b02      	cmp	r3, #2
 800207a:	d901      	bls.n	8002080 <HAL_RCC_OscConfig+0x2c8>
        {
          return HAL_TIMEOUT;
 800207c:	2303      	movs	r3, #3
 800207e:	e10c      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
      while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8002080:	4b6a      	ldr	r3, [pc, #424]	; (800222c <HAL_RCC_OscConfig+0x474>)
 8002082:	681b      	ldr	r3, [r3, #0]
 8002084:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8002088:	2b00      	cmp	r3, #0
 800208a:	d0f0      	beq.n	800206e <HAL_RCC_OscConfig+0x2b6>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 800208c:	687b      	ldr	r3, [r7, #4]
 800208e:	689b      	ldr	r3, [r3, #8]
 8002090:	2b01      	cmp	r3, #1
 8002092:	d106      	bne.n	80020a2 <HAL_RCC_OscConfig+0x2ea>
 8002094:	4b64      	ldr	r3, [pc, #400]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002096:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002098:	4a63      	ldr	r2, [pc, #396]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 800209a:	f043 0301 	orr.w	r3, r3, #1
 800209e:	6713      	str	r3, [r2, #112]	; 0x70
 80020a0:	e01c      	b.n	80020dc <HAL_RCC_OscConfig+0x324>
 80020a2:	687b      	ldr	r3, [r7, #4]
 80020a4:	689b      	ldr	r3, [r3, #8]
 80020a6:	2b05      	cmp	r3, #5
 80020a8:	d10c      	bne.n	80020c4 <HAL_RCC_OscConfig+0x30c>
 80020aa:	4b5f      	ldr	r3, [pc, #380]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80020ac:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80020ae:	4a5e      	ldr	r2, [pc, #376]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80020b0:	f043 0304 	orr.w	r3, r3, #4
 80020b4:	6713      	str	r3, [r2, #112]	; 0x70
 80020b6:	4b5c      	ldr	r3, [pc, #368]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80020b8:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80020ba:	4a5b      	ldr	r2, [pc, #364]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80020bc:	f043 0301 	orr.w	r3, r3, #1
 80020c0:	6713      	str	r3, [r2, #112]	; 0x70
 80020c2:	e00b      	b.n	80020dc <HAL_RCC_OscConfig+0x324>
 80020c4:	4b58      	ldr	r3, [pc, #352]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80020c6:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80020c8:	4a57      	ldr	r2, [pc, #348]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80020ca:	f023 0301 	bic.w	r3, r3, #1
 80020ce:	6713      	str	r3, [r2, #112]	; 0x70
 80020d0:	4b55      	ldr	r3, [pc, #340]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80020d2:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 80020d4:	4a54      	ldr	r2, [pc, #336]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80020d6:	f023 0304 	bic.w	r3, r3, #4
 80020da:	6713      	str	r3, [r2, #112]	; 0x70
    /* Check the LSE State */
    if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
 80020dc:	687b      	ldr	r3, [r7, #4]
 80020de:	689b      	ldr	r3, [r3, #8]
 80020e0:	2b00      	cmp	r3, #0
 80020e2:	d015      	beq.n	8002110 <HAL_RCC_OscConfig+0x358>
    {
      /* Get Start Tick*/
      tickstart = HAL_GetTick();
 80020e4:	f7fe ff58 	bl	8000f98 <HAL_GetTick>
 80020e8:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 80020ea:	e00a      	b.n	8002102 <HAL_RCC_OscConfig+0x34a>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 80020ec:	f7fe ff54 	bl	8000f98 <HAL_GetTick>
 80020f0:	4602      	mov	r2, r0
 80020f2:	693b      	ldr	r3, [r7, #16]
 80020f4:	1ad3      	subs	r3, r2, r3
 80020f6:	f241 3288 	movw	r2, #5000	; 0x1388
 80020fa:	4293      	cmp	r3, r2
 80020fc:	d901      	bls.n	8002102 <HAL_RCC_OscConfig+0x34a>
        {
          return HAL_TIMEOUT;
 80020fe:	2303      	movs	r3, #3
 8002100:	e0cb      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 8002102:	4b49      	ldr	r3, [pc, #292]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002104:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002106:	f003 0302 	and.w	r3, r3, #2
 800210a:	2b00      	cmp	r3, #0
 800210c:	d0ee      	beq.n	80020ec <HAL_RCC_OscConfig+0x334>
 800210e:	e014      	b.n	800213a <HAL_RCC_OscConfig+0x382>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8002110:	f7fe ff42 	bl	8000f98 <HAL_GetTick>
 8002114:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 8002116:	e00a      	b.n	800212e <HAL_RCC_OscConfig+0x376>
      {
        if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
 8002118:	f7fe ff3e 	bl	8000f98 <HAL_GetTick>
 800211c:	4602      	mov	r2, r0
 800211e:	693b      	ldr	r3, [r7, #16]
 8002120:	1ad3      	subs	r3, r2, r3
 8002122:	f241 3288 	movw	r2, #5000	; 0x1388
 8002126:	4293      	cmp	r3, r2
 8002128:	d901      	bls.n	800212e <HAL_RCC_OscConfig+0x376>
        {
          return HAL_TIMEOUT;
 800212a:	2303      	movs	r3, #3
 800212c:	e0b5      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 800212e:	4b3e      	ldr	r3, [pc, #248]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002130:	6f1b      	ldr	r3, [r3, #112]	; 0x70
 8002132:	f003 0302 	and.w	r3, r3, #2
 8002136:	2b00      	cmp	r3, #0
 8002138:	d1ee      	bne.n	8002118 <HAL_RCC_OscConfig+0x360>
        }
      }
    }

    /* Restore clock configuration if changed */
    if(pwrclkchanged == SET)
 800213a:	7dfb      	ldrb	r3, [r7, #23]
 800213c:	2b01      	cmp	r3, #1
 800213e:	d105      	bne.n	800214c <HAL_RCC_OscConfig+0x394>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 8002140:	4b39      	ldr	r3, [pc, #228]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002142:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8002144:	4a38      	ldr	r2, [pc, #224]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002146:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 800214a:	6413      	str	r3, [r2, #64]	; 0x40
    }
  }
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 800214c:	687b      	ldr	r3, [r7, #4]
 800214e:	699b      	ldr	r3, [r3, #24]
 8002150:	2b00      	cmp	r3, #0
 8002152:	f000 80a1 	beq.w	8002298 <HAL_RCC_OscConfig+0x4e0>
  {
    /* Check if the PLL is used as system clock or not */
    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
 8002156:	4b34      	ldr	r3, [pc, #208]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002158:	689b      	ldr	r3, [r3, #8]
 800215a:	f003 030c 	and.w	r3, r3, #12
 800215e:	2b08      	cmp	r3, #8
 8002160:	d05c      	beq.n	800221c <HAL_RCC_OscConfig+0x464>
    {
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 8002162:	687b      	ldr	r3, [r7, #4]
 8002164:	699b      	ldr	r3, [r3, #24]
 8002166:	2b02      	cmp	r3, #2
 8002168:	d141      	bne.n	80021ee <HAL_RCC_OscConfig+0x436>
        assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
        assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
        assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 800216a:	4b31      	ldr	r3, [pc, #196]	; (8002230 <HAL_RCC_OscConfig+0x478>)
 800216c:	2200      	movs	r2, #0
 800216e:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8002170:	f7fe ff12 	bl	8000f98 <HAL_GetTick>
 8002174:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 8002176:	e008      	b.n	800218a <HAL_RCC_OscConfig+0x3d2>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 8002178:	f7fe ff0e 	bl	8000f98 <HAL_GetTick>
 800217c:	4602      	mov	r2, r0
 800217e:	693b      	ldr	r3, [r7, #16]
 8002180:	1ad3      	subs	r3, r2, r3
 8002182:	2b02      	cmp	r3, #2
 8002184:	d901      	bls.n	800218a <HAL_RCC_OscConfig+0x3d2>
          {
            return HAL_TIMEOUT;
 8002186:	2303      	movs	r3, #3
 8002188:	e087      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 800218a:	4b27      	ldr	r3, [pc, #156]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 800218c:	681b      	ldr	r3, [r3, #0]
 800218e:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8002192:	2b00      	cmp	r3, #0
 8002194:	d1f0      	bne.n	8002178 <HAL_RCC_OscConfig+0x3c0>
          }
        }

        /* Configure the main PLL clock source, multiplication and division factors. */
        WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource                                            | \
 8002196:	687b      	ldr	r3, [r7, #4]
 8002198:	69da      	ldr	r2, [r3, #28]
 800219a:	687b      	ldr	r3, [r7, #4]
 800219c:	6a1b      	ldr	r3, [r3, #32]
 800219e:	431a      	orrs	r2, r3
 80021a0:	687b      	ldr	r3, [r7, #4]
 80021a2:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80021a4:	019b      	lsls	r3, r3, #6
 80021a6:	431a      	orrs	r2, r3
 80021a8:	687b      	ldr	r3, [r7, #4]
 80021aa:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 80021ac:	085b      	lsrs	r3, r3, #1
 80021ae:	3b01      	subs	r3, #1
 80021b0:	041b      	lsls	r3, r3, #16
 80021b2:	431a      	orrs	r2, r3
 80021b4:	687b      	ldr	r3, [r7, #4]
 80021b6:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80021b8:	061b      	lsls	r3, r3, #24
 80021ba:	491b      	ldr	r1, [pc, #108]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80021bc:	4313      	orrs	r3, r2
 80021be:	604b      	str	r3, [r1, #4]
                                 RCC_OscInitStruct->PLL.PLLM                                                 | \
                                 (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)             | \
                                 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
                                 (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 80021c0:	4b1b      	ldr	r3, [pc, #108]	; (8002230 <HAL_RCC_OscConfig+0x478>)
 80021c2:	2201      	movs	r2, #1
 80021c4:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80021c6:	f7fe fee7 	bl	8000f98 <HAL_GetTick>
 80021ca:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 80021cc:	e008      	b.n	80021e0 <HAL_RCC_OscConfig+0x428>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 80021ce:	f7fe fee3 	bl	8000f98 <HAL_GetTick>
 80021d2:	4602      	mov	r2, r0
 80021d4:	693b      	ldr	r3, [r7, #16]
 80021d6:	1ad3      	subs	r3, r2, r3
 80021d8:	2b02      	cmp	r3, #2
 80021da:	d901      	bls.n	80021e0 <HAL_RCC_OscConfig+0x428>
          {
            return HAL_TIMEOUT;
 80021dc:	2303      	movs	r3, #3
 80021de:	e05c      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 80021e0:	4b11      	ldr	r3, [pc, #68]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 80021e2:	681b      	ldr	r3, [r3, #0]
 80021e4:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 80021e8:	2b00      	cmp	r3, #0
 80021ea:	d0f0      	beq.n	80021ce <HAL_RCC_OscConfig+0x416>
 80021ec:	e054      	b.n	8002298 <HAL_RCC_OscConfig+0x4e0>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 80021ee:	4b10      	ldr	r3, [pc, #64]	; (8002230 <HAL_RCC_OscConfig+0x478>)
 80021f0:	2200      	movs	r2, #0
 80021f2:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80021f4:	f7fe fed0 	bl	8000f98 <HAL_GetTick>
 80021f8:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 80021fa:	e008      	b.n	800220e <HAL_RCC_OscConfig+0x456>
        {
          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
 80021fc:	f7fe fecc 	bl	8000f98 <HAL_GetTick>
 8002200:	4602      	mov	r2, r0
 8002202:	693b      	ldr	r3, [r7, #16]
 8002204:	1ad3      	subs	r3, r2, r3
 8002206:	2b02      	cmp	r3, #2
 8002208:	d901      	bls.n	800220e <HAL_RCC_OscConfig+0x456>
          {
            return HAL_TIMEOUT;
 800220a:	2303      	movs	r3, #3
 800220c:	e045      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
 800220e:	4b06      	ldr	r3, [pc, #24]	; (8002228 <HAL_RCC_OscConfig+0x470>)
 8002210:	681b      	ldr	r3, [r3, #0]
 8002212:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8002216:	2b00      	cmp	r3, #0
 8002218:	d1f0      	bne.n	80021fc <HAL_RCC_OscConfig+0x444>
 800221a:	e03d      	b.n	8002298 <HAL_RCC_OscConfig+0x4e0>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 800221c:	687b      	ldr	r3, [r7, #4]
 800221e:	699b      	ldr	r3, [r3, #24]
 8002220:	2b01      	cmp	r3, #1
 8002222:	d107      	bne.n	8002234 <HAL_RCC_OscConfig+0x47c>
      {
        return HAL_ERROR;
 8002224:	2301      	movs	r3, #1
 8002226:	e038      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
 8002228:	40023800 	.word	0x40023800
 800222c:	40007000 	.word	0x40007000
 8002230:	42470060 	.word	0x42470060
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->PLLCFGR;
 8002234:	4b1b      	ldr	r3, [pc, #108]	; (80022a4 <HAL_RCC_OscConfig+0x4ec>)
 8002236:	685b      	ldr	r3, [r3, #4]
 8002238:	60fb      	str	r3, [r7, #12]
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
#else
        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 800223a:	687b      	ldr	r3, [r7, #4]
 800223c:	699b      	ldr	r3, [r3, #24]
 800223e:	2b01      	cmp	r3, #1
 8002240:	d028      	beq.n	8002294 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8002242:	68fb      	ldr	r3, [r7, #12]
 8002244:	f403 0280 	and.w	r2, r3, #4194304	; 0x400000
 8002248:	687b      	ldr	r3, [r7, #4]
 800224a:	69db      	ldr	r3, [r3, #28]
        if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
 800224c:	429a      	cmp	r2, r3
 800224e:	d121      	bne.n	8002294 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
 8002250:	68fb      	ldr	r3, [r7, #12]
 8002252:	f003 023f 	and.w	r2, r3, #63	; 0x3f
 8002256:	687b      	ldr	r3, [r7, #4]
 8002258:	6a1b      	ldr	r3, [r3, #32]
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 800225a:	429a      	cmp	r2, r3
 800225c:	d11a      	bne.n	8002294 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
 800225e:	68fa      	ldr	r2, [r7, #12]
 8002260:	f647 73c0 	movw	r3, #32704	; 0x7fc0
 8002264:	4013      	ands	r3, r2
 8002266:	687a      	ldr	r2, [r7, #4]
 8002268:	6a52      	ldr	r2, [r2, #36]	; 0x24
 800226a:	0192      	lsls	r2, r2, #6
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
 800226c:	4293      	cmp	r3, r2
 800226e:	d111      	bne.n	8002294 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
 8002270:	68fb      	ldr	r3, [r7, #12]
 8002272:	f403 3240 	and.w	r2, r3, #196608	; 0x30000
 8002276:	687b      	ldr	r3, [r7, #4]
 8002278:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 800227a:	085b      	lsrs	r3, r3, #1
 800227c:	3b01      	subs	r3, #1
 800227e:	041b      	lsls	r3, r3, #16
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
 8002280:	429a      	cmp	r2, r3
 8002282:	d107      	bne.n	8002294 <HAL_RCC_OscConfig+0x4dc>
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
 8002284:	68fb      	ldr	r3, [r7, #12]
 8002286:	f003 6270 	and.w	r2, r3, #251658240	; 0xf000000
 800228a:	687b      	ldr	r3, [r7, #4]
 800228c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 800228e:	061b      	lsls	r3, r3, #24
            (READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
 8002290:	429a      	cmp	r2, r3
 8002292:	d001      	beq.n	8002298 <HAL_RCC_OscConfig+0x4e0>
#endif
        {
          return HAL_ERROR;
 8002294:	2301      	movs	r3, #1
 8002296:	e000      	b.n	800229a <HAL_RCC_OscConfig+0x4e2>
        }
      }
    }
  }
  return HAL_OK;
 8002298:	2300      	movs	r3, #0
}
 800229a:	4618      	mov	r0, r3
 800229c:	3718      	adds	r7, #24
 800229e:	46bd      	mov	sp, r7
 80022a0:	bd80      	pop	{r7, pc}
 80022a2:	bf00      	nop
 80022a4:	40023800 	.word	0x40023800

080022a8 <HAL_RCC_ClockConfig>:
  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
  *         (for more details refer to section above "Initialization/de-initialization functions")
  * @retval None
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 80022a8:	b580      	push	{r7, lr}
 80022aa:	b084      	sub	sp, #16
 80022ac:	af00      	add	r7, sp, #0
 80022ae:	6078      	str	r0, [r7, #4]
 80022b0:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;

  /* Check Null pointer */
  if(RCC_ClkInitStruct == NULL)
 80022b2:	687b      	ldr	r3, [r7, #4]
 80022b4:	2b00      	cmp	r3, #0
 80022b6:	d101      	bne.n	80022bc <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 80022b8:	2301      	movs	r3, #1
 80022ba:	e0cc      	b.n	8002456 <HAL_RCC_ClockConfig+0x1ae>
  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
    must be correctly programmed according to the frequency of the CPU clock
    (HCLK) and the supply voltage of the device. */

  /* Increasing the number of wait states because of higher CPU frequency */
  if(FLatency > __HAL_FLASH_GET_LATENCY())
 80022bc:	4b68      	ldr	r3, [pc, #416]	; (8002460 <HAL_RCC_ClockConfig+0x1b8>)
 80022be:	681b      	ldr	r3, [r3, #0]
 80022c0:	f003 0307 	and.w	r3, r3, #7
 80022c4:	683a      	ldr	r2, [r7, #0]
 80022c6:	429a      	cmp	r2, r3
 80022c8:	d90c      	bls.n	80022e4 <HAL_RCC_ClockConfig+0x3c>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 80022ca:	4b65      	ldr	r3, [pc, #404]	; (8002460 <HAL_RCC_ClockConfig+0x1b8>)
 80022cc:	683a      	ldr	r2, [r7, #0]
 80022ce:	b2d2      	uxtb	r2, r2
 80022d0:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 80022d2:	4b63      	ldr	r3, [pc, #396]	; (8002460 <HAL_RCC_ClockConfig+0x1b8>)
 80022d4:	681b      	ldr	r3, [r3, #0]
 80022d6:	f003 0307 	and.w	r3, r3, #7
 80022da:	683a      	ldr	r2, [r7, #0]
 80022dc:	429a      	cmp	r2, r3
 80022de:	d001      	beq.n	80022e4 <HAL_RCC_ClockConfig+0x3c>
    {
      return HAL_ERROR;
 80022e0:	2301      	movs	r3, #1
 80022e2:	e0b8      	b.n	8002456 <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- HCLK Configuration --------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 80022e4:	687b      	ldr	r3, [r7, #4]
 80022e6:	681b      	ldr	r3, [r3, #0]
 80022e8:	f003 0302 	and.w	r3, r3, #2
 80022ec:	2b00      	cmp	r3, #0
 80022ee:	d020      	beq.n	8002332 <HAL_RCC_ClockConfig+0x8a>
  {
    /* Set the highest APBx dividers in order to ensure that we do not go through
       a non-spec phase whatever we decrease or increase HCLK. */
    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80022f0:	687b      	ldr	r3, [r7, #4]
 80022f2:	681b      	ldr	r3, [r3, #0]
 80022f4:	f003 0304 	and.w	r3, r3, #4
 80022f8:	2b00      	cmp	r3, #0
 80022fa:	d005      	beq.n	8002308 <HAL_RCC_ClockConfig+0x60>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 80022fc:	4b59      	ldr	r3, [pc, #356]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 80022fe:	689b      	ldr	r3, [r3, #8]
 8002300:	4a58      	ldr	r2, [pc, #352]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 8002302:	f443 53e0 	orr.w	r3, r3, #7168	; 0x1c00
 8002306:	6093      	str	r3, [r2, #8]
    }

    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 8002308:	687b      	ldr	r3, [r7, #4]
 800230a:	681b      	ldr	r3, [r3, #0]
 800230c:	f003 0308 	and.w	r3, r3, #8
 8002310:	2b00      	cmp	r3, #0
 8002312:	d005      	beq.n	8002320 <HAL_RCC_ClockConfig+0x78>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 8002314:	4b53      	ldr	r3, [pc, #332]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 8002316:	689b      	ldr	r3, [r3, #8]
 8002318:	4a52      	ldr	r2, [pc, #328]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 800231a:	f443 4360 	orr.w	r3, r3, #57344	; 0xe000
 800231e:	6093      	str	r3, [r2, #8]
    }

    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 8002320:	4b50      	ldr	r3, [pc, #320]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 8002322:	689b      	ldr	r3, [r3, #8]
 8002324:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 8002328:	687b      	ldr	r3, [r7, #4]
 800232a:	689b      	ldr	r3, [r3, #8]
 800232c:	494d      	ldr	r1, [pc, #308]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 800232e:	4313      	orrs	r3, r2
 8002330:	608b      	str	r3, [r1, #8]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 8002332:	687b      	ldr	r3, [r7, #4]
 8002334:	681b      	ldr	r3, [r3, #0]
 8002336:	f003 0301 	and.w	r3, r3, #1
 800233a:	2b00      	cmp	r3, #0
 800233c:	d044      	beq.n	80023c8 <HAL_RCC_ClockConfig+0x120>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 800233e:	687b      	ldr	r3, [r7, #4]
 8002340:	685b      	ldr	r3, [r3, #4]
 8002342:	2b01      	cmp	r3, #1
 8002344:	d107      	bne.n	8002356 <HAL_RCC_ClockConfig+0xae>
    {
      /* Check the HSE ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 8002346:	4b47      	ldr	r3, [pc, #284]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 8002348:	681b      	ldr	r3, [r3, #0]
 800234a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800234e:	2b00      	cmp	r3, #0
 8002350:	d119      	bne.n	8002386 <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8002352:	2301      	movs	r3, #1
 8002354:	e07f      	b.n	8002456 <HAL_RCC_ClockConfig+0x1ae>
      }
    }
    /* PLL is selected as System Clock Source */
    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 8002356:	687b      	ldr	r3, [r7, #4]
 8002358:	685b      	ldr	r3, [r3, #4]
 800235a:	2b02      	cmp	r3, #2
 800235c:	d003      	beq.n	8002366 <HAL_RCC_ClockConfig+0xbe>
            (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
 800235e:	687b      	ldr	r3, [r7, #4]
 8002360:	685b      	ldr	r3, [r3, #4]
    else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)   ||
 8002362:	2b03      	cmp	r3, #3
 8002364:	d107      	bne.n	8002376 <HAL_RCC_ClockConfig+0xce>
    {
      /* Check the PLL ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 8002366:	4b3f      	ldr	r3, [pc, #252]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 8002368:	681b      	ldr	r3, [r3, #0]
 800236a:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 800236e:	2b00      	cmp	r3, #0
 8002370:	d109      	bne.n	8002386 <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8002372:	2301      	movs	r3, #1
 8002374:	e06f      	b.n	8002456 <HAL_RCC_ClockConfig+0x1ae>
    }
    /* HSI is selected as System Clock Source */
    else
    {
      /* Check the HSI ready flag */
      if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 8002376:	4b3b      	ldr	r3, [pc, #236]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 8002378:	681b      	ldr	r3, [r3, #0]
 800237a:	f003 0302 	and.w	r3, r3, #2
 800237e:	2b00      	cmp	r3, #0
 8002380:	d101      	bne.n	8002386 <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8002382:	2301      	movs	r3, #1
 8002384:	e067      	b.n	8002456 <HAL_RCC_ClockConfig+0x1ae>
      }
    }

    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 8002386:	4b37      	ldr	r3, [pc, #220]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 8002388:	689b      	ldr	r3, [r3, #8]
 800238a:	f023 0203 	bic.w	r2, r3, #3
 800238e:	687b      	ldr	r3, [r7, #4]
 8002390:	685b      	ldr	r3, [r3, #4]
 8002392:	4934      	ldr	r1, [pc, #208]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 8002394:	4313      	orrs	r3, r2
 8002396:	608b      	str	r3, [r1, #8]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 8002398:	f7fe fdfe 	bl	8000f98 <HAL_GetTick>
 800239c:	60f8      	str	r0, [r7, #12]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 800239e:	e00a      	b.n	80023b6 <HAL_RCC_ClockConfig+0x10e>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 80023a0:	f7fe fdfa 	bl	8000f98 <HAL_GetTick>
 80023a4:	4602      	mov	r2, r0
 80023a6:	68fb      	ldr	r3, [r7, #12]
 80023a8:	1ad3      	subs	r3, r2, r3
 80023aa:	f241 3288 	movw	r2, #5000	; 0x1388
 80023ae:	4293      	cmp	r3, r2
 80023b0:	d901      	bls.n	80023b6 <HAL_RCC_ClockConfig+0x10e>
      {
        return HAL_TIMEOUT;
 80023b2:	2303      	movs	r3, #3
 80023b4:	e04f      	b.n	8002456 <HAL_RCC_ClockConfig+0x1ae>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 80023b6:	4b2b      	ldr	r3, [pc, #172]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 80023b8:	689b      	ldr	r3, [r3, #8]
 80023ba:	f003 020c 	and.w	r2, r3, #12
 80023be:	687b      	ldr	r3, [r7, #4]
 80023c0:	685b      	ldr	r3, [r3, #4]
 80023c2:	009b      	lsls	r3, r3, #2
 80023c4:	429a      	cmp	r2, r3
 80023c6:	d1eb      	bne.n	80023a0 <HAL_RCC_ClockConfig+0xf8>
      }
    }
  }

  /* Decreasing the number of wait states because of lower CPU frequency */
  if(FLatency < __HAL_FLASH_GET_LATENCY())
 80023c8:	4b25      	ldr	r3, [pc, #148]	; (8002460 <HAL_RCC_ClockConfig+0x1b8>)
 80023ca:	681b      	ldr	r3, [r3, #0]
 80023cc:	f003 0307 	and.w	r3, r3, #7
 80023d0:	683a      	ldr	r2, [r7, #0]
 80023d2:	429a      	cmp	r2, r3
 80023d4:	d20c      	bcs.n	80023f0 <HAL_RCC_ClockConfig+0x148>
  {
     /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 80023d6:	4b22      	ldr	r3, [pc, #136]	; (8002460 <HAL_RCC_ClockConfig+0x1b8>)
 80023d8:	683a      	ldr	r2, [r7, #0]
 80023da:	b2d2      	uxtb	r2, r2
 80023dc:	701a      	strb	r2, [r3, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if(__HAL_FLASH_GET_LATENCY() != FLatency)
 80023de:	4b20      	ldr	r3, [pc, #128]	; (8002460 <HAL_RCC_ClockConfig+0x1b8>)
 80023e0:	681b      	ldr	r3, [r3, #0]
 80023e2:	f003 0307 	and.w	r3, r3, #7
 80023e6:	683a      	ldr	r2, [r7, #0]
 80023e8:	429a      	cmp	r2, r3
 80023ea:	d001      	beq.n	80023f0 <HAL_RCC_ClockConfig+0x148>
    {
      return HAL_ERROR;
 80023ec:	2301      	movs	r3, #1
 80023ee:	e032      	b.n	8002456 <HAL_RCC_ClockConfig+0x1ae>
    }
  }

  /*-------------------------- PCLK1 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 80023f0:	687b      	ldr	r3, [r7, #4]
 80023f2:	681b      	ldr	r3, [r3, #0]
 80023f4:	f003 0304 	and.w	r3, r3, #4
 80023f8:	2b00      	cmp	r3, #0
 80023fa:	d008      	beq.n	800240e <HAL_RCC_ClockConfig+0x166>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 80023fc:	4b19      	ldr	r3, [pc, #100]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 80023fe:	689b      	ldr	r3, [r3, #8]
 8002400:	f423 52e0 	bic.w	r2, r3, #7168	; 0x1c00
 8002404:	687b      	ldr	r3, [r7, #4]
 8002406:	68db      	ldr	r3, [r3, #12]
 8002408:	4916      	ldr	r1, [pc, #88]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 800240a:	4313      	orrs	r3, r2
 800240c:	608b      	str	r3, [r1, #8]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 800240e:	687b      	ldr	r3, [r7, #4]
 8002410:	681b      	ldr	r3, [r3, #0]
 8002412:	f003 0308 	and.w	r3, r3, #8
 8002416:	2b00      	cmp	r3, #0
 8002418:	d009      	beq.n	800242e <HAL_RCC_ClockConfig+0x186>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
 800241a:	4b12      	ldr	r3, [pc, #72]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 800241c:	689b      	ldr	r3, [r3, #8]
 800241e:	f423 4260 	bic.w	r2, r3, #57344	; 0xe000
 8002422:	687b      	ldr	r3, [r7, #4]
 8002424:	691b      	ldr	r3, [r3, #16]
 8002426:	00db      	lsls	r3, r3, #3
 8002428:	490e      	ldr	r1, [pc, #56]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 800242a:	4313      	orrs	r3, r2
 800242c:	608b      	str	r3, [r1, #8]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
 800242e:	f000 f821 	bl	8002474 <HAL_RCC_GetSysClockFreq>
 8002432:	4602      	mov	r2, r0
 8002434:	4b0b      	ldr	r3, [pc, #44]	; (8002464 <HAL_RCC_ClockConfig+0x1bc>)
 8002436:	689b      	ldr	r3, [r3, #8]
 8002438:	091b      	lsrs	r3, r3, #4
 800243a:	f003 030f 	and.w	r3, r3, #15
 800243e:	490a      	ldr	r1, [pc, #40]	; (8002468 <HAL_RCC_ClockConfig+0x1c0>)
 8002440:	5ccb      	ldrb	r3, [r1, r3]
 8002442:	fa22 f303 	lsr.w	r3, r2, r3
 8002446:	4a09      	ldr	r2, [pc, #36]	; (800246c <HAL_RCC_ClockConfig+0x1c4>)
 8002448:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings */
  HAL_InitTick (uwTickPrio);
 800244a:	4b09      	ldr	r3, [pc, #36]	; (8002470 <HAL_RCC_ClockConfig+0x1c8>)
 800244c:	681b      	ldr	r3, [r3, #0]
 800244e:	4618      	mov	r0, r3
 8002450:	f7fe fc94 	bl	8000d7c <HAL_InitTick>

  return HAL_OK;
 8002454:	2300      	movs	r3, #0
}
 8002456:	4618      	mov	r0, r3
 8002458:	3710      	adds	r7, #16
 800245a:	46bd      	mov	sp, r7
 800245c:	bd80      	pop	{r7, pc}
 800245e:	bf00      	nop
 8002460:	40023c00 	.word	0x40023c00
 8002464:	40023800 	.word	0x40023800
 8002468:	08006354 	.word	0x08006354
 800246c:	20000000 	.word	0x20000000
 8002470:	20000004 	.word	0x20000004

08002474 <HAL_RCC_GetSysClockFreq>:
  *
  *
  * @retval SYSCLK frequency
  */
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8002474:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 8002478:	b094      	sub	sp, #80	; 0x50
 800247a:	af00      	add	r7, sp, #0
  uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
 800247c:	2300      	movs	r3, #0
 800247e:	647b      	str	r3, [r7, #68]	; 0x44
 8002480:	2300      	movs	r3, #0
 8002482:	64fb      	str	r3, [r7, #76]	; 0x4c
 8002484:	2300      	movs	r3, #0
 8002486:	643b      	str	r3, [r7, #64]	; 0x40
  uint32_t sysclockfreq = 0U;
 8002488:	2300      	movs	r3, #0
 800248a:	64bb      	str	r3, [r7, #72]	; 0x48

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (RCC->CFGR & RCC_CFGR_SWS)
 800248c:	4b79      	ldr	r3, [pc, #484]	; (8002674 <HAL_RCC_GetSysClockFreq+0x200>)
 800248e:	689b      	ldr	r3, [r3, #8]
 8002490:	f003 030c 	and.w	r3, r3, #12
 8002494:	2b08      	cmp	r3, #8
 8002496:	d00d      	beq.n	80024b4 <HAL_RCC_GetSysClockFreq+0x40>
 8002498:	2b08      	cmp	r3, #8
 800249a:	f200 80e1 	bhi.w	8002660 <HAL_RCC_GetSysClockFreq+0x1ec>
 800249e:	2b00      	cmp	r3, #0
 80024a0:	d002      	beq.n	80024a8 <HAL_RCC_GetSysClockFreq+0x34>
 80024a2:	2b04      	cmp	r3, #4
 80024a4:	d003      	beq.n	80024ae <HAL_RCC_GetSysClockFreq+0x3a>
 80024a6:	e0db      	b.n	8002660 <HAL_RCC_GetSysClockFreq+0x1ec>
  {
    case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
    {
      sysclockfreq = HSI_VALUE;
 80024a8:	4b73      	ldr	r3, [pc, #460]	; (8002678 <HAL_RCC_GetSysClockFreq+0x204>)
 80024aa:	64bb      	str	r3, [r7, #72]	; 0x48
       break;
 80024ac:	e0db      	b.n	8002666 <HAL_RCC_GetSysClockFreq+0x1f2>
    }
    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock  source */
    {
      sysclockfreq = HSE_VALUE;
 80024ae:	4b73      	ldr	r3, [pc, #460]	; (800267c <HAL_RCC_GetSysClockFreq+0x208>)
 80024b0:	64bb      	str	r3, [r7, #72]	; 0x48
      break;
 80024b2:	e0d8      	b.n	8002666 <HAL_RCC_GetSysClockFreq+0x1f2>
    }
    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock  source */
    {
      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
      SYSCLK = PLL_VCO / PLLP */
      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 80024b4:	4b6f      	ldr	r3, [pc, #444]	; (8002674 <HAL_RCC_GetSysClockFreq+0x200>)
 80024b6:	685b      	ldr	r3, [r3, #4]
 80024b8:	f003 033f 	and.w	r3, r3, #63	; 0x3f
 80024bc:	647b      	str	r3, [r7, #68]	; 0x44
      if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
 80024be:	4b6d      	ldr	r3, [pc, #436]	; (8002674 <HAL_RCC_GetSysClockFreq+0x200>)
 80024c0:	685b      	ldr	r3, [r3, #4]
 80024c2:	f403 0380 	and.w	r3, r3, #4194304	; 0x400000
 80024c6:	2b00      	cmp	r3, #0
 80024c8:	d063      	beq.n	8002592 <HAL_RCC_GetSysClockFreq+0x11e>
      {
        /* HSE used as PLL clock source */
        pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 80024ca:	4b6a      	ldr	r3, [pc, #424]	; (8002674 <HAL_RCC_GetSysClockFreq+0x200>)
 80024cc:	685b      	ldr	r3, [r3, #4]
 80024ce:	099b      	lsrs	r3, r3, #6
 80024d0:	2200      	movs	r2, #0
 80024d2:	63bb      	str	r3, [r7, #56]	; 0x38
 80024d4:	63fa      	str	r2, [r7, #60]	; 0x3c
 80024d6:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 80024d8:	f3c3 0308 	ubfx	r3, r3, #0, #9
 80024dc:	633b      	str	r3, [r7, #48]	; 0x30
 80024de:	2300      	movs	r3, #0
 80024e0:	637b      	str	r3, [r7, #52]	; 0x34
 80024e2:	e9d7 450c 	ldrd	r4, r5, [r7, #48]	; 0x30
 80024e6:	4622      	mov	r2, r4
 80024e8:	462b      	mov	r3, r5
 80024ea:	f04f 0000 	mov.w	r0, #0
 80024ee:	f04f 0100 	mov.w	r1, #0
 80024f2:	0159      	lsls	r1, r3, #5
 80024f4:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
 80024f8:	0150      	lsls	r0, r2, #5
 80024fa:	4602      	mov	r2, r0
 80024fc:	460b      	mov	r3, r1
 80024fe:	4621      	mov	r1, r4
 8002500:	1a51      	subs	r1, r2, r1
 8002502:	6139      	str	r1, [r7, #16]
 8002504:	4629      	mov	r1, r5
 8002506:	eb63 0301 	sbc.w	r3, r3, r1
 800250a:	617b      	str	r3, [r7, #20]
 800250c:	f04f 0200 	mov.w	r2, #0
 8002510:	f04f 0300 	mov.w	r3, #0
 8002514:	e9d7 ab04 	ldrd	sl, fp, [r7, #16]
 8002518:	4659      	mov	r1, fp
 800251a:	018b      	lsls	r3, r1, #6
 800251c:	4651      	mov	r1, sl
 800251e:	ea43 6391 	orr.w	r3, r3, r1, lsr #26
 8002522:	4651      	mov	r1, sl
 8002524:	018a      	lsls	r2, r1, #6
 8002526:	4651      	mov	r1, sl
 8002528:	ebb2 0801 	subs.w	r8, r2, r1
 800252c:	4659      	mov	r1, fp
 800252e:	eb63 0901 	sbc.w	r9, r3, r1
 8002532:	f04f 0200 	mov.w	r2, #0
 8002536:	f04f 0300 	mov.w	r3, #0
 800253a:	ea4f 03c9 	mov.w	r3, r9, lsl #3
 800253e:	ea43 7358 	orr.w	r3, r3, r8, lsr #29
 8002542:	ea4f 02c8 	mov.w	r2, r8, lsl #3
 8002546:	4690      	mov	r8, r2
 8002548:	4699      	mov	r9, r3
 800254a:	4623      	mov	r3, r4
 800254c:	eb18 0303 	adds.w	r3, r8, r3
 8002550:	60bb      	str	r3, [r7, #8]
 8002552:	462b      	mov	r3, r5
 8002554:	eb49 0303 	adc.w	r3, r9, r3
 8002558:	60fb      	str	r3, [r7, #12]
 800255a:	f04f 0200 	mov.w	r2, #0
 800255e:	f04f 0300 	mov.w	r3, #0
 8002562:	e9d7 4502 	ldrd	r4, r5, [r7, #8]
 8002566:	4629      	mov	r1, r5
 8002568:	024b      	lsls	r3, r1, #9
 800256a:	4621      	mov	r1, r4
 800256c:	ea43 53d1 	orr.w	r3, r3, r1, lsr #23
 8002570:	4621      	mov	r1, r4
 8002572:	024a      	lsls	r2, r1, #9
 8002574:	4610      	mov	r0, r2
 8002576:	4619      	mov	r1, r3
 8002578:	6c7b      	ldr	r3, [r7, #68]	; 0x44
 800257a:	2200      	movs	r2, #0
 800257c:	62bb      	str	r3, [r7, #40]	; 0x28
 800257e:	62fa      	str	r2, [r7, #44]	; 0x2c
 8002580:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	; 0x28
 8002584:	f7fd fe2c 	bl	80001e0 <__aeabi_uldivmod>
 8002588:	4602      	mov	r2, r0
 800258a:	460b      	mov	r3, r1
 800258c:	4613      	mov	r3, r2
 800258e:	64fb      	str	r3, [r7, #76]	; 0x4c
 8002590:	e058      	b.n	8002644 <HAL_RCC_GetSysClockFreq+0x1d0>
      }
      else
      {
        /* HSI used as PLL clock source */
        pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
 8002592:	4b38      	ldr	r3, [pc, #224]	; (8002674 <HAL_RCC_GetSysClockFreq+0x200>)
 8002594:	685b      	ldr	r3, [r3, #4]
 8002596:	099b      	lsrs	r3, r3, #6
 8002598:	2200      	movs	r2, #0
 800259a:	4618      	mov	r0, r3
 800259c:	4611      	mov	r1, r2
 800259e:	f3c0 0308 	ubfx	r3, r0, #0, #9
 80025a2:	623b      	str	r3, [r7, #32]
 80025a4:	2300      	movs	r3, #0
 80025a6:	627b      	str	r3, [r7, #36]	; 0x24
 80025a8:	e9d7 8908 	ldrd	r8, r9, [r7, #32]
 80025ac:	4642      	mov	r2, r8
 80025ae:	464b      	mov	r3, r9
 80025b0:	f04f 0000 	mov.w	r0, #0
 80025b4:	f04f 0100 	mov.w	r1, #0
 80025b8:	0159      	lsls	r1, r3, #5
 80025ba:	ea41 61d2 	orr.w	r1, r1, r2, lsr #27
 80025be:	0150      	lsls	r0, r2, #5
 80025c0:	4602      	mov	r2, r0
 80025c2:	460b      	mov	r3, r1
 80025c4:	4641      	mov	r1, r8
 80025c6:	ebb2 0a01 	subs.w	sl, r2, r1
 80025ca:	4649      	mov	r1, r9
 80025cc:	eb63 0b01 	sbc.w	fp, r3, r1
 80025d0:	f04f 0200 	mov.w	r2, #0
 80025d4:	f04f 0300 	mov.w	r3, #0
 80025d8:	ea4f 138b 	mov.w	r3, fp, lsl #6
 80025dc:	ea43 639a 	orr.w	r3, r3, sl, lsr #26
 80025e0:	ea4f 128a 	mov.w	r2, sl, lsl #6
 80025e4:	ebb2 040a 	subs.w	r4, r2, sl
 80025e8:	eb63 050b 	sbc.w	r5, r3, fp
 80025ec:	f04f 0200 	mov.w	r2, #0
 80025f0:	f04f 0300 	mov.w	r3, #0
 80025f4:	00eb      	lsls	r3, r5, #3
 80025f6:	ea43 7354 	orr.w	r3, r3, r4, lsr #29
 80025fa:	00e2      	lsls	r2, r4, #3
 80025fc:	4614      	mov	r4, r2
 80025fe:	461d      	mov	r5, r3
 8002600:	4643      	mov	r3, r8
 8002602:	18e3      	adds	r3, r4, r3
 8002604:	603b      	str	r3, [r7, #0]
 8002606:	464b      	mov	r3, r9
 8002608:	eb45 0303 	adc.w	r3, r5, r3
 800260c:	607b      	str	r3, [r7, #4]
 800260e:	f04f 0200 	mov.w	r2, #0
 8002612:	f04f 0300 	mov.w	r3, #0
 8002616:	e9d7 4500 	ldrd	r4, r5, [r7]
 800261a:	4629      	mov	r1, r5
 800261c:	028b      	lsls	r3, r1, #10
 800261e:	4621      	mov	r1, r4
 8002620:	ea43 5391 	orr.w	r3, r3, r1, lsr #22
 8002624:	4621      	mov	r1, r4
 8002626:	028a      	lsls	r2, r1, #10
 8002628:	4610      	mov	r0, r2
 800262a:	4619      	mov	r1, r3
 800262c:	6c7b      	ldr	r3, [r7, #68]	; 0x44
 800262e:	2200      	movs	r2, #0
 8002630:	61bb      	str	r3, [r7, #24]
 8002632:	61fa      	str	r2, [r7, #28]
 8002634:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
 8002638:	f7fd fdd2 	bl	80001e0 <__aeabi_uldivmod>
 800263c:	4602      	mov	r2, r0
 800263e:	460b      	mov	r3, r1
 8002640:	4613      	mov	r3, r2
 8002642:	64fb      	str	r3, [r7, #76]	; 0x4c
      }
      pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
 8002644:	4b0b      	ldr	r3, [pc, #44]	; (8002674 <HAL_RCC_GetSysClockFreq+0x200>)
 8002646:	685b      	ldr	r3, [r3, #4]
 8002648:	0c1b      	lsrs	r3, r3, #16
 800264a:	f003 0303 	and.w	r3, r3, #3
 800264e:	3301      	adds	r3, #1
 8002650:	005b      	lsls	r3, r3, #1
 8002652:	643b      	str	r3, [r7, #64]	; 0x40

      sysclockfreq = pllvco/pllp;
 8002654:	6cfa      	ldr	r2, [r7, #76]	; 0x4c
 8002656:	6c3b      	ldr	r3, [r7, #64]	; 0x40
 8002658:	fbb2 f3f3 	udiv	r3, r2, r3
 800265c:	64bb      	str	r3, [r7, #72]	; 0x48
      break;
 800265e:	e002      	b.n	8002666 <HAL_RCC_GetSysClockFreq+0x1f2>
    }
    default:
    {
      sysclockfreq = HSI_VALUE;
 8002660:	4b05      	ldr	r3, [pc, #20]	; (8002678 <HAL_RCC_GetSysClockFreq+0x204>)
 8002662:	64bb      	str	r3, [r7, #72]	; 0x48
      break;
 8002664:	bf00      	nop
    }
  }
  return sysclockfreq;
 8002666:	6cbb      	ldr	r3, [r7, #72]	; 0x48
}
 8002668:	4618      	mov	r0, r3
 800266a:	3750      	adds	r7, #80	; 0x50
 800266c:	46bd      	mov	sp, r7
 800266e:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 8002672:	bf00      	nop
 8002674:	40023800 	.word	0x40023800
 8002678:	00f42400 	.word	0x00f42400
 800267c:	007a1200 	.word	0x007a1200

08002680 <HAL_RCC_GetHCLKFreq>:
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 8002680:	b480      	push	{r7}
 8002682:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 8002684:	4b03      	ldr	r3, [pc, #12]	; (8002694 <HAL_RCC_GetHCLKFreq+0x14>)
 8002686:	681b      	ldr	r3, [r3, #0]
}
 8002688:	4618      	mov	r0, r3
 800268a:	46bd      	mov	sp, r7
 800268c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002690:	4770      	bx	lr
 8002692:	bf00      	nop
 8002694:	20000000 	.word	0x20000000

08002698 <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 8002698:	b580      	push	{r7, lr}
 800269a:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
 800269c:	f7ff fff0 	bl	8002680 <HAL_RCC_GetHCLKFreq>
 80026a0:	4602      	mov	r2, r0
 80026a2:	4b05      	ldr	r3, [pc, #20]	; (80026b8 <HAL_RCC_GetPCLK1Freq+0x20>)
 80026a4:	689b      	ldr	r3, [r3, #8]
 80026a6:	0a9b      	lsrs	r3, r3, #10
 80026a8:	f003 0307 	and.w	r3, r3, #7
 80026ac:	4903      	ldr	r1, [pc, #12]	; (80026bc <HAL_RCC_GetPCLK1Freq+0x24>)
 80026ae:	5ccb      	ldrb	r3, [r1, r3]
 80026b0:	fa22 f303 	lsr.w	r3, r2, r3
}
 80026b4:	4618      	mov	r0, r3
 80026b6:	bd80      	pop	{r7, pc}
 80026b8:	40023800 	.word	0x40023800
 80026bc:	08006364 	.word	0x08006364

080026c0 <HAL_RCC_GetPCLK2Freq>:
  * @note   Each time PCLK2 changes, this function must be called to update the
  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK2 frequency
  */
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
 80026c0:	b580      	push	{r7, lr}
 80026c2:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
 80026c4:	f7ff ffdc 	bl	8002680 <HAL_RCC_GetHCLKFreq>
 80026c8:	4602      	mov	r2, r0
 80026ca:	4b05      	ldr	r3, [pc, #20]	; (80026e0 <HAL_RCC_GetPCLK2Freq+0x20>)
 80026cc:	689b      	ldr	r3, [r3, #8]
 80026ce:	0b5b      	lsrs	r3, r3, #13
 80026d0:	f003 0307 	and.w	r3, r3, #7
 80026d4:	4903      	ldr	r1, [pc, #12]	; (80026e4 <HAL_RCC_GetPCLK2Freq+0x24>)
 80026d6:	5ccb      	ldrb	r3, [r1, r3]
 80026d8:	fa22 f303 	lsr.w	r3, r2, r3
}
 80026dc:	4618      	mov	r0, r3
 80026de:	bd80      	pop	{r7, pc}
 80026e0:	40023800 	.word	0x40023800
 80026e4:	08006364 	.word	0x08006364

080026e8 <HAL_RCC_GetClockConfig>:
  * will be configured.
  * @param  pFLatency Pointer on the Flash Latency.
  * @retval None
  */
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
{
 80026e8:	b480      	push	{r7}
 80026ea:	b083      	sub	sp, #12
 80026ec:	af00      	add	r7, sp, #0
 80026ee:	6078      	str	r0, [r7, #4]
 80026f0:	6039      	str	r1, [r7, #0]
  /* Set all possible values for the Clock type parameter --------------------*/
  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
 80026f2:	687b      	ldr	r3, [r7, #4]
 80026f4:	220f      	movs	r2, #15
 80026f6:	601a      	str	r2, [r3, #0]

  /* Get the SYSCLK configuration --------------------------------------------*/
  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
 80026f8:	4b12      	ldr	r3, [pc, #72]	; (8002744 <HAL_RCC_GetClockConfig+0x5c>)
 80026fa:	689b      	ldr	r3, [r3, #8]
 80026fc:	f003 0203 	and.w	r2, r3, #3
 8002700:	687b      	ldr	r3, [r7, #4]
 8002702:	605a      	str	r2, [r3, #4]

  /* Get the HCLK configuration ----------------------------------------------*/
  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
 8002704:	4b0f      	ldr	r3, [pc, #60]	; (8002744 <HAL_RCC_GetClockConfig+0x5c>)
 8002706:	689b      	ldr	r3, [r3, #8]
 8002708:	f003 02f0 	and.w	r2, r3, #240	; 0xf0
 800270c:	687b      	ldr	r3, [r7, #4]
 800270e:	609a      	str	r2, [r3, #8]

  /* Get the APB1 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
 8002710:	4b0c      	ldr	r3, [pc, #48]	; (8002744 <HAL_RCC_GetClockConfig+0x5c>)
 8002712:	689b      	ldr	r3, [r3, #8]
 8002714:	f403 52e0 	and.w	r2, r3, #7168	; 0x1c00
 8002718:	687b      	ldr	r3, [r7, #4]
 800271a:	60da      	str	r2, [r3, #12]

  /* Get the APB2 configuration ----------------------------------------------*/
  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
 800271c:	4b09      	ldr	r3, [pc, #36]	; (8002744 <HAL_RCC_GetClockConfig+0x5c>)
 800271e:	689b      	ldr	r3, [r3, #8]
 8002720:	08db      	lsrs	r3, r3, #3
 8002722:	f403 52e0 	and.w	r2, r3, #7168	; 0x1c00
 8002726:	687b      	ldr	r3, [r7, #4]
 8002728:	611a      	str	r2, [r3, #16]

  /* Get the Flash Wait State (Latency) configuration ------------------------*/
  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
 800272a:	4b07      	ldr	r3, [pc, #28]	; (8002748 <HAL_RCC_GetClockConfig+0x60>)
 800272c:	681b      	ldr	r3, [r3, #0]
 800272e:	f003 0207 	and.w	r2, r3, #7
 8002732:	683b      	ldr	r3, [r7, #0]
 8002734:	601a      	str	r2, [r3, #0]
}
 8002736:	bf00      	nop
 8002738:	370c      	adds	r7, #12
 800273a:	46bd      	mov	sp, r7
 800273c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002740:	4770      	bx	lr
 8002742:	bf00      	nop
 8002744:	40023800 	.word	0x40023800
 8002748:	40023c00 	.word	0x40023c00

0800274c <HAL_TIM_Base_Init>:
  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
 800274c:	b580      	push	{r7, lr}
 800274e:	b082      	sub	sp, #8
 8002750:	af00      	add	r7, sp, #0
 8002752:	6078      	str	r0, [r7, #4]
  /* Check the TIM handle allocation */
  if (htim == NULL)
 8002754:	687b      	ldr	r3, [r7, #4]
 8002756:	2b00      	cmp	r3, #0
 8002758:	d101      	bne.n	800275e <HAL_TIM_Base_Init+0x12>
  {
    return HAL_ERROR;
 800275a:	2301      	movs	r3, #1
 800275c:	e041      	b.n	80027e2 <HAL_TIM_Base_Init+0x96>
  assert_param(IS_TIM_INSTANCE(htim->Instance));
  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));

  if (htim->State == HAL_TIM_STATE_RESET)
 800275e:	687b      	ldr	r3, [r7, #4]
 8002760:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8002764:	b2db      	uxtb	r3, r3
 8002766:	2b00      	cmp	r3, #0
 8002768:	d106      	bne.n	8002778 <HAL_TIM_Base_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    htim->Lock = HAL_UNLOCKED;
 800276a:	687b      	ldr	r3, [r7, #4]
 800276c:	2200      	movs	r2, #0
 800276e:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c
    }
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    htim->Base_MspInitCallback(htim);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_TIM_Base_MspInit(htim);
 8002772:	6878      	ldr	r0, [r7, #4]
 8002774:	f000 f839 	bl	80027ea <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8002778:	687b      	ldr	r3, [r7, #4]
 800277a:	2202      	movs	r2, #2
 800277c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Set the Time Base configuration */
  TIM_Base_SetConfig(htim->Instance, &htim->Init);
 8002780:	687b      	ldr	r3, [r7, #4]
 8002782:	681a      	ldr	r2, [r3, #0]
 8002784:	687b      	ldr	r3, [r7, #4]
 8002786:	3304      	adds	r3, #4
 8002788:	4619      	mov	r1, r3
 800278a:	4610      	mov	r0, r2
 800278c:	f000 f9ca 	bl	8002b24 <TIM_Base_SetConfig>

  /* Initialize the DMA burst operation state */
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
 8002790:	687b      	ldr	r3, [r7, #4]
 8002792:	2201      	movs	r2, #1
 8002794:	f883 2046 	strb.w	r2, [r3, #70]	; 0x46

  /* Initialize the TIM channels state */
  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 8002798:	687b      	ldr	r3, [r7, #4]
 800279a:	2201      	movs	r2, #1
 800279c:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
 80027a0:	687b      	ldr	r3, [r7, #4]
 80027a2:	2201      	movs	r2, #1
 80027a4:	f883 203f 	strb.w	r2, [r3, #63]	; 0x3f
 80027a8:	687b      	ldr	r3, [r7, #4]
 80027aa:	2201      	movs	r2, #1
 80027ac:	f883 2040 	strb.w	r2, [r3, #64]	; 0x40
 80027b0:	687b      	ldr	r3, [r7, #4]
 80027b2:	2201      	movs	r2, #1
 80027b4:	f883 2041 	strb.w	r2, [r3, #65]	; 0x41
  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
 80027b8:	687b      	ldr	r3, [r7, #4]
 80027ba:	2201      	movs	r2, #1
 80027bc:	f883 2042 	strb.w	r2, [r3, #66]	; 0x42
 80027c0:	687b      	ldr	r3, [r7, #4]
 80027c2:	2201      	movs	r2, #1
 80027c4:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
 80027c8:	687b      	ldr	r3, [r7, #4]
 80027ca:	2201      	movs	r2, #1
 80027cc:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
 80027d0:	687b      	ldr	r3, [r7, #4]
 80027d2:	2201      	movs	r2, #1
 80027d4:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45

  /* Initialize the TIM state*/
  htim->State = HAL_TIM_STATE_READY;
 80027d8:	687b      	ldr	r3, [r7, #4]
 80027da:	2201      	movs	r2, #1
 80027dc:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  return HAL_OK;
 80027e0:	2300      	movs	r3, #0
}
 80027e2:	4618      	mov	r0, r3
 80027e4:	3708      	adds	r7, #8
 80027e6:	46bd      	mov	sp, r7
 80027e8:	bd80      	pop	{r7, pc}

080027ea <HAL_TIM_Base_MspInit>:
  * @brief  Initializes the TIM Base MSP.
  * @param  htim TIM Base handle
  * @retval None
  */
__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
{
 80027ea:	b480      	push	{r7}
 80027ec:	b083      	sub	sp, #12
 80027ee:	af00      	add	r7, sp, #0
 80027f0:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_Base_MspInit could be implemented in the user file
   */
}
 80027f2:	bf00      	nop
 80027f4:	370c      	adds	r7, #12
 80027f6:	46bd      	mov	sp, r7
 80027f8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80027fc:	4770      	bx	lr
	...

08002800 <HAL_TIM_Base_Start_IT>:
  * @brief  Starts the TIM Base generation in interrupt mode.
  * @param  htim TIM Base handle
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
 8002800:	b480      	push	{r7}
 8002802:	b085      	sub	sp, #20
 8002804:	af00      	add	r7, sp, #0
 8002806:	6078      	str	r0, [r7, #4]

  /* Check the parameters */
  assert_param(IS_TIM_INSTANCE(htim->Instance));

  /* Check the TIM state */
  if (htim->State != HAL_TIM_STATE_READY)
 8002808:	687b      	ldr	r3, [r7, #4]
 800280a:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 800280e:	b2db      	uxtb	r3, r3
 8002810:	2b01      	cmp	r3, #1
 8002812:	d001      	beq.n	8002818 <HAL_TIM_Base_Start_IT+0x18>
  {
    return HAL_ERROR;
 8002814:	2301      	movs	r3, #1
 8002816:	e044      	b.n	80028a2 <HAL_TIM_Base_Start_IT+0xa2>
  }

  /* Set the TIM state */
  htim->State = HAL_TIM_STATE_BUSY;
 8002818:	687b      	ldr	r3, [r7, #4]
 800281a:	2202      	movs	r2, #2
 800281c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Enable the TIM Update interrupt */
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
 8002820:	687b      	ldr	r3, [r7, #4]
 8002822:	681b      	ldr	r3, [r3, #0]
 8002824:	68da      	ldr	r2, [r3, #12]
 8002826:	687b      	ldr	r3, [r7, #4]
 8002828:	681b      	ldr	r3, [r3, #0]
 800282a:	f042 0201 	orr.w	r2, r2, #1
 800282e:	60da      	str	r2, [r3, #12]

  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
 8002830:	687b      	ldr	r3, [r7, #4]
 8002832:	681b      	ldr	r3, [r3, #0]
 8002834:	4a1e      	ldr	r2, [pc, #120]	; (80028b0 <HAL_TIM_Base_Start_IT+0xb0>)
 8002836:	4293      	cmp	r3, r2
 8002838:	d018      	beq.n	800286c <HAL_TIM_Base_Start_IT+0x6c>
 800283a:	687b      	ldr	r3, [r7, #4]
 800283c:	681b      	ldr	r3, [r3, #0]
 800283e:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8002842:	d013      	beq.n	800286c <HAL_TIM_Base_Start_IT+0x6c>
 8002844:	687b      	ldr	r3, [r7, #4]
 8002846:	681b      	ldr	r3, [r3, #0]
 8002848:	4a1a      	ldr	r2, [pc, #104]	; (80028b4 <HAL_TIM_Base_Start_IT+0xb4>)
 800284a:	4293      	cmp	r3, r2
 800284c:	d00e      	beq.n	800286c <HAL_TIM_Base_Start_IT+0x6c>
 800284e:	687b      	ldr	r3, [r7, #4]
 8002850:	681b      	ldr	r3, [r3, #0]
 8002852:	4a19      	ldr	r2, [pc, #100]	; (80028b8 <HAL_TIM_Base_Start_IT+0xb8>)
 8002854:	4293      	cmp	r3, r2
 8002856:	d009      	beq.n	800286c <HAL_TIM_Base_Start_IT+0x6c>
 8002858:	687b      	ldr	r3, [r7, #4]
 800285a:	681b      	ldr	r3, [r3, #0]
 800285c:	4a17      	ldr	r2, [pc, #92]	; (80028bc <HAL_TIM_Base_Start_IT+0xbc>)
 800285e:	4293      	cmp	r3, r2
 8002860:	d004      	beq.n	800286c <HAL_TIM_Base_Start_IT+0x6c>
 8002862:	687b      	ldr	r3, [r7, #4]
 8002864:	681b      	ldr	r3, [r3, #0]
 8002866:	4a16      	ldr	r2, [pc, #88]	; (80028c0 <HAL_TIM_Base_Start_IT+0xc0>)
 8002868:	4293      	cmp	r3, r2
 800286a:	d111      	bne.n	8002890 <HAL_TIM_Base_Start_IT+0x90>
  {
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
 800286c:	687b      	ldr	r3, [r7, #4]
 800286e:	681b      	ldr	r3, [r3, #0]
 8002870:	689b      	ldr	r3, [r3, #8]
 8002872:	f003 0307 	and.w	r3, r3, #7
 8002876:	60fb      	str	r3, [r7, #12]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 8002878:	68fb      	ldr	r3, [r7, #12]
 800287a:	2b06      	cmp	r3, #6
 800287c:	d010      	beq.n	80028a0 <HAL_TIM_Base_Start_IT+0xa0>
    {
      __HAL_TIM_ENABLE(htim);
 800287e:	687b      	ldr	r3, [r7, #4]
 8002880:	681b      	ldr	r3, [r3, #0]
 8002882:	681a      	ldr	r2, [r3, #0]
 8002884:	687b      	ldr	r3, [r7, #4]
 8002886:	681b      	ldr	r3, [r3, #0]
 8002888:	f042 0201 	orr.w	r2, r2, #1
 800288c:	601a      	str	r2, [r3, #0]
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
 800288e:	e007      	b.n	80028a0 <HAL_TIM_Base_Start_IT+0xa0>
    }
  }
  else
  {
    __HAL_TIM_ENABLE(htim);
 8002890:	687b      	ldr	r3, [r7, #4]
 8002892:	681b      	ldr	r3, [r3, #0]
 8002894:	681a      	ldr	r2, [r3, #0]
 8002896:	687b      	ldr	r3, [r7, #4]
 8002898:	681b      	ldr	r3, [r3, #0]
 800289a:	f042 0201 	orr.w	r2, r2, #1
 800289e:	601a      	str	r2, [r3, #0]
  }

  /* Return function status */
  return HAL_OK;
 80028a0:	2300      	movs	r3, #0
}
 80028a2:	4618      	mov	r0, r3
 80028a4:	3714      	adds	r7, #20
 80028a6:	46bd      	mov	sp, r7
 80028a8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80028ac:	4770      	bx	lr
 80028ae:	bf00      	nop
 80028b0:	40010000 	.word	0x40010000
 80028b4:	40000400 	.word	0x40000400
 80028b8:	40000800 	.word	0x40000800
 80028bc:	40000c00 	.word	0x40000c00
 80028c0:	40014000 	.word	0x40014000

080028c4 <HAL_TIM_IRQHandler>:
  * @brief  This function handles TIM interrupts requests.
  * @param  htim TIM  handle
  * @retval None
  */
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
 80028c4:	b580      	push	{r7, lr}
 80028c6:	b082      	sub	sp, #8
 80028c8:	af00      	add	r7, sp, #0
 80028ca:	6078      	str	r0, [r7, #4]
  /* Capture compare 1 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
 80028cc:	687b      	ldr	r3, [r7, #4]
 80028ce:	681b      	ldr	r3, [r3, #0]
 80028d0:	691b      	ldr	r3, [r3, #16]
 80028d2:	f003 0302 	and.w	r3, r3, #2
 80028d6:	2b02      	cmp	r3, #2
 80028d8:	d122      	bne.n	8002920 <HAL_TIM_IRQHandler+0x5c>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
 80028da:	687b      	ldr	r3, [r7, #4]
 80028dc:	681b      	ldr	r3, [r3, #0]
 80028de:	68db      	ldr	r3, [r3, #12]
 80028e0:	f003 0302 	and.w	r3, r3, #2
 80028e4:	2b02      	cmp	r3, #2
 80028e6:	d11b      	bne.n	8002920 <HAL_TIM_IRQHandler+0x5c>
    {
      {
        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
 80028e8:	687b      	ldr	r3, [r7, #4]
 80028ea:	681b      	ldr	r3, [r3, #0]
 80028ec:	f06f 0202 	mvn.w	r2, #2
 80028f0:	611a      	str	r2, [r3, #16]
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
 80028f2:	687b      	ldr	r3, [r7, #4]
 80028f4:	2201      	movs	r2, #1
 80028f6:	771a      	strb	r2, [r3, #28]

        /* Input capture event */
        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
 80028f8:	687b      	ldr	r3, [r7, #4]
 80028fa:	681b      	ldr	r3, [r3, #0]
 80028fc:	699b      	ldr	r3, [r3, #24]
 80028fe:	f003 0303 	and.w	r3, r3, #3
 8002902:	2b00      	cmp	r3, #0
 8002904:	d003      	beq.n	800290e <HAL_TIM_IRQHandler+0x4a>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->IC_CaptureCallback(htim);
#else
          HAL_TIM_IC_CaptureCallback(htim);
 8002906:	6878      	ldr	r0, [r7, #4]
 8002908:	f000 f8ee 	bl	8002ae8 <HAL_TIM_IC_CaptureCallback>
 800290c:	e005      	b.n	800291a <HAL_TIM_IRQHandler+0x56>
        {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
          htim->OC_DelayElapsedCallback(htim);
          htim->PWM_PulseFinishedCallback(htim);
#else
          HAL_TIM_OC_DelayElapsedCallback(htim);
 800290e:	6878      	ldr	r0, [r7, #4]
 8002910:	f000 f8e0 	bl	8002ad4 <HAL_TIM_OC_DelayElapsedCallback>
          HAL_TIM_PWM_PulseFinishedCallback(htim);
 8002914:	6878      	ldr	r0, [r7, #4]
 8002916:	f000 f8f1 	bl	8002afc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
        }
        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800291a:	687b      	ldr	r3, [r7, #4]
 800291c:	2200      	movs	r2, #0
 800291e:	771a      	strb	r2, [r3, #28]
      }
    }
  }
  /* Capture compare 2 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
 8002920:	687b      	ldr	r3, [r7, #4]
 8002922:	681b      	ldr	r3, [r3, #0]
 8002924:	691b      	ldr	r3, [r3, #16]
 8002926:	f003 0304 	and.w	r3, r3, #4
 800292a:	2b04      	cmp	r3, #4
 800292c:	d122      	bne.n	8002974 <HAL_TIM_IRQHandler+0xb0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
 800292e:	687b      	ldr	r3, [r7, #4]
 8002930:	681b      	ldr	r3, [r3, #0]
 8002932:	68db      	ldr	r3, [r3, #12]
 8002934:	f003 0304 	and.w	r3, r3, #4
 8002938:	2b04      	cmp	r3, #4
 800293a:	d11b      	bne.n	8002974 <HAL_TIM_IRQHandler+0xb0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
 800293c:	687b      	ldr	r3, [r7, #4]
 800293e:	681b      	ldr	r3, [r3, #0]
 8002940:	f06f 0204 	mvn.w	r2, #4
 8002944:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
 8002946:	687b      	ldr	r3, [r7, #4]
 8002948:	2202      	movs	r2, #2
 800294a:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
 800294c:	687b      	ldr	r3, [r7, #4]
 800294e:	681b      	ldr	r3, [r3, #0]
 8002950:	699b      	ldr	r3, [r3, #24]
 8002952:	f403 7340 	and.w	r3, r3, #768	; 0x300
 8002956:	2b00      	cmp	r3, #0
 8002958:	d003      	beq.n	8002962 <HAL_TIM_IRQHandler+0x9e>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 800295a:	6878      	ldr	r0, [r7, #4]
 800295c:	f000 f8c4 	bl	8002ae8 <HAL_TIM_IC_CaptureCallback>
 8002960:	e005      	b.n	800296e <HAL_TIM_IRQHandler+0xaa>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8002962:	6878      	ldr	r0, [r7, #4]
 8002964:	f000 f8b6 	bl	8002ad4 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8002968:	6878      	ldr	r0, [r7, #4]
 800296a:	f000 f8c7 	bl	8002afc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 800296e:	687b      	ldr	r3, [r7, #4]
 8002970:	2200      	movs	r2, #0
 8002972:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 3 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
 8002974:	687b      	ldr	r3, [r7, #4]
 8002976:	681b      	ldr	r3, [r3, #0]
 8002978:	691b      	ldr	r3, [r3, #16]
 800297a:	f003 0308 	and.w	r3, r3, #8
 800297e:	2b08      	cmp	r3, #8
 8002980:	d122      	bne.n	80029c8 <HAL_TIM_IRQHandler+0x104>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
 8002982:	687b      	ldr	r3, [r7, #4]
 8002984:	681b      	ldr	r3, [r3, #0]
 8002986:	68db      	ldr	r3, [r3, #12]
 8002988:	f003 0308 	and.w	r3, r3, #8
 800298c:	2b08      	cmp	r3, #8
 800298e:	d11b      	bne.n	80029c8 <HAL_TIM_IRQHandler+0x104>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
 8002990:	687b      	ldr	r3, [r7, #4]
 8002992:	681b      	ldr	r3, [r3, #0]
 8002994:	f06f 0208 	mvn.w	r2, #8
 8002998:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
 800299a:	687b      	ldr	r3, [r7, #4]
 800299c:	2204      	movs	r2, #4
 800299e:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
 80029a0:	687b      	ldr	r3, [r7, #4]
 80029a2:	681b      	ldr	r3, [r3, #0]
 80029a4:	69db      	ldr	r3, [r3, #28]
 80029a6:	f003 0303 	and.w	r3, r3, #3
 80029aa:	2b00      	cmp	r3, #0
 80029ac:	d003      	beq.n	80029b6 <HAL_TIM_IRQHandler+0xf2>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 80029ae:	6878      	ldr	r0, [r7, #4]
 80029b0:	f000 f89a 	bl	8002ae8 <HAL_TIM_IC_CaptureCallback>
 80029b4:	e005      	b.n	80029c2 <HAL_TIM_IRQHandler+0xfe>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 80029b6:	6878      	ldr	r0, [r7, #4]
 80029b8:	f000 f88c 	bl	8002ad4 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 80029bc:	6878      	ldr	r0, [r7, #4]
 80029be:	f000 f89d 	bl	8002afc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 80029c2:	687b      	ldr	r3, [r7, #4]
 80029c4:	2200      	movs	r2, #0
 80029c6:	771a      	strb	r2, [r3, #28]
    }
  }
  /* Capture compare 4 event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
 80029c8:	687b      	ldr	r3, [r7, #4]
 80029ca:	681b      	ldr	r3, [r3, #0]
 80029cc:	691b      	ldr	r3, [r3, #16]
 80029ce:	f003 0310 	and.w	r3, r3, #16
 80029d2:	2b10      	cmp	r3, #16
 80029d4:	d122      	bne.n	8002a1c <HAL_TIM_IRQHandler+0x158>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
 80029d6:	687b      	ldr	r3, [r7, #4]
 80029d8:	681b      	ldr	r3, [r3, #0]
 80029da:	68db      	ldr	r3, [r3, #12]
 80029dc:	f003 0310 	and.w	r3, r3, #16
 80029e0:	2b10      	cmp	r3, #16
 80029e2:	d11b      	bne.n	8002a1c <HAL_TIM_IRQHandler+0x158>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
 80029e4:	687b      	ldr	r3, [r7, #4]
 80029e6:	681b      	ldr	r3, [r3, #0]
 80029e8:	f06f 0210 	mvn.w	r2, #16
 80029ec:	611a      	str	r2, [r3, #16]
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
 80029ee:	687b      	ldr	r3, [r7, #4]
 80029f0:	2208      	movs	r2, #8
 80029f2:	771a      	strb	r2, [r3, #28]
      /* Input capture event */
      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
 80029f4:	687b      	ldr	r3, [r7, #4]
 80029f6:	681b      	ldr	r3, [r3, #0]
 80029f8:	69db      	ldr	r3, [r3, #28]
 80029fa:	f403 7340 	and.w	r3, r3, #768	; 0x300
 80029fe:	2b00      	cmp	r3, #0
 8002a00:	d003      	beq.n	8002a0a <HAL_TIM_IRQHandler+0x146>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->IC_CaptureCallback(htim);
#else
        HAL_TIM_IC_CaptureCallback(htim);
 8002a02:	6878      	ldr	r0, [r7, #4]
 8002a04:	f000 f870 	bl	8002ae8 <HAL_TIM_IC_CaptureCallback>
 8002a08:	e005      	b.n	8002a16 <HAL_TIM_IRQHandler+0x152>
      {
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
        htim->OC_DelayElapsedCallback(htim);
        htim->PWM_PulseFinishedCallback(htim);
#else
        HAL_TIM_OC_DelayElapsedCallback(htim);
 8002a0a:	6878      	ldr	r0, [r7, #4]
 8002a0c:	f000 f862 	bl	8002ad4 <HAL_TIM_OC_DelayElapsedCallback>
        HAL_TIM_PWM_PulseFinishedCallback(htim);
 8002a10:	6878      	ldr	r0, [r7, #4]
 8002a12:	f000 f873 	bl	8002afc <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
      }
      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
 8002a16:	687b      	ldr	r3, [r7, #4]
 8002a18:	2200      	movs	r2, #0
 8002a1a:	771a      	strb	r2, [r3, #28]
    }
  }
  /* TIM Update event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
 8002a1c:	687b      	ldr	r3, [r7, #4]
 8002a1e:	681b      	ldr	r3, [r3, #0]
 8002a20:	691b      	ldr	r3, [r3, #16]
 8002a22:	f003 0301 	and.w	r3, r3, #1
 8002a26:	2b01      	cmp	r3, #1
 8002a28:	d10e      	bne.n	8002a48 <HAL_TIM_IRQHandler+0x184>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
 8002a2a:	687b      	ldr	r3, [r7, #4]
 8002a2c:	681b      	ldr	r3, [r3, #0]
 8002a2e:	68db      	ldr	r3, [r3, #12]
 8002a30:	f003 0301 	and.w	r3, r3, #1
 8002a34:	2b01      	cmp	r3, #1
 8002a36:	d107      	bne.n	8002a48 <HAL_TIM_IRQHandler+0x184>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
 8002a38:	687b      	ldr	r3, [r7, #4]
 8002a3a:	681b      	ldr	r3, [r3, #0]
 8002a3c:	f06f 0201 	mvn.w	r2, #1
 8002a40:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->PeriodElapsedCallback(htim);
#else
      HAL_TIM_PeriodElapsedCallback(htim);
 8002a42:	6878      	ldr	r0, [r7, #4]
 8002a44:	f7fe f8c2 	bl	8000bcc <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Break input event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
 8002a48:	687b      	ldr	r3, [r7, #4]
 8002a4a:	681b      	ldr	r3, [r3, #0]
 8002a4c:	691b      	ldr	r3, [r3, #16]
 8002a4e:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8002a52:	2b80      	cmp	r3, #128	; 0x80
 8002a54:	d10e      	bne.n	8002a74 <HAL_TIM_IRQHandler+0x1b0>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
 8002a56:	687b      	ldr	r3, [r7, #4]
 8002a58:	681b      	ldr	r3, [r3, #0]
 8002a5a:	68db      	ldr	r3, [r3, #12]
 8002a5c:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8002a60:	2b80      	cmp	r3, #128	; 0x80
 8002a62:	d107      	bne.n	8002a74 <HAL_TIM_IRQHandler+0x1b0>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
 8002a64:	687b      	ldr	r3, [r7, #4]
 8002a66:	681b      	ldr	r3, [r3, #0]
 8002a68:	f06f 0280 	mvn.w	r2, #128	; 0x80
 8002a6c:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->BreakCallback(htim);
#else
      HAL_TIMEx_BreakCallback(htim);
 8002a6e:	6878      	ldr	r0, [r7, #4]
 8002a70:	f000 f8e2 	bl	8002c38 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM Trigger detection event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
 8002a74:	687b      	ldr	r3, [r7, #4]
 8002a76:	681b      	ldr	r3, [r3, #0]
 8002a78:	691b      	ldr	r3, [r3, #16]
 8002a7a:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002a7e:	2b40      	cmp	r3, #64	; 0x40
 8002a80:	d10e      	bne.n	8002aa0 <HAL_TIM_IRQHandler+0x1dc>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
 8002a82:	687b      	ldr	r3, [r7, #4]
 8002a84:	681b      	ldr	r3, [r3, #0]
 8002a86:	68db      	ldr	r3, [r3, #12]
 8002a88:	f003 0340 	and.w	r3, r3, #64	; 0x40
 8002a8c:	2b40      	cmp	r3, #64	; 0x40
 8002a8e:	d107      	bne.n	8002aa0 <HAL_TIM_IRQHandler+0x1dc>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
 8002a90:	687b      	ldr	r3, [r7, #4]
 8002a92:	681b      	ldr	r3, [r3, #0]
 8002a94:	f06f 0240 	mvn.w	r2, #64	; 0x40
 8002a98:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->TriggerCallback(htim);
#else
      HAL_TIM_TriggerCallback(htim);
 8002a9a:	6878      	ldr	r0, [r7, #4]
 8002a9c:	f000 f838 	bl	8002b10 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
  /* TIM commutation event */
  if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
 8002aa0:	687b      	ldr	r3, [r7, #4]
 8002aa2:	681b      	ldr	r3, [r3, #0]
 8002aa4:	691b      	ldr	r3, [r3, #16]
 8002aa6:	f003 0320 	and.w	r3, r3, #32
 8002aaa:	2b20      	cmp	r3, #32
 8002aac:	d10e      	bne.n	8002acc <HAL_TIM_IRQHandler+0x208>
  {
    if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
 8002aae:	687b      	ldr	r3, [r7, #4]
 8002ab0:	681b      	ldr	r3, [r3, #0]
 8002ab2:	68db      	ldr	r3, [r3, #12]
 8002ab4:	f003 0320 	and.w	r3, r3, #32
 8002ab8:	2b20      	cmp	r3, #32
 8002aba:	d107      	bne.n	8002acc <HAL_TIM_IRQHandler+0x208>
    {
      __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
 8002abc:	687b      	ldr	r3, [r7, #4]
 8002abe:	681b      	ldr	r3, [r3, #0]
 8002ac0:	f06f 0220 	mvn.w	r2, #32
 8002ac4:	611a      	str	r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
      htim->CommutationCallback(htim);
#else
      HAL_TIMEx_CommutCallback(htim);
 8002ac6:	6878      	ldr	r0, [r7, #4]
 8002ac8:	f000 f8ac 	bl	8002c24 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
    }
  }
}
 8002acc:	bf00      	nop
 8002ace:	3708      	adds	r7, #8
 8002ad0:	46bd      	mov	sp, r7
 8002ad2:	bd80      	pop	{r7, pc}

08002ad4 <HAL_TIM_OC_DelayElapsedCallback>:
  * @brief  Output Compare callback in non-blocking mode
  * @param  htim TIM OC handle
  * @retval None
  */
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
 8002ad4:	b480      	push	{r7}
 8002ad6:	b083      	sub	sp, #12
 8002ad8:	af00      	add	r7, sp, #0
 8002ada:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
   */
}
 8002adc:	bf00      	nop
 8002ade:	370c      	adds	r7, #12
 8002ae0:	46bd      	mov	sp, r7
 8002ae2:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002ae6:	4770      	bx	lr

08002ae8 <HAL_TIM_IC_CaptureCallback>:
  * @brief  Input Capture callback in non-blocking mode
  * @param  htim TIM IC handle
  * @retval None
  */
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
 8002ae8:	b480      	push	{r7}
 8002aea:	b083      	sub	sp, #12
 8002aec:	af00      	add	r7, sp, #0
 8002aee:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
   */
}
 8002af0:	bf00      	nop
 8002af2:	370c      	adds	r7, #12
 8002af4:	46bd      	mov	sp, r7
 8002af6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002afa:	4770      	bx	lr

08002afc <HAL_TIM_PWM_PulseFinishedCallback>:
  * @brief  PWM Pulse finished callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
 8002afc:	b480      	push	{r7}
 8002afe:	b083      	sub	sp, #12
 8002b00:	af00      	add	r7, sp, #0
 8002b02:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
   */
}
 8002b04:	bf00      	nop
 8002b06:	370c      	adds	r7, #12
 8002b08:	46bd      	mov	sp, r7
 8002b0a:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002b0e:	4770      	bx	lr

08002b10 <HAL_TIM_TriggerCallback>:
  * @brief  Hall Trigger detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
 8002b10:	b480      	push	{r7}
 8002b12:	b083      	sub	sp, #12
 8002b14:	af00      	add	r7, sp, #0
 8002b16:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIM_TriggerCallback could be implemented in the user file
   */
}
 8002b18:	bf00      	nop
 8002b1a:	370c      	adds	r7, #12
 8002b1c:	46bd      	mov	sp, r7
 8002b1e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002b22:	4770      	bx	lr

08002b24 <TIM_Base_SetConfig>:
  * @param  TIMx TIM peripheral
  * @param  Structure TIM Base configuration structure
  * @retval None
  */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
{
 8002b24:	b480      	push	{r7}
 8002b26:	b085      	sub	sp, #20
 8002b28:	af00      	add	r7, sp, #0
 8002b2a:	6078      	str	r0, [r7, #4]
 8002b2c:	6039      	str	r1, [r7, #0]
  uint32_t tmpcr1;
  tmpcr1 = TIMx->CR1;
 8002b2e:	687b      	ldr	r3, [r7, #4]
 8002b30:	681b      	ldr	r3, [r3, #0]
 8002b32:	60fb      	str	r3, [r7, #12]

  /* Set TIM Time Base Unit parameters ---------------------------------------*/
  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 8002b34:	687b      	ldr	r3, [r7, #4]
 8002b36:	4a34      	ldr	r2, [pc, #208]	; (8002c08 <TIM_Base_SetConfig+0xe4>)
 8002b38:	4293      	cmp	r3, r2
 8002b3a:	d00f      	beq.n	8002b5c <TIM_Base_SetConfig+0x38>
 8002b3c:	687b      	ldr	r3, [r7, #4]
 8002b3e:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8002b42:	d00b      	beq.n	8002b5c <TIM_Base_SetConfig+0x38>
 8002b44:	687b      	ldr	r3, [r7, #4]
 8002b46:	4a31      	ldr	r2, [pc, #196]	; (8002c0c <TIM_Base_SetConfig+0xe8>)
 8002b48:	4293      	cmp	r3, r2
 8002b4a:	d007      	beq.n	8002b5c <TIM_Base_SetConfig+0x38>
 8002b4c:	687b      	ldr	r3, [r7, #4]
 8002b4e:	4a30      	ldr	r2, [pc, #192]	; (8002c10 <TIM_Base_SetConfig+0xec>)
 8002b50:	4293      	cmp	r3, r2
 8002b52:	d003      	beq.n	8002b5c <TIM_Base_SetConfig+0x38>
 8002b54:	687b      	ldr	r3, [r7, #4]
 8002b56:	4a2f      	ldr	r2, [pc, #188]	; (8002c14 <TIM_Base_SetConfig+0xf0>)
 8002b58:	4293      	cmp	r3, r2
 8002b5a:	d108      	bne.n	8002b6e <TIM_Base_SetConfig+0x4a>
  {
    /* Select the Counter Mode */
    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
 8002b5c:	68fb      	ldr	r3, [r7, #12]
 8002b5e:	f023 0370 	bic.w	r3, r3, #112	; 0x70
 8002b62:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= Structure->CounterMode;
 8002b64:	683b      	ldr	r3, [r7, #0]
 8002b66:	685b      	ldr	r3, [r3, #4]
 8002b68:	68fa      	ldr	r2, [r7, #12]
 8002b6a:	4313      	orrs	r3, r2
 8002b6c:	60fb      	str	r3, [r7, #12]
  }

  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 8002b6e:	687b      	ldr	r3, [r7, #4]
 8002b70:	4a25      	ldr	r2, [pc, #148]	; (8002c08 <TIM_Base_SetConfig+0xe4>)
 8002b72:	4293      	cmp	r3, r2
 8002b74:	d01b      	beq.n	8002bae <TIM_Base_SetConfig+0x8a>
 8002b76:	687b      	ldr	r3, [r7, #4]
 8002b78:	f1b3 4f80 	cmp.w	r3, #1073741824	; 0x40000000
 8002b7c:	d017      	beq.n	8002bae <TIM_Base_SetConfig+0x8a>
 8002b7e:	687b      	ldr	r3, [r7, #4]
 8002b80:	4a22      	ldr	r2, [pc, #136]	; (8002c0c <TIM_Base_SetConfig+0xe8>)
 8002b82:	4293      	cmp	r3, r2
 8002b84:	d013      	beq.n	8002bae <TIM_Base_SetConfig+0x8a>
 8002b86:	687b      	ldr	r3, [r7, #4]
 8002b88:	4a21      	ldr	r2, [pc, #132]	; (8002c10 <TIM_Base_SetConfig+0xec>)
 8002b8a:	4293      	cmp	r3, r2
 8002b8c:	d00f      	beq.n	8002bae <TIM_Base_SetConfig+0x8a>
 8002b8e:	687b      	ldr	r3, [r7, #4]
 8002b90:	4a20      	ldr	r2, [pc, #128]	; (8002c14 <TIM_Base_SetConfig+0xf0>)
 8002b92:	4293      	cmp	r3, r2
 8002b94:	d00b      	beq.n	8002bae <TIM_Base_SetConfig+0x8a>
 8002b96:	687b      	ldr	r3, [r7, #4]
 8002b98:	4a1f      	ldr	r2, [pc, #124]	; (8002c18 <TIM_Base_SetConfig+0xf4>)
 8002b9a:	4293      	cmp	r3, r2
 8002b9c:	d007      	beq.n	8002bae <TIM_Base_SetConfig+0x8a>
 8002b9e:	687b      	ldr	r3, [r7, #4]
 8002ba0:	4a1e      	ldr	r2, [pc, #120]	; (8002c1c <TIM_Base_SetConfig+0xf8>)
 8002ba2:	4293      	cmp	r3, r2
 8002ba4:	d003      	beq.n	8002bae <TIM_Base_SetConfig+0x8a>
 8002ba6:	687b      	ldr	r3, [r7, #4]
 8002ba8:	4a1d      	ldr	r2, [pc, #116]	; (8002c20 <TIM_Base_SetConfig+0xfc>)
 8002baa:	4293      	cmp	r3, r2
 8002bac:	d108      	bne.n	8002bc0 <TIM_Base_SetConfig+0x9c>
  {
    /* Set the clock division */
    tmpcr1 &= ~TIM_CR1_CKD;
 8002bae:	68fb      	ldr	r3, [r7, #12]
 8002bb0:	f423 7340 	bic.w	r3, r3, #768	; 0x300
 8002bb4:	60fb      	str	r3, [r7, #12]
    tmpcr1 |= (uint32_t)Structure->ClockDivision;
 8002bb6:	683b      	ldr	r3, [r7, #0]
 8002bb8:	68db      	ldr	r3, [r3, #12]
 8002bba:	68fa      	ldr	r2, [r7, #12]
 8002bbc:	4313      	orrs	r3, r2
 8002bbe:	60fb      	str	r3, [r7, #12]
  }

  /* Set the auto-reload preload */
  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
 8002bc0:	68fb      	ldr	r3, [r7, #12]
 8002bc2:	f023 0280 	bic.w	r2, r3, #128	; 0x80
 8002bc6:	683b      	ldr	r3, [r7, #0]
 8002bc8:	695b      	ldr	r3, [r3, #20]
 8002bca:	4313      	orrs	r3, r2
 8002bcc:	60fb      	str	r3, [r7, #12]

  TIMx->CR1 = tmpcr1;
 8002bce:	687b      	ldr	r3, [r7, #4]
 8002bd0:	68fa      	ldr	r2, [r7, #12]
 8002bd2:	601a      	str	r2, [r3, #0]

  /* Set the Autoreload value */
  TIMx->ARR = (uint32_t)Structure->Period ;
 8002bd4:	683b      	ldr	r3, [r7, #0]
 8002bd6:	689a      	ldr	r2, [r3, #8]
 8002bd8:	687b      	ldr	r3, [r7, #4]
 8002bda:	62da      	str	r2, [r3, #44]	; 0x2c

  /* Set the Prescaler value */
  TIMx->PSC = Structure->Prescaler;
 8002bdc:	683b      	ldr	r3, [r7, #0]
 8002bde:	681a      	ldr	r2, [r3, #0]
 8002be0:	687b      	ldr	r3, [r7, #4]
 8002be2:	629a      	str	r2, [r3, #40]	; 0x28

  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 8002be4:	687b      	ldr	r3, [r7, #4]
 8002be6:	4a08      	ldr	r2, [pc, #32]	; (8002c08 <TIM_Base_SetConfig+0xe4>)
 8002be8:	4293      	cmp	r3, r2
 8002bea:	d103      	bne.n	8002bf4 <TIM_Base_SetConfig+0xd0>
  {
    /* Set the Repetition Counter value */
    TIMx->RCR = Structure->RepetitionCounter;
 8002bec:	683b      	ldr	r3, [r7, #0]
 8002bee:	691a      	ldr	r2, [r3, #16]
 8002bf0:	687b      	ldr	r3, [r7, #4]
 8002bf2:	631a      	str	r2, [r3, #48]	; 0x30
  }

  /* Generate an update event to reload the Prescaler
     and the repetition counter (only for advanced timer) value immediately */
  TIMx->EGR = TIM_EGR_UG;
 8002bf4:	687b      	ldr	r3, [r7, #4]
 8002bf6:	2201      	movs	r2, #1
 8002bf8:	615a      	str	r2, [r3, #20]
}
 8002bfa:	bf00      	nop
 8002bfc:	3714      	adds	r7, #20
 8002bfe:	46bd      	mov	sp, r7
 8002c00:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002c04:	4770      	bx	lr
 8002c06:	bf00      	nop
 8002c08:	40010000 	.word	0x40010000
 8002c0c:	40000400 	.word	0x40000400
 8002c10:	40000800 	.word	0x40000800
 8002c14:	40000c00 	.word	0x40000c00
 8002c18:	40014000 	.word	0x40014000
 8002c1c:	40014400 	.word	0x40014400
 8002c20:	40014800 	.word	0x40014800

08002c24 <HAL_TIMEx_CommutCallback>:
  * @brief  Hall commutation changed callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
 8002c24:	b480      	push	{r7}
 8002c26:	b083      	sub	sp, #12
 8002c28:	af00      	add	r7, sp, #0
 8002c2a:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_CommutCallback could be implemented in the user file
   */
}
 8002c2c:	bf00      	nop
 8002c2e:	370c      	adds	r7, #12
 8002c30:	46bd      	mov	sp, r7
 8002c32:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002c36:	4770      	bx	lr

08002c38 <HAL_TIMEx_BreakCallback>:
  * @brief  Hall Break detection callback in non-blocking mode
  * @param  htim TIM handle
  * @retval None
  */
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
 8002c38:	b480      	push	{r7}
 8002c3a:	b083      	sub	sp, #12
 8002c3c:	af00      	add	r7, sp, #0
 8002c3e:	6078      	str	r0, [r7, #4]
  UNUSED(htim);

  /* NOTE : This function should not be modified, when the callback is needed,
            the HAL_TIMEx_BreakCallback could be implemented in the user file
   */
}
 8002c40:	bf00      	nop
 8002c42:	370c      	adds	r7, #12
 8002c44:	46bd      	mov	sp, r7
 8002c46:	f85d 7b04 	ldr.w	r7, [sp], #4
 8002c4a:	4770      	bx	lr

08002c4c <HAL_UART_Init>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
 8002c4c:	b580      	push	{r7, lr}
 8002c4e:	b082      	sub	sp, #8
 8002c50:	af00      	add	r7, sp, #0
 8002c52:	6078      	str	r0, [r7, #4]
  /* Check the UART handle allocation */
  if (huart == NULL)
 8002c54:	687b      	ldr	r3, [r7, #4]
 8002c56:	2b00      	cmp	r3, #0
 8002c58:	d101      	bne.n	8002c5e <HAL_UART_Init+0x12>
  {
    return HAL_ERROR;
 8002c5a:	2301      	movs	r3, #1
 8002c5c:	e03f      	b.n	8002cde <HAL_UART_Init+0x92>
    assert_param(IS_UART_INSTANCE(huart->Instance));
  }
  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));

  if (huart->gState == HAL_UART_STATE_RESET)
 8002c5e:	687b      	ldr	r3, [r7, #4]
 8002c60:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8002c64:	b2db      	uxtb	r3, r3
 8002c66:	2b00      	cmp	r3, #0
 8002c68:	d106      	bne.n	8002c78 <HAL_UART_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    huart->Lock = HAL_UNLOCKED;
 8002c6a:	687b      	ldr	r3, [r7, #4]
 8002c6c:	2200      	movs	r2, #0
 8002c6e:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Init the low level hardware */
    huart->MspInitCallback(huart);
#else
    /* Init the low level hardware : GPIO, CLOCK */
    HAL_UART_MspInit(huart);
 8002c72:	6878      	ldr	r0, [r7, #4]
 8002c74:	f7fe f83a 	bl	8000cec <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
  }

  huart->gState = HAL_UART_STATE_BUSY;
 8002c78:	687b      	ldr	r3, [r7, #4]
 8002c7a:	2224      	movs	r2, #36	; 0x24
 8002c7c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Disable the peripheral */
  __HAL_UART_DISABLE(huart);
 8002c80:	687b      	ldr	r3, [r7, #4]
 8002c82:	681b      	ldr	r3, [r3, #0]
 8002c84:	68da      	ldr	r2, [r3, #12]
 8002c86:	687b      	ldr	r3, [r7, #4]
 8002c88:	681b      	ldr	r3, [r3, #0]
 8002c8a:	f422 5200 	bic.w	r2, r2, #8192	; 0x2000
 8002c8e:	60da      	str	r2, [r3, #12]

  /* Set the UART Communication parameters */
  UART_SetConfig(huart);
 8002c90:	6878      	ldr	r0, [r7, #4]
 8002c92:	f000 f9cb 	bl	800302c <UART_SetConfig>

  /* In asynchronous mode, the following bits must be kept cleared:
     - LINEN and CLKEN bits in the USART_CR2 register,
     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
 8002c96:	687b      	ldr	r3, [r7, #4]
 8002c98:	681b      	ldr	r3, [r3, #0]
 8002c9a:	691a      	ldr	r2, [r3, #16]
 8002c9c:	687b      	ldr	r3, [r7, #4]
 8002c9e:	681b      	ldr	r3, [r3, #0]
 8002ca0:	f422 4290 	bic.w	r2, r2, #18432	; 0x4800
 8002ca4:	611a      	str	r2, [r3, #16]
  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
 8002ca6:	687b      	ldr	r3, [r7, #4]
 8002ca8:	681b      	ldr	r3, [r3, #0]
 8002caa:	695a      	ldr	r2, [r3, #20]
 8002cac:	687b      	ldr	r3, [r7, #4]
 8002cae:	681b      	ldr	r3, [r3, #0]
 8002cb0:	f022 022a 	bic.w	r2, r2, #42	; 0x2a
 8002cb4:	615a      	str	r2, [r3, #20]

  /* Enable the peripheral */
  __HAL_UART_ENABLE(huart);
 8002cb6:	687b      	ldr	r3, [r7, #4]
 8002cb8:	681b      	ldr	r3, [r3, #0]
 8002cba:	68da      	ldr	r2, [r3, #12]
 8002cbc:	687b      	ldr	r3, [r7, #4]
 8002cbe:	681b      	ldr	r3, [r3, #0]
 8002cc0:	f442 5200 	orr.w	r2, r2, #8192	; 0x2000
 8002cc4:	60da      	str	r2, [r3, #12]

  /* Initialize the UART state */
  huart->ErrorCode = HAL_UART_ERROR_NONE;
 8002cc6:	687b      	ldr	r3, [r7, #4]
 8002cc8:	2200      	movs	r2, #0
 8002cca:	641a      	str	r2, [r3, #64]	; 0x40
  huart->gState = HAL_UART_STATE_READY;
 8002ccc:	687b      	ldr	r3, [r7, #4]
 8002cce:	2220      	movs	r2, #32
 8002cd0:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
  huart->RxState = HAL_UART_STATE_READY;
 8002cd4:	687b      	ldr	r3, [r7, #4]
 8002cd6:	2220      	movs	r2, #32
 8002cd8:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

  return HAL_OK;
 8002cdc:	2300      	movs	r3, #0
}
 8002cde:	4618      	mov	r0, r3
 8002ce0:	3708      	adds	r7, #8
 8002ce2:	46bd      	mov	sp, r7
 8002ce4:	bd80      	pop	{r7, pc}

08002ce6 <HAL_UART_Transmit>:
  * @param  Size  Amount of data elements (u8 or u16) to be sent
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 8002ce6:	b580      	push	{r7, lr}
 8002ce8:	b08a      	sub	sp, #40	; 0x28
 8002cea:	af02      	add	r7, sp, #8
 8002cec:	60f8      	str	r0, [r7, #12]
 8002cee:	60b9      	str	r1, [r7, #8]
 8002cf0:	603b      	str	r3, [r7, #0]
 8002cf2:	4613      	mov	r3, r2
 8002cf4:	80fb      	strh	r3, [r7, #6]
  const uint8_t  *pdata8bits;
  const uint16_t *pdata16bits;
  uint32_t tickstart = 0U;
 8002cf6:	2300      	movs	r3, #0
 8002cf8:	617b      	str	r3, [r7, #20]

  /* Check that a Tx process is not already ongoing */
  if (huart->gState == HAL_UART_STATE_READY)
 8002cfa:	68fb      	ldr	r3, [r7, #12]
 8002cfc:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8002d00:	b2db      	uxtb	r3, r3
 8002d02:	2b20      	cmp	r3, #32
 8002d04:	d17c      	bne.n	8002e00 <HAL_UART_Transmit+0x11a>
  {
    if ((pData == NULL) || (Size == 0U))
 8002d06:	68bb      	ldr	r3, [r7, #8]
 8002d08:	2b00      	cmp	r3, #0
 8002d0a:	d002      	beq.n	8002d12 <HAL_UART_Transmit+0x2c>
 8002d0c:	88fb      	ldrh	r3, [r7, #6]
 8002d0e:	2b00      	cmp	r3, #0
 8002d10:	d101      	bne.n	8002d16 <HAL_UART_Transmit+0x30>
    {
      return  HAL_ERROR;
 8002d12:	2301      	movs	r3, #1
 8002d14:	e075      	b.n	8002e02 <HAL_UART_Transmit+0x11c>
    }

    /* Process Locked */
    __HAL_LOCK(huart);
 8002d16:	68fb      	ldr	r3, [r7, #12]
 8002d18:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 8002d1c:	2b01      	cmp	r3, #1
 8002d1e:	d101      	bne.n	8002d24 <HAL_UART_Transmit+0x3e>
 8002d20:	2302      	movs	r3, #2
 8002d22:	e06e      	b.n	8002e02 <HAL_UART_Transmit+0x11c>
 8002d24:	68fb      	ldr	r3, [r7, #12]
 8002d26:	2201      	movs	r2, #1
 8002d28:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8002d2c:	68fb      	ldr	r3, [r7, #12]
 8002d2e:	2200      	movs	r2, #0
 8002d30:	641a      	str	r2, [r3, #64]	; 0x40
    huart->gState = HAL_UART_STATE_BUSY_TX;
 8002d32:	68fb      	ldr	r3, [r7, #12]
 8002d34:	2221      	movs	r2, #33	; 0x21
 8002d36:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

    /* Init tickstart for timeout management */
    tickstart = HAL_GetTick();
 8002d3a:	f7fe f92d 	bl	8000f98 <HAL_GetTick>
 8002d3e:	6178      	str	r0, [r7, #20]

    huart->TxXferSize = Size;
 8002d40:	68fb      	ldr	r3, [r7, #12]
 8002d42:	88fa      	ldrh	r2, [r7, #6]
 8002d44:	849a      	strh	r2, [r3, #36]	; 0x24
    huart->TxXferCount = Size;
 8002d46:	68fb      	ldr	r3, [r7, #12]
 8002d48:	88fa      	ldrh	r2, [r7, #6]
 8002d4a:	84da      	strh	r2, [r3, #38]	; 0x26

    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 8002d4c:	68fb      	ldr	r3, [r7, #12]
 8002d4e:	689b      	ldr	r3, [r3, #8]
 8002d50:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8002d54:	d108      	bne.n	8002d68 <HAL_UART_Transmit+0x82>
 8002d56:	68fb      	ldr	r3, [r7, #12]
 8002d58:	691b      	ldr	r3, [r3, #16]
 8002d5a:	2b00      	cmp	r3, #0
 8002d5c:	d104      	bne.n	8002d68 <HAL_UART_Transmit+0x82>
    {
      pdata8bits  = NULL;
 8002d5e:	2300      	movs	r3, #0
 8002d60:	61fb      	str	r3, [r7, #28]
      pdata16bits = (const uint16_t *) pData;
 8002d62:	68bb      	ldr	r3, [r7, #8]
 8002d64:	61bb      	str	r3, [r7, #24]
 8002d66:	e003      	b.n	8002d70 <HAL_UART_Transmit+0x8a>
    }
    else
    {
      pdata8bits  = pData;
 8002d68:	68bb      	ldr	r3, [r7, #8]
 8002d6a:	61fb      	str	r3, [r7, #28]
      pdata16bits = NULL;
 8002d6c:	2300      	movs	r3, #0
 8002d6e:	61bb      	str	r3, [r7, #24]
    }

    /* Process Unlocked */
    __HAL_UNLOCK(huart);
 8002d70:	68fb      	ldr	r3, [r7, #12]
 8002d72:	2200      	movs	r2, #0
 8002d74:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    while (huart->TxXferCount > 0U)
 8002d78:	e02a      	b.n	8002dd0 <HAL_UART_Transmit+0xea>
    {
      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
 8002d7a:	683b      	ldr	r3, [r7, #0]
 8002d7c:	9300      	str	r3, [sp, #0]
 8002d7e:	697b      	ldr	r3, [r7, #20]
 8002d80:	2200      	movs	r2, #0
 8002d82:	2180      	movs	r1, #128	; 0x80
 8002d84:	68f8      	ldr	r0, [r7, #12]
 8002d86:	f000 f8e2 	bl	8002f4e <UART_WaitOnFlagUntilTimeout>
 8002d8a:	4603      	mov	r3, r0
 8002d8c:	2b00      	cmp	r3, #0
 8002d8e:	d001      	beq.n	8002d94 <HAL_UART_Transmit+0xae>
      {
        return HAL_TIMEOUT;
 8002d90:	2303      	movs	r3, #3
 8002d92:	e036      	b.n	8002e02 <HAL_UART_Transmit+0x11c>
      }
      if (pdata8bits == NULL)
 8002d94:	69fb      	ldr	r3, [r7, #28]
 8002d96:	2b00      	cmp	r3, #0
 8002d98:	d10b      	bne.n	8002db2 <HAL_UART_Transmit+0xcc>
      {
        huart->Instance->DR = (uint16_t)(*pdata16bits & 0x01FFU);
 8002d9a:	69bb      	ldr	r3, [r7, #24]
 8002d9c:	881b      	ldrh	r3, [r3, #0]
 8002d9e:	461a      	mov	r2, r3
 8002da0:	68fb      	ldr	r3, [r7, #12]
 8002da2:	681b      	ldr	r3, [r3, #0]
 8002da4:	f3c2 0208 	ubfx	r2, r2, #0, #9
 8002da8:	605a      	str	r2, [r3, #4]
        pdata16bits++;
 8002daa:	69bb      	ldr	r3, [r7, #24]
 8002dac:	3302      	adds	r3, #2
 8002dae:	61bb      	str	r3, [r7, #24]
 8002db0:	e007      	b.n	8002dc2 <HAL_UART_Transmit+0xdc>
      }
      else
      {
        huart->Instance->DR = (uint8_t)(*pdata8bits & 0xFFU);
 8002db2:	69fb      	ldr	r3, [r7, #28]
 8002db4:	781a      	ldrb	r2, [r3, #0]
 8002db6:	68fb      	ldr	r3, [r7, #12]
 8002db8:	681b      	ldr	r3, [r3, #0]
 8002dba:	605a      	str	r2, [r3, #4]
        pdata8bits++;
 8002dbc:	69fb      	ldr	r3, [r7, #28]
 8002dbe:	3301      	adds	r3, #1
 8002dc0:	61fb      	str	r3, [r7, #28]
      }
      huart->TxXferCount--;
 8002dc2:	68fb      	ldr	r3, [r7, #12]
 8002dc4:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
 8002dc6:	b29b      	uxth	r3, r3
 8002dc8:	3b01      	subs	r3, #1
 8002dca:	b29a      	uxth	r2, r3
 8002dcc:	68fb      	ldr	r3, [r7, #12]
 8002dce:	84da      	strh	r2, [r3, #38]	; 0x26
    while (huart->TxXferCount > 0U)
 8002dd0:	68fb      	ldr	r3, [r7, #12]
 8002dd2:	8cdb      	ldrh	r3, [r3, #38]	; 0x26
 8002dd4:	b29b      	uxth	r3, r3
 8002dd6:	2b00      	cmp	r3, #0
 8002dd8:	d1cf      	bne.n	8002d7a <HAL_UART_Transmit+0x94>
    }

    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
 8002dda:	683b      	ldr	r3, [r7, #0]
 8002ddc:	9300      	str	r3, [sp, #0]
 8002dde:	697b      	ldr	r3, [r7, #20]
 8002de0:	2200      	movs	r2, #0
 8002de2:	2140      	movs	r1, #64	; 0x40
 8002de4:	68f8      	ldr	r0, [r7, #12]
 8002de6:	f000 f8b2 	bl	8002f4e <UART_WaitOnFlagUntilTimeout>
 8002dea:	4603      	mov	r3, r0
 8002dec:	2b00      	cmp	r3, #0
 8002dee:	d001      	beq.n	8002df4 <HAL_UART_Transmit+0x10e>
    {
      return HAL_TIMEOUT;
 8002df0:	2303      	movs	r3, #3
 8002df2:	e006      	b.n	8002e02 <HAL_UART_Transmit+0x11c>
    }

    /* At end of Tx process, restore huart->gState to Ready */
    huart->gState = HAL_UART_STATE_READY;
 8002df4:	68fb      	ldr	r3, [r7, #12]
 8002df6:	2220      	movs	r2, #32
 8002df8:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

    return HAL_OK;
 8002dfc:	2300      	movs	r3, #0
 8002dfe:	e000      	b.n	8002e02 <HAL_UART_Transmit+0x11c>
  }
  else
  {
    return HAL_BUSY;
 8002e00:	2302      	movs	r3, #2
  }
}
 8002e02:	4618      	mov	r0, r3
 8002e04:	3720      	adds	r7, #32
 8002e06:	46bd      	mov	sp, r7
 8002e08:	bd80      	pop	{r7, pc}

08002e0a <HAL_UART_Receive>:
  * @param  Size  Amount of data elements (u8 or u16) to be received.
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 8002e0a:	b580      	push	{r7, lr}
 8002e0c:	b08a      	sub	sp, #40	; 0x28
 8002e0e:	af02      	add	r7, sp, #8
 8002e10:	60f8      	str	r0, [r7, #12]
 8002e12:	60b9      	str	r1, [r7, #8]
 8002e14:	603b      	str	r3, [r7, #0]
 8002e16:	4613      	mov	r3, r2
 8002e18:	80fb      	strh	r3, [r7, #6]
  uint8_t  *pdata8bits;
  uint16_t *pdata16bits;
  uint32_t tickstart = 0U;
 8002e1a:	2300      	movs	r3, #0
 8002e1c:	617b      	str	r3, [r7, #20]

  /* Check that a Rx process is not already ongoing */
  if (huart->RxState == HAL_UART_STATE_READY)
 8002e1e:	68fb      	ldr	r3, [r7, #12]
 8002e20:	f893 303e 	ldrb.w	r3, [r3, #62]	; 0x3e
 8002e24:	b2db      	uxtb	r3, r3
 8002e26:	2b20      	cmp	r3, #32
 8002e28:	f040 808c 	bne.w	8002f44 <HAL_UART_Receive+0x13a>
  {
    if ((pData == NULL) || (Size == 0U))
 8002e2c:	68bb      	ldr	r3, [r7, #8]
 8002e2e:	2b00      	cmp	r3, #0
 8002e30:	d002      	beq.n	8002e38 <HAL_UART_Receive+0x2e>
 8002e32:	88fb      	ldrh	r3, [r7, #6]
 8002e34:	2b00      	cmp	r3, #0
 8002e36:	d101      	bne.n	8002e3c <HAL_UART_Receive+0x32>
    {
      return  HAL_ERROR;
 8002e38:	2301      	movs	r3, #1
 8002e3a:	e084      	b.n	8002f46 <HAL_UART_Receive+0x13c>
    }

    /* Process Locked */
    __HAL_LOCK(huart);
 8002e3c:	68fb      	ldr	r3, [r7, #12]
 8002e3e:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 8002e42:	2b01      	cmp	r3, #1
 8002e44:	d101      	bne.n	8002e4a <HAL_UART_Receive+0x40>
 8002e46:	2302      	movs	r3, #2
 8002e48:	e07d      	b.n	8002f46 <HAL_UART_Receive+0x13c>
 8002e4a:	68fb      	ldr	r3, [r7, #12]
 8002e4c:	2201      	movs	r2, #1
 8002e4e:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    huart->ErrorCode = HAL_UART_ERROR_NONE;
 8002e52:	68fb      	ldr	r3, [r7, #12]
 8002e54:	2200      	movs	r2, #0
 8002e56:	641a      	str	r2, [r3, #64]	; 0x40
    huart->RxState = HAL_UART_STATE_BUSY_RX;
 8002e58:	68fb      	ldr	r3, [r7, #12]
 8002e5a:	2222      	movs	r2, #34	; 0x22
 8002e5c:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
 8002e60:	68fb      	ldr	r3, [r7, #12]
 8002e62:	2200      	movs	r2, #0
 8002e64:	631a      	str	r2, [r3, #48]	; 0x30

    /* Init tickstart for timeout management */
    tickstart = HAL_GetTick();
 8002e66:	f7fe f897 	bl	8000f98 <HAL_GetTick>
 8002e6a:	6178      	str	r0, [r7, #20]

    huart->RxXferSize = Size;
 8002e6c:	68fb      	ldr	r3, [r7, #12]
 8002e6e:	88fa      	ldrh	r2, [r7, #6]
 8002e70:	859a      	strh	r2, [r3, #44]	; 0x2c
    huart->RxXferCount = Size;
 8002e72:	68fb      	ldr	r3, [r7, #12]
 8002e74:	88fa      	ldrh	r2, [r7, #6]
 8002e76:	85da      	strh	r2, [r3, #46]	; 0x2e

    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
 8002e78:	68fb      	ldr	r3, [r7, #12]
 8002e7a:	689b      	ldr	r3, [r3, #8]
 8002e7c:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8002e80:	d108      	bne.n	8002e94 <HAL_UART_Receive+0x8a>
 8002e82:	68fb      	ldr	r3, [r7, #12]
 8002e84:	691b      	ldr	r3, [r3, #16]
 8002e86:	2b00      	cmp	r3, #0
 8002e88:	d104      	bne.n	8002e94 <HAL_UART_Receive+0x8a>
    {
      pdata8bits  = NULL;
 8002e8a:	2300      	movs	r3, #0
 8002e8c:	61fb      	str	r3, [r7, #28]
      pdata16bits = (uint16_t *) pData;
 8002e8e:	68bb      	ldr	r3, [r7, #8]
 8002e90:	61bb      	str	r3, [r7, #24]
 8002e92:	e003      	b.n	8002e9c <HAL_UART_Receive+0x92>
    }
    else
    {
      pdata8bits  = pData;
 8002e94:	68bb      	ldr	r3, [r7, #8]
 8002e96:	61fb      	str	r3, [r7, #28]
      pdata16bits = NULL;
 8002e98:	2300      	movs	r3, #0
 8002e9a:	61bb      	str	r3, [r7, #24]
    }

    /* Process Unlocked */
    __HAL_UNLOCK(huart);
 8002e9c:	68fb      	ldr	r3, [r7, #12]
 8002e9e:	2200      	movs	r2, #0
 8002ea0:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Check the remain data to be received */
    while (huart->RxXferCount > 0U)
 8002ea4:	e043      	b.n	8002f2e <HAL_UART_Receive+0x124>
    {
      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
 8002ea6:	683b      	ldr	r3, [r7, #0]
 8002ea8:	9300      	str	r3, [sp, #0]
 8002eaa:	697b      	ldr	r3, [r7, #20]
 8002eac:	2200      	movs	r2, #0
 8002eae:	2120      	movs	r1, #32
 8002eb0:	68f8      	ldr	r0, [r7, #12]
 8002eb2:	f000 f84c 	bl	8002f4e <UART_WaitOnFlagUntilTimeout>
 8002eb6:	4603      	mov	r3, r0
 8002eb8:	2b00      	cmp	r3, #0
 8002eba:	d001      	beq.n	8002ec0 <HAL_UART_Receive+0xb6>
      {
        return HAL_TIMEOUT;
 8002ebc:	2303      	movs	r3, #3
 8002ebe:	e042      	b.n	8002f46 <HAL_UART_Receive+0x13c>
      }
      if (pdata8bits == NULL)
 8002ec0:	69fb      	ldr	r3, [r7, #28]
 8002ec2:	2b00      	cmp	r3, #0
 8002ec4:	d10c      	bne.n	8002ee0 <HAL_UART_Receive+0xd6>
      {
        *pdata16bits = (uint16_t)(huart->Instance->DR & 0x01FF);
 8002ec6:	68fb      	ldr	r3, [r7, #12]
 8002ec8:	681b      	ldr	r3, [r3, #0]
 8002eca:	685b      	ldr	r3, [r3, #4]
 8002ecc:	b29b      	uxth	r3, r3
 8002ece:	f3c3 0308 	ubfx	r3, r3, #0, #9
 8002ed2:	b29a      	uxth	r2, r3
 8002ed4:	69bb      	ldr	r3, [r7, #24]
 8002ed6:	801a      	strh	r2, [r3, #0]
        pdata16bits++;
 8002ed8:	69bb      	ldr	r3, [r7, #24]
 8002eda:	3302      	adds	r3, #2
 8002edc:	61bb      	str	r3, [r7, #24]
 8002ede:	e01f      	b.n	8002f20 <HAL_UART_Receive+0x116>
      }
      else
      {
        if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE)))
 8002ee0:	68fb      	ldr	r3, [r7, #12]
 8002ee2:	689b      	ldr	r3, [r3, #8]
 8002ee4:	f5b3 5f80 	cmp.w	r3, #4096	; 0x1000
 8002ee8:	d007      	beq.n	8002efa <HAL_UART_Receive+0xf0>
 8002eea:	68fb      	ldr	r3, [r7, #12]
 8002eec:	689b      	ldr	r3, [r3, #8]
 8002eee:	2b00      	cmp	r3, #0
 8002ef0:	d10a      	bne.n	8002f08 <HAL_UART_Receive+0xfe>
 8002ef2:	68fb      	ldr	r3, [r7, #12]
 8002ef4:	691b      	ldr	r3, [r3, #16]
 8002ef6:	2b00      	cmp	r3, #0
 8002ef8:	d106      	bne.n	8002f08 <HAL_UART_Receive+0xfe>
        {
          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
 8002efa:	68fb      	ldr	r3, [r7, #12]
 8002efc:	681b      	ldr	r3, [r3, #0]
 8002efe:	685b      	ldr	r3, [r3, #4]
 8002f00:	b2da      	uxtb	r2, r3
 8002f02:	69fb      	ldr	r3, [r7, #28]
 8002f04:	701a      	strb	r2, [r3, #0]
 8002f06:	e008      	b.n	8002f1a <HAL_UART_Receive+0x110>
        }
        else
        {
          *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
 8002f08:	68fb      	ldr	r3, [r7, #12]
 8002f0a:	681b      	ldr	r3, [r3, #0]
 8002f0c:	685b      	ldr	r3, [r3, #4]
 8002f0e:	b2db      	uxtb	r3, r3
 8002f10:	f003 037f 	and.w	r3, r3, #127	; 0x7f
 8002f14:	b2da      	uxtb	r2, r3
 8002f16:	69fb      	ldr	r3, [r7, #28]
 8002f18:	701a      	strb	r2, [r3, #0]
        }
        pdata8bits++;
 8002f1a:	69fb      	ldr	r3, [r7, #28]
 8002f1c:	3301      	adds	r3, #1
 8002f1e:	61fb      	str	r3, [r7, #28]
      }
      huart->RxXferCount--;
 8002f20:	68fb      	ldr	r3, [r7, #12]
 8002f22:	8ddb      	ldrh	r3, [r3, #46]	; 0x2e
 8002f24:	b29b      	uxth	r3, r3
 8002f26:	3b01      	subs	r3, #1
 8002f28:	b29a      	uxth	r2, r3
 8002f2a:	68fb      	ldr	r3, [r7, #12]
 8002f2c:	85da      	strh	r2, [r3, #46]	; 0x2e
    while (huart->RxXferCount > 0U)
 8002f2e:	68fb      	ldr	r3, [r7, #12]
 8002f30:	8ddb      	ldrh	r3, [r3, #46]	; 0x2e
 8002f32:	b29b      	uxth	r3, r3
 8002f34:	2b00      	cmp	r3, #0
 8002f36:	d1b6      	bne.n	8002ea6 <HAL_UART_Receive+0x9c>
    }

    /* At end of Rx process, restore huart->RxState to Ready */
    huart->RxState = HAL_UART_STATE_READY;
 8002f38:	68fb      	ldr	r3, [r7, #12]
 8002f3a:	2220      	movs	r2, #32
 8002f3c:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

    return HAL_OK;
 8002f40:	2300      	movs	r3, #0
 8002f42:	e000      	b.n	8002f46 <HAL_UART_Receive+0x13c>
  }
  else
  {
    return HAL_BUSY;
 8002f44:	2302      	movs	r3, #2
  }
}
 8002f46:	4618      	mov	r0, r3
 8002f48:	3720      	adds	r7, #32
 8002f4a:	46bd      	mov	sp, r7
 8002f4c:	bd80      	pop	{r7, pc}

08002f4e <UART_WaitOnFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
                                                     uint32_t Tickstart, uint32_t Timeout)
{
 8002f4e:	b580      	push	{r7, lr}
 8002f50:	b090      	sub	sp, #64	; 0x40
 8002f52:	af00      	add	r7, sp, #0
 8002f54:	60f8      	str	r0, [r7, #12]
 8002f56:	60b9      	str	r1, [r7, #8]
 8002f58:	603b      	str	r3, [r7, #0]
 8002f5a:	4613      	mov	r3, r2
 8002f5c:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8002f5e:	e050      	b.n	8003002 <UART_WaitOnFlagUntilTimeout+0xb4>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8002f60:	6cbb      	ldr	r3, [r7, #72]	; 0x48
 8002f62:	f1b3 3fff 	cmp.w	r3, #4294967295
 8002f66:	d04c      	beq.n	8003002 <UART_WaitOnFlagUntilTimeout+0xb4>
    {
      if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
 8002f68:	6cbb      	ldr	r3, [r7, #72]	; 0x48
 8002f6a:	2b00      	cmp	r3, #0
 8002f6c:	d007      	beq.n	8002f7e <UART_WaitOnFlagUntilTimeout+0x30>
 8002f6e:	f7fe f813 	bl	8000f98 <HAL_GetTick>
 8002f72:	4602      	mov	r2, r0
 8002f74:	683b      	ldr	r3, [r7, #0]
 8002f76:	1ad3      	subs	r3, r2, r3
 8002f78:	6cba      	ldr	r2, [r7, #72]	; 0x48
 8002f7a:	429a      	cmp	r2, r3
 8002f7c:	d241      	bcs.n	8003002 <UART_WaitOnFlagUntilTimeout+0xb4>
      {
        /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE));
 8002f7e:	68fb      	ldr	r3, [r7, #12]
 8002f80:	681b      	ldr	r3, [r3, #0]
 8002f82:	330c      	adds	r3, #12
 8002f84:	62bb      	str	r3, [r7, #40]	; 0x28
 */
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
    uint32_t result;

   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002f86:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8002f88:	e853 3f00 	ldrex	r3, [r3]
 8002f8c:	627b      	str	r3, [r7, #36]	; 0x24
   return(result);
 8002f8e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8002f90:	f423 73d0 	bic.w	r3, r3, #416	; 0x1a0
 8002f94:	63fb      	str	r3, [r7, #60]	; 0x3c
 8002f96:	68fb      	ldr	r3, [r7, #12]
 8002f98:	681b      	ldr	r3, [r3, #0]
 8002f9a:	330c      	adds	r3, #12
 8002f9c:	6bfa      	ldr	r2, [r7, #60]	; 0x3c
 8002f9e:	637a      	str	r2, [r7, #52]	; 0x34
 8002fa0:	633b      	str	r3, [r7, #48]	; 0x30
 */
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
   uint32_t result;

   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002fa2:	6b39      	ldr	r1, [r7, #48]	; 0x30
 8002fa4:	6b7a      	ldr	r2, [r7, #52]	; 0x34
 8002fa6:	e841 2300 	strex	r3, r2, [r1]
 8002faa:	62fb      	str	r3, [r7, #44]	; 0x2c
   return(result);
 8002fac:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8002fae:	2b00      	cmp	r3, #0
 8002fb0:	d1e5      	bne.n	8002f7e <UART_WaitOnFlagUntilTimeout+0x30>
        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
 8002fb2:	68fb      	ldr	r3, [r7, #12]
 8002fb4:	681b      	ldr	r3, [r3, #0]
 8002fb6:	3314      	adds	r3, #20
 8002fb8:	617b      	str	r3, [r7, #20]
   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
 8002fba:	697b      	ldr	r3, [r7, #20]
 8002fbc:	e853 3f00 	ldrex	r3, [r3]
 8002fc0:	613b      	str	r3, [r7, #16]
   return(result);
 8002fc2:	693b      	ldr	r3, [r7, #16]
 8002fc4:	f023 0301 	bic.w	r3, r3, #1
 8002fc8:	63bb      	str	r3, [r7, #56]	; 0x38
 8002fca:	68fb      	ldr	r3, [r7, #12]
 8002fcc:	681b      	ldr	r3, [r3, #0]
 8002fce:	3314      	adds	r3, #20
 8002fd0:	6bba      	ldr	r2, [r7, #56]	; 0x38
 8002fd2:	623a      	str	r2, [r7, #32]
 8002fd4:	61fb      	str	r3, [r7, #28]
   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
 8002fd6:	69f9      	ldr	r1, [r7, #28]
 8002fd8:	6a3a      	ldr	r2, [r7, #32]
 8002fda:	e841 2300 	strex	r3, r2, [r1]
 8002fde:	61bb      	str	r3, [r7, #24]
   return(result);
 8002fe0:	69bb      	ldr	r3, [r7, #24]
 8002fe2:	2b00      	cmp	r3, #0
 8002fe4:	d1e5      	bne.n	8002fb2 <UART_WaitOnFlagUntilTimeout+0x64>

        huart->gState  = HAL_UART_STATE_READY;
 8002fe6:	68fb      	ldr	r3, [r7, #12]
 8002fe8:	2220      	movs	r2, #32
 8002fea:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
        huart->RxState = HAL_UART_STATE_READY;
 8002fee:	68fb      	ldr	r3, [r7, #12]
 8002ff0:	2220      	movs	r2, #32
 8002ff2:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

        /* Process Unlocked */
        __HAL_UNLOCK(huart);
 8002ff6:	68fb      	ldr	r3, [r7, #12]
 8002ff8:	2200      	movs	r2, #0
 8002ffa:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

        return HAL_TIMEOUT;
 8002ffe:	2303      	movs	r3, #3
 8003000:	e00f      	b.n	8003022 <UART_WaitOnFlagUntilTimeout+0xd4>
  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
 8003002:	68fb      	ldr	r3, [r7, #12]
 8003004:	681b      	ldr	r3, [r3, #0]
 8003006:	681a      	ldr	r2, [r3, #0]
 8003008:	68bb      	ldr	r3, [r7, #8]
 800300a:	4013      	ands	r3, r2
 800300c:	68ba      	ldr	r2, [r7, #8]
 800300e:	429a      	cmp	r2, r3
 8003010:	bf0c      	ite	eq
 8003012:	2301      	moveq	r3, #1
 8003014:	2300      	movne	r3, #0
 8003016:	b2db      	uxtb	r3, r3
 8003018:	461a      	mov	r2, r3
 800301a:	79fb      	ldrb	r3, [r7, #7]
 800301c:	429a      	cmp	r2, r3
 800301e:	d09f      	beq.n	8002f60 <UART_WaitOnFlagUntilTimeout+0x12>
      }
    }
  }
  return HAL_OK;
 8003020:	2300      	movs	r3, #0
}
 8003022:	4618      	mov	r0, r3
 8003024:	3740      	adds	r7, #64	; 0x40
 8003026:	46bd      	mov	sp, r7
 8003028:	bd80      	pop	{r7, pc}
	...

0800302c <UART_SetConfig>:
  * @param  huart  Pointer to a UART_HandleTypeDef structure that contains
  *                the configuration information for the specified UART module.
  * @retval None
  */
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
 800302c:	e92d 4fb0 	stmdb	sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
 8003030:	b0c0      	sub	sp, #256	; 0x100
 8003032:	af00      	add	r7, sp, #0
 8003034:	f8c7 00f4 	str.w	r0, [r7, #244]	; 0xf4
  assert_param(IS_UART_MODE(huart->Init.Mode));

  /*-------------------------- USART CR2 Configuration -----------------------*/
  /* Configure the UART Stop Bits: Set STOP[13:12] bits
     according to huart->Init.StopBits value */
  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
 8003038:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 800303c:	681b      	ldr	r3, [r3, #0]
 800303e:	691b      	ldr	r3, [r3, #16]
 8003040:	f423 5040 	bic.w	r0, r3, #12288	; 0x3000
 8003044:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8003048:	68d9      	ldr	r1, [r3, #12]
 800304a:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 800304e:	681a      	ldr	r2, [r3, #0]
 8003050:	ea40 0301 	orr.w	r3, r0, r1
 8003054:	6113      	str	r3, [r2, #16]
     Set the M bits according to huart->Init.WordLength value
     Set PCE and PS bits according to huart->Init.Parity value
     Set TE and RE bits according to huart->Init.Mode value
     Set OVER8 bit according to huart->Init.OverSampling value */

  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
 8003056:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 800305a:	689a      	ldr	r2, [r3, #8]
 800305c:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8003060:	691b      	ldr	r3, [r3, #16]
 8003062:	431a      	orrs	r2, r3
 8003064:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8003068:	695b      	ldr	r3, [r3, #20]
 800306a:	431a      	orrs	r2, r3
 800306c:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 8003070:	69db      	ldr	r3, [r3, #28]
 8003072:	4313      	orrs	r3, r2
 8003074:	f8c7 30f8 	str.w	r3, [r7, #248]	; 0xf8
  MODIFY_REG(huart->Instance->CR1,
 8003078:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 800307c:	681b      	ldr	r3, [r3, #0]
 800307e:	68db      	ldr	r3, [r3, #12]
 8003080:	f423 4116 	bic.w	r1, r3, #38400	; 0x9600
 8003084:	f021 010c 	bic.w	r1, r1, #12
 8003088:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 800308c:	681a      	ldr	r2, [r3, #0]
 800308e:	f8d7 30f8 	ldr.w	r3, [r7, #248]	; 0xf8
 8003092:	430b      	orrs	r3, r1
 8003094:	60d3      	str	r3, [r2, #12]
             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
             tmpreg);

  /*-------------------------- USART CR3 Configuration -----------------------*/
  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
 8003096:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 800309a:	681b      	ldr	r3, [r3, #0]
 800309c:	695b      	ldr	r3, [r3, #20]
 800309e:	f423 7040 	bic.w	r0, r3, #768	; 0x300
 80030a2:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80030a6:	6999      	ldr	r1, [r3, #24]
 80030a8:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80030ac:	681a      	ldr	r2, [r3, #0]
 80030ae:	ea40 0301 	orr.w	r3, r0, r1
 80030b2:	6153      	str	r3, [r2, #20]
    if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
    {
      pclk = HAL_RCC_GetPCLK2Freq();
    }
#elif defined(USART6)
    if ((huart->Instance == USART1) || (huart->Instance == USART6))
 80030b4:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80030b8:	681a      	ldr	r2, [r3, #0]
 80030ba:	4b8f      	ldr	r3, [pc, #572]	; (80032f8 <UART_SetConfig+0x2cc>)
 80030bc:	429a      	cmp	r2, r3
 80030be:	d005      	beq.n	80030cc <UART_SetConfig+0xa0>
 80030c0:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80030c4:	681a      	ldr	r2, [r3, #0]
 80030c6:	4b8d      	ldr	r3, [pc, #564]	; (80032fc <UART_SetConfig+0x2d0>)
 80030c8:	429a      	cmp	r2, r3
 80030ca:	d104      	bne.n	80030d6 <UART_SetConfig+0xaa>
    {
      pclk = HAL_RCC_GetPCLK2Freq();
 80030cc:	f7ff faf8 	bl	80026c0 <HAL_RCC_GetPCLK2Freq>
 80030d0:	f8c7 00fc 	str.w	r0, [r7, #252]	; 0xfc
 80030d4:	e003      	b.n	80030de <UART_SetConfig+0xb2>
      pclk = HAL_RCC_GetPCLK2Freq();
    }
#endif /* USART6 */
    else
    {
      pclk = HAL_RCC_GetPCLK1Freq();
 80030d6:	f7ff fadf 	bl	8002698 <HAL_RCC_GetPCLK1Freq>
 80030da:	f8c7 00fc 	str.w	r0, [r7, #252]	; 0xfc
    }
  /*-------------------------- USART BRR Configuration ---------------------*/
  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
 80030de:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80030e2:	69db      	ldr	r3, [r3, #28]
 80030e4:	f5b3 4f00 	cmp.w	r3, #32768	; 0x8000
 80030e8:	f040 810c 	bne.w	8003304 <UART_SetConfig+0x2d8>
  {
    huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
 80030ec:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 80030f0:	2200      	movs	r2, #0
 80030f2:	f8c7 30e8 	str.w	r3, [r7, #232]	; 0xe8
 80030f6:	f8c7 20ec 	str.w	r2, [r7, #236]	; 0xec
 80030fa:	e9d7 453a 	ldrd	r4, r5, [r7, #232]	; 0xe8
 80030fe:	4622      	mov	r2, r4
 8003100:	462b      	mov	r3, r5
 8003102:	1891      	adds	r1, r2, r2
 8003104:	65b9      	str	r1, [r7, #88]	; 0x58
 8003106:	415b      	adcs	r3, r3
 8003108:	65fb      	str	r3, [r7, #92]	; 0x5c
 800310a:	e9d7 2316 	ldrd	r2, r3, [r7, #88]	; 0x58
 800310e:	4621      	mov	r1, r4
 8003110:	eb12 0801 	adds.w	r8, r2, r1
 8003114:	4629      	mov	r1, r5
 8003116:	eb43 0901 	adc.w	r9, r3, r1
 800311a:	f04f 0200 	mov.w	r2, #0
 800311e:	f04f 0300 	mov.w	r3, #0
 8003122:	ea4f 03c9 	mov.w	r3, r9, lsl #3
 8003126:	ea43 7358 	orr.w	r3, r3, r8, lsr #29
 800312a:	ea4f 02c8 	mov.w	r2, r8, lsl #3
 800312e:	4690      	mov	r8, r2
 8003130:	4699      	mov	r9, r3
 8003132:	4623      	mov	r3, r4
 8003134:	eb18 0303 	adds.w	r3, r8, r3
 8003138:	f8c7 30e0 	str.w	r3, [r7, #224]	; 0xe0
 800313c:	462b      	mov	r3, r5
 800313e:	eb49 0303 	adc.w	r3, r9, r3
 8003142:	f8c7 30e4 	str.w	r3, [r7, #228]	; 0xe4
 8003146:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 800314a:	685b      	ldr	r3, [r3, #4]
 800314c:	2200      	movs	r2, #0
 800314e:	f8c7 30d8 	str.w	r3, [r7, #216]	; 0xd8
 8003152:	f8c7 20dc 	str.w	r2, [r7, #220]	; 0xdc
 8003156:	e9d7 1236 	ldrd	r1, r2, [r7, #216]	; 0xd8
 800315a:	460b      	mov	r3, r1
 800315c:	18db      	adds	r3, r3, r3
 800315e:	653b      	str	r3, [r7, #80]	; 0x50
 8003160:	4613      	mov	r3, r2
 8003162:	eb42 0303 	adc.w	r3, r2, r3
 8003166:	657b      	str	r3, [r7, #84]	; 0x54
 8003168:	e9d7 2314 	ldrd	r2, r3, [r7, #80]	; 0x50
 800316c:	e9d7 0138 	ldrd	r0, r1, [r7, #224]	; 0xe0
 8003170:	f7fd f836 	bl	80001e0 <__aeabi_uldivmod>
 8003174:	4602      	mov	r2, r0
 8003176:	460b      	mov	r3, r1
 8003178:	4b61      	ldr	r3, [pc, #388]	; (8003300 <UART_SetConfig+0x2d4>)
 800317a:	fba3 2302 	umull	r2, r3, r3, r2
 800317e:	095b      	lsrs	r3, r3, #5
 8003180:	011c      	lsls	r4, r3, #4
 8003182:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 8003186:	2200      	movs	r2, #0
 8003188:	f8c7 30d0 	str.w	r3, [r7, #208]	; 0xd0
 800318c:	f8c7 20d4 	str.w	r2, [r7, #212]	; 0xd4
 8003190:	e9d7 8934 	ldrd	r8, r9, [r7, #208]	; 0xd0
 8003194:	4642      	mov	r2, r8
 8003196:	464b      	mov	r3, r9
 8003198:	1891      	adds	r1, r2, r2
 800319a:	64b9      	str	r1, [r7, #72]	; 0x48
 800319c:	415b      	adcs	r3, r3
 800319e:	64fb      	str	r3, [r7, #76]	; 0x4c
 80031a0:	e9d7 2312 	ldrd	r2, r3, [r7, #72]	; 0x48
 80031a4:	4641      	mov	r1, r8
 80031a6:	eb12 0a01 	adds.w	sl, r2, r1
 80031aa:	4649      	mov	r1, r9
 80031ac:	eb43 0b01 	adc.w	fp, r3, r1
 80031b0:	f04f 0200 	mov.w	r2, #0
 80031b4:	f04f 0300 	mov.w	r3, #0
 80031b8:	ea4f 03cb 	mov.w	r3, fp, lsl #3
 80031bc:	ea43 735a 	orr.w	r3, r3, sl, lsr #29
 80031c0:	ea4f 02ca 	mov.w	r2, sl, lsl #3
 80031c4:	4692      	mov	sl, r2
 80031c6:	469b      	mov	fp, r3
 80031c8:	4643      	mov	r3, r8
 80031ca:	eb1a 0303 	adds.w	r3, sl, r3
 80031ce:	f8c7 30c8 	str.w	r3, [r7, #200]	; 0xc8
 80031d2:	464b      	mov	r3, r9
 80031d4:	eb4b 0303 	adc.w	r3, fp, r3
 80031d8:	f8c7 30cc 	str.w	r3, [r7, #204]	; 0xcc
 80031dc:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80031e0:	685b      	ldr	r3, [r3, #4]
 80031e2:	2200      	movs	r2, #0
 80031e4:	f8c7 30c0 	str.w	r3, [r7, #192]	; 0xc0
 80031e8:	f8c7 20c4 	str.w	r2, [r7, #196]	; 0xc4
 80031ec:	e9d7 1230 	ldrd	r1, r2, [r7, #192]	; 0xc0
 80031f0:	460b      	mov	r3, r1
 80031f2:	18db      	adds	r3, r3, r3
 80031f4:	643b      	str	r3, [r7, #64]	; 0x40
 80031f6:	4613      	mov	r3, r2
 80031f8:	eb42 0303 	adc.w	r3, r2, r3
 80031fc:	647b      	str	r3, [r7, #68]	; 0x44
 80031fe:	e9d7 2310 	ldrd	r2, r3, [r7, #64]	; 0x40
 8003202:	e9d7 0132 	ldrd	r0, r1, [r7, #200]	; 0xc8
 8003206:	f7fc ffeb 	bl	80001e0 <__aeabi_uldivmod>
 800320a:	4602      	mov	r2, r0
 800320c:	460b      	mov	r3, r1
 800320e:	4611      	mov	r1, r2
 8003210:	4b3b      	ldr	r3, [pc, #236]	; (8003300 <UART_SetConfig+0x2d4>)
 8003212:	fba3 2301 	umull	r2, r3, r3, r1
 8003216:	095b      	lsrs	r3, r3, #5
 8003218:	2264      	movs	r2, #100	; 0x64
 800321a:	fb02 f303 	mul.w	r3, r2, r3
 800321e:	1acb      	subs	r3, r1, r3
 8003220:	00db      	lsls	r3, r3, #3
 8003222:	f103 0232 	add.w	r2, r3, #50	; 0x32
 8003226:	4b36      	ldr	r3, [pc, #216]	; (8003300 <UART_SetConfig+0x2d4>)
 8003228:	fba3 2302 	umull	r2, r3, r3, r2
 800322c:	095b      	lsrs	r3, r3, #5
 800322e:	005b      	lsls	r3, r3, #1
 8003230:	f403 73f8 	and.w	r3, r3, #496	; 0x1f0
 8003234:	441c      	add	r4, r3
 8003236:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 800323a:	2200      	movs	r2, #0
 800323c:	f8c7 30b8 	str.w	r3, [r7, #184]	; 0xb8
 8003240:	f8c7 20bc 	str.w	r2, [r7, #188]	; 0xbc
 8003244:	e9d7 892e 	ldrd	r8, r9, [r7, #184]	; 0xb8
 8003248:	4642      	mov	r2, r8
 800324a:	464b      	mov	r3, r9
 800324c:	1891      	adds	r1, r2, r2
 800324e:	63b9      	str	r1, [r7, #56]	; 0x38
 8003250:	415b      	adcs	r3, r3
 8003252:	63fb      	str	r3, [r7, #60]	; 0x3c
 8003254:	e9d7 230e 	ldrd	r2, r3, [r7, #56]	; 0x38
 8003258:	4641      	mov	r1, r8
 800325a:	1851      	adds	r1, r2, r1
 800325c:	6339      	str	r1, [r7, #48]	; 0x30
 800325e:	4649      	mov	r1, r9
 8003260:	414b      	adcs	r3, r1
 8003262:	637b      	str	r3, [r7, #52]	; 0x34
 8003264:	f04f 0200 	mov.w	r2, #0
 8003268:	f04f 0300 	mov.w	r3, #0
 800326c:	e9d7 ab0c 	ldrd	sl, fp, [r7, #48]	; 0x30
 8003270:	4659      	mov	r1, fp
 8003272:	00cb      	lsls	r3, r1, #3
 8003274:	4651      	mov	r1, sl
 8003276:	ea43 7351 	orr.w	r3, r3, r1, lsr #29
 800327a:	4651      	mov	r1, sl
 800327c:	00ca      	lsls	r2, r1, #3
 800327e:	4610      	mov	r0, r2
 8003280:	4619      	mov	r1, r3
 8003282:	4603      	mov	r3, r0
 8003284:	4642      	mov	r2, r8
 8003286:	189b      	adds	r3, r3, r2
 8003288:	f8c7 30b0 	str.w	r3, [r7, #176]	; 0xb0
 800328c:	464b      	mov	r3, r9
 800328e:	460a      	mov	r2, r1
 8003290:	eb42 0303 	adc.w	r3, r2, r3
 8003294:	f8c7 30b4 	str.w	r3, [r7, #180]	; 0xb4
 8003298:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 800329c:	685b      	ldr	r3, [r3, #4]
 800329e:	2200      	movs	r2, #0
 80032a0:	f8c7 30a8 	str.w	r3, [r7, #168]	; 0xa8
 80032a4:	f8c7 20ac 	str.w	r2, [r7, #172]	; 0xac
 80032a8:	e9d7 122a 	ldrd	r1, r2, [r7, #168]	; 0xa8
 80032ac:	460b      	mov	r3, r1
 80032ae:	18db      	adds	r3, r3, r3
 80032b0:	62bb      	str	r3, [r7, #40]	; 0x28
 80032b2:	4613      	mov	r3, r2
 80032b4:	eb42 0303 	adc.w	r3, r2, r3
 80032b8:	62fb      	str	r3, [r7, #44]	; 0x2c
 80032ba:	e9d7 230a 	ldrd	r2, r3, [r7, #40]	; 0x28
 80032be:	e9d7 012c 	ldrd	r0, r1, [r7, #176]	; 0xb0
 80032c2:	f7fc ff8d 	bl	80001e0 <__aeabi_uldivmod>
 80032c6:	4602      	mov	r2, r0
 80032c8:	460b      	mov	r3, r1
 80032ca:	4b0d      	ldr	r3, [pc, #52]	; (8003300 <UART_SetConfig+0x2d4>)
 80032cc:	fba3 1302 	umull	r1, r3, r3, r2
 80032d0:	095b      	lsrs	r3, r3, #5
 80032d2:	2164      	movs	r1, #100	; 0x64
 80032d4:	fb01 f303 	mul.w	r3, r1, r3
 80032d8:	1ad3      	subs	r3, r2, r3
 80032da:	00db      	lsls	r3, r3, #3
 80032dc:	3332      	adds	r3, #50	; 0x32
 80032de:	4a08      	ldr	r2, [pc, #32]	; (8003300 <UART_SetConfig+0x2d4>)
 80032e0:	fba2 2303 	umull	r2, r3, r2, r3
 80032e4:	095b      	lsrs	r3, r3, #5
 80032e6:	f003 0207 	and.w	r2, r3, #7
 80032ea:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80032ee:	681b      	ldr	r3, [r3, #0]
 80032f0:	4422      	add	r2, r4
 80032f2:	609a      	str	r2, [r3, #8]
  }
  else
  {
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
  }
}
 80032f4:	e106      	b.n	8003504 <UART_SetConfig+0x4d8>
 80032f6:	bf00      	nop
 80032f8:	40011000 	.word	0x40011000
 80032fc:	40011400 	.word	0x40011400
 8003300:	51eb851f 	.word	0x51eb851f
    huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
 8003304:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 8003308:	2200      	movs	r2, #0
 800330a:	f8c7 30a0 	str.w	r3, [r7, #160]	; 0xa0
 800330e:	f8c7 20a4 	str.w	r2, [r7, #164]	; 0xa4
 8003312:	e9d7 8928 	ldrd	r8, r9, [r7, #160]	; 0xa0
 8003316:	4642      	mov	r2, r8
 8003318:	464b      	mov	r3, r9
 800331a:	1891      	adds	r1, r2, r2
 800331c:	6239      	str	r1, [r7, #32]
 800331e:	415b      	adcs	r3, r3
 8003320:	627b      	str	r3, [r7, #36]	; 0x24
 8003322:	e9d7 2308 	ldrd	r2, r3, [r7, #32]
 8003326:	4641      	mov	r1, r8
 8003328:	1854      	adds	r4, r2, r1
 800332a:	4649      	mov	r1, r9
 800332c:	eb43 0501 	adc.w	r5, r3, r1
 8003330:	f04f 0200 	mov.w	r2, #0
 8003334:	f04f 0300 	mov.w	r3, #0
 8003338:	00eb      	lsls	r3, r5, #3
 800333a:	ea43 7354 	orr.w	r3, r3, r4, lsr #29
 800333e:	00e2      	lsls	r2, r4, #3
 8003340:	4614      	mov	r4, r2
 8003342:	461d      	mov	r5, r3
 8003344:	4643      	mov	r3, r8
 8003346:	18e3      	adds	r3, r4, r3
 8003348:	f8c7 3098 	str.w	r3, [r7, #152]	; 0x98
 800334c:	464b      	mov	r3, r9
 800334e:	eb45 0303 	adc.w	r3, r5, r3
 8003352:	f8c7 309c 	str.w	r3, [r7, #156]	; 0x9c
 8003356:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 800335a:	685b      	ldr	r3, [r3, #4]
 800335c:	2200      	movs	r2, #0
 800335e:	f8c7 3090 	str.w	r3, [r7, #144]	; 0x90
 8003362:	f8c7 2094 	str.w	r2, [r7, #148]	; 0x94
 8003366:	f04f 0200 	mov.w	r2, #0
 800336a:	f04f 0300 	mov.w	r3, #0
 800336e:	e9d7 4524 	ldrd	r4, r5, [r7, #144]	; 0x90
 8003372:	4629      	mov	r1, r5
 8003374:	008b      	lsls	r3, r1, #2
 8003376:	4621      	mov	r1, r4
 8003378:	ea43 7391 	orr.w	r3, r3, r1, lsr #30
 800337c:	4621      	mov	r1, r4
 800337e:	008a      	lsls	r2, r1, #2
 8003380:	e9d7 0126 	ldrd	r0, r1, [r7, #152]	; 0x98
 8003384:	f7fc ff2c 	bl	80001e0 <__aeabi_uldivmod>
 8003388:	4602      	mov	r2, r0
 800338a:	460b      	mov	r3, r1
 800338c:	4b60      	ldr	r3, [pc, #384]	; (8003510 <UART_SetConfig+0x4e4>)
 800338e:	fba3 2302 	umull	r2, r3, r3, r2
 8003392:	095b      	lsrs	r3, r3, #5
 8003394:	011c      	lsls	r4, r3, #4
 8003396:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 800339a:	2200      	movs	r2, #0
 800339c:	f8c7 3088 	str.w	r3, [r7, #136]	; 0x88
 80033a0:	f8c7 208c 	str.w	r2, [r7, #140]	; 0x8c
 80033a4:	e9d7 8922 	ldrd	r8, r9, [r7, #136]	; 0x88
 80033a8:	4642      	mov	r2, r8
 80033aa:	464b      	mov	r3, r9
 80033ac:	1891      	adds	r1, r2, r2
 80033ae:	61b9      	str	r1, [r7, #24]
 80033b0:	415b      	adcs	r3, r3
 80033b2:	61fb      	str	r3, [r7, #28]
 80033b4:	e9d7 2306 	ldrd	r2, r3, [r7, #24]
 80033b8:	4641      	mov	r1, r8
 80033ba:	1851      	adds	r1, r2, r1
 80033bc:	6139      	str	r1, [r7, #16]
 80033be:	4649      	mov	r1, r9
 80033c0:	414b      	adcs	r3, r1
 80033c2:	617b      	str	r3, [r7, #20]
 80033c4:	f04f 0200 	mov.w	r2, #0
 80033c8:	f04f 0300 	mov.w	r3, #0
 80033cc:	e9d7 ab04 	ldrd	sl, fp, [r7, #16]
 80033d0:	4659      	mov	r1, fp
 80033d2:	00cb      	lsls	r3, r1, #3
 80033d4:	4651      	mov	r1, sl
 80033d6:	ea43 7351 	orr.w	r3, r3, r1, lsr #29
 80033da:	4651      	mov	r1, sl
 80033dc:	00ca      	lsls	r2, r1, #3
 80033de:	4610      	mov	r0, r2
 80033e0:	4619      	mov	r1, r3
 80033e2:	4603      	mov	r3, r0
 80033e4:	4642      	mov	r2, r8
 80033e6:	189b      	adds	r3, r3, r2
 80033e8:	f8c7 3080 	str.w	r3, [r7, #128]	; 0x80
 80033ec:	464b      	mov	r3, r9
 80033ee:	460a      	mov	r2, r1
 80033f0:	eb42 0303 	adc.w	r3, r2, r3
 80033f4:	f8c7 3084 	str.w	r3, [r7, #132]	; 0x84
 80033f8:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80033fc:	685b      	ldr	r3, [r3, #4]
 80033fe:	2200      	movs	r2, #0
 8003400:	67bb      	str	r3, [r7, #120]	; 0x78
 8003402:	67fa      	str	r2, [r7, #124]	; 0x7c
 8003404:	f04f 0200 	mov.w	r2, #0
 8003408:	f04f 0300 	mov.w	r3, #0
 800340c:	e9d7 891e 	ldrd	r8, r9, [r7, #120]	; 0x78
 8003410:	4649      	mov	r1, r9
 8003412:	008b      	lsls	r3, r1, #2
 8003414:	4641      	mov	r1, r8
 8003416:	ea43 7391 	orr.w	r3, r3, r1, lsr #30
 800341a:	4641      	mov	r1, r8
 800341c:	008a      	lsls	r2, r1, #2
 800341e:	e9d7 0120 	ldrd	r0, r1, [r7, #128]	; 0x80
 8003422:	f7fc fedd 	bl	80001e0 <__aeabi_uldivmod>
 8003426:	4602      	mov	r2, r0
 8003428:	460b      	mov	r3, r1
 800342a:	4611      	mov	r1, r2
 800342c:	4b38      	ldr	r3, [pc, #224]	; (8003510 <UART_SetConfig+0x4e4>)
 800342e:	fba3 2301 	umull	r2, r3, r3, r1
 8003432:	095b      	lsrs	r3, r3, #5
 8003434:	2264      	movs	r2, #100	; 0x64
 8003436:	fb02 f303 	mul.w	r3, r2, r3
 800343a:	1acb      	subs	r3, r1, r3
 800343c:	011b      	lsls	r3, r3, #4
 800343e:	3332      	adds	r3, #50	; 0x32
 8003440:	4a33      	ldr	r2, [pc, #204]	; (8003510 <UART_SetConfig+0x4e4>)
 8003442:	fba2 2303 	umull	r2, r3, r2, r3
 8003446:	095b      	lsrs	r3, r3, #5
 8003448:	f003 03f0 	and.w	r3, r3, #240	; 0xf0
 800344c:	441c      	add	r4, r3
 800344e:	f8d7 30fc 	ldr.w	r3, [r7, #252]	; 0xfc
 8003452:	2200      	movs	r2, #0
 8003454:	673b      	str	r3, [r7, #112]	; 0x70
 8003456:	677a      	str	r2, [r7, #116]	; 0x74
 8003458:	e9d7 891c 	ldrd	r8, r9, [r7, #112]	; 0x70
 800345c:	4642      	mov	r2, r8
 800345e:	464b      	mov	r3, r9
 8003460:	1891      	adds	r1, r2, r2
 8003462:	60b9      	str	r1, [r7, #8]
 8003464:	415b      	adcs	r3, r3
 8003466:	60fb      	str	r3, [r7, #12]
 8003468:	e9d7 2302 	ldrd	r2, r3, [r7, #8]
 800346c:	4641      	mov	r1, r8
 800346e:	1851      	adds	r1, r2, r1
 8003470:	6039      	str	r1, [r7, #0]
 8003472:	4649      	mov	r1, r9
 8003474:	414b      	adcs	r3, r1
 8003476:	607b      	str	r3, [r7, #4]
 8003478:	f04f 0200 	mov.w	r2, #0
 800347c:	f04f 0300 	mov.w	r3, #0
 8003480:	e9d7 ab00 	ldrd	sl, fp, [r7]
 8003484:	4659      	mov	r1, fp
 8003486:	00cb      	lsls	r3, r1, #3
 8003488:	4651      	mov	r1, sl
 800348a:	ea43 7351 	orr.w	r3, r3, r1, lsr #29
 800348e:	4651      	mov	r1, sl
 8003490:	00ca      	lsls	r2, r1, #3
 8003492:	4610      	mov	r0, r2
 8003494:	4619      	mov	r1, r3
 8003496:	4603      	mov	r3, r0
 8003498:	4642      	mov	r2, r8
 800349a:	189b      	adds	r3, r3, r2
 800349c:	66bb      	str	r3, [r7, #104]	; 0x68
 800349e:	464b      	mov	r3, r9
 80034a0:	460a      	mov	r2, r1
 80034a2:	eb42 0303 	adc.w	r3, r2, r3
 80034a6:	66fb      	str	r3, [r7, #108]	; 0x6c
 80034a8:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80034ac:	685b      	ldr	r3, [r3, #4]
 80034ae:	2200      	movs	r2, #0
 80034b0:	663b      	str	r3, [r7, #96]	; 0x60
 80034b2:	667a      	str	r2, [r7, #100]	; 0x64
 80034b4:	f04f 0200 	mov.w	r2, #0
 80034b8:	f04f 0300 	mov.w	r3, #0
 80034bc:	e9d7 8918 	ldrd	r8, r9, [r7, #96]	; 0x60
 80034c0:	4649      	mov	r1, r9
 80034c2:	008b      	lsls	r3, r1, #2
 80034c4:	4641      	mov	r1, r8
 80034c6:	ea43 7391 	orr.w	r3, r3, r1, lsr #30
 80034ca:	4641      	mov	r1, r8
 80034cc:	008a      	lsls	r2, r1, #2
 80034ce:	e9d7 011a 	ldrd	r0, r1, [r7, #104]	; 0x68
 80034d2:	f7fc fe85 	bl	80001e0 <__aeabi_uldivmod>
 80034d6:	4602      	mov	r2, r0
 80034d8:	460b      	mov	r3, r1
 80034da:	4b0d      	ldr	r3, [pc, #52]	; (8003510 <UART_SetConfig+0x4e4>)
 80034dc:	fba3 1302 	umull	r1, r3, r3, r2
 80034e0:	095b      	lsrs	r3, r3, #5
 80034e2:	2164      	movs	r1, #100	; 0x64
 80034e4:	fb01 f303 	mul.w	r3, r1, r3
 80034e8:	1ad3      	subs	r3, r2, r3
 80034ea:	011b      	lsls	r3, r3, #4
 80034ec:	3332      	adds	r3, #50	; 0x32
 80034ee:	4a08      	ldr	r2, [pc, #32]	; (8003510 <UART_SetConfig+0x4e4>)
 80034f0:	fba2 2303 	umull	r2, r3, r2, r3
 80034f4:	095b      	lsrs	r3, r3, #5
 80034f6:	f003 020f 	and.w	r2, r3, #15
 80034fa:	f8d7 30f4 	ldr.w	r3, [r7, #244]	; 0xf4
 80034fe:	681b      	ldr	r3, [r3, #0]
 8003500:	4422      	add	r2, r4
 8003502:	609a      	str	r2, [r3, #8]
}
 8003504:	bf00      	nop
 8003506:	f507 7780 	add.w	r7, r7, #256	; 0x100
 800350a:	46bd      	mov	sp, r7
 800350c:	e8bd 8fb0 	ldmia.w	sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
 8003510:	51eb851f 	.word	0x51eb851f

08003514 <__NVIC_SetPriority>:
{
 8003514:	b480      	push	{r7}
 8003516:	b083      	sub	sp, #12
 8003518:	af00      	add	r7, sp, #0
 800351a:	4603      	mov	r3, r0
 800351c:	6039      	str	r1, [r7, #0]
 800351e:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8003520:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8003524:	2b00      	cmp	r3, #0
 8003526:	db0a      	blt.n	800353e <__NVIC_SetPriority+0x2a>
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8003528:	683b      	ldr	r3, [r7, #0]
 800352a:	b2da      	uxtb	r2, r3
 800352c:	490c      	ldr	r1, [pc, #48]	; (8003560 <__NVIC_SetPriority+0x4c>)
 800352e:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8003532:	0112      	lsls	r2, r2, #4
 8003534:	b2d2      	uxtb	r2, r2
 8003536:	440b      	add	r3, r1
 8003538:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
}
 800353c:	e00a      	b.n	8003554 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 800353e:	683b      	ldr	r3, [r7, #0]
 8003540:	b2da      	uxtb	r2, r3
 8003542:	4908      	ldr	r1, [pc, #32]	; (8003564 <__NVIC_SetPriority+0x50>)
 8003544:	79fb      	ldrb	r3, [r7, #7]
 8003546:	f003 030f 	and.w	r3, r3, #15
 800354a:	3b04      	subs	r3, #4
 800354c:	0112      	lsls	r2, r2, #4
 800354e:	b2d2      	uxtb	r2, r2
 8003550:	440b      	add	r3, r1
 8003552:	761a      	strb	r2, [r3, #24]
}
 8003554:	bf00      	nop
 8003556:	370c      	adds	r7, #12
 8003558:	46bd      	mov	sp, r7
 800355a:	f85d 7b04 	ldr.w	r7, [sp], #4
 800355e:	4770      	bx	lr
 8003560:	e000e100 	.word	0xe000e100
 8003564:	e000ed00 	.word	0xe000ed00

08003568 <SysTick_Handler>:

/*
  SysTick handler implementation that also clears overflow flag.
*/
#if (USE_CUSTOM_SYSTICK_HANDLER_IMPLEMENTATION == 0)
void SysTick_Handler (void) {
 8003568:	b580      	push	{r7, lr}
 800356a:	af00      	add	r7, sp, #0
  /* Clear overflow flag */
  SysTick->CTRL;
 800356c:	4b05      	ldr	r3, [pc, #20]	; (8003584 <SysTick_Handler+0x1c>)
 800356e:	681b      	ldr	r3, [r3, #0]

  if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED) {
 8003570:	f001 fd28 	bl	8004fc4 <xTaskGetSchedulerState>
 8003574:	4603      	mov	r3, r0
 8003576:	2b01      	cmp	r3, #1
 8003578:	d001      	beq.n	800357e <SysTick_Handler+0x16>
    /* Call tick handler */
    xPortSysTickHandler();
 800357a:	f002 fb0d 	bl	8005b98 <xPortSysTickHandler>
  }
}
 800357e:	bf00      	nop
 8003580:	bd80      	pop	{r7, pc}
 8003582:	bf00      	nop
 8003584:	e000e010 	.word	0xe000e010

08003588 <SVC_Setup>:
#endif /* SysTick */

/*
  Setup SVC to reset value.
*/
__STATIC_INLINE void SVC_Setup (void) {
 8003588:	b580      	push	{r7, lr}
 800358a:	af00      	add	r7, sp, #0
#if (__ARM_ARCH_7A__ == 0U)
  /* Service Call interrupt might be configured before kernel start     */
  /* and when its priority is lower or equal to BASEPRI, svc intruction */
  /* causes a Hard Fault.                                               */
  NVIC_SetPriority (SVCall_IRQ_NBR, 0U);
 800358c:	2100      	movs	r1, #0
 800358e:	f06f 0004 	mvn.w	r0, #4
 8003592:	f7ff ffbf 	bl	8003514 <__NVIC_SetPriority>
#endif
}
 8003596:	bf00      	nop
 8003598:	bd80      	pop	{r7, pc}
	...

0800359c <osKernelInitialize>:
static uint32_t OS_Tick_GetOverflow (void);
/* Get OS Tick interval */
static uint32_t OS_Tick_GetInterval (void);
/*---------------------------------------------------------------------------*/

osStatus_t osKernelInitialize (void) {
 800359c:	b480      	push	{r7}
 800359e:	b083      	sub	sp, #12
 80035a0:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 80035a2:	f3ef 8305 	mrs	r3, IPSR
 80035a6:	603b      	str	r3, [r7, #0]
  return(result);
 80035a8:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 80035aa:	2b00      	cmp	r3, #0
 80035ac:	d003      	beq.n	80035b6 <osKernelInitialize+0x1a>
    stat = osErrorISR;
 80035ae:	f06f 0305 	mvn.w	r3, #5
 80035b2:	607b      	str	r3, [r7, #4]
 80035b4:	e00c      	b.n	80035d0 <osKernelInitialize+0x34>
  }
  else {
    if (KernelState == osKernelInactive) {
 80035b6:	4b0a      	ldr	r3, [pc, #40]	; (80035e0 <osKernelInitialize+0x44>)
 80035b8:	681b      	ldr	r3, [r3, #0]
 80035ba:	2b00      	cmp	r3, #0
 80035bc:	d105      	bne.n	80035ca <osKernelInitialize+0x2e>
        EvrFreeRTOSSetup(0U);
      #endif
      #if defined(USE_FreeRTOS_HEAP_5) && (HEAP_5_REGION_SETUP == 1)
        vPortDefineHeapRegions (configHEAP_5_REGIONS);
      #endif
      KernelState = osKernelReady;
 80035be:	4b08      	ldr	r3, [pc, #32]	; (80035e0 <osKernelInitialize+0x44>)
 80035c0:	2201      	movs	r2, #1
 80035c2:	601a      	str	r2, [r3, #0]
      stat = osOK;
 80035c4:	2300      	movs	r3, #0
 80035c6:	607b      	str	r3, [r7, #4]
 80035c8:	e002      	b.n	80035d0 <osKernelInitialize+0x34>
    } else {
      stat = osError;
 80035ca:	f04f 33ff 	mov.w	r3, #4294967295
 80035ce:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 80035d0:	687b      	ldr	r3, [r7, #4]
}
 80035d2:	4618      	mov	r0, r3
 80035d4:	370c      	adds	r7, #12
 80035d6:	46bd      	mov	sp, r7
 80035d8:	f85d 7b04 	ldr.w	r7, [sp], #4
 80035dc:	4770      	bx	lr
 80035de:	bf00      	nop
 80035e0:	2000017c 	.word	0x2000017c

080035e4 <osKernelStart>:
  }

  return (state);
}

osStatus_t osKernelStart (void) {
 80035e4:	b580      	push	{r7, lr}
 80035e6:	b082      	sub	sp, #8
 80035e8:	af00      	add	r7, sp, #0
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 80035ea:	f3ef 8305 	mrs	r3, IPSR
 80035ee:	603b      	str	r3, [r7, #0]
  return(result);
 80035f0:	683b      	ldr	r3, [r7, #0]
  osStatus_t stat;

  if (IS_IRQ()) {
 80035f2:	2b00      	cmp	r3, #0
 80035f4:	d003      	beq.n	80035fe <osKernelStart+0x1a>
    stat = osErrorISR;
 80035f6:	f06f 0305 	mvn.w	r3, #5
 80035fa:	607b      	str	r3, [r7, #4]
 80035fc:	e010      	b.n	8003620 <osKernelStart+0x3c>
  }
  else {
    if (KernelState == osKernelReady) {
 80035fe:	4b0b      	ldr	r3, [pc, #44]	; (800362c <osKernelStart+0x48>)
 8003600:	681b      	ldr	r3, [r3, #0]
 8003602:	2b01      	cmp	r3, #1
 8003604:	d109      	bne.n	800361a <osKernelStart+0x36>
      /* Ensure SVC priority is at the reset value */
      SVC_Setup();
 8003606:	f7ff ffbf 	bl	8003588 <SVC_Setup>
      /* Change state to enable IRQ masking check */
      KernelState = osKernelRunning;
 800360a:	4b08      	ldr	r3, [pc, #32]	; (800362c <osKernelStart+0x48>)
 800360c:	2202      	movs	r2, #2
 800360e:	601a      	str	r2, [r3, #0]
      /* Start the kernel scheduler */
      vTaskStartScheduler();
 8003610:	f001 f87c 	bl	800470c <vTaskStartScheduler>
      stat = osOK;
 8003614:	2300      	movs	r3, #0
 8003616:	607b      	str	r3, [r7, #4]
 8003618:	e002      	b.n	8003620 <osKernelStart+0x3c>
    } else {
      stat = osError;
 800361a:	f04f 33ff 	mov.w	r3, #4294967295
 800361e:	607b      	str	r3, [r7, #4]
    }
  }

  return (stat);
 8003620:	687b      	ldr	r3, [r7, #4]
}
 8003622:	4618      	mov	r0, r3
 8003624:	3708      	adds	r7, #8
 8003626:	46bd      	mov	sp, r7
 8003628:	bd80      	pop	{r7, pc}
 800362a:	bf00      	nop
 800362c:	2000017c 	.word	0x2000017c

08003630 <osThreadNew>:
  return (configCPU_CLOCK_HZ);
}

/*---------------------------------------------------------------------------*/

osThreadId_t osThreadNew (osThreadFunc_t func, void *argument, const osThreadAttr_t *attr) {
 8003630:	b580      	push	{r7, lr}
 8003632:	b08e      	sub	sp, #56	; 0x38
 8003634:	af04      	add	r7, sp, #16
 8003636:	60f8      	str	r0, [r7, #12]
 8003638:	60b9      	str	r1, [r7, #8]
 800363a:	607a      	str	r2, [r7, #4]
  uint32_t stack;
  TaskHandle_t hTask;
  UBaseType_t prio;
  int32_t mem;

  hTask = NULL;
 800363c:	2300      	movs	r3, #0
 800363e:	613b      	str	r3, [r7, #16]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 8003640:	f3ef 8305 	mrs	r3, IPSR
 8003644:	617b      	str	r3, [r7, #20]
  return(result);
 8003646:	697b      	ldr	r3, [r7, #20]

  if (!IS_IRQ() && (func != NULL)) {
 8003648:	2b00      	cmp	r3, #0
 800364a:	d17e      	bne.n	800374a <osThreadNew+0x11a>
 800364c:	68fb      	ldr	r3, [r7, #12]
 800364e:	2b00      	cmp	r3, #0
 8003650:	d07b      	beq.n	800374a <osThreadNew+0x11a>
    stack = configMINIMAL_STACK_SIZE;
 8003652:	2380      	movs	r3, #128	; 0x80
 8003654:	623b      	str	r3, [r7, #32]
    prio  = (UBaseType_t)osPriorityNormal;
 8003656:	2318      	movs	r3, #24
 8003658:	61fb      	str	r3, [r7, #28]

    name = NULL;
 800365a:	2300      	movs	r3, #0
 800365c:	627b      	str	r3, [r7, #36]	; 0x24
    mem  = -1;
 800365e:	f04f 33ff 	mov.w	r3, #4294967295
 8003662:	61bb      	str	r3, [r7, #24]

    if (attr != NULL) {
 8003664:	687b      	ldr	r3, [r7, #4]
 8003666:	2b00      	cmp	r3, #0
 8003668:	d045      	beq.n	80036f6 <osThreadNew+0xc6>
      if (attr->name != NULL) {
 800366a:	687b      	ldr	r3, [r7, #4]
 800366c:	681b      	ldr	r3, [r3, #0]
 800366e:	2b00      	cmp	r3, #0
 8003670:	d002      	beq.n	8003678 <osThreadNew+0x48>
        name = attr->name;
 8003672:	687b      	ldr	r3, [r7, #4]
 8003674:	681b      	ldr	r3, [r3, #0]
 8003676:	627b      	str	r3, [r7, #36]	; 0x24
      }
      if (attr->priority != osPriorityNone) {
 8003678:	687b      	ldr	r3, [r7, #4]
 800367a:	699b      	ldr	r3, [r3, #24]
 800367c:	2b00      	cmp	r3, #0
 800367e:	d002      	beq.n	8003686 <osThreadNew+0x56>
        prio = (UBaseType_t)attr->priority;
 8003680:	687b      	ldr	r3, [r7, #4]
 8003682:	699b      	ldr	r3, [r3, #24]
 8003684:	61fb      	str	r3, [r7, #28]
      }

      if ((prio < osPriorityIdle) || (prio > osPriorityISR) || ((attr->attr_bits & osThreadJoinable) == osThreadJoinable)) {
 8003686:	69fb      	ldr	r3, [r7, #28]
 8003688:	2b00      	cmp	r3, #0
 800368a:	d008      	beq.n	800369e <osThreadNew+0x6e>
 800368c:	69fb      	ldr	r3, [r7, #28]
 800368e:	2b38      	cmp	r3, #56	; 0x38
 8003690:	d805      	bhi.n	800369e <osThreadNew+0x6e>
 8003692:	687b      	ldr	r3, [r7, #4]
 8003694:	685b      	ldr	r3, [r3, #4]
 8003696:	f003 0301 	and.w	r3, r3, #1
 800369a:	2b00      	cmp	r3, #0
 800369c:	d001      	beq.n	80036a2 <osThreadNew+0x72>
        return (NULL);
 800369e:	2300      	movs	r3, #0
 80036a0:	e054      	b.n	800374c <osThreadNew+0x11c>
      }

      if (attr->stack_size > 0U) {
 80036a2:	687b      	ldr	r3, [r7, #4]
 80036a4:	695b      	ldr	r3, [r3, #20]
 80036a6:	2b00      	cmp	r3, #0
 80036a8:	d003      	beq.n	80036b2 <osThreadNew+0x82>
        /* In FreeRTOS stack is not in bytes, but in sizeof(StackType_t) which is 4 on ARM ports.       */
        /* Stack size should be therefore 4 byte aligned in order to avoid division caused side effects */
        stack = attr->stack_size / sizeof(StackType_t);
 80036aa:	687b      	ldr	r3, [r7, #4]
 80036ac:	695b      	ldr	r3, [r3, #20]
 80036ae:	089b      	lsrs	r3, r3, #2
 80036b0:	623b      	str	r3, [r7, #32]
      }

      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 80036b2:	687b      	ldr	r3, [r7, #4]
 80036b4:	689b      	ldr	r3, [r3, #8]
 80036b6:	2b00      	cmp	r3, #0
 80036b8:	d00e      	beq.n	80036d8 <osThreadNew+0xa8>
 80036ba:	687b      	ldr	r3, [r7, #4]
 80036bc:	68db      	ldr	r3, [r3, #12]
 80036be:	2ba7      	cmp	r3, #167	; 0xa7
 80036c0:	d90a      	bls.n	80036d8 <osThreadNew+0xa8>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 80036c2:	687b      	ldr	r3, [r7, #4]
 80036c4:	691b      	ldr	r3, [r3, #16]
      if ((attr->cb_mem    != NULL) && (attr->cb_size    >= sizeof(StaticTask_t)) &&
 80036c6:	2b00      	cmp	r3, #0
 80036c8:	d006      	beq.n	80036d8 <osThreadNew+0xa8>
          (attr->stack_mem != NULL) && (attr->stack_size >  0U)) {
 80036ca:	687b      	ldr	r3, [r7, #4]
 80036cc:	695b      	ldr	r3, [r3, #20]
 80036ce:	2b00      	cmp	r3, #0
 80036d0:	d002      	beq.n	80036d8 <osThreadNew+0xa8>
        mem = 1;
 80036d2:	2301      	movs	r3, #1
 80036d4:	61bb      	str	r3, [r7, #24]
 80036d6:	e010      	b.n	80036fa <osThreadNew+0xca>
      }
      else {
        if ((attr->cb_mem == NULL) && (attr->cb_size == 0U) && (attr->stack_mem == NULL)) {
 80036d8:	687b      	ldr	r3, [r7, #4]
 80036da:	689b      	ldr	r3, [r3, #8]
 80036dc:	2b00      	cmp	r3, #0
 80036de:	d10c      	bne.n	80036fa <osThreadNew+0xca>
 80036e0:	687b      	ldr	r3, [r7, #4]
 80036e2:	68db      	ldr	r3, [r3, #12]
 80036e4:	2b00      	cmp	r3, #0
 80036e6:	d108      	bne.n	80036fa <osThreadNew+0xca>
 80036e8:	687b      	ldr	r3, [r7, #4]
 80036ea:	691b      	ldr	r3, [r3, #16]
 80036ec:	2b00      	cmp	r3, #0
 80036ee:	d104      	bne.n	80036fa <osThreadNew+0xca>
          mem = 0;
 80036f0:	2300      	movs	r3, #0
 80036f2:	61bb      	str	r3, [r7, #24]
 80036f4:	e001      	b.n	80036fa <osThreadNew+0xca>
        }
      }
    }
    else {
      mem = 0;
 80036f6:	2300      	movs	r3, #0
 80036f8:	61bb      	str	r3, [r7, #24]
    }

    if (mem == 1) {
 80036fa:	69bb      	ldr	r3, [r7, #24]
 80036fc:	2b01      	cmp	r3, #1
 80036fe:	d110      	bne.n	8003722 <osThreadNew+0xf2>
      #if (configSUPPORT_STATIC_ALLOCATION == 1)
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 8003700:	687b      	ldr	r3, [r7, #4]
 8003702:	691b      	ldr	r3, [r3, #16]
                                                                                      (StaticTask_t *)attr->cb_mem);
 8003704:	687a      	ldr	r2, [r7, #4]
 8003706:	6892      	ldr	r2, [r2, #8]
        hTask = xTaskCreateStatic ((TaskFunction_t)func, name, stack, argument, prio, (StackType_t  *)attr->stack_mem,
 8003708:	9202      	str	r2, [sp, #8]
 800370a:	9301      	str	r3, [sp, #4]
 800370c:	69fb      	ldr	r3, [r7, #28]
 800370e:	9300      	str	r3, [sp, #0]
 8003710:	68bb      	ldr	r3, [r7, #8]
 8003712:	6a3a      	ldr	r2, [r7, #32]
 8003714:	6a79      	ldr	r1, [r7, #36]	; 0x24
 8003716:	68f8      	ldr	r0, [r7, #12]
 8003718:	f000 fe0c 	bl	8004334 <xTaskCreateStatic>
 800371c:	4603      	mov	r3, r0
 800371e:	613b      	str	r3, [r7, #16]
 8003720:	e013      	b.n	800374a <osThreadNew+0x11a>
      #endif
    }
    else {
      if (mem == 0) {
 8003722:	69bb      	ldr	r3, [r7, #24]
 8003724:	2b00      	cmp	r3, #0
 8003726:	d110      	bne.n	800374a <osThreadNew+0x11a>
        #if (configSUPPORT_DYNAMIC_ALLOCATION == 1)
          if (xTaskCreate ((TaskFunction_t)func, name, (uint16_t)stack, argument, prio, &hTask) != pdPASS) {
 8003728:	6a3b      	ldr	r3, [r7, #32]
 800372a:	b29a      	uxth	r2, r3
 800372c:	f107 0310 	add.w	r3, r7, #16
 8003730:	9301      	str	r3, [sp, #4]
 8003732:	69fb      	ldr	r3, [r7, #28]
 8003734:	9300      	str	r3, [sp, #0]
 8003736:	68bb      	ldr	r3, [r7, #8]
 8003738:	6a79      	ldr	r1, [r7, #36]	; 0x24
 800373a:	68f8      	ldr	r0, [r7, #12]
 800373c:	f000 fe57 	bl	80043ee <xTaskCreate>
 8003740:	4603      	mov	r3, r0
 8003742:	2b01      	cmp	r3, #1
 8003744:	d001      	beq.n	800374a <osThreadNew+0x11a>
            hTask = NULL;
 8003746:	2300      	movs	r3, #0
 8003748:	613b      	str	r3, [r7, #16]
        #endif
      }
    }
  }

  return ((osThreadId_t)hTask);
 800374a:	693b      	ldr	r3, [r7, #16]
}
 800374c:	4618      	mov	r0, r3
 800374e:	3728      	adds	r7, #40	; 0x28
 8003750:	46bd      	mov	sp, r7
 8003752:	bd80      	pop	{r7, pc}

08003754 <osDelay>:
  /* Return flags before clearing */
  return (rflags);
}
#endif /* (configUSE_OS2_THREAD_FLAGS == 1) */

osStatus_t osDelay (uint32_t ticks) {
 8003754:	b580      	push	{r7, lr}
 8003756:	b084      	sub	sp, #16
 8003758:	af00      	add	r7, sp, #0
 800375a:	6078      	str	r0, [r7, #4]
  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
 800375c:	f3ef 8305 	mrs	r3, IPSR
 8003760:	60bb      	str	r3, [r7, #8]
  return(result);
 8003762:	68bb      	ldr	r3, [r7, #8]
  osStatus_t stat;

  if (IS_IRQ()) {
 8003764:	2b00      	cmp	r3, #0
 8003766:	d003      	beq.n	8003770 <osDelay+0x1c>
    stat = osErrorISR;
 8003768:	f06f 0305 	mvn.w	r3, #5
 800376c:	60fb      	str	r3, [r7, #12]
 800376e:	e007      	b.n	8003780 <osDelay+0x2c>
  }
  else {
    stat = osOK;
 8003770:	2300      	movs	r3, #0
 8003772:	60fb      	str	r3, [r7, #12]

    if (ticks != 0U) {
 8003774:	687b      	ldr	r3, [r7, #4]
 8003776:	2b00      	cmp	r3, #0
 8003778:	d002      	beq.n	8003780 <osDelay+0x2c>
      vTaskDelay(ticks);
 800377a:	6878      	ldr	r0, [r7, #4]
 800377c:	f000 ff92 	bl	80046a4 <vTaskDelay>
    }
  }

  return (stat);
 8003780:	68fb      	ldr	r3, [r7, #12]
}
 8003782:	4618      	mov	r0, r3
 8003784:	3710      	adds	r7, #16
 8003786:	46bd      	mov	sp, r7
 8003788:	bd80      	pop	{r7, pc}
	...

0800378c <vApplicationGetIdleTaskMemory>:

/*
  vApplicationGetIdleTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetIdleTaskMemory (StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize) {
 800378c:	b480      	push	{r7}
 800378e:	b085      	sub	sp, #20
 8003790:	af00      	add	r7, sp, #0
 8003792:	60f8      	str	r0, [r7, #12]
 8003794:	60b9      	str	r1, [r7, #8]
 8003796:	607a      	str	r2, [r7, #4]
  /* Idle task control block and stack */
  static StaticTask_t Idle_TCB;
  static StackType_t  Idle_Stack[configMINIMAL_STACK_SIZE];

  *ppxIdleTaskTCBBuffer   = &Idle_TCB;
 8003798:	68fb      	ldr	r3, [r7, #12]
 800379a:	4a07      	ldr	r2, [pc, #28]	; (80037b8 <vApplicationGetIdleTaskMemory+0x2c>)
 800379c:	601a      	str	r2, [r3, #0]
  *ppxIdleTaskStackBuffer = &Idle_Stack[0];
 800379e:	68bb      	ldr	r3, [r7, #8]
 80037a0:	4a06      	ldr	r2, [pc, #24]	; (80037bc <vApplicationGetIdleTaskMemory+0x30>)
 80037a2:	601a      	str	r2, [r3, #0]
  *pulIdleTaskStackSize   = (uint32_t)configMINIMAL_STACK_SIZE;
 80037a4:	687b      	ldr	r3, [r7, #4]
 80037a6:	2280      	movs	r2, #128	; 0x80
 80037a8:	601a      	str	r2, [r3, #0]
}
 80037aa:	bf00      	nop
 80037ac:	3714      	adds	r7, #20
 80037ae:	46bd      	mov	sp, r7
 80037b0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80037b4:	4770      	bx	lr
 80037b6:	bf00      	nop
 80037b8:	20000180 	.word	0x20000180
 80037bc:	20000228 	.word	0x20000228

080037c0 <vApplicationGetTimerTaskMemory>:

/*
  vApplicationGetTimerTaskMemory gets called when configSUPPORT_STATIC_ALLOCATION
  equals to 1 and is required for static memory allocation support.
*/
__WEAK void vApplicationGetTimerTaskMemory (StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize) {
 80037c0:	b480      	push	{r7}
 80037c2:	b085      	sub	sp, #20
 80037c4:	af00      	add	r7, sp, #0
 80037c6:	60f8      	str	r0, [r7, #12]
 80037c8:	60b9      	str	r1, [r7, #8]
 80037ca:	607a      	str	r2, [r7, #4]
  /* Timer task control block and stack */
  static StaticTask_t Timer_TCB;
  static StackType_t  Timer_Stack[configTIMER_TASK_STACK_DEPTH];

  *ppxTimerTaskTCBBuffer   = &Timer_TCB;
 80037cc:	68fb      	ldr	r3, [r7, #12]
 80037ce:	4a07      	ldr	r2, [pc, #28]	; (80037ec <vApplicationGetTimerTaskMemory+0x2c>)
 80037d0:	601a      	str	r2, [r3, #0]
  *ppxTimerTaskStackBuffer = &Timer_Stack[0];
 80037d2:	68bb      	ldr	r3, [r7, #8]
 80037d4:	4a06      	ldr	r2, [pc, #24]	; (80037f0 <vApplicationGetTimerTaskMemory+0x30>)
 80037d6:	601a      	str	r2, [r3, #0]
  *pulTimerTaskStackSize   = (uint32_t)configTIMER_TASK_STACK_DEPTH;
 80037d8:	687b      	ldr	r3, [r7, #4]
 80037da:	f44f 7280 	mov.w	r2, #256	; 0x100
 80037de:	601a      	str	r2, [r3, #0]
}
 80037e0:	bf00      	nop
 80037e2:	3714      	adds	r7, #20
 80037e4:	46bd      	mov	sp, r7
 80037e6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80037ea:	4770      	bx	lr
 80037ec:	20000428 	.word	0x20000428
 80037f0:	200004d0 	.word	0x200004d0

080037f4 <vListInitialise>:
/*-----------------------------------------------------------
 * PUBLIC LIST API documented in list.h
 *----------------------------------------------------------*/

void vListInitialise( List_t * const pxList )
{
 80037f4:	b480      	push	{r7}
 80037f6:	b083      	sub	sp, #12
 80037f8:	af00      	add	r7, sp, #0
 80037fa:	6078      	str	r0, [r7, #4]
	/* The list structure contains a list item which is used to mark the
	end of the list.  To initialise the list the list end is inserted
	as the only list entry. */
	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 80037fc:	687b      	ldr	r3, [r7, #4]
 80037fe:	f103 0208 	add.w	r2, r3, #8
 8003802:	687b      	ldr	r3, [r7, #4]
 8003804:	605a      	str	r2, [r3, #4]

	/* The list end value is the highest possible value in the list to
	ensure it remains at the end of the list. */
	pxList->xListEnd.xItemValue = portMAX_DELAY;
 8003806:	687b      	ldr	r3, [r7, #4]
 8003808:	f04f 32ff 	mov.w	r2, #4294967295
 800380c:	609a      	str	r2, [r3, #8]

	/* The list end next and previous pointers point to itself so we know
	when the list is empty. */
	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 800380e:	687b      	ldr	r3, [r7, #4]
 8003810:	f103 0208 	add.w	r2, r3, #8
 8003814:	687b      	ldr	r3, [r7, #4]
 8003816:	60da      	str	r2, [r3, #12]
	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
 8003818:	687b      	ldr	r3, [r7, #4]
 800381a:	f103 0208 	add.w	r2, r3, #8
 800381e:	687b      	ldr	r3, [r7, #4]
 8003820:	611a      	str	r2, [r3, #16]

	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
 8003822:	687b      	ldr	r3, [r7, #4]
 8003824:	2200      	movs	r2, #0
 8003826:	601a      	str	r2, [r3, #0]

	/* Write known values into the list if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
}
 8003828:	bf00      	nop
 800382a:	370c      	adds	r7, #12
 800382c:	46bd      	mov	sp, r7
 800382e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003832:	4770      	bx	lr

08003834 <vListInitialiseItem>:
/*-----------------------------------------------------------*/

void vListInitialiseItem( ListItem_t * const pxItem )
{
 8003834:	b480      	push	{r7}
 8003836:	b083      	sub	sp, #12
 8003838:	af00      	add	r7, sp, #0
 800383a:	6078      	str	r0, [r7, #4]
	/* Make sure the list item is not recorded as being on a list. */
	pxItem->pxContainer = NULL;
 800383c:	687b      	ldr	r3, [r7, #4]
 800383e:	2200      	movs	r2, #0
 8003840:	611a      	str	r2, [r3, #16]

	/* Write known values into the list item if
	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
}
 8003842:	bf00      	nop
 8003844:	370c      	adds	r7, #12
 8003846:	46bd      	mov	sp, r7
 8003848:	f85d 7b04 	ldr.w	r7, [sp], #4
 800384c:	4770      	bx	lr

0800384e <vListInsertEnd>:
/*-----------------------------------------------------------*/

void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 800384e:	b480      	push	{r7}
 8003850:	b085      	sub	sp, #20
 8003852:	af00      	add	r7, sp, #0
 8003854:	6078      	str	r0, [r7, #4]
 8003856:	6039      	str	r1, [r7, #0]
ListItem_t * const pxIndex = pxList->pxIndex;
 8003858:	687b      	ldr	r3, [r7, #4]
 800385a:	685b      	ldr	r3, [r3, #4]
 800385c:	60fb      	str	r3, [r7, #12]
	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );

	/* Insert a new list item into pxList, but rather than sort the list,
	makes the new list item the last item to be removed by a call to
	listGET_OWNER_OF_NEXT_ENTRY(). */
	pxNewListItem->pxNext = pxIndex;
 800385e:	683b      	ldr	r3, [r7, #0]
 8003860:	68fa      	ldr	r2, [r7, #12]
 8003862:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
 8003864:	68fb      	ldr	r3, [r7, #12]
 8003866:	689a      	ldr	r2, [r3, #8]
 8003868:	683b      	ldr	r3, [r7, #0]
 800386a:	609a      	str	r2, [r3, #8]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	pxIndex->pxPrevious->pxNext = pxNewListItem;
 800386c:	68fb      	ldr	r3, [r7, #12]
 800386e:	689b      	ldr	r3, [r3, #8]
 8003870:	683a      	ldr	r2, [r7, #0]
 8003872:	605a      	str	r2, [r3, #4]
	pxIndex->pxPrevious = pxNewListItem;
 8003874:	68fb      	ldr	r3, [r7, #12]
 8003876:	683a      	ldr	r2, [r7, #0]
 8003878:	609a      	str	r2, [r3, #8]

	/* Remember which list the item is in. */
	pxNewListItem->pxContainer = pxList;
 800387a:	683b      	ldr	r3, [r7, #0]
 800387c:	687a      	ldr	r2, [r7, #4]
 800387e:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 8003880:	687b      	ldr	r3, [r7, #4]
 8003882:	681b      	ldr	r3, [r3, #0]
 8003884:	1c5a      	adds	r2, r3, #1
 8003886:	687b      	ldr	r3, [r7, #4]
 8003888:	601a      	str	r2, [r3, #0]
}
 800388a:	bf00      	nop
 800388c:	3714      	adds	r7, #20
 800388e:	46bd      	mov	sp, r7
 8003890:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003894:	4770      	bx	lr

08003896 <vListInsert>:
/*-----------------------------------------------------------*/

void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
{
 8003896:	b480      	push	{r7}
 8003898:	b085      	sub	sp, #20
 800389a:	af00      	add	r7, sp, #0
 800389c:	6078      	str	r0, [r7, #4]
 800389e:	6039      	str	r1, [r7, #0]
ListItem_t *pxIterator;
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
 80038a0:	683b      	ldr	r3, [r7, #0]
 80038a2:	681b      	ldr	r3, [r3, #0]
 80038a4:	60bb      	str	r3, [r7, #8]
	new list item should be placed after it.  This ensures that TCBs which are
	stored in ready lists (all of which have the same xItemValue value) get a
	share of the CPU.  However, if the xItemValue is the same as the back marker
	the iteration loop below will not end.  Therefore the value is checked
	first, and the algorithm slightly modified if necessary. */
	if( xValueOfInsertion == portMAX_DELAY )
 80038a6:	68bb      	ldr	r3, [r7, #8]
 80038a8:	f1b3 3fff 	cmp.w	r3, #4294967295
 80038ac:	d103      	bne.n	80038b6 <vListInsert+0x20>
	{
		pxIterator = pxList->xListEnd.pxPrevious;
 80038ae:	687b      	ldr	r3, [r7, #4]
 80038b0:	691b      	ldr	r3, [r3, #16]
 80038b2:	60fb      	str	r3, [r7, #12]
 80038b4:	e00c      	b.n	80038d0 <vListInsert+0x3a>
			4) Using a queue or semaphore before it has been initialised or
			   before the scheduler has been started (are interrupts firing
			   before vTaskStartScheduler() has been called?).
		**********************************************************************/

		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
 80038b6:	687b      	ldr	r3, [r7, #4]
 80038b8:	3308      	adds	r3, #8
 80038ba:	60fb      	str	r3, [r7, #12]
 80038bc:	e002      	b.n	80038c4 <vListInsert+0x2e>
 80038be:	68fb      	ldr	r3, [r7, #12]
 80038c0:	685b      	ldr	r3, [r3, #4]
 80038c2:	60fb      	str	r3, [r7, #12]
 80038c4:	68fb      	ldr	r3, [r7, #12]
 80038c6:	685b      	ldr	r3, [r3, #4]
 80038c8:	681b      	ldr	r3, [r3, #0]
 80038ca:	68ba      	ldr	r2, [r7, #8]
 80038cc:	429a      	cmp	r2, r3
 80038ce:	d2f6      	bcs.n	80038be <vListInsert+0x28>
			/* There is nothing to do here, just iterating to the wanted
			insertion position. */
		}
	}

	pxNewListItem->pxNext = pxIterator->pxNext;
 80038d0:	68fb      	ldr	r3, [r7, #12]
 80038d2:	685a      	ldr	r2, [r3, #4]
 80038d4:	683b      	ldr	r3, [r7, #0]
 80038d6:	605a      	str	r2, [r3, #4]
	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
 80038d8:	683b      	ldr	r3, [r7, #0]
 80038da:	685b      	ldr	r3, [r3, #4]
 80038dc:	683a      	ldr	r2, [r7, #0]
 80038de:	609a      	str	r2, [r3, #8]
	pxNewListItem->pxPrevious = pxIterator;
 80038e0:	683b      	ldr	r3, [r7, #0]
 80038e2:	68fa      	ldr	r2, [r7, #12]
 80038e4:	609a      	str	r2, [r3, #8]
	pxIterator->pxNext = pxNewListItem;
 80038e6:	68fb      	ldr	r3, [r7, #12]
 80038e8:	683a      	ldr	r2, [r7, #0]
 80038ea:	605a      	str	r2, [r3, #4]

	/* Remember which list the item is in.  This allows fast removal of the
	item later. */
	pxNewListItem->pxContainer = pxList;
 80038ec:	683b      	ldr	r3, [r7, #0]
 80038ee:	687a      	ldr	r2, [r7, #4]
 80038f0:	611a      	str	r2, [r3, #16]

	( pxList->uxNumberOfItems )++;
 80038f2:	687b      	ldr	r3, [r7, #4]
 80038f4:	681b      	ldr	r3, [r3, #0]
 80038f6:	1c5a      	adds	r2, r3, #1
 80038f8:	687b      	ldr	r3, [r7, #4]
 80038fa:	601a      	str	r2, [r3, #0]
}
 80038fc:	bf00      	nop
 80038fe:	3714      	adds	r7, #20
 8003900:	46bd      	mov	sp, r7
 8003902:	f85d 7b04 	ldr.w	r7, [sp], #4
 8003906:	4770      	bx	lr

08003908 <uxListRemove>:
/*-----------------------------------------------------------*/

UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
{
 8003908:	b480      	push	{r7}
 800390a:	b085      	sub	sp, #20
 800390c:	af00      	add	r7, sp, #0
 800390e:	6078      	str	r0, [r7, #4]
/* The list item knows which list it is in.  Obtain the list from the list
item. */
List_t * const pxList = pxItemToRemove->pxContainer;
 8003910:	687b      	ldr	r3, [r7, #4]
 8003912:	691b      	ldr	r3, [r3, #16]
 8003914:	60fb      	str	r3, [r7, #12]

	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
 8003916:	687b      	ldr	r3, [r7, #4]
 8003918:	685b      	ldr	r3, [r3, #4]
 800391a:	687a      	ldr	r2, [r7, #4]
 800391c:	6892      	ldr	r2, [r2, #8]
 800391e:	609a      	str	r2, [r3, #8]
	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
 8003920:	687b      	ldr	r3, [r7, #4]
 8003922:	689b      	ldr	r3, [r3, #8]
 8003924:	687a      	ldr	r2, [r7, #4]
 8003926:	6852      	ldr	r2, [r2, #4]
 8003928:	605a      	str	r2, [r3, #4]

	/* Only used during decision coverage testing. */
	mtCOVERAGE_TEST_DELAY();

	/* Make sure the index is left pointing to a valid item. */
	if( pxList->pxIndex == pxItemToRemove )
 800392a:	68fb      	ldr	r3, [r7, #12]
 800392c:	685b      	ldr	r3, [r3, #4]
 800392e:	687a      	ldr	r2, [r7, #4]
 8003930:	429a      	cmp	r2, r3
 8003932:	d103      	bne.n	800393c <uxListRemove+0x34>
	{
		pxList->pxIndex = pxItemToRemove->pxPrevious;
 8003934:	687b      	ldr	r3, [r7, #4]
 8003936:	689a      	ldr	r2, [r3, #8]
 8003938:	68fb      	ldr	r3, [r7, #12]
 800393a:	605a      	str	r2, [r3, #4]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxItemToRemove->pxContainer = NULL;
 800393c:	687b      	ldr	r3, [r7, #4]
 800393e:	2200      	movs	r2, #0
 8003940:	611a      	str	r2, [r3, #16]
	( pxList->uxNumberOfItems )--;
 8003942:	68fb      	ldr	r3, [r7, #12]
 8003944:	681b      	ldr	r3, [r3, #0]
 8003946:	1e5a      	subs	r2, r3, #1
 8003948:	68fb      	ldr	r3, [r7, #12]
 800394a:	601a      	str	r2, [r3, #0]

	return pxList->uxNumberOfItems;
 800394c:	68fb      	ldr	r3, [r7, #12]
 800394e:	681b      	ldr	r3, [r3, #0]
}
 8003950:	4618      	mov	r0, r3
 8003952:	3714      	adds	r7, #20
 8003954:	46bd      	mov	sp, r7
 8003956:	f85d 7b04 	ldr.w	r7, [sp], #4
 800395a:	4770      	bx	lr

0800395c <xQueueGenericReset>:
	}														\
	taskEXIT_CRITICAL()
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
{
 800395c:	b580      	push	{r7, lr}
 800395e:	b084      	sub	sp, #16
 8003960:	af00      	add	r7, sp, #0
 8003962:	6078      	str	r0, [r7, #4]
 8003964:	6039      	str	r1, [r7, #0]
Queue_t * const pxQueue = xQueue;
 8003966:	687b      	ldr	r3, [r7, #4]
 8003968:	60fb      	str	r3, [r7, #12]

	configASSERT( pxQueue );
 800396a:	68fb      	ldr	r3, [r7, #12]
 800396c:	2b00      	cmp	r3, #0
 800396e:	d10a      	bne.n	8003986 <xQueueGenericReset+0x2a>

portFORCE_INLINE static void vPortRaiseBASEPRI( void )
{
uint32_t ulNewBASEPRI;

	__asm volatile
 8003970:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003974:	f383 8811 	msr	BASEPRI, r3
 8003978:	f3bf 8f6f 	isb	sy
 800397c:	f3bf 8f4f 	dsb	sy
 8003980:	60bb      	str	r3, [r7, #8]
		"	msr basepri, %0											\n" \
		"	isb														\n" \
		"	dsb														\n" \
		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);
}
 8003982:	bf00      	nop
 8003984:	e7fe      	b.n	8003984 <xQueueGenericReset+0x28>

	taskENTER_CRITICAL();
 8003986:	f002 f875 	bl	8005a74 <vPortEnterCritical>
	{
		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 800398a:	68fb      	ldr	r3, [r7, #12]
 800398c:	681a      	ldr	r2, [r3, #0]
 800398e:	68fb      	ldr	r3, [r7, #12]
 8003990:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8003992:	68f9      	ldr	r1, [r7, #12]
 8003994:	6c09      	ldr	r1, [r1, #64]	; 0x40
 8003996:	fb01 f303 	mul.w	r3, r1, r3
 800399a:	441a      	add	r2, r3
 800399c:	68fb      	ldr	r3, [r7, #12]
 800399e:	609a      	str	r2, [r3, #8]
		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
 80039a0:	68fb      	ldr	r3, [r7, #12]
 80039a2:	2200      	movs	r2, #0
 80039a4:	639a      	str	r2, [r3, #56]	; 0x38
		pxQueue->pcWriteTo = pxQueue->pcHead;
 80039a6:	68fb      	ldr	r3, [r7, #12]
 80039a8:	681a      	ldr	r2, [r3, #0]
 80039aa:	68fb      	ldr	r3, [r7, #12]
 80039ac:	605a      	str	r2, [r3, #4]
		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
 80039ae:	68fb      	ldr	r3, [r7, #12]
 80039b0:	681a      	ldr	r2, [r3, #0]
 80039b2:	68fb      	ldr	r3, [r7, #12]
 80039b4:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 80039b6:	3b01      	subs	r3, #1
 80039b8:	68f9      	ldr	r1, [r7, #12]
 80039ba:	6c09      	ldr	r1, [r1, #64]	; 0x40
 80039bc:	fb01 f303 	mul.w	r3, r1, r3
 80039c0:	441a      	add	r2, r3
 80039c2:	68fb      	ldr	r3, [r7, #12]
 80039c4:	60da      	str	r2, [r3, #12]
		pxQueue->cRxLock = queueUNLOCKED;
 80039c6:	68fb      	ldr	r3, [r7, #12]
 80039c8:	22ff      	movs	r2, #255	; 0xff
 80039ca:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
		pxQueue->cTxLock = queueUNLOCKED;
 80039ce:	68fb      	ldr	r3, [r7, #12]
 80039d0:	22ff      	movs	r2, #255	; 0xff
 80039d2:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45

		if( xNewQueue == pdFALSE )
 80039d6:	683b      	ldr	r3, [r7, #0]
 80039d8:	2b00      	cmp	r3, #0
 80039da:	d114      	bne.n	8003a06 <xQueueGenericReset+0xaa>
			/* If there are tasks blocked waiting to read from the queue, then
			the tasks will remain blocked as after this function exits the queue
			will still be empty.  If there are tasks blocked waiting to write to
			the queue, then one should be unblocked as after this function exits
			it will be possible to write to it. */
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 80039dc:	68fb      	ldr	r3, [r7, #12]
 80039de:	691b      	ldr	r3, [r3, #16]
 80039e0:	2b00      	cmp	r3, #0
 80039e2:	d01a      	beq.n	8003a1a <xQueueGenericReset+0xbe>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 80039e4:	68fb      	ldr	r3, [r7, #12]
 80039e6:	3310      	adds	r3, #16
 80039e8:	4618      	mov	r0, r3
 80039ea:	f001 f929 	bl	8004c40 <xTaskRemoveFromEventList>
 80039ee:	4603      	mov	r3, r0
 80039f0:	2b00      	cmp	r3, #0
 80039f2:	d012      	beq.n	8003a1a <xQueueGenericReset+0xbe>
				{
					queueYIELD_IF_USING_PREEMPTION();
 80039f4:	4b0c      	ldr	r3, [pc, #48]	; (8003a28 <xQueueGenericReset+0xcc>)
 80039f6:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 80039fa:	601a      	str	r2, [r3, #0]
 80039fc:	f3bf 8f4f 	dsb	sy
 8003a00:	f3bf 8f6f 	isb	sy
 8003a04:	e009      	b.n	8003a1a <xQueueGenericReset+0xbe>
			}
		}
		else
		{
			/* Ensure the event queues start in the correct state. */
			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
 8003a06:	68fb      	ldr	r3, [r7, #12]
 8003a08:	3310      	adds	r3, #16
 8003a0a:	4618      	mov	r0, r3
 8003a0c:	f7ff fef2 	bl	80037f4 <vListInitialise>
			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
 8003a10:	68fb      	ldr	r3, [r7, #12]
 8003a12:	3324      	adds	r3, #36	; 0x24
 8003a14:	4618      	mov	r0, r3
 8003a16:	f7ff feed 	bl	80037f4 <vListInitialise>
		}
	}
	taskEXIT_CRITICAL();
 8003a1a:	f002 f85b 	bl	8005ad4 <vPortExitCritical>

	/* A value is returned for calling semantic consistency with previous
	versions. */
	return pdPASS;
 8003a1e:	2301      	movs	r3, #1
}
 8003a20:	4618      	mov	r0, r3
 8003a22:	3710      	adds	r7, #16
 8003a24:	46bd      	mov	sp, r7
 8003a26:	bd80      	pop	{r7, pc}
 8003a28:	e000ed04 	.word	0xe000ed04

08003a2c <xQueueGenericCreateStatic>:
/*-----------------------------------------------------------*/

#if( configSUPPORT_STATIC_ALLOCATION == 1 )

	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
	{
 8003a2c:	b580      	push	{r7, lr}
 8003a2e:	b08e      	sub	sp, #56	; 0x38
 8003a30:	af02      	add	r7, sp, #8
 8003a32:	60f8      	str	r0, [r7, #12]
 8003a34:	60b9      	str	r1, [r7, #8]
 8003a36:	607a      	str	r2, [r7, #4]
 8003a38:	603b      	str	r3, [r7, #0]
	Queue_t *pxNewQueue;

		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
 8003a3a:	68fb      	ldr	r3, [r7, #12]
 8003a3c:	2b00      	cmp	r3, #0
 8003a3e:	d10a      	bne.n	8003a56 <xQueueGenericCreateStatic+0x2a>
	__asm volatile
 8003a40:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003a44:	f383 8811 	msr	BASEPRI, r3
 8003a48:	f3bf 8f6f 	isb	sy
 8003a4c:	f3bf 8f4f 	dsb	sy
 8003a50:	62bb      	str	r3, [r7, #40]	; 0x28
}
 8003a52:	bf00      	nop
 8003a54:	e7fe      	b.n	8003a54 <xQueueGenericCreateStatic+0x28>

		/* The StaticQueue_t structure and the queue storage area must be
		supplied. */
		configASSERT( pxStaticQueue != NULL );
 8003a56:	683b      	ldr	r3, [r7, #0]
 8003a58:	2b00      	cmp	r3, #0
 8003a5a:	d10a      	bne.n	8003a72 <xQueueGenericCreateStatic+0x46>
	__asm volatile
 8003a5c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003a60:	f383 8811 	msr	BASEPRI, r3
 8003a64:	f3bf 8f6f 	isb	sy
 8003a68:	f3bf 8f4f 	dsb	sy
 8003a6c:	627b      	str	r3, [r7, #36]	; 0x24
}
 8003a6e:	bf00      	nop
 8003a70:	e7fe      	b.n	8003a70 <xQueueGenericCreateStatic+0x44>

		/* A queue storage area should be provided if the item size is not 0, and
		should not be provided if the item size is 0. */
		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
 8003a72:	687b      	ldr	r3, [r7, #4]
 8003a74:	2b00      	cmp	r3, #0
 8003a76:	d002      	beq.n	8003a7e <xQueueGenericCreateStatic+0x52>
 8003a78:	68bb      	ldr	r3, [r7, #8]
 8003a7a:	2b00      	cmp	r3, #0
 8003a7c:	d001      	beq.n	8003a82 <xQueueGenericCreateStatic+0x56>
 8003a7e:	2301      	movs	r3, #1
 8003a80:	e000      	b.n	8003a84 <xQueueGenericCreateStatic+0x58>
 8003a82:	2300      	movs	r3, #0
 8003a84:	2b00      	cmp	r3, #0
 8003a86:	d10a      	bne.n	8003a9e <xQueueGenericCreateStatic+0x72>
	__asm volatile
 8003a88:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003a8c:	f383 8811 	msr	BASEPRI, r3
 8003a90:	f3bf 8f6f 	isb	sy
 8003a94:	f3bf 8f4f 	dsb	sy
 8003a98:	623b      	str	r3, [r7, #32]
}
 8003a9a:	bf00      	nop
 8003a9c:	e7fe      	b.n	8003a9c <xQueueGenericCreateStatic+0x70>
		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
 8003a9e:	687b      	ldr	r3, [r7, #4]
 8003aa0:	2b00      	cmp	r3, #0
 8003aa2:	d102      	bne.n	8003aaa <xQueueGenericCreateStatic+0x7e>
 8003aa4:	68bb      	ldr	r3, [r7, #8]
 8003aa6:	2b00      	cmp	r3, #0
 8003aa8:	d101      	bne.n	8003aae <xQueueGenericCreateStatic+0x82>
 8003aaa:	2301      	movs	r3, #1
 8003aac:	e000      	b.n	8003ab0 <xQueueGenericCreateStatic+0x84>
 8003aae:	2300      	movs	r3, #0
 8003ab0:	2b00      	cmp	r3, #0
 8003ab2:	d10a      	bne.n	8003aca <xQueueGenericCreateStatic+0x9e>
	__asm volatile
 8003ab4:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003ab8:	f383 8811 	msr	BASEPRI, r3
 8003abc:	f3bf 8f6f 	isb	sy
 8003ac0:	f3bf 8f4f 	dsb	sy
 8003ac4:	61fb      	str	r3, [r7, #28]
}
 8003ac6:	bf00      	nop
 8003ac8:	e7fe      	b.n	8003ac8 <xQueueGenericCreateStatic+0x9c>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
			the real queue and semaphore structures. */
			volatile size_t xSize = sizeof( StaticQueue_t );
 8003aca:	2350      	movs	r3, #80	; 0x50
 8003acc:	617b      	str	r3, [r7, #20]
			configASSERT( xSize == sizeof( Queue_t ) );
 8003ace:	697b      	ldr	r3, [r7, #20]
 8003ad0:	2b50      	cmp	r3, #80	; 0x50
 8003ad2:	d00a      	beq.n	8003aea <xQueueGenericCreateStatic+0xbe>
	__asm volatile
 8003ad4:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003ad8:	f383 8811 	msr	BASEPRI, r3
 8003adc:	f3bf 8f6f 	isb	sy
 8003ae0:	f3bf 8f4f 	dsb	sy
 8003ae4:	61bb      	str	r3, [r7, #24]
}
 8003ae6:	bf00      	nop
 8003ae8:	e7fe      	b.n	8003ae8 <xQueueGenericCreateStatic+0xbc>
			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
 8003aea:	697b      	ldr	r3, [r7, #20]
		#endif /* configASSERT_DEFINED */

		/* The address of a statically allocated queue was passed in, use it.
		The address of a statically allocated storage area was also passed in
		but is already set. */
		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 8003aec:	683b      	ldr	r3, [r7, #0]
 8003aee:	62fb      	str	r3, [r7, #44]	; 0x2c

		if( pxNewQueue != NULL )
 8003af0:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8003af2:	2b00      	cmp	r3, #0
 8003af4:	d00d      	beq.n	8003b12 <xQueueGenericCreateStatic+0xe6>
			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
			{
				/* Queues can be allocated wither statically or dynamically, so
				note this queue was allocated statically in case the queue is
				later deleted. */
				pxNewQueue->ucStaticallyAllocated = pdTRUE;
 8003af6:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8003af8:	2201      	movs	r2, #1
 8003afa:	f883 2046 	strb.w	r2, [r3, #70]	; 0x46
			}
			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */

			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
 8003afe:	f897 2038 	ldrb.w	r2, [r7, #56]	; 0x38
 8003b02:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8003b04:	9300      	str	r3, [sp, #0]
 8003b06:	4613      	mov	r3, r2
 8003b08:	687a      	ldr	r2, [r7, #4]
 8003b0a:	68b9      	ldr	r1, [r7, #8]
 8003b0c:	68f8      	ldr	r0, [r7, #12]
 8003b0e:	f000 f805 	bl	8003b1c <prvInitialiseNewQueue>
		{
			traceQUEUE_CREATE_FAILED( ucQueueType );
			mtCOVERAGE_TEST_MARKER();
		}

		return pxNewQueue;
 8003b12:	6afb      	ldr	r3, [r7, #44]	; 0x2c
	}
 8003b14:	4618      	mov	r0, r3
 8003b16:	3730      	adds	r7, #48	; 0x30
 8003b18:	46bd      	mov	sp, r7
 8003b1a:	bd80      	pop	{r7, pc}

08003b1c <prvInitialiseNewQueue>:

#endif /* configSUPPORT_STATIC_ALLOCATION */
/*-----------------------------------------------------------*/

static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
{
 8003b1c:	b580      	push	{r7, lr}
 8003b1e:	b084      	sub	sp, #16
 8003b20:	af00      	add	r7, sp, #0
 8003b22:	60f8      	str	r0, [r7, #12]
 8003b24:	60b9      	str	r1, [r7, #8]
 8003b26:	607a      	str	r2, [r7, #4]
 8003b28:	70fb      	strb	r3, [r7, #3]
	/* Remove compiler warnings about unused parameters should
	configUSE_TRACE_FACILITY not be set to 1. */
	( void ) ucQueueType;

	if( uxItemSize == ( UBaseType_t ) 0 )
 8003b2a:	68bb      	ldr	r3, [r7, #8]
 8003b2c:	2b00      	cmp	r3, #0
 8003b2e:	d103      	bne.n	8003b38 <prvInitialiseNewQueue+0x1c>
	{
		/* No RAM was allocated for the queue storage area, but PC head cannot
		be set to NULL because NULL is used as a key to say the queue is used as
		a mutex.  Therefore just set pcHead to point to the queue as a benign
		value that is known to be within the memory map. */
		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
 8003b30:	69bb      	ldr	r3, [r7, #24]
 8003b32:	69ba      	ldr	r2, [r7, #24]
 8003b34:	601a      	str	r2, [r3, #0]
 8003b36:	e002      	b.n	8003b3e <prvInitialiseNewQueue+0x22>
	}
	else
	{
		/* Set the head to the start of the queue storage area. */
		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
 8003b38:	69bb      	ldr	r3, [r7, #24]
 8003b3a:	687a      	ldr	r2, [r7, #4]
 8003b3c:	601a      	str	r2, [r3, #0]
	}

	/* Initialise the queue members as described where the queue type is
	defined. */
	pxNewQueue->uxLength = uxQueueLength;
 8003b3e:	69bb      	ldr	r3, [r7, #24]
 8003b40:	68fa      	ldr	r2, [r7, #12]
 8003b42:	63da      	str	r2, [r3, #60]	; 0x3c
	pxNewQueue->uxItemSize = uxItemSize;
 8003b44:	69bb      	ldr	r3, [r7, #24]
 8003b46:	68ba      	ldr	r2, [r7, #8]
 8003b48:	641a      	str	r2, [r3, #64]	; 0x40
	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
 8003b4a:	2101      	movs	r1, #1
 8003b4c:	69b8      	ldr	r0, [r7, #24]
 8003b4e:	f7ff ff05 	bl	800395c <xQueueGenericReset>

	#if ( configUSE_TRACE_FACILITY == 1 )
	{
		pxNewQueue->ucQueueType = ucQueueType;
 8003b52:	69bb      	ldr	r3, [r7, #24]
 8003b54:	78fa      	ldrb	r2, [r7, #3]
 8003b56:	f883 204c 	strb.w	r2, [r3, #76]	; 0x4c
		pxNewQueue->pxQueueSetContainer = NULL;
	}
	#endif /* configUSE_QUEUE_SETS */

	traceQUEUE_CREATE( pxNewQueue );
}
 8003b5a:	bf00      	nop
 8003b5c:	3710      	adds	r7, #16
 8003b5e:	46bd      	mov	sp, r7
 8003b60:	bd80      	pop	{r7, pc}
	...

08003b64 <xQueueGenericSend>:

#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
{
 8003b64:	b580      	push	{r7, lr}
 8003b66:	b08e      	sub	sp, #56	; 0x38
 8003b68:	af00      	add	r7, sp, #0
 8003b6a:	60f8      	str	r0, [r7, #12]
 8003b6c:	60b9      	str	r1, [r7, #8]
 8003b6e:	607a      	str	r2, [r7, #4]
 8003b70:	603b      	str	r3, [r7, #0]
BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
 8003b72:	2300      	movs	r3, #0
 8003b74:	637b      	str	r3, [r7, #52]	; 0x34
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 8003b76:	68fb      	ldr	r3, [r7, #12]
 8003b78:	633b      	str	r3, [r7, #48]	; 0x30

	configASSERT( pxQueue );
 8003b7a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003b7c:	2b00      	cmp	r3, #0
 8003b7e:	d10a      	bne.n	8003b96 <xQueueGenericSend+0x32>
	__asm volatile
 8003b80:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003b84:	f383 8811 	msr	BASEPRI, r3
 8003b88:	f3bf 8f6f 	isb	sy
 8003b8c:	f3bf 8f4f 	dsb	sy
 8003b90:	62bb      	str	r3, [r7, #40]	; 0x28
}
 8003b92:	bf00      	nop
 8003b94:	e7fe      	b.n	8003b94 <xQueueGenericSend+0x30>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 8003b96:	68bb      	ldr	r3, [r7, #8]
 8003b98:	2b00      	cmp	r3, #0
 8003b9a:	d103      	bne.n	8003ba4 <xQueueGenericSend+0x40>
 8003b9c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003b9e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8003ba0:	2b00      	cmp	r3, #0
 8003ba2:	d101      	bne.n	8003ba8 <xQueueGenericSend+0x44>
 8003ba4:	2301      	movs	r3, #1
 8003ba6:	e000      	b.n	8003baa <xQueueGenericSend+0x46>
 8003ba8:	2300      	movs	r3, #0
 8003baa:	2b00      	cmp	r3, #0
 8003bac:	d10a      	bne.n	8003bc4 <xQueueGenericSend+0x60>
	__asm volatile
 8003bae:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003bb2:	f383 8811 	msr	BASEPRI, r3
 8003bb6:	f3bf 8f6f 	isb	sy
 8003bba:	f3bf 8f4f 	dsb	sy
 8003bbe:	627b      	str	r3, [r7, #36]	; 0x24
}
 8003bc0:	bf00      	nop
 8003bc2:	e7fe      	b.n	8003bc2 <xQueueGenericSend+0x5e>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 8003bc4:	683b      	ldr	r3, [r7, #0]
 8003bc6:	2b02      	cmp	r3, #2
 8003bc8:	d103      	bne.n	8003bd2 <xQueueGenericSend+0x6e>
 8003bca:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003bcc:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8003bce:	2b01      	cmp	r3, #1
 8003bd0:	d101      	bne.n	8003bd6 <xQueueGenericSend+0x72>
 8003bd2:	2301      	movs	r3, #1
 8003bd4:	e000      	b.n	8003bd8 <xQueueGenericSend+0x74>
 8003bd6:	2300      	movs	r3, #0
 8003bd8:	2b00      	cmp	r3, #0
 8003bda:	d10a      	bne.n	8003bf2 <xQueueGenericSend+0x8e>
	__asm volatile
 8003bdc:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003be0:	f383 8811 	msr	BASEPRI, r3
 8003be4:	f3bf 8f6f 	isb	sy
 8003be8:	f3bf 8f4f 	dsb	sy
 8003bec:	623b      	str	r3, [r7, #32]
}
 8003bee:	bf00      	nop
 8003bf0:	e7fe      	b.n	8003bf0 <xQueueGenericSend+0x8c>
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8003bf2:	f001 f9e7 	bl	8004fc4 <xTaskGetSchedulerState>
 8003bf6:	4603      	mov	r3, r0
 8003bf8:	2b00      	cmp	r3, #0
 8003bfa:	d102      	bne.n	8003c02 <xQueueGenericSend+0x9e>
 8003bfc:	687b      	ldr	r3, [r7, #4]
 8003bfe:	2b00      	cmp	r3, #0
 8003c00:	d101      	bne.n	8003c06 <xQueueGenericSend+0xa2>
 8003c02:	2301      	movs	r3, #1
 8003c04:	e000      	b.n	8003c08 <xQueueGenericSend+0xa4>
 8003c06:	2300      	movs	r3, #0
 8003c08:	2b00      	cmp	r3, #0
 8003c0a:	d10a      	bne.n	8003c22 <xQueueGenericSend+0xbe>
	__asm volatile
 8003c0c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003c10:	f383 8811 	msr	BASEPRI, r3
 8003c14:	f3bf 8f6f 	isb	sy
 8003c18:	f3bf 8f4f 	dsb	sy
 8003c1c:	61fb      	str	r3, [r7, #28]
}
 8003c1e:	bf00      	nop
 8003c20:	e7fe      	b.n	8003c20 <xQueueGenericSend+0xbc>
	/*lint -save -e904 This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8003c22:	f001 ff27 	bl	8005a74 <vPortEnterCritical>
		{
			/* Is there room on the queue now?  The running task must be the
			highest priority task wanting to access the queue.  If the head item
			in the queue is to be overwritten then it does not matter if the
			queue is full. */
			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 8003c26:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003c28:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8003c2a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003c2c:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8003c2e:	429a      	cmp	r2, r3
 8003c30:	d302      	bcc.n	8003c38 <xQueueGenericSend+0xd4>
 8003c32:	683b      	ldr	r3, [r7, #0]
 8003c34:	2b02      	cmp	r3, #2
 8003c36:	d129      	bne.n	8003c8c <xQueueGenericSend+0x128>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 8003c38:	683a      	ldr	r2, [r7, #0]
 8003c3a:	68b9      	ldr	r1, [r7, #8]
 8003c3c:	6b38      	ldr	r0, [r7, #48]	; 0x30
 8003c3e:	f000 fa0b 	bl	8004058 <prvCopyDataToQueue>
 8003c42:	62f8      	str	r0, [r7, #44]	; 0x2c

					/* If there was a task waiting for data to arrive on the
					queue then unblock it now. */
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8003c44:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003c46:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003c48:	2b00      	cmp	r3, #0
 8003c4a:	d010      	beq.n	8003c6e <xQueueGenericSend+0x10a>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8003c4c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003c4e:	3324      	adds	r3, #36	; 0x24
 8003c50:	4618      	mov	r0, r3
 8003c52:	f000 fff5 	bl	8004c40 <xTaskRemoveFromEventList>
 8003c56:	4603      	mov	r3, r0
 8003c58:	2b00      	cmp	r3, #0
 8003c5a:	d013      	beq.n	8003c84 <xQueueGenericSend+0x120>
						{
							/* The unblocked task has a priority higher than
							our own so yield immediately.  Yes it is ok to do
							this from within the critical section - the kernel
							takes care of that. */
							queueYIELD_IF_USING_PREEMPTION();
 8003c5c:	4b3f      	ldr	r3, [pc, #252]	; (8003d5c <xQueueGenericSend+0x1f8>)
 8003c5e:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8003c62:	601a      	str	r2, [r3, #0]
 8003c64:	f3bf 8f4f 	dsb	sy
 8003c68:	f3bf 8f6f 	isb	sy
 8003c6c:	e00a      	b.n	8003c84 <xQueueGenericSend+0x120>
						else
						{
							mtCOVERAGE_TEST_MARKER();
						}
					}
					else if( xYieldRequired != pdFALSE )
 8003c6e:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8003c70:	2b00      	cmp	r3, #0
 8003c72:	d007      	beq.n	8003c84 <xQueueGenericSend+0x120>
					{
						/* This path is a special case that will only get
						executed if the task was holding multiple mutexes and
						the mutexes were given back in an order that is
						different to that in which they were taken. */
						queueYIELD_IF_USING_PREEMPTION();
 8003c74:	4b39      	ldr	r3, [pc, #228]	; (8003d5c <xQueueGenericSend+0x1f8>)
 8003c76:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8003c7a:	601a      	str	r2, [r3, #0]
 8003c7c:	f3bf 8f4f 	dsb	sy
 8003c80:	f3bf 8f6f 	isb	sy
						mtCOVERAGE_TEST_MARKER();
					}
				}
				#endif /* configUSE_QUEUE_SETS */

				taskEXIT_CRITICAL();
 8003c84:	f001 ff26 	bl	8005ad4 <vPortExitCritical>
				return pdPASS;
 8003c88:	2301      	movs	r3, #1
 8003c8a:	e063      	b.n	8003d54 <xQueueGenericSend+0x1f0>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 8003c8c:	687b      	ldr	r3, [r7, #4]
 8003c8e:	2b00      	cmp	r3, #0
 8003c90:	d103      	bne.n	8003c9a <xQueueGenericSend+0x136>
				{
					/* The queue was full and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 8003c92:	f001 ff1f 	bl	8005ad4 <vPortExitCritical>

					/* Return to the original privilege level before exiting
					the function. */
					traceQUEUE_SEND_FAILED( pxQueue );
					return errQUEUE_FULL;
 8003c96:	2300      	movs	r3, #0
 8003c98:	e05c      	b.n	8003d54 <xQueueGenericSend+0x1f0>
				}
				else if( xEntryTimeSet == pdFALSE )
 8003c9a:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 8003c9c:	2b00      	cmp	r3, #0
 8003c9e:	d106      	bne.n	8003cae <xQueueGenericSend+0x14a>
				{
					/* The queue was full and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 8003ca0:	f107 0314 	add.w	r3, r7, #20
 8003ca4:	4618      	mov	r0, r3
 8003ca6:	f001 f82f 	bl	8004d08 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 8003caa:	2301      	movs	r3, #1
 8003cac:	637b      	str	r3, [r7, #52]	; 0x34
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 8003cae:	f001 ff11 	bl	8005ad4 <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 8003cb2:	f000 fd9b 	bl	80047ec <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 8003cb6:	f001 fedd 	bl	8005a74 <vPortEnterCritical>
 8003cba:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003cbc:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
 8003cc0:	b25b      	sxtb	r3, r3
 8003cc2:	f1b3 3fff 	cmp.w	r3, #4294967295
 8003cc6:	d103      	bne.n	8003cd0 <xQueueGenericSend+0x16c>
 8003cc8:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003cca:	2200      	movs	r2, #0
 8003ccc:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
 8003cd0:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003cd2:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 8003cd6:	b25b      	sxtb	r3, r3
 8003cd8:	f1b3 3fff 	cmp.w	r3, #4294967295
 8003cdc:	d103      	bne.n	8003ce6 <xQueueGenericSend+0x182>
 8003cde:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003ce0:	2200      	movs	r2, #0
 8003ce2:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
 8003ce6:	f001 fef5 	bl	8005ad4 <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 8003cea:	1d3a      	adds	r2, r7, #4
 8003cec:	f107 0314 	add.w	r3, r7, #20
 8003cf0:	4611      	mov	r1, r2
 8003cf2:	4618      	mov	r0, r3
 8003cf4:	f001 f81e 	bl	8004d34 <xTaskCheckForTimeOut>
 8003cf8:	4603      	mov	r3, r0
 8003cfa:	2b00      	cmp	r3, #0
 8003cfc:	d124      	bne.n	8003d48 <xQueueGenericSend+0x1e4>
		{
			if( prvIsQueueFull( pxQueue ) != pdFALSE )
 8003cfe:	6b38      	ldr	r0, [r7, #48]	; 0x30
 8003d00:	f000 faa2 	bl	8004248 <prvIsQueueFull>
 8003d04:	4603      	mov	r3, r0
 8003d06:	2b00      	cmp	r3, #0
 8003d08:	d018      	beq.n	8003d3c <xQueueGenericSend+0x1d8>
			{
				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
 8003d0a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8003d0c:	3310      	adds	r3, #16
 8003d0e:	687a      	ldr	r2, [r7, #4]
 8003d10:	4611      	mov	r1, r2
 8003d12:	4618      	mov	r0, r3
 8003d14:	f000 ff44 	bl	8004ba0 <vTaskPlaceOnEventList>
				/* Unlocking the queue means queue events can effect the
				event list.  It is possible that interrupts occurring now
				remove this task from the event list again - but as the
				scheduler is suspended the task will go onto the pending
				ready last instead of the actual ready list. */
				prvUnlockQueue( pxQueue );
 8003d18:	6b38      	ldr	r0, [r7, #48]	; 0x30
 8003d1a:	f000 fa2d 	bl	8004178 <prvUnlockQueue>
				/* Resuming the scheduler will move tasks from the pending
				ready list into the ready list - so it is feasible that this
				task is already in a ready list before it yields - in which
				case the yield will not cause a context switch unless there
				is also a higher priority task in the pending ready list. */
				if( xTaskResumeAll() == pdFALSE )
 8003d1e:	f000 fd73 	bl	8004808 <xTaskResumeAll>
 8003d22:	4603      	mov	r3, r0
 8003d24:	2b00      	cmp	r3, #0
 8003d26:	f47f af7c 	bne.w	8003c22 <xQueueGenericSend+0xbe>
				{
					portYIELD_WITHIN_API();
 8003d2a:	4b0c      	ldr	r3, [pc, #48]	; (8003d5c <xQueueGenericSend+0x1f8>)
 8003d2c:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8003d30:	601a      	str	r2, [r3, #0]
 8003d32:	f3bf 8f4f 	dsb	sy
 8003d36:	f3bf 8f6f 	isb	sy
 8003d3a:	e772      	b.n	8003c22 <xQueueGenericSend+0xbe>
				}
			}
			else
			{
				/* Try again. */
				prvUnlockQueue( pxQueue );
 8003d3c:	6b38      	ldr	r0, [r7, #48]	; 0x30
 8003d3e:	f000 fa1b 	bl	8004178 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 8003d42:	f000 fd61 	bl	8004808 <xTaskResumeAll>
 8003d46:	e76c      	b.n	8003c22 <xQueueGenericSend+0xbe>
			}
		}
		else
		{
			/* The timeout has expired. */
			prvUnlockQueue( pxQueue );
 8003d48:	6b38      	ldr	r0, [r7, #48]	; 0x30
 8003d4a:	f000 fa15 	bl	8004178 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8003d4e:	f000 fd5b 	bl	8004808 <xTaskResumeAll>

			traceQUEUE_SEND_FAILED( pxQueue );
			return errQUEUE_FULL;
 8003d52:	2300      	movs	r3, #0
		}
	} /*lint -restore */
}
 8003d54:	4618      	mov	r0, r3
 8003d56:	3738      	adds	r7, #56	; 0x38
 8003d58:	46bd      	mov	sp, r7
 8003d5a:	bd80      	pop	{r7, pc}
 8003d5c:	e000ed04 	.word	0xe000ed04

08003d60 <xQueueGenericSendFromISR>:
/*-----------------------------------------------------------*/

BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
{
 8003d60:	b580      	push	{r7, lr}
 8003d62:	b090      	sub	sp, #64	; 0x40
 8003d64:	af00      	add	r7, sp, #0
 8003d66:	60f8      	str	r0, [r7, #12]
 8003d68:	60b9      	str	r1, [r7, #8]
 8003d6a:	607a      	str	r2, [r7, #4]
 8003d6c:	603b      	str	r3, [r7, #0]
BaseType_t xReturn;
UBaseType_t uxSavedInterruptStatus;
Queue_t * const pxQueue = xQueue;
 8003d6e:	68fb      	ldr	r3, [r7, #12]
 8003d70:	63bb      	str	r3, [r7, #56]	; 0x38

	configASSERT( pxQueue );
 8003d72:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003d74:	2b00      	cmp	r3, #0
 8003d76:	d10a      	bne.n	8003d8e <xQueueGenericSendFromISR+0x2e>
	__asm volatile
 8003d78:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003d7c:	f383 8811 	msr	BASEPRI, r3
 8003d80:	f3bf 8f6f 	isb	sy
 8003d84:	f3bf 8f4f 	dsb	sy
 8003d88:	62bb      	str	r3, [r7, #40]	; 0x28
}
 8003d8a:	bf00      	nop
 8003d8c:	e7fe      	b.n	8003d8c <xQueueGenericSendFromISR+0x2c>
	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
 8003d8e:	68bb      	ldr	r3, [r7, #8]
 8003d90:	2b00      	cmp	r3, #0
 8003d92:	d103      	bne.n	8003d9c <xQueueGenericSendFromISR+0x3c>
 8003d94:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003d96:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8003d98:	2b00      	cmp	r3, #0
 8003d9a:	d101      	bne.n	8003da0 <xQueueGenericSendFromISR+0x40>
 8003d9c:	2301      	movs	r3, #1
 8003d9e:	e000      	b.n	8003da2 <xQueueGenericSendFromISR+0x42>
 8003da0:	2300      	movs	r3, #0
 8003da2:	2b00      	cmp	r3, #0
 8003da4:	d10a      	bne.n	8003dbc <xQueueGenericSendFromISR+0x5c>
	__asm volatile
 8003da6:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003daa:	f383 8811 	msr	BASEPRI, r3
 8003dae:	f3bf 8f6f 	isb	sy
 8003db2:	f3bf 8f4f 	dsb	sy
 8003db6:	627b      	str	r3, [r7, #36]	; 0x24
}
 8003db8:	bf00      	nop
 8003dba:	e7fe      	b.n	8003dba <xQueueGenericSendFromISR+0x5a>
	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
 8003dbc:	683b      	ldr	r3, [r7, #0]
 8003dbe:	2b02      	cmp	r3, #2
 8003dc0:	d103      	bne.n	8003dca <xQueueGenericSendFromISR+0x6a>
 8003dc2:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003dc4:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8003dc6:	2b01      	cmp	r3, #1
 8003dc8:	d101      	bne.n	8003dce <xQueueGenericSendFromISR+0x6e>
 8003dca:	2301      	movs	r3, #1
 8003dcc:	e000      	b.n	8003dd0 <xQueueGenericSendFromISR+0x70>
 8003dce:	2300      	movs	r3, #0
 8003dd0:	2b00      	cmp	r3, #0
 8003dd2:	d10a      	bne.n	8003dea <xQueueGenericSendFromISR+0x8a>
	__asm volatile
 8003dd4:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003dd8:	f383 8811 	msr	BASEPRI, r3
 8003ddc:	f3bf 8f6f 	isb	sy
 8003de0:	f3bf 8f4f 	dsb	sy
 8003de4:	623b      	str	r3, [r7, #32]
}
 8003de6:	bf00      	nop
 8003de8:	e7fe      	b.n	8003de8 <xQueueGenericSendFromISR+0x88>
	that have been assigned a priority at or (logically) below the maximum
	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
	safe API to ensure interrupt entry is as fast and as simple as possible.
	More information (albeit Cortex-M specific) is provided on the following
	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
 8003dea:	f001 ff25 	bl	8005c38 <vPortValidateInterruptPriority>

portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
{
uint32_t ulOriginalBASEPRI, ulNewBASEPRI;

	__asm volatile
 8003dee:	f3ef 8211 	mrs	r2, BASEPRI
 8003df2:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003df6:	f383 8811 	msr	BASEPRI, r3
 8003dfa:	f3bf 8f6f 	isb	sy
 8003dfe:	f3bf 8f4f 	dsb	sy
 8003e02:	61fa      	str	r2, [r7, #28]
 8003e04:	61bb      	str	r3, [r7, #24]
		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
	);

	/* This return will not be reached but is necessary to prevent compiler
	warnings. */
	return ulOriginalBASEPRI;
 8003e06:	69fb      	ldr	r3, [r7, #28]
	/* Similar to xQueueGenericSend, except without blocking if there is no room
	in the queue.  Also don't directly wake a task that was blocked on a queue
	read, instead return a flag to say whether a context switch is required or
	not (i.e. has a task with a higher priority than us been woken by this
	post). */
	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
 8003e08:	637b      	str	r3, [r7, #52]	; 0x34
	{
		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
 8003e0a:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003e0c:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8003e0e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003e10:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 8003e12:	429a      	cmp	r2, r3
 8003e14:	d302      	bcc.n	8003e1c <xQueueGenericSendFromISR+0xbc>
 8003e16:	683b      	ldr	r3, [r7, #0]
 8003e18:	2b02      	cmp	r3, #2
 8003e1a:	d12f      	bne.n	8003e7c <xQueueGenericSendFromISR+0x11c>
		{
			const int8_t cTxLock = pxQueue->cTxLock;
 8003e1c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003e1e:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 8003e22:	f887 3033 	strb.w	r3, [r7, #51]	; 0x33
			const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
 8003e26:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003e28:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 8003e2a:	62fb      	str	r3, [r7, #44]	; 0x2c
			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
			in a task disinheriting a priority and prvCopyDataToQueue() can be
			called here even though the disinherit function does not check if
			the scheduler is suspended before accessing the ready lists. */
			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
 8003e2c:	683a      	ldr	r2, [r7, #0]
 8003e2e:	68b9      	ldr	r1, [r7, #8]
 8003e30:	6bb8      	ldr	r0, [r7, #56]	; 0x38
 8003e32:	f000 f911 	bl	8004058 <prvCopyDataToQueue>

			/* The event list is not altered if the queue is locked.  This will
			be done when the queue is unlocked later. */
			if( cTxLock == queueUNLOCKED )
 8003e36:	f997 3033 	ldrsb.w	r3, [r7, #51]	; 0x33
 8003e3a:	f1b3 3fff 	cmp.w	r3, #4294967295
 8003e3e:	d112      	bne.n	8003e66 <xQueueGenericSendFromISR+0x106>
						}
					}
				}
				#else /* configUSE_QUEUE_SETS */
				{
					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 8003e40:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003e42:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8003e44:	2b00      	cmp	r3, #0
 8003e46:	d016      	beq.n	8003e76 <xQueueGenericSendFromISR+0x116>
					{
						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8003e48:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003e4a:	3324      	adds	r3, #36	; 0x24
 8003e4c:	4618      	mov	r0, r3
 8003e4e:	f000 fef7 	bl	8004c40 <xTaskRemoveFromEventList>
 8003e52:	4603      	mov	r3, r0
 8003e54:	2b00      	cmp	r3, #0
 8003e56:	d00e      	beq.n	8003e76 <xQueueGenericSendFromISR+0x116>
						{
							/* The task waiting has a higher priority so record that a
							context	switch is required. */
							if( pxHigherPriorityTaskWoken != NULL )
 8003e58:	687b      	ldr	r3, [r7, #4]
 8003e5a:	2b00      	cmp	r3, #0
 8003e5c:	d00b      	beq.n	8003e76 <xQueueGenericSendFromISR+0x116>
							{
								*pxHigherPriorityTaskWoken = pdTRUE;
 8003e5e:	687b      	ldr	r3, [r7, #4]
 8003e60:	2201      	movs	r2, #1
 8003e62:	601a      	str	r2, [r3, #0]
 8003e64:	e007      	b.n	8003e76 <xQueueGenericSendFromISR+0x116>
			}
			else
			{
				/* Increment the lock count so the task that unlocks the queue
				knows that data was posted while it was locked. */
				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
 8003e66:	f897 3033 	ldrb.w	r3, [r7, #51]	; 0x33
 8003e6a:	3301      	adds	r3, #1
 8003e6c:	b2db      	uxtb	r3, r3
 8003e6e:	b25a      	sxtb	r2, r3
 8003e70:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8003e72:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
			}

			xReturn = pdPASS;
 8003e76:	2301      	movs	r3, #1
 8003e78:	63fb      	str	r3, [r7, #60]	; 0x3c
		{
 8003e7a:	e001      	b.n	8003e80 <xQueueGenericSendFromISR+0x120>
		}
		else
		{
			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
			xReturn = errQUEUE_FULL;
 8003e7c:	2300      	movs	r3, #0
 8003e7e:	63fb      	str	r3, [r7, #60]	; 0x3c
 8003e80:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 8003e82:	617b      	str	r3, [r7, #20]
}
/*-----------------------------------------------------------*/

portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
{
	__asm volatile
 8003e84:	697b      	ldr	r3, [r7, #20]
 8003e86:	f383 8811 	msr	BASEPRI, r3
	(
		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
	);
}
 8003e8a:	bf00      	nop
		}
	}
	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );

	return xReturn;
 8003e8c:	6bfb      	ldr	r3, [r7, #60]	; 0x3c
}
 8003e8e:	4618      	mov	r0, r3
 8003e90:	3740      	adds	r7, #64	; 0x40
 8003e92:	46bd      	mov	sp, r7
 8003e94:	bd80      	pop	{r7, pc}
	...

08003e98 <xQueueReceive>:
	return xReturn;
}
/*-----------------------------------------------------------*/

BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
{
 8003e98:	b580      	push	{r7, lr}
 8003e9a:	b08c      	sub	sp, #48	; 0x30
 8003e9c:	af00      	add	r7, sp, #0
 8003e9e:	60f8      	str	r0, [r7, #12]
 8003ea0:	60b9      	str	r1, [r7, #8]
 8003ea2:	607a      	str	r2, [r7, #4]
BaseType_t xEntryTimeSet = pdFALSE;
 8003ea4:	2300      	movs	r3, #0
 8003ea6:	62fb      	str	r3, [r7, #44]	; 0x2c
TimeOut_t xTimeOut;
Queue_t * const pxQueue = xQueue;
 8003ea8:	68fb      	ldr	r3, [r7, #12]
 8003eaa:	62bb      	str	r3, [r7, #40]	; 0x28

	/* Check the pointer is not NULL. */
	configASSERT( ( pxQueue ) );
 8003eac:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003eae:	2b00      	cmp	r3, #0
 8003eb0:	d10a      	bne.n	8003ec8 <xQueueReceive+0x30>
	__asm volatile
 8003eb2:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003eb6:	f383 8811 	msr	BASEPRI, r3
 8003eba:	f3bf 8f6f 	isb	sy
 8003ebe:	f3bf 8f4f 	dsb	sy
 8003ec2:	623b      	str	r3, [r7, #32]
}
 8003ec4:	bf00      	nop
 8003ec6:	e7fe      	b.n	8003ec6 <xQueueReceive+0x2e>

	/* The buffer into which data is received can only be NULL if the data size
	is zero (so no data is copied into the buffer. */
	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
 8003ec8:	68bb      	ldr	r3, [r7, #8]
 8003eca:	2b00      	cmp	r3, #0
 8003ecc:	d103      	bne.n	8003ed6 <xQueueReceive+0x3e>
 8003ece:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003ed0:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8003ed2:	2b00      	cmp	r3, #0
 8003ed4:	d101      	bne.n	8003eda <xQueueReceive+0x42>
 8003ed6:	2301      	movs	r3, #1
 8003ed8:	e000      	b.n	8003edc <xQueueReceive+0x44>
 8003eda:	2300      	movs	r3, #0
 8003edc:	2b00      	cmp	r3, #0
 8003ede:	d10a      	bne.n	8003ef6 <xQueueReceive+0x5e>
	__asm volatile
 8003ee0:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003ee4:	f383 8811 	msr	BASEPRI, r3
 8003ee8:	f3bf 8f6f 	isb	sy
 8003eec:	f3bf 8f4f 	dsb	sy
 8003ef0:	61fb      	str	r3, [r7, #28]
}
 8003ef2:	bf00      	nop
 8003ef4:	e7fe      	b.n	8003ef4 <xQueueReceive+0x5c>

	/* Cannot block if the scheduler is suspended. */
	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
	{
		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
 8003ef6:	f001 f865 	bl	8004fc4 <xTaskGetSchedulerState>
 8003efa:	4603      	mov	r3, r0
 8003efc:	2b00      	cmp	r3, #0
 8003efe:	d102      	bne.n	8003f06 <xQueueReceive+0x6e>
 8003f00:	687b      	ldr	r3, [r7, #4]
 8003f02:	2b00      	cmp	r3, #0
 8003f04:	d101      	bne.n	8003f0a <xQueueReceive+0x72>
 8003f06:	2301      	movs	r3, #1
 8003f08:	e000      	b.n	8003f0c <xQueueReceive+0x74>
 8003f0a:	2300      	movs	r3, #0
 8003f0c:	2b00      	cmp	r3, #0
 8003f0e:	d10a      	bne.n	8003f26 <xQueueReceive+0x8e>
	__asm volatile
 8003f10:	f04f 0350 	mov.w	r3, #80	; 0x50
 8003f14:	f383 8811 	msr	BASEPRI, r3
 8003f18:	f3bf 8f6f 	isb	sy
 8003f1c:	f3bf 8f4f 	dsb	sy
 8003f20:	61bb      	str	r3, [r7, #24]
}
 8003f22:	bf00      	nop
 8003f24:	e7fe      	b.n	8003f24 <xQueueReceive+0x8c>
	/*lint -save -e904  This function relaxes the coding standard somewhat to
	allow return statements within the function itself.  This is done in the
	interest of execution time efficiency. */
	for( ;; )
	{
		taskENTER_CRITICAL();
 8003f26:	f001 fda5 	bl	8005a74 <vPortEnterCritical>
		{
			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8003f2a:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003f2c:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 8003f2e:	627b      	str	r3, [r7, #36]	; 0x24

			/* Is there data in the queue now?  To be running the calling task
			must be the highest priority task wanting to access the queue. */
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 8003f30:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8003f32:	2b00      	cmp	r3, #0
 8003f34:	d01f      	beq.n	8003f76 <xQueueReceive+0xde>
			{
				/* Data available, remove one item. */
				prvCopyDataFromQueue( pxQueue, pvBuffer );
 8003f36:	68b9      	ldr	r1, [r7, #8]
 8003f38:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8003f3a:	f000 f8f7 	bl	800412c <prvCopyDataFromQueue>
				traceQUEUE_RECEIVE( pxQueue );
				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
 8003f3e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8003f40:	1e5a      	subs	r2, r3, #1
 8003f42:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003f44:	639a      	str	r2, [r3, #56]	; 0x38

				/* There is now space in the queue, were any tasks waiting to
				post to the queue?  If so, unblock the highest priority waiting
				task. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 8003f46:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003f48:	691b      	ldr	r3, [r3, #16]
 8003f4a:	2b00      	cmp	r3, #0
 8003f4c:	d00f      	beq.n	8003f6e <xQueueReceive+0xd6>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 8003f4e:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003f50:	3310      	adds	r3, #16
 8003f52:	4618      	mov	r0, r3
 8003f54:	f000 fe74 	bl	8004c40 <xTaskRemoveFromEventList>
 8003f58:	4603      	mov	r3, r0
 8003f5a:	2b00      	cmp	r3, #0
 8003f5c:	d007      	beq.n	8003f6e <xQueueReceive+0xd6>
					{
						queueYIELD_IF_USING_PREEMPTION();
 8003f5e:	4b3d      	ldr	r3, [pc, #244]	; (8004054 <xQueueReceive+0x1bc>)
 8003f60:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8003f64:	601a      	str	r2, [r3, #0]
 8003f66:	f3bf 8f4f 	dsb	sy
 8003f6a:	f3bf 8f6f 	isb	sy
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				taskEXIT_CRITICAL();
 8003f6e:	f001 fdb1 	bl	8005ad4 <vPortExitCritical>
				return pdPASS;
 8003f72:	2301      	movs	r3, #1
 8003f74:	e069      	b.n	800404a <xQueueReceive+0x1b2>
			}
			else
			{
				if( xTicksToWait == ( TickType_t ) 0 )
 8003f76:	687b      	ldr	r3, [r7, #4]
 8003f78:	2b00      	cmp	r3, #0
 8003f7a:	d103      	bne.n	8003f84 <xQueueReceive+0xec>
				{
					/* The queue was empty and no block time is specified (or
					the block time has expired) so leave now. */
					taskEXIT_CRITICAL();
 8003f7c:	f001 fdaa 	bl	8005ad4 <vPortExitCritical>
					traceQUEUE_RECEIVE_FAILED( pxQueue );
					return errQUEUE_EMPTY;
 8003f80:	2300      	movs	r3, #0
 8003f82:	e062      	b.n	800404a <xQueueReceive+0x1b2>
				}
				else if( xEntryTimeSet == pdFALSE )
 8003f84:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8003f86:	2b00      	cmp	r3, #0
 8003f88:	d106      	bne.n	8003f98 <xQueueReceive+0x100>
				{
					/* The queue was empty and a block time was specified so
					configure the timeout structure. */
					vTaskInternalSetTimeOutState( &xTimeOut );
 8003f8a:	f107 0310 	add.w	r3, r7, #16
 8003f8e:	4618      	mov	r0, r3
 8003f90:	f000 feba 	bl	8004d08 <vTaskInternalSetTimeOutState>
					xEntryTimeSet = pdTRUE;
 8003f94:	2301      	movs	r3, #1
 8003f96:	62fb      	str	r3, [r7, #44]	; 0x2c
					/* Entry time was already set. */
					mtCOVERAGE_TEST_MARKER();
				}
			}
		}
		taskEXIT_CRITICAL();
 8003f98:	f001 fd9c 	bl	8005ad4 <vPortExitCritical>

		/* Interrupts and other tasks can send to and receive from the queue
		now the critical section has been exited. */

		vTaskSuspendAll();
 8003f9c:	f000 fc26 	bl	80047ec <vTaskSuspendAll>
		prvLockQueue( pxQueue );
 8003fa0:	f001 fd68 	bl	8005a74 <vPortEnterCritical>
 8003fa4:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003fa6:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
 8003faa:	b25b      	sxtb	r3, r3
 8003fac:	f1b3 3fff 	cmp.w	r3, #4294967295
 8003fb0:	d103      	bne.n	8003fba <xQueueReceive+0x122>
 8003fb2:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003fb4:	2200      	movs	r2, #0
 8003fb6:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
 8003fba:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003fbc:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 8003fc0:	b25b      	sxtb	r3, r3
 8003fc2:	f1b3 3fff 	cmp.w	r3, #4294967295
 8003fc6:	d103      	bne.n	8003fd0 <xQueueReceive+0x138>
 8003fc8:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003fca:	2200      	movs	r2, #0
 8003fcc:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
 8003fd0:	f001 fd80 	bl	8005ad4 <vPortExitCritical>

		/* Update the timeout state to see if it has expired yet. */
		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
 8003fd4:	1d3a      	adds	r2, r7, #4
 8003fd6:	f107 0310 	add.w	r3, r7, #16
 8003fda:	4611      	mov	r1, r2
 8003fdc:	4618      	mov	r0, r3
 8003fde:	f000 fea9 	bl	8004d34 <xTaskCheckForTimeOut>
 8003fe2:	4603      	mov	r3, r0
 8003fe4:	2b00      	cmp	r3, #0
 8003fe6:	d123      	bne.n	8004030 <xQueueReceive+0x198>
		{
			/* The timeout has not expired.  If the queue is still empty place
			the task on the list of tasks waiting to receive from the queue. */
			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 8003fe8:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8003fea:	f000 f917 	bl	800421c <prvIsQueueEmpty>
 8003fee:	4603      	mov	r3, r0
 8003ff0:	2b00      	cmp	r3, #0
 8003ff2:	d017      	beq.n	8004024 <xQueueReceive+0x18c>
			{
				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
 8003ff4:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8003ff6:	3324      	adds	r3, #36	; 0x24
 8003ff8:	687a      	ldr	r2, [r7, #4]
 8003ffa:	4611      	mov	r1, r2
 8003ffc:	4618      	mov	r0, r3
 8003ffe:	f000 fdcf 	bl	8004ba0 <vTaskPlaceOnEventList>
				prvUnlockQueue( pxQueue );
 8004002:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8004004:	f000 f8b8 	bl	8004178 <prvUnlockQueue>
				if( xTaskResumeAll() == pdFALSE )
 8004008:	f000 fbfe 	bl	8004808 <xTaskResumeAll>
 800400c:	4603      	mov	r3, r0
 800400e:	2b00      	cmp	r3, #0
 8004010:	d189      	bne.n	8003f26 <xQueueReceive+0x8e>
				{
					portYIELD_WITHIN_API();
 8004012:	4b10      	ldr	r3, [pc, #64]	; (8004054 <xQueueReceive+0x1bc>)
 8004014:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8004018:	601a      	str	r2, [r3, #0]
 800401a:	f3bf 8f4f 	dsb	sy
 800401e:	f3bf 8f6f 	isb	sy
 8004022:	e780      	b.n	8003f26 <xQueueReceive+0x8e>
			}
			else
			{
				/* The queue contains data again.  Loop back to try and read the
				data. */
				prvUnlockQueue( pxQueue );
 8004024:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8004026:	f000 f8a7 	bl	8004178 <prvUnlockQueue>
				( void ) xTaskResumeAll();
 800402a:	f000 fbed 	bl	8004808 <xTaskResumeAll>
 800402e:	e77a      	b.n	8003f26 <xQueueReceive+0x8e>
		}
		else
		{
			/* Timed out.  If there is no data in the queue exit, otherwise loop
			back and attempt to read the data. */
			prvUnlockQueue( pxQueue );
 8004030:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8004032:	f000 f8a1 	bl	8004178 <prvUnlockQueue>
			( void ) xTaskResumeAll();
 8004036:	f000 fbe7 	bl	8004808 <xTaskResumeAll>

			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
 800403a:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 800403c:	f000 f8ee 	bl	800421c <prvIsQueueEmpty>
 8004040:	4603      	mov	r3, r0
 8004042:	2b00      	cmp	r3, #0
 8004044:	f43f af6f 	beq.w	8003f26 <xQueueReceive+0x8e>
			{
				traceQUEUE_RECEIVE_FAILED( pxQueue );
				return errQUEUE_EMPTY;
 8004048:	2300      	movs	r3, #0
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	} /*lint -restore */
}
 800404a:	4618      	mov	r0, r3
 800404c:	3730      	adds	r7, #48	; 0x30
 800404e:	46bd      	mov	sp, r7
 8004050:	bd80      	pop	{r7, pc}
 8004052:	bf00      	nop
 8004054:	e000ed04 	.word	0xe000ed04

08004058 <prvCopyDataToQueue>:

#endif /* configUSE_MUTEXES */
/*-----------------------------------------------------------*/

static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
{
 8004058:	b580      	push	{r7, lr}
 800405a:	b086      	sub	sp, #24
 800405c:	af00      	add	r7, sp, #0
 800405e:	60f8      	str	r0, [r7, #12]
 8004060:	60b9      	str	r1, [r7, #8]
 8004062:	607a      	str	r2, [r7, #4]
BaseType_t xReturn = pdFALSE;
 8004064:	2300      	movs	r3, #0
 8004066:	617b      	str	r3, [r7, #20]
UBaseType_t uxMessagesWaiting;

	/* This function is called from a critical section. */

	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
 8004068:	68fb      	ldr	r3, [r7, #12]
 800406a:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 800406c:	613b      	str	r3, [r7, #16]

	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
 800406e:	68fb      	ldr	r3, [r7, #12]
 8004070:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004072:	2b00      	cmp	r3, #0
 8004074:	d10d      	bne.n	8004092 <prvCopyDataToQueue+0x3a>
	{
		#if ( configUSE_MUTEXES == 1 )
		{
			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
 8004076:	68fb      	ldr	r3, [r7, #12]
 8004078:	681b      	ldr	r3, [r3, #0]
 800407a:	2b00      	cmp	r3, #0
 800407c:	d14d      	bne.n	800411a <prvCopyDataToQueue+0xc2>
			{
				/* The mutex is no longer being held. */
				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
 800407e:	68fb      	ldr	r3, [r7, #12]
 8004080:	689b      	ldr	r3, [r3, #8]
 8004082:	4618      	mov	r0, r3
 8004084:	f000 ffbc 	bl	8005000 <xTaskPriorityDisinherit>
 8004088:	6178      	str	r0, [r7, #20]
				pxQueue->u.xSemaphore.xMutexHolder = NULL;
 800408a:	68fb      	ldr	r3, [r7, #12]
 800408c:	2200      	movs	r2, #0
 800408e:	609a      	str	r2, [r3, #8]
 8004090:	e043      	b.n	800411a <prvCopyDataToQueue+0xc2>
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configUSE_MUTEXES */
	}
	else if( xPosition == queueSEND_TO_BACK )
 8004092:	687b      	ldr	r3, [r7, #4]
 8004094:	2b00      	cmp	r3, #0
 8004096:	d119      	bne.n	80040cc <prvCopyDataToQueue+0x74>
	{
		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8004098:	68fb      	ldr	r3, [r7, #12]
 800409a:	6858      	ldr	r0, [r3, #4]
 800409c:	68fb      	ldr	r3, [r7, #12]
 800409e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80040a0:	461a      	mov	r2, r3
 80040a2:	68b9      	ldr	r1, [r7, #8]
 80040a4:	f002 f876 	bl	8006194 <memcpy>
		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 80040a8:	68fb      	ldr	r3, [r7, #12]
 80040aa:	685a      	ldr	r2, [r3, #4]
 80040ac:	68fb      	ldr	r3, [r7, #12]
 80040ae:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80040b0:	441a      	add	r2, r3
 80040b2:	68fb      	ldr	r3, [r7, #12]
 80040b4:	605a      	str	r2, [r3, #4]
		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 80040b6:	68fb      	ldr	r3, [r7, #12]
 80040b8:	685a      	ldr	r2, [r3, #4]
 80040ba:	68fb      	ldr	r3, [r7, #12]
 80040bc:	689b      	ldr	r3, [r3, #8]
 80040be:	429a      	cmp	r2, r3
 80040c0:	d32b      	bcc.n	800411a <prvCopyDataToQueue+0xc2>
		{
			pxQueue->pcWriteTo = pxQueue->pcHead;
 80040c2:	68fb      	ldr	r3, [r7, #12]
 80040c4:	681a      	ldr	r2, [r3, #0]
 80040c6:	68fb      	ldr	r3, [r7, #12]
 80040c8:	605a      	str	r2, [r3, #4]
 80040ca:	e026      	b.n	800411a <prvCopyDataToQueue+0xc2>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
 80040cc:	68fb      	ldr	r3, [r7, #12]
 80040ce:	68d8      	ldr	r0, [r3, #12]
 80040d0:	68fb      	ldr	r3, [r7, #12]
 80040d2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80040d4:	461a      	mov	r2, r3
 80040d6:	68b9      	ldr	r1, [r7, #8]
 80040d8:	f002 f85c 	bl	8006194 <memcpy>
		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
 80040dc:	68fb      	ldr	r3, [r7, #12]
 80040de:	68da      	ldr	r2, [r3, #12]
 80040e0:	68fb      	ldr	r3, [r7, #12]
 80040e2:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80040e4:	425b      	negs	r3, r3
 80040e6:	441a      	add	r2, r3
 80040e8:	68fb      	ldr	r3, [r7, #12]
 80040ea:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
 80040ec:	68fb      	ldr	r3, [r7, #12]
 80040ee:	68da      	ldr	r2, [r3, #12]
 80040f0:	68fb      	ldr	r3, [r7, #12]
 80040f2:	681b      	ldr	r3, [r3, #0]
 80040f4:	429a      	cmp	r2, r3
 80040f6:	d207      	bcs.n	8004108 <prvCopyDataToQueue+0xb0>
		{
			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
 80040f8:	68fb      	ldr	r3, [r7, #12]
 80040fa:	689a      	ldr	r2, [r3, #8]
 80040fc:	68fb      	ldr	r3, [r7, #12]
 80040fe:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004100:	425b      	negs	r3, r3
 8004102:	441a      	add	r2, r3
 8004104:	68fb      	ldr	r3, [r7, #12]
 8004106:	60da      	str	r2, [r3, #12]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		if( xPosition == queueOVERWRITE )
 8004108:	687b      	ldr	r3, [r7, #4]
 800410a:	2b02      	cmp	r3, #2
 800410c:	d105      	bne.n	800411a <prvCopyDataToQueue+0xc2>
		{
			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
 800410e:	693b      	ldr	r3, [r7, #16]
 8004110:	2b00      	cmp	r3, #0
 8004112:	d002      	beq.n	800411a <prvCopyDataToQueue+0xc2>
			{
				/* An item is not being added but overwritten, so subtract
				one from the recorded number of items in the queue so when
				one is added again below the number of recorded items remains
				correct. */
				--uxMessagesWaiting;
 8004114:	693b      	ldr	r3, [r7, #16]
 8004116:	3b01      	subs	r3, #1
 8004118:	613b      	str	r3, [r7, #16]
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
 800411a:	693b      	ldr	r3, [r7, #16]
 800411c:	1c5a      	adds	r2, r3, #1
 800411e:	68fb      	ldr	r3, [r7, #12]
 8004120:	639a      	str	r2, [r3, #56]	; 0x38

	return xReturn;
 8004122:	697b      	ldr	r3, [r7, #20]
}
 8004124:	4618      	mov	r0, r3
 8004126:	3718      	adds	r7, #24
 8004128:	46bd      	mov	sp, r7
 800412a:	bd80      	pop	{r7, pc}

0800412c <prvCopyDataFromQueue>:
/*-----------------------------------------------------------*/

static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
{
 800412c:	b580      	push	{r7, lr}
 800412e:	b082      	sub	sp, #8
 8004130:	af00      	add	r7, sp, #0
 8004132:	6078      	str	r0, [r7, #4]
 8004134:	6039      	str	r1, [r7, #0]
	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
 8004136:	687b      	ldr	r3, [r7, #4]
 8004138:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 800413a:	2b00      	cmp	r3, #0
 800413c:	d018      	beq.n	8004170 <prvCopyDataFromQueue+0x44>
	{
		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
 800413e:	687b      	ldr	r3, [r7, #4]
 8004140:	68da      	ldr	r2, [r3, #12]
 8004142:	687b      	ldr	r3, [r7, #4]
 8004144:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004146:	441a      	add	r2, r3
 8004148:	687b      	ldr	r3, [r7, #4]
 800414a:	60da      	str	r2, [r3, #12]
		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
 800414c:	687b      	ldr	r3, [r7, #4]
 800414e:	68da      	ldr	r2, [r3, #12]
 8004150:	687b      	ldr	r3, [r7, #4]
 8004152:	689b      	ldr	r3, [r3, #8]
 8004154:	429a      	cmp	r2, r3
 8004156:	d303      	bcc.n	8004160 <prvCopyDataFromQueue+0x34>
		{
			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
 8004158:	687b      	ldr	r3, [r7, #4]
 800415a:	681a      	ldr	r2, [r3, #0]
 800415c:	687b      	ldr	r3, [r7, #4]
 800415e:	60da      	str	r2, [r3, #12]
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
 8004160:	687b      	ldr	r3, [r7, #4]
 8004162:	68d9      	ldr	r1, [r3, #12]
 8004164:	687b      	ldr	r3, [r7, #4]
 8004166:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8004168:	461a      	mov	r2, r3
 800416a:	6838      	ldr	r0, [r7, #0]
 800416c:	f002 f812 	bl	8006194 <memcpy>
	}
}
 8004170:	bf00      	nop
 8004172:	3708      	adds	r7, #8
 8004174:	46bd      	mov	sp, r7
 8004176:	bd80      	pop	{r7, pc}

08004178 <prvUnlockQueue>:
/*-----------------------------------------------------------*/

static void prvUnlockQueue( Queue_t * const pxQueue )
{
 8004178:	b580      	push	{r7, lr}
 800417a:	b084      	sub	sp, #16
 800417c:	af00      	add	r7, sp, #0
 800417e:	6078      	str	r0, [r7, #4]

	/* The lock counts contains the number of extra data items placed or
	removed from the queue while the queue was locked.  When a queue is
	locked items can be added or removed, but the event lists cannot be
	updated. */
	taskENTER_CRITICAL();
 8004180:	f001 fc78 	bl	8005a74 <vPortEnterCritical>
	{
		int8_t cTxLock = pxQueue->cTxLock;
 8004184:	687b      	ldr	r3, [r7, #4]
 8004186:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 800418a:	73fb      	strb	r3, [r7, #15]

		/* See if data was added to the queue while it was locked. */
		while( cTxLock > queueLOCKED_UNMODIFIED )
 800418c:	e011      	b.n	80041b2 <prvUnlockQueue+0x3a>
			}
			#else /* configUSE_QUEUE_SETS */
			{
				/* Tasks that are removed from the event list will get added to
				the pending ready list as the scheduler is still suspended. */
				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
 800418e:	687b      	ldr	r3, [r7, #4]
 8004190:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8004192:	2b00      	cmp	r3, #0
 8004194:	d012      	beq.n	80041bc <prvUnlockQueue+0x44>
				{
					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
 8004196:	687b      	ldr	r3, [r7, #4]
 8004198:	3324      	adds	r3, #36	; 0x24
 800419a:	4618      	mov	r0, r3
 800419c:	f000 fd50 	bl	8004c40 <xTaskRemoveFromEventList>
 80041a0:	4603      	mov	r3, r0
 80041a2:	2b00      	cmp	r3, #0
 80041a4:	d001      	beq.n	80041aa <prvUnlockQueue+0x32>
					{
						/* The task waiting has a higher priority so record that
						a context switch is required. */
						vTaskMissedYield();
 80041a6:	f000 fe27 	bl	8004df8 <vTaskMissedYield>
					break;
				}
			}
			#endif /* configUSE_QUEUE_SETS */

			--cTxLock;
 80041aa:	7bfb      	ldrb	r3, [r7, #15]
 80041ac:	3b01      	subs	r3, #1
 80041ae:	b2db      	uxtb	r3, r3
 80041b0:	73fb      	strb	r3, [r7, #15]
		while( cTxLock > queueLOCKED_UNMODIFIED )
 80041b2:	f997 300f 	ldrsb.w	r3, [r7, #15]
 80041b6:	2b00      	cmp	r3, #0
 80041b8:	dce9      	bgt.n	800418e <prvUnlockQueue+0x16>
 80041ba:	e000      	b.n	80041be <prvUnlockQueue+0x46>
					break;
 80041bc:	bf00      	nop
		}

		pxQueue->cTxLock = queueUNLOCKED;
 80041be:	687b      	ldr	r3, [r7, #4]
 80041c0:	22ff      	movs	r2, #255	; 0xff
 80041c2:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
	}
	taskEXIT_CRITICAL();
 80041c6:	f001 fc85 	bl	8005ad4 <vPortExitCritical>

	/* Do the same for the Rx lock. */
	taskENTER_CRITICAL();
 80041ca:	f001 fc53 	bl	8005a74 <vPortEnterCritical>
	{
		int8_t cRxLock = pxQueue->cRxLock;
 80041ce:	687b      	ldr	r3, [r7, #4]
 80041d0:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
 80041d4:	73bb      	strb	r3, [r7, #14]

		while( cRxLock > queueLOCKED_UNMODIFIED )
 80041d6:	e011      	b.n	80041fc <prvUnlockQueue+0x84>
		{
			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
 80041d8:	687b      	ldr	r3, [r7, #4]
 80041da:	691b      	ldr	r3, [r3, #16]
 80041dc:	2b00      	cmp	r3, #0
 80041de:	d012      	beq.n	8004206 <prvUnlockQueue+0x8e>
			{
				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
 80041e0:	687b      	ldr	r3, [r7, #4]
 80041e2:	3310      	adds	r3, #16
 80041e4:	4618      	mov	r0, r3
 80041e6:	f000 fd2b 	bl	8004c40 <xTaskRemoveFromEventList>
 80041ea:	4603      	mov	r3, r0
 80041ec:	2b00      	cmp	r3, #0
 80041ee:	d001      	beq.n	80041f4 <prvUnlockQueue+0x7c>
				{
					vTaskMissedYield();
 80041f0:	f000 fe02 	bl	8004df8 <vTaskMissedYield>
				else
				{
					mtCOVERAGE_TEST_MARKER();
				}

				--cRxLock;
 80041f4:	7bbb      	ldrb	r3, [r7, #14]
 80041f6:	3b01      	subs	r3, #1
 80041f8:	b2db      	uxtb	r3, r3
 80041fa:	73bb      	strb	r3, [r7, #14]
		while( cRxLock > queueLOCKED_UNMODIFIED )
 80041fc:	f997 300e 	ldrsb.w	r3, [r7, #14]
 8004200:	2b00      	cmp	r3, #0
 8004202:	dce9      	bgt.n	80041d8 <prvUnlockQueue+0x60>
 8004204:	e000      	b.n	8004208 <prvUnlockQueue+0x90>
			}
			else
			{
				break;
 8004206:	bf00      	nop
			}
		}

		pxQueue->cRxLock = queueUNLOCKED;
 8004208:	687b      	ldr	r3, [r7, #4]
 800420a:	22ff      	movs	r2, #255	; 0xff
 800420c:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
	}
	taskEXIT_CRITICAL();
 8004210:	f001 fc60 	bl	8005ad4 <vPortExitCritical>
}
 8004214:	bf00      	nop
 8004216:	3710      	adds	r7, #16
 8004218:	46bd      	mov	sp, r7
 800421a:	bd80      	pop	{r7, pc}

0800421c <prvIsQueueEmpty>:
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
{
 800421c:	b580      	push	{r7, lr}
 800421e:	b084      	sub	sp, #16
 8004220:	af00      	add	r7, sp, #0
 8004222:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8004224:	f001 fc26 	bl	8005a74 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
 8004228:	687b      	ldr	r3, [r7, #4]
 800422a:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 800422c:	2b00      	cmp	r3, #0
 800422e:	d102      	bne.n	8004236 <prvIsQueueEmpty+0x1a>
		{
			xReturn = pdTRUE;
 8004230:	2301      	movs	r3, #1
 8004232:	60fb      	str	r3, [r7, #12]
 8004234:	e001      	b.n	800423a <prvIsQueueEmpty+0x1e>
		}
		else
		{
			xReturn = pdFALSE;
 8004236:	2300      	movs	r3, #0
 8004238:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 800423a:	f001 fc4b 	bl	8005ad4 <vPortExitCritical>

	return xReturn;
 800423e:	68fb      	ldr	r3, [r7, #12]
}
 8004240:	4618      	mov	r0, r3
 8004242:	3710      	adds	r7, #16
 8004244:	46bd      	mov	sp, r7
 8004246:	bd80      	pop	{r7, pc}

08004248 <prvIsQueueFull>:
	return xReturn;
} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
/*-----------------------------------------------------------*/

static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
{
 8004248:	b580      	push	{r7, lr}
 800424a:	b084      	sub	sp, #16
 800424c:	af00      	add	r7, sp, #0
 800424e:	6078      	str	r0, [r7, #4]
BaseType_t xReturn;

	taskENTER_CRITICAL();
 8004250:	f001 fc10 	bl	8005a74 <vPortEnterCritical>
	{
		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
 8004254:	687b      	ldr	r3, [r7, #4]
 8004256:	6b9a      	ldr	r2, [r3, #56]	; 0x38
 8004258:	687b      	ldr	r3, [r7, #4]
 800425a:	6bdb      	ldr	r3, [r3, #60]	; 0x3c
 800425c:	429a      	cmp	r2, r3
 800425e:	d102      	bne.n	8004266 <prvIsQueueFull+0x1e>
		{
			xReturn = pdTRUE;
 8004260:	2301      	movs	r3, #1
 8004262:	60fb      	str	r3, [r7, #12]
 8004264:	e001      	b.n	800426a <prvIsQueueFull+0x22>
		}
		else
		{
			xReturn = pdFALSE;
 8004266:	2300      	movs	r3, #0
 8004268:	60fb      	str	r3, [r7, #12]
		}
	}
	taskEXIT_CRITICAL();
 800426a:	f001 fc33 	bl	8005ad4 <vPortExitCritical>

	return xReturn;
 800426e:	68fb      	ldr	r3, [r7, #12]
}
 8004270:	4618      	mov	r0, r3
 8004272:	3710      	adds	r7, #16
 8004274:	46bd      	mov	sp, r7
 8004276:	bd80      	pop	{r7, pc}

08004278 <vQueueAddToRegistry>:
/*-----------------------------------------------------------*/

#if ( configQUEUE_REGISTRY_SIZE > 0 )

	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
	{
 8004278:	b480      	push	{r7}
 800427a:	b085      	sub	sp, #20
 800427c:	af00      	add	r7, sp, #0
 800427e:	6078      	str	r0, [r7, #4]
 8004280:	6039      	str	r1, [r7, #0]
	UBaseType_t ux;

		/* See if there is an empty space in the registry.  A NULL name denotes
		a free slot. */
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 8004282:	2300      	movs	r3, #0
 8004284:	60fb      	str	r3, [r7, #12]
 8004286:	e014      	b.n	80042b2 <vQueueAddToRegistry+0x3a>
		{
			if( xQueueRegistry[ ux ].pcQueueName == NULL )
 8004288:	4a0f      	ldr	r2, [pc, #60]	; (80042c8 <vQueueAddToRegistry+0x50>)
 800428a:	68fb      	ldr	r3, [r7, #12]
 800428c:	f852 3033 	ldr.w	r3, [r2, r3, lsl #3]
 8004290:	2b00      	cmp	r3, #0
 8004292:	d10b      	bne.n	80042ac <vQueueAddToRegistry+0x34>
			{
				/* Store the information on this queue. */
				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
 8004294:	490c      	ldr	r1, [pc, #48]	; (80042c8 <vQueueAddToRegistry+0x50>)
 8004296:	68fb      	ldr	r3, [r7, #12]
 8004298:	683a      	ldr	r2, [r7, #0]
 800429a:	f841 2033 	str.w	r2, [r1, r3, lsl #3]
				xQueueRegistry[ ux ].xHandle = xQueue;
 800429e:	4a0a      	ldr	r2, [pc, #40]	; (80042c8 <vQueueAddToRegistry+0x50>)
 80042a0:	68fb      	ldr	r3, [r7, #12]
 80042a2:	00db      	lsls	r3, r3, #3
 80042a4:	4413      	add	r3, r2
 80042a6:	687a      	ldr	r2, [r7, #4]
 80042a8:	605a      	str	r2, [r3, #4]

				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
				break;
 80042aa:	e006      	b.n	80042ba <vQueueAddToRegistry+0x42>
		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
 80042ac:	68fb      	ldr	r3, [r7, #12]
 80042ae:	3301      	adds	r3, #1
 80042b0:	60fb      	str	r3, [r7, #12]
 80042b2:	68fb      	ldr	r3, [r7, #12]
 80042b4:	2b07      	cmp	r3, #7
 80042b6:	d9e7      	bls.n	8004288 <vQueueAddToRegistry+0x10>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}
	}
 80042b8:	bf00      	nop
 80042ba:	bf00      	nop
 80042bc:	3714      	adds	r7, #20
 80042be:	46bd      	mov	sp, r7
 80042c0:	f85d 7b04 	ldr.w	r7, [sp], #4
 80042c4:	4770      	bx	lr
 80042c6:	bf00      	nop
 80042c8:	200008d0 	.word	0x200008d0

080042cc <vQueueWaitForMessageRestricted>:
/*-----------------------------------------------------------*/

#if ( configUSE_TIMERS == 1 )

	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 80042cc:	b580      	push	{r7, lr}
 80042ce:	b086      	sub	sp, #24
 80042d0:	af00      	add	r7, sp, #0
 80042d2:	60f8      	str	r0, [r7, #12]
 80042d4:	60b9      	str	r1, [r7, #8]
 80042d6:	607a      	str	r2, [r7, #4]
	Queue_t * const pxQueue = xQueue;
 80042d8:	68fb      	ldr	r3, [r7, #12]
 80042da:	617b      	str	r3, [r7, #20]
		will not actually cause the task to block, just place it on a blocked
		list.  It will not block until the scheduler is unlocked - at which
		time a yield will be performed.  If an item is added to the queue while
		the queue is locked, and the calling task blocks on the queue, then the
		calling task will be immediately unblocked when the queue is unlocked. */
		prvLockQueue( pxQueue );
 80042dc:	f001 fbca 	bl	8005a74 <vPortEnterCritical>
 80042e0:	697b      	ldr	r3, [r7, #20]
 80042e2:	f893 3044 	ldrb.w	r3, [r3, #68]	; 0x44
 80042e6:	b25b      	sxtb	r3, r3
 80042e8:	f1b3 3fff 	cmp.w	r3, #4294967295
 80042ec:	d103      	bne.n	80042f6 <vQueueWaitForMessageRestricted+0x2a>
 80042ee:	697b      	ldr	r3, [r7, #20]
 80042f0:	2200      	movs	r2, #0
 80042f2:	f883 2044 	strb.w	r2, [r3, #68]	; 0x44
 80042f6:	697b      	ldr	r3, [r7, #20]
 80042f8:	f893 3045 	ldrb.w	r3, [r3, #69]	; 0x45
 80042fc:	b25b      	sxtb	r3, r3
 80042fe:	f1b3 3fff 	cmp.w	r3, #4294967295
 8004302:	d103      	bne.n	800430c <vQueueWaitForMessageRestricted+0x40>
 8004304:	697b      	ldr	r3, [r7, #20]
 8004306:	2200      	movs	r2, #0
 8004308:	f883 2045 	strb.w	r2, [r3, #69]	; 0x45
 800430c:	f001 fbe2 	bl	8005ad4 <vPortExitCritical>
		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
 8004310:	697b      	ldr	r3, [r7, #20]
 8004312:	6b9b      	ldr	r3, [r3, #56]	; 0x38
 8004314:	2b00      	cmp	r3, #0
 8004316:	d106      	bne.n	8004326 <vQueueWaitForMessageRestricted+0x5a>
		{
			/* There is nothing in the queue, block for the specified period. */
			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
 8004318:	697b      	ldr	r3, [r7, #20]
 800431a:	3324      	adds	r3, #36	; 0x24
 800431c:	687a      	ldr	r2, [r7, #4]
 800431e:	68b9      	ldr	r1, [r7, #8]
 8004320:	4618      	mov	r0, r3
 8004322:	f000 fc61 	bl	8004be8 <vTaskPlaceOnEventListRestricted>
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
		prvUnlockQueue( pxQueue );
 8004326:	6978      	ldr	r0, [r7, #20]
 8004328:	f7ff ff26 	bl	8004178 <prvUnlockQueue>
	}
 800432c:	bf00      	nop
 800432e:	3718      	adds	r7, #24
 8004330:	46bd      	mov	sp, r7
 8004332:	bd80      	pop	{r7, pc}

08004334 <xTaskCreateStatic>:
									const uint32_t ulStackDepth,
									void * const pvParameters,
									UBaseType_t uxPriority,
									StackType_t * const puxStackBuffer,
									StaticTask_t * const pxTaskBuffer )
	{
 8004334:	b580      	push	{r7, lr}
 8004336:	b08e      	sub	sp, #56	; 0x38
 8004338:	af04      	add	r7, sp, #16
 800433a:	60f8      	str	r0, [r7, #12]
 800433c:	60b9      	str	r1, [r7, #8]
 800433e:	607a      	str	r2, [r7, #4]
 8004340:	603b      	str	r3, [r7, #0]
	TCB_t *pxNewTCB;
	TaskHandle_t xReturn;

		configASSERT( puxStackBuffer != NULL );
 8004342:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 8004344:	2b00      	cmp	r3, #0
 8004346:	d10a      	bne.n	800435e <xTaskCreateStatic+0x2a>
	__asm volatile
 8004348:	f04f 0350 	mov.w	r3, #80	; 0x50
 800434c:	f383 8811 	msr	BASEPRI, r3
 8004350:	f3bf 8f6f 	isb	sy
 8004354:	f3bf 8f4f 	dsb	sy
 8004358:	623b      	str	r3, [r7, #32]
}
 800435a:	bf00      	nop
 800435c:	e7fe      	b.n	800435c <xTaskCreateStatic+0x28>
		configASSERT( pxTaskBuffer != NULL );
 800435e:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 8004360:	2b00      	cmp	r3, #0
 8004362:	d10a      	bne.n	800437a <xTaskCreateStatic+0x46>
	__asm volatile
 8004364:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004368:	f383 8811 	msr	BASEPRI, r3
 800436c:	f3bf 8f6f 	isb	sy
 8004370:	f3bf 8f4f 	dsb	sy
 8004374:	61fb      	str	r3, [r7, #28]
}
 8004376:	bf00      	nop
 8004378:	e7fe      	b.n	8004378 <xTaskCreateStatic+0x44>
		#if( configASSERT_DEFINED == 1 )
		{
			/* Sanity check that the size of the structure used to declare a
			variable of type StaticTask_t equals the size of the real task
			structure. */
			volatile size_t xSize = sizeof( StaticTask_t );
 800437a:	23a8      	movs	r3, #168	; 0xa8
 800437c:	613b      	str	r3, [r7, #16]
			configASSERT( xSize == sizeof( TCB_t ) );
 800437e:	693b      	ldr	r3, [r7, #16]
 8004380:	2ba8      	cmp	r3, #168	; 0xa8
 8004382:	d00a      	beq.n	800439a <xTaskCreateStatic+0x66>
	__asm volatile
 8004384:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004388:	f383 8811 	msr	BASEPRI, r3
 800438c:	f3bf 8f6f 	isb	sy
 8004390:	f3bf 8f4f 	dsb	sy
 8004394:	61bb      	str	r3, [r7, #24]
}
 8004396:	bf00      	nop
 8004398:	e7fe      	b.n	8004398 <xTaskCreateStatic+0x64>
			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
 800439a:	693b      	ldr	r3, [r7, #16]
		}
		#endif /* configASSERT_DEFINED */


		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
 800439c:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 800439e:	2b00      	cmp	r3, #0
 80043a0:	d01e      	beq.n	80043e0 <xTaskCreateStatic+0xac>
 80043a2:	6b7b      	ldr	r3, [r7, #52]	; 0x34
 80043a4:	2b00      	cmp	r3, #0
 80043a6:	d01b      	beq.n	80043e0 <xTaskCreateStatic+0xac>
		{
			/* The memory used for the task's TCB and stack are passed into this
			function - use them. */
			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
 80043a8:	6bbb      	ldr	r3, [r7, #56]	; 0x38
 80043aa:	627b      	str	r3, [r7, #36]	; 0x24
			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
 80043ac:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80043ae:	6b7a      	ldr	r2, [r7, #52]	; 0x34
 80043b0:	631a      	str	r2, [r3, #48]	; 0x30

			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created statically in case the task is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
 80043b2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80043b4:	2202      	movs	r2, #2
 80043b6:	f883 20a5 	strb.w	r2, [r3, #165]	; 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
 80043ba:	2300      	movs	r3, #0
 80043bc:	9303      	str	r3, [sp, #12]
 80043be:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80043c0:	9302      	str	r3, [sp, #8]
 80043c2:	f107 0314 	add.w	r3, r7, #20
 80043c6:	9301      	str	r3, [sp, #4]
 80043c8:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 80043ca:	9300      	str	r3, [sp, #0]
 80043cc:	683b      	ldr	r3, [r7, #0]
 80043ce:	687a      	ldr	r2, [r7, #4]
 80043d0:	68b9      	ldr	r1, [r7, #8]
 80043d2:	68f8      	ldr	r0, [r7, #12]
 80043d4:	f000 f850 	bl	8004478 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 80043d8:	6a78      	ldr	r0, [r7, #36]	; 0x24
 80043da:	f000 f8f3 	bl	80045c4 <prvAddNewTaskToReadyList>
 80043de:	e001      	b.n	80043e4 <xTaskCreateStatic+0xb0>
		}
		else
		{
			xReturn = NULL;
 80043e0:	2300      	movs	r3, #0
 80043e2:	617b      	str	r3, [r7, #20]
		}

		return xReturn;
 80043e4:	697b      	ldr	r3, [r7, #20]
	}
 80043e6:	4618      	mov	r0, r3
 80043e8:	3728      	adds	r7, #40	; 0x28
 80043ea:	46bd      	mov	sp, r7
 80043ec:	bd80      	pop	{r7, pc}

080043ee <xTaskCreate>:
							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
							const configSTACK_DEPTH_TYPE usStackDepth,
							void * const pvParameters,
							UBaseType_t uxPriority,
							TaskHandle_t * const pxCreatedTask )
	{
 80043ee:	b580      	push	{r7, lr}
 80043f0:	b08c      	sub	sp, #48	; 0x30
 80043f2:	af04      	add	r7, sp, #16
 80043f4:	60f8      	str	r0, [r7, #12]
 80043f6:	60b9      	str	r1, [r7, #8]
 80043f8:	603b      	str	r3, [r7, #0]
 80043fa:	4613      	mov	r3, r2
 80043fc:	80fb      	strh	r3, [r7, #6]
		#else /* portSTACK_GROWTH */
		{
		StackType_t *pxStack;

			/* Allocate space for the stack used by the task being created. */
			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
 80043fe:	88fb      	ldrh	r3, [r7, #6]
 8004400:	009b      	lsls	r3, r3, #2
 8004402:	4618      	mov	r0, r3
 8004404:	f001 fc58 	bl	8005cb8 <pvPortMalloc>
 8004408:	6178      	str	r0, [r7, #20]

			if( pxStack != NULL )
 800440a:	697b      	ldr	r3, [r7, #20]
 800440c:	2b00      	cmp	r3, #0
 800440e:	d00e      	beq.n	800442e <xTaskCreate+0x40>
			{
				/* Allocate space for the TCB. */
				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
 8004410:	20a8      	movs	r0, #168	; 0xa8
 8004412:	f001 fc51 	bl	8005cb8 <pvPortMalloc>
 8004416:	61f8      	str	r0, [r7, #28]

				if( pxNewTCB != NULL )
 8004418:	69fb      	ldr	r3, [r7, #28]
 800441a:	2b00      	cmp	r3, #0
 800441c:	d003      	beq.n	8004426 <xTaskCreate+0x38>
				{
					/* Store the stack location in the TCB. */
					pxNewTCB->pxStack = pxStack;
 800441e:	69fb      	ldr	r3, [r7, #28]
 8004420:	697a      	ldr	r2, [r7, #20]
 8004422:	631a      	str	r2, [r3, #48]	; 0x30
 8004424:	e005      	b.n	8004432 <xTaskCreate+0x44>
				}
				else
				{
					/* The stack cannot be used as the TCB was not created.  Free
					it again. */
					vPortFree( pxStack );
 8004426:	6978      	ldr	r0, [r7, #20]
 8004428:	f001 fd12 	bl	8005e50 <vPortFree>
 800442c:	e001      	b.n	8004432 <xTaskCreate+0x44>
				}
			}
			else
			{
				pxNewTCB = NULL;
 800442e:	2300      	movs	r3, #0
 8004430:	61fb      	str	r3, [r7, #28]
			}
		}
		#endif /* portSTACK_GROWTH */

		if( pxNewTCB != NULL )
 8004432:	69fb      	ldr	r3, [r7, #28]
 8004434:	2b00      	cmp	r3, #0
 8004436:	d017      	beq.n	8004468 <xTaskCreate+0x7a>
		{
			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
			{
				/* Tasks can be created statically or dynamically, so note this
				task was created dynamically in case it is later deleted. */
				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
 8004438:	69fb      	ldr	r3, [r7, #28]
 800443a:	2200      	movs	r2, #0
 800443c:	f883 20a5 	strb.w	r2, [r3, #165]	; 0xa5
			}
			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */

			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
 8004440:	88fa      	ldrh	r2, [r7, #6]
 8004442:	2300      	movs	r3, #0
 8004444:	9303      	str	r3, [sp, #12]
 8004446:	69fb      	ldr	r3, [r7, #28]
 8004448:	9302      	str	r3, [sp, #8]
 800444a:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 800444c:	9301      	str	r3, [sp, #4]
 800444e:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004450:	9300      	str	r3, [sp, #0]
 8004452:	683b      	ldr	r3, [r7, #0]
 8004454:	68b9      	ldr	r1, [r7, #8]
 8004456:	68f8      	ldr	r0, [r7, #12]
 8004458:	f000 f80e 	bl	8004478 <prvInitialiseNewTask>
			prvAddNewTaskToReadyList( pxNewTCB );
 800445c:	69f8      	ldr	r0, [r7, #28]
 800445e:	f000 f8b1 	bl	80045c4 <prvAddNewTaskToReadyList>
			xReturn = pdPASS;
 8004462:	2301      	movs	r3, #1
 8004464:	61bb      	str	r3, [r7, #24]
 8004466:	e002      	b.n	800446e <xTaskCreate+0x80>
		}
		else
		{
			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
 8004468:	f04f 33ff 	mov.w	r3, #4294967295
 800446c:	61bb      	str	r3, [r7, #24]
		}

		return xReturn;
 800446e:	69bb      	ldr	r3, [r7, #24]
	}
 8004470:	4618      	mov	r0, r3
 8004472:	3720      	adds	r7, #32
 8004474:	46bd      	mov	sp, r7
 8004476:	bd80      	pop	{r7, pc}

08004478 <prvInitialiseNewTask>:
									void * const pvParameters,
									UBaseType_t uxPriority,
									TaskHandle_t * const pxCreatedTask,
									TCB_t *pxNewTCB,
									const MemoryRegion_t * const xRegions )
{
 8004478:	b580      	push	{r7, lr}
 800447a:	b088      	sub	sp, #32
 800447c:	af00      	add	r7, sp, #0
 800447e:	60f8      	str	r0, [r7, #12]
 8004480:	60b9      	str	r1, [r7, #8]
 8004482:	607a      	str	r2, [r7, #4]
 8004484:	603b      	str	r3, [r7, #0]

	/* Avoid dependency on memset() if it is not required. */
	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
	{
		/* Fill the stack with a known value to assist debugging. */
		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
 8004486:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004488:	6b18      	ldr	r0, [r3, #48]	; 0x30
 800448a:	687b      	ldr	r3, [r7, #4]
 800448c:	009b      	lsls	r3, r3, #2
 800448e:	461a      	mov	r2, r3
 8004490:	21a5      	movs	r1, #165	; 0xa5
 8004492:	f001 fdfb 	bl	800608c <memset>
	grows from high memory to low (as per the 80x86) or vice versa.
	portSTACK_GROWTH is used to make the result positive or negative as required
	by the port. */
	#if( portSTACK_GROWTH < 0 )
	{
		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
 8004496:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004498:	6b1a      	ldr	r2, [r3, #48]	; 0x30
 800449a:	687b      	ldr	r3, [r7, #4]
 800449c:	f103 4380 	add.w	r3, r3, #1073741824	; 0x40000000
 80044a0:	3b01      	subs	r3, #1
 80044a2:	009b      	lsls	r3, r3, #2
 80044a4:	4413      	add	r3, r2
 80044a6:	61bb      	str	r3, [r7, #24]
		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
 80044a8:	69bb      	ldr	r3, [r7, #24]
 80044aa:	f023 0307 	bic.w	r3, r3, #7
 80044ae:	61bb      	str	r3, [r7, #24]

		/* Check the alignment of the calculated top of stack is correct. */
		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
 80044b0:	69bb      	ldr	r3, [r7, #24]
 80044b2:	f003 0307 	and.w	r3, r3, #7
 80044b6:	2b00      	cmp	r3, #0
 80044b8:	d00a      	beq.n	80044d0 <prvInitialiseNewTask+0x58>
	__asm volatile
 80044ba:	f04f 0350 	mov.w	r3, #80	; 0x50
 80044be:	f383 8811 	msr	BASEPRI, r3
 80044c2:	f3bf 8f6f 	isb	sy
 80044c6:	f3bf 8f4f 	dsb	sy
 80044ca:	617b      	str	r3, [r7, #20]
}
 80044cc:	bf00      	nop
 80044ce:	e7fe      	b.n	80044ce <prvInitialiseNewTask+0x56>
		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
	}
	#endif /* portSTACK_GROWTH */

	/* Store the task name in the TCB. */
	if( pcName != NULL )
 80044d0:	68bb      	ldr	r3, [r7, #8]
 80044d2:	2b00      	cmp	r3, #0
 80044d4:	d01f      	beq.n	8004516 <prvInitialiseNewTask+0x9e>
	{
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 80044d6:	2300      	movs	r3, #0
 80044d8:	61fb      	str	r3, [r7, #28]
 80044da:	e012      	b.n	8004502 <prvInitialiseNewTask+0x8a>
		{
			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
 80044dc:	68ba      	ldr	r2, [r7, #8]
 80044de:	69fb      	ldr	r3, [r7, #28]
 80044e0:	4413      	add	r3, r2
 80044e2:	7819      	ldrb	r1, [r3, #0]
 80044e4:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 80044e6:	69fb      	ldr	r3, [r7, #28]
 80044e8:	4413      	add	r3, r2
 80044ea:	3334      	adds	r3, #52	; 0x34
 80044ec:	460a      	mov	r2, r1
 80044ee:	701a      	strb	r2, [r3, #0]

			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
			configMAX_TASK_NAME_LEN characters just in case the memory after the
			string is not accessible (extremely unlikely). */
			if( pcName[ x ] == ( char ) 0x00 )
 80044f0:	68ba      	ldr	r2, [r7, #8]
 80044f2:	69fb      	ldr	r3, [r7, #28]
 80044f4:	4413      	add	r3, r2
 80044f6:	781b      	ldrb	r3, [r3, #0]
 80044f8:	2b00      	cmp	r3, #0
 80044fa:	d006      	beq.n	800450a <prvInitialiseNewTask+0x92>
		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
 80044fc:	69fb      	ldr	r3, [r7, #28]
 80044fe:	3301      	adds	r3, #1
 8004500:	61fb      	str	r3, [r7, #28]
 8004502:	69fb      	ldr	r3, [r7, #28]
 8004504:	2b0f      	cmp	r3, #15
 8004506:	d9e9      	bls.n	80044dc <prvInitialiseNewTask+0x64>
 8004508:	e000      	b.n	800450c <prvInitialiseNewTask+0x94>
			{
				break;
 800450a:	bf00      	nop
			}
		}

		/* Ensure the name string is terminated in the case that the string length
		was greater or equal to configMAX_TASK_NAME_LEN. */
		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
 800450c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800450e:	2200      	movs	r2, #0
 8004510:	f883 2043 	strb.w	r2, [r3, #67]	; 0x43
 8004514:	e003      	b.n	800451e <prvInitialiseNewTask+0xa6>
	}
	else
	{
		/* The task has not been given a name, so just ensure there is a NULL
		terminator when it is read out. */
		pxNewTCB->pcTaskName[ 0 ] = 0x00;
 8004516:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004518:	2200      	movs	r2, #0
 800451a:	f883 2034 	strb.w	r2, [r3, #52]	; 0x34
	}

	/* This is used as an array index so must ensure it's not too large.  First
	remove the privilege bit if one is present. */
	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
 800451e:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004520:	2b37      	cmp	r3, #55	; 0x37
 8004522:	d901      	bls.n	8004528 <prvInitialiseNewTask+0xb0>
	{
		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
 8004524:	2337      	movs	r3, #55	; 0x37
 8004526:	62bb      	str	r3, [r7, #40]	; 0x28
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	pxNewTCB->uxPriority = uxPriority;
 8004528:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800452a:	6aba      	ldr	r2, [r7, #40]	; 0x28
 800452c:	62da      	str	r2, [r3, #44]	; 0x2c
	#if ( configUSE_MUTEXES == 1 )
	{
		pxNewTCB->uxBasePriority = uxPriority;
 800452e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004530:	6aba      	ldr	r2, [r7, #40]	; 0x28
 8004532:	64da      	str	r2, [r3, #76]	; 0x4c
		pxNewTCB->uxMutexesHeld = 0;
 8004534:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004536:	2200      	movs	r2, #0
 8004538:	651a      	str	r2, [r3, #80]	; 0x50
	}
	#endif /* configUSE_MUTEXES */

	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
 800453a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800453c:	3304      	adds	r3, #4
 800453e:	4618      	mov	r0, r3
 8004540:	f7ff f978 	bl	8003834 <vListInitialiseItem>
	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
 8004544:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004546:	3318      	adds	r3, #24
 8004548:	4618      	mov	r0, r3
 800454a:	f7ff f973 	bl	8003834 <vListInitialiseItem>

	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
	back to	the containing TCB from a generic item in a list. */
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
 800454e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004550:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 8004552:	611a      	str	r2, [r3, #16]

	/* Event lists are always in priority order. */
	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8004554:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8004556:	f1c3 0238 	rsb	r2, r3, #56	; 0x38
 800455a:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800455c:	619a      	str	r2, [r3, #24]
	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
 800455e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004560:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 8004562:	625a      	str	r2, [r3, #36]	; 0x24
	}
	#endif

	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
	{
		pxNewTCB->ulNotifiedValue = 0;
 8004564:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004566:	2200      	movs	r2, #0
 8004568:	f8c3 20a0 	str.w	r2, [r3, #160]	; 0xa0
		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
 800456c:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800456e:	2200      	movs	r2, #0
 8004570:	f883 20a4 	strb.w	r2, [r3, #164]	; 0xa4
	#if ( configUSE_NEWLIB_REENTRANT == 1 )
	{
		/* Initialise this task's Newlib reent structure.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
 8004574:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004576:	3354      	adds	r3, #84	; 0x54
 8004578:	224c      	movs	r2, #76	; 0x4c
 800457a:	2100      	movs	r1, #0
 800457c:	4618      	mov	r0, r3
 800457e:	f001 fd85 	bl	800608c <memset>
 8004582:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004584:	4a0c      	ldr	r2, [pc, #48]	; (80045b8 <prvInitialiseNewTask+0x140>)
 8004586:	659a      	str	r2, [r3, #88]	; 0x58
 8004588:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 800458a:	4a0c      	ldr	r2, [pc, #48]	; (80045bc <prvInitialiseNewTask+0x144>)
 800458c:	65da      	str	r2, [r3, #92]	; 0x5c
 800458e:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 8004590:	4a0b      	ldr	r2, [pc, #44]	; (80045c0 <prvInitialiseNewTask+0x148>)
 8004592:	661a      	str	r2, [r3, #96]	; 0x60
			}
			#endif /* portSTACK_GROWTH */
		}
		#else /* portHAS_STACK_OVERFLOW_CHECKING */
		{
			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
 8004594:	683a      	ldr	r2, [r7, #0]
 8004596:	68f9      	ldr	r1, [r7, #12]
 8004598:	69b8      	ldr	r0, [r7, #24]
 800459a:	f001 f941 	bl	8005820 <pxPortInitialiseStack>
 800459e:	4602      	mov	r2, r0
 80045a0:	6b3b      	ldr	r3, [r7, #48]	; 0x30
 80045a2:	601a      	str	r2, [r3, #0]
		}
		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
	}
	#endif /* portUSING_MPU_WRAPPERS */

	if( pxCreatedTask != NULL )
 80045a4:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 80045a6:	2b00      	cmp	r3, #0
 80045a8:	d002      	beq.n	80045b0 <prvInitialiseNewTask+0x138>
	{
		/* Pass the handle out in an anonymous way.  The handle can be used to
		change the created task's priority, delete the created task, etc.*/
		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
 80045aa:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 80045ac:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 80045ae:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 80045b0:	bf00      	nop
 80045b2:	3720      	adds	r7, #32
 80045b4:	46bd      	mov	sp, r7
 80045b6:	bd80      	pop	{r7, pc}
 80045b8:	20004b64 	.word	0x20004b64
 80045bc:	20004bcc 	.word	0x20004bcc
 80045c0:	20004c34 	.word	0x20004c34

080045c4 <prvAddNewTaskToReadyList>:
/*-----------------------------------------------------------*/

static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
{
 80045c4:	b580      	push	{r7, lr}
 80045c6:	b082      	sub	sp, #8
 80045c8:	af00      	add	r7, sp, #0
 80045ca:	6078      	str	r0, [r7, #4]
	/* Ensure interrupts don't access the task lists while the lists are being
	updated. */
	taskENTER_CRITICAL();
 80045cc:	f001 fa52 	bl	8005a74 <vPortEnterCritical>
	{
		uxCurrentNumberOfTasks++;
 80045d0:	4b2d      	ldr	r3, [pc, #180]	; (8004688 <prvAddNewTaskToReadyList+0xc4>)
 80045d2:	681b      	ldr	r3, [r3, #0]
 80045d4:	3301      	adds	r3, #1
 80045d6:	4a2c      	ldr	r2, [pc, #176]	; (8004688 <prvAddNewTaskToReadyList+0xc4>)
 80045d8:	6013      	str	r3, [r2, #0]
		if( pxCurrentTCB == NULL )
 80045da:	4b2c      	ldr	r3, [pc, #176]	; (800468c <prvAddNewTaskToReadyList+0xc8>)
 80045dc:	681b      	ldr	r3, [r3, #0]
 80045de:	2b00      	cmp	r3, #0
 80045e0:	d109      	bne.n	80045f6 <prvAddNewTaskToReadyList+0x32>
		{
			/* There are no other tasks, or all the other tasks are in
			the suspended state - make this the current task. */
			pxCurrentTCB = pxNewTCB;
 80045e2:	4a2a      	ldr	r2, [pc, #168]	; (800468c <prvAddNewTaskToReadyList+0xc8>)
 80045e4:	687b      	ldr	r3, [r7, #4]
 80045e6:	6013      	str	r3, [r2, #0]

			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
 80045e8:	4b27      	ldr	r3, [pc, #156]	; (8004688 <prvAddNewTaskToReadyList+0xc4>)
 80045ea:	681b      	ldr	r3, [r3, #0]
 80045ec:	2b01      	cmp	r3, #1
 80045ee:	d110      	bne.n	8004612 <prvAddNewTaskToReadyList+0x4e>
			{
				/* This is the first task to be created so do the preliminary
				initialisation required.  We will not recover if this call
				fails, but we will report the failure. */
				prvInitialiseTaskLists();
 80045f0:	f000 fc26 	bl	8004e40 <prvInitialiseTaskLists>
 80045f4:	e00d      	b.n	8004612 <prvAddNewTaskToReadyList+0x4e>
		else
		{
			/* If the scheduler is not already running, make this task the
			current task if it is the highest priority task to be created
			so far. */
			if( xSchedulerRunning == pdFALSE )
 80045f6:	4b26      	ldr	r3, [pc, #152]	; (8004690 <prvAddNewTaskToReadyList+0xcc>)
 80045f8:	681b      	ldr	r3, [r3, #0]
 80045fa:	2b00      	cmp	r3, #0
 80045fc:	d109      	bne.n	8004612 <prvAddNewTaskToReadyList+0x4e>
			{
				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
 80045fe:	4b23      	ldr	r3, [pc, #140]	; (800468c <prvAddNewTaskToReadyList+0xc8>)
 8004600:	681b      	ldr	r3, [r3, #0]
 8004602:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004604:	687b      	ldr	r3, [r7, #4]
 8004606:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004608:	429a      	cmp	r2, r3
 800460a:	d802      	bhi.n	8004612 <prvAddNewTaskToReadyList+0x4e>
				{
					pxCurrentTCB = pxNewTCB;
 800460c:	4a1f      	ldr	r2, [pc, #124]	; (800468c <prvAddNewTaskToReadyList+0xc8>)
 800460e:	687b      	ldr	r3, [r7, #4]
 8004610:	6013      	str	r3, [r2, #0]
			{
				mtCOVERAGE_TEST_MARKER();
			}
		}

		uxTaskNumber++;
 8004612:	4b20      	ldr	r3, [pc, #128]	; (8004694 <prvAddNewTaskToReadyList+0xd0>)
 8004614:	681b      	ldr	r3, [r3, #0]
 8004616:	3301      	adds	r3, #1
 8004618:	4a1e      	ldr	r2, [pc, #120]	; (8004694 <prvAddNewTaskToReadyList+0xd0>)
 800461a:	6013      	str	r3, [r2, #0]

		#if ( configUSE_TRACE_FACILITY == 1 )
		{
			/* Add a counter into the TCB for tracing only. */
			pxNewTCB->uxTCBNumber = uxTaskNumber;
 800461c:	4b1d      	ldr	r3, [pc, #116]	; (8004694 <prvAddNewTaskToReadyList+0xd0>)
 800461e:	681a      	ldr	r2, [r3, #0]
 8004620:	687b      	ldr	r3, [r7, #4]
 8004622:	645a      	str	r2, [r3, #68]	; 0x44
		}
		#endif /* configUSE_TRACE_FACILITY */
		traceTASK_CREATE( pxNewTCB );

		prvAddTaskToReadyList( pxNewTCB );
 8004624:	687b      	ldr	r3, [r7, #4]
 8004626:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004628:	4b1b      	ldr	r3, [pc, #108]	; (8004698 <prvAddNewTaskToReadyList+0xd4>)
 800462a:	681b      	ldr	r3, [r3, #0]
 800462c:	429a      	cmp	r2, r3
 800462e:	d903      	bls.n	8004638 <prvAddNewTaskToReadyList+0x74>
 8004630:	687b      	ldr	r3, [r7, #4]
 8004632:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004634:	4a18      	ldr	r2, [pc, #96]	; (8004698 <prvAddNewTaskToReadyList+0xd4>)
 8004636:	6013      	str	r3, [r2, #0]
 8004638:	687b      	ldr	r3, [r7, #4]
 800463a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 800463c:	4613      	mov	r3, r2
 800463e:	009b      	lsls	r3, r3, #2
 8004640:	4413      	add	r3, r2
 8004642:	009b      	lsls	r3, r3, #2
 8004644:	4a15      	ldr	r2, [pc, #84]	; (800469c <prvAddNewTaskToReadyList+0xd8>)
 8004646:	441a      	add	r2, r3
 8004648:	687b      	ldr	r3, [r7, #4]
 800464a:	3304      	adds	r3, #4
 800464c:	4619      	mov	r1, r3
 800464e:	4610      	mov	r0, r2
 8004650:	f7ff f8fd 	bl	800384e <vListInsertEnd>

		portSETUP_TCB( pxNewTCB );
	}
	taskEXIT_CRITICAL();
 8004654:	f001 fa3e 	bl	8005ad4 <vPortExitCritical>

	if( xSchedulerRunning != pdFALSE )
 8004658:	4b0d      	ldr	r3, [pc, #52]	; (8004690 <prvAddNewTaskToReadyList+0xcc>)
 800465a:	681b      	ldr	r3, [r3, #0]
 800465c:	2b00      	cmp	r3, #0
 800465e:	d00e      	beq.n	800467e <prvAddNewTaskToReadyList+0xba>
	{
		/* If the created task is of a higher priority than the current task
		then it should run now. */
		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
 8004660:	4b0a      	ldr	r3, [pc, #40]	; (800468c <prvAddNewTaskToReadyList+0xc8>)
 8004662:	681b      	ldr	r3, [r3, #0]
 8004664:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004666:	687b      	ldr	r3, [r7, #4]
 8004668:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 800466a:	429a      	cmp	r2, r3
 800466c:	d207      	bcs.n	800467e <prvAddNewTaskToReadyList+0xba>
		{
			taskYIELD_IF_USING_PREEMPTION();
 800466e:	4b0c      	ldr	r3, [pc, #48]	; (80046a0 <prvAddNewTaskToReadyList+0xdc>)
 8004670:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8004674:	601a      	str	r2, [r3, #0]
 8004676:	f3bf 8f4f 	dsb	sy
 800467a:	f3bf 8f6f 	isb	sy
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 800467e:	bf00      	nop
 8004680:	3708      	adds	r7, #8
 8004682:	46bd      	mov	sp, r7
 8004684:	bd80      	pop	{r7, pc}
 8004686:	bf00      	nop
 8004688:	20000de4 	.word	0x20000de4
 800468c:	20000910 	.word	0x20000910
 8004690:	20000df0 	.word	0x20000df0
 8004694:	20000e00 	.word	0x20000e00
 8004698:	20000dec 	.word	0x20000dec
 800469c:	20000914 	.word	0x20000914
 80046a0:	e000ed04 	.word	0xe000ed04

080046a4 <vTaskDelay>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelay == 1 )

	void vTaskDelay( const TickType_t xTicksToDelay )
	{
 80046a4:	b580      	push	{r7, lr}
 80046a6:	b084      	sub	sp, #16
 80046a8:	af00      	add	r7, sp, #0
 80046aa:	6078      	str	r0, [r7, #4]
	BaseType_t xAlreadyYielded = pdFALSE;
 80046ac:	2300      	movs	r3, #0
 80046ae:	60fb      	str	r3, [r7, #12]

		/* A delay time of zero just forces a reschedule. */
		if( xTicksToDelay > ( TickType_t ) 0U )
 80046b0:	687b      	ldr	r3, [r7, #4]
 80046b2:	2b00      	cmp	r3, #0
 80046b4:	d017      	beq.n	80046e6 <vTaskDelay+0x42>
		{
			configASSERT( uxSchedulerSuspended == 0 );
 80046b6:	4b13      	ldr	r3, [pc, #76]	; (8004704 <vTaskDelay+0x60>)
 80046b8:	681b      	ldr	r3, [r3, #0]
 80046ba:	2b00      	cmp	r3, #0
 80046bc:	d00a      	beq.n	80046d4 <vTaskDelay+0x30>
	__asm volatile
 80046be:	f04f 0350 	mov.w	r3, #80	; 0x50
 80046c2:	f383 8811 	msr	BASEPRI, r3
 80046c6:	f3bf 8f6f 	isb	sy
 80046ca:	f3bf 8f4f 	dsb	sy
 80046ce:	60bb      	str	r3, [r7, #8]
}
 80046d0:	bf00      	nop
 80046d2:	e7fe      	b.n	80046d2 <vTaskDelay+0x2e>
			vTaskSuspendAll();
 80046d4:	f000 f88a 	bl	80047ec <vTaskSuspendAll>
				list or removed from the blocked list until the scheduler
				is resumed.

				This task cannot be in an event list as it is the currently
				executing task. */
				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
 80046d8:	2100      	movs	r1, #0
 80046da:	6878      	ldr	r0, [r7, #4]
 80046dc:	f000 fcfe 	bl	80050dc <prvAddCurrentTaskToDelayedList>
			}
			xAlreadyYielded = xTaskResumeAll();
 80046e0:	f000 f892 	bl	8004808 <xTaskResumeAll>
 80046e4:	60f8      	str	r0, [r7, #12]
			mtCOVERAGE_TEST_MARKER();
		}

		/* Force a reschedule if xTaskResumeAll has not already done so, we may
		have put ourselves to sleep. */
		if( xAlreadyYielded == pdFALSE )
 80046e6:	68fb      	ldr	r3, [r7, #12]
 80046e8:	2b00      	cmp	r3, #0
 80046ea:	d107      	bne.n	80046fc <vTaskDelay+0x58>
		{
			portYIELD_WITHIN_API();
 80046ec:	4b06      	ldr	r3, [pc, #24]	; (8004708 <vTaskDelay+0x64>)
 80046ee:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 80046f2:	601a      	str	r2, [r3, #0]
 80046f4:	f3bf 8f4f 	dsb	sy
 80046f8:	f3bf 8f6f 	isb	sy
		}
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
 80046fc:	bf00      	nop
 80046fe:	3710      	adds	r7, #16
 8004700:	46bd      	mov	sp, r7
 8004702:	bd80      	pop	{r7, pc}
 8004704:	20000e0c 	.word	0x20000e0c
 8004708:	e000ed04 	.word	0xe000ed04

0800470c <vTaskStartScheduler>:

#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
/*-----------------------------------------------------------*/

void vTaskStartScheduler( void )
{
 800470c:	b580      	push	{r7, lr}
 800470e:	b08a      	sub	sp, #40	; 0x28
 8004710:	af04      	add	r7, sp, #16
BaseType_t xReturn;

	/* Add the idle task at the lowest priority. */
	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
	{
		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
 8004712:	2300      	movs	r3, #0
 8004714:	60bb      	str	r3, [r7, #8]
		StackType_t *pxIdleTaskStackBuffer = NULL;
 8004716:	2300      	movs	r3, #0
 8004718:	607b      	str	r3, [r7, #4]
		uint32_t ulIdleTaskStackSize;

		/* The Idle task is created using user provided RAM - obtain the
		address of the RAM then create the idle task. */
		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
 800471a:	463a      	mov	r2, r7
 800471c:	1d39      	adds	r1, r7, #4
 800471e:	f107 0308 	add.w	r3, r7, #8
 8004722:	4618      	mov	r0, r3
 8004724:	f7ff f832 	bl	800378c <vApplicationGetIdleTaskMemory>
		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
 8004728:	6839      	ldr	r1, [r7, #0]
 800472a:	687b      	ldr	r3, [r7, #4]
 800472c:	68ba      	ldr	r2, [r7, #8]
 800472e:	9202      	str	r2, [sp, #8]
 8004730:	9301      	str	r3, [sp, #4]
 8004732:	2300      	movs	r3, #0
 8004734:	9300      	str	r3, [sp, #0]
 8004736:	2300      	movs	r3, #0
 8004738:	460a      	mov	r2, r1
 800473a:	4924      	ldr	r1, [pc, #144]	; (80047cc <vTaskStartScheduler+0xc0>)
 800473c:	4824      	ldr	r0, [pc, #144]	; (80047d0 <vTaskStartScheduler+0xc4>)
 800473e:	f7ff fdf9 	bl	8004334 <xTaskCreateStatic>
 8004742:	4603      	mov	r3, r0
 8004744:	4a23      	ldr	r2, [pc, #140]	; (80047d4 <vTaskStartScheduler+0xc8>)
 8004746:	6013      	str	r3, [r2, #0]
												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
												pxIdleTaskStackBuffer,
												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */

		if( xIdleTaskHandle != NULL )
 8004748:	4b22      	ldr	r3, [pc, #136]	; (80047d4 <vTaskStartScheduler+0xc8>)
 800474a:	681b      	ldr	r3, [r3, #0]
 800474c:	2b00      	cmp	r3, #0
 800474e:	d002      	beq.n	8004756 <vTaskStartScheduler+0x4a>
		{
			xReturn = pdPASS;
 8004750:	2301      	movs	r3, #1
 8004752:	617b      	str	r3, [r7, #20]
 8004754:	e001      	b.n	800475a <vTaskStartScheduler+0x4e>
		}
		else
		{
			xReturn = pdFAIL;
 8004756:	2300      	movs	r3, #0
 8004758:	617b      	str	r3, [r7, #20]
	}
	#endif /* configSUPPORT_STATIC_ALLOCATION */

	#if ( configUSE_TIMERS == 1 )
	{
		if( xReturn == pdPASS )
 800475a:	697b      	ldr	r3, [r7, #20]
 800475c:	2b01      	cmp	r3, #1
 800475e:	d102      	bne.n	8004766 <vTaskStartScheduler+0x5a>
		{
			xReturn = xTimerCreateTimerTask();
 8004760:	f000 fd10 	bl	8005184 <xTimerCreateTimerTask>
 8004764:	6178      	str	r0, [r7, #20]
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif /* configUSE_TIMERS */

	if( xReturn == pdPASS )
 8004766:	697b      	ldr	r3, [r7, #20]
 8004768:	2b01      	cmp	r3, #1
 800476a:	d11b      	bne.n	80047a4 <vTaskStartScheduler+0x98>
	__asm volatile
 800476c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004770:	f383 8811 	msr	BASEPRI, r3
 8004774:	f3bf 8f6f 	isb	sy
 8004778:	f3bf 8f4f 	dsb	sy
 800477c:	613b      	str	r3, [r7, #16]
}
 800477e:	bf00      	nop
		{
			/* Switch Newlib's _impure_ptr variable to point to the _reent
			structure specific to the task that will run first.
			See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 8004780:	4b15      	ldr	r3, [pc, #84]	; (80047d8 <vTaskStartScheduler+0xcc>)
 8004782:	681b      	ldr	r3, [r3, #0]
 8004784:	3354      	adds	r3, #84	; 0x54
 8004786:	4a15      	ldr	r2, [pc, #84]	; (80047dc <vTaskStartScheduler+0xd0>)
 8004788:	6013      	str	r3, [r2, #0]
		}
		#endif /* configUSE_NEWLIB_REENTRANT */

		xNextTaskUnblockTime = portMAX_DELAY;
 800478a:	4b15      	ldr	r3, [pc, #84]	; (80047e0 <vTaskStartScheduler+0xd4>)
 800478c:	f04f 32ff 	mov.w	r2, #4294967295
 8004790:	601a      	str	r2, [r3, #0]
		xSchedulerRunning = pdTRUE;
 8004792:	4b14      	ldr	r3, [pc, #80]	; (80047e4 <vTaskStartScheduler+0xd8>)
 8004794:	2201      	movs	r2, #1
 8004796:	601a      	str	r2, [r3, #0]
		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
 8004798:	4b13      	ldr	r3, [pc, #76]	; (80047e8 <vTaskStartScheduler+0xdc>)
 800479a:	2200      	movs	r2, #0
 800479c:	601a      	str	r2, [r3, #0]

		traceTASK_SWITCHED_IN();

		/* Setting up the timer tick is hardware specific and thus in the
		portable interface. */
		if( xPortStartScheduler() != pdFALSE )
 800479e:	f001 f8c7 	bl	8005930 <xPortStartScheduler>
	}

	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
	meaning xIdleTaskHandle is not used anywhere else. */
	( void ) xIdleTaskHandle;
}
 80047a2:	e00e      	b.n	80047c2 <vTaskStartScheduler+0xb6>
		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
 80047a4:	697b      	ldr	r3, [r7, #20]
 80047a6:	f1b3 3fff 	cmp.w	r3, #4294967295
 80047aa:	d10a      	bne.n	80047c2 <vTaskStartScheduler+0xb6>
	__asm volatile
 80047ac:	f04f 0350 	mov.w	r3, #80	; 0x50
 80047b0:	f383 8811 	msr	BASEPRI, r3
 80047b4:	f3bf 8f6f 	isb	sy
 80047b8:	f3bf 8f4f 	dsb	sy
 80047bc:	60fb      	str	r3, [r7, #12]
}
 80047be:	bf00      	nop
 80047c0:	e7fe      	b.n	80047c0 <vTaskStartScheduler+0xb4>
}
 80047c2:	bf00      	nop
 80047c4:	3718      	adds	r7, #24
 80047c6:	46bd      	mov	sp, r7
 80047c8:	bd80      	pop	{r7, pc}
 80047ca:	bf00      	nop
 80047cc:	080062ac 	.word	0x080062ac
 80047d0:	08004e11 	.word	0x08004e11
 80047d4:	20000e08 	.word	0x20000e08
 80047d8:	20000910 	.word	0x20000910
 80047dc:	2000005c 	.word	0x2000005c
 80047e0:	20000e04 	.word	0x20000e04
 80047e4:	20000df0 	.word	0x20000df0
 80047e8:	20000de8 	.word	0x20000de8

080047ec <vTaskSuspendAll>:
	vPortEndScheduler();
}
/*----------------------------------------------------------*/

void vTaskSuspendAll( void )
{
 80047ec:	b480      	push	{r7}
 80047ee:	af00      	add	r7, sp, #0
	do not otherwise exhibit real time behaviour. */
	portSOFTWARE_BARRIER();

	/* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
	is used to allow calls to vTaskSuspendAll() to nest. */
	++uxSchedulerSuspended;
 80047f0:	4b04      	ldr	r3, [pc, #16]	; (8004804 <vTaskSuspendAll+0x18>)
 80047f2:	681b      	ldr	r3, [r3, #0]
 80047f4:	3301      	adds	r3, #1
 80047f6:	4a03      	ldr	r2, [pc, #12]	; (8004804 <vTaskSuspendAll+0x18>)
 80047f8:	6013      	str	r3, [r2, #0]

	/* Enforces ordering for ports and optimised compilers that may otherwise place
	the above increment elsewhere. */
	portMEMORY_BARRIER();
}
 80047fa:	bf00      	nop
 80047fc:	46bd      	mov	sp, r7
 80047fe:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004802:	4770      	bx	lr
 8004804:	20000e0c 	.word	0x20000e0c

08004808 <xTaskResumeAll>:

#endif /* configUSE_TICKLESS_IDLE */
/*----------------------------------------------------------*/

BaseType_t xTaskResumeAll( void )
{
 8004808:	b580      	push	{r7, lr}
 800480a:	b084      	sub	sp, #16
 800480c:	af00      	add	r7, sp, #0
TCB_t *pxTCB = NULL;
 800480e:	2300      	movs	r3, #0
 8004810:	60fb      	str	r3, [r7, #12]
BaseType_t xAlreadyYielded = pdFALSE;
 8004812:	2300      	movs	r3, #0
 8004814:	60bb      	str	r3, [r7, #8]

	/* If uxSchedulerSuspended is zero then this function does not match a
	previous call to vTaskSuspendAll(). */
	configASSERT( uxSchedulerSuspended );
 8004816:	4b42      	ldr	r3, [pc, #264]	; (8004920 <xTaskResumeAll+0x118>)
 8004818:	681b      	ldr	r3, [r3, #0]
 800481a:	2b00      	cmp	r3, #0
 800481c:	d10a      	bne.n	8004834 <xTaskResumeAll+0x2c>
	__asm volatile
 800481e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004822:	f383 8811 	msr	BASEPRI, r3
 8004826:	f3bf 8f6f 	isb	sy
 800482a:	f3bf 8f4f 	dsb	sy
 800482e:	603b      	str	r3, [r7, #0]
}
 8004830:	bf00      	nop
 8004832:	e7fe      	b.n	8004832 <xTaskResumeAll+0x2a>
	/* It is possible that an ISR caused a task to be removed from an event
	list while the scheduler was suspended.  If this was the case then the
	removed task will have been added to the xPendingReadyList.  Once the
	scheduler has been resumed it is safe to move all the pending ready
	tasks from this list into their appropriate ready list. */
	taskENTER_CRITICAL();
 8004834:	f001 f91e 	bl	8005a74 <vPortEnterCritical>
	{
		--uxSchedulerSuspended;
 8004838:	4b39      	ldr	r3, [pc, #228]	; (8004920 <xTaskResumeAll+0x118>)
 800483a:	681b      	ldr	r3, [r3, #0]
 800483c:	3b01      	subs	r3, #1
 800483e:	4a38      	ldr	r2, [pc, #224]	; (8004920 <xTaskResumeAll+0x118>)
 8004840:	6013      	str	r3, [r2, #0]

		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8004842:	4b37      	ldr	r3, [pc, #220]	; (8004920 <xTaskResumeAll+0x118>)
 8004844:	681b      	ldr	r3, [r3, #0]
 8004846:	2b00      	cmp	r3, #0
 8004848:	d162      	bne.n	8004910 <xTaskResumeAll+0x108>
		{
			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
 800484a:	4b36      	ldr	r3, [pc, #216]	; (8004924 <xTaskResumeAll+0x11c>)
 800484c:	681b      	ldr	r3, [r3, #0]
 800484e:	2b00      	cmp	r3, #0
 8004850:	d05e      	beq.n	8004910 <xTaskResumeAll+0x108>
			{
				/* Move any readied tasks from the pending list into the
				appropriate ready list. */
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 8004852:	e02f      	b.n	80048b4 <xTaskResumeAll+0xac>
				{
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8004854:	4b34      	ldr	r3, [pc, #208]	; (8004928 <xTaskResumeAll+0x120>)
 8004856:	68db      	ldr	r3, [r3, #12]
 8004858:	68db      	ldr	r3, [r3, #12]
 800485a:	60fb      	str	r3, [r7, #12]
					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 800485c:	68fb      	ldr	r3, [r7, #12]
 800485e:	3318      	adds	r3, #24
 8004860:	4618      	mov	r0, r3
 8004862:	f7ff f851 	bl	8003908 <uxListRemove>
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8004866:	68fb      	ldr	r3, [r7, #12]
 8004868:	3304      	adds	r3, #4
 800486a:	4618      	mov	r0, r3
 800486c:	f7ff f84c 	bl	8003908 <uxListRemove>
					prvAddTaskToReadyList( pxTCB );
 8004870:	68fb      	ldr	r3, [r7, #12]
 8004872:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004874:	4b2d      	ldr	r3, [pc, #180]	; (800492c <xTaskResumeAll+0x124>)
 8004876:	681b      	ldr	r3, [r3, #0]
 8004878:	429a      	cmp	r2, r3
 800487a:	d903      	bls.n	8004884 <xTaskResumeAll+0x7c>
 800487c:	68fb      	ldr	r3, [r7, #12]
 800487e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004880:	4a2a      	ldr	r2, [pc, #168]	; (800492c <xTaskResumeAll+0x124>)
 8004882:	6013      	str	r3, [r2, #0]
 8004884:	68fb      	ldr	r3, [r7, #12]
 8004886:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004888:	4613      	mov	r3, r2
 800488a:	009b      	lsls	r3, r3, #2
 800488c:	4413      	add	r3, r2
 800488e:	009b      	lsls	r3, r3, #2
 8004890:	4a27      	ldr	r2, [pc, #156]	; (8004930 <xTaskResumeAll+0x128>)
 8004892:	441a      	add	r2, r3
 8004894:	68fb      	ldr	r3, [r7, #12]
 8004896:	3304      	adds	r3, #4
 8004898:	4619      	mov	r1, r3
 800489a:	4610      	mov	r0, r2
 800489c:	f7fe ffd7 	bl	800384e <vListInsertEnd>

					/* If the moved task has a priority higher than the current
					task then a yield must be performed. */
					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 80048a0:	68fb      	ldr	r3, [r7, #12]
 80048a2:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80048a4:	4b23      	ldr	r3, [pc, #140]	; (8004934 <xTaskResumeAll+0x12c>)
 80048a6:	681b      	ldr	r3, [r3, #0]
 80048a8:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80048aa:	429a      	cmp	r2, r3
 80048ac:	d302      	bcc.n	80048b4 <xTaskResumeAll+0xac>
					{
						xYieldPending = pdTRUE;
 80048ae:	4b22      	ldr	r3, [pc, #136]	; (8004938 <xTaskResumeAll+0x130>)
 80048b0:	2201      	movs	r2, #1
 80048b2:	601a      	str	r2, [r3, #0]
				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
 80048b4:	4b1c      	ldr	r3, [pc, #112]	; (8004928 <xTaskResumeAll+0x120>)
 80048b6:	681b      	ldr	r3, [r3, #0]
 80048b8:	2b00      	cmp	r3, #0
 80048ba:	d1cb      	bne.n	8004854 <xTaskResumeAll+0x4c>
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( pxTCB != NULL )
 80048bc:	68fb      	ldr	r3, [r7, #12]
 80048be:	2b00      	cmp	r3, #0
 80048c0:	d001      	beq.n	80048c6 <xTaskResumeAll+0xbe>
					which may have prevented the next unblock time from being
					re-calculated, in which case re-calculate it now.  Mainly
					important for low power tickless implementations, where
					this can prevent an unnecessary exit from low power
					state. */
					prvResetNextTaskUnblockTime();
 80048c2:	f000 fb5f 	bl	8004f84 <prvResetNextTaskUnblockTime>
				/* If any ticks occurred while the scheduler was suspended then
				they should be processed now.  This ensures the tick count does
				not	slip, and that any delayed tasks are resumed at the correct
				time. */
				{
					TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
 80048c6:	4b1d      	ldr	r3, [pc, #116]	; (800493c <xTaskResumeAll+0x134>)
 80048c8:	681b      	ldr	r3, [r3, #0]
 80048ca:	607b      	str	r3, [r7, #4]

					if( xPendedCounts > ( TickType_t ) 0U )
 80048cc:	687b      	ldr	r3, [r7, #4]
 80048ce:	2b00      	cmp	r3, #0
 80048d0:	d010      	beq.n	80048f4 <xTaskResumeAll+0xec>
					{
						do
						{
							if( xTaskIncrementTick() != pdFALSE )
 80048d2:	f000 f847 	bl	8004964 <xTaskIncrementTick>
 80048d6:	4603      	mov	r3, r0
 80048d8:	2b00      	cmp	r3, #0
 80048da:	d002      	beq.n	80048e2 <xTaskResumeAll+0xda>
							{
								xYieldPending = pdTRUE;
 80048dc:	4b16      	ldr	r3, [pc, #88]	; (8004938 <xTaskResumeAll+0x130>)
 80048de:	2201      	movs	r2, #1
 80048e0:	601a      	str	r2, [r3, #0]
							}
							else
							{
								mtCOVERAGE_TEST_MARKER();
							}
							--xPendedCounts;
 80048e2:	687b      	ldr	r3, [r7, #4]
 80048e4:	3b01      	subs	r3, #1
 80048e6:	607b      	str	r3, [r7, #4]
						} while( xPendedCounts > ( TickType_t ) 0U );
 80048e8:	687b      	ldr	r3, [r7, #4]
 80048ea:	2b00      	cmp	r3, #0
 80048ec:	d1f1      	bne.n	80048d2 <xTaskResumeAll+0xca>

						xPendedTicks = 0;
 80048ee:	4b13      	ldr	r3, [pc, #76]	; (800493c <xTaskResumeAll+0x134>)
 80048f0:	2200      	movs	r2, #0
 80048f2:	601a      	str	r2, [r3, #0]
					{
						mtCOVERAGE_TEST_MARKER();
					}
				}

				if( xYieldPending != pdFALSE )
 80048f4:	4b10      	ldr	r3, [pc, #64]	; (8004938 <xTaskResumeAll+0x130>)
 80048f6:	681b      	ldr	r3, [r3, #0]
 80048f8:	2b00      	cmp	r3, #0
 80048fa:	d009      	beq.n	8004910 <xTaskResumeAll+0x108>
				{
					#if( configUSE_PREEMPTION != 0 )
					{
						xAlreadyYielded = pdTRUE;
 80048fc:	2301      	movs	r3, #1
 80048fe:	60bb      	str	r3, [r7, #8]
					}
					#endif
					taskYIELD_IF_USING_PREEMPTION();
 8004900:	4b0f      	ldr	r3, [pc, #60]	; (8004940 <xTaskResumeAll+0x138>)
 8004902:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8004906:	601a      	str	r2, [r3, #0]
 8004908:	f3bf 8f4f 	dsb	sy
 800490c:	f3bf 8f6f 	isb	sy
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 8004910:	f001 f8e0 	bl	8005ad4 <vPortExitCritical>

	return xAlreadyYielded;
 8004914:	68bb      	ldr	r3, [r7, #8]
}
 8004916:	4618      	mov	r0, r3
 8004918:	3710      	adds	r7, #16
 800491a:	46bd      	mov	sp, r7
 800491c:	bd80      	pop	{r7, pc}
 800491e:	bf00      	nop
 8004920:	20000e0c 	.word	0x20000e0c
 8004924:	20000de4 	.word	0x20000de4
 8004928:	20000da4 	.word	0x20000da4
 800492c:	20000dec 	.word	0x20000dec
 8004930:	20000914 	.word	0x20000914
 8004934:	20000910 	.word	0x20000910
 8004938:	20000df8 	.word	0x20000df8
 800493c:	20000df4 	.word	0x20000df4
 8004940:	e000ed04 	.word	0xe000ed04

08004944 <xTaskGetTickCount>:
/*-----------------------------------------------------------*/

TickType_t xTaskGetTickCount( void )
{
 8004944:	b480      	push	{r7}
 8004946:	b083      	sub	sp, #12
 8004948:	af00      	add	r7, sp, #0
TickType_t xTicks;

	/* Critical section required if running on a 16 bit processor. */
	portTICK_TYPE_ENTER_CRITICAL();
	{
		xTicks = xTickCount;
 800494a:	4b05      	ldr	r3, [pc, #20]	; (8004960 <xTaskGetTickCount+0x1c>)
 800494c:	681b      	ldr	r3, [r3, #0]
 800494e:	607b      	str	r3, [r7, #4]
	}
	portTICK_TYPE_EXIT_CRITICAL();

	return xTicks;
 8004950:	687b      	ldr	r3, [r7, #4]
}
 8004952:	4618      	mov	r0, r3
 8004954:	370c      	adds	r7, #12
 8004956:	46bd      	mov	sp, r7
 8004958:	f85d 7b04 	ldr.w	r7, [sp], #4
 800495c:	4770      	bx	lr
 800495e:	bf00      	nop
 8004960:	20000de8 	.word	0x20000de8

08004964 <xTaskIncrementTick>:

#endif /* INCLUDE_xTaskAbortDelay */
/*----------------------------------------------------------*/

BaseType_t xTaskIncrementTick( void )
{
 8004964:	b580      	push	{r7, lr}
 8004966:	b086      	sub	sp, #24
 8004968:	af00      	add	r7, sp, #0
TCB_t * pxTCB;
TickType_t xItemValue;
BaseType_t xSwitchRequired = pdFALSE;
 800496a:	2300      	movs	r3, #0
 800496c:	617b      	str	r3, [r7, #20]

	/* Called by the portable layer each time a tick interrupt occurs.
	Increments the tick then checks to see if the new tick value will cause any
	tasks to be unblocked. */
	traceTASK_INCREMENT_TICK( xTickCount );
	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 800496e:	4b4f      	ldr	r3, [pc, #316]	; (8004aac <xTaskIncrementTick+0x148>)
 8004970:	681b      	ldr	r3, [r3, #0]
 8004972:	2b00      	cmp	r3, #0
 8004974:	f040 808f 	bne.w	8004a96 <xTaskIncrementTick+0x132>
	{
		/* Minor optimisation.  The tick count cannot change in this
		block. */
		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
 8004978:	4b4d      	ldr	r3, [pc, #308]	; (8004ab0 <xTaskIncrementTick+0x14c>)
 800497a:	681b      	ldr	r3, [r3, #0]
 800497c:	3301      	adds	r3, #1
 800497e:	613b      	str	r3, [r7, #16]

		/* Increment the RTOS tick, switching the delayed and overflowed
		delayed lists if it wraps to 0. */
		xTickCount = xConstTickCount;
 8004980:	4a4b      	ldr	r2, [pc, #300]	; (8004ab0 <xTaskIncrementTick+0x14c>)
 8004982:	693b      	ldr	r3, [r7, #16]
 8004984:	6013      	str	r3, [r2, #0]

		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
 8004986:	693b      	ldr	r3, [r7, #16]
 8004988:	2b00      	cmp	r3, #0
 800498a:	d120      	bne.n	80049ce <xTaskIncrementTick+0x6a>
		{
			taskSWITCH_DELAYED_LISTS();
 800498c:	4b49      	ldr	r3, [pc, #292]	; (8004ab4 <xTaskIncrementTick+0x150>)
 800498e:	681b      	ldr	r3, [r3, #0]
 8004990:	681b      	ldr	r3, [r3, #0]
 8004992:	2b00      	cmp	r3, #0
 8004994:	d00a      	beq.n	80049ac <xTaskIncrementTick+0x48>
	__asm volatile
 8004996:	f04f 0350 	mov.w	r3, #80	; 0x50
 800499a:	f383 8811 	msr	BASEPRI, r3
 800499e:	f3bf 8f6f 	isb	sy
 80049a2:	f3bf 8f4f 	dsb	sy
 80049a6:	603b      	str	r3, [r7, #0]
}
 80049a8:	bf00      	nop
 80049aa:	e7fe      	b.n	80049aa <xTaskIncrementTick+0x46>
 80049ac:	4b41      	ldr	r3, [pc, #260]	; (8004ab4 <xTaskIncrementTick+0x150>)
 80049ae:	681b      	ldr	r3, [r3, #0]
 80049b0:	60fb      	str	r3, [r7, #12]
 80049b2:	4b41      	ldr	r3, [pc, #260]	; (8004ab8 <xTaskIncrementTick+0x154>)
 80049b4:	681b      	ldr	r3, [r3, #0]
 80049b6:	4a3f      	ldr	r2, [pc, #252]	; (8004ab4 <xTaskIncrementTick+0x150>)
 80049b8:	6013      	str	r3, [r2, #0]
 80049ba:	4a3f      	ldr	r2, [pc, #252]	; (8004ab8 <xTaskIncrementTick+0x154>)
 80049bc:	68fb      	ldr	r3, [r7, #12]
 80049be:	6013      	str	r3, [r2, #0]
 80049c0:	4b3e      	ldr	r3, [pc, #248]	; (8004abc <xTaskIncrementTick+0x158>)
 80049c2:	681b      	ldr	r3, [r3, #0]
 80049c4:	3301      	adds	r3, #1
 80049c6:	4a3d      	ldr	r2, [pc, #244]	; (8004abc <xTaskIncrementTick+0x158>)
 80049c8:	6013      	str	r3, [r2, #0]
 80049ca:	f000 fadb 	bl	8004f84 <prvResetNextTaskUnblockTime>

		/* See if this tick has made a timeout expire.  Tasks are stored in
		the	queue in the order of their wake time - meaning once one task
		has been found whose block time has not expired there is no need to
		look any further down the list. */
		if( xConstTickCount >= xNextTaskUnblockTime )
 80049ce:	4b3c      	ldr	r3, [pc, #240]	; (8004ac0 <xTaskIncrementTick+0x15c>)
 80049d0:	681b      	ldr	r3, [r3, #0]
 80049d2:	693a      	ldr	r2, [r7, #16]
 80049d4:	429a      	cmp	r2, r3
 80049d6:	d349      	bcc.n	8004a6c <xTaskIncrementTick+0x108>
		{
			for( ;; )
			{
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 80049d8:	4b36      	ldr	r3, [pc, #216]	; (8004ab4 <xTaskIncrementTick+0x150>)
 80049da:	681b      	ldr	r3, [r3, #0]
 80049dc:	681b      	ldr	r3, [r3, #0]
 80049de:	2b00      	cmp	r3, #0
 80049e0:	d104      	bne.n	80049ec <xTaskIncrementTick+0x88>
					/* The delayed list is empty.  Set xNextTaskUnblockTime
					to the maximum possible value so it is extremely
					unlikely that the
					if( xTickCount >= xNextTaskUnblockTime ) test will pass
					next time through. */
					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80049e2:	4b37      	ldr	r3, [pc, #220]	; (8004ac0 <xTaskIncrementTick+0x15c>)
 80049e4:	f04f 32ff 	mov.w	r2, #4294967295
 80049e8:	601a      	str	r2, [r3, #0]
					break;
 80049ea:	e03f      	b.n	8004a6c <xTaskIncrementTick+0x108>
				{
					/* The delayed list is not empty, get the value of the
					item at the head of the delayed list.  This is the time
					at which the task at the head of the delayed list must
					be removed from the Blocked state. */
					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80049ec:	4b31      	ldr	r3, [pc, #196]	; (8004ab4 <xTaskIncrementTick+0x150>)
 80049ee:	681b      	ldr	r3, [r3, #0]
 80049f0:	68db      	ldr	r3, [r3, #12]
 80049f2:	68db      	ldr	r3, [r3, #12]
 80049f4:	60bb      	str	r3, [r7, #8]
					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
 80049f6:	68bb      	ldr	r3, [r7, #8]
 80049f8:	685b      	ldr	r3, [r3, #4]
 80049fa:	607b      	str	r3, [r7, #4]

					if( xConstTickCount < xItemValue )
 80049fc:	693a      	ldr	r2, [r7, #16]
 80049fe:	687b      	ldr	r3, [r7, #4]
 8004a00:	429a      	cmp	r2, r3
 8004a02:	d203      	bcs.n	8004a0c <xTaskIncrementTick+0xa8>
						/* It is not time to unblock this item yet, but the
						item value is the time at which the task at the head
						of the blocked list must be removed from the Blocked
						state -	so record the item value in
						xNextTaskUnblockTime. */
						xNextTaskUnblockTime = xItemValue;
 8004a04:	4a2e      	ldr	r2, [pc, #184]	; (8004ac0 <xTaskIncrementTick+0x15c>)
 8004a06:	687b      	ldr	r3, [r7, #4]
 8004a08:	6013      	str	r3, [r2, #0]
						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
 8004a0a:	e02f      	b.n	8004a6c <xTaskIncrementTick+0x108>
					{
						mtCOVERAGE_TEST_MARKER();
					}

					/* It is time to remove the item from the Blocked state. */
					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8004a0c:	68bb      	ldr	r3, [r7, #8]
 8004a0e:	3304      	adds	r3, #4
 8004a10:	4618      	mov	r0, r3
 8004a12:	f7fe ff79 	bl	8003908 <uxListRemove>

					/* Is the task waiting on an event also?  If so remove
					it from the event list. */
					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
 8004a16:	68bb      	ldr	r3, [r7, #8]
 8004a18:	6a9b      	ldr	r3, [r3, #40]	; 0x28
 8004a1a:	2b00      	cmp	r3, #0
 8004a1c:	d004      	beq.n	8004a28 <xTaskIncrementTick+0xc4>
					{
						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
 8004a1e:	68bb      	ldr	r3, [r7, #8]
 8004a20:	3318      	adds	r3, #24
 8004a22:	4618      	mov	r0, r3
 8004a24:	f7fe ff70 	bl	8003908 <uxListRemove>
						mtCOVERAGE_TEST_MARKER();
					}

					/* Place the unblocked task into the appropriate ready
					list. */
					prvAddTaskToReadyList( pxTCB );
 8004a28:	68bb      	ldr	r3, [r7, #8]
 8004a2a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004a2c:	4b25      	ldr	r3, [pc, #148]	; (8004ac4 <xTaskIncrementTick+0x160>)
 8004a2e:	681b      	ldr	r3, [r3, #0]
 8004a30:	429a      	cmp	r2, r3
 8004a32:	d903      	bls.n	8004a3c <xTaskIncrementTick+0xd8>
 8004a34:	68bb      	ldr	r3, [r7, #8]
 8004a36:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004a38:	4a22      	ldr	r2, [pc, #136]	; (8004ac4 <xTaskIncrementTick+0x160>)
 8004a3a:	6013      	str	r3, [r2, #0]
 8004a3c:	68bb      	ldr	r3, [r7, #8]
 8004a3e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004a40:	4613      	mov	r3, r2
 8004a42:	009b      	lsls	r3, r3, #2
 8004a44:	4413      	add	r3, r2
 8004a46:	009b      	lsls	r3, r3, #2
 8004a48:	4a1f      	ldr	r2, [pc, #124]	; (8004ac8 <xTaskIncrementTick+0x164>)
 8004a4a:	441a      	add	r2, r3
 8004a4c:	68bb      	ldr	r3, [r7, #8]
 8004a4e:	3304      	adds	r3, #4
 8004a50:	4619      	mov	r1, r3
 8004a52:	4610      	mov	r0, r2
 8004a54:	f7fe fefb 	bl	800384e <vListInsertEnd>
					{
						/* Preemption is on, but a context switch should
						only be performed if the unblocked task has a
						priority that is equal to or higher than the
						currently executing task. */
						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
 8004a58:	68bb      	ldr	r3, [r7, #8]
 8004a5a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004a5c:	4b1b      	ldr	r3, [pc, #108]	; (8004acc <xTaskIncrementTick+0x168>)
 8004a5e:	681b      	ldr	r3, [r3, #0]
 8004a60:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004a62:	429a      	cmp	r2, r3
 8004a64:	d3b8      	bcc.n	80049d8 <xTaskIncrementTick+0x74>
						{
							xSwitchRequired = pdTRUE;
 8004a66:	2301      	movs	r3, #1
 8004a68:	617b      	str	r3, [r7, #20]
				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8004a6a:	e7b5      	b.n	80049d8 <xTaskIncrementTick+0x74>
		/* Tasks of equal priority to the currently running task will share
		processing time (time slice) if preemption is on, and the application
		writer has not explicitly turned time slicing off. */
		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
		{
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
 8004a6c:	4b17      	ldr	r3, [pc, #92]	; (8004acc <xTaskIncrementTick+0x168>)
 8004a6e:	681b      	ldr	r3, [r3, #0]
 8004a70:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004a72:	4915      	ldr	r1, [pc, #84]	; (8004ac8 <xTaskIncrementTick+0x164>)
 8004a74:	4613      	mov	r3, r2
 8004a76:	009b      	lsls	r3, r3, #2
 8004a78:	4413      	add	r3, r2
 8004a7a:	009b      	lsls	r3, r3, #2
 8004a7c:	440b      	add	r3, r1
 8004a7e:	681b      	ldr	r3, [r3, #0]
 8004a80:	2b01      	cmp	r3, #1
 8004a82:	d901      	bls.n	8004a88 <xTaskIncrementTick+0x124>
			{
				xSwitchRequired = pdTRUE;
 8004a84:	2301      	movs	r3, #1
 8004a86:	617b      	str	r3, [r7, #20]
		}
		#endif /* configUSE_TICK_HOOK */

		#if ( configUSE_PREEMPTION == 1 )
		{
			if( xYieldPending != pdFALSE )
 8004a88:	4b11      	ldr	r3, [pc, #68]	; (8004ad0 <xTaskIncrementTick+0x16c>)
 8004a8a:	681b      	ldr	r3, [r3, #0]
 8004a8c:	2b00      	cmp	r3, #0
 8004a8e:	d007      	beq.n	8004aa0 <xTaskIncrementTick+0x13c>
			{
				xSwitchRequired = pdTRUE;
 8004a90:	2301      	movs	r3, #1
 8004a92:	617b      	str	r3, [r7, #20]
 8004a94:	e004      	b.n	8004aa0 <xTaskIncrementTick+0x13c>
		}
		#endif /* configUSE_PREEMPTION */
	}
	else
	{
		++xPendedTicks;
 8004a96:	4b0f      	ldr	r3, [pc, #60]	; (8004ad4 <xTaskIncrementTick+0x170>)
 8004a98:	681b      	ldr	r3, [r3, #0]
 8004a9a:	3301      	adds	r3, #1
 8004a9c:	4a0d      	ldr	r2, [pc, #52]	; (8004ad4 <xTaskIncrementTick+0x170>)
 8004a9e:	6013      	str	r3, [r2, #0]
			vApplicationTickHook();
		}
		#endif
	}

	return xSwitchRequired;
 8004aa0:	697b      	ldr	r3, [r7, #20]
}
 8004aa2:	4618      	mov	r0, r3
 8004aa4:	3718      	adds	r7, #24
 8004aa6:	46bd      	mov	sp, r7
 8004aa8:	bd80      	pop	{r7, pc}
 8004aaa:	bf00      	nop
 8004aac:	20000e0c 	.word	0x20000e0c
 8004ab0:	20000de8 	.word	0x20000de8
 8004ab4:	20000d9c 	.word	0x20000d9c
 8004ab8:	20000da0 	.word	0x20000da0
 8004abc:	20000dfc 	.word	0x20000dfc
 8004ac0:	20000e04 	.word	0x20000e04
 8004ac4:	20000dec 	.word	0x20000dec
 8004ac8:	20000914 	.word	0x20000914
 8004acc:	20000910 	.word	0x20000910
 8004ad0:	20000df8 	.word	0x20000df8
 8004ad4:	20000df4 	.word	0x20000df4

08004ad8 <vTaskSwitchContext>:

#endif /* configUSE_APPLICATION_TASK_TAG */
/*-----------------------------------------------------------*/

void vTaskSwitchContext( void )
{
 8004ad8:	b480      	push	{r7}
 8004ada:	b085      	sub	sp, #20
 8004adc:	af00      	add	r7, sp, #0
	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
 8004ade:	4b2a      	ldr	r3, [pc, #168]	; (8004b88 <vTaskSwitchContext+0xb0>)
 8004ae0:	681b      	ldr	r3, [r3, #0]
 8004ae2:	2b00      	cmp	r3, #0
 8004ae4:	d003      	beq.n	8004aee <vTaskSwitchContext+0x16>
	{
		/* The scheduler is currently suspended - do not allow a context
		switch. */
		xYieldPending = pdTRUE;
 8004ae6:	4b29      	ldr	r3, [pc, #164]	; (8004b8c <vTaskSwitchContext+0xb4>)
 8004ae8:	2201      	movs	r2, #1
 8004aea:	601a      	str	r2, [r3, #0]
			for additional information. */
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
		}
		#endif /* configUSE_NEWLIB_REENTRANT */
	}
}
 8004aec:	e046      	b.n	8004b7c <vTaskSwitchContext+0xa4>
		xYieldPending = pdFALSE;
 8004aee:	4b27      	ldr	r3, [pc, #156]	; (8004b8c <vTaskSwitchContext+0xb4>)
 8004af0:	2200      	movs	r2, #0
 8004af2:	601a      	str	r2, [r3, #0]
		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8004af4:	4b26      	ldr	r3, [pc, #152]	; (8004b90 <vTaskSwitchContext+0xb8>)
 8004af6:	681b      	ldr	r3, [r3, #0]
 8004af8:	60fb      	str	r3, [r7, #12]
 8004afa:	e010      	b.n	8004b1e <vTaskSwitchContext+0x46>
 8004afc:	68fb      	ldr	r3, [r7, #12]
 8004afe:	2b00      	cmp	r3, #0
 8004b00:	d10a      	bne.n	8004b18 <vTaskSwitchContext+0x40>
	__asm volatile
 8004b02:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004b06:	f383 8811 	msr	BASEPRI, r3
 8004b0a:	f3bf 8f6f 	isb	sy
 8004b0e:	f3bf 8f4f 	dsb	sy
 8004b12:	607b      	str	r3, [r7, #4]
}
 8004b14:	bf00      	nop
 8004b16:	e7fe      	b.n	8004b16 <vTaskSwitchContext+0x3e>
 8004b18:	68fb      	ldr	r3, [r7, #12]
 8004b1a:	3b01      	subs	r3, #1
 8004b1c:	60fb      	str	r3, [r7, #12]
 8004b1e:	491d      	ldr	r1, [pc, #116]	; (8004b94 <vTaskSwitchContext+0xbc>)
 8004b20:	68fa      	ldr	r2, [r7, #12]
 8004b22:	4613      	mov	r3, r2
 8004b24:	009b      	lsls	r3, r3, #2
 8004b26:	4413      	add	r3, r2
 8004b28:	009b      	lsls	r3, r3, #2
 8004b2a:	440b      	add	r3, r1
 8004b2c:	681b      	ldr	r3, [r3, #0]
 8004b2e:	2b00      	cmp	r3, #0
 8004b30:	d0e4      	beq.n	8004afc <vTaskSwitchContext+0x24>
 8004b32:	68fa      	ldr	r2, [r7, #12]
 8004b34:	4613      	mov	r3, r2
 8004b36:	009b      	lsls	r3, r3, #2
 8004b38:	4413      	add	r3, r2
 8004b3a:	009b      	lsls	r3, r3, #2
 8004b3c:	4a15      	ldr	r2, [pc, #84]	; (8004b94 <vTaskSwitchContext+0xbc>)
 8004b3e:	4413      	add	r3, r2
 8004b40:	60bb      	str	r3, [r7, #8]
 8004b42:	68bb      	ldr	r3, [r7, #8]
 8004b44:	685b      	ldr	r3, [r3, #4]
 8004b46:	685a      	ldr	r2, [r3, #4]
 8004b48:	68bb      	ldr	r3, [r7, #8]
 8004b4a:	605a      	str	r2, [r3, #4]
 8004b4c:	68bb      	ldr	r3, [r7, #8]
 8004b4e:	685a      	ldr	r2, [r3, #4]
 8004b50:	68bb      	ldr	r3, [r7, #8]
 8004b52:	3308      	adds	r3, #8
 8004b54:	429a      	cmp	r2, r3
 8004b56:	d104      	bne.n	8004b62 <vTaskSwitchContext+0x8a>
 8004b58:	68bb      	ldr	r3, [r7, #8]
 8004b5a:	685b      	ldr	r3, [r3, #4]
 8004b5c:	685a      	ldr	r2, [r3, #4]
 8004b5e:	68bb      	ldr	r3, [r7, #8]
 8004b60:	605a      	str	r2, [r3, #4]
 8004b62:	68bb      	ldr	r3, [r7, #8]
 8004b64:	685b      	ldr	r3, [r3, #4]
 8004b66:	68db      	ldr	r3, [r3, #12]
 8004b68:	4a0b      	ldr	r2, [pc, #44]	; (8004b98 <vTaskSwitchContext+0xc0>)
 8004b6a:	6013      	str	r3, [r2, #0]
 8004b6c:	4a08      	ldr	r2, [pc, #32]	; (8004b90 <vTaskSwitchContext+0xb8>)
 8004b6e:	68fb      	ldr	r3, [r7, #12]
 8004b70:	6013      	str	r3, [r2, #0]
			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
 8004b72:	4b09      	ldr	r3, [pc, #36]	; (8004b98 <vTaskSwitchContext+0xc0>)
 8004b74:	681b      	ldr	r3, [r3, #0]
 8004b76:	3354      	adds	r3, #84	; 0x54
 8004b78:	4a08      	ldr	r2, [pc, #32]	; (8004b9c <vTaskSwitchContext+0xc4>)
 8004b7a:	6013      	str	r3, [r2, #0]
}
 8004b7c:	bf00      	nop
 8004b7e:	3714      	adds	r7, #20
 8004b80:	46bd      	mov	sp, r7
 8004b82:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004b86:	4770      	bx	lr
 8004b88:	20000e0c 	.word	0x20000e0c
 8004b8c:	20000df8 	.word	0x20000df8
 8004b90:	20000dec 	.word	0x20000dec
 8004b94:	20000914 	.word	0x20000914
 8004b98:	20000910 	.word	0x20000910
 8004b9c:	2000005c 	.word	0x2000005c

08004ba0 <vTaskPlaceOnEventList>:
/*-----------------------------------------------------------*/

void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
{
 8004ba0:	b580      	push	{r7, lr}
 8004ba2:	b084      	sub	sp, #16
 8004ba4:	af00      	add	r7, sp, #0
 8004ba6:	6078      	str	r0, [r7, #4]
 8004ba8:	6039      	str	r1, [r7, #0]
	configASSERT( pxEventList );
 8004baa:	687b      	ldr	r3, [r7, #4]
 8004bac:	2b00      	cmp	r3, #0
 8004bae:	d10a      	bne.n	8004bc6 <vTaskPlaceOnEventList+0x26>
	__asm volatile
 8004bb0:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004bb4:	f383 8811 	msr	BASEPRI, r3
 8004bb8:	f3bf 8f6f 	isb	sy
 8004bbc:	f3bf 8f4f 	dsb	sy
 8004bc0:	60fb      	str	r3, [r7, #12]
}
 8004bc2:	bf00      	nop
 8004bc4:	e7fe      	b.n	8004bc4 <vTaskPlaceOnEventList+0x24>

	/* Place the event list item of the TCB in the appropriate event list.
	This is placed in the list in priority order so the highest priority task
	is the first to be woken by the event.  The queue that contains the event
	list is locked, preventing simultaneous access from interrupts. */
	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 8004bc6:	4b07      	ldr	r3, [pc, #28]	; (8004be4 <vTaskPlaceOnEventList+0x44>)
 8004bc8:	681b      	ldr	r3, [r3, #0]
 8004bca:	3318      	adds	r3, #24
 8004bcc:	4619      	mov	r1, r3
 8004bce:	6878      	ldr	r0, [r7, #4]
 8004bd0:	f7fe fe61 	bl	8003896 <vListInsert>

	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
 8004bd4:	2101      	movs	r1, #1
 8004bd6:	6838      	ldr	r0, [r7, #0]
 8004bd8:	f000 fa80 	bl	80050dc <prvAddCurrentTaskToDelayedList>
}
 8004bdc:	bf00      	nop
 8004bde:	3710      	adds	r7, #16
 8004be0:	46bd      	mov	sp, r7
 8004be2:	bd80      	pop	{r7, pc}
 8004be4:	20000910 	.word	0x20000910

08004be8 <vTaskPlaceOnEventListRestricted>:
/*-----------------------------------------------------------*/

#if( configUSE_TIMERS == 1 )

	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
	{
 8004be8:	b580      	push	{r7, lr}
 8004bea:	b086      	sub	sp, #24
 8004bec:	af00      	add	r7, sp, #0
 8004bee:	60f8      	str	r0, [r7, #12]
 8004bf0:	60b9      	str	r1, [r7, #8]
 8004bf2:	607a      	str	r2, [r7, #4]
		configASSERT( pxEventList );
 8004bf4:	68fb      	ldr	r3, [r7, #12]
 8004bf6:	2b00      	cmp	r3, #0
 8004bf8:	d10a      	bne.n	8004c10 <vTaskPlaceOnEventListRestricted+0x28>
	__asm volatile
 8004bfa:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004bfe:	f383 8811 	msr	BASEPRI, r3
 8004c02:	f3bf 8f6f 	isb	sy
 8004c06:	f3bf 8f4f 	dsb	sy
 8004c0a:	617b      	str	r3, [r7, #20]
}
 8004c0c:	bf00      	nop
 8004c0e:	e7fe      	b.n	8004c0e <vTaskPlaceOnEventListRestricted+0x26>

		/* Place the event list item of the TCB in the appropriate event list.
		In this case it is assume that this is the only task that is going to
		be waiting on this event list, so the faster vListInsertEnd() function
		can be used in place of vListInsert. */
		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
 8004c10:	4b0a      	ldr	r3, [pc, #40]	; (8004c3c <vTaskPlaceOnEventListRestricted+0x54>)
 8004c12:	681b      	ldr	r3, [r3, #0]
 8004c14:	3318      	adds	r3, #24
 8004c16:	4619      	mov	r1, r3
 8004c18:	68f8      	ldr	r0, [r7, #12]
 8004c1a:	f7fe fe18 	bl	800384e <vListInsertEnd>

		/* If the task should block indefinitely then set the block time to a
		value that will be recognised as an indefinite delay inside the
		prvAddCurrentTaskToDelayedList() function. */
		if( xWaitIndefinitely != pdFALSE )
 8004c1e:	687b      	ldr	r3, [r7, #4]
 8004c20:	2b00      	cmp	r3, #0
 8004c22:	d002      	beq.n	8004c2a <vTaskPlaceOnEventListRestricted+0x42>
		{
			xTicksToWait = portMAX_DELAY;
 8004c24:	f04f 33ff 	mov.w	r3, #4294967295
 8004c28:	60bb      	str	r3, [r7, #8]
		}

		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
 8004c2a:	6879      	ldr	r1, [r7, #4]
 8004c2c:	68b8      	ldr	r0, [r7, #8]
 8004c2e:	f000 fa55 	bl	80050dc <prvAddCurrentTaskToDelayedList>
	}
 8004c32:	bf00      	nop
 8004c34:	3718      	adds	r7, #24
 8004c36:	46bd      	mov	sp, r7
 8004c38:	bd80      	pop	{r7, pc}
 8004c3a:	bf00      	nop
 8004c3c:	20000910 	.word	0x20000910

08004c40 <xTaskRemoveFromEventList>:

#endif /* configUSE_TIMERS */
/*-----------------------------------------------------------*/

BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
{
 8004c40:	b580      	push	{r7, lr}
 8004c42:	b086      	sub	sp, #24
 8004c44:	af00      	add	r7, sp, #0
 8004c46:	6078      	str	r0, [r7, #4]
	get called - the lock count on the queue will get modified instead.  This
	means exclusive access to the event list is guaranteed here.

	This function assumes that a check has already been made to ensure that
	pxEventList is not empty. */
	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8004c48:	687b      	ldr	r3, [r7, #4]
 8004c4a:	68db      	ldr	r3, [r3, #12]
 8004c4c:	68db      	ldr	r3, [r3, #12]
 8004c4e:	613b      	str	r3, [r7, #16]
	configASSERT( pxUnblockedTCB );
 8004c50:	693b      	ldr	r3, [r7, #16]
 8004c52:	2b00      	cmp	r3, #0
 8004c54:	d10a      	bne.n	8004c6c <xTaskRemoveFromEventList+0x2c>
	__asm volatile
 8004c56:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004c5a:	f383 8811 	msr	BASEPRI, r3
 8004c5e:	f3bf 8f6f 	isb	sy
 8004c62:	f3bf 8f4f 	dsb	sy
 8004c66:	60fb      	str	r3, [r7, #12]
}
 8004c68:	bf00      	nop
 8004c6a:	e7fe      	b.n	8004c6a <xTaskRemoveFromEventList+0x2a>
	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
 8004c6c:	693b      	ldr	r3, [r7, #16]
 8004c6e:	3318      	adds	r3, #24
 8004c70:	4618      	mov	r0, r3
 8004c72:	f7fe fe49 	bl	8003908 <uxListRemove>

	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8004c76:	4b1e      	ldr	r3, [pc, #120]	; (8004cf0 <xTaskRemoveFromEventList+0xb0>)
 8004c78:	681b      	ldr	r3, [r3, #0]
 8004c7a:	2b00      	cmp	r3, #0
 8004c7c:	d11d      	bne.n	8004cba <xTaskRemoveFromEventList+0x7a>
	{
		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
 8004c7e:	693b      	ldr	r3, [r7, #16]
 8004c80:	3304      	adds	r3, #4
 8004c82:	4618      	mov	r0, r3
 8004c84:	f7fe fe40 	bl	8003908 <uxListRemove>
		prvAddTaskToReadyList( pxUnblockedTCB );
 8004c88:	693b      	ldr	r3, [r7, #16]
 8004c8a:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004c8c:	4b19      	ldr	r3, [pc, #100]	; (8004cf4 <xTaskRemoveFromEventList+0xb4>)
 8004c8e:	681b      	ldr	r3, [r3, #0]
 8004c90:	429a      	cmp	r2, r3
 8004c92:	d903      	bls.n	8004c9c <xTaskRemoveFromEventList+0x5c>
 8004c94:	693b      	ldr	r3, [r7, #16]
 8004c96:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004c98:	4a16      	ldr	r2, [pc, #88]	; (8004cf4 <xTaskRemoveFromEventList+0xb4>)
 8004c9a:	6013      	str	r3, [r2, #0]
 8004c9c:	693b      	ldr	r3, [r7, #16]
 8004c9e:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004ca0:	4613      	mov	r3, r2
 8004ca2:	009b      	lsls	r3, r3, #2
 8004ca4:	4413      	add	r3, r2
 8004ca6:	009b      	lsls	r3, r3, #2
 8004ca8:	4a13      	ldr	r2, [pc, #76]	; (8004cf8 <xTaskRemoveFromEventList+0xb8>)
 8004caa:	441a      	add	r2, r3
 8004cac:	693b      	ldr	r3, [r7, #16]
 8004cae:	3304      	adds	r3, #4
 8004cb0:	4619      	mov	r1, r3
 8004cb2:	4610      	mov	r0, r2
 8004cb4:	f7fe fdcb 	bl	800384e <vListInsertEnd>
 8004cb8:	e005      	b.n	8004cc6 <xTaskRemoveFromEventList+0x86>
	}
	else
	{
		/* The delayed and ready lists cannot be accessed, so hold this task
		pending until the scheduler is resumed. */
		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
 8004cba:	693b      	ldr	r3, [r7, #16]
 8004cbc:	3318      	adds	r3, #24
 8004cbe:	4619      	mov	r1, r3
 8004cc0:	480e      	ldr	r0, [pc, #56]	; (8004cfc <xTaskRemoveFromEventList+0xbc>)
 8004cc2:	f7fe fdc4 	bl	800384e <vListInsertEnd>
	}

	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
 8004cc6:	693b      	ldr	r3, [r7, #16]
 8004cc8:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8004cca:	4b0d      	ldr	r3, [pc, #52]	; (8004d00 <xTaskRemoveFromEventList+0xc0>)
 8004ccc:	681b      	ldr	r3, [r3, #0]
 8004cce:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8004cd0:	429a      	cmp	r2, r3
 8004cd2:	d905      	bls.n	8004ce0 <xTaskRemoveFromEventList+0xa0>
	{
		/* Return true if the task removed from the event list has a higher
		priority than the calling task.  This allows the calling task to know if
		it should force a context switch now. */
		xReturn = pdTRUE;
 8004cd4:	2301      	movs	r3, #1
 8004cd6:	617b      	str	r3, [r7, #20]

		/* Mark that a yield is pending in case the user is not using the
		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
		xYieldPending = pdTRUE;
 8004cd8:	4b0a      	ldr	r3, [pc, #40]	; (8004d04 <xTaskRemoveFromEventList+0xc4>)
 8004cda:	2201      	movs	r2, #1
 8004cdc:	601a      	str	r2, [r3, #0]
 8004cde:	e001      	b.n	8004ce4 <xTaskRemoveFromEventList+0xa4>
	}
	else
	{
		xReturn = pdFALSE;
 8004ce0:	2300      	movs	r3, #0
 8004ce2:	617b      	str	r3, [r7, #20]
	}

	return xReturn;
 8004ce4:	697b      	ldr	r3, [r7, #20]
}
 8004ce6:	4618      	mov	r0, r3
 8004ce8:	3718      	adds	r7, #24
 8004cea:	46bd      	mov	sp, r7
 8004cec:	bd80      	pop	{r7, pc}
 8004cee:	bf00      	nop
 8004cf0:	20000e0c 	.word	0x20000e0c
 8004cf4:	20000dec 	.word	0x20000dec
 8004cf8:	20000914 	.word	0x20000914
 8004cfc:	20000da4 	.word	0x20000da4
 8004d00:	20000910 	.word	0x20000910
 8004d04:	20000df8 	.word	0x20000df8

08004d08 <vTaskInternalSetTimeOutState>:
	taskEXIT_CRITICAL();
}
/*-----------------------------------------------------------*/

void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
{
 8004d08:	b480      	push	{r7}
 8004d0a:	b083      	sub	sp, #12
 8004d0c:	af00      	add	r7, sp, #0
 8004d0e:	6078      	str	r0, [r7, #4]
	/* For internal use only as it does not use a critical section. */
	pxTimeOut->xOverflowCount = xNumOfOverflows;
 8004d10:	4b06      	ldr	r3, [pc, #24]	; (8004d2c <vTaskInternalSetTimeOutState+0x24>)
 8004d12:	681a      	ldr	r2, [r3, #0]
 8004d14:	687b      	ldr	r3, [r7, #4]
 8004d16:	601a      	str	r2, [r3, #0]
	pxTimeOut->xTimeOnEntering = xTickCount;
 8004d18:	4b05      	ldr	r3, [pc, #20]	; (8004d30 <vTaskInternalSetTimeOutState+0x28>)
 8004d1a:	681a      	ldr	r2, [r3, #0]
 8004d1c:	687b      	ldr	r3, [r7, #4]
 8004d1e:	605a      	str	r2, [r3, #4]
}
 8004d20:	bf00      	nop
 8004d22:	370c      	adds	r7, #12
 8004d24:	46bd      	mov	sp, r7
 8004d26:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004d2a:	4770      	bx	lr
 8004d2c:	20000dfc 	.word	0x20000dfc
 8004d30:	20000de8 	.word	0x20000de8

08004d34 <xTaskCheckForTimeOut>:
/*-----------------------------------------------------------*/

BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
{
 8004d34:	b580      	push	{r7, lr}
 8004d36:	b088      	sub	sp, #32
 8004d38:	af00      	add	r7, sp, #0
 8004d3a:	6078      	str	r0, [r7, #4]
 8004d3c:	6039      	str	r1, [r7, #0]
BaseType_t xReturn;

	configASSERT( pxTimeOut );
 8004d3e:	687b      	ldr	r3, [r7, #4]
 8004d40:	2b00      	cmp	r3, #0
 8004d42:	d10a      	bne.n	8004d5a <xTaskCheckForTimeOut+0x26>
	__asm volatile
 8004d44:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004d48:	f383 8811 	msr	BASEPRI, r3
 8004d4c:	f3bf 8f6f 	isb	sy
 8004d50:	f3bf 8f4f 	dsb	sy
 8004d54:	613b      	str	r3, [r7, #16]
}
 8004d56:	bf00      	nop
 8004d58:	e7fe      	b.n	8004d58 <xTaskCheckForTimeOut+0x24>
	configASSERT( pxTicksToWait );
 8004d5a:	683b      	ldr	r3, [r7, #0]
 8004d5c:	2b00      	cmp	r3, #0
 8004d5e:	d10a      	bne.n	8004d76 <xTaskCheckForTimeOut+0x42>
	__asm volatile
 8004d60:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004d64:	f383 8811 	msr	BASEPRI, r3
 8004d68:	f3bf 8f6f 	isb	sy
 8004d6c:	f3bf 8f4f 	dsb	sy
 8004d70:	60fb      	str	r3, [r7, #12]
}
 8004d72:	bf00      	nop
 8004d74:	e7fe      	b.n	8004d74 <xTaskCheckForTimeOut+0x40>

	taskENTER_CRITICAL();
 8004d76:	f000 fe7d 	bl	8005a74 <vPortEnterCritical>
	{
		/* Minor optimisation.  The tick count cannot change in this block. */
		const TickType_t xConstTickCount = xTickCount;
 8004d7a:	4b1d      	ldr	r3, [pc, #116]	; (8004df0 <xTaskCheckForTimeOut+0xbc>)
 8004d7c:	681b      	ldr	r3, [r3, #0]
 8004d7e:	61bb      	str	r3, [r7, #24]
		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
 8004d80:	687b      	ldr	r3, [r7, #4]
 8004d82:	685b      	ldr	r3, [r3, #4]
 8004d84:	69ba      	ldr	r2, [r7, #24]
 8004d86:	1ad3      	subs	r3, r2, r3
 8004d88:	617b      	str	r3, [r7, #20]
			}
			else
		#endif

		#if ( INCLUDE_vTaskSuspend == 1 )
			if( *pxTicksToWait == portMAX_DELAY )
 8004d8a:	683b      	ldr	r3, [r7, #0]
 8004d8c:	681b      	ldr	r3, [r3, #0]
 8004d8e:	f1b3 3fff 	cmp.w	r3, #4294967295
 8004d92:	d102      	bne.n	8004d9a <xTaskCheckForTimeOut+0x66>
			{
				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
				specified is the maximum block time then the task should block
				indefinitely, and therefore never time out. */
				xReturn = pdFALSE;
 8004d94:	2300      	movs	r3, #0
 8004d96:	61fb      	str	r3, [r7, #28]
 8004d98:	e023      	b.n	8004de2 <xTaskCheckForTimeOut+0xae>
			}
			else
		#endif

		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
 8004d9a:	687b      	ldr	r3, [r7, #4]
 8004d9c:	681a      	ldr	r2, [r3, #0]
 8004d9e:	4b15      	ldr	r3, [pc, #84]	; (8004df4 <xTaskCheckForTimeOut+0xc0>)
 8004da0:	681b      	ldr	r3, [r3, #0]
 8004da2:	429a      	cmp	r2, r3
 8004da4:	d007      	beq.n	8004db6 <xTaskCheckForTimeOut+0x82>
 8004da6:	687b      	ldr	r3, [r7, #4]
 8004da8:	685b      	ldr	r3, [r3, #4]
 8004daa:	69ba      	ldr	r2, [r7, #24]
 8004dac:	429a      	cmp	r2, r3
 8004dae:	d302      	bcc.n	8004db6 <xTaskCheckForTimeOut+0x82>
			/* The tick count is greater than the time at which
			vTaskSetTimeout() was called, but has also overflowed since
			vTaskSetTimeOut() was called.  It must have wrapped all the way
			around and gone past again. This passed since vTaskSetTimeout()
			was called. */
			xReturn = pdTRUE;
 8004db0:	2301      	movs	r3, #1
 8004db2:	61fb      	str	r3, [r7, #28]
 8004db4:	e015      	b.n	8004de2 <xTaskCheckForTimeOut+0xae>
		}
		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
 8004db6:	683b      	ldr	r3, [r7, #0]
 8004db8:	681b      	ldr	r3, [r3, #0]
 8004dba:	697a      	ldr	r2, [r7, #20]
 8004dbc:	429a      	cmp	r2, r3
 8004dbe:	d20b      	bcs.n	8004dd8 <xTaskCheckForTimeOut+0xa4>
		{
			/* Not a genuine timeout. Adjust parameters for time remaining. */
			*pxTicksToWait -= xElapsedTime;
 8004dc0:	683b      	ldr	r3, [r7, #0]
 8004dc2:	681a      	ldr	r2, [r3, #0]
 8004dc4:	697b      	ldr	r3, [r7, #20]
 8004dc6:	1ad2      	subs	r2, r2, r3
 8004dc8:	683b      	ldr	r3, [r7, #0]
 8004dca:	601a      	str	r2, [r3, #0]
			vTaskInternalSetTimeOutState( pxTimeOut );
 8004dcc:	6878      	ldr	r0, [r7, #4]
 8004dce:	f7ff ff9b 	bl	8004d08 <vTaskInternalSetTimeOutState>
			xReturn = pdFALSE;
 8004dd2:	2300      	movs	r3, #0
 8004dd4:	61fb      	str	r3, [r7, #28]
 8004dd6:	e004      	b.n	8004de2 <xTaskCheckForTimeOut+0xae>
		}
		else
		{
			*pxTicksToWait = 0;
 8004dd8:	683b      	ldr	r3, [r7, #0]
 8004dda:	2200      	movs	r2, #0
 8004ddc:	601a      	str	r2, [r3, #0]
			xReturn = pdTRUE;
 8004dde:	2301      	movs	r3, #1
 8004de0:	61fb      	str	r3, [r7, #28]
		}
	}
	taskEXIT_CRITICAL();
 8004de2:	f000 fe77 	bl	8005ad4 <vPortExitCritical>

	return xReturn;
 8004de6:	69fb      	ldr	r3, [r7, #28]
}
 8004de8:	4618      	mov	r0, r3
 8004dea:	3720      	adds	r7, #32
 8004dec:	46bd      	mov	sp, r7
 8004dee:	bd80      	pop	{r7, pc}
 8004df0:	20000de8 	.word	0x20000de8
 8004df4:	20000dfc 	.word	0x20000dfc

08004df8 <vTaskMissedYield>:
/*-----------------------------------------------------------*/

void vTaskMissedYield( void )
{
 8004df8:	b480      	push	{r7}
 8004dfa:	af00      	add	r7, sp, #0
	xYieldPending = pdTRUE;
 8004dfc:	4b03      	ldr	r3, [pc, #12]	; (8004e0c <vTaskMissedYield+0x14>)
 8004dfe:	2201      	movs	r2, #1
 8004e00:	601a      	str	r2, [r3, #0]
}
 8004e02:	bf00      	nop
 8004e04:	46bd      	mov	sp, r7
 8004e06:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004e0a:	4770      	bx	lr
 8004e0c:	20000df8 	.word	0x20000df8

08004e10 <prvIdleTask>:
 *
 * void prvIdleTask( void *pvParameters );
 *
 */
static portTASK_FUNCTION( prvIdleTask, pvParameters )
{
 8004e10:	b580      	push	{r7, lr}
 8004e12:	b082      	sub	sp, #8
 8004e14:	af00      	add	r7, sp, #0
 8004e16:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* See if any tasks have deleted themselves - if so then the idle task
		is responsible for freeing the deleted task's TCB and stack. */
		prvCheckTasksWaitingTermination();
 8004e18:	f000 f852 	bl	8004ec0 <prvCheckTasksWaitingTermination>

			A critical region is not required here as we are just reading from
			the list, and an occasional incorrect value will not matter.  If
			the ready list at the idle priority contains more than one task
			then a task other than the idle task is ready to execute. */
			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
 8004e1c:	4b06      	ldr	r3, [pc, #24]	; (8004e38 <prvIdleTask+0x28>)
 8004e1e:	681b      	ldr	r3, [r3, #0]
 8004e20:	2b01      	cmp	r3, #1
 8004e22:	d9f9      	bls.n	8004e18 <prvIdleTask+0x8>
			{
				taskYIELD();
 8004e24:	4b05      	ldr	r3, [pc, #20]	; (8004e3c <prvIdleTask+0x2c>)
 8004e26:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8004e2a:	601a      	str	r2, [r3, #0]
 8004e2c:	f3bf 8f4f 	dsb	sy
 8004e30:	f3bf 8f6f 	isb	sy
		prvCheckTasksWaitingTermination();
 8004e34:	e7f0      	b.n	8004e18 <prvIdleTask+0x8>
 8004e36:	bf00      	nop
 8004e38:	20000914 	.word	0x20000914
 8004e3c:	e000ed04 	.word	0xe000ed04

08004e40 <prvInitialiseTaskLists>:

#endif /* portUSING_MPU_WRAPPERS */
/*-----------------------------------------------------------*/

static void prvInitialiseTaskLists( void )
{
 8004e40:	b580      	push	{r7, lr}
 8004e42:	b082      	sub	sp, #8
 8004e44:	af00      	add	r7, sp, #0
UBaseType_t uxPriority;

	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8004e46:	2300      	movs	r3, #0
 8004e48:	607b      	str	r3, [r7, #4]
 8004e4a:	e00c      	b.n	8004e66 <prvInitialiseTaskLists+0x26>
	{
		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
 8004e4c:	687a      	ldr	r2, [r7, #4]
 8004e4e:	4613      	mov	r3, r2
 8004e50:	009b      	lsls	r3, r3, #2
 8004e52:	4413      	add	r3, r2
 8004e54:	009b      	lsls	r3, r3, #2
 8004e56:	4a12      	ldr	r2, [pc, #72]	; (8004ea0 <prvInitialiseTaskLists+0x60>)
 8004e58:	4413      	add	r3, r2
 8004e5a:	4618      	mov	r0, r3
 8004e5c:	f7fe fcca 	bl	80037f4 <vListInitialise>
	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
 8004e60:	687b      	ldr	r3, [r7, #4]
 8004e62:	3301      	adds	r3, #1
 8004e64:	607b      	str	r3, [r7, #4]
 8004e66:	687b      	ldr	r3, [r7, #4]
 8004e68:	2b37      	cmp	r3, #55	; 0x37
 8004e6a:	d9ef      	bls.n	8004e4c <prvInitialiseTaskLists+0xc>
	}

	vListInitialise( &xDelayedTaskList1 );
 8004e6c:	480d      	ldr	r0, [pc, #52]	; (8004ea4 <prvInitialiseTaskLists+0x64>)
 8004e6e:	f7fe fcc1 	bl	80037f4 <vListInitialise>
	vListInitialise( &xDelayedTaskList2 );
 8004e72:	480d      	ldr	r0, [pc, #52]	; (8004ea8 <prvInitialiseTaskLists+0x68>)
 8004e74:	f7fe fcbe 	bl	80037f4 <vListInitialise>
	vListInitialise( &xPendingReadyList );
 8004e78:	480c      	ldr	r0, [pc, #48]	; (8004eac <prvInitialiseTaskLists+0x6c>)
 8004e7a:	f7fe fcbb 	bl	80037f4 <vListInitialise>

	#if ( INCLUDE_vTaskDelete == 1 )
	{
		vListInitialise( &xTasksWaitingTermination );
 8004e7e:	480c      	ldr	r0, [pc, #48]	; (8004eb0 <prvInitialiseTaskLists+0x70>)
 8004e80:	f7fe fcb8 	bl	80037f4 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskDelete */

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		vListInitialise( &xSuspendedTaskList );
 8004e84:	480b      	ldr	r0, [pc, #44]	; (8004eb4 <prvInitialiseTaskLists+0x74>)
 8004e86:	f7fe fcb5 	bl	80037f4 <vListInitialise>
	}
	#endif /* INCLUDE_vTaskSuspend */

	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
	using list2. */
	pxDelayedTaskList = &xDelayedTaskList1;
 8004e8a:	4b0b      	ldr	r3, [pc, #44]	; (8004eb8 <prvInitialiseTaskLists+0x78>)
 8004e8c:	4a05      	ldr	r2, [pc, #20]	; (8004ea4 <prvInitialiseTaskLists+0x64>)
 8004e8e:	601a      	str	r2, [r3, #0]
	pxOverflowDelayedTaskList = &xDelayedTaskList2;
 8004e90:	4b0a      	ldr	r3, [pc, #40]	; (8004ebc <prvInitialiseTaskLists+0x7c>)
 8004e92:	4a05      	ldr	r2, [pc, #20]	; (8004ea8 <prvInitialiseTaskLists+0x68>)
 8004e94:	601a      	str	r2, [r3, #0]
}
 8004e96:	bf00      	nop
 8004e98:	3708      	adds	r7, #8
 8004e9a:	46bd      	mov	sp, r7
 8004e9c:	bd80      	pop	{r7, pc}
 8004e9e:	bf00      	nop
 8004ea0:	20000914 	.word	0x20000914
 8004ea4:	20000d74 	.word	0x20000d74
 8004ea8:	20000d88 	.word	0x20000d88
 8004eac:	20000da4 	.word	0x20000da4
 8004eb0:	20000db8 	.word	0x20000db8
 8004eb4:	20000dd0 	.word	0x20000dd0
 8004eb8:	20000d9c 	.word	0x20000d9c
 8004ebc:	20000da0 	.word	0x20000da0

08004ec0 <prvCheckTasksWaitingTermination>:
/*-----------------------------------------------------------*/

static void prvCheckTasksWaitingTermination( void )
{
 8004ec0:	b580      	push	{r7, lr}
 8004ec2:	b082      	sub	sp, #8
 8004ec4:	af00      	add	r7, sp, #0
	{
		TCB_t *pxTCB;

		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
		being called too often in the idle task. */
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8004ec6:	e019      	b.n	8004efc <prvCheckTasksWaitingTermination+0x3c>
		{
			taskENTER_CRITICAL();
 8004ec8:	f000 fdd4 	bl	8005a74 <vPortEnterCritical>
			{
				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8004ecc:	4b10      	ldr	r3, [pc, #64]	; (8004f10 <prvCheckTasksWaitingTermination+0x50>)
 8004ece:	68db      	ldr	r3, [r3, #12]
 8004ed0:	68db      	ldr	r3, [r3, #12]
 8004ed2:	607b      	str	r3, [r7, #4]
				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
 8004ed4:	687b      	ldr	r3, [r7, #4]
 8004ed6:	3304      	adds	r3, #4
 8004ed8:	4618      	mov	r0, r3
 8004eda:	f7fe fd15 	bl	8003908 <uxListRemove>
				--uxCurrentNumberOfTasks;
 8004ede:	4b0d      	ldr	r3, [pc, #52]	; (8004f14 <prvCheckTasksWaitingTermination+0x54>)
 8004ee0:	681b      	ldr	r3, [r3, #0]
 8004ee2:	3b01      	subs	r3, #1
 8004ee4:	4a0b      	ldr	r2, [pc, #44]	; (8004f14 <prvCheckTasksWaitingTermination+0x54>)
 8004ee6:	6013      	str	r3, [r2, #0]
				--uxDeletedTasksWaitingCleanUp;
 8004ee8:	4b0b      	ldr	r3, [pc, #44]	; (8004f18 <prvCheckTasksWaitingTermination+0x58>)
 8004eea:	681b      	ldr	r3, [r3, #0]
 8004eec:	3b01      	subs	r3, #1
 8004eee:	4a0a      	ldr	r2, [pc, #40]	; (8004f18 <prvCheckTasksWaitingTermination+0x58>)
 8004ef0:	6013      	str	r3, [r2, #0]
			}
			taskEXIT_CRITICAL();
 8004ef2:	f000 fdef 	bl	8005ad4 <vPortExitCritical>

			prvDeleteTCB( pxTCB );
 8004ef6:	6878      	ldr	r0, [r7, #4]
 8004ef8:	f000 f810 	bl	8004f1c <prvDeleteTCB>
		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
 8004efc:	4b06      	ldr	r3, [pc, #24]	; (8004f18 <prvCheckTasksWaitingTermination+0x58>)
 8004efe:	681b      	ldr	r3, [r3, #0]
 8004f00:	2b00      	cmp	r3, #0
 8004f02:	d1e1      	bne.n	8004ec8 <prvCheckTasksWaitingTermination+0x8>
		}
	}
	#endif /* INCLUDE_vTaskDelete */
}
 8004f04:	bf00      	nop
 8004f06:	bf00      	nop
 8004f08:	3708      	adds	r7, #8
 8004f0a:	46bd      	mov	sp, r7
 8004f0c:	bd80      	pop	{r7, pc}
 8004f0e:	bf00      	nop
 8004f10:	20000db8 	.word	0x20000db8
 8004f14:	20000de4 	.word	0x20000de4
 8004f18:	20000dcc 	.word	0x20000dcc

08004f1c <prvDeleteTCB>:
/*-----------------------------------------------------------*/

#if ( INCLUDE_vTaskDelete == 1 )

	static void prvDeleteTCB( TCB_t *pxTCB )
	{
 8004f1c:	b580      	push	{r7, lr}
 8004f1e:	b084      	sub	sp, #16
 8004f20:	af00      	add	r7, sp, #0
 8004f22:	6078      	str	r0, [r7, #4]
		to the task to free any memory allocated at the application level.
		See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
		for additional information. */
		#if ( configUSE_NEWLIB_REENTRANT == 1 )
		{
			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
 8004f24:	687b      	ldr	r3, [r7, #4]
 8004f26:	3354      	adds	r3, #84	; 0x54
 8004f28:	4618      	mov	r0, r3
 8004f2a:	f001 f8b7 	bl	800609c <_reclaim_reent>
		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
		{
			/* The task could have been allocated statically or dynamically, so
			check what was statically allocated before trying to free the
			memory. */
			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
 8004f2e:	687b      	ldr	r3, [r7, #4]
 8004f30:	f893 30a5 	ldrb.w	r3, [r3, #165]	; 0xa5
 8004f34:	2b00      	cmp	r3, #0
 8004f36:	d108      	bne.n	8004f4a <prvDeleteTCB+0x2e>
			{
				/* Both the stack and TCB were allocated dynamically, so both
				must be freed. */
				vPortFree( pxTCB->pxStack );
 8004f38:	687b      	ldr	r3, [r7, #4]
 8004f3a:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8004f3c:	4618      	mov	r0, r3
 8004f3e:	f000 ff87 	bl	8005e50 <vPortFree>
				vPortFree( pxTCB );
 8004f42:	6878      	ldr	r0, [r7, #4]
 8004f44:	f000 ff84 	bl	8005e50 <vPortFree>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
				mtCOVERAGE_TEST_MARKER();
			}
		}
		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
	}
 8004f48:	e018      	b.n	8004f7c <prvDeleteTCB+0x60>
			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
 8004f4a:	687b      	ldr	r3, [r7, #4]
 8004f4c:	f893 30a5 	ldrb.w	r3, [r3, #165]	; 0xa5
 8004f50:	2b01      	cmp	r3, #1
 8004f52:	d103      	bne.n	8004f5c <prvDeleteTCB+0x40>
				vPortFree( pxTCB );
 8004f54:	6878      	ldr	r0, [r7, #4]
 8004f56:	f000 ff7b 	bl	8005e50 <vPortFree>
	}
 8004f5a:	e00f      	b.n	8004f7c <prvDeleteTCB+0x60>
				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
 8004f5c:	687b      	ldr	r3, [r7, #4]
 8004f5e:	f893 30a5 	ldrb.w	r3, [r3, #165]	; 0xa5
 8004f62:	2b02      	cmp	r3, #2
 8004f64:	d00a      	beq.n	8004f7c <prvDeleteTCB+0x60>
	__asm volatile
 8004f66:	f04f 0350 	mov.w	r3, #80	; 0x50
 8004f6a:	f383 8811 	msr	BASEPRI, r3
 8004f6e:	f3bf 8f6f 	isb	sy
 8004f72:	f3bf 8f4f 	dsb	sy
 8004f76:	60fb      	str	r3, [r7, #12]
}
 8004f78:	bf00      	nop
 8004f7a:	e7fe      	b.n	8004f7a <prvDeleteTCB+0x5e>
	}
 8004f7c:	bf00      	nop
 8004f7e:	3710      	adds	r7, #16
 8004f80:	46bd      	mov	sp, r7
 8004f82:	bd80      	pop	{r7, pc}

08004f84 <prvResetNextTaskUnblockTime>:

#endif /* INCLUDE_vTaskDelete */
/*-----------------------------------------------------------*/

static void prvResetNextTaskUnblockTime( void )
{
 8004f84:	b480      	push	{r7}
 8004f86:	b083      	sub	sp, #12
 8004f88:	af00      	add	r7, sp, #0
TCB_t *pxTCB;

	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
 8004f8a:	4b0c      	ldr	r3, [pc, #48]	; (8004fbc <prvResetNextTaskUnblockTime+0x38>)
 8004f8c:	681b      	ldr	r3, [r3, #0]
 8004f8e:	681b      	ldr	r3, [r3, #0]
 8004f90:	2b00      	cmp	r3, #0
 8004f92:	d104      	bne.n	8004f9e <prvResetNextTaskUnblockTime+0x1a>
	{
		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
		the maximum possible value so it is	extremely unlikely that the
		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
		there is an item in the delayed list. */
		xNextTaskUnblockTime = portMAX_DELAY;
 8004f94:	4b0a      	ldr	r3, [pc, #40]	; (8004fc0 <prvResetNextTaskUnblockTime+0x3c>)
 8004f96:	f04f 32ff 	mov.w	r2, #4294967295
 8004f9a:	601a      	str	r2, [r3, #0]
		which the task at the head of the delayed list should be removed
		from the Blocked state. */
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
	}
}
 8004f9c:	e008      	b.n	8004fb0 <prvResetNextTaskUnblockTime+0x2c>
		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 8004f9e:	4b07      	ldr	r3, [pc, #28]	; (8004fbc <prvResetNextTaskUnblockTime+0x38>)
 8004fa0:	681b      	ldr	r3, [r3, #0]
 8004fa2:	68db      	ldr	r3, [r3, #12]
 8004fa4:	68db      	ldr	r3, [r3, #12]
 8004fa6:	607b      	str	r3, [r7, #4]
		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
 8004fa8:	687b      	ldr	r3, [r7, #4]
 8004faa:	685b      	ldr	r3, [r3, #4]
 8004fac:	4a04      	ldr	r2, [pc, #16]	; (8004fc0 <prvResetNextTaskUnblockTime+0x3c>)
 8004fae:	6013      	str	r3, [r2, #0]
}
 8004fb0:	bf00      	nop
 8004fb2:	370c      	adds	r7, #12
 8004fb4:	46bd      	mov	sp, r7
 8004fb6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004fba:	4770      	bx	lr
 8004fbc:	20000d9c 	.word	0x20000d9c
 8004fc0:	20000e04 	.word	0x20000e04

08004fc4 <xTaskGetSchedulerState>:
/*-----------------------------------------------------------*/

#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )

	BaseType_t xTaskGetSchedulerState( void )
	{
 8004fc4:	b480      	push	{r7}
 8004fc6:	b083      	sub	sp, #12
 8004fc8:	af00      	add	r7, sp, #0
	BaseType_t xReturn;

		if( xSchedulerRunning == pdFALSE )
 8004fca:	4b0b      	ldr	r3, [pc, #44]	; (8004ff8 <xTaskGetSchedulerState+0x34>)
 8004fcc:	681b      	ldr	r3, [r3, #0]
 8004fce:	2b00      	cmp	r3, #0
 8004fd0:	d102      	bne.n	8004fd8 <xTaskGetSchedulerState+0x14>
		{
			xReturn = taskSCHEDULER_NOT_STARTED;
 8004fd2:	2301      	movs	r3, #1
 8004fd4:	607b      	str	r3, [r7, #4]
 8004fd6:	e008      	b.n	8004fea <xTaskGetSchedulerState+0x26>
		}
		else
		{
			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
 8004fd8:	4b08      	ldr	r3, [pc, #32]	; (8004ffc <xTaskGetSchedulerState+0x38>)
 8004fda:	681b      	ldr	r3, [r3, #0]
 8004fdc:	2b00      	cmp	r3, #0
 8004fde:	d102      	bne.n	8004fe6 <xTaskGetSchedulerState+0x22>
			{
				xReturn = taskSCHEDULER_RUNNING;
 8004fe0:	2302      	movs	r3, #2
 8004fe2:	607b      	str	r3, [r7, #4]
 8004fe4:	e001      	b.n	8004fea <xTaskGetSchedulerState+0x26>
			}
			else
			{
				xReturn = taskSCHEDULER_SUSPENDED;
 8004fe6:	2300      	movs	r3, #0
 8004fe8:	607b      	str	r3, [r7, #4]
			}
		}

		return xReturn;
 8004fea:	687b      	ldr	r3, [r7, #4]
	}
 8004fec:	4618      	mov	r0, r3
 8004fee:	370c      	adds	r7, #12
 8004ff0:	46bd      	mov	sp, r7
 8004ff2:	f85d 7b04 	ldr.w	r7, [sp], #4
 8004ff6:	4770      	bx	lr
 8004ff8:	20000df0 	.word	0x20000df0
 8004ffc:	20000e0c 	.word	0x20000e0c

08005000 <xTaskPriorityDisinherit>:
/*-----------------------------------------------------------*/

#if ( configUSE_MUTEXES == 1 )

	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
	{
 8005000:	b580      	push	{r7, lr}
 8005002:	b086      	sub	sp, #24
 8005004:	af00      	add	r7, sp, #0
 8005006:	6078      	str	r0, [r7, #4]
	TCB_t * const pxTCB = pxMutexHolder;
 8005008:	687b      	ldr	r3, [r7, #4]
 800500a:	613b      	str	r3, [r7, #16]
	BaseType_t xReturn = pdFALSE;
 800500c:	2300      	movs	r3, #0
 800500e:	617b      	str	r3, [r7, #20]

		if( pxMutexHolder != NULL )
 8005010:	687b      	ldr	r3, [r7, #4]
 8005012:	2b00      	cmp	r3, #0
 8005014:	d056      	beq.n	80050c4 <xTaskPriorityDisinherit+0xc4>
		{
			/* A task can only have an inherited priority if it holds the mutex.
			If the mutex is held by a task then it cannot be given from an
			interrupt, and if a mutex is given by the holding task then it must
			be the running state task. */
			configASSERT( pxTCB == pxCurrentTCB );
 8005016:	4b2e      	ldr	r3, [pc, #184]	; (80050d0 <xTaskPriorityDisinherit+0xd0>)
 8005018:	681b      	ldr	r3, [r3, #0]
 800501a:	693a      	ldr	r2, [r7, #16]
 800501c:	429a      	cmp	r2, r3
 800501e:	d00a      	beq.n	8005036 <xTaskPriorityDisinherit+0x36>
	__asm volatile
 8005020:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005024:	f383 8811 	msr	BASEPRI, r3
 8005028:	f3bf 8f6f 	isb	sy
 800502c:	f3bf 8f4f 	dsb	sy
 8005030:	60fb      	str	r3, [r7, #12]
}
 8005032:	bf00      	nop
 8005034:	e7fe      	b.n	8005034 <xTaskPriorityDisinherit+0x34>
			configASSERT( pxTCB->uxMutexesHeld );
 8005036:	693b      	ldr	r3, [r7, #16]
 8005038:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 800503a:	2b00      	cmp	r3, #0
 800503c:	d10a      	bne.n	8005054 <xTaskPriorityDisinherit+0x54>
	__asm volatile
 800503e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005042:	f383 8811 	msr	BASEPRI, r3
 8005046:	f3bf 8f6f 	isb	sy
 800504a:	f3bf 8f4f 	dsb	sy
 800504e:	60bb      	str	r3, [r7, #8]
}
 8005050:	bf00      	nop
 8005052:	e7fe      	b.n	8005052 <xTaskPriorityDisinherit+0x52>
			( pxTCB->uxMutexesHeld )--;
 8005054:	693b      	ldr	r3, [r7, #16]
 8005056:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 8005058:	1e5a      	subs	r2, r3, #1
 800505a:	693b      	ldr	r3, [r7, #16]
 800505c:	651a      	str	r2, [r3, #80]	; 0x50

			/* Has the holder of the mutex inherited the priority of another
			task? */
			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
 800505e:	693b      	ldr	r3, [r7, #16]
 8005060:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8005062:	693b      	ldr	r3, [r7, #16]
 8005064:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 8005066:	429a      	cmp	r2, r3
 8005068:	d02c      	beq.n	80050c4 <xTaskPriorityDisinherit+0xc4>
			{
				/* Only disinherit if no other mutexes are held. */
				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
 800506a:	693b      	ldr	r3, [r7, #16]
 800506c:	6d1b      	ldr	r3, [r3, #80]	; 0x50
 800506e:	2b00      	cmp	r3, #0
 8005070:	d128      	bne.n	80050c4 <xTaskPriorityDisinherit+0xc4>
					/* A task can only have an inherited priority if it holds
					the mutex.  If the mutex is held by a task then it cannot be
					given from an interrupt, and if a mutex is given by the
					holding task then it must be the running state task.  Remove
					the holding task from the ready/delayed list. */
					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 8005072:	693b      	ldr	r3, [r7, #16]
 8005074:	3304      	adds	r3, #4
 8005076:	4618      	mov	r0, r3
 8005078:	f7fe fc46 	bl	8003908 <uxListRemove>
					}

					/* Disinherit the priority before adding the task into the
					new	ready list. */
					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
					pxTCB->uxPriority = pxTCB->uxBasePriority;
 800507c:	693b      	ldr	r3, [r7, #16]
 800507e:	6cda      	ldr	r2, [r3, #76]	; 0x4c
 8005080:	693b      	ldr	r3, [r7, #16]
 8005082:	62da      	str	r2, [r3, #44]	; 0x2c

					/* Reset the event list item value.  It cannot be in use for
					any other purpose if this task is running, and it must be
					running to give back the mutex. */
					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 8005084:	693b      	ldr	r3, [r7, #16]
 8005086:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8005088:	f1c3 0238 	rsb	r2, r3, #56	; 0x38
 800508c:	693b      	ldr	r3, [r7, #16]
 800508e:	619a      	str	r2, [r3, #24]
					prvAddTaskToReadyList( pxTCB );
 8005090:	693b      	ldr	r3, [r7, #16]
 8005092:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 8005094:	4b0f      	ldr	r3, [pc, #60]	; (80050d4 <xTaskPriorityDisinherit+0xd4>)
 8005096:	681b      	ldr	r3, [r3, #0]
 8005098:	429a      	cmp	r2, r3
 800509a:	d903      	bls.n	80050a4 <xTaskPriorityDisinherit+0xa4>
 800509c:	693b      	ldr	r3, [r7, #16]
 800509e:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 80050a0:	4a0c      	ldr	r2, [pc, #48]	; (80050d4 <xTaskPriorityDisinherit+0xd4>)
 80050a2:	6013      	str	r3, [r2, #0]
 80050a4:	693b      	ldr	r3, [r7, #16]
 80050a6:	6ada      	ldr	r2, [r3, #44]	; 0x2c
 80050a8:	4613      	mov	r3, r2
 80050aa:	009b      	lsls	r3, r3, #2
 80050ac:	4413      	add	r3, r2
 80050ae:	009b      	lsls	r3, r3, #2
 80050b0:	4a09      	ldr	r2, [pc, #36]	; (80050d8 <xTaskPriorityDisinherit+0xd8>)
 80050b2:	441a      	add	r2, r3
 80050b4:	693b      	ldr	r3, [r7, #16]
 80050b6:	3304      	adds	r3, #4
 80050b8:	4619      	mov	r1, r3
 80050ba:	4610      	mov	r0, r2
 80050bc:	f7fe fbc7 	bl	800384e <vListInsertEnd>
					in an order different to that in which they were taken.
					If a context switch did not occur when the first mutex was
					returned, even if a task was waiting on it, then a context
					switch should occur when the last mutex is returned whether
					a task is waiting on it or not. */
					xReturn = pdTRUE;
 80050c0:	2301      	movs	r3, #1
 80050c2:	617b      	str	r3, [r7, #20]
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}

		return xReturn;
 80050c4:	697b      	ldr	r3, [r7, #20]
	}
 80050c6:	4618      	mov	r0, r3
 80050c8:	3718      	adds	r7, #24
 80050ca:	46bd      	mov	sp, r7
 80050cc:	bd80      	pop	{r7, pc}
 80050ce:	bf00      	nop
 80050d0:	20000910 	.word	0x20000910
 80050d4:	20000dec 	.word	0x20000dec
 80050d8:	20000914 	.word	0x20000914

080050dc <prvAddCurrentTaskToDelayedList>:

#endif
/*-----------------------------------------------------------*/

static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
{
 80050dc:	b580      	push	{r7, lr}
 80050de:	b084      	sub	sp, #16
 80050e0:	af00      	add	r7, sp, #0
 80050e2:	6078      	str	r0, [r7, #4]
 80050e4:	6039      	str	r1, [r7, #0]
TickType_t xTimeToWake;
const TickType_t xConstTickCount = xTickCount;
 80050e6:	4b21      	ldr	r3, [pc, #132]	; (800516c <prvAddCurrentTaskToDelayedList+0x90>)
 80050e8:	681b      	ldr	r3, [r3, #0]
 80050ea:	60fb      	str	r3, [r7, #12]
	}
	#endif

	/* Remove the task from the ready list before adding it to the blocked list
	as the same list item is used for both lists. */
	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
 80050ec:	4b20      	ldr	r3, [pc, #128]	; (8005170 <prvAddCurrentTaskToDelayedList+0x94>)
 80050ee:	681b      	ldr	r3, [r3, #0]
 80050f0:	3304      	adds	r3, #4
 80050f2:	4618      	mov	r0, r3
 80050f4:	f7fe fc08 	bl	8003908 <uxListRemove>
		mtCOVERAGE_TEST_MARKER();
	}

	#if ( INCLUDE_vTaskSuspend == 1 )
	{
		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
 80050f8:	687b      	ldr	r3, [r7, #4]
 80050fa:	f1b3 3fff 	cmp.w	r3, #4294967295
 80050fe:	d10a      	bne.n	8005116 <prvAddCurrentTaskToDelayedList+0x3a>
 8005100:	683b      	ldr	r3, [r7, #0]
 8005102:	2b00      	cmp	r3, #0
 8005104:	d007      	beq.n	8005116 <prvAddCurrentTaskToDelayedList+0x3a>
		{
			/* Add the task to the suspended task list instead of a delayed task
			list to ensure it is not woken by a timing event.  It will block
			indefinitely. */
			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8005106:	4b1a      	ldr	r3, [pc, #104]	; (8005170 <prvAddCurrentTaskToDelayedList+0x94>)
 8005108:	681b      	ldr	r3, [r3, #0]
 800510a:	3304      	adds	r3, #4
 800510c:	4619      	mov	r1, r3
 800510e:	4819      	ldr	r0, [pc, #100]	; (8005174 <prvAddCurrentTaskToDelayedList+0x98>)
 8005110:	f7fe fb9d 	bl	800384e <vListInsertEnd>

		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
		( void ) xCanBlockIndefinitely;
	}
	#endif /* INCLUDE_vTaskSuspend */
}
 8005114:	e026      	b.n	8005164 <prvAddCurrentTaskToDelayedList+0x88>
			xTimeToWake = xConstTickCount + xTicksToWait;
 8005116:	68fa      	ldr	r2, [r7, #12]
 8005118:	687b      	ldr	r3, [r7, #4]
 800511a:	4413      	add	r3, r2
 800511c:	60bb      	str	r3, [r7, #8]
			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
 800511e:	4b14      	ldr	r3, [pc, #80]	; (8005170 <prvAddCurrentTaskToDelayedList+0x94>)
 8005120:	681b      	ldr	r3, [r3, #0]
 8005122:	68ba      	ldr	r2, [r7, #8]
 8005124:	605a      	str	r2, [r3, #4]
			if( xTimeToWake < xConstTickCount )
 8005126:	68ba      	ldr	r2, [r7, #8]
 8005128:	68fb      	ldr	r3, [r7, #12]
 800512a:	429a      	cmp	r2, r3
 800512c:	d209      	bcs.n	8005142 <prvAddCurrentTaskToDelayedList+0x66>
				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 800512e:	4b12      	ldr	r3, [pc, #72]	; (8005178 <prvAddCurrentTaskToDelayedList+0x9c>)
 8005130:	681a      	ldr	r2, [r3, #0]
 8005132:	4b0f      	ldr	r3, [pc, #60]	; (8005170 <prvAddCurrentTaskToDelayedList+0x94>)
 8005134:	681b      	ldr	r3, [r3, #0]
 8005136:	3304      	adds	r3, #4
 8005138:	4619      	mov	r1, r3
 800513a:	4610      	mov	r0, r2
 800513c:	f7fe fbab 	bl	8003896 <vListInsert>
}
 8005140:	e010      	b.n	8005164 <prvAddCurrentTaskToDelayedList+0x88>
				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
 8005142:	4b0e      	ldr	r3, [pc, #56]	; (800517c <prvAddCurrentTaskToDelayedList+0xa0>)
 8005144:	681a      	ldr	r2, [r3, #0]
 8005146:	4b0a      	ldr	r3, [pc, #40]	; (8005170 <prvAddCurrentTaskToDelayedList+0x94>)
 8005148:	681b      	ldr	r3, [r3, #0]
 800514a:	3304      	adds	r3, #4
 800514c:	4619      	mov	r1, r3
 800514e:	4610      	mov	r0, r2
 8005150:	f7fe fba1 	bl	8003896 <vListInsert>
				if( xTimeToWake < xNextTaskUnblockTime )
 8005154:	4b0a      	ldr	r3, [pc, #40]	; (8005180 <prvAddCurrentTaskToDelayedList+0xa4>)
 8005156:	681b      	ldr	r3, [r3, #0]
 8005158:	68ba      	ldr	r2, [r7, #8]
 800515a:	429a      	cmp	r2, r3
 800515c:	d202      	bcs.n	8005164 <prvAddCurrentTaskToDelayedList+0x88>
					xNextTaskUnblockTime = xTimeToWake;
 800515e:	4a08      	ldr	r2, [pc, #32]	; (8005180 <prvAddCurrentTaskToDelayedList+0xa4>)
 8005160:	68bb      	ldr	r3, [r7, #8]
 8005162:	6013      	str	r3, [r2, #0]
}
 8005164:	bf00      	nop
 8005166:	3710      	adds	r7, #16
 8005168:	46bd      	mov	sp, r7
 800516a:	bd80      	pop	{r7, pc}
 800516c:	20000de8 	.word	0x20000de8
 8005170:	20000910 	.word	0x20000910
 8005174:	20000dd0 	.word	0x20000dd0
 8005178:	20000da0 	.word	0x20000da0
 800517c:	20000d9c 	.word	0x20000d9c
 8005180:	20000e04 	.word	0x20000e04

08005184 <xTimerCreateTimerTask>:
									TimerCallbackFunction_t pxCallbackFunction,
									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
/*-----------------------------------------------------------*/

BaseType_t xTimerCreateTimerTask( void )
{
 8005184:	b580      	push	{r7, lr}
 8005186:	b08a      	sub	sp, #40	; 0x28
 8005188:	af04      	add	r7, sp, #16
BaseType_t xReturn = pdFAIL;
 800518a:	2300      	movs	r3, #0
 800518c:	617b      	str	r3, [r7, #20]

	/* This function is called when the scheduler is started if
	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
	timer service task has been created/initialised.  If timers have already
	been created then the initialisation will already have been performed. */
	prvCheckForValidListAndQueue();
 800518e:	f000 fb07 	bl	80057a0 <prvCheckForValidListAndQueue>

	if( xTimerQueue != NULL )
 8005192:	4b1c      	ldr	r3, [pc, #112]	; (8005204 <xTimerCreateTimerTask+0x80>)
 8005194:	681b      	ldr	r3, [r3, #0]
 8005196:	2b00      	cmp	r3, #0
 8005198:	d021      	beq.n	80051de <xTimerCreateTimerTask+0x5a>
	{
		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
		{
			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
 800519a:	2300      	movs	r3, #0
 800519c:	60fb      	str	r3, [r7, #12]
			StackType_t *pxTimerTaskStackBuffer = NULL;
 800519e:	2300      	movs	r3, #0
 80051a0:	60bb      	str	r3, [r7, #8]
			uint32_t ulTimerTaskStackSize;

			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
 80051a2:	1d3a      	adds	r2, r7, #4
 80051a4:	f107 0108 	add.w	r1, r7, #8
 80051a8:	f107 030c 	add.w	r3, r7, #12
 80051ac:	4618      	mov	r0, r3
 80051ae:	f7fe fb07 	bl	80037c0 <vApplicationGetTimerTaskMemory>
			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
 80051b2:	6879      	ldr	r1, [r7, #4]
 80051b4:	68bb      	ldr	r3, [r7, #8]
 80051b6:	68fa      	ldr	r2, [r7, #12]
 80051b8:	9202      	str	r2, [sp, #8]
 80051ba:	9301      	str	r3, [sp, #4]
 80051bc:	2302      	movs	r3, #2
 80051be:	9300      	str	r3, [sp, #0]
 80051c0:	2300      	movs	r3, #0
 80051c2:	460a      	mov	r2, r1
 80051c4:	4910      	ldr	r1, [pc, #64]	; (8005208 <xTimerCreateTimerTask+0x84>)
 80051c6:	4811      	ldr	r0, [pc, #68]	; (800520c <xTimerCreateTimerTask+0x88>)
 80051c8:	f7ff f8b4 	bl	8004334 <xTaskCreateStatic>
 80051cc:	4603      	mov	r3, r0
 80051ce:	4a10      	ldr	r2, [pc, #64]	; (8005210 <xTimerCreateTimerTask+0x8c>)
 80051d0:	6013      	str	r3, [r2, #0]
													NULL,
													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
													pxTimerTaskStackBuffer,
													pxTimerTaskTCBBuffer );

			if( xTimerTaskHandle != NULL )
 80051d2:	4b0f      	ldr	r3, [pc, #60]	; (8005210 <xTimerCreateTimerTask+0x8c>)
 80051d4:	681b      	ldr	r3, [r3, #0]
 80051d6:	2b00      	cmp	r3, #0
 80051d8:	d001      	beq.n	80051de <xTimerCreateTimerTask+0x5a>
			{
				xReturn = pdPASS;
 80051da:	2301      	movs	r3, #1
 80051dc:	617b      	str	r3, [r7, #20]
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	configASSERT( xReturn );
 80051de:	697b      	ldr	r3, [r7, #20]
 80051e0:	2b00      	cmp	r3, #0
 80051e2:	d10a      	bne.n	80051fa <xTimerCreateTimerTask+0x76>
	__asm volatile
 80051e4:	f04f 0350 	mov.w	r3, #80	; 0x50
 80051e8:	f383 8811 	msr	BASEPRI, r3
 80051ec:	f3bf 8f6f 	isb	sy
 80051f0:	f3bf 8f4f 	dsb	sy
 80051f4:	613b      	str	r3, [r7, #16]
}
 80051f6:	bf00      	nop
 80051f8:	e7fe      	b.n	80051f8 <xTimerCreateTimerTask+0x74>
	return xReturn;
 80051fa:	697b      	ldr	r3, [r7, #20]
}
 80051fc:	4618      	mov	r0, r3
 80051fe:	3718      	adds	r7, #24
 8005200:	46bd      	mov	sp, r7
 8005202:	bd80      	pop	{r7, pc}
 8005204:	20000e40 	.word	0x20000e40
 8005208:	080062b4 	.word	0x080062b4
 800520c:	08005349 	.word	0x08005349
 8005210:	20000e44 	.word	0x20000e44

08005214 <xTimerGenericCommand>:
	}
}
/*-----------------------------------------------------------*/

BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
{
 8005214:	b580      	push	{r7, lr}
 8005216:	b08a      	sub	sp, #40	; 0x28
 8005218:	af00      	add	r7, sp, #0
 800521a:	60f8      	str	r0, [r7, #12]
 800521c:	60b9      	str	r1, [r7, #8]
 800521e:	607a      	str	r2, [r7, #4]
 8005220:	603b      	str	r3, [r7, #0]
BaseType_t xReturn = pdFAIL;
 8005222:	2300      	movs	r3, #0
 8005224:	627b      	str	r3, [r7, #36]	; 0x24
DaemonTaskMessage_t xMessage;

	configASSERT( xTimer );
 8005226:	68fb      	ldr	r3, [r7, #12]
 8005228:	2b00      	cmp	r3, #0
 800522a:	d10a      	bne.n	8005242 <xTimerGenericCommand+0x2e>
	__asm volatile
 800522c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005230:	f383 8811 	msr	BASEPRI, r3
 8005234:	f3bf 8f6f 	isb	sy
 8005238:	f3bf 8f4f 	dsb	sy
 800523c:	623b      	str	r3, [r7, #32]
}
 800523e:	bf00      	nop
 8005240:	e7fe      	b.n	8005240 <xTimerGenericCommand+0x2c>

	/* Send a message to the timer service task to perform a particular action
	on a particular timer definition. */
	if( xTimerQueue != NULL )
 8005242:	4b1a      	ldr	r3, [pc, #104]	; (80052ac <xTimerGenericCommand+0x98>)
 8005244:	681b      	ldr	r3, [r3, #0]
 8005246:	2b00      	cmp	r3, #0
 8005248:	d02a      	beq.n	80052a0 <xTimerGenericCommand+0x8c>
	{
		/* Send a command to the timer service task to start the xTimer timer. */
		xMessage.xMessageID = xCommandID;
 800524a:	68bb      	ldr	r3, [r7, #8]
 800524c:	613b      	str	r3, [r7, #16]
		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
 800524e:	687b      	ldr	r3, [r7, #4]
 8005250:	617b      	str	r3, [r7, #20]
		xMessage.u.xTimerParameters.pxTimer = xTimer;
 8005252:	68fb      	ldr	r3, [r7, #12]
 8005254:	61bb      	str	r3, [r7, #24]

		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
 8005256:	68bb      	ldr	r3, [r7, #8]
 8005258:	2b05      	cmp	r3, #5
 800525a:	dc18      	bgt.n	800528e <xTimerGenericCommand+0x7a>
		{
			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
 800525c:	f7ff feb2 	bl	8004fc4 <xTaskGetSchedulerState>
 8005260:	4603      	mov	r3, r0
 8005262:	2b02      	cmp	r3, #2
 8005264:	d109      	bne.n	800527a <xTimerGenericCommand+0x66>
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
 8005266:	4b11      	ldr	r3, [pc, #68]	; (80052ac <xTimerGenericCommand+0x98>)
 8005268:	6818      	ldr	r0, [r3, #0]
 800526a:	f107 0110 	add.w	r1, r7, #16
 800526e:	2300      	movs	r3, #0
 8005270:	6b3a      	ldr	r2, [r7, #48]	; 0x30
 8005272:	f7fe fc77 	bl	8003b64 <xQueueGenericSend>
 8005276:	6278      	str	r0, [r7, #36]	; 0x24
 8005278:	e012      	b.n	80052a0 <xTimerGenericCommand+0x8c>
			}
			else
			{
				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
 800527a:	4b0c      	ldr	r3, [pc, #48]	; (80052ac <xTimerGenericCommand+0x98>)
 800527c:	6818      	ldr	r0, [r3, #0]
 800527e:	f107 0110 	add.w	r1, r7, #16
 8005282:	2300      	movs	r3, #0
 8005284:	2200      	movs	r2, #0
 8005286:	f7fe fc6d 	bl	8003b64 <xQueueGenericSend>
 800528a:	6278      	str	r0, [r7, #36]	; 0x24
 800528c:	e008      	b.n	80052a0 <xTimerGenericCommand+0x8c>
			}
		}
		else
		{
			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
 800528e:	4b07      	ldr	r3, [pc, #28]	; (80052ac <xTimerGenericCommand+0x98>)
 8005290:	6818      	ldr	r0, [r3, #0]
 8005292:	f107 0110 	add.w	r1, r7, #16
 8005296:	2300      	movs	r3, #0
 8005298:	683a      	ldr	r2, [r7, #0]
 800529a:	f7fe fd61 	bl	8003d60 <xQueueGenericSendFromISR>
 800529e:	6278      	str	r0, [r7, #36]	; 0x24
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}

	return xReturn;
 80052a0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
}
 80052a2:	4618      	mov	r0, r3
 80052a4:	3728      	adds	r7, #40	; 0x28
 80052a6:	46bd      	mov	sp, r7
 80052a8:	bd80      	pop	{r7, pc}
 80052aa:	bf00      	nop
 80052ac:	20000e40 	.word	0x20000e40

080052b0 <prvProcessExpiredTimer>:
	return pxTimer->pcTimerName;
}
/*-----------------------------------------------------------*/

static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
{
 80052b0:	b580      	push	{r7, lr}
 80052b2:	b088      	sub	sp, #32
 80052b4:	af02      	add	r7, sp, #8
 80052b6:	6078      	str	r0, [r7, #4]
 80052b8:	6039      	str	r1, [r7, #0]
BaseType_t xResult;
Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80052ba:	4b22      	ldr	r3, [pc, #136]	; (8005344 <prvProcessExpiredTimer+0x94>)
 80052bc:	681b      	ldr	r3, [r3, #0]
 80052be:	68db      	ldr	r3, [r3, #12]
 80052c0:	68db      	ldr	r3, [r3, #12]
 80052c2:	617b      	str	r3, [r7, #20]

	/* Remove the timer from the list of active timers.  A check has already
	been performed to ensure the list is not empty. */
	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 80052c4:	697b      	ldr	r3, [r7, #20]
 80052c6:	3304      	adds	r3, #4
 80052c8:	4618      	mov	r0, r3
 80052ca:	f7fe fb1d 	bl	8003908 <uxListRemove>
	traceTIMER_EXPIRED( pxTimer );

	/* If the timer is an auto-reload timer then calculate the next
	expiry time and re-insert the timer in the list of active timers. */
	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 80052ce:	697b      	ldr	r3, [r7, #20]
 80052d0:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 80052d4:	f003 0304 	and.w	r3, r3, #4
 80052d8:	2b00      	cmp	r3, #0
 80052da:	d022      	beq.n	8005322 <prvProcessExpiredTimer+0x72>
	{
		/* The timer is inserted into a list using a time relative to anything
		other than the current time.  It will therefore be inserted into the
		correct list relative to the time this task thinks it is now. */
		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
 80052dc:	697b      	ldr	r3, [r7, #20]
 80052de:	699a      	ldr	r2, [r3, #24]
 80052e0:	687b      	ldr	r3, [r7, #4]
 80052e2:	18d1      	adds	r1, r2, r3
 80052e4:	687b      	ldr	r3, [r7, #4]
 80052e6:	683a      	ldr	r2, [r7, #0]
 80052e8:	6978      	ldr	r0, [r7, #20]
 80052ea:	f000 f8d1 	bl	8005490 <prvInsertTimerInActiveList>
 80052ee:	4603      	mov	r3, r0
 80052f0:	2b00      	cmp	r3, #0
 80052f2:	d01f      	beq.n	8005334 <prvProcessExpiredTimer+0x84>
		{
			/* The timer expired before it was added to the active timer
			list.  Reload it now.  */
			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 80052f4:	2300      	movs	r3, #0
 80052f6:	9300      	str	r3, [sp, #0]
 80052f8:	2300      	movs	r3, #0
 80052fa:	687a      	ldr	r2, [r7, #4]
 80052fc:	2100      	movs	r1, #0
 80052fe:	6978      	ldr	r0, [r7, #20]
 8005300:	f7ff ff88 	bl	8005214 <xTimerGenericCommand>
 8005304:	6138      	str	r0, [r7, #16]
			configASSERT( xResult );
 8005306:	693b      	ldr	r3, [r7, #16]
 8005308:	2b00      	cmp	r3, #0
 800530a:	d113      	bne.n	8005334 <prvProcessExpiredTimer+0x84>
	__asm volatile
 800530c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005310:	f383 8811 	msr	BASEPRI, r3
 8005314:	f3bf 8f6f 	isb	sy
 8005318:	f3bf 8f4f 	dsb	sy
 800531c:	60fb      	str	r3, [r7, #12]
}
 800531e:	bf00      	nop
 8005320:	e7fe      	b.n	8005320 <prvProcessExpiredTimer+0x70>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	else
	{
		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8005322:	697b      	ldr	r3, [r7, #20]
 8005324:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005328:	f023 0301 	bic.w	r3, r3, #1
 800532c:	b2da      	uxtb	r2, r3
 800532e:	697b      	ldr	r3, [r7, #20]
 8005330:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
		mtCOVERAGE_TEST_MARKER();
	}

	/* Call the timer callback. */
	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 8005334:	697b      	ldr	r3, [r7, #20]
 8005336:	6a1b      	ldr	r3, [r3, #32]
 8005338:	6978      	ldr	r0, [r7, #20]
 800533a:	4798      	blx	r3
}
 800533c:	bf00      	nop
 800533e:	3718      	adds	r7, #24
 8005340:	46bd      	mov	sp, r7
 8005342:	bd80      	pop	{r7, pc}
 8005344:	20000e38 	.word	0x20000e38

08005348 <prvTimerTask>:
/*-----------------------------------------------------------*/

static portTASK_FUNCTION( prvTimerTask, pvParameters )
{
 8005348:	b580      	push	{r7, lr}
 800534a:	b084      	sub	sp, #16
 800534c:	af00      	add	r7, sp, #0
 800534e:	6078      	str	r0, [r7, #4]

	for( ;; )
	{
		/* Query the timers list to see if it contains any timers, and if so,
		obtain the time at which the next timer will expire. */
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 8005350:	f107 0308 	add.w	r3, r7, #8
 8005354:	4618      	mov	r0, r3
 8005356:	f000 f857 	bl	8005408 <prvGetNextExpireTime>
 800535a:	60f8      	str	r0, [r7, #12]

		/* If a timer has expired, process it.  Otherwise, block this task
		until either a timer does expire, or a command is received. */
		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
 800535c:	68bb      	ldr	r3, [r7, #8]
 800535e:	4619      	mov	r1, r3
 8005360:	68f8      	ldr	r0, [r7, #12]
 8005362:	f000 f803 	bl	800536c <prvProcessTimerOrBlockTask>

		/* Empty the command queue. */
		prvProcessReceivedCommands();
 8005366:	f000 f8d5 	bl	8005514 <prvProcessReceivedCommands>
		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
 800536a:	e7f1      	b.n	8005350 <prvTimerTask+0x8>

0800536c <prvProcessTimerOrBlockTask>:
	}
}
/*-----------------------------------------------------------*/

static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
{
 800536c:	b580      	push	{r7, lr}
 800536e:	b084      	sub	sp, #16
 8005370:	af00      	add	r7, sp, #0
 8005372:	6078      	str	r0, [r7, #4]
 8005374:	6039      	str	r1, [r7, #0]
TickType_t xTimeNow;
BaseType_t xTimerListsWereSwitched;

	vTaskSuspendAll();
 8005376:	f7ff fa39 	bl	80047ec <vTaskSuspendAll>
		/* Obtain the time now to make an assessment as to whether the timer
		has expired or not.  If obtaining the time causes the lists to switch
		then don't process this timer as any timers that remained in the list
		when the lists were switched will have been processed within the
		prvSampleTimeNow() function. */
		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 800537a:	f107 0308 	add.w	r3, r7, #8
 800537e:	4618      	mov	r0, r3
 8005380:	f000 f866 	bl	8005450 <prvSampleTimeNow>
 8005384:	60f8      	str	r0, [r7, #12]
		if( xTimerListsWereSwitched == pdFALSE )
 8005386:	68bb      	ldr	r3, [r7, #8]
 8005388:	2b00      	cmp	r3, #0
 800538a:	d130      	bne.n	80053ee <prvProcessTimerOrBlockTask+0x82>
		{
			/* The tick count has not overflowed, has the timer expired? */
			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
 800538c:	683b      	ldr	r3, [r7, #0]
 800538e:	2b00      	cmp	r3, #0
 8005390:	d10a      	bne.n	80053a8 <prvProcessTimerOrBlockTask+0x3c>
 8005392:	687a      	ldr	r2, [r7, #4]
 8005394:	68fb      	ldr	r3, [r7, #12]
 8005396:	429a      	cmp	r2, r3
 8005398:	d806      	bhi.n	80053a8 <prvProcessTimerOrBlockTask+0x3c>
			{
				( void ) xTaskResumeAll();
 800539a:	f7ff fa35 	bl	8004808 <xTaskResumeAll>
				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
 800539e:	68f9      	ldr	r1, [r7, #12]
 80053a0:	6878      	ldr	r0, [r7, #4]
 80053a2:	f7ff ff85 	bl	80052b0 <prvProcessExpiredTimer>
		else
		{
			( void ) xTaskResumeAll();
		}
	}
}
 80053a6:	e024      	b.n	80053f2 <prvProcessTimerOrBlockTask+0x86>
				if( xListWasEmpty != pdFALSE )
 80053a8:	683b      	ldr	r3, [r7, #0]
 80053aa:	2b00      	cmp	r3, #0
 80053ac:	d008      	beq.n	80053c0 <prvProcessTimerOrBlockTask+0x54>
					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
 80053ae:	4b13      	ldr	r3, [pc, #76]	; (80053fc <prvProcessTimerOrBlockTask+0x90>)
 80053b0:	681b      	ldr	r3, [r3, #0]
 80053b2:	681b      	ldr	r3, [r3, #0]
 80053b4:	2b00      	cmp	r3, #0
 80053b6:	d101      	bne.n	80053bc <prvProcessTimerOrBlockTask+0x50>
 80053b8:	2301      	movs	r3, #1
 80053ba:	e000      	b.n	80053be <prvProcessTimerOrBlockTask+0x52>
 80053bc:	2300      	movs	r3, #0
 80053be:	603b      	str	r3, [r7, #0]
				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
 80053c0:	4b0f      	ldr	r3, [pc, #60]	; (8005400 <prvProcessTimerOrBlockTask+0x94>)
 80053c2:	6818      	ldr	r0, [r3, #0]
 80053c4:	687a      	ldr	r2, [r7, #4]
 80053c6:	68fb      	ldr	r3, [r7, #12]
 80053c8:	1ad3      	subs	r3, r2, r3
 80053ca:	683a      	ldr	r2, [r7, #0]
 80053cc:	4619      	mov	r1, r3
 80053ce:	f7fe ff7d 	bl	80042cc <vQueueWaitForMessageRestricted>
				if( xTaskResumeAll() == pdFALSE )
 80053d2:	f7ff fa19 	bl	8004808 <xTaskResumeAll>
 80053d6:	4603      	mov	r3, r0
 80053d8:	2b00      	cmp	r3, #0
 80053da:	d10a      	bne.n	80053f2 <prvProcessTimerOrBlockTask+0x86>
					portYIELD_WITHIN_API();
 80053dc:	4b09      	ldr	r3, [pc, #36]	; (8005404 <prvProcessTimerOrBlockTask+0x98>)
 80053de:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 80053e2:	601a      	str	r2, [r3, #0]
 80053e4:	f3bf 8f4f 	dsb	sy
 80053e8:	f3bf 8f6f 	isb	sy
}
 80053ec:	e001      	b.n	80053f2 <prvProcessTimerOrBlockTask+0x86>
			( void ) xTaskResumeAll();
 80053ee:	f7ff fa0b 	bl	8004808 <xTaskResumeAll>
}
 80053f2:	bf00      	nop
 80053f4:	3710      	adds	r7, #16
 80053f6:	46bd      	mov	sp, r7
 80053f8:	bd80      	pop	{r7, pc}
 80053fa:	bf00      	nop
 80053fc:	20000e3c 	.word	0x20000e3c
 8005400:	20000e40 	.word	0x20000e40
 8005404:	e000ed04 	.word	0xe000ed04

08005408 <prvGetNextExpireTime>:
/*-----------------------------------------------------------*/

static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
{
 8005408:	b480      	push	{r7}
 800540a:	b085      	sub	sp, #20
 800540c:	af00      	add	r7, sp, #0
 800540e:	6078      	str	r0, [r7, #4]
	the timer with the nearest expiry time will expire.  If there are no
	active timers then just set the next expire time to 0.  That will cause
	this task to unblock when the tick count overflows, at which point the
	timer lists will be switched and the next expiry time can be
	re-assessed.  */
	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
 8005410:	4b0e      	ldr	r3, [pc, #56]	; (800544c <prvGetNextExpireTime+0x44>)
 8005412:	681b      	ldr	r3, [r3, #0]
 8005414:	681b      	ldr	r3, [r3, #0]
 8005416:	2b00      	cmp	r3, #0
 8005418:	d101      	bne.n	800541e <prvGetNextExpireTime+0x16>
 800541a:	2201      	movs	r2, #1
 800541c:	e000      	b.n	8005420 <prvGetNextExpireTime+0x18>
 800541e:	2200      	movs	r2, #0
 8005420:	687b      	ldr	r3, [r7, #4]
 8005422:	601a      	str	r2, [r3, #0]
	if( *pxListWasEmpty == pdFALSE )
 8005424:	687b      	ldr	r3, [r7, #4]
 8005426:	681b      	ldr	r3, [r3, #0]
 8005428:	2b00      	cmp	r3, #0
 800542a:	d105      	bne.n	8005438 <prvGetNextExpireTime+0x30>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 800542c:	4b07      	ldr	r3, [pc, #28]	; (800544c <prvGetNextExpireTime+0x44>)
 800542e:	681b      	ldr	r3, [r3, #0]
 8005430:	68db      	ldr	r3, [r3, #12]
 8005432:	681b      	ldr	r3, [r3, #0]
 8005434:	60fb      	str	r3, [r7, #12]
 8005436:	e001      	b.n	800543c <prvGetNextExpireTime+0x34>
	}
	else
	{
		/* Ensure the task unblocks when the tick count rolls over. */
		xNextExpireTime = ( TickType_t ) 0U;
 8005438:	2300      	movs	r3, #0
 800543a:	60fb      	str	r3, [r7, #12]
	}

	return xNextExpireTime;
 800543c:	68fb      	ldr	r3, [r7, #12]
}
 800543e:	4618      	mov	r0, r3
 8005440:	3714      	adds	r7, #20
 8005442:	46bd      	mov	sp, r7
 8005444:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005448:	4770      	bx	lr
 800544a:	bf00      	nop
 800544c:	20000e38 	.word	0x20000e38

08005450 <prvSampleTimeNow>:
/*-----------------------------------------------------------*/

static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
{
 8005450:	b580      	push	{r7, lr}
 8005452:	b084      	sub	sp, #16
 8005454:	af00      	add	r7, sp, #0
 8005456:	6078      	str	r0, [r7, #4]
TickType_t xTimeNow;
PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */

	xTimeNow = xTaskGetTickCount();
 8005458:	f7ff fa74 	bl	8004944 <xTaskGetTickCount>
 800545c:	60f8      	str	r0, [r7, #12]

	if( xTimeNow < xLastTime )
 800545e:	4b0b      	ldr	r3, [pc, #44]	; (800548c <prvSampleTimeNow+0x3c>)
 8005460:	681b      	ldr	r3, [r3, #0]
 8005462:	68fa      	ldr	r2, [r7, #12]
 8005464:	429a      	cmp	r2, r3
 8005466:	d205      	bcs.n	8005474 <prvSampleTimeNow+0x24>
	{
		prvSwitchTimerLists();
 8005468:	f000 f936 	bl	80056d8 <prvSwitchTimerLists>
		*pxTimerListsWereSwitched = pdTRUE;
 800546c:	687b      	ldr	r3, [r7, #4]
 800546e:	2201      	movs	r2, #1
 8005470:	601a      	str	r2, [r3, #0]
 8005472:	e002      	b.n	800547a <prvSampleTimeNow+0x2a>
	}
	else
	{
		*pxTimerListsWereSwitched = pdFALSE;
 8005474:	687b      	ldr	r3, [r7, #4]
 8005476:	2200      	movs	r2, #0
 8005478:	601a      	str	r2, [r3, #0]
	}

	xLastTime = xTimeNow;
 800547a:	4a04      	ldr	r2, [pc, #16]	; (800548c <prvSampleTimeNow+0x3c>)
 800547c:	68fb      	ldr	r3, [r7, #12]
 800547e:	6013      	str	r3, [r2, #0]

	return xTimeNow;
 8005480:	68fb      	ldr	r3, [r7, #12]
}
 8005482:	4618      	mov	r0, r3
 8005484:	3710      	adds	r7, #16
 8005486:	46bd      	mov	sp, r7
 8005488:	bd80      	pop	{r7, pc}
 800548a:	bf00      	nop
 800548c:	20000e48 	.word	0x20000e48

08005490 <prvInsertTimerInActiveList>:
/*-----------------------------------------------------------*/

static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
{
 8005490:	b580      	push	{r7, lr}
 8005492:	b086      	sub	sp, #24
 8005494:	af00      	add	r7, sp, #0
 8005496:	60f8      	str	r0, [r7, #12]
 8005498:	60b9      	str	r1, [r7, #8]
 800549a:	607a      	str	r2, [r7, #4]
 800549c:	603b      	str	r3, [r7, #0]
BaseType_t xProcessTimerNow = pdFALSE;
 800549e:	2300      	movs	r3, #0
 80054a0:	617b      	str	r3, [r7, #20]

	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
 80054a2:	68fb      	ldr	r3, [r7, #12]
 80054a4:	68ba      	ldr	r2, [r7, #8]
 80054a6:	605a      	str	r2, [r3, #4]
	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 80054a8:	68fb      	ldr	r3, [r7, #12]
 80054aa:	68fa      	ldr	r2, [r7, #12]
 80054ac:	611a      	str	r2, [r3, #16]

	if( xNextExpiryTime <= xTimeNow )
 80054ae:	68ba      	ldr	r2, [r7, #8]
 80054b0:	687b      	ldr	r3, [r7, #4]
 80054b2:	429a      	cmp	r2, r3
 80054b4:	d812      	bhi.n	80054dc <prvInsertTimerInActiveList+0x4c>
	{
		/* Has the expiry time elapsed between the command to start/reset a
		timer was issued, and the time the command was processed? */
		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
 80054b6:	687a      	ldr	r2, [r7, #4]
 80054b8:	683b      	ldr	r3, [r7, #0]
 80054ba:	1ad2      	subs	r2, r2, r3
 80054bc:	68fb      	ldr	r3, [r7, #12]
 80054be:	699b      	ldr	r3, [r3, #24]
 80054c0:	429a      	cmp	r2, r3
 80054c2:	d302      	bcc.n	80054ca <prvInsertTimerInActiveList+0x3a>
		{
			/* The time between a command being issued and the command being
			processed actually exceeds the timers period.  */
			xProcessTimerNow = pdTRUE;
 80054c4:	2301      	movs	r3, #1
 80054c6:	617b      	str	r3, [r7, #20]
 80054c8:	e01b      	b.n	8005502 <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
 80054ca:	4b10      	ldr	r3, [pc, #64]	; (800550c <prvInsertTimerInActiveList+0x7c>)
 80054cc:	681a      	ldr	r2, [r3, #0]
 80054ce:	68fb      	ldr	r3, [r7, #12]
 80054d0:	3304      	adds	r3, #4
 80054d2:	4619      	mov	r1, r3
 80054d4:	4610      	mov	r0, r2
 80054d6:	f7fe f9de 	bl	8003896 <vListInsert>
 80054da:	e012      	b.n	8005502 <prvInsertTimerInActiveList+0x72>
		}
	}
	else
	{
		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
 80054dc:	687a      	ldr	r2, [r7, #4]
 80054de:	683b      	ldr	r3, [r7, #0]
 80054e0:	429a      	cmp	r2, r3
 80054e2:	d206      	bcs.n	80054f2 <prvInsertTimerInActiveList+0x62>
 80054e4:	68ba      	ldr	r2, [r7, #8]
 80054e6:	683b      	ldr	r3, [r7, #0]
 80054e8:	429a      	cmp	r2, r3
 80054ea:	d302      	bcc.n	80054f2 <prvInsertTimerInActiveList+0x62>
		{
			/* If, since the command was issued, the tick count has overflowed
			but the expiry time has not, then the timer must have already passed
			its expiry time and should be processed immediately. */
			xProcessTimerNow = pdTRUE;
 80054ec:	2301      	movs	r3, #1
 80054ee:	617b      	str	r3, [r7, #20]
 80054f0:	e007      	b.n	8005502 <prvInsertTimerInActiveList+0x72>
		}
		else
		{
			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 80054f2:	4b07      	ldr	r3, [pc, #28]	; (8005510 <prvInsertTimerInActiveList+0x80>)
 80054f4:	681a      	ldr	r2, [r3, #0]
 80054f6:	68fb      	ldr	r3, [r7, #12]
 80054f8:	3304      	adds	r3, #4
 80054fa:	4619      	mov	r1, r3
 80054fc:	4610      	mov	r0, r2
 80054fe:	f7fe f9ca 	bl	8003896 <vListInsert>
		}
	}

	return xProcessTimerNow;
 8005502:	697b      	ldr	r3, [r7, #20]
}
 8005504:	4618      	mov	r0, r3
 8005506:	3718      	adds	r7, #24
 8005508:	46bd      	mov	sp, r7
 800550a:	bd80      	pop	{r7, pc}
 800550c:	20000e3c 	.word	0x20000e3c
 8005510:	20000e38 	.word	0x20000e38

08005514 <prvProcessReceivedCommands>:
/*-----------------------------------------------------------*/

static void	prvProcessReceivedCommands( void )
{
 8005514:	b580      	push	{r7, lr}
 8005516:	b08e      	sub	sp, #56	; 0x38
 8005518:	af02      	add	r7, sp, #8
DaemonTaskMessage_t xMessage;
Timer_t *pxTimer;
BaseType_t xTimerListsWereSwitched, xResult;
TickType_t xTimeNow;

	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 800551a:	e0ca      	b.n	80056b2 <prvProcessReceivedCommands+0x19e>
	{
		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
		{
			/* Negative commands are pended function calls rather than timer
			commands. */
			if( xMessage.xMessageID < ( BaseType_t ) 0 )
 800551c:	687b      	ldr	r3, [r7, #4]
 800551e:	2b00      	cmp	r3, #0
 8005520:	da18      	bge.n	8005554 <prvProcessReceivedCommands+0x40>
			{
				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
 8005522:	1d3b      	adds	r3, r7, #4
 8005524:	3304      	adds	r3, #4
 8005526:	62fb      	str	r3, [r7, #44]	; 0x2c

				/* The timer uses the xCallbackParameters member to request a
				callback be executed.  Check the callback is not NULL. */
				configASSERT( pxCallback );
 8005528:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 800552a:	2b00      	cmp	r3, #0
 800552c:	d10a      	bne.n	8005544 <prvProcessReceivedCommands+0x30>
	__asm volatile
 800552e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005532:	f383 8811 	msr	BASEPRI, r3
 8005536:	f3bf 8f6f 	isb	sy
 800553a:	f3bf 8f4f 	dsb	sy
 800553e:	61fb      	str	r3, [r7, #28]
}
 8005540:	bf00      	nop
 8005542:	e7fe      	b.n	8005542 <prvProcessReceivedCommands+0x2e>

				/* Call the function. */
				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
 8005544:	6afb      	ldr	r3, [r7, #44]	; 0x2c
 8005546:	681b      	ldr	r3, [r3, #0]
 8005548:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 800554a:	6850      	ldr	r0, [r2, #4]
 800554c:	6afa      	ldr	r2, [r7, #44]	; 0x2c
 800554e:	6892      	ldr	r2, [r2, #8]
 8005550:	4611      	mov	r1, r2
 8005552:	4798      	blx	r3
		}
		#endif /* INCLUDE_xTimerPendFunctionCall */

		/* Commands that are positive are timer commands rather than pended
		function calls. */
		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
 8005554:	687b      	ldr	r3, [r7, #4]
 8005556:	2b00      	cmp	r3, #0
 8005558:	f2c0 80ab 	blt.w	80056b2 <prvProcessReceivedCommands+0x19e>
		{
			/* The messages uses the xTimerParameters member to work on a
			software timer. */
			pxTimer = xMessage.u.xTimerParameters.pxTimer;
 800555c:	68fb      	ldr	r3, [r7, #12]
 800555e:	62bb      	str	r3, [r7, #40]	; 0x28

			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
 8005560:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005562:	695b      	ldr	r3, [r3, #20]
 8005564:	2b00      	cmp	r3, #0
 8005566:	d004      	beq.n	8005572 <prvProcessReceivedCommands+0x5e>
			{
				/* The timer is in a list, remove it. */
				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 8005568:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800556a:	3304      	adds	r3, #4
 800556c:	4618      	mov	r0, r3
 800556e:	f7fe f9cb 	bl	8003908 <uxListRemove>
			it must be present in the function call.  prvSampleTimeNow() must be
			called after the message is received from xTimerQueue so there is no
			possibility of a higher priority task adding a message to the message
			queue with a time that is ahead of the timer daemon task (because it
			pre-empted the timer daemon task after the xTimeNow value was set). */
			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
 8005572:	463b      	mov	r3, r7
 8005574:	4618      	mov	r0, r3
 8005576:	f7ff ff6b 	bl	8005450 <prvSampleTimeNow>
 800557a:	6278      	str	r0, [r7, #36]	; 0x24

			switch( xMessage.xMessageID )
 800557c:	687b      	ldr	r3, [r7, #4]
 800557e:	2b09      	cmp	r3, #9
 8005580:	f200 8096 	bhi.w	80056b0 <prvProcessReceivedCommands+0x19c>
 8005584:	a201      	add	r2, pc, #4	; (adr r2, 800558c <prvProcessReceivedCommands+0x78>)
 8005586:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800558a:	bf00      	nop
 800558c:	080055b5 	.word	0x080055b5
 8005590:	080055b5 	.word	0x080055b5
 8005594:	080055b5 	.word	0x080055b5
 8005598:	08005629 	.word	0x08005629
 800559c:	0800563d 	.word	0x0800563d
 80055a0:	08005687 	.word	0x08005687
 80055a4:	080055b5 	.word	0x080055b5
 80055a8:	080055b5 	.word	0x080055b5
 80055ac:	08005629 	.word	0x08005629
 80055b0:	0800563d 	.word	0x0800563d
				case tmrCOMMAND_START_FROM_ISR :
				case tmrCOMMAND_RESET :
				case tmrCOMMAND_RESET_FROM_ISR :
				case tmrCOMMAND_START_DONT_TRACE :
					/* Start or restart a timer. */
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 80055b4:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80055b6:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 80055ba:	f043 0301 	orr.w	r3, r3, #1
 80055be:	b2da      	uxtb	r2, r3
 80055c0:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80055c2:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
 80055c6:	68ba      	ldr	r2, [r7, #8]
 80055c8:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80055ca:	699b      	ldr	r3, [r3, #24]
 80055cc:	18d1      	adds	r1, r2, r3
 80055ce:	68bb      	ldr	r3, [r7, #8]
 80055d0:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 80055d2:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 80055d4:	f7ff ff5c 	bl	8005490 <prvInsertTimerInActiveList>
 80055d8:	4603      	mov	r3, r0
 80055da:	2b00      	cmp	r3, #0
 80055dc:	d069      	beq.n	80056b2 <prvProcessReceivedCommands+0x19e>
					{
						/* The timer expired before it was added to the active
						timer list.  Process it now. */
						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 80055de:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80055e0:	6a1b      	ldr	r3, [r3, #32]
 80055e2:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 80055e4:	4798      	blx	r3
						traceTIMER_EXPIRED( pxTimer );

						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 80055e6:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80055e8:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 80055ec:	f003 0304 	and.w	r3, r3, #4
 80055f0:	2b00      	cmp	r3, #0
 80055f2:	d05e      	beq.n	80056b2 <prvProcessReceivedCommands+0x19e>
						{
							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
 80055f4:	68ba      	ldr	r2, [r7, #8]
 80055f6:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80055f8:	699b      	ldr	r3, [r3, #24]
 80055fa:	441a      	add	r2, r3
 80055fc:	2300      	movs	r3, #0
 80055fe:	9300      	str	r3, [sp, #0]
 8005600:	2300      	movs	r3, #0
 8005602:	2100      	movs	r1, #0
 8005604:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8005606:	f7ff fe05 	bl	8005214 <xTimerGenericCommand>
 800560a:	6238      	str	r0, [r7, #32]
							configASSERT( xResult );
 800560c:	6a3b      	ldr	r3, [r7, #32]
 800560e:	2b00      	cmp	r3, #0
 8005610:	d14f      	bne.n	80056b2 <prvProcessReceivedCommands+0x19e>
	__asm volatile
 8005612:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005616:	f383 8811 	msr	BASEPRI, r3
 800561a:	f3bf 8f6f 	isb	sy
 800561e:	f3bf 8f4f 	dsb	sy
 8005622:	61bb      	str	r3, [r7, #24]
}
 8005624:	bf00      	nop
 8005626:	e7fe      	b.n	8005626 <prvProcessReceivedCommands+0x112>
					break;

				case tmrCOMMAND_STOP :
				case tmrCOMMAND_STOP_FROM_ISR :
					/* The timer has already been removed from the active list. */
					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 8005628:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800562a:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 800562e:	f023 0301 	bic.w	r3, r3, #1
 8005632:	b2da      	uxtb	r2, r3
 8005634:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005636:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
					break;
 800563a:	e03a      	b.n	80056b2 <prvProcessReceivedCommands+0x19e>

				case tmrCOMMAND_CHANGE_PERIOD :
				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
 800563c:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800563e:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 8005642:	f043 0301 	orr.w	r3, r3, #1
 8005646:	b2da      	uxtb	r2, r3
 8005648:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800564a:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
 800564e:	68ba      	ldr	r2, [r7, #8]
 8005650:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005652:	619a      	str	r2, [r3, #24]
					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
 8005654:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005656:	699b      	ldr	r3, [r3, #24]
 8005658:	2b00      	cmp	r3, #0
 800565a:	d10a      	bne.n	8005672 <prvProcessReceivedCommands+0x15e>
	__asm volatile
 800565c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005660:	f383 8811 	msr	BASEPRI, r3
 8005664:	f3bf 8f6f 	isb	sy
 8005668:	f3bf 8f4f 	dsb	sy
 800566c:	617b      	str	r3, [r7, #20]
}
 800566e:	bf00      	nop
 8005670:	e7fe      	b.n	8005670 <prvProcessReceivedCommands+0x15c>
					be longer or shorter than the old one.  The command time is
					therefore set to the current time, and as the period cannot
					be zero the next expiry time can only be in the future,
					meaning (unlike for the xTimerStart() case above) there is
					no fail case that needs to be handled here. */
					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
 8005672:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005674:	699a      	ldr	r2, [r3, #24]
 8005676:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005678:	18d1      	adds	r1, r2, r3
 800567a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 800567c:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 800567e:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8005680:	f7ff ff06 	bl	8005490 <prvInsertTimerInActiveList>
					break;
 8005684:	e015      	b.n	80056b2 <prvProcessReceivedCommands+0x19e>
					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
					{
						/* The timer has already been removed from the active list,
						just free up the memory if the memory was dynamically
						allocated. */
						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
 8005686:	6abb      	ldr	r3, [r7, #40]	; 0x28
 8005688:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 800568c:	f003 0302 	and.w	r3, r3, #2
 8005690:	2b00      	cmp	r3, #0
 8005692:	d103      	bne.n	800569c <prvProcessReceivedCommands+0x188>
						{
							vPortFree( pxTimer );
 8005694:	6ab8      	ldr	r0, [r7, #40]	; 0x28
 8005696:	f000 fbdb 	bl	8005e50 <vPortFree>
 800569a:	e00a      	b.n	80056b2 <prvProcessReceivedCommands+0x19e>
						}
						else
						{
							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
 800569c:	6abb      	ldr	r3, [r7, #40]	; 0x28
 800569e:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 80056a2:	f023 0301 	bic.w	r3, r3, #1
 80056a6:	b2da      	uxtb	r2, r3
 80056a8:	6abb      	ldr	r3, [r7, #40]	; 0x28
 80056aa:	f883 2028 	strb.w	r2, [r3, #40]	; 0x28
						no need to free the memory - just mark the timer as
						"not active". */
						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
					}
					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
					break;
 80056ae:	e000      	b.n	80056b2 <prvProcessReceivedCommands+0x19e>

				default	:
					/* Don't expect to get here. */
					break;
 80056b0:	bf00      	nop
	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
 80056b2:	4b08      	ldr	r3, [pc, #32]	; (80056d4 <prvProcessReceivedCommands+0x1c0>)
 80056b4:	681b      	ldr	r3, [r3, #0]
 80056b6:	1d39      	adds	r1, r7, #4
 80056b8:	2200      	movs	r2, #0
 80056ba:	4618      	mov	r0, r3
 80056bc:	f7fe fbec 	bl	8003e98 <xQueueReceive>
 80056c0:	4603      	mov	r3, r0
 80056c2:	2b00      	cmp	r3, #0
 80056c4:	f47f af2a 	bne.w	800551c <prvProcessReceivedCommands+0x8>
			}
		}
	}
}
 80056c8:	bf00      	nop
 80056ca:	bf00      	nop
 80056cc:	3730      	adds	r7, #48	; 0x30
 80056ce:	46bd      	mov	sp, r7
 80056d0:	bd80      	pop	{r7, pc}
 80056d2:	bf00      	nop
 80056d4:	20000e40 	.word	0x20000e40

080056d8 <prvSwitchTimerLists>:
/*-----------------------------------------------------------*/

static void prvSwitchTimerLists( void )
{
 80056d8:	b580      	push	{r7, lr}
 80056da:	b088      	sub	sp, #32
 80056dc:	af02      	add	r7, sp, #8

	/* The tick count has overflowed.  The timer lists must be switched.
	If there are any timers still referenced from the current timer list
	then they must have expired and should be processed before the lists
	are switched. */
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 80056de:	e048      	b.n	8005772 <prvSwitchTimerLists+0x9a>
	{
		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
 80056e0:	4b2d      	ldr	r3, [pc, #180]	; (8005798 <prvSwitchTimerLists+0xc0>)
 80056e2:	681b      	ldr	r3, [r3, #0]
 80056e4:	68db      	ldr	r3, [r3, #12]
 80056e6:	681b      	ldr	r3, [r3, #0]
 80056e8:	613b      	str	r3, [r7, #16]

		/* Remove the timer from the list. */
		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
 80056ea:	4b2b      	ldr	r3, [pc, #172]	; (8005798 <prvSwitchTimerLists+0xc0>)
 80056ec:	681b      	ldr	r3, [r3, #0]
 80056ee:	68db      	ldr	r3, [r3, #12]
 80056f0:	68db      	ldr	r3, [r3, #12]
 80056f2:	60fb      	str	r3, [r7, #12]
		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
 80056f4:	68fb      	ldr	r3, [r7, #12]
 80056f6:	3304      	adds	r3, #4
 80056f8:	4618      	mov	r0, r3
 80056fa:	f7fe f905 	bl	8003908 <uxListRemove>
		traceTIMER_EXPIRED( pxTimer );

		/* Execute its callback, then send a command to restart the timer if
		it is an auto-reload timer.  It cannot be restarted here as the lists
		have not yet been switched. */
		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
 80056fe:	68fb      	ldr	r3, [r7, #12]
 8005700:	6a1b      	ldr	r3, [r3, #32]
 8005702:	68f8      	ldr	r0, [r7, #12]
 8005704:	4798      	blx	r3

		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
 8005706:	68fb      	ldr	r3, [r7, #12]
 8005708:	f893 3028 	ldrb.w	r3, [r3, #40]	; 0x28
 800570c:	f003 0304 	and.w	r3, r3, #4
 8005710:	2b00      	cmp	r3, #0
 8005712:	d02e      	beq.n	8005772 <prvSwitchTimerLists+0x9a>
			the timer going into the same timer list then it has already expired
			and the timer should be re-inserted into the current list so it is
			processed again within this loop.  Otherwise a command should be sent
			to restart the timer to ensure it is only inserted into a list after
			the lists have been swapped. */
			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
 8005714:	68fb      	ldr	r3, [r7, #12]
 8005716:	699b      	ldr	r3, [r3, #24]
 8005718:	693a      	ldr	r2, [r7, #16]
 800571a:	4413      	add	r3, r2
 800571c:	60bb      	str	r3, [r7, #8]
			if( xReloadTime > xNextExpireTime )
 800571e:	68ba      	ldr	r2, [r7, #8]
 8005720:	693b      	ldr	r3, [r7, #16]
 8005722:	429a      	cmp	r2, r3
 8005724:	d90e      	bls.n	8005744 <prvSwitchTimerLists+0x6c>
			{
				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
 8005726:	68fb      	ldr	r3, [r7, #12]
 8005728:	68ba      	ldr	r2, [r7, #8]
 800572a:	605a      	str	r2, [r3, #4]
				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
 800572c:	68fb      	ldr	r3, [r7, #12]
 800572e:	68fa      	ldr	r2, [r7, #12]
 8005730:	611a      	str	r2, [r3, #16]
				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
 8005732:	4b19      	ldr	r3, [pc, #100]	; (8005798 <prvSwitchTimerLists+0xc0>)
 8005734:	681a      	ldr	r2, [r3, #0]
 8005736:	68fb      	ldr	r3, [r7, #12]
 8005738:	3304      	adds	r3, #4
 800573a:	4619      	mov	r1, r3
 800573c:	4610      	mov	r0, r2
 800573e:	f7fe f8aa 	bl	8003896 <vListInsert>
 8005742:	e016      	b.n	8005772 <prvSwitchTimerLists+0x9a>
			}
			else
			{
				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
 8005744:	2300      	movs	r3, #0
 8005746:	9300      	str	r3, [sp, #0]
 8005748:	2300      	movs	r3, #0
 800574a:	693a      	ldr	r2, [r7, #16]
 800574c:	2100      	movs	r1, #0
 800574e:	68f8      	ldr	r0, [r7, #12]
 8005750:	f7ff fd60 	bl	8005214 <xTimerGenericCommand>
 8005754:	6078      	str	r0, [r7, #4]
				configASSERT( xResult );
 8005756:	687b      	ldr	r3, [r7, #4]
 8005758:	2b00      	cmp	r3, #0
 800575a:	d10a      	bne.n	8005772 <prvSwitchTimerLists+0x9a>
	__asm volatile
 800575c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005760:	f383 8811 	msr	BASEPRI, r3
 8005764:	f3bf 8f6f 	isb	sy
 8005768:	f3bf 8f4f 	dsb	sy
 800576c:	603b      	str	r3, [r7, #0]
}
 800576e:	bf00      	nop
 8005770:	e7fe      	b.n	8005770 <prvSwitchTimerLists+0x98>
	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
 8005772:	4b09      	ldr	r3, [pc, #36]	; (8005798 <prvSwitchTimerLists+0xc0>)
 8005774:	681b      	ldr	r3, [r3, #0]
 8005776:	681b      	ldr	r3, [r3, #0]
 8005778:	2b00      	cmp	r3, #0
 800577a:	d1b1      	bne.n	80056e0 <prvSwitchTimerLists+0x8>
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}

	pxTemp = pxCurrentTimerList;
 800577c:	4b06      	ldr	r3, [pc, #24]	; (8005798 <prvSwitchTimerLists+0xc0>)
 800577e:	681b      	ldr	r3, [r3, #0]
 8005780:	617b      	str	r3, [r7, #20]
	pxCurrentTimerList = pxOverflowTimerList;
 8005782:	4b06      	ldr	r3, [pc, #24]	; (800579c <prvSwitchTimerLists+0xc4>)
 8005784:	681b      	ldr	r3, [r3, #0]
 8005786:	4a04      	ldr	r2, [pc, #16]	; (8005798 <prvSwitchTimerLists+0xc0>)
 8005788:	6013      	str	r3, [r2, #0]
	pxOverflowTimerList = pxTemp;
 800578a:	4a04      	ldr	r2, [pc, #16]	; (800579c <prvSwitchTimerLists+0xc4>)
 800578c:	697b      	ldr	r3, [r7, #20]
 800578e:	6013      	str	r3, [r2, #0]
}
 8005790:	bf00      	nop
 8005792:	3718      	adds	r7, #24
 8005794:	46bd      	mov	sp, r7
 8005796:	bd80      	pop	{r7, pc}
 8005798:	20000e38 	.word	0x20000e38
 800579c:	20000e3c 	.word	0x20000e3c

080057a0 <prvCheckForValidListAndQueue>:
/*-----------------------------------------------------------*/

static void prvCheckForValidListAndQueue( void )
{
 80057a0:	b580      	push	{r7, lr}
 80057a2:	b082      	sub	sp, #8
 80057a4:	af02      	add	r7, sp, #8
	/* Check that the list from which active timers are referenced, and the
	queue used to communicate with the timer service, have been
	initialised. */
	taskENTER_CRITICAL();
 80057a6:	f000 f965 	bl	8005a74 <vPortEnterCritical>
	{
		if( xTimerQueue == NULL )
 80057aa:	4b15      	ldr	r3, [pc, #84]	; (8005800 <prvCheckForValidListAndQueue+0x60>)
 80057ac:	681b      	ldr	r3, [r3, #0]
 80057ae:	2b00      	cmp	r3, #0
 80057b0:	d120      	bne.n	80057f4 <prvCheckForValidListAndQueue+0x54>
		{
			vListInitialise( &xActiveTimerList1 );
 80057b2:	4814      	ldr	r0, [pc, #80]	; (8005804 <prvCheckForValidListAndQueue+0x64>)
 80057b4:	f7fe f81e 	bl	80037f4 <vListInitialise>
			vListInitialise( &xActiveTimerList2 );
 80057b8:	4813      	ldr	r0, [pc, #76]	; (8005808 <prvCheckForValidListAndQueue+0x68>)
 80057ba:	f7fe f81b 	bl	80037f4 <vListInitialise>
			pxCurrentTimerList = &xActiveTimerList1;
 80057be:	4b13      	ldr	r3, [pc, #76]	; (800580c <prvCheckForValidListAndQueue+0x6c>)
 80057c0:	4a10      	ldr	r2, [pc, #64]	; (8005804 <prvCheckForValidListAndQueue+0x64>)
 80057c2:	601a      	str	r2, [r3, #0]
			pxOverflowTimerList = &xActiveTimerList2;
 80057c4:	4b12      	ldr	r3, [pc, #72]	; (8005810 <prvCheckForValidListAndQueue+0x70>)
 80057c6:	4a10      	ldr	r2, [pc, #64]	; (8005808 <prvCheckForValidListAndQueue+0x68>)
 80057c8:	601a      	str	r2, [r3, #0]
				/* The timer queue is allocated statically in case
				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */

				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
 80057ca:	2300      	movs	r3, #0
 80057cc:	9300      	str	r3, [sp, #0]
 80057ce:	4b11      	ldr	r3, [pc, #68]	; (8005814 <prvCheckForValidListAndQueue+0x74>)
 80057d0:	4a11      	ldr	r2, [pc, #68]	; (8005818 <prvCheckForValidListAndQueue+0x78>)
 80057d2:	2110      	movs	r1, #16
 80057d4:	200a      	movs	r0, #10
 80057d6:	f7fe f929 	bl	8003a2c <xQueueGenericCreateStatic>
 80057da:	4603      	mov	r3, r0
 80057dc:	4a08      	ldr	r2, [pc, #32]	; (8005800 <prvCheckForValidListAndQueue+0x60>)
 80057de:	6013      	str	r3, [r2, #0]
			}
			#endif

			#if ( configQUEUE_REGISTRY_SIZE > 0 )
			{
				if( xTimerQueue != NULL )
 80057e0:	4b07      	ldr	r3, [pc, #28]	; (8005800 <prvCheckForValidListAndQueue+0x60>)
 80057e2:	681b      	ldr	r3, [r3, #0]
 80057e4:	2b00      	cmp	r3, #0
 80057e6:	d005      	beq.n	80057f4 <prvCheckForValidListAndQueue+0x54>
				{
					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
 80057e8:	4b05      	ldr	r3, [pc, #20]	; (8005800 <prvCheckForValidListAndQueue+0x60>)
 80057ea:	681b      	ldr	r3, [r3, #0]
 80057ec:	490b      	ldr	r1, [pc, #44]	; (800581c <prvCheckForValidListAndQueue+0x7c>)
 80057ee:	4618      	mov	r0, r3
 80057f0:	f7fe fd42 	bl	8004278 <vQueueAddToRegistry>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
	taskEXIT_CRITICAL();
 80057f4:	f000 f96e 	bl	8005ad4 <vPortExitCritical>
}
 80057f8:	bf00      	nop
 80057fa:	46bd      	mov	sp, r7
 80057fc:	bd80      	pop	{r7, pc}
 80057fe:	bf00      	nop
 8005800:	20000e40 	.word	0x20000e40
 8005804:	20000e10 	.word	0x20000e10
 8005808:	20000e24 	.word	0x20000e24
 800580c:	20000e38 	.word	0x20000e38
 8005810:	20000e3c 	.word	0x20000e3c
 8005814:	20000eec 	.word	0x20000eec
 8005818:	20000e4c 	.word	0x20000e4c
 800581c:	080062bc 	.word	0x080062bc

08005820 <pxPortInitialiseStack>:

/*
 * See header file for description.
 */
StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
{
 8005820:	b480      	push	{r7}
 8005822:	b085      	sub	sp, #20
 8005824:	af00      	add	r7, sp, #0
 8005826:	60f8      	str	r0, [r7, #12]
 8005828:	60b9      	str	r1, [r7, #8]
 800582a:	607a      	str	r2, [r7, #4]
	/* Simulate the stack frame as it would be created by a context switch
	interrupt. */

	/* Offset added to account for the way the MCU uses the stack on entry/exit
	of interrupts, and to ensure alignment. */
	pxTopOfStack--;
 800582c:	68fb      	ldr	r3, [r7, #12]
 800582e:	3b04      	subs	r3, #4
 8005830:	60fb      	str	r3, [r7, #12]

	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
 8005832:	68fb      	ldr	r3, [r7, #12]
 8005834:	f04f 7280 	mov.w	r2, #16777216	; 0x1000000
 8005838:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 800583a:	68fb      	ldr	r3, [r7, #12]
 800583c:	3b04      	subs	r3, #4
 800583e:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
 8005840:	68bb      	ldr	r3, [r7, #8]
 8005842:	f023 0201 	bic.w	r2, r3, #1
 8005846:	68fb      	ldr	r3, [r7, #12]
 8005848:	601a      	str	r2, [r3, #0]
	pxTopOfStack--;
 800584a:	68fb      	ldr	r3, [r7, #12]
 800584c:	3b04      	subs	r3, #4
 800584e:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
 8005850:	4a0c      	ldr	r2, [pc, #48]	; (8005884 <pxPortInitialiseStack+0x64>)
 8005852:	68fb      	ldr	r3, [r7, #12]
 8005854:	601a      	str	r2, [r3, #0]

	/* Save code space by skipping register initialisation. */
	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
 8005856:	68fb      	ldr	r3, [r7, #12]
 8005858:	3b14      	subs	r3, #20
 800585a:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
 800585c:	687a      	ldr	r2, [r7, #4]
 800585e:	68fb      	ldr	r3, [r7, #12]
 8005860:	601a      	str	r2, [r3, #0]

	/* A save method is being used that requires each task to maintain its
	own exec return value. */
	pxTopOfStack--;
 8005862:	68fb      	ldr	r3, [r7, #12]
 8005864:	3b04      	subs	r3, #4
 8005866:	60fb      	str	r3, [r7, #12]
	*pxTopOfStack = portINITIAL_EXC_RETURN;
 8005868:	68fb      	ldr	r3, [r7, #12]
 800586a:	f06f 0202 	mvn.w	r2, #2
 800586e:	601a      	str	r2, [r3, #0]

	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
 8005870:	68fb      	ldr	r3, [r7, #12]
 8005872:	3b20      	subs	r3, #32
 8005874:	60fb      	str	r3, [r7, #12]

	return pxTopOfStack;
 8005876:	68fb      	ldr	r3, [r7, #12]
}
 8005878:	4618      	mov	r0, r3
 800587a:	3714      	adds	r7, #20
 800587c:	46bd      	mov	sp, r7
 800587e:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005882:	4770      	bx	lr
 8005884:	08005889 	.word	0x08005889

08005888 <prvTaskExitError>:
/*-----------------------------------------------------------*/

static void prvTaskExitError( void )
{
 8005888:	b480      	push	{r7}
 800588a:	b085      	sub	sp, #20
 800588c:	af00      	add	r7, sp, #0
volatile uint32_t ulDummy = 0;
 800588e:	2300      	movs	r3, #0
 8005890:	607b      	str	r3, [r7, #4]
	its caller as there is nothing to return to.  If a task wants to exit it
	should instead call vTaskDelete( NULL ).

	Artificially force an assert() to be triggered if configASSERT() is
	defined, then stop here so application writers can catch the error. */
	configASSERT( uxCriticalNesting == ~0UL );
 8005892:	4b12      	ldr	r3, [pc, #72]	; (80058dc <prvTaskExitError+0x54>)
 8005894:	681b      	ldr	r3, [r3, #0]
 8005896:	f1b3 3fff 	cmp.w	r3, #4294967295
 800589a:	d00a      	beq.n	80058b2 <prvTaskExitError+0x2a>
	__asm volatile
 800589c:	f04f 0350 	mov.w	r3, #80	; 0x50
 80058a0:	f383 8811 	msr	BASEPRI, r3
 80058a4:	f3bf 8f6f 	isb	sy
 80058a8:	f3bf 8f4f 	dsb	sy
 80058ac:	60fb      	str	r3, [r7, #12]
}
 80058ae:	bf00      	nop
 80058b0:	e7fe      	b.n	80058b0 <prvTaskExitError+0x28>
	__asm volatile
 80058b2:	f04f 0350 	mov.w	r3, #80	; 0x50
 80058b6:	f383 8811 	msr	BASEPRI, r3
 80058ba:	f3bf 8f6f 	isb	sy
 80058be:	f3bf 8f4f 	dsb	sy
 80058c2:	60bb      	str	r3, [r7, #8]
}
 80058c4:	bf00      	nop
	portDISABLE_INTERRUPTS();
	while( ulDummy == 0 )
 80058c6:	bf00      	nop
 80058c8:	687b      	ldr	r3, [r7, #4]
 80058ca:	2b00      	cmp	r3, #0
 80058cc:	d0fc      	beq.n	80058c8 <prvTaskExitError+0x40>
		about code appearing after this function is called - making ulDummy
		volatile makes the compiler think the function could return and
		therefore not output an 'unreachable code' warning for code that appears
		after it. */
	}
}
 80058ce:	bf00      	nop
 80058d0:	bf00      	nop
 80058d2:	3714      	adds	r7, #20
 80058d4:	46bd      	mov	sp, r7
 80058d6:	f85d 7b04 	ldr.w	r7, [sp], #4
 80058da:	4770      	bx	lr
 80058dc:	2000000c 	.word	0x2000000c

080058e0 <SVC_Handler>:
/*-----------------------------------------------------------*/

void vPortSVCHandler( void )
{
	__asm volatile (
 80058e0:	4b07      	ldr	r3, [pc, #28]	; (8005900 <pxCurrentTCBConst2>)
 80058e2:	6819      	ldr	r1, [r3, #0]
 80058e4:	6808      	ldr	r0, [r1, #0]
 80058e6:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 80058ea:	f380 8809 	msr	PSP, r0
 80058ee:	f3bf 8f6f 	isb	sy
 80058f2:	f04f 0000 	mov.w	r0, #0
 80058f6:	f380 8811 	msr	BASEPRI, r0
 80058fa:	4770      	bx	lr
 80058fc:	f3af 8000 	nop.w

08005900 <pxCurrentTCBConst2>:
 8005900:	20000910 	.word	0x20000910
					"	bx r14							\n"
					"									\n"
					"	.align 4						\n"
					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
				);
}
 8005904:	bf00      	nop
 8005906:	bf00      	nop

08005908 <prvPortStartFirstTask>:
{
	/* Start the first task.  This also clears the bit that indicates the FPU is
	in use in case the FPU was used before the scheduler was started - which
	would otherwise result in the unnecessary leaving of space in the SVC stack
	for lazy saving of FPU registers. */
	__asm volatile(
 8005908:	4808      	ldr	r0, [pc, #32]	; (800592c <prvPortStartFirstTask+0x24>)
 800590a:	6800      	ldr	r0, [r0, #0]
 800590c:	6800      	ldr	r0, [r0, #0]
 800590e:	f380 8808 	msr	MSP, r0
 8005912:	f04f 0000 	mov.w	r0, #0
 8005916:	f380 8814 	msr	CONTROL, r0
 800591a:	b662      	cpsie	i
 800591c:	b661      	cpsie	f
 800591e:	f3bf 8f4f 	dsb	sy
 8005922:	f3bf 8f6f 	isb	sy
 8005926:	df00      	svc	0
 8005928:	bf00      	nop
					" dsb					\n"
					" isb					\n"
					" svc 0					\n" /* System call to start first task. */
					" nop					\n"
				);
}
 800592a:	bf00      	nop
 800592c:	e000ed08 	.word	0xe000ed08

08005930 <xPortStartScheduler>:

/*
 * See header file for description.
 */
BaseType_t xPortStartScheduler( void )
{
 8005930:	b580      	push	{r7, lr}
 8005932:	b086      	sub	sp, #24
 8005934:	af00      	add	r7, sp, #0
	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );

	/* This port can be used on all revisions of the Cortex-M7 core other than
	the r0p1 parts.  r0p1 parts should use the port from the
	/source/portable/GCC/ARM_CM7/r0p1 directory. */
	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
 8005936:	4b46      	ldr	r3, [pc, #280]	; (8005a50 <xPortStartScheduler+0x120>)
 8005938:	681b      	ldr	r3, [r3, #0]
 800593a:	4a46      	ldr	r2, [pc, #280]	; (8005a54 <xPortStartScheduler+0x124>)
 800593c:	4293      	cmp	r3, r2
 800593e:	d10a      	bne.n	8005956 <xPortStartScheduler+0x26>
	__asm volatile
 8005940:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005944:	f383 8811 	msr	BASEPRI, r3
 8005948:	f3bf 8f6f 	isb	sy
 800594c:	f3bf 8f4f 	dsb	sy
 8005950:	613b      	str	r3, [r7, #16]
}
 8005952:	bf00      	nop
 8005954:	e7fe      	b.n	8005954 <xPortStartScheduler+0x24>
	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
 8005956:	4b3e      	ldr	r3, [pc, #248]	; (8005a50 <xPortStartScheduler+0x120>)
 8005958:	681b      	ldr	r3, [r3, #0]
 800595a:	4a3f      	ldr	r2, [pc, #252]	; (8005a58 <xPortStartScheduler+0x128>)
 800595c:	4293      	cmp	r3, r2
 800595e:	d10a      	bne.n	8005976 <xPortStartScheduler+0x46>
	__asm volatile
 8005960:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005964:	f383 8811 	msr	BASEPRI, r3
 8005968:	f3bf 8f6f 	isb	sy
 800596c:	f3bf 8f4f 	dsb	sy
 8005970:	60fb      	str	r3, [r7, #12]
}
 8005972:	bf00      	nop
 8005974:	e7fe      	b.n	8005974 <xPortStartScheduler+0x44>

	#if( configASSERT_DEFINED == 1 )
	{
		volatile uint32_t ulOriginalPriority;
		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
 8005976:	4b39      	ldr	r3, [pc, #228]	; (8005a5c <xPortStartScheduler+0x12c>)
 8005978:	617b      	str	r3, [r7, #20]
		functions can be called.  ISR safe functions are those that end in
		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
		ensure interrupt entry is as fast and simple as possible.

		Save the interrupt priority value that is about to be clobbered. */
		ulOriginalPriority = *pucFirstUserPriorityRegister;
 800597a:	697b      	ldr	r3, [r7, #20]
 800597c:	781b      	ldrb	r3, [r3, #0]
 800597e:	b2db      	uxtb	r3, r3
 8005980:	607b      	str	r3, [r7, #4]

		/* Determine the number of priority bits available.  First write to all
		possible bits. */
		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
 8005982:	697b      	ldr	r3, [r7, #20]
 8005984:	22ff      	movs	r2, #255	; 0xff
 8005986:	701a      	strb	r2, [r3, #0]

		/* Read the value back to see how many bits stuck. */
		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
 8005988:	697b      	ldr	r3, [r7, #20]
 800598a:	781b      	ldrb	r3, [r3, #0]
 800598c:	b2db      	uxtb	r3, r3
 800598e:	70fb      	strb	r3, [r7, #3]

		/* Use the same mask on the maximum system call priority. */
		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
 8005990:	78fb      	ldrb	r3, [r7, #3]
 8005992:	b2db      	uxtb	r3, r3
 8005994:	f003 0350 	and.w	r3, r3, #80	; 0x50
 8005998:	b2da      	uxtb	r2, r3
 800599a:	4b31      	ldr	r3, [pc, #196]	; (8005a60 <xPortStartScheduler+0x130>)
 800599c:	701a      	strb	r2, [r3, #0]

		/* Calculate the maximum acceptable priority group value for the number
		of bits read back. */
		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
 800599e:	4b31      	ldr	r3, [pc, #196]	; (8005a64 <xPortStartScheduler+0x134>)
 80059a0:	2207      	movs	r2, #7
 80059a2:	601a      	str	r2, [r3, #0]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 80059a4:	e009      	b.n	80059ba <xPortStartScheduler+0x8a>
		{
			ulMaxPRIGROUPValue--;
 80059a6:	4b2f      	ldr	r3, [pc, #188]	; (8005a64 <xPortStartScheduler+0x134>)
 80059a8:	681b      	ldr	r3, [r3, #0]
 80059aa:	3b01      	subs	r3, #1
 80059ac:	4a2d      	ldr	r2, [pc, #180]	; (8005a64 <xPortStartScheduler+0x134>)
 80059ae:	6013      	str	r3, [r2, #0]
			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
 80059b0:	78fb      	ldrb	r3, [r7, #3]
 80059b2:	b2db      	uxtb	r3, r3
 80059b4:	005b      	lsls	r3, r3, #1
 80059b6:	b2db      	uxtb	r3, r3
 80059b8:	70fb      	strb	r3, [r7, #3]
		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
 80059ba:	78fb      	ldrb	r3, [r7, #3]
 80059bc:	b2db      	uxtb	r3, r3
 80059be:	f003 0380 	and.w	r3, r3, #128	; 0x80
 80059c2:	2b80      	cmp	r3, #128	; 0x80
 80059c4:	d0ef      	beq.n	80059a6 <xPortStartScheduler+0x76>
		#ifdef configPRIO_BITS
		{
			/* Check the FreeRTOS configuration that defines the number of
			priority bits matches the number of priority bits actually queried
			from the hardware. */
			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
 80059c6:	4b27      	ldr	r3, [pc, #156]	; (8005a64 <xPortStartScheduler+0x134>)
 80059c8:	681b      	ldr	r3, [r3, #0]
 80059ca:	f1c3 0307 	rsb	r3, r3, #7
 80059ce:	2b04      	cmp	r3, #4
 80059d0:	d00a      	beq.n	80059e8 <xPortStartScheduler+0xb8>
	__asm volatile
 80059d2:	f04f 0350 	mov.w	r3, #80	; 0x50
 80059d6:	f383 8811 	msr	BASEPRI, r3
 80059da:	f3bf 8f6f 	isb	sy
 80059de:	f3bf 8f4f 	dsb	sy
 80059e2:	60bb      	str	r3, [r7, #8]
}
 80059e4:	bf00      	nop
 80059e6:	e7fe      	b.n	80059e6 <xPortStartScheduler+0xb6>
		}
		#endif

		/* Shift the priority group value back to its position within the AIRCR
		register. */
		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
 80059e8:	4b1e      	ldr	r3, [pc, #120]	; (8005a64 <xPortStartScheduler+0x134>)
 80059ea:	681b      	ldr	r3, [r3, #0]
 80059ec:	021b      	lsls	r3, r3, #8
 80059ee:	4a1d      	ldr	r2, [pc, #116]	; (8005a64 <xPortStartScheduler+0x134>)
 80059f0:	6013      	str	r3, [r2, #0]
		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
 80059f2:	4b1c      	ldr	r3, [pc, #112]	; (8005a64 <xPortStartScheduler+0x134>)
 80059f4:	681b      	ldr	r3, [r3, #0]
 80059f6:	f403 63e0 	and.w	r3, r3, #1792	; 0x700
 80059fa:	4a1a      	ldr	r2, [pc, #104]	; (8005a64 <xPortStartScheduler+0x134>)
 80059fc:	6013      	str	r3, [r2, #0]

		/* Restore the clobbered interrupt priority register to its original
		value. */
		*pucFirstUserPriorityRegister = ulOriginalPriority;
 80059fe:	687b      	ldr	r3, [r7, #4]
 8005a00:	b2da      	uxtb	r2, r3
 8005a02:	697b      	ldr	r3, [r7, #20]
 8005a04:	701a      	strb	r2, [r3, #0]
	}
	#endif /* conifgASSERT_DEFINED */

	/* Make PendSV and SysTick the lowest priority interrupts. */
	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
 8005a06:	4b18      	ldr	r3, [pc, #96]	; (8005a68 <xPortStartScheduler+0x138>)
 8005a08:	681b      	ldr	r3, [r3, #0]
 8005a0a:	4a17      	ldr	r2, [pc, #92]	; (8005a68 <xPortStartScheduler+0x138>)
 8005a0c:	f443 0370 	orr.w	r3, r3, #15728640	; 0xf00000
 8005a10:	6013      	str	r3, [r2, #0]
	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
 8005a12:	4b15      	ldr	r3, [pc, #84]	; (8005a68 <xPortStartScheduler+0x138>)
 8005a14:	681b      	ldr	r3, [r3, #0]
 8005a16:	4a14      	ldr	r2, [pc, #80]	; (8005a68 <xPortStartScheduler+0x138>)
 8005a18:	f043 4370 	orr.w	r3, r3, #4026531840	; 0xf0000000
 8005a1c:	6013      	str	r3, [r2, #0]

	/* Start the timer that generates the tick ISR.  Interrupts are disabled
	here already. */
	vPortSetupTimerInterrupt();
 8005a1e:	f000 f8dd 	bl	8005bdc <vPortSetupTimerInterrupt>

	/* Initialise the critical nesting count ready for the first task. */
	uxCriticalNesting = 0;
 8005a22:	4b12      	ldr	r3, [pc, #72]	; (8005a6c <xPortStartScheduler+0x13c>)
 8005a24:	2200      	movs	r2, #0
 8005a26:	601a      	str	r2, [r3, #0]

	/* Ensure the VFP is enabled - it should be anyway. */
	vPortEnableVFP();
 8005a28:	f000 f8fc 	bl	8005c24 <vPortEnableVFP>

	/* Lazy save always. */
	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
 8005a2c:	4b10      	ldr	r3, [pc, #64]	; (8005a70 <xPortStartScheduler+0x140>)
 8005a2e:	681b      	ldr	r3, [r3, #0]
 8005a30:	4a0f      	ldr	r2, [pc, #60]	; (8005a70 <xPortStartScheduler+0x140>)
 8005a32:	f043 4340 	orr.w	r3, r3, #3221225472	; 0xc0000000
 8005a36:	6013      	str	r3, [r2, #0]

	/* Start the first task. */
	prvPortStartFirstTask();
 8005a38:	f7ff ff66 	bl	8005908 <prvPortStartFirstTask>
	exit error function to prevent compiler warnings about a static function
	not being called in the case that the application writer overrides this
	functionality by defining configTASK_RETURN_ADDRESS.  Call
	vTaskSwitchContext() so link time optimisation does not remove the
	symbol. */
	vTaskSwitchContext();
 8005a3c:	f7ff f84c 	bl	8004ad8 <vTaskSwitchContext>
	prvTaskExitError();
 8005a40:	f7ff ff22 	bl	8005888 <prvTaskExitError>

	/* Should not get here! */
	return 0;
 8005a44:	2300      	movs	r3, #0
}
 8005a46:	4618      	mov	r0, r3
 8005a48:	3718      	adds	r7, #24
 8005a4a:	46bd      	mov	sp, r7
 8005a4c:	bd80      	pop	{r7, pc}
 8005a4e:	bf00      	nop
 8005a50:	e000ed00 	.word	0xe000ed00
 8005a54:	410fc271 	.word	0x410fc271
 8005a58:	410fc270 	.word	0x410fc270
 8005a5c:	e000e400 	.word	0xe000e400
 8005a60:	20000f3c 	.word	0x20000f3c
 8005a64:	20000f40 	.word	0x20000f40
 8005a68:	e000ed20 	.word	0xe000ed20
 8005a6c:	2000000c 	.word	0x2000000c
 8005a70:	e000ef34 	.word	0xe000ef34

08005a74 <vPortEnterCritical>:
	configASSERT( uxCriticalNesting == 1000UL );
}
/*-----------------------------------------------------------*/

void vPortEnterCritical( void )
{
 8005a74:	b480      	push	{r7}
 8005a76:	b083      	sub	sp, #12
 8005a78:	af00      	add	r7, sp, #0
	__asm volatile
 8005a7a:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005a7e:	f383 8811 	msr	BASEPRI, r3
 8005a82:	f3bf 8f6f 	isb	sy
 8005a86:	f3bf 8f4f 	dsb	sy
 8005a8a:	607b      	str	r3, [r7, #4]
}
 8005a8c:	bf00      	nop
	portDISABLE_INTERRUPTS();
	uxCriticalNesting++;
 8005a8e:	4b0f      	ldr	r3, [pc, #60]	; (8005acc <vPortEnterCritical+0x58>)
 8005a90:	681b      	ldr	r3, [r3, #0]
 8005a92:	3301      	adds	r3, #1
 8005a94:	4a0d      	ldr	r2, [pc, #52]	; (8005acc <vPortEnterCritical+0x58>)
 8005a96:	6013      	str	r3, [r2, #0]
	/* This is not the interrupt safe version of the enter critical function so
	assert() if it is being called from an interrupt context.  Only API
	functions that end in "FromISR" can be used in an interrupt.  Only assert if
	the critical nesting count is 1 to protect against recursive calls if the
	assert function also uses a critical section. */
	if( uxCriticalNesting == 1 )
 8005a98:	4b0c      	ldr	r3, [pc, #48]	; (8005acc <vPortEnterCritical+0x58>)
 8005a9a:	681b      	ldr	r3, [r3, #0]
 8005a9c:	2b01      	cmp	r3, #1
 8005a9e:	d10f      	bne.n	8005ac0 <vPortEnterCritical+0x4c>
	{
		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
 8005aa0:	4b0b      	ldr	r3, [pc, #44]	; (8005ad0 <vPortEnterCritical+0x5c>)
 8005aa2:	681b      	ldr	r3, [r3, #0]
 8005aa4:	b2db      	uxtb	r3, r3
 8005aa6:	2b00      	cmp	r3, #0
 8005aa8:	d00a      	beq.n	8005ac0 <vPortEnterCritical+0x4c>
	__asm volatile
 8005aaa:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005aae:	f383 8811 	msr	BASEPRI, r3
 8005ab2:	f3bf 8f6f 	isb	sy
 8005ab6:	f3bf 8f4f 	dsb	sy
 8005aba:	603b      	str	r3, [r7, #0]
}
 8005abc:	bf00      	nop
 8005abe:	e7fe      	b.n	8005abe <vPortEnterCritical+0x4a>
	}
}
 8005ac0:	bf00      	nop
 8005ac2:	370c      	adds	r7, #12
 8005ac4:	46bd      	mov	sp, r7
 8005ac6:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005aca:	4770      	bx	lr
 8005acc:	2000000c 	.word	0x2000000c
 8005ad0:	e000ed04 	.word	0xe000ed04

08005ad4 <vPortExitCritical>:
/*-----------------------------------------------------------*/

void vPortExitCritical( void )
{
 8005ad4:	b480      	push	{r7}
 8005ad6:	b083      	sub	sp, #12
 8005ad8:	af00      	add	r7, sp, #0
	configASSERT( uxCriticalNesting );
 8005ada:	4b12      	ldr	r3, [pc, #72]	; (8005b24 <vPortExitCritical+0x50>)
 8005adc:	681b      	ldr	r3, [r3, #0]
 8005ade:	2b00      	cmp	r3, #0
 8005ae0:	d10a      	bne.n	8005af8 <vPortExitCritical+0x24>
	__asm volatile
 8005ae2:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005ae6:	f383 8811 	msr	BASEPRI, r3
 8005aea:	f3bf 8f6f 	isb	sy
 8005aee:	f3bf 8f4f 	dsb	sy
 8005af2:	607b      	str	r3, [r7, #4]
}
 8005af4:	bf00      	nop
 8005af6:	e7fe      	b.n	8005af6 <vPortExitCritical+0x22>
	uxCriticalNesting--;
 8005af8:	4b0a      	ldr	r3, [pc, #40]	; (8005b24 <vPortExitCritical+0x50>)
 8005afa:	681b      	ldr	r3, [r3, #0]
 8005afc:	3b01      	subs	r3, #1
 8005afe:	4a09      	ldr	r2, [pc, #36]	; (8005b24 <vPortExitCritical+0x50>)
 8005b00:	6013      	str	r3, [r2, #0]
	if( uxCriticalNesting == 0 )
 8005b02:	4b08      	ldr	r3, [pc, #32]	; (8005b24 <vPortExitCritical+0x50>)
 8005b04:	681b      	ldr	r3, [r3, #0]
 8005b06:	2b00      	cmp	r3, #0
 8005b08:	d105      	bne.n	8005b16 <vPortExitCritical+0x42>
 8005b0a:	2300      	movs	r3, #0
 8005b0c:	603b      	str	r3, [r7, #0]
	__asm volatile
 8005b0e:	683b      	ldr	r3, [r7, #0]
 8005b10:	f383 8811 	msr	BASEPRI, r3
}
 8005b14:	bf00      	nop
	{
		portENABLE_INTERRUPTS();
	}
}
 8005b16:	bf00      	nop
 8005b18:	370c      	adds	r7, #12
 8005b1a:	46bd      	mov	sp, r7
 8005b1c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005b20:	4770      	bx	lr
 8005b22:	bf00      	nop
 8005b24:	2000000c 	.word	0x2000000c
	...

08005b30 <PendSV_Handler>:

void xPortPendSVHandler( void )
{
	/* This is a naked function. */

	__asm volatile
 8005b30:	f3ef 8009 	mrs	r0, PSP
 8005b34:	f3bf 8f6f 	isb	sy
 8005b38:	4b15      	ldr	r3, [pc, #84]	; (8005b90 <pxCurrentTCBConst>)
 8005b3a:	681a      	ldr	r2, [r3, #0]
 8005b3c:	f01e 0f10 	tst.w	lr, #16
 8005b40:	bf08      	it	eq
 8005b42:	ed20 8a10 	vstmdbeq	r0!, {s16-s31}
 8005b46:	e920 4ff0 	stmdb	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8005b4a:	6010      	str	r0, [r2, #0]
 8005b4c:	e92d 0009 	stmdb	sp!, {r0, r3}
 8005b50:	f04f 0050 	mov.w	r0, #80	; 0x50
 8005b54:	f380 8811 	msr	BASEPRI, r0
 8005b58:	f3bf 8f4f 	dsb	sy
 8005b5c:	f3bf 8f6f 	isb	sy
 8005b60:	f7fe ffba 	bl	8004ad8 <vTaskSwitchContext>
 8005b64:	f04f 0000 	mov.w	r0, #0
 8005b68:	f380 8811 	msr	BASEPRI, r0
 8005b6c:	bc09      	pop	{r0, r3}
 8005b6e:	6819      	ldr	r1, [r3, #0]
 8005b70:	6808      	ldr	r0, [r1, #0]
 8005b72:	e8b0 4ff0 	ldmia.w	r0!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
 8005b76:	f01e 0f10 	tst.w	lr, #16
 8005b7a:	bf08      	it	eq
 8005b7c:	ecb0 8a10 	vldmiaeq	r0!, {s16-s31}
 8005b80:	f380 8809 	msr	PSP, r0
 8005b84:	f3bf 8f6f 	isb	sy
 8005b88:	4770      	bx	lr
 8005b8a:	bf00      	nop
 8005b8c:	f3af 8000 	nop.w

08005b90 <pxCurrentTCBConst>:
 8005b90:	20000910 	.word	0x20000910
	"										\n"
	"	.align 4							\n"
	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
	);
}
 8005b94:	bf00      	nop
 8005b96:	bf00      	nop

08005b98 <xPortSysTickHandler>:
/*-----------------------------------------------------------*/

void xPortSysTickHandler( void )
{
 8005b98:	b580      	push	{r7, lr}
 8005b9a:	b082      	sub	sp, #8
 8005b9c:	af00      	add	r7, sp, #0
	__asm volatile
 8005b9e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005ba2:	f383 8811 	msr	BASEPRI, r3
 8005ba6:	f3bf 8f6f 	isb	sy
 8005baa:	f3bf 8f4f 	dsb	sy
 8005bae:	607b      	str	r3, [r7, #4]
}
 8005bb0:	bf00      	nop
	save and then restore the interrupt mask value as its value is already
	known. */
	portDISABLE_INTERRUPTS();
	{
		/* Increment the RTOS tick. */
		if( xTaskIncrementTick() != pdFALSE )
 8005bb2:	f7fe fed7 	bl	8004964 <xTaskIncrementTick>
 8005bb6:	4603      	mov	r3, r0
 8005bb8:	2b00      	cmp	r3, #0
 8005bba:	d003      	beq.n	8005bc4 <xPortSysTickHandler+0x2c>
		{
			/* A context switch is required.  Context switching is performed in
			the PendSV interrupt.  Pend the PendSV interrupt. */
			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
 8005bbc:	4b06      	ldr	r3, [pc, #24]	; (8005bd8 <xPortSysTickHandler+0x40>)
 8005bbe:	f04f 5280 	mov.w	r2, #268435456	; 0x10000000
 8005bc2:	601a      	str	r2, [r3, #0]
 8005bc4:	2300      	movs	r3, #0
 8005bc6:	603b      	str	r3, [r7, #0]
	__asm volatile
 8005bc8:	683b      	ldr	r3, [r7, #0]
 8005bca:	f383 8811 	msr	BASEPRI, r3
}
 8005bce:	bf00      	nop
		}
	}
	portENABLE_INTERRUPTS();
}
 8005bd0:	bf00      	nop
 8005bd2:	3708      	adds	r7, #8
 8005bd4:	46bd      	mov	sp, r7
 8005bd6:	bd80      	pop	{r7, pc}
 8005bd8:	e000ed04 	.word	0xe000ed04

08005bdc <vPortSetupTimerInterrupt>:
/*
 * Setup the systick timer to generate the tick interrupts at the required
 * frequency.
 */
__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
{
 8005bdc:	b480      	push	{r7}
 8005bde:	af00      	add	r7, sp, #0
		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
	}
	#endif /* configUSE_TICKLESS_IDLE */

	/* Stop and clear the SysTick. */
	portNVIC_SYSTICK_CTRL_REG = 0UL;
 8005be0:	4b0b      	ldr	r3, [pc, #44]	; (8005c10 <vPortSetupTimerInterrupt+0x34>)
 8005be2:	2200      	movs	r2, #0
 8005be4:	601a      	str	r2, [r3, #0]
	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
 8005be6:	4b0b      	ldr	r3, [pc, #44]	; (8005c14 <vPortSetupTimerInterrupt+0x38>)
 8005be8:	2200      	movs	r2, #0
 8005bea:	601a      	str	r2, [r3, #0]

	/* Configure SysTick to interrupt at the requested rate. */
	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
 8005bec:	4b0a      	ldr	r3, [pc, #40]	; (8005c18 <vPortSetupTimerInterrupt+0x3c>)
 8005bee:	681b      	ldr	r3, [r3, #0]
 8005bf0:	4a0a      	ldr	r2, [pc, #40]	; (8005c1c <vPortSetupTimerInterrupt+0x40>)
 8005bf2:	fba2 2303 	umull	r2, r3, r2, r3
 8005bf6:	099b      	lsrs	r3, r3, #6
 8005bf8:	4a09      	ldr	r2, [pc, #36]	; (8005c20 <vPortSetupTimerInterrupt+0x44>)
 8005bfa:	3b01      	subs	r3, #1
 8005bfc:	6013      	str	r3, [r2, #0]
	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
 8005bfe:	4b04      	ldr	r3, [pc, #16]	; (8005c10 <vPortSetupTimerInterrupt+0x34>)
 8005c00:	2207      	movs	r2, #7
 8005c02:	601a      	str	r2, [r3, #0]
}
 8005c04:	bf00      	nop
 8005c06:	46bd      	mov	sp, r7
 8005c08:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005c0c:	4770      	bx	lr
 8005c0e:	bf00      	nop
 8005c10:	e000e010 	.word	0xe000e010
 8005c14:	e000e018 	.word	0xe000e018
 8005c18:	20000000 	.word	0x20000000
 8005c1c:	10624dd3 	.word	0x10624dd3
 8005c20:	e000e014 	.word	0xe000e014

08005c24 <vPortEnableVFP>:
/*-----------------------------------------------------------*/

/* This is a naked function. */
static void vPortEnableVFP( void )
{
	__asm volatile
 8005c24:	f8df 000c 	ldr.w	r0, [pc, #12]	; 8005c34 <vPortEnableVFP+0x10>
 8005c28:	6801      	ldr	r1, [r0, #0]
 8005c2a:	f441 0170 	orr.w	r1, r1, #15728640	; 0xf00000
 8005c2e:	6001      	str	r1, [r0, #0]
 8005c30:	4770      	bx	lr
		"								\n"
		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
		"	str r1, [r0]				\n"
		"	bx r14						"
	);
}
 8005c32:	bf00      	nop
 8005c34:	e000ed88 	.word	0xe000ed88

08005c38 <vPortValidateInterruptPriority>:
/*-----------------------------------------------------------*/

#if( configASSERT_DEFINED == 1 )

	void vPortValidateInterruptPriority( void )
	{
 8005c38:	b480      	push	{r7}
 8005c3a:	b085      	sub	sp, #20
 8005c3c:	af00      	add	r7, sp, #0
	uint32_t ulCurrentInterrupt;
	uint8_t ucCurrentPriority;

		/* Obtain the number of the currently executing interrupt. */
		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
 8005c3e:	f3ef 8305 	mrs	r3, IPSR
 8005c42:	60fb      	str	r3, [r7, #12]

		/* Is the interrupt number a user defined interrupt? */
		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
 8005c44:	68fb      	ldr	r3, [r7, #12]
 8005c46:	2b0f      	cmp	r3, #15
 8005c48:	d914      	bls.n	8005c74 <vPortValidateInterruptPriority+0x3c>
		{
			/* Look up the interrupt's priority. */
			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
 8005c4a:	4a17      	ldr	r2, [pc, #92]	; (8005ca8 <vPortValidateInterruptPriority+0x70>)
 8005c4c:	68fb      	ldr	r3, [r7, #12]
 8005c4e:	4413      	add	r3, r2
 8005c50:	781b      	ldrb	r3, [r3, #0]
 8005c52:	72fb      	strb	r3, [r7, #11]
			interrupt entry is as fast and simple as possible.

			The following links provide detailed information:
			http://www.freertos.org/RTOS-Cortex-M3-M4.html
			http://www.freertos.org/FAQHelp.html */
			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
 8005c54:	4b15      	ldr	r3, [pc, #84]	; (8005cac <vPortValidateInterruptPriority+0x74>)
 8005c56:	781b      	ldrb	r3, [r3, #0]
 8005c58:	7afa      	ldrb	r2, [r7, #11]
 8005c5a:	429a      	cmp	r2, r3
 8005c5c:	d20a      	bcs.n	8005c74 <vPortValidateInterruptPriority+0x3c>
	__asm volatile
 8005c5e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005c62:	f383 8811 	msr	BASEPRI, r3
 8005c66:	f3bf 8f6f 	isb	sy
 8005c6a:	f3bf 8f4f 	dsb	sy
 8005c6e:	607b      	str	r3, [r7, #4]
}
 8005c70:	bf00      	nop
 8005c72:	e7fe      	b.n	8005c72 <vPortValidateInterruptPriority+0x3a>
		configuration then the correct setting can be achieved on all Cortex-M
		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
		scheduler.  Note however that some vendor specific peripheral libraries
		assume a non-zero priority group setting, in which cases using a value
		of zero will result in unpredictable behaviour. */
		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
 8005c74:	4b0e      	ldr	r3, [pc, #56]	; (8005cb0 <vPortValidateInterruptPriority+0x78>)
 8005c76:	681b      	ldr	r3, [r3, #0]
 8005c78:	f403 62e0 	and.w	r2, r3, #1792	; 0x700
 8005c7c:	4b0d      	ldr	r3, [pc, #52]	; (8005cb4 <vPortValidateInterruptPriority+0x7c>)
 8005c7e:	681b      	ldr	r3, [r3, #0]
 8005c80:	429a      	cmp	r2, r3
 8005c82:	d90a      	bls.n	8005c9a <vPortValidateInterruptPriority+0x62>
	__asm volatile
 8005c84:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005c88:	f383 8811 	msr	BASEPRI, r3
 8005c8c:	f3bf 8f6f 	isb	sy
 8005c90:	f3bf 8f4f 	dsb	sy
 8005c94:	603b      	str	r3, [r7, #0]
}
 8005c96:	bf00      	nop
 8005c98:	e7fe      	b.n	8005c98 <vPortValidateInterruptPriority+0x60>
	}
 8005c9a:	bf00      	nop
 8005c9c:	3714      	adds	r7, #20
 8005c9e:	46bd      	mov	sp, r7
 8005ca0:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005ca4:	4770      	bx	lr
 8005ca6:	bf00      	nop
 8005ca8:	e000e3f0 	.word	0xe000e3f0
 8005cac:	20000f3c 	.word	0x20000f3c
 8005cb0:	e000ed0c 	.word	0xe000ed0c
 8005cb4:	20000f40 	.word	0x20000f40

08005cb8 <pvPortMalloc>:
static size_t xBlockAllocatedBit = 0;

/*-----------------------------------------------------------*/

void *pvPortMalloc( size_t xWantedSize )
{
 8005cb8:	b580      	push	{r7, lr}
 8005cba:	b08a      	sub	sp, #40	; 0x28
 8005cbc:	af00      	add	r7, sp, #0
 8005cbe:	6078      	str	r0, [r7, #4]
BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
void *pvReturn = NULL;
 8005cc0:	2300      	movs	r3, #0
 8005cc2:	61fb      	str	r3, [r7, #28]

	vTaskSuspendAll();
 8005cc4:	f7fe fd92 	bl	80047ec <vTaskSuspendAll>
	{
		/* If this is the first call to malloc then the heap will require
		initialisation to setup the list of free blocks. */
		if( pxEnd == NULL )
 8005cc8:	4b5b      	ldr	r3, [pc, #364]	; (8005e38 <pvPortMalloc+0x180>)
 8005cca:	681b      	ldr	r3, [r3, #0]
 8005ccc:	2b00      	cmp	r3, #0
 8005cce:	d101      	bne.n	8005cd4 <pvPortMalloc+0x1c>
		{
			prvHeapInit();
 8005cd0:	f000 f920 	bl	8005f14 <prvHeapInit>

		/* Check the requested block size is not so large that the top bit is
		set.  The top bit of the block size member of the BlockLink_t structure
		is used to determine who owns the block - the application or the
		kernel, so it must be free. */
		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
 8005cd4:	4b59      	ldr	r3, [pc, #356]	; (8005e3c <pvPortMalloc+0x184>)
 8005cd6:	681a      	ldr	r2, [r3, #0]
 8005cd8:	687b      	ldr	r3, [r7, #4]
 8005cda:	4013      	ands	r3, r2
 8005cdc:	2b00      	cmp	r3, #0
 8005cde:	f040 8093 	bne.w	8005e08 <pvPortMalloc+0x150>
		{
			/* The wanted size is increased so it can contain a BlockLink_t
			structure in addition to the requested amount of bytes. */
			if( xWantedSize > 0 )
 8005ce2:	687b      	ldr	r3, [r7, #4]
 8005ce4:	2b00      	cmp	r3, #0
 8005ce6:	d01d      	beq.n	8005d24 <pvPortMalloc+0x6c>
			{
				xWantedSize += xHeapStructSize;
 8005ce8:	2208      	movs	r2, #8
 8005cea:	687b      	ldr	r3, [r7, #4]
 8005cec:	4413      	add	r3, r2
 8005cee:	607b      	str	r3, [r7, #4]

				/* Ensure that blocks are always aligned to the required number
				of bytes. */
				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
 8005cf0:	687b      	ldr	r3, [r7, #4]
 8005cf2:	f003 0307 	and.w	r3, r3, #7
 8005cf6:	2b00      	cmp	r3, #0
 8005cf8:	d014      	beq.n	8005d24 <pvPortMalloc+0x6c>
				{
					/* Byte alignment required. */
					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
 8005cfa:	687b      	ldr	r3, [r7, #4]
 8005cfc:	f023 0307 	bic.w	r3, r3, #7
 8005d00:	3308      	adds	r3, #8
 8005d02:	607b      	str	r3, [r7, #4]
					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
 8005d04:	687b      	ldr	r3, [r7, #4]
 8005d06:	f003 0307 	and.w	r3, r3, #7
 8005d0a:	2b00      	cmp	r3, #0
 8005d0c:	d00a      	beq.n	8005d24 <pvPortMalloc+0x6c>
	__asm volatile
 8005d0e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005d12:	f383 8811 	msr	BASEPRI, r3
 8005d16:	f3bf 8f6f 	isb	sy
 8005d1a:	f3bf 8f4f 	dsb	sy
 8005d1e:	617b      	str	r3, [r7, #20]
}
 8005d20:	bf00      	nop
 8005d22:	e7fe      	b.n	8005d22 <pvPortMalloc+0x6a>
			else
			{
				mtCOVERAGE_TEST_MARKER();
			}

			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
 8005d24:	687b      	ldr	r3, [r7, #4]
 8005d26:	2b00      	cmp	r3, #0
 8005d28:	d06e      	beq.n	8005e08 <pvPortMalloc+0x150>
 8005d2a:	4b45      	ldr	r3, [pc, #276]	; (8005e40 <pvPortMalloc+0x188>)
 8005d2c:	681b      	ldr	r3, [r3, #0]
 8005d2e:	687a      	ldr	r2, [r7, #4]
 8005d30:	429a      	cmp	r2, r3
 8005d32:	d869      	bhi.n	8005e08 <pvPortMalloc+0x150>
			{
				/* Traverse the list from the start	(lowest address) block until
				one	of adequate size is found. */
				pxPreviousBlock = &xStart;
 8005d34:	4b43      	ldr	r3, [pc, #268]	; (8005e44 <pvPortMalloc+0x18c>)
 8005d36:	623b      	str	r3, [r7, #32]
				pxBlock = xStart.pxNextFreeBlock;
 8005d38:	4b42      	ldr	r3, [pc, #264]	; (8005e44 <pvPortMalloc+0x18c>)
 8005d3a:	681b      	ldr	r3, [r3, #0]
 8005d3c:	627b      	str	r3, [r7, #36]	; 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8005d3e:	e004      	b.n	8005d4a <pvPortMalloc+0x92>
				{
					pxPreviousBlock = pxBlock;
 8005d40:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005d42:	623b      	str	r3, [r7, #32]
					pxBlock = pxBlock->pxNextFreeBlock;
 8005d44:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005d46:	681b      	ldr	r3, [r3, #0]
 8005d48:	627b      	str	r3, [r7, #36]	; 0x24
				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
 8005d4a:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005d4c:	685b      	ldr	r3, [r3, #4]
 8005d4e:	687a      	ldr	r2, [r7, #4]
 8005d50:	429a      	cmp	r2, r3
 8005d52:	d903      	bls.n	8005d5c <pvPortMalloc+0xa4>
 8005d54:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005d56:	681b      	ldr	r3, [r3, #0]
 8005d58:	2b00      	cmp	r3, #0
 8005d5a:	d1f1      	bne.n	8005d40 <pvPortMalloc+0x88>
				}

				/* If the end marker was reached then a block of adequate size
				was	not found. */
				if( pxBlock != pxEnd )
 8005d5c:	4b36      	ldr	r3, [pc, #216]	; (8005e38 <pvPortMalloc+0x180>)
 8005d5e:	681b      	ldr	r3, [r3, #0]
 8005d60:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 8005d62:	429a      	cmp	r2, r3
 8005d64:	d050      	beq.n	8005e08 <pvPortMalloc+0x150>
				{
					/* Return the memory space pointed to - jumping over the
					BlockLink_t structure at its start. */
					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
 8005d66:	6a3b      	ldr	r3, [r7, #32]
 8005d68:	681b      	ldr	r3, [r3, #0]
 8005d6a:	2208      	movs	r2, #8
 8005d6c:	4413      	add	r3, r2
 8005d6e:	61fb      	str	r3, [r7, #28]

					/* This block is being returned for use so must be taken out
					of the list of free blocks. */
					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
 8005d70:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005d72:	681a      	ldr	r2, [r3, #0]
 8005d74:	6a3b      	ldr	r3, [r7, #32]
 8005d76:	601a      	str	r2, [r3, #0]

					/* If the block is larger than required it can be split into
					two. */
					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
 8005d78:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005d7a:	685a      	ldr	r2, [r3, #4]
 8005d7c:	687b      	ldr	r3, [r7, #4]
 8005d7e:	1ad2      	subs	r2, r2, r3
 8005d80:	2308      	movs	r3, #8
 8005d82:	005b      	lsls	r3, r3, #1
 8005d84:	429a      	cmp	r2, r3
 8005d86:	d91f      	bls.n	8005dc8 <pvPortMalloc+0x110>
					{
						/* This block is to be split into two.  Create a new
						block following the number of bytes requested. The void
						cast is used to prevent byte alignment warnings from the
						compiler. */
						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
 8005d88:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 8005d8a:	687b      	ldr	r3, [r7, #4]
 8005d8c:	4413      	add	r3, r2
 8005d8e:	61bb      	str	r3, [r7, #24]
						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
 8005d90:	69bb      	ldr	r3, [r7, #24]
 8005d92:	f003 0307 	and.w	r3, r3, #7
 8005d96:	2b00      	cmp	r3, #0
 8005d98:	d00a      	beq.n	8005db0 <pvPortMalloc+0xf8>
	__asm volatile
 8005d9a:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005d9e:	f383 8811 	msr	BASEPRI, r3
 8005da2:	f3bf 8f6f 	isb	sy
 8005da6:	f3bf 8f4f 	dsb	sy
 8005daa:	613b      	str	r3, [r7, #16]
}
 8005dac:	bf00      	nop
 8005dae:	e7fe      	b.n	8005dae <pvPortMalloc+0xf6>

						/* Calculate the sizes of two blocks split from the
						single block. */
						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
 8005db0:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005db2:	685a      	ldr	r2, [r3, #4]
 8005db4:	687b      	ldr	r3, [r7, #4]
 8005db6:	1ad2      	subs	r2, r2, r3
 8005db8:	69bb      	ldr	r3, [r7, #24]
 8005dba:	605a      	str	r2, [r3, #4]
						pxBlock->xBlockSize = xWantedSize;
 8005dbc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005dbe:	687a      	ldr	r2, [r7, #4]
 8005dc0:	605a      	str	r2, [r3, #4]

						/* Insert the new block into the list of free blocks. */
						prvInsertBlockIntoFreeList( pxNewBlockLink );
 8005dc2:	69b8      	ldr	r0, [r7, #24]
 8005dc4:	f000 f908 	bl	8005fd8 <prvInsertBlockIntoFreeList>
					else
					{
						mtCOVERAGE_TEST_MARKER();
					}

					xFreeBytesRemaining -= pxBlock->xBlockSize;
 8005dc8:	4b1d      	ldr	r3, [pc, #116]	; (8005e40 <pvPortMalloc+0x188>)
 8005dca:	681a      	ldr	r2, [r3, #0]
 8005dcc:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005dce:	685b      	ldr	r3, [r3, #4]
 8005dd0:	1ad3      	subs	r3, r2, r3
 8005dd2:	4a1b      	ldr	r2, [pc, #108]	; (8005e40 <pvPortMalloc+0x188>)
 8005dd4:	6013      	str	r3, [r2, #0]

					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
 8005dd6:	4b1a      	ldr	r3, [pc, #104]	; (8005e40 <pvPortMalloc+0x188>)
 8005dd8:	681a      	ldr	r2, [r3, #0]
 8005dda:	4b1b      	ldr	r3, [pc, #108]	; (8005e48 <pvPortMalloc+0x190>)
 8005ddc:	681b      	ldr	r3, [r3, #0]
 8005dde:	429a      	cmp	r2, r3
 8005de0:	d203      	bcs.n	8005dea <pvPortMalloc+0x132>
					{
						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
 8005de2:	4b17      	ldr	r3, [pc, #92]	; (8005e40 <pvPortMalloc+0x188>)
 8005de4:	681b      	ldr	r3, [r3, #0]
 8005de6:	4a18      	ldr	r2, [pc, #96]	; (8005e48 <pvPortMalloc+0x190>)
 8005de8:	6013      	str	r3, [r2, #0]
						mtCOVERAGE_TEST_MARKER();
					}

					/* The block is being returned - it is allocated and owned
					by the application and has no "next" block. */
					pxBlock->xBlockSize |= xBlockAllocatedBit;
 8005dea:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005dec:	685a      	ldr	r2, [r3, #4]
 8005dee:	4b13      	ldr	r3, [pc, #76]	; (8005e3c <pvPortMalloc+0x184>)
 8005df0:	681b      	ldr	r3, [r3, #0]
 8005df2:	431a      	orrs	r2, r3
 8005df4:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005df6:	605a      	str	r2, [r3, #4]
					pxBlock->pxNextFreeBlock = NULL;
 8005df8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8005dfa:	2200      	movs	r2, #0
 8005dfc:	601a      	str	r2, [r3, #0]
					xNumberOfSuccessfulAllocations++;
 8005dfe:	4b13      	ldr	r3, [pc, #76]	; (8005e4c <pvPortMalloc+0x194>)
 8005e00:	681b      	ldr	r3, [r3, #0]
 8005e02:	3301      	adds	r3, #1
 8005e04:	4a11      	ldr	r2, [pc, #68]	; (8005e4c <pvPortMalloc+0x194>)
 8005e06:	6013      	str	r3, [r2, #0]
			mtCOVERAGE_TEST_MARKER();
		}

		traceMALLOC( pvReturn, xWantedSize );
	}
	( void ) xTaskResumeAll();
 8005e08:	f7fe fcfe 	bl	8004808 <xTaskResumeAll>
			mtCOVERAGE_TEST_MARKER();
		}
	}
	#endif

	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
 8005e0c:	69fb      	ldr	r3, [r7, #28]
 8005e0e:	f003 0307 	and.w	r3, r3, #7
 8005e12:	2b00      	cmp	r3, #0
 8005e14:	d00a      	beq.n	8005e2c <pvPortMalloc+0x174>
	__asm volatile
 8005e16:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005e1a:	f383 8811 	msr	BASEPRI, r3
 8005e1e:	f3bf 8f6f 	isb	sy
 8005e22:	f3bf 8f4f 	dsb	sy
 8005e26:	60fb      	str	r3, [r7, #12]
}
 8005e28:	bf00      	nop
 8005e2a:	e7fe      	b.n	8005e2a <pvPortMalloc+0x172>
	return pvReturn;
 8005e2c:	69fb      	ldr	r3, [r7, #28]
}
 8005e2e:	4618      	mov	r0, r3
 8005e30:	3728      	adds	r7, #40	; 0x28
 8005e32:	46bd      	mov	sp, r7
 8005e34:	bd80      	pop	{r7, pc}
 8005e36:	bf00      	nop
 8005e38:	20004b4c 	.word	0x20004b4c
 8005e3c:	20004b60 	.word	0x20004b60
 8005e40:	20004b50 	.word	0x20004b50
 8005e44:	20004b44 	.word	0x20004b44
 8005e48:	20004b54 	.word	0x20004b54
 8005e4c:	20004b58 	.word	0x20004b58

08005e50 <vPortFree>:
/*-----------------------------------------------------------*/

void vPortFree( void *pv )
{
 8005e50:	b580      	push	{r7, lr}
 8005e52:	b086      	sub	sp, #24
 8005e54:	af00      	add	r7, sp, #0
 8005e56:	6078      	str	r0, [r7, #4]
uint8_t *puc = ( uint8_t * ) pv;
 8005e58:	687b      	ldr	r3, [r7, #4]
 8005e5a:	617b      	str	r3, [r7, #20]
BlockLink_t *pxLink;

	if( pv != NULL )
 8005e5c:	687b      	ldr	r3, [r7, #4]
 8005e5e:	2b00      	cmp	r3, #0
 8005e60:	d04d      	beq.n	8005efe <vPortFree+0xae>
	{
		/* The memory being freed will have an BlockLink_t structure immediately
		before it. */
		puc -= xHeapStructSize;
 8005e62:	2308      	movs	r3, #8
 8005e64:	425b      	negs	r3, r3
 8005e66:	697a      	ldr	r2, [r7, #20]
 8005e68:	4413      	add	r3, r2
 8005e6a:	617b      	str	r3, [r7, #20]

		/* This casting is to keep the compiler from issuing warnings. */
		pxLink = ( void * ) puc;
 8005e6c:	697b      	ldr	r3, [r7, #20]
 8005e6e:	613b      	str	r3, [r7, #16]

		/* Check the block is actually allocated. */
		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
 8005e70:	693b      	ldr	r3, [r7, #16]
 8005e72:	685a      	ldr	r2, [r3, #4]
 8005e74:	4b24      	ldr	r3, [pc, #144]	; (8005f08 <vPortFree+0xb8>)
 8005e76:	681b      	ldr	r3, [r3, #0]
 8005e78:	4013      	ands	r3, r2
 8005e7a:	2b00      	cmp	r3, #0
 8005e7c:	d10a      	bne.n	8005e94 <vPortFree+0x44>
	__asm volatile
 8005e7e:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005e82:	f383 8811 	msr	BASEPRI, r3
 8005e86:	f3bf 8f6f 	isb	sy
 8005e8a:	f3bf 8f4f 	dsb	sy
 8005e8e:	60fb      	str	r3, [r7, #12]
}
 8005e90:	bf00      	nop
 8005e92:	e7fe      	b.n	8005e92 <vPortFree+0x42>
		configASSERT( pxLink->pxNextFreeBlock == NULL );
 8005e94:	693b      	ldr	r3, [r7, #16]
 8005e96:	681b      	ldr	r3, [r3, #0]
 8005e98:	2b00      	cmp	r3, #0
 8005e9a:	d00a      	beq.n	8005eb2 <vPortFree+0x62>
	__asm volatile
 8005e9c:	f04f 0350 	mov.w	r3, #80	; 0x50
 8005ea0:	f383 8811 	msr	BASEPRI, r3
 8005ea4:	f3bf 8f6f 	isb	sy
 8005ea8:	f3bf 8f4f 	dsb	sy
 8005eac:	60bb      	str	r3, [r7, #8]
}
 8005eae:	bf00      	nop
 8005eb0:	e7fe      	b.n	8005eb0 <vPortFree+0x60>

		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
 8005eb2:	693b      	ldr	r3, [r7, #16]
 8005eb4:	685a      	ldr	r2, [r3, #4]
 8005eb6:	4b14      	ldr	r3, [pc, #80]	; (8005f08 <vPortFree+0xb8>)
 8005eb8:	681b      	ldr	r3, [r3, #0]
 8005eba:	4013      	ands	r3, r2
 8005ebc:	2b00      	cmp	r3, #0
 8005ebe:	d01e      	beq.n	8005efe <vPortFree+0xae>
		{
			if( pxLink->pxNextFreeBlock == NULL )
 8005ec0:	693b      	ldr	r3, [r7, #16]
 8005ec2:	681b      	ldr	r3, [r3, #0]
 8005ec4:	2b00      	cmp	r3, #0
 8005ec6:	d11a      	bne.n	8005efe <vPortFree+0xae>
			{
				/* The block is being returned to the heap - it is no longer
				allocated. */
				pxLink->xBlockSize &= ~xBlockAllocatedBit;
 8005ec8:	693b      	ldr	r3, [r7, #16]
 8005eca:	685a      	ldr	r2, [r3, #4]
 8005ecc:	4b0e      	ldr	r3, [pc, #56]	; (8005f08 <vPortFree+0xb8>)
 8005ece:	681b      	ldr	r3, [r3, #0]
 8005ed0:	43db      	mvns	r3, r3
 8005ed2:	401a      	ands	r2, r3
 8005ed4:	693b      	ldr	r3, [r7, #16]
 8005ed6:	605a      	str	r2, [r3, #4]

				vTaskSuspendAll();
 8005ed8:	f7fe fc88 	bl	80047ec <vTaskSuspendAll>
				{
					/* Add this block to the list of free blocks. */
					xFreeBytesRemaining += pxLink->xBlockSize;
 8005edc:	693b      	ldr	r3, [r7, #16]
 8005ede:	685a      	ldr	r2, [r3, #4]
 8005ee0:	4b0a      	ldr	r3, [pc, #40]	; (8005f0c <vPortFree+0xbc>)
 8005ee2:	681b      	ldr	r3, [r3, #0]
 8005ee4:	4413      	add	r3, r2
 8005ee6:	4a09      	ldr	r2, [pc, #36]	; (8005f0c <vPortFree+0xbc>)
 8005ee8:	6013      	str	r3, [r2, #0]
					traceFREE( pv, pxLink->xBlockSize );
					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
 8005eea:	6938      	ldr	r0, [r7, #16]
 8005eec:	f000 f874 	bl	8005fd8 <prvInsertBlockIntoFreeList>
					xNumberOfSuccessfulFrees++;
 8005ef0:	4b07      	ldr	r3, [pc, #28]	; (8005f10 <vPortFree+0xc0>)
 8005ef2:	681b      	ldr	r3, [r3, #0]
 8005ef4:	3301      	adds	r3, #1
 8005ef6:	4a06      	ldr	r2, [pc, #24]	; (8005f10 <vPortFree+0xc0>)
 8005ef8:	6013      	str	r3, [r2, #0]
				}
				( void ) xTaskResumeAll();
 8005efa:	f7fe fc85 	bl	8004808 <xTaskResumeAll>
		else
		{
			mtCOVERAGE_TEST_MARKER();
		}
	}
}
 8005efe:	bf00      	nop
 8005f00:	3718      	adds	r7, #24
 8005f02:	46bd      	mov	sp, r7
 8005f04:	bd80      	pop	{r7, pc}
 8005f06:	bf00      	nop
 8005f08:	20004b60 	.word	0x20004b60
 8005f0c:	20004b50 	.word	0x20004b50
 8005f10:	20004b5c 	.word	0x20004b5c

08005f14 <prvHeapInit>:
	/* This just exists to keep the linker quiet. */
}
/*-----------------------------------------------------------*/

static void prvHeapInit( void )
{
 8005f14:	b480      	push	{r7}
 8005f16:	b085      	sub	sp, #20
 8005f18:	af00      	add	r7, sp, #0
BlockLink_t *pxFirstFreeBlock;
uint8_t *pucAlignedHeap;
size_t uxAddress;
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
 8005f1a:	f44f 5370 	mov.w	r3, #15360	; 0x3c00
 8005f1e:	60bb      	str	r3, [r7, #8]

	/* Ensure the heap starts on a correctly aligned boundary. */
	uxAddress = ( size_t ) ucHeap;
 8005f20:	4b27      	ldr	r3, [pc, #156]	; (8005fc0 <prvHeapInit+0xac>)
 8005f22:	60fb      	str	r3, [r7, #12]

	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
 8005f24:	68fb      	ldr	r3, [r7, #12]
 8005f26:	f003 0307 	and.w	r3, r3, #7
 8005f2a:	2b00      	cmp	r3, #0
 8005f2c:	d00c      	beq.n	8005f48 <prvHeapInit+0x34>
	{
		uxAddress += ( portBYTE_ALIGNMENT - 1 );
 8005f2e:	68fb      	ldr	r3, [r7, #12]
 8005f30:	3307      	adds	r3, #7
 8005f32:	60fb      	str	r3, [r7, #12]
		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8005f34:	68fb      	ldr	r3, [r7, #12]
 8005f36:	f023 0307 	bic.w	r3, r3, #7
 8005f3a:	60fb      	str	r3, [r7, #12]
		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
 8005f3c:	68ba      	ldr	r2, [r7, #8]
 8005f3e:	68fb      	ldr	r3, [r7, #12]
 8005f40:	1ad3      	subs	r3, r2, r3
 8005f42:	4a1f      	ldr	r2, [pc, #124]	; (8005fc0 <prvHeapInit+0xac>)
 8005f44:	4413      	add	r3, r2
 8005f46:	60bb      	str	r3, [r7, #8]
	}

	pucAlignedHeap = ( uint8_t * ) uxAddress;
 8005f48:	68fb      	ldr	r3, [r7, #12]
 8005f4a:	607b      	str	r3, [r7, #4]

	/* xStart is used to hold a pointer to the first item in the list of free
	blocks.  The void cast is used to prevent compiler warnings. */
	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
 8005f4c:	4a1d      	ldr	r2, [pc, #116]	; (8005fc4 <prvHeapInit+0xb0>)
 8005f4e:	687b      	ldr	r3, [r7, #4]
 8005f50:	6013      	str	r3, [r2, #0]
	xStart.xBlockSize = ( size_t ) 0;
 8005f52:	4b1c      	ldr	r3, [pc, #112]	; (8005fc4 <prvHeapInit+0xb0>)
 8005f54:	2200      	movs	r2, #0
 8005f56:	605a      	str	r2, [r3, #4]

	/* pxEnd is used to mark the end of the list of free blocks and is inserted
	at the end of the heap space. */
	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
 8005f58:	687b      	ldr	r3, [r7, #4]
 8005f5a:	68ba      	ldr	r2, [r7, #8]
 8005f5c:	4413      	add	r3, r2
 8005f5e:	60fb      	str	r3, [r7, #12]
	uxAddress -= xHeapStructSize;
 8005f60:	2208      	movs	r2, #8
 8005f62:	68fb      	ldr	r3, [r7, #12]
 8005f64:	1a9b      	subs	r3, r3, r2
 8005f66:	60fb      	str	r3, [r7, #12]
	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
 8005f68:	68fb      	ldr	r3, [r7, #12]
 8005f6a:	f023 0307 	bic.w	r3, r3, #7
 8005f6e:	60fb      	str	r3, [r7, #12]
	pxEnd = ( void * ) uxAddress;
 8005f70:	68fb      	ldr	r3, [r7, #12]
 8005f72:	4a15      	ldr	r2, [pc, #84]	; (8005fc8 <prvHeapInit+0xb4>)
 8005f74:	6013      	str	r3, [r2, #0]
	pxEnd->xBlockSize = 0;
 8005f76:	4b14      	ldr	r3, [pc, #80]	; (8005fc8 <prvHeapInit+0xb4>)
 8005f78:	681b      	ldr	r3, [r3, #0]
 8005f7a:	2200      	movs	r2, #0
 8005f7c:	605a      	str	r2, [r3, #4]
	pxEnd->pxNextFreeBlock = NULL;
 8005f7e:	4b12      	ldr	r3, [pc, #72]	; (8005fc8 <prvHeapInit+0xb4>)
 8005f80:	681b      	ldr	r3, [r3, #0]
 8005f82:	2200      	movs	r2, #0
 8005f84:	601a      	str	r2, [r3, #0]

	/* To start with there is a single free block that is sized to take up the
	entire heap space, minus the space taken by pxEnd. */
	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
 8005f86:	687b      	ldr	r3, [r7, #4]
 8005f88:	603b      	str	r3, [r7, #0]
	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
 8005f8a:	683b      	ldr	r3, [r7, #0]
 8005f8c:	68fa      	ldr	r2, [r7, #12]
 8005f8e:	1ad2      	subs	r2, r2, r3
 8005f90:	683b      	ldr	r3, [r7, #0]
 8005f92:	605a      	str	r2, [r3, #4]
	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
 8005f94:	4b0c      	ldr	r3, [pc, #48]	; (8005fc8 <prvHeapInit+0xb4>)
 8005f96:	681a      	ldr	r2, [r3, #0]
 8005f98:	683b      	ldr	r3, [r7, #0]
 8005f9a:	601a      	str	r2, [r3, #0]

	/* Only one block exists - and it covers the entire usable heap space. */
	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 8005f9c:	683b      	ldr	r3, [r7, #0]
 8005f9e:	685b      	ldr	r3, [r3, #4]
 8005fa0:	4a0a      	ldr	r2, [pc, #40]	; (8005fcc <prvHeapInit+0xb8>)
 8005fa2:	6013      	str	r3, [r2, #0]
	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
 8005fa4:	683b      	ldr	r3, [r7, #0]
 8005fa6:	685b      	ldr	r3, [r3, #4]
 8005fa8:	4a09      	ldr	r2, [pc, #36]	; (8005fd0 <prvHeapInit+0xbc>)
 8005faa:	6013      	str	r3, [r2, #0]

	/* Work out the position of the top bit in a size_t variable. */
	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
 8005fac:	4b09      	ldr	r3, [pc, #36]	; (8005fd4 <prvHeapInit+0xc0>)
 8005fae:	f04f 4200 	mov.w	r2, #2147483648	; 0x80000000
 8005fb2:	601a      	str	r2, [r3, #0]
}
 8005fb4:	bf00      	nop
 8005fb6:	3714      	adds	r7, #20
 8005fb8:	46bd      	mov	sp, r7
 8005fba:	f85d 7b04 	ldr.w	r7, [sp], #4
 8005fbe:	4770      	bx	lr
 8005fc0:	20000f44 	.word	0x20000f44
 8005fc4:	20004b44 	.word	0x20004b44
 8005fc8:	20004b4c 	.word	0x20004b4c
 8005fcc:	20004b54 	.word	0x20004b54
 8005fd0:	20004b50 	.word	0x20004b50
 8005fd4:	20004b60 	.word	0x20004b60

08005fd8 <prvInsertBlockIntoFreeList>:
/*-----------------------------------------------------------*/

static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
{
 8005fd8:	b480      	push	{r7}
 8005fda:	b085      	sub	sp, #20
 8005fdc:	af00      	add	r7, sp, #0
 8005fde:	6078      	str	r0, [r7, #4]
BlockLink_t *pxIterator;
uint8_t *puc;

	/* Iterate through the list until a block is found that has a higher address
	than the block being inserted. */
	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
 8005fe0:	4b28      	ldr	r3, [pc, #160]	; (8006084 <prvInsertBlockIntoFreeList+0xac>)
 8005fe2:	60fb      	str	r3, [r7, #12]
 8005fe4:	e002      	b.n	8005fec <prvInsertBlockIntoFreeList+0x14>
 8005fe6:	68fb      	ldr	r3, [r7, #12]
 8005fe8:	681b      	ldr	r3, [r3, #0]
 8005fea:	60fb      	str	r3, [r7, #12]
 8005fec:	68fb      	ldr	r3, [r7, #12]
 8005fee:	681b      	ldr	r3, [r3, #0]
 8005ff0:	687a      	ldr	r2, [r7, #4]
 8005ff2:	429a      	cmp	r2, r3
 8005ff4:	d8f7      	bhi.n	8005fe6 <prvInsertBlockIntoFreeList+0xe>
		/* Nothing to do here, just iterate to the right position. */
	}

	/* Do the block being inserted, and the block it is being inserted after
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxIterator;
 8005ff6:	68fb      	ldr	r3, [r7, #12]
 8005ff8:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
 8005ffa:	68fb      	ldr	r3, [r7, #12]
 8005ffc:	685b      	ldr	r3, [r3, #4]
 8005ffe:	68ba      	ldr	r2, [r7, #8]
 8006000:	4413      	add	r3, r2
 8006002:	687a      	ldr	r2, [r7, #4]
 8006004:	429a      	cmp	r2, r3
 8006006:	d108      	bne.n	800601a <prvInsertBlockIntoFreeList+0x42>
	{
		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
 8006008:	68fb      	ldr	r3, [r7, #12]
 800600a:	685a      	ldr	r2, [r3, #4]
 800600c:	687b      	ldr	r3, [r7, #4]
 800600e:	685b      	ldr	r3, [r3, #4]
 8006010:	441a      	add	r2, r3
 8006012:	68fb      	ldr	r3, [r7, #12]
 8006014:	605a      	str	r2, [r3, #4]
		pxBlockToInsert = pxIterator;
 8006016:	68fb      	ldr	r3, [r7, #12]
 8006018:	607b      	str	r3, [r7, #4]
		mtCOVERAGE_TEST_MARKER();
	}

	/* Do the block being inserted, and the block it is being inserted before
	make a contiguous block of memory? */
	puc = ( uint8_t * ) pxBlockToInsert;
 800601a:	687b      	ldr	r3, [r7, #4]
 800601c:	60bb      	str	r3, [r7, #8]
	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
 800601e:	687b      	ldr	r3, [r7, #4]
 8006020:	685b      	ldr	r3, [r3, #4]
 8006022:	68ba      	ldr	r2, [r7, #8]
 8006024:	441a      	add	r2, r3
 8006026:	68fb      	ldr	r3, [r7, #12]
 8006028:	681b      	ldr	r3, [r3, #0]
 800602a:	429a      	cmp	r2, r3
 800602c:	d118      	bne.n	8006060 <prvInsertBlockIntoFreeList+0x88>
	{
		if( pxIterator->pxNextFreeBlock != pxEnd )
 800602e:	68fb      	ldr	r3, [r7, #12]
 8006030:	681a      	ldr	r2, [r3, #0]
 8006032:	4b15      	ldr	r3, [pc, #84]	; (8006088 <prvInsertBlockIntoFreeList+0xb0>)
 8006034:	681b      	ldr	r3, [r3, #0]
 8006036:	429a      	cmp	r2, r3
 8006038:	d00d      	beq.n	8006056 <prvInsertBlockIntoFreeList+0x7e>
		{
			/* Form one big block from the two blocks. */
			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
 800603a:	687b      	ldr	r3, [r7, #4]
 800603c:	685a      	ldr	r2, [r3, #4]
 800603e:	68fb      	ldr	r3, [r7, #12]
 8006040:	681b      	ldr	r3, [r3, #0]
 8006042:	685b      	ldr	r3, [r3, #4]
 8006044:	441a      	add	r2, r3
 8006046:	687b      	ldr	r3, [r7, #4]
 8006048:	605a      	str	r2, [r3, #4]
			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
 800604a:	68fb      	ldr	r3, [r7, #12]
 800604c:	681b      	ldr	r3, [r3, #0]
 800604e:	681a      	ldr	r2, [r3, #0]
 8006050:	687b      	ldr	r3, [r7, #4]
 8006052:	601a      	str	r2, [r3, #0]
 8006054:	e008      	b.n	8006068 <prvInsertBlockIntoFreeList+0x90>
		}
		else
		{
			pxBlockToInsert->pxNextFreeBlock = pxEnd;
 8006056:	4b0c      	ldr	r3, [pc, #48]	; (8006088 <prvInsertBlockIntoFreeList+0xb0>)
 8006058:	681a      	ldr	r2, [r3, #0]
 800605a:	687b      	ldr	r3, [r7, #4]
 800605c:	601a      	str	r2, [r3, #0]
 800605e:	e003      	b.n	8006068 <prvInsertBlockIntoFreeList+0x90>
		}
	}
	else
	{
		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
 8006060:	68fb      	ldr	r3, [r7, #12]
 8006062:	681a      	ldr	r2, [r3, #0]
 8006064:	687b      	ldr	r3, [r7, #4]
 8006066:	601a      	str	r2, [r3, #0]

	/* If the block being inserted plugged a gab, so was merged with the block
	before and the block after, then it's pxNextFreeBlock pointer will have
	already been set, and should not be set here as that would make it point
	to itself. */
	if( pxIterator != pxBlockToInsert )
 8006068:	68fa      	ldr	r2, [r7, #12]
 800606a:	687b      	ldr	r3, [r7, #4]
 800606c:	429a      	cmp	r2, r3
 800606e:	d002      	beq.n	8006076 <prvInsertBlockIntoFreeList+0x9e>
	{
		pxIterator->pxNextFreeBlock = pxBlockToInsert;
 8006070:	68fb      	ldr	r3, [r7, #12]
 8006072:	687a      	ldr	r2, [r7, #4]
 8006074:	601a      	str	r2, [r3, #0]
	}
	else
	{
		mtCOVERAGE_TEST_MARKER();
	}
}
 8006076:	bf00      	nop
 8006078:	3714      	adds	r7, #20
 800607a:	46bd      	mov	sp, r7
 800607c:	f85d 7b04 	ldr.w	r7, [sp], #4
 8006080:	4770      	bx	lr
 8006082:	bf00      	nop
 8006084:	20004b44 	.word	0x20004b44
 8006088:	20004b4c 	.word	0x20004b4c

0800608c <memset>:
 800608c:	4402      	add	r2, r0
 800608e:	4603      	mov	r3, r0
 8006090:	4293      	cmp	r3, r2
 8006092:	d100      	bne.n	8006096 <memset+0xa>
 8006094:	4770      	bx	lr
 8006096:	f803 1b01 	strb.w	r1, [r3], #1
 800609a:	e7f9      	b.n	8006090 <memset+0x4>

0800609c <_reclaim_reent>:
 800609c:	4b29      	ldr	r3, [pc, #164]	; (8006144 <_reclaim_reent+0xa8>)
 800609e:	681b      	ldr	r3, [r3, #0]
 80060a0:	4283      	cmp	r3, r0
 80060a2:	b570      	push	{r4, r5, r6, lr}
 80060a4:	4604      	mov	r4, r0
 80060a6:	d04b      	beq.n	8006140 <_reclaim_reent+0xa4>
 80060a8:	69c3      	ldr	r3, [r0, #28]
 80060aa:	b143      	cbz	r3, 80060be <_reclaim_reent+0x22>
 80060ac:	68db      	ldr	r3, [r3, #12]
 80060ae:	2b00      	cmp	r3, #0
 80060b0:	d144      	bne.n	800613c <_reclaim_reent+0xa0>
 80060b2:	69e3      	ldr	r3, [r4, #28]
 80060b4:	6819      	ldr	r1, [r3, #0]
 80060b6:	b111      	cbz	r1, 80060be <_reclaim_reent+0x22>
 80060b8:	4620      	mov	r0, r4
 80060ba:	f000 f879 	bl	80061b0 <_free_r>
 80060be:	6961      	ldr	r1, [r4, #20]
 80060c0:	b111      	cbz	r1, 80060c8 <_reclaim_reent+0x2c>
 80060c2:	4620      	mov	r0, r4
 80060c4:	f000 f874 	bl	80061b0 <_free_r>
 80060c8:	69e1      	ldr	r1, [r4, #28]
 80060ca:	b111      	cbz	r1, 80060d2 <_reclaim_reent+0x36>
 80060cc:	4620      	mov	r0, r4
 80060ce:	f000 f86f 	bl	80061b0 <_free_r>
 80060d2:	6b21      	ldr	r1, [r4, #48]	; 0x30
 80060d4:	b111      	cbz	r1, 80060dc <_reclaim_reent+0x40>
 80060d6:	4620      	mov	r0, r4
 80060d8:	f000 f86a 	bl	80061b0 <_free_r>
 80060dc:	6b61      	ldr	r1, [r4, #52]	; 0x34
 80060de:	b111      	cbz	r1, 80060e6 <_reclaim_reent+0x4a>
 80060e0:	4620      	mov	r0, r4
 80060e2:	f000 f865 	bl	80061b0 <_free_r>
 80060e6:	6ba1      	ldr	r1, [r4, #56]	; 0x38
 80060e8:	b111      	cbz	r1, 80060f0 <_reclaim_reent+0x54>
 80060ea:	4620      	mov	r0, r4
 80060ec:	f000 f860 	bl	80061b0 <_free_r>
 80060f0:	6ca1      	ldr	r1, [r4, #72]	; 0x48
 80060f2:	b111      	cbz	r1, 80060fa <_reclaim_reent+0x5e>
 80060f4:	4620      	mov	r0, r4
 80060f6:	f000 f85b 	bl	80061b0 <_free_r>
 80060fa:	6c61      	ldr	r1, [r4, #68]	; 0x44
 80060fc:	b111      	cbz	r1, 8006104 <_reclaim_reent+0x68>
 80060fe:	4620      	mov	r0, r4
 8006100:	f000 f856 	bl	80061b0 <_free_r>
 8006104:	6ae1      	ldr	r1, [r4, #44]	; 0x2c
 8006106:	b111      	cbz	r1, 800610e <_reclaim_reent+0x72>
 8006108:	4620      	mov	r0, r4
 800610a:	f000 f851 	bl	80061b0 <_free_r>
 800610e:	6a23      	ldr	r3, [r4, #32]
 8006110:	b1b3      	cbz	r3, 8006140 <_reclaim_reent+0xa4>
 8006112:	4620      	mov	r0, r4
 8006114:	e8bd 4070 	ldmia.w	sp!, {r4, r5, r6, lr}
 8006118:	4718      	bx	r3
 800611a:	5949      	ldr	r1, [r1, r5]
 800611c:	b941      	cbnz	r1, 8006130 <_reclaim_reent+0x94>
 800611e:	3504      	adds	r5, #4
 8006120:	69e3      	ldr	r3, [r4, #28]
 8006122:	2d80      	cmp	r5, #128	; 0x80
 8006124:	68d9      	ldr	r1, [r3, #12]
 8006126:	d1f8      	bne.n	800611a <_reclaim_reent+0x7e>
 8006128:	4620      	mov	r0, r4
 800612a:	f000 f841 	bl	80061b0 <_free_r>
 800612e:	e7c0      	b.n	80060b2 <_reclaim_reent+0x16>
 8006130:	680e      	ldr	r6, [r1, #0]
 8006132:	4620      	mov	r0, r4
 8006134:	f000 f83c 	bl	80061b0 <_free_r>
 8006138:	4631      	mov	r1, r6
 800613a:	e7ef      	b.n	800611c <_reclaim_reent+0x80>
 800613c:	2500      	movs	r5, #0
 800613e:	e7ef      	b.n	8006120 <_reclaim_reent+0x84>
 8006140:	bd70      	pop	{r4, r5, r6, pc}
 8006142:	bf00      	nop
 8006144:	2000005c 	.word	0x2000005c

08006148 <__libc_init_array>:
 8006148:	b570      	push	{r4, r5, r6, lr}
 800614a:	4d0d      	ldr	r5, [pc, #52]	; (8006180 <__libc_init_array+0x38>)
 800614c:	4c0d      	ldr	r4, [pc, #52]	; (8006184 <__libc_init_array+0x3c>)
 800614e:	1b64      	subs	r4, r4, r5
 8006150:	10a4      	asrs	r4, r4, #2
 8006152:	2600      	movs	r6, #0
 8006154:	42a6      	cmp	r6, r4
 8006156:	d109      	bne.n	800616c <__libc_init_array+0x24>
 8006158:	4d0b      	ldr	r5, [pc, #44]	; (8006188 <__libc_init_array+0x40>)
 800615a:	4c0c      	ldr	r4, [pc, #48]	; (800618c <__libc_init_array+0x44>)
 800615c:	f000 f880 	bl	8006260 <_init>
 8006160:	1b64      	subs	r4, r4, r5
 8006162:	10a4      	asrs	r4, r4, #2
 8006164:	2600      	movs	r6, #0
 8006166:	42a6      	cmp	r6, r4
 8006168:	d105      	bne.n	8006176 <__libc_init_array+0x2e>
 800616a:	bd70      	pop	{r4, r5, r6, pc}
 800616c:	f855 3b04 	ldr.w	r3, [r5], #4
 8006170:	4798      	blx	r3
 8006172:	3601      	adds	r6, #1
 8006174:	e7ee      	b.n	8006154 <__libc_init_array+0xc>
 8006176:	f855 3b04 	ldr.w	r3, [r5], #4
 800617a:	4798      	blx	r3
 800617c:	3601      	adds	r6, #1
 800617e:	e7f2      	b.n	8006166 <__libc_init_array+0x1e>
 8006180:	08006374 	.word	0x08006374
 8006184:	08006374 	.word	0x08006374
 8006188:	08006374 	.word	0x08006374
 800618c:	08006378 	.word	0x08006378

08006190 <__retarget_lock_acquire_recursive>:
 8006190:	4770      	bx	lr

08006192 <__retarget_lock_release_recursive>:
 8006192:	4770      	bx	lr

08006194 <memcpy>:
 8006194:	440a      	add	r2, r1
 8006196:	4291      	cmp	r1, r2
 8006198:	f100 33ff 	add.w	r3, r0, #4294967295
 800619c:	d100      	bne.n	80061a0 <memcpy+0xc>
 800619e:	4770      	bx	lr
 80061a0:	b510      	push	{r4, lr}
 80061a2:	f811 4b01 	ldrb.w	r4, [r1], #1
 80061a6:	f803 4f01 	strb.w	r4, [r3, #1]!
 80061aa:	4291      	cmp	r1, r2
 80061ac:	d1f9      	bne.n	80061a2 <memcpy+0xe>
 80061ae:	bd10      	pop	{r4, pc}

080061b0 <_free_r>:
 80061b0:	b537      	push	{r0, r1, r2, r4, r5, lr}
 80061b2:	2900      	cmp	r1, #0
 80061b4:	d044      	beq.n	8006240 <_free_r+0x90>
 80061b6:	f851 3c04 	ldr.w	r3, [r1, #-4]
 80061ba:	9001      	str	r0, [sp, #4]
 80061bc:	2b00      	cmp	r3, #0
 80061be:	f1a1 0404 	sub.w	r4, r1, #4
 80061c2:	bfb8      	it	lt
 80061c4:	18e4      	addlt	r4, r4, r3
 80061c6:	f000 f83f 	bl	8006248 <__malloc_lock>
 80061ca:	4a1e      	ldr	r2, [pc, #120]	; (8006244 <_free_r+0x94>)
 80061cc:	9801      	ldr	r0, [sp, #4]
 80061ce:	6813      	ldr	r3, [r2, #0]
 80061d0:	b933      	cbnz	r3, 80061e0 <_free_r+0x30>
 80061d2:	6063      	str	r3, [r4, #4]
 80061d4:	6014      	str	r4, [r2, #0]
 80061d6:	b003      	add	sp, #12
 80061d8:	e8bd 4030 	ldmia.w	sp!, {r4, r5, lr}
 80061dc:	f000 b83a 	b.w	8006254 <__malloc_unlock>
 80061e0:	42a3      	cmp	r3, r4
 80061e2:	d908      	bls.n	80061f6 <_free_r+0x46>
 80061e4:	6825      	ldr	r5, [r4, #0]
 80061e6:	1961      	adds	r1, r4, r5
 80061e8:	428b      	cmp	r3, r1
 80061ea:	bf01      	itttt	eq
 80061ec:	6819      	ldreq	r1, [r3, #0]
 80061ee:	685b      	ldreq	r3, [r3, #4]
 80061f0:	1949      	addeq	r1, r1, r5
 80061f2:	6021      	streq	r1, [r4, #0]
 80061f4:	e7ed      	b.n	80061d2 <_free_r+0x22>
 80061f6:	461a      	mov	r2, r3
 80061f8:	685b      	ldr	r3, [r3, #4]
 80061fa:	b10b      	cbz	r3, 8006200 <_free_r+0x50>
 80061fc:	42a3      	cmp	r3, r4
 80061fe:	d9fa      	bls.n	80061f6 <_free_r+0x46>
 8006200:	6811      	ldr	r1, [r2, #0]
 8006202:	1855      	adds	r5, r2, r1
 8006204:	42a5      	cmp	r5, r4
 8006206:	d10b      	bne.n	8006220 <_free_r+0x70>
 8006208:	6824      	ldr	r4, [r4, #0]
 800620a:	4421      	add	r1, r4
 800620c:	1854      	adds	r4, r2, r1
 800620e:	42a3      	cmp	r3, r4
 8006210:	6011      	str	r1, [r2, #0]
 8006212:	d1e0      	bne.n	80061d6 <_free_r+0x26>
 8006214:	681c      	ldr	r4, [r3, #0]
 8006216:	685b      	ldr	r3, [r3, #4]
 8006218:	6053      	str	r3, [r2, #4]
 800621a:	440c      	add	r4, r1
 800621c:	6014      	str	r4, [r2, #0]
 800621e:	e7da      	b.n	80061d6 <_free_r+0x26>
 8006220:	d902      	bls.n	8006228 <_free_r+0x78>
 8006222:	230c      	movs	r3, #12
 8006224:	6003      	str	r3, [r0, #0]
 8006226:	e7d6      	b.n	80061d6 <_free_r+0x26>
 8006228:	6825      	ldr	r5, [r4, #0]
 800622a:	1961      	adds	r1, r4, r5
 800622c:	428b      	cmp	r3, r1
 800622e:	bf04      	itt	eq
 8006230:	6819      	ldreq	r1, [r3, #0]
 8006232:	685b      	ldreq	r3, [r3, #4]
 8006234:	6063      	str	r3, [r4, #4]
 8006236:	bf04      	itt	eq
 8006238:	1949      	addeq	r1, r1, r5
 800623a:	6021      	streq	r1, [r4, #0]
 800623c:	6054      	str	r4, [r2, #4]
 800623e:	e7ca      	b.n	80061d6 <_free_r+0x26>
 8006240:	b003      	add	sp, #12
 8006242:	bd30      	pop	{r4, r5, pc}
 8006244:	20004ca0 	.word	0x20004ca0

08006248 <__malloc_lock>:
 8006248:	4801      	ldr	r0, [pc, #4]	; (8006250 <__malloc_lock+0x8>)
 800624a:	f7ff bfa1 	b.w	8006190 <__retarget_lock_acquire_recursive>
 800624e:	bf00      	nop
 8006250:	20004c9c 	.word	0x20004c9c

08006254 <__malloc_unlock>:
 8006254:	4801      	ldr	r0, [pc, #4]	; (800625c <__malloc_unlock+0x8>)
 8006256:	f7ff bf9c 	b.w	8006192 <__retarget_lock_release_recursive>
 800625a:	bf00      	nop
 800625c:	20004c9c 	.word	0x20004c9c

08006260 <_init>:
 8006260:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8006262:	bf00      	nop
 8006264:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8006266:	bc08      	pop	{r3}
 8006268:	469e      	mov	lr, r3
 800626a:	4770      	bx	lr

0800626c <_fini>:
 800626c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800626e:	bf00      	nop
 8006270:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8006272:	bc08      	pop	{r3}
 8006274:	469e      	mov	lr, r3
 8006276:	4770      	bx	lr
